From 9ffee1c4be7c1981e47e520172638a4b00881880 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Wed, 11 May 2016 15:07:32 +0530 Subject: clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM The branch clocks MMSS_MMAGIC_AXI_CLK and MMAGIC_BIMC_AXI_CLK are controlled by RPM when the APPs processor enable or disable the RPM_MMAXI_CLK. During the boot sequence, someone can enable the RPM_MMAXI_CLK, resulting in register status bits showing that these clocks are enabled, our clock driver may look at the enabled status of these clocks and try to disable them since it thinks they are unused. Don't make the clock driver touch these clocks. Signed-off-by: Archit Taneja Signed-off-by: Stephen Boyd --- drivers/clk/qcom/mmcc-msm8996.c | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 6df7ff36b416..847dd9dadeca 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -1279,21 +1279,6 @@ static struct clk_branch mmss_misc_cxo_clk = { }, }; -static struct clk_branch mmss_mmagic_axi_clk = { - .halt_reg = 0x506c, - .clkr = { - .enable_reg = 0x506c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mmagic_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch mmss_mmagic_maxi_clk = { .halt_reg = 0x5074, .clkr = { @@ -1579,21 +1564,6 @@ static struct clk_branch smmu_video_axi_clk = { }, }; -static struct clk_branch mmagic_bimc_axi_clk = { - .halt_reg = 0x5294, - .clkr = { - .enable_reg = 0x5294, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmagic_bimc_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { .halt_reg = 0x5298, .clkr = { @@ -3121,7 +3091,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, - [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr, [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, @@ -3141,7 +3110,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, - [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr, [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, -- cgit v1.2.3