From 1f737ffa13efd3da2c703d45894ea234e9290c89 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 28 Jul 2017 18:32:28 +0200 Subject: clk: meson: mpll: fix mpll0 fractional part ignored mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/clk/meson/clkc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/meson/clkc.h') diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index d6feafe8bd6c..1629da9b4141 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -118,6 +118,7 @@ struct meson_clk_mpll { struct parm sdm_en; struct parm n2; struct parm en; + struct parm ssen; spinlock_t *lock; }; -- cgit v1.2.3