From 55b8fd4f428501b0f35d62b8313311fd9863c188 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Tue, 10 Apr 2012 09:02:35 +0530 Subject: SPEAr: clk: Add VCO-PLL Synthesizer clock All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar Reviewed-by: Mike Turquette --- drivers/clk/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 24aa7144811b..0f5e03d1ef5c 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -2,3 +2,6 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ clk-mux.o clk-divider.o clk-fixed-factor.o + +# SoCs specific +obj-$(CONFIG_PLAT_SPEAR) += spear/ -- cgit v1.2.3