From 9169d3a88072b20f42e68a946e916bd7dfbc7f2c Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 10 Oct 2012 23:14:01 +0200 Subject: drm/i915: disable wc gtt pte mappings on gen2 It doesn't work since the gtt pte range sits in the middle of the mmio bar. We didn't notice that since both my and Chris' gen2 machines don't support PAT and hence all wc io mapping request will automatically be demoted to uc. This regression has been introduce in commit edef7e685da05c13cce50c0126189c80fe2c8f71 Author: Chris Wilson Date: Fri Sep 14 11:57:47 2012 +0100 agp/intel: Use a write-combining map for updating PTEs Reported-by: Egbert Eich Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834 Acked-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/char/agp/intel-gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/char') diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index e01f5eaaec82..38390f7c6ab6 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -667,7 +667,7 @@ static int intel_gtt_init(void) gtt_map_size = intel_private.base.gtt_total_entries * 4; intel_private.gtt = NULL; - if (INTEL_GTT_GEN < 6) + if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2) intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, gtt_map_size); if (intel_private.gtt == NULL) -- cgit v1.2.3