From 867e359b97c970a60626d5d76bbe2a8fadbf38fb Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Fri, 28 May 2010 23:09:12 -0400 Subject: arch/tile: core support for Tilera 32-bit chips. This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: Chris Metcalf Acked-by: Arnd Bergmann Acked-by: FUJITA Tomonori Reviewed-by: Paul Mundt --- drivers/char/Makefile | 1 + drivers/char/hvc_tile.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 drivers/char/hvc_tile.c (limited to 'drivers/char') diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 88d6eac69754..273cee1cc77b 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_RIO) += rio/ generic_serial.o obj-$(CONFIG_HVC_CONSOLE) += hvc_vio.o hvsi.o obj-$(CONFIG_HVC_ISERIES) += hvc_iseries.o obj-$(CONFIG_HVC_RTAS) += hvc_rtas.o +obj-$(CONFIG_HVC_TILE) += hvc_tile.o obj-$(CONFIG_HVC_BEAT) += hvc_beat.o obj-$(CONFIG_HVC_DRIVER) += hvc_console.o obj-$(CONFIG_HVC_IRQ) += hvc_irq.o diff --git a/drivers/char/hvc_tile.c b/drivers/char/hvc_tile.c new file mode 100644 index 000000000000..75715b32f22a --- /dev/null +++ b/drivers/char/hvc_tile.c @@ -0,0 +1,67 @@ +/* + * %LINUX_LICENSE% + * + * + * + * + * + * + * + * + * + * + * + * Tilera TILE Processor hypervisor console + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "hvc_console.h" + +static int hvc_tile_put_chars(uint32_t vt, const char *buf, int count) +{ + return hv_console_write((HV_VirtAddr)buf, count); +} + +static int hvc_tile_get_chars(uint32_t vt, char *buf, int count) +{ + int i, c; + + for (i = 0; i < count; ++i) { + c = hv_console_read_if_ready(); + if (c < 0) + break; + buf[i] = c; + } + + return i; +} + +static const struct hv_ops hvc_tile_get_put_ops = { + .get_chars = hvc_tile_get_chars, + .put_chars = hvc_tile_put_chars, +}; + +static int __init hvc_tile_console_init(void) +{ + extern void disable_early_printk(void); + hvc_instantiate(0, 0, &hvc_tile_get_put_ops); + add_preferred_console("hvc", 0, NULL); + disable_early_printk(); + return 0; +} +console_initcall(hvc_tile_console_init); + +static int __init hvc_tile_init(void) +{ + hvc_alloc(0, 0, &hvc_tile_get_put_ops, 128); + return 0; +} +device_initcall(hvc_tile_init); -- cgit v1.2.3 From ef06f55a5c936a395f3ee2e1237bbebdb4396c65 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Fri, 2 Jul 2010 14:19:35 -0400 Subject: arch/tile: catch up on various minor cleanups. None of these changes fix any actual bugs, but are just various cleanups that fell out along the way. In particular, some unused #defines and includes are removed, PREFETCH_STRIDE is added (the default is right for our shipping chips, but wrong for our next generation), our tile-specific prefetching code is removed so the (identical) generic prefetching code can be used instead, a comment is fixed to be proper GPL and not just a "paste GPL here" token, a "//" comment is converted to "/* */", etc. Signed-off-by: Chris Metcalf Acked-by: Arnd Bergmann --- arch/tile/include/asm/cache.h | 5 ----- arch/tile/include/asm/irqflags.h | 1 - arch/tile/include/asm/processor.h | 24 ++++++------------------ arch/tile/include/asm/system.h | 2 -- arch/tile/include/asm/thread_info.h | 5 ----- arch/tile/include/hv/hypervisor.h | 2 +- drivers/char/hvc_tile.c | 18 +++++++++--------- 7 files changed, 16 insertions(+), 41 deletions(-) (limited to 'drivers/char') diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index 869a14f4ceae..f6101840c9e7 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -21,11 +21,6 @@ #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -/* bytes per L1 instruction cache line */ -#define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE() -#define L1I_CACHE_BYTES (1 << L1I_CACHE_SHIFT) -#define L1I_CACHE_ALIGN(x) (((x)+(L1I_CACHE_BYTES-1)) & -L1I_CACHE_BYTES) - /* bytes per L2 cache line */ #define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE() #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h index cf5bffd00fef..45cf67c2f286 100644 --- a/arch/tile/include/asm/irqflags.h +++ b/arch/tile/include/asm/irqflags.h @@ -15,7 +15,6 @@ #ifndef _ASM_TILE_IRQFLAGS_H #define _ASM_TILE_IRQFLAGS_H -#include #include #include diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h index 09584e263b00..d942d09b252e 100644 --- a/arch/tile/include/asm/processor.h +++ b/arch/tile/include/asm/processor.h @@ -267,32 +267,20 @@ extern int hash_default; /* Should kernel stack pages be hash-for-home? */ extern int kstack_hash; + +/* Does MAP_ANONYMOUS return hash-for-home pages by default? */ +#define uheap_hash hash_default + #else #define hash_default 0 #define kstack_hash 0 +#define uheap_hash 0 #endif /* Are we using huge pages in the TLB for kernel data? */ extern int kdata_huge; -/* - * Note that with OLOC the prefetch will return an unused read word to - * the issuing tile, which will cause some MDN traffic. Benchmarking - * should be done to see whether this outweighs prefetching. - */ -#define ARCH_HAS_PREFETCH -#define ARCH_HAS_PREFETCHW -#define ARCH_HAS_SPINLOCK_PREFETCH - -#define prefetch(ptr) __builtin_prefetch((ptr), 0, 3) -#define prefetchw(ptr) __builtin_prefetch((ptr), 1, 3) - -#ifdef CONFIG_SMP -#define spin_lock_prefetch(ptr) prefetchw(ptr) -#else -/* Nothing to prefetch. */ -#define spin_lock_prefetch(lock) do { } while (0) -#endif +#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE() #else /* __ASSEMBLY__ */ diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h index 0935094f370a..f749be327ce0 100644 --- a/arch/tile/include/asm/system.h +++ b/arch/tile/include/asm/system.h @@ -136,8 +136,6 @@ mb_incoherent(void) #define set_mb(var, value) \ do { var = value; mb(); } while (0) -#include - /* * Pause the DMA engine and static network before task switching. */ diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h index beec8729564a..3872f2b345d2 100644 --- a/arch/tile/include/asm/thread_info.h +++ b/arch/tile/include/asm/thread_info.h @@ -150,11 +150,6 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti, #endif #define TS_POLLING 0x0004 /* in idle loop but not sleeping */ #define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal */ -#define TS_EXEC_HASH_SET 0x0010 /* apply TS_EXEC_HASH_xxx flags */ -#define TS_EXEC_HASH_RO 0x0020 /* during exec, hash r/o segments */ -#define TS_EXEC_HASH_RW 0x0040 /* during exec, hash r/w segments */ -#define TS_EXEC_HASH_STACK 0x0080 /* during exec, hash the stack */ -#define TS_EXEC_HASH_FLAGS 0x00f0 /* mask for TS_EXEC_HASH_xxx flags */ #define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING) diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h index a90d2989587a..59b46dc53994 100644 --- a/arch/tile/include/hv/hypervisor.h +++ b/arch/tile/include/hv/hypervisor.h @@ -547,7 +547,7 @@ void hv_assert_intr(HV_IntrMask assert_mask); */ HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt); -#endif // !CHIP_HAS_IPI() +#endif /* !CHIP_HAS_IPI() */ /** Store memory mapping in debug memory so that external debugger can read it. * A maximum of 16 entries can be stored. diff --git a/drivers/char/hvc_tile.c b/drivers/char/hvc_tile.c index 75715b32f22a..c4efb55cbc03 100644 --- a/drivers/char/hvc_tile.c +++ b/drivers/char/hvc_tile.c @@ -1,15 +1,15 @@ /* - * %LINUX_LICENSE% - * - * - * - * - * - * - * - * + * Copyright 2010 Tilera Corporation. All Rights Reserved. * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. * * Tilera TILE Processor hypervisor console */ -- cgit v1.2.3