From 4beba08ba1574f6d427347edaba5b924b2f70826 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 11 Dec 2012 07:06:37 +0100 Subject: ARM: 7600/1: include CONFIG_DEBUG_LL_INCLUDE rather than mach/debug-macro.S Commit 91a9fec (ARM: move debug macros to common location) moves arch/arm/kernel/debug.S and arch/arm/kernel/head.S to CONFIG_DEBUG_LL_INCLUDE, but leaves arch/arm/boot/compressed/head.S still with mach/debug-macro.S. This causes the following build error on platforms that moved to new DEBUG_LL inclusion mechanism, when arch/arm/boot/compressed/head.S is compiled with DEBUG turned on. AS arch/arm/boot/compressed/head.o arch/arm/boot/compressed/head.S:49:30: fatal error: mach/debug-macro.S: No such file or directory compilation terminated. Fix the problem by replacing mach/debug-macro.S inclusion with CONFIG_DEBUG_LL_INCLUDE one. Reported-by: Steev Klimaszewski Signed-off-by: Shawn Guo Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 49ca86e37b8d..fe4d9c3ad761 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -44,7 +44,7 @@ #else -#include +#include CONFIG_DEBUG_LL_INCLUDE .macro writeb, ch, rb senduart \ch, \rb -- cgit v1.2.3 From b8b499c86be58cb309964fcab5b62ac4a240a878 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 12 Dec 2012 08:32:11 +0100 Subject: ARM: 7602/1: Pass real "__machine_arch_type" variable to setup_machine_tags() procedure This modification is needed to proper boot the custom machines with the IDs that are not described in the mach-types.h table. Signed-off-by: Alexander Shiyan Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 9a89bf4aefe1..3f6cbb2e3eda 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -733,7 +733,7 @@ void __init setup_arch(char **cmdline_p) setup_processor(); mdesc = setup_machine_fdt(__atags_pointer); if (!mdesc) - mdesc = setup_machine_tags(__atags_pointer, machine_arch_type); + mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type); machine_desc = mdesc; machine_name = mdesc->name; -- cgit v1.2.3 From dad5451a322bb682704f3ab13a558508a83e0b93 Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Fri, 14 Dec 2012 16:46:17 +0100 Subject: ARM: 7605/1: vmlinux.lds: Move .notes section next to the rodata The .notes, being read-only data by nature, were placed between read-write .data and .bss. This was harmful in case of the XIP kernel, as being placed in the RAM range, most likely far from the ROM address, was inflating the XIP images. Moving the .notes at the end of the read-only section (consisting of .text, .rodata and unwind info) fixes the problem. Reported-by: Marc Kleine-Budde Signed-off-by: Pawel Moll Tested-by: Marc Kleine-Budde Signed-off-by: Russell King --- arch/arm/kernel/vmlinux.lds.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index b9f38e388b43..11c1785bf63e 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -140,6 +140,8 @@ SECTIONS } #endif + NOTES + _etext = .; /* End of text and rodata section */ #ifndef CONFIG_XIP_KERNEL @@ -295,8 +297,6 @@ SECTIONS } #endif - NOTES - BSS_SECTION(0, 0, 0) _end = .; -- cgit v1.2.3 From 7bf9b7bef881aac820bf1f2e9951a17b09bd7e04 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sun, 16 Dec 2012 00:25:57 +0000 Subject: ARM: missing ->mmap_sem around find_vma() in swp_emulate.c find_vma() is *not* safe when somebody else is removing vmas. Not just the return value might get bogus just as you are getting it (this instance doesn't try to dereference the resulting vma), the search itself can get buggered in rather spectacular ways. IOW, ->mmap_sem really, really is not optional here. Signed-off-by: Al Viro Cc: Signed-off-by: Russell King --- arch/arm/kernel/swp_emulate.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index df745188f5de..ab1017bd1667 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -109,10 +109,12 @@ static void set_segfault(struct pt_regs *regs, unsigned long addr) { siginfo_t info; + down_read(¤t->mm->mmap_sem); if (find_vma(current->mm, addr) == NULL) info.si_code = SEGV_MAPERR; else info.si_code = SEGV_ACCERR; + up_read(¤t->mm->mmap_sem); info.si_signo = SIGSEGV; info.si_errno = 0; -- cgit v1.2.3 From d056a699dd3d9366dd3b4d9996e7848209199cda Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 19 Dec 2012 15:01:08 +0100 Subject: ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs flush_cache_louis flushes the D-side caches to the point of unification inner-shareable. On uniprocessor CPUs, this is defined as zero and therefore no flushing will take place. Rather than invent a new interface for UP systems, instead use our SMP_ON_UP patching code to read the LoUU from the CLIDR instead. Cc: Cc: Lorenzo Pieralisi Tested-by: Guennadi Liakhovetski Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/mm/cache-v7.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index cd956647c21a..7539ec275065 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr - mov r3, r3, lsr #20 @ r3 = LoUIS * 2 + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr + ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 + ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0 b flush_levels @ start flushing cache levels -- cgit v1.2.3 From e6ee4b2b57a8e0d8e551031173de080b338d3969 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 19 Dec 2012 15:01:50 +0100 Subject: ARM: 7607/1: realview: fix private peripheral memory base for EB rev. B boards Commit 34ae6c96a6a7 ("ARM: 7298/1: realview: fix mapping of MPCore private memory region") accidentally broke the definition for the base address of the private peripheral region on revision B Realview-EB boards. This patch uses the correct address for REALVIEW_EB11MP_PRIV_MEM_BASE. Cc: Acked-by: Marc Zyngier Tested-by: Florian Fainelli Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/mach-realview/include/mach/board-eb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h index 124bce6b4d7b..a301e61a5554 100644 --- a/arch/arm/mach-realview/include/mach/board-eb.h +++ b/arch/arm/mach-realview/include/mach/board-eb.h @@ -47,7 +47,7 @@ #define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB -#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000 +#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x10100000 #define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ #else -- cgit v1.2.3