From 35a6ae07c663499875309f18730f3440bb59f6fe Mon Sep 17 00:00:00 2001 From: Adrian-Ken Rueegsegger Date: Wed, 23 Mar 2016 11:34:29 +0100 Subject: x86/PCI: Refine PCI support check in pcibios_init() Also consider raw_pci_ext_ops when validating if a system has PCI support. This leads to proper resource allocation via pcibios_resource_survey() in the case where PCI config space is exclusively accessed through MMCONFIG. Signed-off-by: Adrian-Ken Rueegsegger Signed-off-by: Bjorn Helgaas --- arch/x86/pci/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 381a43c40bf7..8196054fedb0 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -516,7 +516,7 @@ void __init pcibios_set_cache_line_size(void) int __init pcibios_init(void) { - if (!raw_pci_ops) { + if (!raw_pci_ops && !raw_pci_ext_ops) { printk(KERN_WARNING "PCI: System does not support PCI\n"); return 0; } -- cgit v1.2.3 From 4f6926e9fdf94208dc37da0cd17835328fa4dbba Mon Sep 17 00:00:00 2001 From: Petr Štetiar Date: Fri, 1 Apr 2016 14:41:47 +0200 Subject: ARM: dts: imx6: Fix PCIe reset GPIO polarity on Toradex Apalis Ixora MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding reset-gpio-active-high boolean DT binding property, which we need to make PCIe working on Apalis SoMs and not break old DTBs. While at it, I've fixed comment and GPIO polarity. On Apalis SoMs the GPIO1_IO28 used to PCIe reset is not connected directly to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is inverted, active-high. Signed-off-by: Petr Štetiar Signed-off-by: Bjorn Helgaas --- arch/arm/boot/dts/imx6q-apalis-ixora.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 2cba82d0d859..4b533cb5c82e 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -174,8 +174,9 @@ }; &pcie { - /* active-low meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_LOW>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; status = "okay"; }; -- cgit v1.2.3 From c20e128030caf0537d5e906753eac1c28fefdb75 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 25 Apr 2016 15:59:50 -0500 Subject: alpha/PCI: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IO The alpha pci_mmap_resource() is used for both IORESOURCE_MEM and IORESOURCE_IO resources, but iomem_is_exclusive() is only applicable for IORESOURCE_MEM. Call iomem_is_exclusive() only for IORESOURCE_MEM resources, and do it earlier to match the generic version of pci_mmap_resource(). Fixes: 10a0ef39fbd1 ("PCI/alpha: pci sysfs resources") Signed-off-by: Bjorn Helgaas CC: Ivan Kokshaysky --- arch/alpha/kernel/pci-sysfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/alpha/kernel/pci-sysfs.c b/arch/alpha/kernel/pci-sysfs.c index 99e8d4796c96..92c0d460815b 100644 --- a/arch/alpha/kernel/pci-sysfs.c +++ b/arch/alpha/kernel/pci-sysfs.c @@ -77,10 +77,10 @@ static int pci_mmap_resource(struct kobject *kobj, if (i >= PCI_ROM_RESOURCE) return -ENODEV; - if (!__pci_mmap_fits(pdev, i, vma, sparse)) + if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start)) return -EINVAL; - if (iomem_is_exclusive(res->start)) + if (!__pci_mmap_fits(pdev, i, vma, sparse)) return -EINVAL; pcibios_resource_to_bus(pdev->bus, &bar, res); -- cgit v1.2.3 From b410f3b68d7ea8ca93abeb3420684c0378b7e134 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 20 Apr 2016 08:45:31 -0700 Subject: ARM: dts: imx6qp: Specify imx6qp version of PCIe core I.MX6Quad Plus has a slightly different version of PCIe core than reqular i.MX6Quad. Tested-by: Gary Bisson Signed-off-by: Andrey Smirnov Signed-off-by: Bjorn Helgaas Reviewed-by: Fabio Estevam --- arch/arm/boot/dts/imx6qp.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 1ada71437e49..886dbf2eca49 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -82,5 +82,8 @@ "ldb_di0", "ldb_di1", "prg"; }; + pcie: pcie@0x01000000 { + compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; + }; }; }; -- cgit v1.2.3 From da77b67195de1c65bef4908fa29967c4d0af2da2 Mon Sep 17 00:00:00 2001 From: Prarit Bhargava Date: Wed, 11 May 2016 12:27:15 -0400 Subject: x86/PCI: Mark Broadwell-EP Home Agent 1 as having non-compliant BARs Commit b894157145e4 ("x86/PCI: Mark Broadwell-EP Home Agent & PCU as having non-compliant BARs") marked Home Agent 0 & PCU has having non-compliant BARs. Home Agent 1 also has non-compliant BARs. Mark Home Agent 1 as having non-compliant BARs so the PCI core doesn't touch them. The problem with these devices is documented in the Xeon v4 specification update: BDF2 PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration Problem: During system initialization the Operating System may access the standard PCI BARs (Base Address Registers). Due to this erratum, accesses to the Home Agent BAR registers (Bus 1; Device 18; Function 0,4; Offsets (0x14-0x24) will return non-zero values. Implication: The operating system may issue a warning. Intel has not observed any functional failures due to this erratum. Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html Fixes: b894157145e4 ("x86/PCI: Mark Broadwell-EP Home Agent & PCU as having non-compliant BARs") Signed-off-by: Prarit Bhargava Signed-off-by: Bjorn Helgaas CC: Thomas Gleixner CC: Ingo Molnar CC: "H. Peter Anvin" CC: Andi Kleen --- arch/x86/pci/fixup.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index b7de1929714b..837ea36a837d 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -552,9 +552,16 @@ static void twinhead_reserve_killing_zone(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone); +/* + * Broadwell EP Home Agent BARs erroneously return non-zero values when read. + * + * See http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html + * entry BDF2. + */ static void pci_bdwep_bar(struct pci_dev *dev) { dev->non_compliant_bars = 1; } +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_bdwep_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_bdwep_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_bdwep_bar); -- cgit v1.2.3