From 31d4dcf705c33da28e3688bfb1f11889cf8b29f9 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 17 Mar 2015 11:39:30 +0200 Subject: drm/i915/bxt: Broxton uses the same GMS values as Skylake v2: Rebase on top of the early-quirks rework from Ville. Signed-off-by: Damien Lespiau (v1) Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index fe9f0b79a18b..ab470e475199 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -546,6 +546,7 @@ static const struct pci_device_id intel_stolen_ids[] __initconst = { INTEL_BDW_D_IDS(&gen8_stolen_funcs), INTEL_CHV_IDS(&chv_stolen_funcs), INTEL_SKL_IDS(&gen9_stolen_funcs), + INTEL_BXT_IDS(&gen9_stolen_funcs), }; static void __init intel_graphics_stolen(int num, int slot, int func) -- cgit v1.2.3 From 4f01e65037187581971f8b1068d4e1b1300a6562 Mon Sep 17 00:00:00 2001 From: Hyungwon Hwang Date: Fri, 12 Jun 2015 21:59:10 +0900 Subject: ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' The clock which was named as 'pll_clk' is actually not the clock source of PLL in MIPI DSI. This patch fixes this disagreement. Signed-off-by: Hyungwon Hwang Acked-by: Krzysztof Kozlowski Signed-off-by: Inki Dae --- arch/arm/boot/dts/exynos4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e20cdc24c3bb..1538d7ae7b86 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -167,7 +167,7 @@ phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; + clock-names = "bus_clk", "sclk_mipi"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3