From 0d23dc34a7cefde5ee25c321949579694edbd16d Mon Sep 17 00:00:00 2001 From: "Peter Zijlstra (Intel)" Date: Mon, 11 Apr 2022 18:19:35 +0800 Subject: x86/perf/core: Add pebs_capable to store valid PEBS_COUNTER_MASK value The value of pebs_counter_mask will be accessed frequently for repeated use in the intel_guest_get_msrs(). So it can be optimized instead of endlessly mucking about with branches. Signed-off-by: Peter Zijlstra (Intel) Message-Id: <20220411101946.20262-7-likexu@tencent.com> Signed-off-by: Paolo Bonzini --- arch/x86/events/perf_event.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/x86/events/perf_event.h') diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 07fdef4f9ad2..09c68265b577 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -828,6 +828,7 @@ struct x86_pmu { void (*pebs_aliases)(struct perf_event *event); unsigned long large_pebs_flags; u64 rtm_abort_event; + u64 pebs_capable; /* * Intel LBR -- cgit v1.2.3