From 0a9426df1858f71ac84eb7eef500b4247de5e3bb Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 9 Oct 2012 09:47:37 +0100 Subject: UAPI: (Scripted) Disintegrate arch/sh/include/asm Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones --- arch/sh/include/asm/cpu-features.h | 26 -------------------------- 1 file changed, 26 deletions(-) delete mode 100644 arch/sh/include/asm/cpu-features.h (limited to 'arch/sh/include/asm/cpu-features.h') diff --git a/arch/sh/include/asm/cpu-features.h b/arch/sh/include/asm/cpu-features.h deleted file mode 100644 index 694abe490edb..000000000000 --- a/arch/sh/include/asm/cpu-features.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef __ASM_SH_CPU_FEATURES_H -#define __ASM_SH_CPU_FEATURES_H - -/* - * Processor flags - * - * Note: When adding a new flag, keep cpu_flags[] in - * arch/sh/kernel/setup.c in sync so symbolic name - * mapping of the processor flags has a chance of being - * reasonably accurate. - * - * These flags are also available through the ELF - * auxiliary vector as AT_HWCAP. - */ -#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ -#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ -#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ -#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ -#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ -#define CPU_HAS_PTEA 0x0020 /* PTEA register */ -#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ -#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ -#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ -#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ - -#endif /* __ASM_SH_CPU_FEATURES_H */ -- cgit v1.2.3