From 363c55cae53742f3f685a1814912c6d4fda245b4 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Thu, 4 Jun 2009 20:27:10 +0800 Subject: MIPS: Add hibernation support [Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't support. As implemented in this patch cache and tlb flushing will also be invoked with interrupts disabled so smp_call_function() will blow up in charming ways. So limit to !SMP.] Reviewed-by: Pavel Machek Reviewed-by: Yan Hua Reviewed-by: Arnaud Patard Reviewed-by: Atsushi Nemoto Signed-off-by: Wu Zhangjin Signed-off-by: Hu Hongbing Signed-off-by: Ralf Baechle --- arch/mips/power/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 arch/mips/power/cpu.c (limited to 'arch/mips/power/cpu.c') diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c new file mode 100644 index 000000000000..7995df45dc8d --- /dev/null +++ b/arch/mips/power/cpu.c @@ -0,0 +1,43 @@ +/* + * Suspend support specific for mips. + * + * Licensed under the GPLv2 + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Hu Hongbing + * Wu Zhangjin + */ +#include +#include +#include + +static u32 saved_status; +struct pt_regs saved_regs; + +void save_processor_state(void) +{ + saved_status = read_c0_status(); + + if (is_fpu_owner()) + save_fp(current); + if (cpu_has_dsp) + save_dsp(current); +} + +void restore_processor_state(void) +{ + write_c0_status(saved_status); + + if (is_fpu_owner()) + restore_fp(current); + if (cpu_has_dsp) + restore_dsp(current); +} + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); + unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); + + return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); +} -- cgit v1.2.3