From 70768ebaa5872e11f68d71761bb9fa1546cb451e Mon Sep 17 00:00:00 2001 From: WANG Xuerui Date: Sat, 30 May 2020 15:32:41 +0800 Subject: MIPS: Loongson64: Guard against future cores without CPUCFG Previously it was thought that all future Loongson cores would come with native CPUCFG. From new information shared by Huacai this is definitely not true (maybe some future 2K cores, for example), so collisions at PRID_REV level are inevitable. The CPU model matching needs to take PRID_IMP into consideration. The emulation logic needs to be disabled for those future cores as well, as we cannot possibly encode their non-discoverable features right now. Reported-by: Huacai Chen Cc: Jiaxun Yang Signed-off-by: WANG Xuerui Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-loongson64/cpucfg-emul.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h index 01dc308df7b2..d64af19c210d 100644 --- a/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h +++ b/arch/mips/include/asm/mach-loongson64/cpucfg-emul.h @@ -12,6 +12,12 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c); +static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c) +{ + /* All supported cores have non-zero LOONGSON_CFG1 data. */ + return c->loongson3_cpucfg_data[0] != 0; +} + static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c, __u64 sel) { @@ -53,6 +59,11 @@ static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c) { } +static inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c) +{ + return false; +} + static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c, __u64 sel) { -- cgit v1.2.3