From 497e803ebf98ea88c7191e67333bfcc6ffd64bc6 Mon Sep 17 00:00:00 2001 From: Matt Redfearn Date: Fri, 18 Dec 2015 12:47:00 +0000 Subject: MIPS: smp-cps: Ensure secondary cores start with EVA disabled The kernel currently assumes that a core will start up in legacy mode using the exception base provided through the CM GCR registers. If a core has been configured in hardware to start in EVA mode, these assumptions will fail. This patch ensures that secondary cores are initialized to meet these assumptions. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11907/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mips-cm.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/include/asm') diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 6516e9da5133..b196825a1de9 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -243,6 +243,10 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 +/* GCR_RESET_EXT_BASE register fields */ +#define CM_GCR_RESET_EXT_BASE_EVARESET BIT(31) +#define CM_GCR_RESET_EXT_BASE_UEB BIT(30) + /* GCR_ACCESS register fields */ #define CM_GCR_ACCESS_ACCESSEN_SHF 0 #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) -- cgit v1.2.3