From c24a8a7a99885d5b986f38f6631f69e7794a3e5e Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Sat, 21 Dec 2013 16:52:13 +0530 Subject: MIPS: Netlogic: Add MSI support for XLP Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6270/ --- arch/mips/include/asm/mach-netlogic/irq.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/include/asm/mach-netlogic') diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h index 868ed8a2ed5c..c0dbd530cca6 100644 --- a/arch/mips/include/asm/mach-netlogic/irq.h +++ b/arch/mips/include/asm/mach-netlogic/irq.h @@ -9,7 +9,8 @@ #define __ASM_NETLOGIC_IRQ_H #include -#define NR_IRQS (64 * NLM_NR_NODES) +#define NLM_IRQS_PER_NODE 1024 +#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES) #define MIPS_CPU_IRQ_BASE 0 -- cgit v1.2.3