From a413647bb5bbe5414cd68332ff77588db09d10be Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 8 May 2009 07:40:25 +0000 Subject: Blackfin: pull updated anomaly lists from toolchain Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf518/include/mach/anomaly.h | 35 ++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) (limited to 'arch/blackfin/mach-bf518/include') diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index c847bb101076..b69bd9af38dd 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h @@ -6,14 +6,19 @@ * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */ +/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ +#if __SILICON_REVISION__ < 0 +# error will not work on BF518 silicon version +#endif + #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ #define ANOMALY_05000074 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) @@ -47,7 +52,7 @@ #define ANOMALY_05000435 (1) /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ #define ANOMALY_05000438 (1) -/* Preboot Cannot be Used to Program the PLL_DIV Register */ +/* Preboot Cannot be Used to Alter the PLL_DIV Register */ #define ANOMALY_05000439 (1) /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ #define ANOMALY_05000440 (1) @@ -61,32 +66,56 @@ #define ANOMALY_05000453 (1) /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ #define ANOMALY_05000455 (1) +/* False Hardware Error when RETI points to invalid memory */ +#define ANOMALY_05000461 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000119 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) #define ANOMALY_05000285 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (0) +#define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (0) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) #endif -- cgit v1.2.3 From ee0263cc2e7d774655bba6a6750a06099a3cebf0 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Wed, 20 May 2009 06:06:15 +0000 Subject: Blackfin: BF518F-EZBRD: handle required portmuxing of async pins The two high address lines on the BF51x are not dedicated which means we need to handle them like any other peripheral pin if we want to access the upper 2MB of parallel flash. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf518/boards/ezbrd.c | 9 +++++++++ arch/blackfin/mach-bf518/include/mach/portmux.h | 6 +++++- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/mach-bf518/include') diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 41f2eacfef20..602dce028b7b 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -82,7 +82,11 @@ static struct physmap_flash_data ezbrd_flash_data = { static struct resource ezbrd_flash_resource = { .start = 0x20000000, +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + .end = 0x202fffff, +#else .end = 0x203fffff, +#endif .flags = IORESOURCE_MEM, }; @@ -678,6 +682,11 @@ static int __init ezbrd_init(void) ARRAY_SIZE(bfin_i2c_board_info)); platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); + /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */ + peripheral_request(P_AMS2, "ParaFlash"); +#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE) + peripheral_request(P_AMS3, "ParaFlash"); +#endif return 0; } diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h index f618b487b2b0..a0fc77fd3315 100644 --- a/arch/blackfin/mach-bf518/include/mach/portmux.h +++ b/arch/blackfin/mach-bf518/include/mach/portmux.h @@ -185,6 +185,10 @@ #define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) #define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) -#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1)) +/* AMS */ +#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) + +#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1)) #endif /* _MACH_PORTMUX_H_ */ -- cgit v1.2.3