From 4934540d9fd49c13dd1fbef640fcdad75e9a3329 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 7 Jan 2009 23:14:38 +0800 Subject: Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- arch/blackfin/include/asm/mem_init.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/blackfin/include') diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 3cbc0f81ebf3..255a9316ad36 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -13,7 +13,8 @@ defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_MT48LC32M8A2_75) || \ defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ - defined(CONFIG_MEM_MT48LC32M16A2TG_75) + defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) #if (CONFIG_SCLK_HZ > 119402985) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -100,7 +101,8 @@ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ - defined(CONFIG_MEM_MT48LC16M16A2TG_75) + defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) /*SDRAM INFORMATION: */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -- cgit v1.2.3