From 5d89137a17ca804ee60077f5d4ad8d7ca60f0614 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 10 Apr 2009 20:52:08 +0000 Subject: Blackfin: fix data cache flushing when doing icache flushing Make sure we flush all data caches and their write buffers before flushing icache, otherwise random edge cases could crop up where stale data is read into icache from external memory. As fallout, punt the combined icache + dcache flush function since we cannot safely do them back to back -- the SSYNC is needed between the dcache flush and the icache flush. Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/include/asm/cacheflush.h | 35 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 19 deletions(-) (limited to 'arch/blackfin/include/asm/cacheflush.h') diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 1b040f5b4feb..d7726ab486ff 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h @@ -30,7 +30,8 @@ #ifndef _BLACKFIN_CACHEFLUSH_H #define _BLACKFIN_CACHEFLUSH_H -extern void blackfin_icache_dcache_flush_range(unsigned long start_address, unsigned long end_address); +#include /* for SSYNC() */ + extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); @@ -54,32 +55,28 @@ extern void blackfin_invalidate_entire_dcache(void); static inline void flush_icache_range(unsigned start, unsigned end) { -#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE) - -# if defined(CONFIG_BFIN_WT) - blackfin_icache_flush_range((start), (end)); - flush_icache_range_others(start, end); -# else - blackfin_icache_dcache_flush_range((start), (end)); -# endif - -#else +#if defined(CONFIG_BFIN_WB) + blackfin_dcache_flush_range(start, end); +#endif -# if defined(CONFIG_BFIN_ICACHE) - blackfin_icache_flush_range((start), (end)); + /* Make sure all write buffers in the data side of the core + * are flushed before trying to invalidate the icache. This + * needs to be after the data flush and before the icache + * flush so that the SSYNC does the right thing in preventing + * the instruction prefetcher from hitting things in cached + * memory at the wrong time -- it runs much further ahead than + * the pipeline. + */ + SSYNC(); +#if defined(CONFIG_BFIN_ICACHE) + blackfin_icache_flush_range(start, end); flush_icache_range_others(start, end); -# endif -# if defined(CONFIG_BFIN_DCACHE) - blackfin_dcache_flush_range((start), (end)); -# endif - #endif } #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ do { memcpy(dst, src, len); \ flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ - flush_icache_range_others((unsigned long) (dst), (unsigned long) (dst) + (len));\ } while (0) #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) -- cgit v1.2.3 From f339f46b05cfe289024b15a0525c8b61f1426a88 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 19 May 2009 12:58:13 +0000 Subject: Blackfin: fix detection of cached L2 SRAM Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly else memory easily goes unflushed when working with DMA. Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/cacheflush.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/blackfin/include/asm/cacheflush.h') diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index d7726ab486ff..94697f0f6f40 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h @@ -108,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr) addr >= _ramend && addr < physical_mem_end) return 1; +#ifndef CONFIG_BFIN_L2_NOT_CACHED + if (addr >= L2_START && addr < L2_START + L2_LENGTH) + return 1; +#endif + return 0; } -- cgit v1.2.3