From 802139d00970f32396ea4e25ab7a371967691da8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 18 Apr 2017 12:22:03 +0800 Subject: ARM: sun8i: a83t: Drop skeleton.dtsi skeleton.dtsi is deprecated. Remove it from sun8i-a83t.dtsi and add the needed device nodes directly. Also drop an extra, non-style-conforming line in the copyright license header. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 0ec143773ee9..913aacafe8d5 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -40,15 +40,20 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "skeleton.dtsi" - #include / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + }; + + chosen { + }; cpus { #address-cells = <1>; @@ -146,6 +151,11 @@ }; }; + memory { + reg = <0x40000000 0x80000000>; + device_type = "memory"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From e53bfb022fd21637270c43e83a853b823fc6b1d1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 18 Apr 2017 12:22:05 +0800 Subject: ARM: sun8i: a83t: Rename pinmux setting names The pinmux setting nodes all have an address element in their node names, however the pinctrl node does not have #address-cells. Rename the existing pinmux setting nodes and labels in sun8i-a83t.dtsi, dropping identifiers for functions that only have one possible setting, and using the pingroup name if the function is identically available on different pingroups. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 2 +- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 342e1d33fa1c..aecdeeb368ed 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -59,6 +59,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 88b1e0970b8d..d2614f101ecc 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -60,6 +60,6 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 913aacafe8d5..5f5c10c04dd3 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -174,7 +174,7 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0_pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -182,13 +182,13 @@ bias-pull-up; }; - uart0_pins_a: uart0@0 { - pins = "PF2", "PF4"; + uart0_pb_pins: uart0_pb_pins { + pins = "PB9", "PB10"; function = "uart0"; }; - uart0_pins_b: uart0@1 { - pins = "PB9", "PB10"; + uart0_pf_pins: uart0_pf_pins { + pins = "PF2", "PF4"; function = "uart0"; }; }; -- cgit v1.2.3 From 8a92770b648121570eafc7fdec5bb50b8e4a7347 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:16 +0800 Subject: ARM: sunxi: common-regulators: Drop pinmux settings for GPIO pins As part of our effort to move pinctrl/GPIO interlocking into the driver where it belongs, this patch drops the definition and usage of the pinmux settings for the common regulators defined in sunxi-common-regulators.dtsi. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 8 ------ arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 --- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 4 --- .../boot/dts/sun5i-a13-empire-electronix-d709.dts | 4 --- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 5 ---- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 4 --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 5 ---- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8 ------ arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 4 --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 --- arch/arm/boot/dts/sunxi-common-regulators.dtsi | 30 ---------------------- 13 files changed, 88 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index 85dcf81ab64e..bc4351bb851f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -120,10 +120,6 @@ status = "okay"; }; -&usb2_vbus_pin_a { - pins = "PH6"; -}; - &usb_otg { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index c6f742a7e69f..d2dee8d434bf 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -136,14 +136,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG13"; -}; - -&usb1_vbus_pin_a { - pins = "PB10"; -}; - &usb_otg { dr_mode = "host"; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index a27c3fa58736..16f839df4227 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -168,10 +168,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - pins = "PG13"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 894f874a5beb..eff36fe1aaa3 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -271,10 +271,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG11"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index ea3e5655a61b..5482be174e12 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -216,10 +216,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 34411d27aadf..3dbb0d7c2f8c 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -207,10 +207,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 2489c16f7efa..584fa579ded2 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -186,7 +186,6 @@ }; ®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ status = "okay"; }; @@ -202,10 +201,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 95f591bb8ced..38072c7e10e2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -269,10 +269,6 @@ status = "okay"; }; -&usb0_vbus_pin_a { - pins = "PG12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index d4f74f476f25..b4c87a23e3f8 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -344,11 +344,6 @@ status = "okay"; }; -&usb1_vbus_pin_a { - /* different pin from sunxi-common-regulators */ - pins = "PH24"; -}; - &usbphy { usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 96bb0bc198ba..004b6ddac813 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -85,10 +85,6 @@ }; }; -&ahci_pwr_pin_a { - pins = "PB3"; -}; - &ahci { target-supply = <®_ahci_5v>; status = "okay"; @@ -319,10 +315,6 @@ status = "okay"; }; -&usb2_vbus_pin_a { - pins = "PH12"; -}; - &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 7c96b53b76bf..98177b5891cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -106,10 +106,6 @@ status = "okay"; }; -&ahci_pwr_pin_a { - pins = "PH2"; -}; - &codec { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 5b6d14555b7c..d7d5330c566f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -195,10 +195,6 @@ status = "disabled"; }; -&usb1_vbus_pin_a { - pins = "PG13"; -}; - &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index ce5c53e4452f..d8e5826fb3de 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -44,33 +44,9 @@ #include -&pio { - ahci_pwr_pin_a: ahci_pwr_pin@0 { - pins = "PB8"; - function = "gpio_out"; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - pins = "PB9"; - function = "gpio_out"; - }; - - usb1_vbus_pin_a: usb1_vbus_pin@0 { - pins = "PH6"; - function = "gpio_out"; - }; - - usb2_vbus_pin_a: usb2_vbus_pin@0 { - pins = "PH3"; - function = "gpio_out"; - }; -}; - / { reg_ahci_5v: ahci-5v { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&ahci_pwr_pin_a>; regulator-name = "ahci-5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -82,8 +58,6 @@ reg_usb0_vbus: usb0-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_vbus_pin_a>; regulator-name = "usb0-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -94,8 +68,6 @@ reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_a>; regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -107,8 +79,6 @@ reg_usb2_vbus: usb2-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_a>; regulator-name = "usb2-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; -- cgit v1.2.3 From cf439662affda9475d4b71b910aad856fc3966d3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:17 +0800 Subject: ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting As part of our effort to move pinctrl/GPIO interlocking into the driver where it belongs, this patch drops the definition and usage of the mmc0_cd_pin_reference_design pinmux setting for the default mmc0 card detect GPIO pin. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +- arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 2 +- arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 2 +- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +- arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +- arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +- arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +- arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +- arch/arm/boot/dts/sun4i-a10-marsboard.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mk802.dts | 2 +- arch/arm/boot/dts/sun4i-a10-mk802ii.dts | 2 +- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +- arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ------ arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 2 +- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 2 +- arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-m3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ------ 38 files changed, 36 insertions(+), 48 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index f2a01fe2bebc..f80d37ddc4c6 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -171,7 +171,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index 942d739a4384..6b02de592a02 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -109,7 +109,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts index 17f8c5ec011c..a7d61994b8fd 100644 --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -128,7 +128,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index d844938e2aa7..a698a994e5ff 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -142,7 +142,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index aad3bec1cb39..e0777ae808c7 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -163,7 +163,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts index 9616cdecce93..d8bfd7b74916 100644 --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts @@ -146,7 +146,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index a1a7282199d5..856cfc9128e6 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -107,7 +107,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts index bc4351bb851f..6506595268b2 100644 --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts @@ -79,7 +79,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index b8923b92cb36..d51d8c302daf 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -161,7 +161,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index a1a2bbb3f9d3..a8e479fe43ca 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -147,7 +147,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 4a27eb9102cd..2acb89a87d41 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -305,7 +305,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts index 4e798f014c99..92e3e030ced3 100644 --- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts +++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -100,7 +100,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts index 308dc1513041..92b2d4af3d21 100644 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts @@ -140,7 +140,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index 98a5f7258dca..0f927da28ee1 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -141,7 +141,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 484c57493bd2..a5ed9e4e22c6 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -97,7 +97,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts index 2b75745cd246..81db6824a2c7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts @@ -72,7 +72,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts index c861fa7e356c..e74a881fd9a7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts @@ -83,7 +83,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 3a2522a9419d..462412ee903c 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -145,7 +145,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 83596fd2ccfc..84f55e76df0c 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -147,7 +147,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index a68c7cc53b94..c0f8c88b5a7d 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -149,7 +149,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b63668ece151..41c2579143fd 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -1030,12 +1030,6 @@ bias-pull-up; }; - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - pins = "PH1"; - function = "gpio_in"; - bias-pull-up; - }; - ps20_pins_a: ps20@0 { pins = "PI20", "PI21"; function = "ps2"; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index a2eab7aa80e0..7ac5bcc9f972 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -137,7 +137,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 102903e83bd2..4ebeecf9c3d7 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -178,7 +178,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index 99c00b9a1546..6e6264cd69f8 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -160,7 +160,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index 4da49717da21..e5cbcad3a556 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -157,7 +157,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index 28d3abbdc2d4..794e7617f545 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -104,7 +104,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */ diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts index d52222c82cb8..8a8a6dbcd414 100644 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts @@ -121,7 +121,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts index 86f69813683e..43c94787ef07 100644 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -117,7 +117,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index c4ee30709f3a..f7413094183c 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -109,7 +109,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 1af5b46862cb..64c8ef9a2756 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -187,7 +187,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index dcd0f7a0dffa..2ce1a9f13a17 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -130,7 +130,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index e7d45425758c..097bd755764c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -131,7 +131,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index def0ad8395bb..0b7403e4d687 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -198,7 +198,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index f47a5c46bc20..39bc73db72e5 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -130,7 +130,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 98177b5891cb..777152a3df0f 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -156,7 +156,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index e19f17177755..f8d0aafb9f88 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -151,7 +151,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index c3078d4f1093..84462d7961f5 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -120,7 +120,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 93aa55970bd7..c03b59aaec82 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1190,12 +1190,6 @@ bias-pull-up; }; - mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { - pins = "PH1"; - function = "gpio_in"; - bias-pull-up; - }; - mmc2_pins_a: mmc2@0 { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; -- cgit v1.2.3 From 52826587a44f55e958e89c6f21bfdaadf0273ac8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:18 +0800 Subject: ARM: sun8i: h3: orangepi-pc: Enable USB OTG The Orange Pi PC, PC Plus, and Plus 2E all have a USB OTG port that can be used in both powered host mode and peripheral mode. When in peripheral mode, the port does not power the board. There is no VBUS sensing on the port. All three boards have all related pins routed the same way. The device tree file for the Orange Pi Plus 2E is based on the Orange Pi PC Plus, which itself is based on the Orange Pi PC. Changes to the base Orange Pi PC device tree file affects all 3 boards. This patch adds the regulator controlling VBUS on the OTG port, the GPIO for the ID detect pin, and enables the USB OTG and host controllers. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index f148111c326d..1a044b17d6c6 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -97,6 +97,10 @@ status = "okay"; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -125,6 +129,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -156,6 +164,11 @@ }; }; +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -180,7 +193,14 @@ status = "disabled"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { - /* USB VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on USB host ports are always on */ status = "okay"; }; -- cgit v1.2.3 From ef00b70d386499aa110a03fa283e35f5839f13fa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 19 Apr 2017 13:09:19 +0800 Subject: ARM: sun8i: h3: bananapi-m2-plus: Enable USB OTG The Bananapi M2 Plus has a USB OTG port that can be used in both powered host mode and peripheral mode. When in peripheral mode, the port does not power the board. There is no VBUS sensing on the port. This patch adds the regulator controlling VBUS on the OTG port, the GPIO for the ID detect pin, and enables the USB OTG and host controllers. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index 52acbe111cad..17c7c088cdea 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -92,6 +92,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -145,6 +149,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -170,6 +178,11 @@ }; }; +®_usb0_vbus { + gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */ + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -182,7 +195,14 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { - /* USB VBUS is on as long as VCC-IO is on */ + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + usb0_vbus-supply = <®_usb0_vbus>; + /* USB host VBUS is on as long as VCC-IO is on */ status = "okay"; }; -- cgit v1.2.3 From 84f1738a9c6b9171e226e5324863e3257b89a503 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 20 Apr 2017 16:25:09 +0530 Subject: ARM: sun8i: Use - instead of @ for DT OPP entries Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski Reported-by: Masahiro Yamada Suggested-by: Mark Rutland Signed-off-by: Viresh Kumar Acked-by: Maxime Ripard Acked-by: Rob Herring Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4 ++-- arch/arm/boot/dts/sun8i-a33.dtsi | 30 +++++++++++++------------- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 9b620cc1d5f1..8a0b42a2c2da 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -88,13 +88,13 @@ }; &cpu0_opp_table { - opp@1104000000 { + opp-1104000000 { opp-hz = /bits/ 64 <1104000000>; opp-microvolt = <1320000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1320000>; clock-latency-ns = <244144>; /* 8 32k periods */ diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 013978259372..22660919bd08 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -50,73 +50,73 @@ compatible = "operating-points-v2"; opp-shared; - opp@120000000 { + opp-120000000 { opp-hz = /bits/ 64 <120000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@240000000 { + opp-240000000 { opp-hz = /bits/ 64 <240000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@312000000 { + opp-312000000 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@408000000 { + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@480000000 { + opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@504000000 { + opp-504000000 { opp-hz = /bits/ 64 <504000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@648000000 { + opp-648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@720000000 { + opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@816000000 { + opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@912000000 { + opp-912000000 { opp-hz = /bits/ 64 <912000000>; opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@1008000000 { + opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000>; clock-latency-ns = <244144>; /* 8 32k periods */ @@ -164,15 +164,15 @@ mali_opp_table: gpu-opp-table { compatible = "operating-points-v2"; - opp@144000000 { + opp-144000000 { opp-hz = /bits/ 64 <144000000>; }; - opp@240000000 { + opp-240000000 { opp-hz = /bits/ 64 <240000000>; }; - opp@384000000 { + opp-384000000 { opp-hz = /bits/ 64 <384000000>; }; }; -- cgit v1.2.3 From 4ee75fa55b7afd4cb65e378f0381f307bd63fa6c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:18 +0200 Subject: ARM: dtsi: axp209: add battery power supply subnode The X-Powers AXP209 PMIC exposes battery supply various data such as the battery status (charging, discharging, full, dead), current max limit, current current, battery capacity (in percentage), voltage max and min limits, current voltage, and battery capacity (in Ah). This adds the battery power supply subnode for AXP20X PMIC. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/axp209.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index 9677dd5cf6b6..3c8fa26e87b7 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -64,6 +64,11 @@ #gpio-cells = <2>; }; + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp209-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <1500>; -- cgit v1.2.3 From 4ec5c401269607903d59e11332fd55f43a4531e7 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:19 +0200 Subject: ARM: dtsi: axp22x: add battery power supply subnode The X-Powers AXP22X PMIC exposes battery supply various data such as the battery status (charging, discharging, full, dead), current max limit, current current, battery capacity (in percentage), voltage max limit, current voltage, and battery capacity (in Ah). This adds the battery power supply subnode for AXP22X PMIC. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/axp22x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi index 67331c5f1714..87fb08e812ec 100644 --- a/arch/arm/boot/dts/axp22x.dtsi +++ b/arch/arm/boot/dts/axp22x.dtsi @@ -57,6 +57,11 @@ status = "disabled"; }; + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp221-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; -- cgit v1.2.3 From e7c42f327bc8444205f4d258718648b32fcca04e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:20 +0200 Subject: ARM: dts: sun8i: sina33: enable battery power supply subnode The Sinlinx SinA33 has an AXP223 PMIC and a battery connector, thus, we enable the battery power supply subnode in its Device Tree. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 8a0b42a2c2da..433cf2a2a9a2 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -196,6 +196,10 @@ status = "okay"; }; +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <3000000>; -- cgit v1.2.3 From b9107d3798b8fdf6098be6672a5e181a35b918d0 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 18 Apr 2017 09:34:21 +0200 Subject: ARM: sun5i: chip: enable battery power supply subnode The NextThing Co. CHIP has an AXP209 PMIC with battery connector. This enables the battery power supply subnode. Signed-off-by: Quentin Schulz Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index d0785602663b..879a4b0f3bd5 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -132,6 +132,10 @@ status = "okay"; }; +&battery_power_supply { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins_a>; -- cgit v1.2.3 From 9a26882a7378ade6a74f845d439c8ef39b1a4712 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 21 Apr 2017 16:38:56 +0800 Subject: ARM: dts: sun6i: Add second display pipeline device nodes The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display frontends, backends, and tcons each. The relationship between the backends and tcons are 1:1, but the frontends can feed either backend. Add device nodes and of graph nodes describing this relationship. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 168 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 167 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 9c999d3788f6..dfcf64515d7f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -232,7 +232,7 @@ de: display-engine { compatible = "allwinner,sun6i-a31-display-engine"; - allwinner,pipelines = <&fe0>; + allwinner,pipelines = <&fe0>, <&fe1>; status = "disabled"; }; @@ -289,6 +289,43 @@ }; }; + tcon1: lcd-controller@01c0d000 { + compatible = "allwinner,sun6i-a31-tcon"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + resets = <&ccu RST_AHB1_LCD1>; + reset-names = "lcd"; + clocks = <&ccu CLK_AHB1_LCD1>, + <&ccu CLK_LCD1_CH0>, + <&ccu CLK_LCD1_CH1>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon1-pixel-clock"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon1_in_drc1: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -896,6 +933,130 @@ reg = <0>; remote-endpoint = <&be0_in_fe0>; }; + + fe0_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe0>; + }; + }; + }; + }; + + fe1: display-frontend@01e20000 { + compatible = "allwinner,sun6i-a31-display-frontend"; + reg = <0x01e20000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, + <&ccu CLK_DRAM_FE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_FE1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe1_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe1>; + }; + + fe1_out_be1: endpoint@1 { + reg = <1>; + remote-endpoint = <&be1_in_fe1>; + }; + }; + }; + }; + + be1: display-backend@01e40000 { + compatible = "allwinner,sun6i-a31-display-backend"; + reg = <0x01e40000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, + <&ccu CLK_DRAM_BE1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_BE1>; + + assigned-clocks = <&ccu CLK_BE1>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be1_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be1>; + }; + + be1_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be1>; + }; + }; + + be1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be1_out_drc1: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc1_in_be1>; + }; + }; + }; + }; + + drc1: drc@01e50000 { + compatible = "allwinner,sun6i-a31-drc"; + reg = <0x01e50000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, + <&ccu CLK_DRAM_DRC1>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_AHB1_DRC1>; + + assigned-clocks = <&ccu CLK_IEP_DRC1>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc1_in_be1: endpoint@0 { + reg = <0>; + remote-endpoint = <&be1_out_drc1>; + }; + }; + + drc1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc1_out_tcon1: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon1_in_drc1>; + }; }; }; }; @@ -926,6 +1087,11 @@ reg = <0>; remote-endpoint = <&fe0_out_be0>; }; + + be0_in_fe1: endpoint@1 { + reg = <1>; + remote-endpoint = <&fe1_out_be0>; + }; }; be0_out: port@1 { -- cgit v1.2.3 From f89f2a37cc52d13e94c91e134055a9d70c4b6690 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 21 Apr 2017 16:38:57 +0800 Subject: ARM: dts: sun6i: Enable tcon0 by default tcon0 contains a muxing register used to mux tcon output to downstream hdmi or mipi dsi encoders. tcon0 must be available for the mux to be configured. Whether the display subsystem is enabled or not is now solely controlled by the display-engine node. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 1 - arch/arm/boot/dts/sun6i-a31.dtsi | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index b4c87a23e3f8..55607208468b 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -319,7 +319,6 @@ &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd0_rgb888_pins>; - status = "okay"; }; &tcon0_out { diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index dfcf64515d7f..d0cede5aaeb5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -264,7 +264,6 @@ "tcon-ch0", "tcon-ch1"; clock-output-names = "tcon0-pixel-clock"; - status = "disabled"; ports { #address-cells = <1>; -- cgit v1.2.3 From e407e25d4f925d7be6d51fc8bc262efe7876bcf8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 1 May 2017 11:14:07 +0800 Subject: ARM: sun8i: a83t: Drop leading zeroes from device node addresses Kbuild now complains about leading zeroes in the address portion of device node names. Get rid of them all, except for the uart device node. U-boot currently hard codes the device node path. We can remove the leading zero for the uart once we teach U-boot to use the aliases or stdout-path property. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 5f5c10c04dd3..aecde8be53bc 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -162,7 +162,7 @@ #size-cells = <1>; ranges; - pio: pinctrl@01c20800 { + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; interrupts = , , @@ -193,7 +193,7 @@ }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = , @@ -201,7 +201,7 @@ clocks = <&osc24M>; }; - watchdog@01c20ca0 { + watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = ; @@ -218,7 +218,7 @@ status = "disabled"; }; - gic: interrupt-controller@01c81000 { + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, -- cgit v1.2.3 From 62628be26caae02b9320494c2fc5feb7daf7c1ee Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 1 May 2017 11:14:08 +0800 Subject: ARM: sun8i: a83t: Replace underscores with hyphens in pinmux node names We should use hyphens and not underscores in device node names. Replace the ones that were just added. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index aecde8be53bc..c0a1e4f74b89 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -174,7 +174,7 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - mmc0_pins: mmc0_pins { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -182,12 +182,12 @@ bias-pull-up; }; - uart0_pb_pins: uart0_pb_pins { + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; }; - uart0_pf_pins: uart0_pf_pins { + uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; }; -- cgit v1.2.3 From e20f04935176ec16f62c3c9c8b219490661aa10c Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Wed, 10 May 2017 11:51:38 +0000 Subject: ARM: dts: sun8i-h3: orange-pi-2: Enable audio codec The Orange Pi 2 routes the LINEOUT pins through a SGM8900 PA which needs to be enabled. The onboard microphone is routed to MIC1, with MBIAS providing power. Signed-off-by: Marcus Cooper Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index d7d5330c566f..8ff71b1bb45b 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -104,6 +104,15 @@ }; }; +&codec { + allwinner,pa-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ + allwinner,audio-routing = + "Speaker", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + &ehci1 { status = "okay"; }; -- cgit v1.2.3 From 392aba5558843891cb938cbb8f3da1e1557c87c4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Sat, 6 May 2017 07:30:38 +0200 Subject: arm: dts: sun7i-a20-bananapi: name the GPIO lines This names the GPIO lines on the Banana Pi board in accordance with the A20_Banana_Pi v1.4 Specification. This will make these line names reflect through to user space so that they can easily be identified and used with the new character device ABI. Signed-off-by: Oleksij Rempel Reviewed-by: Linus Walleij Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 51 ++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index ed2f35adf542..88a1c2363c6c 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -177,6 +177,57 @@ }; &pio { + gpio-line-names = + /* PA */ + "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", + "ETXD2", "ETXD1", "ETXD0", + "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO", + "ETXEN", "ETXCK", "ECRS", + "ECOL", "ETXERR", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PB */ + "PMU-SCK", "PMU-SDA", "", "", "", "", "", "", + "", "USB0-DRV", "", "", "", "", "", "", + "", "", "", "", "SCL", "SDA", "", "", + "", "", "", "", "", "", "", "", + /* PC */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PE */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PF */ + "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3", + "SD0-D2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PG */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* PH */ + "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "", + "", "", "SD0-DET", "", "", "", "", "", + "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN", + "LED1", "", "", "", "", "", "", "", + /* PI */ + "", "", "", "IO-GCLK", "", "", "", "", + "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI", + "SPI-MISO", "SPI-CE1", "", + "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", + "", "", "", "", "", "", "", ""; + usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; -- cgit v1.2.3 From 8378be878a5dd66cdad8bf06fd01396c532159e6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:39:58 +0800 Subject: ARM: sun8i: v3s: restore the usage of CCU definitions All the used CCU definitions are stripped from the V3s DTSI file when it's merged, as the DTSI file and the CCU device tree binding headers went to different trees. As they're all in Linus's tree now, restore the usage of the definitions. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 64 +++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 71075969e5e6..3b50fa580261 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -41,6 +41,8 @@ */ #include +#include +#include / { #address-cells = <1>; @@ -55,7 +57,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&ccu 14>; + clocks = <&ccu CLK_CPU>; }; }; @@ -96,15 +98,15 @@ mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ccu 22>, - <&ccu 45>, - <&ccu 47>, - <&ccu 46>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu 7>; + resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = ; status = "disabled"; @@ -115,15 +117,15 @@ mmc1: mmc@01c10000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ccu 23>, - <&ccu 48>, - <&ccu 50>, - <&ccu 49>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu 8>; + resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; status = "disabled"; @@ -134,15 +136,15 @@ mmc2: mmc@01c11000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ccu 24>, - <&ccu 51>, - <&ccu 53>, - <&ccu 52>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu 9>; + resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = ; status = "disabled"; @@ -153,8 +155,8 @@ usb_otg: usb@01c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; - clocks = <&ccu 29>; - resets = <&ccu 17>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; interrupts = ; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -169,9 +171,9 @@ <0x01c1a800 0x4>; reg-names = "phy_ctrl", "pmu0"; - clocks = <&ccu 56>; + clocks = <&ccu CLK_USB_PHY0>; clock-names = "usb0_phy"; - resets = <&ccu 0>; + resets = <&ccu RST_USB_PHY0>; reset-names = "usb0_reset"; status = "disabled"; #phy-cells = <1>; @@ -198,7 +200,7 @@ reg = <0x01c20800 0x400>; interrupts = , ; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -244,8 +246,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 49>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -255,8 +257,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 41>; - resets = <&ccu 50>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -266,8 +268,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 42>; - resets = <&ccu 51>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; @@ -275,8 +277,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; - clocks = <&ccu 38>; - resets = <&ccu 46>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "disabled"; @@ -288,8 +290,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; - clocks = <&ccu 39>; - resets = <&ccu 47>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 37eac4f9c6e819238fd8d02e9597b1d15e23b6e1 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:39:59 +0800 Subject: ARM: sun8i: v3s: add LRADC device node Allwinner V3s features a LRADC like the ones in older SoCs. Add a device tree node for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3b50fa580261..b9a3df941fb4 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -240,6 +240,13 @@ interrupts = ; }; + lradc: lradc@1c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x400>; + interrupts = ; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3 From be3c1392b3b7a0243a5a4bf3ae6fe42ee983974d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:40:00 +0800 Subject: ARM: sun8i: v3s: add pinmux for mmc1 The dock board of Lichee Pi Zero features a MicroSD slot on MMC1, which can be used with a MicroSD card or the MicroSD-slot Wi-Fi card provided by Lichee Pi Zero. Add pinmux for the mmc1 controller, and specify it in the mmc1 device node as it's the only pinmux for mmc1. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index b9a3df941fb4..6ff50665e5e6 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -128,6 +128,8 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -224,6 +226,14 @@ drive-strength = <30>; bias-pull-up; }; + + mmc1_pins: mmc1 { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; }; timer@01c20c00 { -- cgit v1.2.3 From 87ac8e18ee7217187170e038f2fa9a1faf59dcc7 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 15 May 2017 16:40:01 +0800 Subject: ARM: sun8i: v3s: add support for Lichee Pi Zero w/ dock board The Lichee Pi Zero board has a "dock board" which needs to be soldered with the 1.27mm stamp holes on a Lichee Pi Zero board. It features: - Onboard MIC and headphone jack (not supported yet) - Ethernet port (not supported yet) - An extra MicroSD slot connected to MMC1 controller - four keys connected to the LRADC. As it needs to be soldered with the main board to use, add a stand-alone device tree for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 96 ++++++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..929a4167fcaa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -905,7 +905,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-parrot.dtb \ - sun8i-v3s-licheepi-zero.dtb + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts new file mode 100644 index 000000000000..d1311098ea45 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-v3s-licheepi-zero.dts" + +#include + +/ { + model = "Lichee Pi Zero with Dock"; + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", + "allwinner,sun8i-v3s"; + + leds { + /* The LEDs use PG0~2 pins, which conflict with MMC1 */ + status = "disbaled"; + }; +}; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; + + button@600 { + label = "Select"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; + + button@800 { + label = "Start"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; +}; -- cgit v1.2.3 From 2a451bfa9870a766acc54243ed5e75435e9a1b03 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 17 May 2017 21:52:57 +0800 Subject: ARM: sun8i: v3s: enable SPI Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller at PC bank. The controller itself is identical to the one in H3 SoC. Add device tree node and the only pinmux node for it. Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi early sample. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 6ff50665e5e6..a49ebef53c91 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -234,6 +234,11 @@ drive-strength = <30>; bias-pull-up; }; + + spi0_pins: spi0 { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; }; timer@01c20c00 { @@ -314,6 +319,20 @@ #size-cells = <0>; }; + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- cgit v1.2.3 From 0d2c6f023ea173ef59a930b67e2e02a943f60b63 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 17 May 2017 09:40:49 +0200 Subject: ARM: sun5i: a10s: Add the HDMI controller node The A10s has an HDMI controller connected to the second TCON channel. Add it to our DT. Since the TV Encoder was the only channel 1 user so far, also add the property now that we have several users. Signed-off-by: Maxime Ripard [wens@csie.org: Replaced CLK_PLL_VIDEO[01]_2X with raw numbers for now Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 47 +++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i.dtsi | 1 + 2 files changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 1e38ff80366c..18f25c5e75ae 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -71,7 +71,46 @@ }; }; + display-engine { + compatible = "allwinner,sun5i-a10s-display-engine"; + allwinner,pipelines = <&fe0>; + }; + soc@01c00000 { + hdmi: hdmi@01c16000 { + compatible = "allwinner,sun5i-a10s-hdmi"; + reg = <0x01c16000 0x1000>; + interrupts = <58>; + clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, + <&ccu 9>, + <&ccu 16>; + clock-names = "ahb", "mod", "pll-0", "pll-1"; + dmas = <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_NORMAL 16>, + <&dma SUN4I_DMA_DEDICATED 24>; + dma-names = "ddc-tx", "ddc-rx", "audio-tx"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + pwm: pwm@01c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; @@ -128,3 +167,11 @@ &sram_a { }; + +&tcon0_out { + tcon0_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5175f9cc9bed..0e29f1d98a9e 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -272,6 +272,7 @@ tcon0_out_tve0: endpoint@1 { reg = <1>; remote-endpoint = <&tve0_in_tcon0>; + allwinner,tcon-channel = <1>; }; }; }; -- cgit v1.2.3 From d050971c42b0df9056114086ce835a8db0074b84 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 17 May 2017 09:40:50 +0200 Subject: ARM: sun5i: a10s-olinuxino: Enable HDMI The A10s Olinuxino has an HDMI connector. Make sure we can use it. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index eff36fe1aaa3..da95118af4dc 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -63,6 +63,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -76,6 +87,10 @@ }; }; +&be0 { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -91,6 +106,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -248,6 +273,10 @@ status = "okay"; }; +&tcon0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 1a8c176b2f15b879746b85b4c0d585f2016b65e3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 May 2017 15:06:10 +0800 Subject: ARM: sun8i: a83t: Add CCU device nodes Now that we have support for the A83T CCU, add a device node for it, and replace any existing placeholder clock phandles with the correct ones. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c0a1e4f74b89..c9a5d07b2ada 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -162,13 +162,23 @@ #size-cells = <1>; ranges; + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-a83t-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc16Md512>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; interrupts = , , ; reg = <0x01c20800 0x400>; - clocks = <&osc24M>; + clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -214,7 +224,8 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&ccu 53>; + resets = <&ccu 40>; status = "disabled"; }; -- cgit v1.2.3 From c31d488470820ab18eabd2c5bb9a08834d554d28 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 May 2017 15:06:11 +0800 Subject: ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator The datasheets for Allwinner SoCs set strict requirements on the stability of the external crystal oscillators. Add the accuracy for the main 24MHz oscillator to the device tree. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c9a5d07b2ada..e12dd7170b8f 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -126,6 +126,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; -- cgit v1.2.3 From e5b558a5b2296009574f9237185f4e139f4b50f9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 21 May 2017 18:16:55 -0300 Subject: ARM: dts: sunxi: Fix BCM43xx node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "bcrmf" is a typo and "wifi" is the preferred form to describe such node, so change it accordingly. Reported-by: Andreas Färber Reviewed-by: Chen-Yu Tsai Signed-off-by: Fabio Estevam Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 2 +- arch/arm/boot/dts/sun7i-a20-bananapro.dts | 2 +- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index bdfdce8ca6ba..51e6f1d21c32 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -138,7 +138,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 08e776ae095a..4c03cc3fd7b3 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -172,7 +172,7 @@ wakeup-source; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts index 83516bc81225..e7af1b7c33d5 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts @@ -172,7 +172,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 4ebeecf9c3d7..8dbf732c7aa9 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -195,7 +195,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index e5cbcad3a556..55809973a568 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -173,7 +173,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index 84462d7961f5..7f8405a0dd0f 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -137,7 +137,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index 17c7c088cdea..883072b611fa 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -130,7 +130,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; -- cgit v1.2.3 From 749b7a9775a63bc8b87bbbe185d849df4c39158d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:50 +0800 Subject: ARM: sun8i: a83t: Add device node for DMA controller The A83T SoC has a DMA controller that supports 8 DMA channels to and from various peripherals. Add a device node for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index e12dd7170b8f..47196feda26b 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -163,6 +163,15 @@ #size-cells = <1>; ranges; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-a83t-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu 21>; + resets = <&ccu 7>; + #dma-cells = <1>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-a83t-ccu"; reg = <0x01c20000 0x400>; -- cgit v1.2.3 From 9ecf12302cd2baaba2dfedc0173978ab37416866 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:51 +0800 Subject: ARM: sun8i: a83t: Add device node for SPDIF transmitter The A83T SoC has an SPDIF transmitter block. According to the vendor BSP kernel, it is compatible with the one found on the H3 SoC. Add a device node and pinmux setting for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 47196feda26b..1dc4cfe81534 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -202,6 +202,11 @@ bias-pull-up; }; + spdif_tx_pin: spdif-tx-pin { + pins = "PE18"; + function = "spdif"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; @@ -228,6 +233,22 @@ clocks = <&osc24M>; }; + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-spdif", + "allwinner,sun8i-h3-spdif"; + reg = <0x01c21000 0x400>; + interrupts = ; + clocks = <&ccu 44>, <&ccu 76>; + resets = <&ccu 32>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3 From 54f3b7f051d6467b8eaccaf0abee4669785a1b31 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 12:03:34 +0800 Subject: ARM: sun8i: a83t: cubietruck-plus: Add LED device nodes The Cubietruck Plus has 4 LEDs in different colors. Add device nodes for them. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index d2614f101ecc..9e10cc6f39d4 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -45,6 +45,8 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include + / { model = "Cubietech Cubietruck Plus"; compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; @@ -56,6 +58,30 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "cubietruck-plus:blue:usr"; + gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ + }; + + orange { + label = "cubietruck-plus:orange:usr"; + gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ + }; + + white { + label = "cubietruck-plus:white:usr"; + gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ + }; + + green { + label = "cubietruck-plus:green:usr"; + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + }; + }; }; &uart0 { -- cgit v1.2.3 From beea147ecdc3bcf3d6cf6006a65e00cc29c27f73 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 22 May 2017 14:25:52 +0800 Subject: ARM: sun8i: a83t: cubietruck-plus: Enable SPDIF output The Cubietruck Plus has an optical SPDIF out connector. Enable SPDIF audio output for this board. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 9e10cc6f39d4..cff33454fc24 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -82,6 +82,28 @@ gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&spdif { + status = "okay"; }; &uart0 { -- cgit v1.2.3 From 0ac409a6cac35a8190f7c6fdbfc274603ee43e7f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:33 +0800 Subject: ARM: sun7i: a20: cubieboard2: Move usb_otg node for alphabetical ordering We want to keep node references in alphabetical order, except for instances where node must be #included first. Move the usb_otg node reference so that all references to non-AXP209 device nodes are in alphabetical order. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 7ac5bcc9f972..c21edd75d0b3 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -174,11 +174,6 @@ status = "okay"; }; -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - #include "axp209.dtsi" ®_dcdc2 { @@ -220,6 +215,11 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { pinctrl-names = "default"; pinctrl-0 = <&usb0_id_detect_pin>; -- cgit v1.2.3 From 6df31af7d827ab8dbcf0baec0411813d7a709150 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:34 +0800 Subject: ARM: sun7i: a20: cubieboard2: Enable AXP209's ACIN power supply The ACIN pins of the AXP209 PMIC on the Cubieboard 2 are tied to the DC jack on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index c21edd75d0b3..2a50207618cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -176,6 +176,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -- cgit v1.2.3 From 17aafb5b336b5cb78973c290b12aa0bd239be7fe Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:35 +0800 Subject: ARM: sun7i: a20: bananapi-m1-plus: Enable AXP209's ACIN power supply The ACIN pins of the AXP209 PMIC on the Bananapi M1 Plus are tied to the "power input" micro USB connector next to the SATA connector on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 4c03cc3fd7b3..eb55e74232c9 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -144,6 +144,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; -- cgit v1.2.3 From 2fb90080db2c76e2ffcce1b8b3867250091b4d65 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:36 +0800 Subject: ARM: sun4i: a10: cubieboard: Enable AXP209's ACIN power supply The ACIN pins of the AXP209 PMIC on the Cubieboard are tied to the DC jack on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index a698a994e5ff..404ce7694899 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -182,6 +182,10 @@ #include "axp209.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -- cgit v1.2.3 From c7b7158f397b6e2fc5cd13925b185502ca026158 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:37 +0800 Subject: ARM: sun6i: a31: hummingbird: Enable AXP221's ACIN power supply The ACIN pins of the AXP221 PMIC on the A31 Hummingbird are tied to the DC jack on the board through a 12V to 5V buck converter. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 55607208468b..9ecb5f0b3f83 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -253,6 +253,10 @@ #include "axp22x.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v1.2.3 From 3c0492811ef83b3dfed88a7c3fe759ac7ad0197f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 May 2017 15:31:38 +0800 Subject: ARM: sun7i: a20: cubietruck: Tie AXP209's USB power supply to USB PHY The USB PHY can use either a GPIO pin or the PMIC's USB power supply to sense VBUS. Since both options are available on the Cubietruck, add the missing property for the USB power supply to the USB PHY node. The device tree provides all usable options. Ultimately, which method is used is up to the driver implementation. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 8dbf732c7aa9..bb510187602c 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -336,6 +336,7 @@ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; -- cgit v1.2.3 From 45857ae954783bcbab6f67c2300b7d98d214c393 Mon Sep 17 00:00:00 2001 From: Sergey Matyukevich Date: Sun, 28 May 2017 13:30:26 +0300 Subject: ARM: dts: orange-pi-zero: add node for SPI NOR Add node for SPI NOR flash on orange-pi-zero board. Disable this node by default and leave it to users to enable it if their board has SPI NOR flash chip populated. SPI NOR flash was optional in the first production batch in Dec 2016. In later batches flash chip was pre-populated. However there should be quite a few boards around which do not have flash chip. Signed-off-by: Sergey Matyukevich Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index 9e8b082c134f..0b8b969f7c64 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -143,6 +143,19 @@ status = "okay"; }; +&spi0 { + /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 2ed2388bc0c5b7d04c7b079d673ce61a0333c818 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 30 May 2017 17:42:50 +0000 Subject: ARM: dts: sun8i: h3: Add initial NanoPi M1 Plus support NanoPi M1 Plus is designed and developed by FriendlyElec for professionals, enterprise users, makers and hobbyists using the Allwinner H3 SOC. NanoPi M1 Plus key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 64 +++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 929a4167fcaa..2d9b5b0b5747 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -895,6 +895,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb \ sun8i-h3-orangepi-2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts new file mode 100644 index 000000000000..8ddd1b2cc097 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1 Plus"; + compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; -- cgit v1.2.3 From c80aec5e0596858f8e8b26fb4844969ea5eb66e7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 May 2017 15:58:20 +0800 Subject: ARM: sun8i: a83t: Add device node for PRCM The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. The PRCM also has controls for various power domains. These are not supported yet, neither in software nor in the device tree binding. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 1dc4cfe81534..49aeb56970ba 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -270,5 +270,15 @@ #interrupt-cells = <3>; interrupts = ; }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-a83t-r-ccu"; + reg = <0x01f01400 0x400>; + clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, + <&ccu 6>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- cgit v1.2.3 From e1679f09210fc2ed762747588c49f3b8909b9067 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 1 Jun 2017 21:39:04 +0200 Subject: ARM: sun5i: add a cryptographic engine node Add a node for the cryptographic engine that can be found on sun5i SoCs. This cryptographic engine is compatible with the Allwinner cryptographic accelerator driver. Signed-off-by: Antoine Tenart Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0e29f1d98a9e..98cc00341b00 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -356,6 +356,15 @@ status = "disabled"; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun5i-a13-crypto", + "allwinner,sun4i-a10-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <54>; + clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; + clock-names = "ahb", "mod"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; -- cgit v1.2.3 From 9bea19aac3226872af247f4d37d673fd15431941 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 1 Jun 2017 21:39:05 +0200 Subject: ARM: dts: sunxi: add SoC specific compatibles for the crypto nodes Add SoC specific compatibles for all sunXi crypto nodes, in addition to the one already used (allwinner,sun4i-a10-crypto). Signed-off-by: Antoine Tenart Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 3 ++- arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d0cede5aaeb5..aebc3f9dc7b6 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -816,7 +816,8 @@ }; crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + compatible = "allwinner,sun6i-a31-crypto", + "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c03b59aaec82..96bee776e145 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1019,7 +1019,8 @@ }; crypto: crypto-engine@01c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + compatible = "allwinner,sun7i-a20-crypto", + "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; clocks = <&ahb_gates 5>, <&ss_clk>; -- cgit v1.2.3 From 21b29920933086b34f4a58692a079e9914115019 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 24 May 2017 19:17:23 +0800 Subject: ARM: sun8i: v3s: add device nodes for DE2 display pipeline Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer and only one TCON connected to this mixer, which have RGB LCD output. Add device nodes for this display pipeline. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-v3s.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index a49ebef53c91..3a06dc5b3746 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -61,6 +61,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -95,6 +101,83 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-v3s-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks 0>, + <&display_clocks 6>; + clock-names = "bus", + "mod"; + resets = <&display_clocks 0>; + assigned-clocks = <&display_clocks 6>; + assigned-clock-rates = <150000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; -- cgit v1.2.3 From 694ca10ca059812219a2841f3c385aca8f6a3b17 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 3 Jun 2017 22:44:27 +0800 Subject: ARM: sun8i: a83t: Add device node for R_PIO The A83T has 1 pingroup with 13 pins belonging to the R_PIO or special pin controller. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Acked-by: Linus Walleij --- arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 49aeb56970ba..bf63e3b77572 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -44,6 +44,8 @@ #include +#include + / { interrupt-parent = <&gic>; #address-cells = <1>; @@ -280,5 +282,18 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun8i-a83t-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- cgit v1.2.3 From 0e9d528f0702ee07216a7f1d2a55cee0b23a3bba Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 7 Jun 2017 19:33:44 +0200 Subject: ARM: sun8i: a83t: Add dt node for the syscon control module This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index bf63e3b77572..8923ba625b76 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -165,6 +165,12 @@ #size-cells = <1>; ranges; + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-a83t-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a83t-dma"; reg = <0x01c02000 0x1000>; -- cgit v1.2.3 From 723ca929a507a05bf4638f620b284f25d2047cf3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 10 Jun 2017 00:05:48 +0800 Subject: ARM: sun6i: a31s: primo81: Change USB OTG to OTG mode Now that we have support for the AXP221 PMIC's USB VBUS detection and DRIVEVBUS vbus control, we can use the USB OTG port in proper OTG mode. This patch enables the aforementioned PMIC functions, adds the OTG ID detection pin to the USB PHY node, and changes the mode of USB OTG to "otg". Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index f3712753fa42..73b163a7d9dd 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -158,6 +158,7 @@ reg = <0x68>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; }; }; @@ -226,6 +227,11 @@ regulator-name = "vddio-csi"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_eldo3 { regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1320000>; @@ -238,12 +244,18 @@ }; &usb_otg { - /* otg support requires support for AXP221 usb-power-supply and GPIO */ - dr_mode = "host"; + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { status = "okay"; }; &usbphy { + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; status = "okay"; }; -- cgit v1.2.3 From d5e9edfd37fc32098349b7753637bc1c80a16003 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 10 Jun 2017 00:05:49 +0800 Subject: ARM: sun6i: a31s: primo81: Enable battery power supply The MSI Primo81 tablet has a 3500 mAh 3.7V LiPo battery. Enable the PMIC's battery power supply so the battery can be monitored. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 73b163a7d9dd..4c10123509c4 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -164,6 +164,10 @@ #include "axp22x.dtsi" +&battery_power_supply { + status = "okay"; +}; + ®_aldo3 { regulator-always-on; regulator-min-microvolt = <2700000>; -- cgit v1.2.3