From f24284adcdeae963aacf0c9b17979c875069cd80 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Fri, 24 Feb 2006 21:37:50 +0000 Subject: [ARM] noMMU: block sys_fork in nommu mode The sys_fork is not supported in nommu mode. The other syscalls that is not supported in nommu mode are to be defined as cond_signal in kernel/sys_ni.c. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/kernel/sys_arm.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index a491de2d9024..8170af471439 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third, */ asmlinkage int sys_fork(struct pt_regs *regs) { +#ifdef CONFIG_MMU return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL); +#else + /* can not support in nommu mode */ + return(-EINVAL); +#endif } /* Clone a task - this clones the calling program thread. -- cgit v1.2.3 From 0f44ba1d1e67201c0c58af26eb441fa7014c89ec Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 24 Feb 2006 21:04:56 +0000 Subject: [ARM] Move read of processor ID out of lookup_processor_type() Read the processor ID at boot, and save it in "processor_id" as we did before. Later, when we re-parse the CPU type in the setup.c code, re-use the value stored in "processor_id". This allows a cleaner work-around for noMMU devices without CP#15. Signed-off-by: Russell King --- arch/arm/kernel/head.S | 15 +++++++++------ arch/arm/kernel/setup.c | 4 ++-- 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 1aca1775b28f..571d6d584919 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -82,6 +82,7 @@ ENTRY(stext) msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode @ and irqs disabled + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? beq __error_p @ yes, error 'p' @@ -156,6 +157,7 @@ ENTRY(secondary_startup) * as it has already been validated by the primary processor. */ msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor? moveq r0, #'p' @ yes, error 'p' @@ -450,19 +452,19 @@ __error: * (and therefore, we are not in the correct address space). We have to * calculate the offset. * + * r9 = cpuid * Returns: * r3, r4, r6 corrupted * r5 = proc_info pointer in physical address space - * r9 = cpuid + * r9 = cpuid (preserved) */ .type __lookup_processor_type, %function __lookup_processor_type: adr r3, 3f - ldmda r3, {r5, r6, r9} - sub r3, r3, r9 @ get offset between virt&phys + ldmda r3, {r5 - r7} + sub r3, r3, r7 @ get offset between virt&phys add r5, r5, r3 @ convert virt addresses to add r6, r6, r3 @ physical address space - mrc p15, 0, r9, c0, c0 @ get processor id 1: ldmia r5, {r3, r4} @ value, mask and r4, r4, r9 @ mask wanted bits teq r3, r4 @@ -477,10 +479,11 @@ __lookup_processor_type: * This provides a C-API version of the above function. */ ENTRY(lookup_processor_type) - stmfd sp!, {r4 - r6, r9, lr} + stmfd sp!, {r4 - r7, r9, lr} + mov r9, r0 bl __lookup_processor_type mov r0, r5 - ldmfd sp!, {r4 - r6, r9, pc} + ldmfd sp!, {r4 - r7, r9, pc} /* * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 08974cbe9824..b7cd280bfd63 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -278,7 +278,7 @@ int cpu_architecture(void) * These functions re-use the assembly code in head.S, which * already provide the required functionality. */ -extern struct proc_info_list *lookup_processor_type(void); +extern struct proc_info_list *lookup_processor_type(unsigned int); extern struct machine_desc *lookup_machine_type(unsigned int); static void __init setup_processor(void) @@ -290,7 +290,7 @@ static void __init setup_processor(void) * types. The linker builds this table for us from the * entries in arch/arm/mm/proc-*.S */ - list = lookup_processor_type(); + list = lookup_processor_type(processor_id); if (!list) { printk("CPU configuration botched (ID %08x), unable " "to continue.\n", processor_id); -- cgit v1.2.3 From 74945c8616a50074277e18641baaae7464006766 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 16 Mar 2006 14:44:36 +0000 Subject: [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King --- arch/arm/mach-sa1100/assabet.c | 1 + arch/arm/mm/proc-arm1020.S | 1 + arch/arm/mm/proc-arm1020e.S | 1 + arch/arm/mm/proc-arm1022.S | 1 + arch/arm/mm/proc-arm1026.S | 1 + arch/arm/mm/proc-arm6_7.S | 1 + arch/arm/mm/proc-arm720.S | 1 + arch/arm/mm/proc-arm920.S | 1 + arch/arm/mm/proc-arm922.S | 1 + arch/arm/mm/proc-arm925.S | 1 + arch/arm/mm/proc-arm926.S | 1 + arch/arm/mm/proc-sa110.S | 1 + arch/arm/mm/proc-sa1100.S | 1 + arch/arm/mm/proc-v6.S | 1 + arch/arm/mm/proc-xscale.S | 1 + include/asm-arm/pgalloc.h | 5 +++ include/asm-arm/pgtable-hwdef.h | 88 +++++++++++++++++++++++++++++++++++++++++ include/asm-arm/pgtable.h | 80 ------------------------------------- 18 files changed, 108 insertions(+), 80 deletions(-) create mode 100644 include/asm-arm/pgtable-hwdef.h (limited to 'arch/arm') diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index a599bb0d4ab8..c58f12ba7a93 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 82ec954e45b6..5f460d717253 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 7375fe930f72..3e5ea5508839 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 6ca639094d6f..f778545d57a2 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 10317e4f55d2..148c111fde73 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 8e7e1e70ab05..540359b475d0 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index a13e0184d343..72b0819326db 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index d16513899999..e57d3b8de4b7 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 23b8ed97f4e3..3170b37f82f2 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index ee95c52db513..eb78850addaa 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 7d042dc20c47..23ad5027d90c 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index bd330c4075a1..c916a6cae404 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 91b89124c0d7..41f21f2dd8ff 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -23,6 +23,7 @@ #include #include #include +#include #include /* diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 92f3ca31b7b9..9a7e7c096aa9 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2d3823ec3153..3e7e6a8f4109 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index bc18ff405181..c4ac2e67768d 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h @@ -10,10 +10,15 @@ #ifndef _ASMARM_PGALLOC_H #define _ASMARM_PGALLOC_H +#include +#include #include #include #include +#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) +#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) + /* * Since we have only two-level page tables, these are trivial */ diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h new file mode 100644 index 000000000000..1d033495cc75 --- /dev/null +++ b/include/asm-arm/pgtable-hwdef.h @@ -0,0 +1,88 @@ +/* + * linux/include/asm-arm/pgtable-hwdef.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASMARM_PGTABLE_HWDEF_H +#define _ASMARM_PGTABLE_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_FAULT (0 << 0) +#define PMD_TYPE_TABLE (1 << 0) +#define PMD_TYPE_SECT (2 << 0) +#define PMD_BIT4 (1 << 4) +#define PMD_DOMAIN(x) ((x) << 5) +#define PMD_PROTECTION (1 << 9) /* v5 */ +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (1 << 2) +#define PMD_SECT_CACHEABLE (1 << 3) +#define PMD_SECT_AP_WRITE (1 << 10) +#define PMD_SECT_AP_READ (1 << 11) +#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ +#define PMD_SECT_APX (1 << 15) /* v6 */ +#define PMD_SECT_S (1 << 16) /* v6 */ +#define PMD_SECT_nG (1 << 17) /* v6 */ +#define PMD_SECT_SUPER (1 << 18) /* v6 */ + +#define PMD_SECT_UNCACHED (0) +#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) +#define PMD_SECT_WT (PMD_SECT_CACHEABLE) +#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) +#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) + +/* + * - coarse table (not used) + */ + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_FAULT (0 << 0) +#define PTE_TYPE_LARGE (1 << 0) +#define PTE_TYPE_SMALL (2 << 0) +#define PTE_TYPE_EXT (3 << 0) /* v5 */ +#define PTE_BUFFERABLE (1 << 2) +#define PTE_CACHEABLE (1 << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_XN (1 << 0) /* v6 */ +#define PTE_EXT_AP_MASK (3 << 4) +#define PTE_EXT_AP0 (1 << 4) +#define PTE_EXT_AP1 (2 << 4) +#define PTE_EXT_AP_UNO_SRO (0 << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ +#define PTE_EXT_APX (1 << 9) /* v6 */ +#define PTE_EXT_SHARED (1 << 10) /* v6 */ +#define PTE_EXT_NG (1 << 11) /* v6 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_MASK (0xff << 4) +#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) +#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) +#define PTE_SMALL_AP_URO_SRW (0xaa << 4) +#define PTE_SMALL_AP_URW_SRW (0xff << 4) + +#endif diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 70e00d08345e..e595ae24efe2 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -136,81 +136,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PMD) - * - common - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (1 << 0) -#define PMD_TYPE_SECT (2 << 0) -#define PMD_BIT4 (1 << 4) -#define PMD_DOMAIN(x) ((x) << 5) -#define PMD_PROTECTION (1 << 9) /* v5 */ -/* - * - section - */ -#define PMD_SECT_BUFFERABLE (1 << 2) -#define PMD_SECT_CACHEABLE (1 << 3) -#define PMD_SECT_AP_WRITE (1 << 10) -#define PMD_SECT_AP_READ (1 << 11) -#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ -#define PMD_SECT_APX (1 << 15) /* v6 */ -#define PMD_SECT_S (1 << 16) /* v6 */ -#define PMD_SECT_nG (1 << 17) /* v6 */ -#define PMD_SECT_SUPER (1 << 18) /* v6 */ - -#define PMD_SECT_UNCACHED (0) -#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) -#define PMD_SECT_WT (PMD_SECT_CACHEABLE) -#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) -#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) - -/* - * - coarse table (not used) - */ - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* v5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* v6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ -#define PTE_EXT_APX (1 << 9) /* v6 */ -#define PTE_EXT_SHARED (1 << 10) /* v6 */ -#define PTE_EXT_NG (1 << 11) /* v6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) - /* * "Linux" PTE definitions. * @@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #ifndef __ASSEMBLY__ -#include - -#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) -#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) - /* * The following macros handle the cache and bufferable bits... */ -- cgit v1.2.3 From 48fa14f7618fe89cac9b807b05b66df4b595fc7e Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 16 Mar 2006 14:52:33 +0000 Subject: [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG Rather than having a growing dependency line, use select to set these configuration symbols. Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 3b79d0e23455..57a48d92ac41 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -266,12 +266,18 @@ config CPU_32v6K # This defines the compiler instruction set which depends on the machine type. config CPU_32v3 bool + select TLS_REG_EMUL if SMP + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v4 bool + select TLS_REG_EMUL if SMP + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v5 bool + select TLS_REG_EMUL if SMP + select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v6 bool @@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE config TLS_REG_EMUL bool - default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) help An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to @@ -436,7 +441,6 @@ config HAS_TLS_REG config NEEDS_SYSCALL_FOR_CMPXCHG bool - default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) help SMP on a pre-ARMv6 processor? Well OK then. Forget about fast user space cmpxchg support. -- cgit v1.2.3 From c76b6b41d0ae29e1127d9f81cb687cabda57c14c Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Fri, 24 Mar 2006 09:53:18 +0000 Subject: [ARM] nommu: rename compressed/head.S symbols to a new style This patch renames symbols to a new style to prepare mpu support code merging. e.g. __armv4_cache_on --> __armv4_mmu_cache_on Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 82 ++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 41 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index db3389d8e027..491c7e4c9ac6 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size str r1, [r0] mov pc, lr -__armv4_cache_on: +__armv4_mmu_cache_on: mov r12, lr bl __setup_mmu mov r0, #0 @@ -367,24 +367,24 @@ __armv4_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x0030 - bl __common_cache_on + bl __common_mmu_cache_on mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mov pc, r12 -__arm6_cache_on: +__arm6_mmu_cache_on: mov r12, lr bl __setup_mmu mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 mov r0, #0x30 - bl __common_cache_on + bl __common_mmu_cache_on mov r0, #0 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 mov pc, r12 -__common_cache_on: +__common_mmu_cache_on: #ifndef DEBUG orr r0, r0, #0x000d @ Write buffer, mmu #endif @@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types proc_types: .word 0x41560600 @ ARM6/610 .word 0xffffffe0 - b __arm6_cache_off @ works, but slow - b __arm6_cache_off + b __arm6_mmu_cache_off @ works, but slow + b __arm6_mmu_cache_off mov pc, lr -@ b __arm6_cache_on @ untested -@ b __arm6_cache_off -@ b __armv3_cache_flush +@ b __arm6_mmu_cache_on @ untested +@ b __arm6_mmu_cache_off +@ b __armv3_mmu_cache_flush .word 0x00000000 @ old ARM ID .word 0x0000f000 @@ -486,14 +486,14 @@ proc_types: .word 0x41007000 @ ARM7/710 .word 0xfff8fe00 - b __arm7_cache_off - b __arm7_cache_off + b __arm7_mmu_cache_off + b __arm7_mmu_cache_off mov pc, lr .word 0x41807200 @ ARM720T (writethrough) .word 0xffffff00 - b __armv4_cache_on - b __armv4_cache_off + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off mov pc, lr .word 0x00007000 @ ARM7 IDs @@ -506,41 +506,41 @@ proc_types: .word 0x4401a100 @ sa110 / sa1100 .word 0xffffffe0 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x6901b110 @ sa1110 .word 0xfffffff0 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush @ These match on the architecture ID .word 0x00020000 @ ARMv4T .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x00050000 @ ARMv5TE .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x00060000 @ ARMv5TEJ .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv4_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush .word 0x00070000 @ ARMv6 .word 0x000f0000 - b __armv4_cache_on - b __armv4_cache_off - b __armv6_cache_flush + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv6_mmu_cache_flush .word 0 @ unrecognised type .word 0 @@ -562,7 +562,7 @@ proc_types: cache_off: mov r3, #12 @ cache_off function b call_cache_fn -__armv4_cache_off: +__armv4_mmu_cache_off: mrc p15, 0, r0, c1, c0 bic r0, r0, #0x000d mcr p15, 0, r0, c1, c0 @ turn MMU and cache off @@ -571,15 +571,15 @@ __armv4_cache_off: mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 mov pc, lr -__arm6_cache_off: +__arm6_mmu_cache_off: mov r0, #0x00000030 @ ARM6 control reg. - b __armv3_cache_off + b __armv3_mmu_cache_off -__arm7_cache_off: +__arm7_mmu_cache_off: mov r0, #0x00000070 @ ARM7 control reg. - b __armv3_cache_off + b __armv3_mmu_cache_off -__armv3_cache_off: +__armv3_mmu_cache_off: mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 @@ -601,7 +601,7 @@ cache_clean_flush: mov r3, #16 b call_cache_fn -__armv6_cache_flush: +__armv6_mmu_cache_flush: mov r1, #0 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB @@ -609,7 +609,7 @@ __armv6_cache_flush: mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr -__armv4_cache_flush: +__armv4_mmu_cache_flush: mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size mrc p15, 0, r3, c0, c0, 1 @ read cache type @@ -637,7 +637,7 @@ no_cache_id: mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr -__armv3_cache_flush: +__armv3_mmu_cache_flush: mov r1, #0 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 mov pc, lr -- cgit v1.2.3