From 7666e9ec9b58f64e4a1a462620ae3d0015ee39bf Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:59 +0100 Subject: arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards RIFSC is a firewall controller. Add "st,stm32mp25-rifsc" compatible and reference RIFSC as an access-control-provider. Keep "simple-bus" compatible backward compatibility. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++-- arch/arm64/boot/dts/st/stm32mp255.dtsi | 33 ++++++++++++++++----------------- 2 files changed, 21 insertions(+), 19 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5dd4f3580a60..af1444bf9442 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -123,11 +123,12 @@ interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; usart2: serial@400e0000 { @@ -135,6 +136,7 @@ reg = <0x400e0000 0x400>; interrupts = ; clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; status = "disabled"; }; @@ -148,6 +150,7 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + access-controllers = <&rifsc 76>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 17f197c5b22b..570c5dd0b2c3 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,22 +5,21 @@ */ #include "stm32mp253.dtsi" -/ { - soc@0 { - rifsc: rifsc-bus@42080000 { - vdec: vdec@480d0000 { - compatible = "st,stm32mp25-vdec"; - reg = <0x480d0000 0x3c8>; - interrupts = ; - clocks = <&ck_icn_p_vdec>; - }; +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + access-controllers = <&rifsc 89>; - venc: venc@480e0000 { - compatible = "st,stm32mp25-venc"; - reg = <0x480e0000 0x800>; - interrupts = ; - clocks = <&ck_icn_ls_mcu>; - }; - }; }; -}; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = ; + clocks = <&ck_icn_ls_mcu>; + access-controllers = <&rifsc 90>; + }; +}; \ No newline at end of file -- cgit v1.2.3 From 948a4db95dc8c86e70357c20fe2aede7fab69219 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 11 Apr 2024 11:24:53 +0200 Subject: arm64: dts: st: add rcc support for STM32MP25 Add RCC support to manage clocks and resets on the STM32MP25. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 144 ++++++++++++++++++++++++--------- arch/arm64/boot/dts/st/stm32mp255.dtsi | 4 +- 2 files changed, 110 insertions(+), 38 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index af1444bf9442..193808919e83 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -3,7 +3,9 @@ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ +#include #include +#include / { #address-cells = <2>; @@ -35,34 +37,16 @@ }; clocks { - ck_flexgen_08: ck-flexgen-08 { + clk_dsi_txbyte: txbyteclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <100000000>; + clock-frequency = <0>; }; - ck_flexgen_51: ck-flexgen-51 { + clk_rcbsec: clk-rcbsec { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_ls_mcu: ck-icn-ls-mcu { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_p_vdec: ck-icn-p-vdec { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_p_venc: ck-icn-p-venc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; + clock-frequency = <64000000>; }; }; @@ -135,7 +119,7 @@ compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; interrupts = ; - clocks = <&ck_flexgen_08>; + clocks = <&rcc CK_KER_USART2>; access-controllers = <&rifsc 32>; status = "disabled"; }; @@ -145,8 +129,9 @@ arm,primecell-periphid = <0x00353180>; reg = <0x48220000 0x400>, <0x44230400 0x8>; interrupts = ; - clocks = <&ck_flexgen_51>; + clocks = <&rcc CK_KER_SDMMC1 >; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; @@ -171,6 +156,93 @@ }; }; + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; @@ -189,7 +261,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; st,bank-name = "GPIOA"; status = "disabled"; }; @@ -200,7 +272,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x10000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; st,bank-name = "GPIOB"; status = "disabled"; }; @@ -211,7 +283,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x20000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; st,bank-name = "GPIOC"; status = "disabled"; }; @@ -222,7 +294,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x30000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; st,bank-name = "GPIOD"; status = "disabled"; }; @@ -233,7 +305,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x40000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; st,bank-name = "GPIOE"; status = "disabled"; }; @@ -244,7 +316,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x50000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; st,bank-name = "GPIOF"; status = "disabled"; }; @@ -255,7 +327,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x60000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; st,bank-name = "GPIOG"; status = "disabled"; }; @@ -266,7 +338,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x70000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; st,bank-name = "GPIOH"; status = "disabled"; }; @@ -277,7 +349,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x80000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; st,bank-name = "GPIOI"; status = "disabled"; }; @@ -288,7 +360,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x90000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; st,bank-name = "GPIOJ"; status = "disabled"; }; @@ -299,7 +371,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0xa0000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; st,bank-name = "GPIOK"; status = "disabled"; }; @@ -318,7 +390,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 570c5dd0b2c3..f689b47c5010 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -10,7 +10,7 @@ compatible = "st,stm32mp25-vdec"; reg = <0x480d0000 0x3c8>; interrupts = ; - clocks = <&ck_icn_p_vdec>; + clocks = <&rcc CK_BUS_VDEC>; access-controllers = <&rifsc 89>; }; @@ -19,7 +19,7 @@ compatible = "st,stm32mp25-venc"; reg = <0x480e0000 0x800>; interrupts = ; - clocks = <&ck_icn_ls_mcu>; + clocks = <&rcc CK_BUS_VENC>; access-controllers = <&rifsc 90>; }; }; \ No newline at end of file -- cgit v1.2.3 From 9fd205d487989a58028ea1089c16bba589b17cfb Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 15 Dec 2023 18:06:11 +0100 Subject: arm64: dts: st: add all 8 i2c nodes on stm32mp251 Add the 8 nodes for all i2c instances available on the stm32mp251. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 104 +++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 193808919e83..b55839bc2bfc 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -124,6 +124,110 @@ status = "disabled"; }; + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c3: i2c@40140000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40140000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C3>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 43>; + status = "disabled"; + }; + + i2c4: i2c@40150000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40150000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C4>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 44>; + status = "disabled"; + }; + + i2c5: i2c@40160000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40160000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C5>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 45>; + status = "disabled"; + }; + + i2c6: i2c@40170000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40170000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C6>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 46>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 48>; + status = "disabled"; + }; + sdmmc1: mmc@48220000 { compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00353180>; -- cgit v1.2.3 From a3d208bf04c45ea64b1fd72fd643bb83745d7883 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 15 Dec 2023 18:06:12 +0100 Subject: arm64: dts: st: add i2c2/i2c8 pins for stm32mp25 Add the i2c2 and i2c8 pins used on STM32MP257F-EV1 board. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 66791a974f8f..4194807606ce 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,23 @@ #include &pinctrl { + i2c2_pins_a: i2c2-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_a: i2c2-sleep-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -90,3 +107,22 @@ }; }; }; + +&pinctrl_z { + i2c8_pins_a: i2c8-0 { + pins { + pinmux = , /* I2C8_SCL */ + ; /* I2C8_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c8_sleep_pins_a: i2c8-sleep-0 { + pins { + pinmux = , /* I2C8_SCL */ + ; /* I2C8_SDA */ + }; + }; +}; -- cgit v1.2.3 From 004434bccfcb29e218044d96d8fe6ce8e9077796 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 15 Dec 2023 18:06:13 +0100 Subject: arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1 Add properties for i2c2 and i2c8 available on the stm32mp257f-ev1. i2c2 is enabled since several devices are attached to it while i2c8 is kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index b2d3afb15758..0ea8e69bfb3d 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -55,6 +55,26 @@ status = "okay"; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <13>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <57>; + i2c-scl-falling-time-ns = <7>; + clock-frequency = <400000>; + status = "disabled"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; -- cgit v1.2.3 From f08b42c11955653c48cfcc7886a15166bea8be46 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 25 Apr 2024 10:10:50 +0200 Subject: arm64: dts: st: add all 8 spi nodes on stm32mp251 Add the 8 nodes for all spi instances available on the stm32mp251. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 96 ++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index b55839bc2bfc..64240f94d05d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -115,6 +115,30 @@ #access-controller-cells = <1>; ranges; + spi2: spi@400b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; @@ -215,6 +239,78 @@ status = "disabled"; }; + spi1: spi@40230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + spi6: spi@40350000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40350000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI6>; + resets = <&rcc SPI6_R>; + access-controllers = <&rifsc 27>; + status = "disabled"; + }; + + spi7: spi@40360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40360000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI7>; + resets = <&rcc SPI7_R>; + access-controllers = <&rifsc 28>; + status = "disabled"; + }; + + spi8: spi@46020000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + i2c8: i2c@46040000 { compatible = "st,stm32mp25-i2c"; reg = <0x46040000 0x400>; -- cgit v1.2.3 From 1d1d4072138d193b3923f9e4c9181650a60c87ac Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 18 Dec 2023 16:57:17 +0100 Subject: arm64: dts: st: add spi3/spi8 pins for stm32mp25 Add the spi3 and spi8 pins used on STM32MP257F-EV1 board. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 4194807606ce..7a82896dcbf6 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -77,6 +77,28 @@ }; }; + spi3_pins_a: spi3-0 { + pins1 { + pinmux = , /* SPI3_SCK */ + ; /* SPI3_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins1 { + pinmux = , /* SPI3_SCK */ + , /* SPI3_MOSI */ + ; /* SPI3_MISO */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = ; /* USART2_TX */ @@ -126,3 +148,27 @@ }; }; }; + +&pinctrl_z { + spi8_pins_a: spi8-0 { + pins1 { + pinmux = , /* SPI8_SCK */ + ; /* SPI8_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI8_MISO */ + bias-disable; + }; + }; + + spi8_sleep_pins_a: spi8-sleep-0 { + pins1 { + pinmux = , /* SPI8_SCK */ + , /* SPI8_MOSI */ + ; /* SPI8_MISO */ + }; + }; +}; -- cgit v1.2.3 From bc99659688ba39def8fd43758e9ea88a3c3c9817 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 18 Dec 2023 16:57:18 +0100 Subject: arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1 Add properties for spi3 and spi8 available on the stm32mp257f-ev1. Both are kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 0ea8e69bfb3d..27b7360e5dba 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -88,6 +88,20 @@ status = "okay"; }; +&spi3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + status = "disabled"; +}; + +&spi8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi8_pins_a>; + pinctrl-1 = <&spi8_sleep_pins_a>; + status = "disabled"; +}; + &usart2 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart2_pins_a>; -- cgit v1.2.3 From 36cf0d86d760f30b59bc61ffc72c58503c353a17 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 24 Apr 2024 18:53:44 +0200 Subject: arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25 Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP251 is a single core Cortex A35, STM32MP253 is a dual core CA35. Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++---- arch/arm64/boot/dts/st/stm32mp253.dtsi | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 64240f94d05d..4b48e4ed2d28 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -93,10 +93,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&intc>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; always-on; }; diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index af48e82efe8a..029f88981961 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -20,4 +20,11 @@ ; interrupt-affinity = <&cpu0>, <&cpu1>; }; + + timer { + interrupts = , + , + , + ; + }; }; -- cgit v1.2.3