From 54af0ceb75958a8b7e62138646cfa6c114e71a77 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Feb 2023 15:38:38 +0200 Subject: arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Add device nodes required to enable GPU on the SM8350 platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio [bjorn: Workaround for lacking RPMH_REGULATOR_LEVEL_LOW_SVS_L1 constant] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209133839.762631-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 178 +++++++++++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) (limited to 'arch/arm64/boot/dts/qcom/sm8350.dtsi') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 742e9dd17084..1c97e28da6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1765,6 +1766,183 @@ #hwlock-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-660.1", "qcom,adreno"; + + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + /* note: downstream checks gpu binning for 670 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-level = ; + }; + + opp-778000000 { + opp-hz = /bits/ 64 <778000000>; + opp-level = ; + }; + + opp-738000000 { + opp-hz = /bits/ 64 <738000000>; + opp-level = ; + }; + + opp-676000000 { + opp-hz = /bits/ 64 <676000000>; + opp-level = ; + }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + opp-level = ; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-level = ; + }; + + opp-491000000 { + opp-hz = /bits/ 64 <491000000>; + opp-level = ; + }; + + opp-443000000 { + opp-hz = /bits/ 64 <443000000>; + opp-level = ; + }; + + opp-379000000 { + opp-hz = /bits/ 64 <379000000>; + opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; + + reg = <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "bus", + "iface", + "ahb", + "hlos1_vote_gpu_smmu", + "cx_gmu", + "hub_cx_int", + "hub_aon"; + + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,sm8350-lpass-ag-noc"; reg = <0 0x03c40000 0 0xf080>; -- cgit v1.2.3