From 6769b93c082afb7241708685f1c23cbaf5bf00eb Mon Sep 17 00:00:00 2001 From: Yingjoe Chen Date: Fri, 1 May 2015 14:49:31 +0800 Subject: arm64: dts: mt8173: Fixup pinctrl nodes The 8173 pinctrl node doesn't follow dts convention. Fix them. Also add a comment to explain pinctrl register usage to make it more clear. Signed-off-by: Yingjoe Chen Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot/dts/mediatek') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 924fdb6673ff..45951964965a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -106,14 +106,13 @@ compatible = "simple-bus"; ranges; - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@0x10005000 { + /* + * Pinctrl access register at 0x10005000 through regmap. + * Register 0x1000b000 is used by EINT. + */ + pio: pinctrl@10005000 { compatible = "mediatek,mt8173-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; + reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; pins-are-numbered; gpio-controller; @@ -121,8 +120,13 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = , - , - ; + , + ; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; }; sysirq: intpol-controller@10200620 { -- cgit v1.2.3 From e881ad1bc6e46fc933fef77cfe587625e30478e9 Mon Sep 17 00:00:00 2001 From: Daniel Kurtz Date: Wed, 20 May 2015 18:20:07 +0800 Subject: arm64: dts: mt8173: fix some indentation Fix indentation nits to make mt8173.dtsi more consistent. Signed-off-by: Eddie Huang Signed-off-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'arch/arm64/boot/dts/mediatek') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 45951964965a..27237a1c1a87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -91,13 +91,13 @@ compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; soc { @@ -131,7 +131,7 @@ sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8173-sysirq", - "mediatek,mt6577-sysirq"; + "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; @@ -153,7 +153,7 @@ uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; clocks = <&uart_clk>; @@ -162,7 +162,7 @@ uart1: serial@11003000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; clocks = <&uart_clk>; @@ -171,7 +171,7 @@ uart2: serial@11004000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; clocks = <&uart_clk>; @@ -180,13 +180,12 @@ uart3: serial@11005000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; clocks = <&uart_clk>; status = "disabled"; }; }; - }; -- cgit v1.2.3