From 91f1be92eb511c549b1e2e723bdeb13e7cb33a99 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 2 Jan 2018 15:55:58 +0100 Subject: arm64: dts: marvell: replace cpm by cp0, cps by cp1 In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1. This commit is the result of: sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/* So it is a purely mechaninal change. Signed-off-by: Thomas Petazzoni Suggested-by: Hanna Hawa Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot/dts/marvell/armada-70x0.dtsi') diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index 9917cff3dae6..f63b4fbd642b 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -46,17 +46,17 @@ / { aliases { - gpio1 = &cpm_gpio1; - gpio2 = &cpm_gpio2; - spi1 = &cpm_spi0; - spi2 = &cpm_spi1; + gpio1 = &cp0_gpio1; + gpio2 = &cp0_gpio2; + spi1 = &cp0_spi0; + spi2 = &cp0_spi1; }; }; /* * Instantiate the CP110 */ -#define CP110_NAME cpm +#define CP110_NAME cp0 #define CP110_BASE f2000000 #define CP110_PCIE_IO_BASE 0xf9000000 #define CP110_PCIE_MEM_BASE 0xf6000000 @@ -74,16 +74,16 @@ #undef CP110_PCIE1_BASE #undef CP110_PCIE2_BASE -&cpm_gpio1 { +&cp0_gpio1 { status = "okay"; }; -&cpm_gpio2 { +&cp0_gpio2 { status = "okay"; }; -&cpm_syscon0 { - cpm_pinctrl: pinctrl { +&cp0_syscon0 { + cp0_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; nand_pins: nand-pins { -- cgit v1.2.3