From a004ee350177ece3c059831ea49293d62aea7ca6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 22 Nov 2016 23:58:29 +0800 Subject: arm64: dts: allwinner: add USB1-related nodes of Allwinner A64 Allwinner A64 have two HCI USB controllers, a OTG controller and a USB PHY device which have two ports. One of the port is wired to both a HCI USB controller and the OTG controller, which is currently not supported. The another one is only wired to a HCI controller, and the device node of OHCI/EHCI controller of the port can be added now. Also the A64 USB PHY device node is also added for the HCI controllers to work. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index e0dcab8eb035..692611e86c98 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -42,8 +42,10 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include +#include / { interrupt-parent = <&gic>; @@ -120,6 +122,50 @@ #size-cells = <1>; ranges; + usbphy: phy@01c19400 { + compatible = "allwinner,sun50i-a64-usb-phy"; + reg = <0x01c19400 0x14>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", + "pmu1"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@01c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; -- cgit v1.2.3 From 972a3ecdf27f3ebdd1ce0dccd1b548ef3c04b8ed Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 23 Nov 2016 00:59:01 +0800 Subject: arm64: dts: add MUSB node to Allwinner A64 dtsi Allwinner A64 SoC has a MUSB controller like the one in A33, so add a node for it, just use the compatible of A33 MUSB. Host mode is tested to work properly on Pine64 and will be added into the device tree of Pine64 in next patch. Peripheral mode is also tested on Pine64, by changing dr_mode property of usb_otg node and use a non-standard USB Type-A to Type-A cable. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 692611e86c98..99b6bb1e141c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -122,6 +122,19 @@ #size-cells = <1>; ranges; + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun50i-a64-usb-phy"; reg = <0x01c19400 0x14>, -- cgit v1.2.3 From 4f9758302ccaf753cd4ba6a5eb740392a4d24773 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 24 Jan 2017 10:32:29 +0800 Subject: arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm64/boot/dts/allwinner/*.dts? Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 99b6bb1e141c..6ec831177b22 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -44,7 +44,6 @@ #include #include -#include #include / { -- cgit v1.2.3 From f3dff3478a8a7b09f9a92023955a151584658893 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 6 Oct 2016 02:25:22 +0100 Subject: arm64: allwinner: a64: Add MMC nodes The A64 has 3 MMC controllers, one of them being especially targeted to eMMC. Among other things, it has a data strobe signal and a 8 bits data width. The two other are more usual controllers that will have a 4 bits width at most and no data strobe signal, which limits it to more usual SD or MMC peripherals. Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard Tested-by: Florian Vaussard Acked-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 6ec831177b22..d06a4dc93e93 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -121,6 +121,45 @@ #size-cells = <1>; ranges; + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun50i-a64-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + usb_otg: usb@01c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; -- cgit v1.2.3 From a3e8f4926248b3c12933aacec4432e9b6de004bb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 9 Jan 2017 16:39:15 +0100 Subject: arm64: allwinner: a64: Add MMC pinctrl nodes The A64 only has a single set of pins for each MMC controller. Since we already have boards that require all of them, let's add them to the DTSI. Reviewed-by: Andre Przywara Signed-off-by: Maxime Ripard Tested-by: Florian Vaussard Acked-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index d06a4dc93e93..acc7071a7540 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -243,6 +243,31 @@ function = "i2c1"; }; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC1", "PC5", "PC6", "PC8", "PC9", + "PC10","PC11", "PC12", "PC13", + "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + uart0_pins_a: uart0@0 { pins = "PB8", "PB9"; function = "uart0"; -- cgit v1.2.3 From 22be992faea70b95bcb48e2d5efa41733fcfeab7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 9 Jan 2017 15:53:59 +0100 Subject: arm64: allwinner: a64: Increase the MMC max frequency The eMMC controller seem to have a maximum frequency of 200MHz, while the regular MMC controllers are capped at 150MHz. Since older SoCs cannot go that high, we cannot change the default maximum frequency, but fortunately for us we have a property for that in the DT. This also has the side effect of allowing to use the MMC HS200 and SD SDR104 modes for the boards that support it (with either 1.2v or 1.8v IOs). Signed-off-by: Maxime Ripard Tested-by: Florian Vaussard Acked-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index acc7071a7540..9ae4f589fb1c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -129,6 +129,7 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = ; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -142,6 +143,7 @@ resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = ; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -155,6 +157,7 @@ resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = ; + max-frequency = <200000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From e7ba733d32cc9487b62b07219ad911c77764a681 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 10 Jan 2017 01:22:32 +0000 Subject: arm64: allwinner: a64: add UART1 pin nodes On many boards UART1 connects to a Bluetooth chip, so add the pinctrl nodes for the only pins providing access to that UART. That includes those pins for hardware flow control (RTS/CTS). Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 9ae4f589fb1c..1c64ea2d23f9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -275,6 +275,16 @@ pins = "PB8", "PB9"; function = "uart0"; }; + + uart1_pins: uart1_pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1_rts_cts_pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; }; uart0: serial@1c28000 { -- cgit v1.2.3