From a09e2b21cab92e98728c16f0e6f456f723dadf8b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 7 Feb 2011 10:51:04 +0900 Subject: ARM: SAMSUNG: Ensure struct sys_device is declared in plat/pm.h Previously we were relying on it being pulled in by other headers for the prototype of s3c24xx_irq_suspend() and s3c24xx_irq_resume(). Signed-off-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/include/plat/pm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index d9025e377675..30518cc9a67c 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -17,6 +17,8 @@ #include +struct sys_device; + #ifdef CONFIG_PM extern __init int s3c_pm_init(void); -- cgit v1.2.3 From 9613afc36a3114b776d7b09877060062cd3e4d89 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Fri, 18 Feb 2011 17:36:06 +0900 Subject: ARM: SAMSUNG: Drop exporting s3c24xx_ts_set_platdata s3c24xx_ts_set_platdata is annotated __init and not used by any module, thus don't export it. This patch fixes below warning: WARNING: arch/arm/plat-samsung/built-in.o(__ksymtab+0x90): Section mismatch in reference from the variable __ksymtab_s3c24xx_ts_set_platdata to the function .init.text:s3c24xx_ts_set_platdata() The symbol s3c24xx_ts_set_platdata is exported and annotated __init Fix this by removing the __init annotation of s3c24xx_ts_set_platdata or drop the export. Signed-off-by: Axel Lin Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/dev-ts.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c index 236ef8427d7d..3e4bd8147bf4 100644 --- a/arch/arm/plat-samsung/dev-ts.c +++ b/arch/arm/plat-samsung/dev-ts.c @@ -58,4 +58,3 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) s3c_device_ts.dev.platform_data = npd; } -EXPORT_SYMBOL(s3c24xx_ts_set_platdata); -- cgit v1.2.3 From 3db3ae5eb94eb8579991174fe66999261b66018d Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Mon, 14 Feb 2011 16:22:36 +0900 Subject: ARM: EXYNOS4: Update device support This patch updates device support of EXYNOS4 according to the change of ARCH name, EXYNOS4. Cc: Ben Dooks Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos4/dev-audio.c | 367 +++++++++++++++++++++++++++++ arch/arm/mach-exynos4/dev-pd.c | 139 +++++++++++ arch/arm/mach-exynos4/dev-sysmmu.c | 189 +++++++++++++++ arch/arm/mach-exynos4/setup-i2c1.c | 23 ++ arch/arm/mach-exynos4/setup-i2c2.c | 23 ++ arch/arm/mach-exynos4/setup-i2c3.c | 23 ++ arch/arm/mach-exynos4/setup-i2c4.c | 23 ++ arch/arm/mach-exynos4/setup-i2c5.c | 23 ++ arch/arm/mach-exynos4/setup-i2c6.c | 23 ++ arch/arm/mach-exynos4/setup-i2c7.c | 23 ++ arch/arm/mach-exynos4/setup-sdhci-gpio.c | 152 ++++++++++++ arch/arm/mach-exynos4/setup-sdhci.c | 69 ++++++ arch/arm/mach-s5pv310/dev-audio.c | 364 ---------------------------- arch/arm/mach-s5pv310/dev-pd.c | 139 ----------- arch/arm/mach-s5pv310/dev-sysmmu.c | 187 --------------- arch/arm/mach-s5pv310/setup-i2c1.c | 23 -- arch/arm/mach-s5pv310/setup-i2c2.c | 23 -- arch/arm/mach-s5pv310/setup-i2c3.c | 23 -- arch/arm/mach-s5pv310/setup-i2c4.c | 23 -- arch/arm/mach-s5pv310/setup-i2c5.c | 23 -- arch/arm/mach-s5pv310/setup-i2c6.c | 23 -- arch/arm/mach-s5pv310/setup-i2c7.c | 23 -- arch/arm/mach-s5pv310/setup-sdhci-gpio.c | 152 ------------ arch/arm/mach-s5pv310/setup-sdhci.c | 69 ------ arch/arm/plat-samsung/include/plat/devs.h | 23 +- arch/arm/plat-samsung/include/plat/pd.h | 4 +- arch/arm/plat-samsung/include/plat/sdhci.h | 63 ++--- 27 files changed, 1125 insertions(+), 1114 deletions(-) create mode 100644 arch/arm/mach-exynos4/dev-audio.c create mode 100644 arch/arm/mach-exynos4/dev-pd.c create mode 100644 arch/arm/mach-exynos4/dev-sysmmu.c create mode 100644 arch/arm/mach-exynos4/setup-i2c1.c create mode 100644 arch/arm/mach-exynos4/setup-i2c2.c create mode 100644 arch/arm/mach-exynos4/setup-i2c3.c create mode 100644 arch/arm/mach-exynos4/setup-i2c4.c create mode 100644 arch/arm/mach-exynos4/setup-i2c5.c create mode 100644 arch/arm/mach-exynos4/setup-i2c6.c create mode 100644 arch/arm/mach-exynos4/setup-i2c7.c create mode 100644 arch/arm/mach-exynos4/setup-sdhci-gpio.c create mode 100644 arch/arm/mach-exynos4/setup-sdhci.c delete mode 100644 arch/arm/mach-s5pv310/dev-audio.c delete mode 100644 arch/arm/mach-s5pv310/dev-pd.c delete mode 100644 arch/arm/mach-s5pv310/dev-sysmmu.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c1.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c2.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c3.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c4.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c5.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c6.c delete mode 100644 arch/arm/mach-s5pv310/setup-i2c7.c delete mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c delete mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c new file mode 100644 index 000000000000..1eed5f9f7bd3 --- /dev/null +++ b/arch/arm/mach-exynos4/dev-audio.c @@ -0,0 +1,367 @@ +/* linux/arch/arm/mach-exynos4/dev-audio.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +static const char *rclksrc[] = { + [0] = "busclk", + [1] = "i2sclk", +}; + +static int exynos4_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2)); + break; + case 1: + s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2)); + break; + case 2: + s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4)); + break; + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata i2sv5_pdata = { + .cfg_gpio = exynos4_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI + | QUIRK_NEED_RSTCLR, + .src_clk = rclksrc, + }, + }, +}; + +static struct resource exynos4_i2s0_resource[] = { + [0] = { + .start = EXYNOS4_PA_I2S0, + .end = EXYNOS4_PA_I2S0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_I2S0S_TX, + .end = DMACH_I2S0S_TX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_i2s0 = { + .name = "samsung-i2s", + .id = 0, + .num_resources = ARRAY_SIZE(exynos4_i2s0_resource), + .resource = exynos4_i2s0_resource, + .dev = { + .platform_data = &i2sv5_pdata, + }, +}; + +static const char *rclksrc_v3[] = { + [0] = "sclk_i2s", + [1] = "no_such_clock", +}; + +static struct s3c_audio_pdata i2sv3_pdata = { + .cfg_gpio = exynos4_cfg_i2s, + .type = { + .i2s = { + .quirks = QUIRK_NO_MUXPSR, + .src_clk = rclksrc_v3, + }, + }, +}; + +static struct resource exynos4_i2s1_resource[] = { + [0] = { + .start = EXYNOS4_PA_I2S1, + .end = EXYNOS4_PA_I2S1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_i2s1 = { + .name = "samsung-i2s", + .id = 1, + .num_resources = ARRAY_SIZE(exynos4_i2s1_resource), + .resource = exynos4_i2s1_resource, + .dev = { + .platform_data = &i2sv3_pdata, + }, +}; + +static struct resource exynos4_i2s2_resource[] = { + [0] = { + .start = EXYNOS4_PA_I2S2, + .end = EXYNOS4_PA_I2S2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_i2s2 = { + .name = "samsung-i2s", + .id = 2, + .num_resources = ARRAY_SIZE(exynos4_i2s2_resource), + .resource = exynos4_i2s2_resource, + .dev = { + .platform_data = &i2sv3_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int exynos4_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3)); + break; + case 1: + s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3)); + break; + case 2: + s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3)); + break; + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = exynos4_pcm_cfg_gpio, +}; + +static struct resource exynos4_pcm0_resource[] = { + [0] = { + .start = EXYNOS4_PA_PCM0, + .end = EXYNOS4_PA_PCM0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_pcm0 = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(exynos4_pcm0_resource), + .resource = exynos4_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource exynos4_pcm1_resource[] = { + [0] = { + .start = EXYNOS4_PA_PCM1, + .end = EXYNOS4_PA_PCM1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM1_TX, + .end = DMACH_PCM1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM1_RX, + .end = DMACH_PCM1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_pcm1 = { + .name = "samsung-pcm", + .id = 1, + .num_resources = ARRAY_SIZE(exynos4_pcm1_resource), + .resource = exynos4_pcm1_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource exynos4_pcm2_resource[] = { + [0] = { + .start = EXYNOS4_PA_PCM2, + .end = EXYNOS4_PA_PCM2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM2_TX, + .end = DMACH_PCM2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM2_RX, + .end = DMACH_PCM2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device exynos4_device_pcm2 = { + .name = "samsung-pcm", + .id = 2, + .num_resources = ARRAY_SIZE(exynos4_pcm2_resource), + .resource = exynos4_pcm2_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +/* AC97 Controller platform devices */ + +static int exynos4_ac97_cfg_gpio(struct platform_device *pdev) +{ + return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4)); +} + +static struct resource exynos4_ac97_resource[] = { + [0] = { + .start = EXYNOS4_PA_AC97, + .end = EXYNOS4_PA_AC97 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_AC97_PCMOUT, + .end = DMACH_AC97_PCMOUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_AC97_PCMIN, + .end = DMACH_AC97_PCMIN, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_AC97_MICIN, + .end = DMACH_AC97_MICIN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = IRQ_AC97, + .end = IRQ_AC97, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_audio_pdata s3c_ac97_pdata = { + .cfg_gpio = exynos4_ac97_cfg_gpio, +}; + +static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32); + +struct platform_device exynos4_device_ac97 = { + .name = "samsung-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_ac97_resource), + .resource = exynos4_ac97_resource, + .dev = { + .platform_data = &s3c_ac97_pdata, + .dma_mask = &exynos4_ac97_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* S/PDIF Controller platform_device */ + +static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3)); + + return 0; +} + +static struct resource exynos4_spdif_resource[] = { + [0] = { + .start = EXYNOS4_PA_SPDIF, + .end = EXYNOS4_PA_SPDIF + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPDIF, + .end = DMACH_SPDIF, + .flags = IORESOURCE_DMA, + }, +}; + +static struct s3c_audio_pdata samsung_spdif_pdata = { + .cfg_gpio = exynos4_spdif_cfg_gpio, +}; + +static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32); + +struct platform_device exynos4_device_spdif = { + .name = "samsung-spdif", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_spdif_resource), + .resource = exynos4_spdif_resource, + .dev = { + .platform_data = &samsung_spdif_pdata, + .dma_mask = &exynos4_spdif_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-exynos4/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c new file mode 100644 index 000000000000..3273f25d6a75 --- /dev/null +++ b/arch/arm/mach-exynos4/dev-pd.c @@ -0,0 +1,139 @@ +/* linux/arch/arm/mach-exynos4/dev-pd.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Power Domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include + +#include + +static int exynos4_pd_enable(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + u32 timeout; + + __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base); + + /* Wait max 1ms */ + timeout = 10; + while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) + != S5P_INT_LOCAL_PWR_EN) { + if (timeout == 0) { + printk(KERN_ERR "Power domain %s enable failed.\n", + dev_name(dev)); + return -ETIMEDOUT; + } + timeout--; + udelay(100); + } + + return 0; +} + +static int exynos4_pd_disable(struct device *dev) +{ + struct samsung_pd_info *pdata = dev->platform_data; + u32 timeout; + + __raw_writel(0, pdata->base); + + /* Wait max 1ms */ + timeout = 10; + while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) { + if (timeout == 0) { + printk(KERN_ERR "Power domain %s disable failed.\n", + dev_name(dev)); + return -ETIMEDOUT; + } + timeout--; + udelay(100); + } + + return 0; +} + +struct platform_device exynos4_device_pd[] = { + { + .name = "samsung-pd", + .id = 0, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_MFC_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 1, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_G3D_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 2, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_LCD0_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 3, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_LCD1_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 4, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_TV_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 5, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_CAM_CONF, + }, + }, + }, { + .name = "samsung-pd", + .id = 6, + .dev = { + .platform_data = &(struct samsung_pd_info) { + .enable = exynos4_pd_enable, + .disable = exynos4_pd_disable, + .base = S5P_PMU_GPS_CONF, + }, + }, + }, +}; diff --git a/arch/arm/mach-exynos4/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c new file mode 100644 index 000000000000..a10790a614ec --- /dev/null +++ b/arch/arm/mach-exynos4/dev-sysmmu.c @@ -0,0 +1,189 @@ +/* linux/arch/arm/mach-exynos4/dev-sysmmu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - System MMU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +static struct resource exynos4_sysmmu_resource[] = { + [0] = { + .start = EXYNOS4_PA_SYSMMU_MDMA, + .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SYSMMU_MDMA0_0, + .end = IRQ_SYSMMU_MDMA0_0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = EXYNOS4_PA_SYSMMU_SSS, + .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = IRQ_SYSMMU_SSS_0, + .end = IRQ_SYSMMU_SSS_0, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = EXYNOS4_PA_SYSMMU_FIMC0, + .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = IRQ_SYSMMU_FIMC0_0, + .end = IRQ_SYSMMU_FIMC0_0, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = EXYNOS4_PA_SYSMMU_FIMC1, + .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = IRQ_SYSMMU_FIMC1_0, + .end = IRQ_SYSMMU_FIMC1_0, + .flags = IORESOURCE_IRQ, + }, + [8] = { + .start = EXYNOS4_PA_SYSMMU_FIMC2, + .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = IRQ_SYSMMU_FIMC2_0, + .end = IRQ_SYSMMU_FIMC2_0, + .flags = IORESOURCE_IRQ, + }, + [10] = { + .start = EXYNOS4_PA_SYSMMU_FIMC3, + .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [11] = { + .start = IRQ_SYSMMU_FIMC3_0, + .end = IRQ_SYSMMU_FIMC3_0, + .flags = IORESOURCE_IRQ, + }, + [12] = { + .start = EXYNOS4_PA_SYSMMU_JPEG, + .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [13] = { + .start = IRQ_SYSMMU_JPEG_0, + .end = IRQ_SYSMMU_JPEG_0, + .flags = IORESOURCE_IRQ, + }, + [14] = { + .start = EXYNOS4_PA_SYSMMU_FIMD0, + .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [15] = { + .start = IRQ_SYSMMU_LCD0_M0_0, + .end = IRQ_SYSMMU_LCD0_M0_0, + .flags = IORESOURCE_IRQ, + }, + [16] = { + .start = EXYNOS4_PA_SYSMMU_FIMD1, + .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [17] = { + .start = IRQ_SYSMMU_LCD1_M1_0, + .end = IRQ_SYSMMU_LCD1_M1_0, + .flags = IORESOURCE_IRQ, + }, + [18] = { + .start = EXYNOS4_PA_SYSMMU_PCIe, + .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [19] = { + .start = IRQ_SYSMMU_PCIE_0, + .end = IRQ_SYSMMU_PCIE_0, + .flags = IORESOURCE_IRQ, + }, + [20] = { + .start = EXYNOS4_PA_SYSMMU_G2D, + .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [21] = { + .start = IRQ_SYSMMU_2D_0, + .end = IRQ_SYSMMU_2D_0, + .flags = IORESOURCE_IRQ, + }, + [22] = { + .start = EXYNOS4_PA_SYSMMU_ROTATOR, + .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [23] = { + .start = IRQ_SYSMMU_ROTATOR_0, + .end = IRQ_SYSMMU_ROTATOR_0, + .flags = IORESOURCE_IRQ, + }, + [24] = { + .start = EXYNOS4_PA_SYSMMU_MDMA2, + .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [25] = { + .start = IRQ_SYSMMU_MDMA1_0, + .end = IRQ_SYSMMU_MDMA1_0, + .flags = IORESOURCE_IRQ, + }, + [26] = { + .start = EXYNOS4_PA_SYSMMU_TV, + .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [27] = { + .start = IRQ_SYSMMU_TV_M0_0, + .end = IRQ_SYSMMU_TV_M0_0, + .flags = IORESOURCE_IRQ, + }, + [28] = { + .start = EXYNOS4_PA_SYSMMU_MFC_L, + .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [29] = { + .start = IRQ_SYSMMU_MFC_M0_0, + .end = IRQ_SYSMMU_MFC_M0_0, + .flags = IORESOURCE_IRQ, + }, + [30] = { + .start = EXYNOS4_PA_SYSMMU_MFC_R, + .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [31] = { + .start = IRQ_SYSMMU_MFC_M1_0, + .end = IRQ_SYSMMU_MFC_M1_0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device exynos4_device_sysmmu = { + .name = "s5p-sysmmu", + .id = 32, + .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource), + .resource = exynos4_sysmmu_resource, +}; + +EXPORT_SYMBOL(exynos4_device_sysmmu); diff --git a/arch/arm/mach-exynos4/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c new file mode 100644 index 000000000000..fd7235a43f6e --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c1.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c1.c + * + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * I2C1 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c new file mode 100644 index 000000000000..2694b19e8b37 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c2.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c2.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * + * I2C2 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c2_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c new file mode 100644 index 000000000000..379bd306993f --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c3.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c3.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C3 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c3_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c new file mode 100644 index 000000000000..9f3c04855b76 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c4.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c4.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C4 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c4_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c new file mode 100644 index 000000000000..77e1a1e57c76 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c5.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c5.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C5 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c5_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c new file mode 100644 index 000000000000..284d12b7af0e --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c6.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c6.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C6 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c6_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, + S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c new file mode 100644 index 000000000000..b7611ee359a2 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-i2c7.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-exynos4/setup-i2c7.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C7 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c7_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c new file mode 100644 index 000000000000..1b3d3a2de95c --- /dev/null +++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c @@ -0,0 +1,152 @@ +/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK0[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + switch (width) { + case 8: + for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { + /* Data pin GPK1[3:6] to special-funtion 3 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + case 4: + for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { + /* Data pin GPK0[3:6] to special-funtion 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + default: + break; + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK1[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { + /* Data pin GPK1[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK2[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + switch (width) { + case 8: + for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { + /* Data pin GPK3[3:6] to special-function 3 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + case 4: + for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) { + /* Data pin GPK2[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + default: + break; + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK3[0:1] pins to special-function 2 */ + for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { + /* Data pin GPK3[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c new file mode 100644 index 000000000000..85f9433d4836 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-sdhci.c @@ -0,0 +1,69 @@ +/* linux/arch/arm/mach-exynos4/setup-sdhci.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *exynos4_hsmmc_clksrcs[4] = { + [0] = NULL, + [1] = NULL, + [2] = "sclk_mmc", /* mmc_bus */ + [3] = NULL, +}; + +void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, + struct mmc_ios *ios, struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + /* don't need to alter anything acording to card-type */ + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + + /* select base clock source to HCLK */ + + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + + /* + * clear async mode, enable conflict mask, rx feedback ctrl, SD + * clk hold and no use debounce count + */ + + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + /* Tx and Rx feedback clock delay control */ + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-s5pv310/dev-audio.c deleted file mode 100644 index a1964242f0fa..000000000000 --- a/arch/arm/mach-s5pv310/dev-audio.c +++ /dev/null @@ -1,364 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/dev-audio.c - * - * Copyright (c) 2010 Samsung Electronics Co. Ltd - * Jaswinder Singh - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include -#include - -#include -#include -#include - -static const char *rclksrc[] = { - [0] = "busclk", - [1] = "i2sclk", -}; - -static int s5pv310_cfg_i2s(struct platform_device *pdev) -{ - /* configure GPIO for i2s port */ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2)); - break; - case 1: - s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2)); - break; - case 2: - s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4)); - break; - default: - printk(KERN_ERR "Invalid Device %d\n", pdev->id); - return -EINVAL; - } - - return 0; -} - -static struct s3c_audio_pdata i2sv5_pdata = { - .cfg_gpio = s5pv310_cfg_i2s, - .type = { - .i2s = { - .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI - | QUIRK_NEED_RSTCLR, - .src_clk = rclksrc, - }, - }, -}; - -static struct resource s5pv310_i2s0_resource[] = { - [0] = { - .start = S5PV310_PA_I2S0, - .end = S5PV310_PA_I2S0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S0_TX, - .end = DMACH_I2S0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S0_RX, - .end = DMACH_I2S0_RX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_I2S0S_TX, - .end = DMACH_I2S0S_TX, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s5pv310_device_i2s0 = { - .name = "samsung-i2s", - .id = 0, - .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource), - .resource = s5pv310_i2s0_resource, - .dev = { - .platform_data = &i2sv5_pdata, - }, -}; - -static const char *rclksrc_v3[] = { - [0] = "sclk_i2s", - [1] = "no_such_clock", -}; - -static struct s3c_audio_pdata i2sv3_pdata = { - .cfg_gpio = s5pv310_cfg_i2s, - .type = { - .i2s = { - .quirks = QUIRK_NO_MUXPSR, - .src_clk = rclksrc_v3, - }, - }, -}; - -static struct resource s5pv310_i2s1_resource[] = { - [0] = { - .start = S5PV310_PA_I2S1, - .end = S5PV310_PA_I2S1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S1_TX, - .end = DMACH_I2S1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S1_RX, - .end = DMACH_I2S1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s5pv310_device_i2s1 = { - .name = "samsung-i2s", - .id = 1, - .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource), - .resource = s5pv310_i2s1_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; - -static struct resource s5pv310_i2s2_resource[] = { - [0] = { - .start = S5PV310_PA_I2S2, - .end = S5PV310_PA_I2S2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_I2S2_TX, - .end = DMACH_I2S2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_I2S2_RX, - .end = DMACH_I2S2_RX, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s5pv310_device_i2s2 = { - .name = "samsung-i2s", - .id = 2, - .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource), - .resource = s5pv310_i2s2_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; - -/* PCM Controller platform_devices */ - -static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev) -{ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3)); - break; - case 1: - s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3)); - break; - case 2: - s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3)); - break; - default: - printk(KERN_DEBUG "Invalid PCM Controller number!"); - return -EINVAL; - } - - return 0; -} - -static struct s3c_audio_pdata s3c_pcm_pdata = { - .cfg_gpio = s5pv310_pcm_cfg_gpio, -}; - -static struct resource s5pv310_pcm0_resource[] = { - [0] = { - .start = S5PV310_PA_PCM0, - .end = S5PV310_PA_PCM0 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM0_TX, - .end = DMACH_PCM0_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM0_RX, - .end = DMACH_PCM0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s5pv310_device_pcm0 = { - .name = "samsung-pcm", - .id = 0, - .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource), - .resource = s5pv310_pcm0_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -static struct resource s5pv310_pcm1_resource[] = { - [0] = { - .start = S5PV310_PA_PCM1, - .end = S5PV310_PA_PCM1 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM1_TX, - .end = DMACH_PCM1_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM1_RX, - .end = DMACH_PCM1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s5pv310_device_pcm1 = { - .name = "samsung-pcm", - .id = 1, - .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource), - .resource = s5pv310_pcm1_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -static struct resource s5pv310_pcm2_resource[] = { - [0] = { - .start = S5PV310_PA_PCM2, - .end = S5PV310_PA_PCM2 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_PCM2_TX, - .end = DMACH_PCM2_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_PCM2_RX, - .end = DMACH_PCM2_RX, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device s5pv310_device_pcm2 = { - .name = "samsung-pcm", - .id = 2, - .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource), - .resource = s5pv310_pcm2_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -/* AC97 Controller platform devices */ - -static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev) -{ - return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4)); -} - -static struct resource s5pv310_ac97_resource[] = { - [0] = { - .start = S5PV310_PA_AC97, - .end = S5PV310_PA_AC97 + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_AC97_PCMOUT, - .end = DMACH_AC97_PCMOUT, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMACH_AC97_PCMIN, - .end = DMACH_AC97_PCMIN, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DMACH_AC97_MICIN, - .end = DMACH_AC97_MICIN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .start = IRQ_AC97, - .end = IRQ_AC97, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct s3c_audio_pdata s3c_ac97_pdata = { - .cfg_gpio = s5pv310_ac97_cfg_gpio, -}; - -static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5pv310_device_ac97 = { - .name = "samsung-ac97", - .id = -1, - .num_resources = ARRAY_SIZE(s5pv310_ac97_resource), - .resource = s5pv310_ac97_resource, - .dev = { - .platform_data = &s3c_ac97_pdata, - .dma_mask = &s5pv310_ac97_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* S/PDIF Controller platform_device */ - -static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev) -{ - s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3)); - - return 0; -} - -static struct resource s5pv310_spdif_resource[] = { - [0] = { - .start = S5PV310_PA_SPDIF, - .end = S5PV310_PA_SPDIF + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMACH_SPDIF, - .end = DMACH_SPDIF, - .flags = IORESOURCE_DMA, - }, -}; - -static struct s3c_audio_pdata samsung_spdif_pdata = { - .cfg_gpio = s5pv310_spdif_cfg_gpio, -}; - -static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5pv310_device_spdif = { - .name = "samsung-spdif", - .id = -1, - .num_resources = ARRAY_SIZE(s5pv310_spdif_resource), - .resource = s5pv310_spdif_resource, - .dev = { - .platform_data = &samsung_spdif_pdata, - .dma_mask = &s5pv310_spdif_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-s5pv310/dev-pd.c deleted file mode 100644 index 58a50c2d0b67..000000000000 --- a/arch/arm/mach-s5pv310/dev-pd.c +++ /dev/null @@ -1,139 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/dev-pd.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5PV310 - Power Domain support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include - -#include - -#include - -static int s5pv310_pd_enable(struct device *dev) -{ - struct samsung_pd_info *pdata = dev->platform_data; - u32 timeout; - - __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base); - - /* Wait max 1ms */ - timeout = 10; - while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) - != S5P_INT_LOCAL_PWR_EN) { - if (timeout == 0) { - printk(KERN_ERR "Power domain %s enable failed.\n", - dev_name(dev)); - return -ETIMEDOUT; - } - timeout--; - udelay(100); - } - - return 0; -} - -static int s5pv310_pd_disable(struct device *dev) -{ - struct samsung_pd_info *pdata = dev->platform_data; - u32 timeout; - - __raw_writel(0, pdata->base); - - /* Wait max 1ms */ - timeout = 10; - while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) { - if (timeout == 0) { - printk(KERN_ERR "Power domain %s disable failed.\n", - dev_name(dev)); - return -ETIMEDOUT; - } - timeout--; - udelay(100); - } - - return 0; -} - -struct platform_device s5pv310_device_pd[] = { - { - .name = "samsung-pd", - .id = 0, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_MFC_CONF, - }, - }, - }, { - .name = "samsung-pd", - .id = 1, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_G3D_CONF, - }, - }, - }, { - .name = "samsung-pd", - .id = 2, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_LCD0_CONF, - }, - }, - }, { - .name = "samsung-pd", - .id = 3, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_LCD1_CONF, - }, - }, - }, { - .name = "samsung-pd", - .id = 4, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_TV_CONF, - }, - }, - }, { - .name = "samsung-pd", - .id = 5, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_CAM_CONF, - }, - }, - }, { - .name = "samsung-pd", - .id = 6, - .dev = { - .platform_data = &(struct samsung_pd_info) { - .enable = s5pv310_pd_enable, - .disable = s5pv310_pd_disable, - .base = S5P_PMU_GPS_CONF, - }, - }, - }, -}; diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-s5pv310/dev-sysmmu.c deleted file mode 100644 index e1bb200ac0f0..000000000000 --- a/arch/arm/mach-s5pv310/dev-sysmmu.c +++ /dev/null @@ -1,187 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -static struct resource s5pv310_sysmmu_resource[] = { - [0] = { - .start = S5PV310_PA_SYSMMU_MDMA, - .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SYSMMU_MDMA0_0, - .end = IRQ_SYSMMU_MDMA0_0, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = S5PV310_PA_SYSMMU_SSS, - .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [3] = { - .start = IRQ_SYSMMU_SSS_0, - .end = IRQ_SYSMMU_SSS_0, - .flags = IORESOURCE_IRQ, - }, - [4] = { - .start = S5PV310_PA_SYSMMU_FIMC0, - .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [5] = { - .start = IRQ_SYSMMU_FIMC0_0, - .end = IRQ_SYSMMU_FIMC0_0, - .flags = IORESOURCE_IRQ, - }, - [6] = { - .start = S5PV310_PA_SYSMMU_FIMC1, - .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [7] = { - .start = IRQ_SYSMMU_FIMC1_0, - .end = IRQ_SYSMMU_FIMC1_0, - .flags = IORESOURCE_IRQ, - }, - [8] = { - .start = S5PV310_PA_SYSMMU_FIMC2, - .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [9] = { - .start = IRQ_SYSMMU_FIMC2_0, - .end = IRQ_SYSMMU_FIMC2_0, - .flags = IORESOURCE_IRQ, - }, - [10] = { - .start = S5PV310_PA_SYSMMU_FIMC3, - .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [11] = { - .start = IRQ_SYSMMU_FIMC3_0, - .end = IRQ_SYSMMU_FIMC3_0, - .flags = IORESOURCE_IRQ, - }, - [12] = { - .start = S5PV310_PA_SYSMMU_JPEG, - .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [13] = { - .start = IRQ_SYSMMU_JPEG_0, - .end = IRQ_SYSMMU_JPEG_0, - .flags = IORESOURCE_IRQ, - }, - [14] = { - .start = S5PV310_PA_SYSMMU_FIMD0, - .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [15] = { - .start = IRQ_SYSMMU_LCD0_M0_0, - .end = IRQ_SYSMMU_LCD0_M0_0, - .flags = IORESOURCE_IRQ, - }, - [16] = { - .start = S5PV310_PA_SYSMMU_FIMD1, - .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [17] = { - .start = IRQ_SYSMMU_LCD1_M1_0, - .end = IRQ_SYSMMU_LCD1_M1_0, - .flags = IORESOURCE_IRQ, - }, - [18] = { - .start = S5PV310_PA_SYSMMU_PCIe, - .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [19] = { - .start = IRQ_SYSMMU_PCIE_0, - .end = IRQ_SYSMMU_PCIE_0, - .flags = IORESOURCE_IRQ, - }, - [20] = { - .start = S5PV310_PA_SYSMMU_G2D, - .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [21] = { - .start = IRQ_SYSMMU_2D_0, - .end = IRQ_SYSMMU_2D_0, - .flags = IORESOURCE_IRQ, - }, - [22] = { - .start = S5PV310_PA_SYSMMU_ROTATOR, - .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [23] = { - .start = IRQ_SYSMMU_ROTATOR_0, - .end = IRQ_SYSMMU_ROTATOR_0, - .flags = IORESOURCE_IRQ, - }, - [24] = { - .start = S5PV310_PA_SYSMMU_MDMA2, - .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [25] = { - .start = IRQ_SYSMMU_MDMA1_0, - .end = IRQ_SYSMMU_MDMA1_0, - .flags = IORESOURCE_IRQ, - }, - [26] = { - .start = S5PV310_PA_SYSMMU_TV, - .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [27] = { - .start = IRQ_SYSMMU_TV_M0_0, - .end = IRQ_SYSMMU_TV_M0_0, - .flags = IORESOURCE_IRQ, - }, - [28] = { - .start = S5PV310_PA_SYSMMU_MFC_L, - .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [29] = { - .start = IRQ_SYSMMU_MFC_M0_0, - .end = IRQ_SYSMMU_MFC_M0_0, - .flags = IORESOURCE_IRQ, - }, - [30] = { - .start = S5PV310_PA_SYSMMU_MFC_R, - .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [31] = { - .start = IRQ_SYSMMU_MFC_M1_0, - .end = IRQ_SYSMMU_MFC_M1_0, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s5pv310_device_sysmmu = { - .name = "s5p-sysmmu", - .id = 32, - .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource), - .resource = s5pv310_sysmmu_resource, -}; - -EXPORT_SYMBOL(s5pv310_device_sysmmu); diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c deleted file mode 100644 index 9d07e4e2f14c..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c1.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c1.c - * - * Copyright (C) 2010 Samsung Electronics Co., Ltd. - * - * I2C1 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c1_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c deleted file mode 100644 index 4163b1233daf..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c2.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c2.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * - * I2C2 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c2_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-s5pv310/setup-i2c3.c deleted file mode 100644 index 180f153d2a20..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c3.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c3.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C3 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c3_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-s5pv310/setup-i2c4.c deleted file mode 100644 index 909e8dfc5316..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c4.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c4.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C4 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c4_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPB(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-s5pv310/setup-i2c5.c deleted file mode 100644 index 5d0fa4ac0283..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c5.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c5.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C5 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c5_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPB(6), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-s5pv310/setup-i2c6.c deleted file mode 100644 index 34aafab92ac4..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c6.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c6.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C6 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c6_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2, - S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-s5pv310/setup-i2c7.c deleted file mode 100644 index 9b25b8d18920..000000000000 --- a/arch/arm/mach-s5pv310/setup-i2c7.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-s5pv310/setup-i2c7.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C7 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include -#include -#include - -void s3c_i2c7_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c deleted file mode 100644 index 86d38cc49135..000000000000 --- a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c +++ /dev/null @@ -1,152 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK0[0:1] pins to special-function 2 */ - for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case 8: - for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-funtion 3 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case 4: - for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) { - /* Data pin GPK0[3:6] to special-funtion 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - default: - break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK1[0:1] pins to special-function 2 */ - for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK2[0:1] pins to special-function 2 */ - for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case 8: - for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { - /* Data pin GPK3[3:6] to special-function 3 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case 4: - for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) { - /* Data pin GPK2[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - default: - break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK3[0:1] pins to special-function 2 */ - for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { - /* Data pin GPK3[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c deleted file mode 100644 index db8358fc4662..000000000000 --- a/arch/arm/mach-s5pv310/setup-sdhci.c +++ /dev/null @@ -1,69 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/setup-sdhci.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include - -#include - -/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ - -char *s5pv310_hsmmc_clksrcs[4] = { - [0] = NULL, - [1] = NULL, - [2] = "sclk_mmc", /* mmc_bus */ - [3] = NULL, -}; - -void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, - struct mmc_ios *ios, struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - /* don't need to alter anything acording to card-type */ - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - - /* select base clock source to HCLK */ - - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - - /* - * clear async mode, enable conflict mask, rx feedback ctrl, SD - * clk hold and no use debounce count - */ - - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - /* Tx and Rx feedback clock delay control */ - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index b4d208b42957..e2b3ab997cff 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -1,4 +1,7 @@ /* arch/arm/plat-samsung/include/plat/devs.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com * * Copyright (c) 2004 Simtec Electronics * Ben Dooks @@ -96,15 +99,15 @@ extern struct platform_device s5pv210_device_iis1; extern struct platform_device s5pv210_device_iis2; extern struct platform_device s5pv210_device_spdif; -extern struct platform_device s5pv310_device_ac97; -extern struct platform_device s5pv310_device_pcm0; -extern struct platform_device s5pv310_device_pcm1; -extern struct platform_device s5pv310_device_pcm2; -extern struct platform_device s5pv310_device_i2s0; -extern struct platform_device s5pv310_device_i2s1; -extern struct platform_device s5pv310_device_i2s2; -extern struct platform_device s5pv310_device_spdif; -extern struct platform_device s5pv310_device_pd[]; +extern struct platform_device exynos4_device_ac97; +extern struct platform_device exynos4_device_pcm0; +extern struct platform_device exynos4_device_pcm1; +extern struct platform_device exynos4_device_pcm2; +extern struct platform_device exynos4_device_i2s0; +extern struct platform_device exynos4_device_i2s1; +extern struct platform_device exynos4_device_i2s2; +extern struct platform_device exynos4_device_spdif; +extern struct platform_device exynos4_device_pd[]; extern struct platform_device s5p6442_device_pcm0; extern struct platform_device s5p6442_device_pcm1; @@ -137,7 +140,7 @@ extern struct platform_device s5p_device_fimc2; extern struct platform_device s5p_device_mipi_csis0; extern struct platform_device s5p_device_mipi_csis1; -extern struct platform_device s5pv310_device_sysmmu; +extern struct platform_device exynos4_device_sysmmu; /* s3c2440 specific devices */ diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h index 5f0ad85783db..abb4bc32716a 100644 --- a/arch/arm/plat-samsung/include/plat/pd.h +++ b/arch/arm/plat-samsung/include/plat/pd.h @@ -1,6 +1,6 @@ /* linux/arch/arm/plat-samsung/include/plat/pd.h * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * * This program is free software; you can redistribute it and/or modify @@ -17,7 +17,7 @@ struct samsung_pd_info { void __iomem *base; }; -enum s5pv310_pd_block { +enum exynos4_pd_block { PD_MFC, PD_G3D, PD_LCD0, diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 5a41a0b69eec..b0bdf16549d5 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -1,4 +1,7 @@ -/* linux/arch/arm/plat-s3c/include/plat/sdhci.h +/* linux/arch/arm/plat-samsung/include/plat/sdhci.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics @@ -119,10 +122,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w); -extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); +extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); /* S3C2416 SDHCI setup */ @@ -334,57 +337,57 @@ static inline void s5pv210_default_sdhci3(void) { } #endif /* CONFIG_S5PV210_SETUP_SDHCI */ -/* S5PV310 SDHCI setup */ -#ifdef CONFIG_S5PV310_SETUP_SDHCI -extern char *s5pv310_hsmmc_clksrcs[4]; +/* EXYNOS4 SDHCI setup */ +#ifdef CONFIG_EXYNOS4_SETUP_SDHCI +extern char *exynos4_hsmmc_clksrcs[4]; -extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, +extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, struct mmc_card *card); -static inline void s5pv310_default_sdhci0(void) +static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } -static inline void s5pv310_default_sdhci1(void) +static inline void exynos4_default_sdhci1(void) { #ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } -static inline void s5pv310_default_sdhci2(void) +static inline void exynos4_default_sdhci2(void) { #ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; + s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } -static inline void s5pv310_default_sdhci3(void) +static inline void exynos4_default_sdhci3(void) { #ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs; - s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio; - s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; + s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; + s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; + s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } #else -static inline void s5pv310_default_sdhci0(void) { } -static inline void s5pv310_default_sdhci1(void) { } -static inline void s5pv310_default_sdhci2(void) { } -static inline void s5pv310_default_sdhci3(void) { } +static inline void exynos4_default_sdhci0(void) { } +static inline void exynos4_default_sdhci1(void) { } +static inline void exynos4_default_sdhci2(void) { } +static inline void exynos4_default_sdhci3(void) { } -#endif /* CONFIG_S5PV310_SETUP_SDHCI */ +#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ #endif /* __PLAT_S3C_SDHCI_H */ -- cgit v1.2.3 From 2e2f3d3792de5913897b6bb49ac13915b0b020d5 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 6 Feb 2011 17:39:31 +0000 Subject: ARM: pm: convert samsung platforms to generic suspend/resume support Tested-by: Kukjin Kim Signed-off-by: Russell King --- arch/arm/mach-s3c64xx/sleep.S | 63 ++----------------- arch/arm/mach-s5pv210/sleep.S | 105 ++------------------------------ arch/arm/plat-s3c24xx/sleep.S | 57 ++--------------- arch/arm/plat-samsung/include/plat/pm.h | 12 +--- arch/arm/plat-samsung/pm.c | 16 +---- 5 files changed, 14 insertions(+), 239 deletions(-) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S index b2ef44317368..afe5a762f46e 100644 --- a/arch/arm/mach-s3c64xx/sleep.S +++ b/arch/arm/mach-s3c64xx/sleep.S @@ -32,25 +32,13 @@ * code after resume. * * entry: - * r0 = pointer to the save block + * r1 = v:p offset */ ENTRY(s3c_cpu_save) stmfd sp!, { r4 - r12, lr } - - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control - mrc p15, 0, r9, c1, c0, 0 @ Control register - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls - - stmia r0, { r4 - r13 } @ Save CP registers and SP - - @@ save our state to ram - bl s3c_pm_cb_flushcache + ldr r3, =resume_with_mmu + bl cpu_suspend @@ call final suspend code ldr r0, =pm_cpu_sleep @@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save) resume_with_mmu: ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save - .data - - /* the next bit is code, but it requires easy access to the - * s3c_sleep_save_phys data before the MMU is switched on, so - * we store the code that needs this variable in the .data where - * the value can be written to (the .text segment is RO). - */ - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - /* Sleep magic, the word before the resume entry point so that the * bootloader can check for a resumeable image. */ @@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume) orr r0, r0, #1 << 15 @ GPN15 str r0, [ r3, #S3C64XX_GPNDAT ] #endif - - /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches - * are thoroughly cleaned just in case the bootloader didn't do it - * for us. */ - mov r0, #0 - mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer - @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs - @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches - - ldr r0, s3c_sleep_save_phys - ldmia r0, { r4 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register - - mov r0, #0 @ restore copro access controls - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls - mcr p15, 0, r0, c7, c5, 4 - - ldr r2, =resume_with_mmu - mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ - nop - mov pc, r2 /* jump back */ - - .end + b cpu_resume diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index d4d222b716b4..a3d649466fb1 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -35,50 +35,24 @@ /* s3c_cpu_save * * entry: - * r0 = save address (virtual addr of s3c_sleep_save_phys) + * r1 = v:p offset */ ENTRY(s3c_cpu_save) stmfd sp!, { r3 - r12, lr } - - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control - mrc p15, 0, r9, c1, c0, 0 @ Control register - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls - mrc p15, 0, r12, c10, c2, 0 @ Read PRRR - mrc p15, 0, r3, c10, c2, 1 @ READ NMRR - - stmia r0, { r3 - r13 } - - bl s3c_pm_cb_flushcache + ldr r3, =resume_with_mmu + bl cpu_suspend ldr r0, =pm_cpu_sleep ldr r0, [ r0 ] mov pc, r0 resume_with_mmu: - /* - * After MMU is turned on, restore the previous MMU table. - */ - ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET) - add r4, r4, r9 - str r12, [r4] - ldmfd sp!, { r3 - r12, pc } .ltorg - .data - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the * s3c_cpu_resume entry. @@ -96,75 +70,4 @@ s3c_sleep_save_phys: */ ENTRY(s3c_cpu_resume) - mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE - msr cpsr_c, r0 - - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs - mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache - - ldr r0, s3c_sleep_save_phys @ address of restore block - ldmia r0, { r3 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 - - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register - - mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB - - mov r0, #0 @ restore copro access - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access - mcr p15, 0, r0, c7, c5, 4 - - mcr p15, 0, r12, c10, c2, 0 @ write PRRR - mcr p15, 0, r3, c10, c2, 1 @ write NMRR - - /* - * In Cortex-A8, when MMU is turned on, the pipeline is flushed. - * And there are no valid entries in the MMU table at this point. - * So before turning on the MMU, the MMU entry for the DRAM address - * range is added. After the MMU is turned on, the other entries - * in the MMU table will be restored. - */ - - /* r6 = Translation Table BASE0 */ - mov r4, r6 - mov r4, r4, LSR #14 - mov r4, r4, LSL #14 - - /* Load address for adding to MMU table list */ - ldr r11, =0xE010F000 @ INFORM0 reg. - ldr r10, [r11, #0] - mov r10, r10, LSR #18 - bic r10, r10, #0x3 - orr r4, r4, r10 - - /* Calculate MMU table entry */ - mov r10, r10, LSL #18 - ldr r5, =0x40E - orr r10, r10, r5 - - /* Back up originally data */ - ldr r12, [r4] - - /* Add calculated MMU table entry into MMU table list */ - str r10, [r4] - - ldr r2, =resume_with_mmu - mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc - - nop - nop - nop - nop - nop @ second-to-last before mmu - - mov pc, r2 @ go back to virtual address - - .ltorg + b cpu_resume diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index e73e3b6e88d2..fd7032f84ae7 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -44,23 +44,13 @@ /* s3c_cpu_save * * entry: - * r0 = save address (virtual addr of s3c_sleep_save_phys) + * r1 = v:p offset */ ENTRY(s3c_cpu_save) stmfd sp!, { r4 - r12, lr } - - @@ store co-processor registers - - mrc p15, 0, r4, c13, c0, 0 @ PID - mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ translation table base address - mrc p15, 0, r7, c1, c0, 0 @ control register - - stmia r0, { r4 - r13 } - - @@ write our state back to RAM - bl s3c_pm_cb_flushcache + ldr r3, =resume_with_mmu + bl cpu_suspend @@ jump to final code to send system to sleep ldr r0, =pm_cpu_sleep @@ -76,20 +66,6 @@ resume_with_mmu: .ltorg - @@ the next bits sit in the .data segment, even though they - @@ happen to be code... the s3c_sleep_save_phys needs to be - @@ accessed by the resume code before it can restore the MMU. - @@ This means that the variable has to be close enough for the - @@ code to read it... since the .text segment needs to be RO, - @@ the data segment can be the only place to put this code. - - .data - - .global s3c_sleep_save_phys -s3c_sleep_save_phys: - .word 0 - - /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the * s3c_cpu_resume entry. @@ -100,10 +76,6 @@ s3c_sleep_save_phys: /* s3c_cpu_resume * * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) */ ENTRY(s3c_cpu_resume) @@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume) beq 1001b #endif /* CONFIG_DEBUG_RESUME */ - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs - mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches - - ldr r0, s3c_sleep_save_phys @ address of restore block - ldmia r0, { r4 - r13 } - - mcr p15, 0, r4, c13, c0, 0 @ PID - mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ translation table base - -#ifdef CONFIG_DEBUG_RESUME - mov r3, #'R' - strb r3, [ r2, #S3C2410_UTXH ] -#endif - - ldr r2, =resume_with_mmu - mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc - nop @ second-to-last before mmu - mov pc, r2 @ go back to virtual address - - .ltorg + b cpu_resume diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index d9025e377675..4aa697dfe13f 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -50,13 +50,11 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */ /* from sleep.S */ -extern int s3c_cpu_save(unsigned long *saveblk); +extern int s3c_cpu_save(unsigned long *saveblk, long); extern void s3c_cpu_resume(void); extern void s3c2410_cpu_suspend(void); -extern unsigned long s3c_sleep_save_phys; - /* sleep save info */ /** @@ -179,13 +177,5 @@ extern void s3c_pm_restore_gpios(void); */ extern void s3c_pm_save_gpios(void); -/** - * s3c_pm_cb_flushcache - callback for assembly code - * - * Callback to issue flush_cache_all() as this call is - * not a directly callable object. - */ -extern void s3c_pm_cb_flushcache(void); - extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 02d531fb3f81..d5b58d31903c 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -241,8 +241,6 @@ void (*pm_cpu_sleep)(void); static int s3c_pm_enter(suspend_state_t state) { - static unsigned long regs_save[16]; - /* ensure the debug is initialised (if enabled) */ s3c_pm_debug_init(); @@ -266,12 +264,6 @@ static int s3c_pm_enter(suspend_state_t state) return -EINVAL; } - /* store the physical address of the register recovery block */ - - s3c_sleep_save_phys = virt_to_phys(regs_save); - - S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); - /* save all necessary core registers not covered by the drivers */ s3c_pm_save_gpios(); @@ -305,7 +297,7 @@ static int s3c_pm_enter(suspend_state_t state) * we resume as it saves its own register state and restores it * during the resume. */ - s3c_cpu_save(regs_save); + s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET); /* restore the cpu state using the kernel's cpu init code. */ @@ -336,12 +328,6 @@ static int s3c_pm_enter(suspend_state_t state) return 0; } -/* callback from assembly code */ -void s3c_pm_cb_flushcache(void) -{ - flush_cache_all(); -} - static int s3c_pm_prepare(void) { /* prepare check area if configured */ -- cgit v1.2.3 From 2ce30137094969123a8846ca4f68c2628ea4a658 Mon Sep 17 00:00:00 2001 From: Banajit Goswami Date: Mon, 28 Feb 2011 22:24:51 +0530 Subject: ARM: SAMSUNG: Move PWM device definition from plat-s3c24xx to plat-samsung This patch does the following:- 1. It moves file pwm.c from plat-s3c24xx to plat-samsung. This will enable all machines with Samsung SoCs to make use of the same code. 2. The device definitions have been separated to a new file dev-pwm.c for better clarity and structure. 3. It will enable all Samsung S3C and S5P series SoC's to use common PWM Kconfig definition. Signed-off-by: Banajit Goswami Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c64xx/Kconfig | 4 ++-- arch/arm/plat-s3c24xx/Kconfig | 7 ------ arch/arm/plat-samsung/Kconfig | 13 ++++++++++ arch/arm/plat-samsung/Makefile | 1 + arch/arm/plat-samsung/dev-pwm.c | 53 +++++++++++++++++++++++++++++++++++++++++ arch/arm/plat-samsung/pwm.c | 33 ------------------------- 6 files changed, 69 insertions(+), 42 deletions(-) create mode 100644 arch/arm/plat-samsung/dev-pwm.c (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 579d2f0f4dd0..f3a953f02dd6 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -231,7 +231,7 @@ config MACH_HMT select S3C_DEV_NAND select S3C_DEV_USB_HOST select S3C64XX_SETUP_FB_24BPP - select HAVE_PWM + select SAMSUNG_DEV_PWM help Machine support for the Airgoo HMT @@ -249,8 +249,8 @@ config MACH_SMARTQ select S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_FB_24BPP select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS - select HAVE_PWM help Shared machine support for SmartQ 5/7 diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index eb105e61c746..d9c4096ebf45 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -56,13 +56,6 @@ config S3C24XX_DCLK help Clock code for supporting DCLK/CLKOUT on S3C24XX architectures -config S3C24XX_PWM - bool "PWM device support" - select HAVE_PWM - help - Support for exporting the PWM timer blocks via the pwm device - system. - # gpio configurations config S3C24XX_GPIO_EXTRA diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 32be05cf82a3..be72100b81b4 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -273,6 +273,19 @@ config SAMSUNG_DEV_KEYPAD help Compile in platform device definitions for keypad +config SAMSUNG_DEV_PWM + bool + default y if ARCH_S3C2410 + help + Compile in platform device definition for PWM Timer + +config S3C24XX_PWM + bool "PWM device support" + select HAVE_PWM + help + Support for exporting the PWM timer blocks via the pwm device + system + # DMA config S3C_DMA diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 29932f88a8d6..e9de58a2e294 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o +obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o # DMA support diff --git a/arch/arm/plat-samsung/dev-pwm.c b/arch/arm/plat-samsung/dev-pwm.c new file mode 100644 index 000000000000..dab47b0e1900 --- /dev/null +++ b/arch/arm/plat-samsung/dev-pwm.c @@ -0,0 +1,53 @@ +/* linux/arch/arm/plat-samsung/dev-pwm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2007 Ben Dooks + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks , + * + * S3C series device definition for the PWM timer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include + +#include + +#define TIMER_RESOURCE_SIZE (1) + +#define TIMER_RESOURCE(_tmr, _irq) \ + (struct resource [TIMER_RESOURCE_SIZE]) { \ + [0] = { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } \ + } + +#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ + .name = "s3c24xx-pwm", \ + .id = _tmr_no, \ + .num_resources = TIMER_RESOURCE_SIZE, \ + .resource = TIMER_RESOURCE(_tmr_no, _irq), \ + +/* + * since we already have an static mapping for the timer, + * we do not bother setting any IO resource for the base. + */ + +struct platform_device s3c_device_timer[] = { + [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, + [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, + [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, + [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, + [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, +}; +EXPORT_SYMBOL(s3c_device_timer); diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index 2eeb49fa056d..f37457c52064 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c @@ -20,10 +20,8 @@ #include #include -#include #include -#include #include struct pwm_device { @@ -47,37 +45,6 @@ struct pwm_device { static struct clk *clk_scaler[2]; -/* Standard setup for a timer block. */ - -#define TIMER_RESOURCE_SIZE (1) - -#define TIMER_RESOURCE(_tmr, _irq) \ - (struct resource [TIMER_RESOURCE_SIZE]) { \ - [0] = { \ - .start = _irq, \ - .end = _irq, \ - .flags = IORESOURCE_IRQ \ - } \ - } - -#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ - .name = "s3c24xx-pwm", \ - .id = _tmr_no, \ - .num_resources = TIMER_RESOURCE_SIZE, \ - .resource = TIMER_RESOURCE(_tmr_no, _irq), \ - -/* since we already have an static mapping for the timer, we do not - * bother setting any IO resource for the base. - */ - -struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, -}; - static inline int pwm_is_tdiv(struct pwm_device *pwm) { return clk_get_parent(pwm->clk) == pwm->clk_div; -- cgit v1.2.3 From 13c608d244600be1d324067dff1a1a1192fc0730 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 4 Mar 2011 07:55:44 +0900 Subject: ARM: SAMSUNG: Include devs.h in dev-uart.c to prototype devices Ensures that the declaration agrees with the definition and makes sparse happy. Signed-off-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/dev-uart.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c index 3776cd952450..5928105490fa 100644 --- a/arch/arm/plat-samsung/dev-uart.c +++ b/arch/arm/plat-samsung/dev-uart.c @@ -15,6 +15,8 @@ #include #include +#include + /* uart devices */ static struct platform_device s3c24xx_uart_device0 = { -- cgit v1.2.3 From 604eefeb2308cda72325fd8754aecb55075ae866 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Sat, 12 Mar 2011 08:58:01 +0900 Subject: ARM: S5P: Add platform definitions for FIMC3 Add support for fourth FIMC platform device definition and define resources for FIMC modules on EXYNOS4 machines. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos4/cpu.c | 7 +++++ arch/arm/mach-exynos4/include/mach/irqs.h | 5 +++ arch/arm/mach-exynos4/include/mach/map.h | 9 ++++++ arch/arm/plat-s5p/Kconfig | 5 +++ arch/arm/plat-s5p/Makefile | 1 + arch/arm/plat-s5p/dev-fimc3.c | 43 ++++++++++++++++++++++++++ arch/arm/plat-samsung/include/plat/devs.h | 1 + arch/arm/plat-samsung/include/plat/fimc-core.h | 5 +++ 8 files changed, 76 insertions(+) create mode 100644 arch/arm/plat-s5p/dev-fimc3.c (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 479dfa1951c8..793011391943 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #include @@ -120,6 +122,11 @@ void __init exynos4_map_io(void) exynos4_default_sdhci1(); exynos4_default_sdhci2(); exynos4_default_sdhci3(); + + s3c_fimc_setname(0, "exynos4-fimc"); + s3c_fimc_setname(1, "exynos4-fimc"); + s3c_fimc_setname(2, "exynos4-fimc"); + s3c_fimc_setname(3, "exynos4-fimc"); } void __init exynos4_init_clocks(int xtal) diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h index e3556d45c75b..1db1de8e3e81 100644 --- a/arch/arm/mach-exynos4/include/mach/irqs.h +++ b/arch/arm/mach-exynos4/include/mach/irqs.h @@ -108,6 +108,11 @@ #define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0) #define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1) +#define IRQ_FIMC0 COMBINER_IRQ(32, 0) +#define IRQ_FIMC1 COMBINER_IRQ(32, 1) +#define IRQ_FIMC2 COMBINER_IRQ(33, 0) +#define IRQ_FIMC3 COMBINER_IRQ(33, 1) + #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) #define IRQ_MCT_L1 COMBINER_IRQ(35, 3) diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 89ab6f75776c..4f50b07a376a 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -25,6 +25,11 @@ #define EXYNOS4_PA_SYSRAM 0x02020000 +#define EXYNOS4_PA_FIMC0 0x11800000 +#define EXYNOS4_PA_FIMC1 0x11810000 +#define EXYNOS4_PA_FIMC2 0x11820000 +#define EXYNOS4_PA_FIMC3 0x11830000 + #define EXYNOS4_PA_I2S0 0x03830000 #define EXYNOS4_PA_I2S1 0xE3100000 #define EXYNOS4_PA_I2S2 0xE2A00000 @@ -120,6 +125,10 @@ #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG #define S5P_PA_CHIPID EXYNOS4_PA_CHIPID +#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 +#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 +#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 +#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 0e4144771240..849229716586 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -65,6 +65,11 @@ config S5P_DEV_FIMC2 help Compile in platform device definitions for FIMC controller 2 +config S5P_DEV_FIMC3 + bool + help + Compile in platform device definitions for FIMC controller 3 + config S5P_DEV_ONENAND bool help diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index a788266b5e5f..42afff7f60be 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_S5P_HRT) += s5p-time.o obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o +obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o diff --git a/arch/arm/plat-s5p/dev-fimc3.c b/arch/arm/plat-s5p/dev-fimc3.c new file mode 100644 index 000000000000..ef31beca386c --- /dev/null +++ b/arch/arm/plat-s5p/dev-fimc3.c @@ -0,0 +1,43 @@ +/* linux/arch/arm/plat-s5p/dev-fimc3.c + * + * Copyright (c) 2010 Samsung Electronics + * + * Base S5P FIMC3 resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +static struct resource s5p_fimc3_resource[] = { + [0] = { + .start = S5P_PA_FIMC3, + .end = S5P_PA_FIMC3 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC3, + .end = IRQ_FIMC3, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 s5p_fimc3_dma_mask = DMA_BIT_MASK(32); + +struct platform_device s5p_device_fimc3 = { + .name = "s5p-fimc", + .id = 3, + .num_resources = ARRAY_SIZE(s5p_fimc3_resource), + .resource = s5p_fimc3_resource, + .dev = { + .dma_mask = &s5p_fimc3_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index e2b3ab997cff..7231ccf89ebb 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -136,6 +136,7 @@ extern struct platform_device samsung_device_keypad; extern struct platform_device s5p_device_fimc0; extern struct platform_device s5p_device_fimc1; extern struct platform_device s5p_device_fimc2; +extern struct platform_device s5p_device_fimc3; extern struct platform_device s5p_device_mipi_csis0; extern struct platform_device s5p_device_mipi_csis1; diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h index 81a3bfeeccad..945a99d59563 100644 --- a/arch/arm/plat-samsung/include/plat/fimc-core.h +++ b/arch/arm/plat-samsung/include/plat/fimc-core.h @@ -37,6 +37,11 @@ static inline void s3c_fimc_setname(int id, char *name) case 2: s5p_device_fimc2.name = name; break; +#endif +#ifdef CONFIG_S5P_DEV_FIMC3 + case 3: + s5p_device_fimc3.name = name; + break; #endif } } -- cgit v1.2.3 From 1663895cb434b586d022d6414f03316469cf284d Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Thu, 10 Mar 2011 13:33:59 +0900 Subject: ARM: EXYNOS4: Suspend to RAM Support This patch adds support suspend to ram for EXYNOS4210. As a note, this includes function of outer cache flush because it is used before entering PM. Signed-off-by: Jaecheol Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos4/Makefile | 1 + arch/arm/mach-exynos4/include/mach/pm-core.h | 49 ++++ arch/arm/mach-exynos4/pm.c | 420 +++++++++++++++++++++++++++ arch/arm/mach-exynos4/sleep.S | 76 +++++ arch/arm/plat-samsung/include/plat/cpu.h | 1 + 5 files changed, 547 insertions(+) create mode 100644 arch/arm/mach-exynos4/include/mach/pm-core.h create mode 100644 arch/arm/mach-exynos4/pm.c create mode 100644 arch/arm/mach-exynos4/sleep.S (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 56e367b48fbb..991a4c5f4677 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -14,6 +14,7 @@ obj- := obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o +obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h new file mode 100644 index 000000000000..f26e46bc06ca --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/pm-core.h @@ -0,0 +1,49 @@ +/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h, + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#include + +static inline void s3c_pm_debug_init_uart(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + unsigned int tmp; + tmp = __raw_readl(S5P_WAKEUP_MASK); + tmp &= ~(1 << 31); + __raw_writel(tmp, S5P_WAKEUP_MASK); + + __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); + __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ + /* nothing here yet */ +} diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c new file mode 100644 index 000000000000..10d917d9e3ad --- /dev/null +++ b/arch/arm/mach-exynos4/pm.c @@ -0,0 +1,420 @@ +/* linux/arch/arm/mach-exynos4/pm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4210 - Power Management support + * + * Based on arch/arm/mach-s3c2410/pm.c + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +static struct sleep_save exynos4_sleep[] = { + { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, }, + { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, }, + { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, }, + { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, }, + { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, }, + { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, }, + { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, }, + { .reg = S5P_L2_0_LOWPWR , .val = 0x3, }, + { .reg = S5P_L2_1_LOWPWR , .val = 0x3, }, + { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, }, + { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, }, + { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, }, + { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, }, + { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, }, + { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, }, + { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, }, + { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, }, + { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, }, + { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, }, + { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, }, + { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, }, + { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, }, + { .reg = S5P_XXTI_LOWPWR , .val = 0x0, }, + { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, }, + { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, }, + { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, }, + { .reg = S5P_CAM_LOWPWR , .val = 0x0, }, + { .reg = S5P_TV_LOWPWR , .val = 0x0, }, + { .reg = S5P_MFC_LOWPWR , .val = 0x0, }, + { .reg = S5P_G3D_LOWPWR , .val = 0x0, }, + { .reg = S5P_LCD0_LOWPWR , .val = 0x0, }, + { .reg = S5P_LCD1_LOWPWR , .val = 0x0, }, + { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, }, + { .reg = S5P_GPS_LOWPWR , .val = 0x0, }, + { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, }, +}; + +static struct sleep_save exynos4_set_clksrc[] = { + { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, + { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, + { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, + { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, + { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, + { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, + { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, + { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, + { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, + { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, +}; + +static struct sleep_save exynos4_core_save[] = { + /* CMU side */ + SAVE_ITEM(S5P_CLKDIV_LEFTBUS), + SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), + SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), + SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), + SAVE_ITEM(S5P_EPLL_CON0), + SAVE_ITEM(S5P_EPLL_CON1), + SAVE_ITEM(S5P_VPLL_CON0), + SAVE_ITEM(S5P_VPLL_CON1), + SAVE_ITEM(S5P_CLKSRC_TOP0), + SAVE_ITEM(S5P_CLKSRC_TOP1), + SAVE_ITEM(S5P_CLKSRC_CAM), + SAVE_ITEM(S5P_CLKSRC_MFC), + SAVE_ITEM(S5P_CLKSRC_IMAGE), + SAVE_ITEM(S5P_CLKSRC_LCD0), + SAVE_ITEM(S5P_CLKSRC_LCD1), + SAVE_ITEM(S5P_CLKSRC_MAUDIO), + SAVE_ITEM(S5P_CLKSRC_FSYS), + SAVE_ITEM(S5P_CLKSRC_PERIL0), + SAVE_ITEM(S5P_CLKSRC_PERIL1), + SAVE_ITEM(S5P_CLKDIV_CAM), + SAVE_ITEM(S5P_CLKDIV_TV), + SAVE_ITEM(S5P_CLKDIV_MFC), + SAVE_ITEM(S5P_CLKDIV_G3D), + SAVE_ITEM(S5P_CLKDIV_IMAGE), + SAVE_ITEM(S5P_CLKDIV_LCD0), + SAVE_ITEM(S5P_CLKDIV_LCD1), + SAVE_ITEM(S5P_CLKDIV_MAUDIO), + SAVE_ITEM(S5P_CLKDIV_FSYS0), + SAVE_ITEM(S5P_CLKDIV_FSYS1), + SAVE_ITEM(S5P_CLKDIV_FSYS2), + SAVE_ITEM(S5P_CLKDIV_FSYS3), + SAVE_ITEM(S5P_CLKDIV_PERIL0), + SAVE_ITEM(S5P_CLKDIV_PERIL1), + SAVE_ITEM(S5P_CLKDIV_PERIL2), + SAVE_ITEM(S5P_CLKDIV_PERIL3), + SAVE_ITEM(S5P_CLKDIV_PERIL4), + SAVE_ITEM(S5P_CLKDIV_PERIL5), + SAVE_ITEM(S5P_CLKDIV_TOP), + SAVE_ITEM(S5P_CLKSRC_MASK_CAM), + SAVE_ITEM(S5P_CLKSRC_MASK_TV), + SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), + SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), + SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), + SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), + SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), + SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), + SAVE_ITEM(S5P_CLKGATE_SCLKCAM), + SAVE_ITEM(S5P_CLKGATE_IP_CAM), + SAVE_ITEM(S5P_CLKGATE_IP_TV), + SAVE_ITEM(S5P_CLKGATE_IP_MFC), + SAVE_ITEM(S5P_CLKGATE_IP_G3D), + SAVE_ITEM(S5P_CLKGATE_IP_IMAGE), + SAVE_ITEM(S5P_CLKGATE_IP_LCD0), + SAVE_ITEM(S5P_CLKGATE_IP_LCD1), + SAVE_ITEM(S5P_CLKGATE_IP_FSYS), + SAVE_ITEM(S5P_CLKGATE_IP_GPS), + SAVE_ITEM(S5P_CLKGATE_IP_PERIL), + SAVE_ITEM(S5P_CLKGATE_IP_PERIR), + SAVE_ITEM(S5P_CLKGATE_BLOCK), + SAVE_ITEM(S5P_CLKSRC_MASK_DMC), + SAVE_ITEM(S5P_CLKSRC_DMC), + SAVE_ITEM(S5P_CLKDIV_DMC0), + SAVE_ITEM(S5P_CLKDIV_DMC1), + SAVE_ITEM(S5P_CLKGATE_IP_DMC), + SAVE_ITEM(S5P_CLKSRC_CPU), + SAVE_ITEM(S5P_CLKDIV_CPU), + SAVE_ITEM(S5P_CLKGATE_SCLKCPU), + SAVE_ITEM(S5P_CLKGATE_IP_CPU), + /* GIC side */ + SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), + SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), + SAVE_ITEM(S5P_VA_GIC_CPU + 0x008), + SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C), + SAVE_ITEM(S5P_VA_GIC_CPU + 0x014), + SAVE_ITEM(S5P_VA_GIC_CPU + 0x018), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x000), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x004), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x100), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x104), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x108), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x300), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x304), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x308), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x400), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x404), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x408), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x410), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x414), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x418), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x420), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x424), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x428), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x430), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x434), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x438), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x440), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x444), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x448), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x450), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x454), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x458), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C), + + SAVE_ITEM(S5P_VA_GIC_DIST + 0x800), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x804), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x808), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x810), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x814), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x818), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x820), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x824), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x828), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x830), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x834), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x838), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x840), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x844), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x848), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x850), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x854), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x858), + SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C), + + SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00), + SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04), + SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08), + SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C), + SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10), + SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14), + + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), + SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), +}; + +static struct sleep_save exynos4_l2cc_save[] = { + SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), + SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), + SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), + SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), + SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), +}; + +void exynos4_cpu_suspend(void) +{ + unsigned long tmp; + unsigned long mask = 0xFFFFFFFF; + + /* Setting Central Sequence Register for power down mode */ + + tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + tmp &= ~(S5P_CENTRAL_LOWPWR_CFG); + __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + + /* Setting Central Sequence option Register */ + + tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); + tmp &= ~(S5P_USE_MASK); + tmp |= S5P_USE_STANDBY_WFI0; + __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); + + /* Clear all interrupt pending to avoid early wakeup */ + + __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280)); + __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284)); + __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288)); + + /* Disable all interrupt */ + + __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000)); + __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000)); + __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184)); + __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188)); + + outer_flush_all(); + + /* issue the standby signal into the pm unit. */ + cpu_do_idle(); + + /* we should never get past here */ + panic("sleep resumed to originator?"); +} + +static void exynos4_pm_prepare(void) +{ + u32 tmp; + + s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); + s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); + + tmp = __raw_readl(S5P_INFORM1); + + /* Set value of power down register for sleep mode */ + + s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep)); + __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); + + /* ensure at least INFORM0 has the resume address */ + + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); + + /* Before enter central sequence mode, clock src register have to set */ + + s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); + +} + +static int exynos4_pm_add(struct sys_device *sysdev) +{ + pm_cpu_prep = exynos4_pm_prepare; + pm_cpu_sleep = exynos4_cpu_suspend; + + return 0; +} + +/* This function copy from linux/arch/arm/kernel/smp_scu.c */ + +void exynos4_scu_enable(void __iomem *scu_base) +{ + u32 scu_ctrl; + + scu_ctrl = __raw_readl(scu_base); + /* already enabled? */ + if (scu_ctrl & 1) + return; + + scu_ctrl |= 1; + __raw_writel(scu_ctrl, scu_base); + + /* + * Ensure that the data accessed by CPU0 before the SCU was + * initialised is visible to the other CPUs. + */ + flush_cache_all(); +} + +static int exynos4_pm_resume(struct sys_device *dev) +{ + /* For release retention */ + + __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); + __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); + __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); + __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); + __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); + __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); + __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); + + s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); + + exynos4_scu_enable(S5P_VA_SCU); + +#ifdef CONFIG_CACHE_L2X0 + s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); + outer_inv_all(); + /* enable L2X0*/ + writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); +#endif + + return 0; +} + +static struct sysdev_driver exynos4_pm_driver = { + .add = exynos4_pm_add, + .resume = exynos4_pm_resume, +}; + +static __init int exynos4_pm_drvinit(void) +{ + unsigned int tmp; + + s3c_pm_init(); + + /* All wakeup disable */ + + tmp = __raw_readl(S5P_WAKEUP_MASK); + tmp |= ((0xFF << 8) | (0x1F << 1)); + __raw_writel(tmp, S5P_WAKEUP_MASK); + + return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); +} +arch_initcall(exynos4_pm_drvinit); diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S new file mode 100644 index 000000000000..6b62425417a6 --- /dev/null +++ b/arch/arm/mach-exynos4/sleep.S @@ -0,0 +1,76 @@ +/* linux/arch/arm/mach-exynos4/sleep.S + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4210 power Manager (Suspend-To-RAM) support + * Based on S3C2410 sleep code by: + * Ben Dooks, (c) 2004 Simtec Electronics + * + * Based on PXA/SA1100 sleep code by: + * Nicolas Pitre, (c) 2002 Monta Vista Software Inc + * Cliff Brake, (c) 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include + + .text + + /* + * s3c_cpu_save + * + * entry: + * r1 = v:p offset + */ + +ENTRY(s3c_cpu_save) + + stmfd sp!, { r3 - r12, lr } + ldr r3, =resume_with_mmu + bl cpu_suspend + + ldr r0, =pm_cpu_sleep + ldr r0, [ r0 ] + mov pc, r0 + +resume_with_mmu: + ldmfd sp!, { r3 - r12, pc } + + .ltorg + + /* + * sleep magic, to allow the bootloader to check for an valid + * image to resume to. Must be the first word before the + * s3c_cpu_resume entry. + */ + + .word 0x2bedf00d + + /* + * s3c_cpu_resume + * + * resume code entry for bootloader to call + * + * we must put this code here in the data segment as we have no + * other way of restoring the stack pointer after sleep, and we + * must not write to the code segment (code is read-only) + */ + +ENTRY(s3c_cpu_resume) + b cpu_resume diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 9addb3dfb4bc..cedfff51c82b 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -82,6 +82,7 @@ extern struct sysdev_class s3c64xx_sysclass; extern struct sysdev_class s5p64x0_sysclass; extern struct sysdev_class s5p6442_sysclass; extern struct sysdev_class s5pv210_sysclass; +extern struct sysdev_class exynos4_sysclass; extern void (*s5pc1xx_idle)(void); -- cgit v1.2.3 From 40360217fdbbb9afbbe23639dbc964fb2735a83f Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Tue, 15 Mar 2011 18:35:24 +0900 Subject: ARM: EXYNOS4: Add support for SATA on ARMLEX4210 Adds the device definitions, platform specific initialization and clocks for SATA on ARMLEX4210. Signed-off-by: Abhilash Kesavan Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos4/Kconfig | 1 + arch/arm/mach-exynos4/Makefile | 1 + arch/arm/mach-exynos4/clock.c | 7 + arch/arm/mach-exynos4/dev-ahci.c | 263 ++++++++++++++++++++++++++ arch/arm/mach-exynos4/include/mach/map.h | 4 + arch/arm/mach-exynos4/include/mach/regs-pmu.h | 2 + arch/arm/mach-exynos4/mach-armlex4210.c | 1 + arch/arm/plat-samsung/include/plat/devs.h | 1 + 8 files changed, 280 insertions(+) create mode 100644 arch/arm/mach-exynos4/dev-ahci.c (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index 8d7398fdd05c..8b841e693902 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -129,6 +129,7 @@ config MACH_ARMLEX4210 select S3C_DEV_HSMMC3 select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI + select SATA_AHCI_PLATFORM help Machine support for Samsung ARMLEX4210 based on EXYNOS4210 diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 9473adbb6c19..486d8b4b38d3 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -52,3 +52,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 7bf3c4e35d26..fac6a3b4a62b 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -431,6 +431,12 @@ static struct clk init_clocks_off[] = { .id = 1, .enable = exynos4_clk_ip_lcd1_ctrl, .ctrlbit = (1 << 0), + }, { + .name = "sataphy", + .id = -1, + .parent = &clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 3), }, { .name = "hsmmc", .id = 0, @@ -464,6 +470,7 @@ static struct clk init_clocks_off[] = { }, { .name = "sata", .id = -1, + .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 10), }, { diff --git a/arch/arm/mach-exynos4/dev-ahci.c b/arch/arm/mach-exynos4/dev-ahci.c new file mode 100644 index 000000000000..f57a3de8e1d2 --- /dev/null +++ b/arch/arm/mach-exynos4/dev-ahci.c @@ -0,0 +1,263 @@ +/* linux/arch/arm/mach-exynos4/dev-ahci.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - AHCI support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +/* PHY Control Register */ +#define SATA_CTRL0 0x0 +/* PHY Link Control Register */ +#define SATA_CTRL1 0x4 +/* PHY Status Register */ +#define SATA_PHY_STATUS 0x8 + +#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27) +#define SATA_CTRL0_SPEED_MODE (1 << 26) +#define SATA_CTRL0_M_PHY_CAL (1 << 19) +#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10) +#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9) +#define SATA_CTRL0_PHY_POR_N (1 << 8) + +#define SATA_CTRL1_RST_PMALIVE_N (1 << 8) +#define SATA_CTRL1_RST_RXOOB_N (1 << 7) +#define SATA_CTRL1_RST_RX_N (1 << 6) +#define SATA_CTRL1_RST_TX_N (1 << 5) + +#define SATA_PHY_STATUS_CMU_OK (1 << 18) +#define SATA_PHY_STATUS_LANE_OK (1 << 16) + +#define LANE0 0x200 +#define COM_LANE 0xA00 + +#define HOST_PORTS_IMPL 0xC +#define SCLK_SATA_FREQ (67 * MHZ) + +static void __iomem *phy_base, *phy_ctrl; + +struct phy_reg { + u8 reg; + u8 val; +}; + +/* SATA PHY setup */ +static const struct phy_reg exynos4_sataphy_cmu[] = { + { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 }, + { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 }, + { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 }, + { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 }, + { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 }, + { 0x6b, 0xc8 }, { 0x6c, 0x06 }, +}; + +static const struct phy_reg exynos4_sataphy_lane[] = { + { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 }, + { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 }, + { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e }, + { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 }, + { 0x51, 0x0f }, +}; + +static const struct phy_reg exynos4_sataphy_comlane[] = { + { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d }, + { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 }, + { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 }, + { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 }, + { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 }, + { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 }, + { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 }, + { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d }, + { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 }, + { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 }, + { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 }, + { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff }, + { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 }, + { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 }, +}; + +static int wait_for_phy_ready(void __iomem *reg, unsigned long bit) +{ + unsigned long timeout; + + /* wait for maximum of 3 sec */ + timeout = jiffies + msecs_to_jiffies(3000); + while (!(__raw_readl(reg) & bit)) { + if (time_after(jiffies, timeout)) + return -1; + cpu_relax(); + } + return 0; +} + +static int ahci_phy_init(void __iomem *mmio) +{ + int i, ctrl0; + + for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++) + __raw_writeb(exynos4_sataphy_cmu[i].val, + phy_base + (exynos4_sataphy_cmu[i].reg * 4)); + + for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++) + __raw_writeb(exynos4_sataphy_lane[i].val, + phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4); + + for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++) + __raw_writeb(exynos4_sataphy_comlane[i].val, + phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4); + + __raw_writeb(0x07, phy_base); + + ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); + ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N; + __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); + + if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, + SATA_PHY_STATUS_CMU_OK) < 0) { + printk(KERN_ERR "PHY CMU not ready\n"); + return -EBUSY; + } + + __raw_writeb(0x03, phy_base + (COM_LANE * 4)); + + ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); + ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N; + __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); + + if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, + SATA_PHY_STATUS_LANE_OK) < 0) { + printk(KERN_ERR "PHY LANE not ready\n"); + return -EBUSY; + } + + ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); + ctrl0 |= SATA_CTRL0_M_PHY_CAL; + __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); + + return 0; +} + +static int exynos4_ahci_init(struct device *dev, void __iomem *mmio) +{ + struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata; + int val, ret; + + phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K); + if (!phy_base) { + dev_err(dev, "failed to allocate memory for SATA PHY\n"); + return -ENOMEM; + } + + phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16); + if (!phy_ctrl) { + dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n"); + ret = -ENOMEM; + goto err1; + } + + clk_sata = clk_get(dev, "sata"); + if (IS_ERR(clk_sata)) { + dev_err(dev, "failed to get sata clock\n"); + ret = PTR_ERR(clk_sata); + clk_sata = NULL; + goto err2; + + } + clk_enable(clk_sata); + + clk_sataphy = clk_get(dev, "sataphy"); + if (IS_ERR(clk_sataphy)) { + dev_err(dev, "failed to get sataphy clock\n"); + ret = PTR_ERR(clk_sataphy); + clk_sataphy = NULL; + goto err3; + } + clk_enable(clk_sataphy); + + clk_sclk_sata = clk_get(dev, "sclk_sata"); + if (IS_ERR(clk_sclk_sata)) { + dev_err(dev, "failed to get sclk_sata\n"); + ret = PTR_ERR(clk_sclk_sata); + clk_sclk_sata = NULL; + goto err4; + } + clk_enable(clk_sclk_sata); + clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ); + + __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL); + + /* Enable PHY link control */ + val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N | + SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N; + __raw_writel(val, phy_ctrl + SATA_CTRL1); + + /* Set communication speed as 3Gbps and enable PHY power */ + val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE | + SATA_CTRL0_PHY_POR_N; + __raw_writel(val, phy_ctrl + SATA_CTRL0); + + /* Port0 is available */ + __raw_writel(0x1, mmio + HOST_PORTS_IMPL); + + return ahci_phy_init(mmio); + +err4: + clk_disable(clk_sataphy); + clk_put(clk_sataphy); +err3: + clk_disable(clk_sata); + clk_put(clk_sata); +err2: + iounmap(phy_ctrl); +err1: + iounmap(phy_base); + + return ret; +} + +static struct ahci_platform_data exynos4_ahci_pdata = { + .init = exynos4_ahci_init, +}; + +static struct resource exynos4_ahci_resource[] = { + [0] = { + .start = EXYNOS4_PA_SATA, + .end = EXYNOS4_PA_SATA + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SATA, + .end = IRQ_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32); + +struct platform_device exynos4_device_ahci = { + .name = "ahci", + .id = -1, + .resource = exynos4_ahci_resource, + .num_resources = ARRAY_SIZE(exynos4_ahci_resource), + .dev = { + .platform_data = &exynos4_ahci_pdata, + .dma_mask = &exynos4_ahci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 4f50b07a376a..874f7d288126 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -93,6 +93,10 @@ #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) +#define EXYNOS4_PA_SATA 0x12560000 +#define EXYNOS4_PA_SATAPHY 0x125D0000 +#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 + #define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS4_PA_UART 0x13800000 diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index fa1da9451689..62b0014d05e0 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h @@ -38,6 +38,7 @@ #define S5P_MIPI_DPHY_SRESETN (1 << 1) #define S5P_MIPI_DPHY_MRESETN (1 << 2) +#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) #define S5P_INFORM2 S5P_PMUREG(0x0808) @@ -153,6 +154,7 @@ #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) +#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 #define S5P_INT_LOCAL_PWR_EN 0x7 #define S5P_CHECK_SLEEP 0x00000BAD diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c index 1ec7e77bed82..b482c6285fc4 100644 --- a/arch/arm/mach-exynos4/mach-armlex4210.c +++ b/arch/arm/mach-exynos4/mach-armlex4210.c @@ -158,6 +158,7 @@ static struct platform_device *armlex4210_devices[] __initdata = { &exynos4_device_sysmmu, &samsung_asoc_dma, &armlex4210_smsc911x, + &exynos4_device_ahci, }; static void __init armlex4210_smsc911x_init(void) diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 7231ccf89ebb..f0da6b70fba4 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -108,6 +108,7 @@ extern struct platform_device exynos4_device_i2s1; extern struct platform_device exynos4_device_i2s2; extern struct platform_device exynos4_device_spdif; extern struct platform_device exynos4_device_pd[]; +extern struct platform_device exynos4_device_ahci; extern struct platform_device s5p6442_device_pcm0; extern struct platform_device s5p6442_device_pcm1; -- cgit v1.2.3 From a43efddc3bf8b143ff9352763cd39d425db14d27 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 15 Mar 2011 21:17:43 +0900 Subject: ARM: S5P: Add function to register gpio interrupt bank data This patch removes all global data from common s5p gpio interrupt handler code. This enables to reuse this code on EXYNOS4 platform. Instead of global data (IRQ_GPIOINT interrupt number, S5P_GPIOINT_GROUP_MAXNR groups count), a s5p_register_gpioint_bank() function is introduced. It is aimed to be called from gpiolib init. Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pc100/gpiolib.c | 1 + arch/arm/mach-s5pv210/gpiolib.c | 1 + arch/arm/plat-s5p/irq-gpioint.c | 68 +++++++++++++++++++++++---- arch/arm/plat-samsung/include/plat/gpio-cfg.h | 16 +++++++ 4 files changed, 76 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-samsung') diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 20856eb7dd51..2842394b28b5 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c @@ -348,6 +348,7 @@ static __init int s5pc100_gpiolib_init(void) } samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips); + s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); return 0; } diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c index ab673effd767..1ba20a703e05 100644 --- a/arch/arm/mach-s5pv210/gpiolib.c +++ b/arch/arm/mach-s5pv210/gpiolib.c @@ -281,6 +281,7 @@ static __init int s5pv210_gpiolib_init(void) } samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); + s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); return 0; } diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index 79a7b1c5a57e..cd87d3256e03 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -29,7 +30,16 @@ #define PEND_OFFSET 0xA00 #define REG_OFFSET(x) ((x) << 2) -static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR]; +struct s5p_gpioint_bank { + struct list_head list; + int start; + int nr_groups; + int irq; + struct s3c_gpio_chip **chips; + void (*handler)(unsigned int, struct irq_desc *); +}; + +LIST_HEAD(banks); static int s5p_gpioint_get_offset(struct irq_data *data) { @@ -139,11 +149,12 @@ static struct irq_chip s5p_gpioint = { static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) { + struct s5p_gpioint_bank *bank = get_irq_data(irq); int group, pend_offset, mask_offset; unsigned int pend, mask; - for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) { - struct s3c_gpio_chip *chip = irq_chips[group]; + for (group = 0; group < bank->nr_groups; group++) { + struct s3c_gpio_chip *chip = bank->chips[group]; if (!chip) continue; @@ -168,23 +179,44 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) { static int used_gpioint_groups = 0; - static bool handler_registered = 0; int irq, group = chip->group; int i; + struct s5p_gpioint_bank *bank = NULL; if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) return -ENOMEM; + list_for_each_entry(bank, &banks, list) { + if (group >= bank->start && + group < bank->start + bank->nr_groups) + break; + } + if (!bank) + return -EINVAL; + + if (!bank->handler) { + bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) * + bank->nr_groups, GFP_KERNEL); + if (!bank->chips) + return -ENOMEM; + + set_irq_chained_handler(bank->irq, s5p_gpioint_handler); + set_irq_data(bank->irq, bank); + bank->handler = s5p_gpioint_handler; + printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", + bank->irq); + } + + /* + * chained GPIO irq has been sucessfully registered, allocate new gpio + * int group and assign irq nubmers + */ + chip->irq_base = S5P_GPIOINT_BASE + used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE; used_gpioint_groups++; - if (!handler_registered) { - set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler); - handler_registered = 1; - } - - irq_chips[group] = chip; + bank->chips[group - bank->start] = chip; for (i = 0; i < chip->chip.ngpio; i++) { irq = chip->irq_base + i; set_irq_chip(irq, &s5p_gpioint); @@ -221,3 +253,19 @@ int __init s5p_register_gpio_interrupt(int pin) } return ret; } + +int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups) +{ + struct s5p_gpioint_bank *bank; + + bank = kzalloc(sizeof(*bank), GFP_KERNEL); + if (!bank) + return -ENOMEM; + + bank->start = start; + bank->nr_groups = nr_groups; + bank->irq = chain_irq; + + list_add_tail(&bank->list, &banks); + return 0; +} diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index e4b5cf126fa9..5e04fa6eda74 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -225,4 +225,20 @@ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); */ extern int s5p_register_gpio_interrupt(int pin); +/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt + * registration (see s5p_register_gpio_interrupt function) + * @chain_irq: chained irq number for the gpio int handler for this bank + * @start: start gpio group number of this bank + * @nr_groups: number of gpio groups handled by this bank + * + * This functions registers initial information about gpio banks that + * can be later used by the s5p_register_gpio_interrupt() function to + * enable support for gpio interrupt for particular gpio group. + */ +#ifdef CONFIG_S5P_GPIO_INT +extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups); +#else +#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0) +#endif + #endif /* __PLAT_GPIO_CFG_H */ -- cgit v1.2.3