From 7af36b9787e19b4cbde9ee984e431d64b586784e Mon Sep 17 00:00:00 2001 From: Sunyoung Kang Date: Sat, 18 Sep 2010 10:59:31 +0900 Subject: ARM: S5PV310: Update CMU registers for CPUFREQ This patch adds CMU(Clock Management Unit) registers for S5PV310/S5PC210 CPUFREQ driver and modifies some register names according to datasheet. Signed-off-by: Sunyoung Kang Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-s5pv310/clock.c') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 58c9d33f36fe..fdce2b48efc6 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = { .id = -1, }, .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, + .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, }; static struct clksrc_clk clk_sclk_dmc = { @@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = { .id = -1, .parent = &clk_mout_corebus.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, }; static struct clksrc_clk clk_aclk_cored = { @@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = { .id = -1, .parent = &clk_sclk_dmc.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, }; static struct clksrc_clk clk_aclk_corep = { @@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = { .id = -1, .parent = &clk_aclk_cored.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, }; static struct clksrc_clk clk_aclk_acp = { @@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = { .id = -1, .parent = &clk_mout_corebus.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, }; static struct clksrc_clk clk_pclk_acp = { @@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = { .id = -1, .parent = &clk_aclk_acp.clk, }, - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, + .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, }; /* Core list of CMU_TOP side */ -- cgit v1.2.3 From 877d1b571d7763dbf57e38de2827177ad5369e64 Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Thu, 23 Dec 2010 14:25:31 +0900 Subject: ARM: S5PV310: Add FOUT APLL get rate function FOUT APLL clock is used as a source of ARM core clock. So we need that the clock source can be changed dynamically by using CPUFREQ driver. This patch can give correct frequency when calling clk_get_rate() function. Signed-off-by: Jaecheol Lee Signed-off-by: Sangwook Ju Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310/clock.c') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index fdce2b48efc6..752a07ed7c19 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -990,6 +990,17 @@ static struct clksrc_clk *sysclks[] = { &clk_dout_mmc4, }; +static int xtal_rate; + +static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk) +{ + return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); +} + +static struct clk_ops s5pv310_fout_apll_ops = { + .get_rate = s5pv310_fout_apll_get_rate, +}; + void __init_or_cpufreq s5pv310_setup_clocks(void) { struct clk *xtal_clk; @@ -1013,6 +1024,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); + + xtal_rate = xtal; + clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); @@ -1026,7 +1040,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), __raw_readl(S5P_VPLL_CON1), pll_4650); - clk_fout_apll.rate = apll; + clk_fout_apll.ops = &s5pv310_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; -- cgit v1.2.3 From 3055c6dad620af9e2c5432feb5ec7d5ac46d54b0 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:54:35 +0900 Subject: ARM: S5PV310: Add PDMA clocks Define PDMA clocks for the controller 0 and 1. Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/mach-s5pv310/clock.c') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 58c9d33f36fe..ace8f52aa04f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -466,6 +466,16 @@ static struct clk init_clocks_disable[] = { .id = -1, .enable = s5pv310_clk_ip_fsys_ctrl, .ctrlbit = (1 << 10), + }, { + .name = "pdma", + .id = 0, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "pdma", + .id = 1, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), }, { .name = "adc", .id = -1, -- cgit v1.2.3 From aa227557dde1d8de2eba19655320d4af360054fd Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:54:57 +0900 Subject: ARM: S5PV310: Add AC97 clock Define clock for the AC97 controller. Signed-off-by: Jassi Brar Acked-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-s5pv310/clock.c') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index ace8f52aa04f..189198a8fd6f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -516,6 +516,11 @@ static struct clk init_clocks_disable[] = { .id = 2, .enable = s5pv310_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), + }, { + .name = "ac97", + .id = -1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 27), }, { .name = "fimg2d", .id = -1, -- cgit v1.2.3 From 2d27043f7b7692252cc76aa13a95b4ff88558977 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 21 Dec 2010 09:57:03 +0900 Subject: ARM: S5PV310: Define I2S clocks Define missing controller clocks for the I2S-0, 1 and 2 blocks. Signed-off-by: Jassi Brar Acked-by: Mark Brown [kgene.kim@samsung.com: Added description] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/mach-s5pv310/clock.c') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 189198a8fd6f..6d22c43c6ee8 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -516,6 +516,21 @@ static struct clk init_clocks_disable[] = { .id = 2, .enable = s5pv310_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), + }, { + .name = "iis", + .id = 0, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 19), + }, { + .name = "iis", + .id = 1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 20), + }, { + .name = "iis", + .id = 2, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 21), }, { .name = "ac97", .id = -1, -- cgit v1.2.3 From 957c461e82f7a8ddcd7fb25c01c43917f64fde33 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Tue, 4 Jan 2011 17:58:22 +0900 Subject: ARM: S5PV310: Tidy init+disable clock usage and s3c24xx_register_clocks cleanup This patch changes the clock registration code to use the s3c_register_clocks() followed by s3c_disable_clocks() instead of the loops it was using and cleanups the return of s3c24xx_register_clocks() because it includes it. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'arch/arm/mach-s5pv310/clock.c') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 58c9d33f36fe..fdd477696b9a 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -384,7 +384,7 @@ static struct clksrc_clk clk_sclk_vpll = { .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, }; -static struct clk init_clocks_disable[] = { +static struct clk init_clocks_off[] = { { .name = "timers", .id = -1, @@ -1061,13 +1061,9 @@ static struct clk *clks[] __initdata = { void __init s5pv310_register_clocks(void) { - struct clk *clkp; - int ret; int ptr; - ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - if (ret > 0) - printk(KERN_ERR "Failed to register %u clocks\n", ret); + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); @@ -1075,15 +1071,8 @@ void __init s5pv310_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - (clkp->enable)(clkp, 0); - } + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_pwmclk_init(); } -- cgit v1.2.3