From b7806dc7cba840ea538706621486475d93a53c55 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 8 Feb 2013 22:50:58 +0530 Subject: ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method While waking up CPU from off state using clock domain force wakeup, restore the CPU power state to ON state before putting CPU clock domain under hardware control. Otherwise CPU wakeup might fail. The change is recommended for all OMAP4+ devices though the PRCM weakness was observed on OMAP5 devices first. As a result of weakness, lock-up is observed inside the hardware state machine of local CPU PRCM and results are UN-predictable as per designers. In software testing, we have seen hard-locks most of the time where system gets frozen. With power domain state restored, system behaves correctly. So update the code accordingly. Acked-by: Nishanth Menon Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap-smp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/omap-smp.c') diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 0cbb677c4df4..e4441cc7aca2 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -83,6 +83,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * { static struct clockdomain *cpu1_clkdm; static bool booted; + static struct powerdomain *cpu1_pwrdm; void __iomem *base = omap_get_wakeupgen_base(); /* @@ -102,8 +103,10 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * else __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); - if (!cpu1_clkdm) + if (!cpu1_clkdm && !cpu1_pwrdm) { cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); + cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm"); + } /* * The SGI(Software Generated Interrupts) are not wakeup capable @@ -116,7 +119,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * * Section : * 4.3.4.2 Power States of CPU0 and CPU1 */ - if (booted) { + if (booted && cpu1_pwrdm && cpu1_clkdm) { /* * GIC distributor control register has changed between * CortexA9 r1pX and r2pX. The Control Register secure @@ -137,7 +140,12 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * gic_dist_disable(); } + /* + * Ensure that CPU power state is set to ON to avoid CPU + * powerdomain transition on wfi + */ clkdm_wakeup(cpu1_clkdm); + omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON); clkdm_allow_idle(cpu1_clkdm); if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { -- cgit v1.2.3