From 257d643d7d7cd81075b6dee88cfba14f773805c7 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Sat, 2 Jul 2011 08:00:24 +0530 Subject: OMAP4: clocks: Update the clock tree with 4460 clock nodes Add the new clock nodes (bandgap_ts_fclk, div_ts_ck) for omap4460. Handle these nodes using the clock flags (CK_*). Signed-off-by: Rajendra Nayak Signed-off-by: Nishanth Menon Signed-off-by: Benoit Cousson Reviewed-by: Kevin Hilman Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock44xx_data.c | 39 ++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8c965671b4d4..639e00e0eac2 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1486,6 +1486,40 @@ static struct clk dss_dss_clk = { .recalc = &followparent_recalc, }; +static const struct clksel_rate div3_8to32_rates[] = { + { .div = 8, .val = 0, .flags = RATE_IN_44XX }, + { .div = 16, .val = 1, .flags = RATE_IN_44XX }, + { .div = 32, .val = 2, .flags = RATE_IN_44XX }, + { .div = 0 }, +}; + +static const struct clksel div_ts_div[] = { + { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates }, + { .parent = NULL }, +}; + +static struct clk div_ts_ck = { + .name = "div_ts_ck", + .parent = &l4_wkup_clk_mux_ck, + .clksel = div_ts_div, + .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk bandgap_ts_fclk = { + .name = "bandgap_ts_fclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &div_ts_ck, + .recalc = &followparent_recalc, +}; + static struct clk dss_48mhz_clk = { .name = "dss_48mhz_clk", .ops = &clkops_omap2_dflt, @@ -3110,7 +3144,9 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), @@ -3293,6 +3329,9 @@ int __init omap4xxx_clk_init(void) if (cpu_is_omap44xx()) { cpu_mask = RATE_IN_4430; cpu_clkflg = CK_443X; + } else if (cpu_is_omap446x()) { + cpu_mask = RATE_IN_4460; + cpu_clkflg = CK_446X; } clk_init(&omap2_clk_functions); -- cgit v1.2.3 From 962519e07e44bdeb381fdc7689361a144fe3491c Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Sat, 9 Jul 2011 19:14:45 -0600 Subject: OMAP4: clock data: Add sddiv to USB DPLL The USB DPLL is a J-Type DPLL with the sddiv extra parameter. Add it in USB DPLL. Signed-off-by: Benoit Cousson Cc: Paul Walmsley [paul@pwsan.com: dropped UNIPRO change since it is removed in a later patch] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8c965671b4d4..f28a9c943cfc 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1015,6 +1015,7 @@ static struct dpll_data dpll_usb_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, .max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_divider = OMAP4430_MAX_DPLL_DIV, .min_divider = 1, -- cgit v1.2.3 From 6629f3c47006dd00db0b87ce02a55a16ecacfbbf Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Sat, 9 Jul 2011 19:14:45 -0600 Subject: OMAP4: clock data: Remove usb_host_fs clkdev with NULL dev usb_host_fs_fck does have a clkdev mapping with "usbhs-omap.0" and "fs_fck" alias used by the driver. The entry with NULL dev is thus not needed anymore. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Felipe Balbi Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index f28a9c943cfc..0fa1cb88331c 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3205,7 +3205,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), @@ -3217,7 +3216,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), @@ -3227,7 +3225,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), -- cgit v1.2.3 From 7ecd4228b48192890220e1fd1b39c8bd2988aa80 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Sat, 9 Jul 2011 19:14:45 -0600 Subject: OMAP4: clock data: Re-order some clock nodes and structure fields A couple of fieds were edited manually and thus do not stick to the template used by the generator and by other structures. Move them to the correct location. Signed-off-by: Benoit Cousson Cc: Paul Walmsley [paul@pwsan.com: dropped the UNIPRO changes since those will be removed in a later patch] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 66 +++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 32 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 0fa1cb88331c..4b57d55f5a11 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = { static struct clk pad_clks_ck = { .name = "pad_clks_ck", .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_CLKSEL_ABE, + .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, }; static struct clk pad_slimbus_core_clks_ck = { @@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = { static struct clk slimbus_clk = { .name = "slimbus_clk", .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_CLKSEL_ABE, + .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, }; static struct clk sys_32k_ck = { @@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = { static struct clk dpll_abe_x2_ck = { .name = "dpll_abe_x2_ck", .parent = &dpll_abe_ck, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .flags = CLOCK_CLKOUTX2, .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap3_clkoutx2_recalc, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, }; static const struct clksel_rate div31_1to31_rates[] = { @@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = { .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, }; static struct clk dpll_core_m7x2_ck = { @@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = { static struct clk dpll_per_x2_ck = { .name = "dpll_per_x2_ck", .parent = &dpll_per_ck, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, .flags = CLOCK_CLKOUTX2, .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap3_clkoutx2_recalc, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, }; static const struct clksel dpll_per_m2x2_div[] = { @@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = { .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, }; static struct clk dpll_per_m4x2_ck = { @@ -970,8 +970,9 @@ static struct clk dpll_unipro_ck = { static struct clk dpll_unipro_x2_ck = { .name = "dpll_unipro_x2_ck", .parent = &dpll_unipro_ck, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap3_clkoutx2_recalc, }; @@ -1036,8 +1037,8 @@ static struct clk dpll_usb_ck = { static struct clk dpll_usb_clkdcoldo_ck = { .name = "dpll_usb_clkdcoldo_ck", .parent = &dpll_usb_ck, - .ops = &clkops_omap4_dpllmx_ops, .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &followparent_recalc, }; @@ -1847,8 +1848,8 @@ static struct clk l3_instr_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", .flags = ENABLE_ON_INIT, + .clkdm_name = "l3_instr_clkdm", .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -1858,8 +1859,8 @@ static struct clk l3_main_3_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", .flags = ENABLE_ON_INIT, + .clkdm_name = "l3_instr_clkdm", .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -2163,8 +2164,8 @@ static struct clk ocp_wp_noc_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_instr_clkdm", .flags = ENABLE_ON_INIT, + .clkdm_name = "l3_instr_clkdm", .parent = &l3_div_ck, .recalc = &followparent_recalc, }; @@ -2896,6 +2897,7 @@ static struct clk auxclk2_ck = { .enable_reg = OMAP4_SCRM_AUXCLK2, .enable_bit = OMAP4_ENABLE_SHIFT, }; + static struct clk auxclk3_ck = { .name = "auxclk3_ck", .parent = &sys_clkin_ck, @@ -3217,7 +3219,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), - CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), @@ -3226,15 +3227,25 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), @@ -3251,6 +3262,7 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), @@ -3268,19 +3280,9 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), + CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), - CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), }; int __init omap4xxx_clk_init(void) -- cgit v1.2.3 From 628479a8ea5d32ef26ba0b4eb26f8d6712a574ec Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Sat, 9 Jul 2011 19:14:46 -0600 Subject: OMAP4: clock data: Fix max mult and div for USB DPLL The DPLL USB can generate higher speed (x2) than the regular ones. The max multiplication value is then twice the previous value. Fix both max_mult and max_div with that correct values. Change the max_div variable type to u16 to allow storing up to 256. Replace as well the define with the value to avoid unneeded indirection and provide a better readability. Remove the defines that become useless. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx.h | 7 ------- arch/arm/mach-omap2/clock44xx_data.c | 29 ++++++++++++++--------------- arch/arm/plat-omap/include/plat/clock.h | 2 +- 3 files changed, 15 insertions(+), 23 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h index 6be1095936db..7ceb870e7ab8 100644 --- a/arch/arm/mach-omap2/clock44xx.h +++ b/arch/arm/mach-omap2/clock44xx.h @@ -8,13 +8,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H -/* - * XXX Missing values for the OMAP4 DPLL_USB - * XXX Missing min_multiplier values for all OMAP4 DPLLs - */ -#define OMAP4430_MAX_DPLL_MULT 2047 -#define OMAP4430_MAX_DPLL_DIV 128 - int omap4xxx_clk_init(void); #endif diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 4b57d55f5a11..8307c9ebd309 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 2047, + .max_divider = 128, .min_divider = 1, }; @@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 2047, + .max_divider = 128, .min_divider = 1, }; @@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 2047, + .max_divider = 128, .min_divider = 1, }; @@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 2047, + .max_divider = 128, .min_divider = 1, }; @@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 2047, + .max_divider = 128, .min_divider = 1, }; @@ -949,9 +949,8 @@ static struct dpll_data dpll_unipro_dd = { .enable_mask = OMAP4430_DPLL_EN_MASK, .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 2047, + .max_divider = 128, .min_divider = 1, }; @@ -1017,8 +1016,8 @@ static struct dpll_data dpll_usb_dd = { .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, - .max_multiplier = OMAP4430_MAX_DPLL_MULT, - .max_divider = OMAP4430_MAX_DPLL_DIV, + .max_multiplier = 4095, + .max_divider = 256, .min_divider = 1, }; diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 006e599c6613..f57e0649ab30 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -152,7 +152,7 @@ struct dpll_data { u16 max_multiplier; u8 last_rounded_n; u8 min_divider; - u8 max_divider; + u16 max_divider; u8 modes; #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) void __iomem *autoidle_reg; -- cgit v1.2.3 From de474535763c1a5c50cb26f34ec60f10aebc53fe Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Sat, 9 Jul 2011 19:14:47 -0600 Subject: OMAP4: clock data: Remove McASP2, McASP3 and MMC6 clocks McASP2, 3 and MMC6 modules are not present in the OMAP4 family. Remove the fclk and the clksel related to these nodes. Rename the references that were potentially re-used in order nodes. Remove related macros in prcm header files. Update TI copyright date. Signed-off-by: Jon Hunter [b-cousson@ti.com: Update the patch according to autogen output] Signed-off-by: Benoit Cousson [paul@pwsan.com: split PRCM data changes into a separate patch] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 86 +++++++++++++----------------------- 1 file changed, 31 insertions(+), 55 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8307c9ebd309..96bc668c74b3 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1170,19 +1170,6 @@ static struct clk func_96m_fclk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel hsmmc6_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk hsmmc6_fclk = { - .name = "hsmmc6_fclk", - .parent = &func_64m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - static const struct clksel_rate div2_1to8_rates[] = { { .div = 1, .val = 0, .flags = RATE_IN_4430 }, { .div = 8, .val = 1, .flags = RATE_IN_4430 }, @@ -1265,6 +1252,21 @@ static struct clk l4_wkup_clk_mux_ck = { .recalc = &omap2_clksel_recalc, }; +static struct clk ocp_abe_iclk = { + .name = "ocp_abe_iclk", + .parent = &aess_fclk, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk per_abe_24m_fclk = { + .name = "per_abe_24m_fclk", + .parent = &dpll_abe_m2_ck, + .ops = &clkops_null, + .fixed_div = 4, + .recalc = &omap_fixed_divisor_recalc, +}; + static const struct clksel per_abe_nc_fclk_div[] = { { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, { .parent = NULL }, @@ -1282,41 +1284,6 @@ static struct clk per_abe_nc_fclk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel mcasp2_fclk_sel[] = { - { .parent = &func_96m_fclk, .rates = div_1_0_rates }, - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk mcasp2_fclk = { - .name = "mcasp2_fclk", - .parent = &func_96m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp3_fclk = { - .name = "mcasp3_fclk", - .parent = &func_96m_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk ocp_abe_iclk = { - .name = "ocp_abe_iclk", - .parent = &aess_fclk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk per_abe_24m_fclk = { - .name = "per_abe_24m_fclk", - .parent = &dpll_abe_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; - static const struct clksel pmd_stm_clock_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, @@ -1996,10 +1963,16 @@ static struct clk mcbsp3_fck = { .clkdm_name = "abe_clkdm", }; +static const struct clksel mcbsp4_sync_mux_sel[] = { + { .parent = &func_96m_fclk, .rates = div_1_0_rates }, + { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + static struct clk mcbsp4_sync_mux_ck = { .name = "mcbsp4_sync_mux_ck", .parent = &func_96m_fclk, - .clksel = mcasp2_fclk_sel, + .clksel = mcbsp4_sync_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, @@ -2078,11 +2051,17 @@ static struct clk mcspi4_fck = { .recalc = &followparent_recalc, }; +static const struct clksel hsmmc1_fclk_sel[] = { + { .parent = &func_64m_fclk, .rates = div_1_0_rates }, + { .parent = &func_96m_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + /* Merged hsmmc1_fclk into mmc1 */ static struct clk mmc1_fck = { .name = "mmc1_fck", .parent = &func_64m_fclk, - .clksel = hsmmc6_fclk_sel, + .clksel = hsmmc1_fclk_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -2097,7 +2076,7 @@ static struct clk mmc1_fck = { static struct clk mmc2_fck = { .name = "mmc2_fck", .parent = &func_64m_fclk, - .clksel = hsmmc6_fclk_sel, + .clksel = hsmmc1_fclk_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -3094,17 +3073,14 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), - CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), - CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), - CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), -- cgit v1.2.3 From 571078aa3485073964b611493eee480b5dc3c084 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Sat, 9 Jul 2011 19:14:47 -0600 Subject: OMAP4: clock data: Remove UNIPRO clock nodes UNIPRO was removed from OMAP4 devices from ES2.0 onwards. Since this IP was anyway non-functional and not supported, it is best to remove it completely. Signed-off-by: Jon Hunter [b-cousson@ti.com: Update the changelog] Signed-off-by: Benoit Cousson [paul@pwsan.com: split PRCM header file changes into a separate patch] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 60 ------------------------------------ 1 file changed, 60 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 96bc668c74b3..044df38f65ce 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = { .set_rate = &omap2_clksel_set_rate, }; -/* DPLL_UNIPRO */ -static struct dpll_data dpll_unipro_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static struct clk dpll_unipro_ck = { - .name = "dpll_unipro_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_unipro_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_unipro_x2_ck = { - .name = "dpll_unipro_x2_ck", - .parent = &dpll_unipro_ck, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_unipro_m2x2_div[] = { - { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_unipro_m2x2_ck = { - .name = "dpll_unipro_m2x2_ck", - .parent = &dpll_unipro_x2_ck, - .clksel = dpll_unipro_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - static struct clk usb_hs_clk_div_ck = { .name = "usb_hs_clk_div_ck", .parent = &dpll_abe_m3x2_ck, @@ -3058,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), - CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), - CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), - CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), -- cgit v1.2.3 From 3a23aafcde66f6327bda0a6423586dfd8d694eb4 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Sat, 9 Jul 2011 20:39:44 -0600 Subject: OMAP4: hwmod data: Modify DSS opt clocks Add missing DSS optional clocks to HWMOD data for OMAP4xxx. Add HWMOD_CONTROL_OPT_CLKS_IN_RESET flag for dispc to fix dispc reset. Signed-off-by: Tomi Valkeinen [b-cousson@ti.com: Remove a comment and update the subject] Signed-off-by: Benoit Cousson Cc: Tomi Valkeinen [paul@pwsan.com: removed DSS "fck" role and some clkdev aliases at Tomi's request] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 8 ++++---- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 33 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 044df38f65ce..7a0b112f2207 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3032,10 +3032,10 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), - CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), - CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), - CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), CLK("omapdss_dss", "ick", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index e01143725b08..a7fbe5cb81d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1267,9 +1267,16 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { &omap44xx_l4_per__dss_dispc, }; +static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, + { .role = "tv_clk", .clk = "dss_tv_clk" }, + { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, +}; + static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_dss_dispc_irqs, .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, .main_clk = "dss_fck", @@ -1278,6 +1285,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, }, }, + .opt_clks = dss_dispc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks), .slaves = omap44xx_dss_dispc_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -1358,6 +1367,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { &omap44xx_l4_per__dss_dsi1, }; +static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .name = "dss_dsi1", .class = &omap44xx_dsi_hwmod_class, @@ -1369,6 +1382,8 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, }, }, + .opt_clks = dss_dsi1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), .slaves = omap44xx_dss_dsi1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -1428,6 +1443,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { &omap44xx_l4_per__dss_dsi2, }; +static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .name = "dss_dsi2", .class = &omap44xx_dsi_hwmod_class, @@ -1439,6 +1458,8 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, }, }, + .opt_clks = dss_dsi2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), .slaves = omap44xx_dss_dsi2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -1518,6 +1539,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { &omap44xx_l4_per__dss_hdmi, }; +static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .name = "dss_hdmi", .class = &omap44xx_hdmi_hwmod_class, @@ -1529,6 +1554,8 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, }, }, + .opt_clks = dss_hdmi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), .slaves = omap44xx_dss_hdmi_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -1603,6 +1630,10 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { &omap44xx_l4_per__dss_rfbi, }; +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_fck" }, +}; + static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .name = "dss_rfbi", .class = &omap44xx_rfbi_hwmod_class, @@ -1613,6 +1644,8 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, }, }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), .slaves = omap44xx_dss_rfbi_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -- cgit v1.2.3 From 93cac2ad0f9459422d0af79b6937d6e83ed3aec9 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sat, 9 Jul 2011 20:42:59 -0600 Subject: OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by L3 interconnect. Because of CPU speculative nature, such accesses are possible which can lead to indirect access to GPMC and if it's clock is not running, it can result in hang/abort on the platform. Above makes access to GPMC unpredictable during the execution, so it's module mode needs to be kept under hardware control instead of software control. Since the auto gating is supported for GPMC, there isn't any power impact because of this change. The issue was un-covered with security middleware running along with HLOS. In this case GPMC had a valid MMU descriptor on secure side where as HLOS didn't map the GMPC because it isn't being used. Signed-off-by: Santosh Shilimkar [b-cousson@ti.com: Update subject and fix typos in the changelog] Signed-off-by: Benoit Cousson Cc: Kevin Hilman Cc: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8c965671b4d4..72a3976d6c43 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1694,6 +1694,7 @@ static struct clk gpmc_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .flags = ENABLE_ON_INIT, .clkdm_name = "l3_2_clkdm", .parent = &l3_div_ck, .recalc = &followparent_recalc, -- cgit v1.2.3 From bf1e0776cf5e4ef2622de3a4b63f84175b5b48ab Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Sun, 10 Jul 2011 05:54:12 -0600 Subject: OMAP: omap_device: Create clkdev entry for hwmod main_clk Extend the existing function to create clkdev for every optional clocks to add a well one "fck" alias for the main_clk of the omap_hwmod. It will allow to remove these static clkdev entries from the clockXXX_data.c file. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Kevin Hilman Cc: Todd Poynor [paul@pwsan.com: remove all of the "fck" role clkdev aliases from the clock data files; fixed error message] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2420_data.c | 22 +++++----- arch/arm/mach-omap2/clock2430_data.c | 32 +++++++------- arch/arm/mach-omap2/clock3xxx_data.c | 44 +++++++++---------- arch/arm/mach-omap2/clock44xx_data.c | 38 ++++++++-------- arch/arm/plat-omap/omap_device.c | 85 +++++++++++++++++++++--------------- 5 files changed, 118 insertions(+), 103 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 2926d028b6e9..debc040872f1 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_242X), - CLK("omapdss_dss", "fck", &dss1_fck, CK_242X), - CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X), - CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), @@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), @@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), - CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), @@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "eac_ick", &eac_ick, CK_242X), CLK(NULL, "eac_fck", &eac_fck, CK_242X), CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), - CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), - CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), - CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 0c79d39e3021..96a942e42db1 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ CLK("omapdss_dss", "ick", &dss_ick, CK_243X), - CLK("omapdss_dss", "fck", &dss1_fck, CK_243X), - CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X), - CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), @@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), - CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), @@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), - CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), @@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = { CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), - CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X), + CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), - CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X), + CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), @@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), - CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X), + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), - CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X), + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 75b119bd9cda..ffd55b1c4396 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3289,25 +3289,25 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), - CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX), + CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), - CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX), - CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), - CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), - CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), - CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), - CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), @@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), - CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX), - CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX), - CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), + CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), + CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), @@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), - CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), + CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), @@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 257882028492..763507f54339 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3057,12 +3057,12 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), - CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), + CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), - CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), - CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), - CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), + CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), @@ -3073,23 +3073,23 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), - CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), - CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), - CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), - CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), - CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), - CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), - CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), + CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), + CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), + CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), + CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), + CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), @@ -3146,7 +3146,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index c8b9cd1716ba..be45147651cb 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -236,56 +236,71 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) return 0; } +static void _add_clkdev(struct omap_device *od, const char *clk_alias, + const char *clk_name) +{ + struct clk *r; + struct clk_lookup *l; + + if (!clk_alias || !clk_name) + return; + + pr_debug("omap_device: %s: Creating %s -> %s\n", + dev_name(&od->pdev.dev), clk_alias, clk_name); + + r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias); + if (!IS_ERR(r)) { + pr_warning("omap_device: %s: alias %s already exists\n", + dev_name(&od->pdev.dev), clk_alias); + clk_put(r); + return; + } + + r = omap_clk_get_by_name(clk_name); + if (IS_ERR(r)) { + pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n", + dev_name(&od->pdev.dev), clk_name); + return; + } + + l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev)); + if (!l) { + pr_err("omap_device: %s: clkdev_alloc for %s failed\n", + dev_name(&od->pdev.dev), clk_alias); + return; + } + + clkdev_add(l); +} + /** - * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks + * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks + * and main clock * @od: struct omap_device *od + * @oh: struct omap_hwmod *oh * - * For every optional clock present per hwmod per omap_device, this function - * adds an entry in the clkdev table of the form - * if it does not exist already. + * For the main clock and every optional clock present per hwmod per + * omap_device, this function adds an entry in the clkdev table of the + * form if it does not exist already. * * The function is called from inside omap_device_build_ss(), after * omap_device_register. * * This allows drivers to get a pointer to its optional clocks based on its role * by calling clk_get(, ). + * In the case of the main clock, a "fck" alias is used. * * No return value. */ -static void _add_optional_clock_clkdev(struct omap_device *od, - struct omap_hwmod *oh) +static void _add_hwmod_clocks_clkdev(struct omap_device *od, + struct omap_hwmod *oh) { int i; - for (i = 0; i < oh->opt_clks_cnt; i++) { - struct omap_hwmod_opt_clk *oc; - struct clk *r; - struct clk_lookup *l; - - oc = &oh->opt_clks[i]; - - if (!oc->_clk) - continue; - - r = clk_get_sys(dev_name(&od->pdev.dev), oc->role); - if (!IS_ERR(r)) - continue; /* clkdev entry exists */ + _add_clkdev(od, "fck", oh->main_clk); - r = omap_clk_get_by_name((char *)oc->clk); - if (IS_ERR(r)) { - pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n", - dev_name(&od->pdev.dev), oc->clk); - continue; - } - - l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev)); - if (!l) { - pr_err("omap_device: %s: clkdev_alloc for %s failed\n", - dev_name(&od->pdev.dev), oc->role); - return; - } - clkdev_add(l); - } + for (i = 0; i < oh->opt_clks_cnt; i++) + _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk); } @@ -492,7 +507,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, for (i = 0; i < oh_cnt; i++) { hwmods[i]->od = od; - _add_optional_clock_clkdev(od, hwmods[i]); + _add_hwmod_clocks_clkdev(od, hwmods[i]); } if (ret) -- cgit v1.2.3 From ad03f1cb2d44257afa63a2171e84daad931c48cb Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Sun, 10 Jul 2011 05:56:14 -0600 Subject: OMAP4: clock data: Add missing divider selection for auxclks On OMAP4 the auxclk nodes (part of SCRM) support both divider as well as parent selection. Supporting this requires splitting the existing nodes (which support only parent selection) into two nodes, one for parent and another for divider selection. The nodes for parent selection are named auxclk*_src_ck and the ones for divider selection as auxclk*_ck. Signed-off-by: Rajendra Nayak [b-cousson@ti.com: Rebase on top of clock cleanup and autogen alignement] Signed-off-by: Benoit Cousson Cc: Paul Walmsley Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 176 ++++++++++++++++++++++++++++++----- 1 file changed, 152 insertions(+), 24 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 257882028492..2fcdb8d3b515 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -2774,19 +2774,39 @@ static struct clk trace_clk_div_ck = { /* SCRM aux clk nodes */ -static const struct clksel auxclk_sel[] = { +static const struct clksel auxclk_src_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, { .parent = NULL }, }; -static struct clk auxclk0_ck = { - .name = "auxclk0_ck", +static const struct clksel_rate div16_1to16_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 3, .val = 2, .flags = RATE_IN_4430 }, + { .div = 4, .val = 3, .flags = RATE_IN_4430 }, + { .div = 5, .val = 4, .flags = RATE_IN_4430 }, + { .div = 6, .val = 5, .flags = RATE_IN_4430 }, + { .div = 7, .val = 6, .flags = RATE_IN_4430 }, + { .div = 8, .val = 7, .flags = RATE_IN_4430 }, + { .div = 9, .val = 8, .flags = RATE_IN_4430 }, + { .div = 10, .val = 9, .flags = RATE_IN_4430 }, + { .div = 11, .val = 10, .flags = RATE_IN_4430 }, + { .div = 12, .val = 11, .flags = RATE_IN_4430 }, + { .div = 13, .val = 12, .flags = RATE_IN_4430 }, + { .div = 14, .val = 13, .flags = RATE_IN_4430 }, + { .div = 15, .val = 14, .flags = RATE_IN_4430 }, + { .div = 16, .val = 15, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + +static struct clk auxclk0_src_ck = { + .name = "auxclk0_src_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_omap2_dflt, - .clksel = auxclk_sel, + .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK0, .clksel_mask = OMAP4_SRCSELECT_MASK, .recalc = &omap2_clksel_recalc, @@ -2794,12 +2814,29 @@ static struct clk auxclk0_ck = { .enable_bit = OMAP4_ENABLE_SHIFT, }; -static struct clk auxclk1_ck = { - .name = "auxclk1_ck", +static const struct clksel auxclk0_sel[] = { + { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk0_ck = { + .name = "auxclk0_ck", + .parent = &auxclk0_src_ck, + .clksel = auxclk0_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK0, + .clksel_mask = OMAP4_CLKDIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk auxclk1_src_ck = { + .name = "auxclk1_src_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_omap2_dflt, - .clksel = auxclk_sel, + .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK1, .clksel_mask = OMAP4_SRCSELECT_MASK, .recalc = &omap2_clksel_recalc, @@ -2807,12 +2844,29 @@ static struct clk auxclk1_ck = { .enable_bit = OMAP4_ENABLE_SHIFT, }; -static struct clk auxclk2_ck = { - .name = "auxclk2_ck", +static const struct clksel auxclk1_sel[] = { + { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk1_ck = { + .name = "auxclk1_ck", + .parent = &auxclk1_src_ck, + .clksel = auxclk1_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK1, + .clksel_mask = OMAP4_CLKDIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk auxclk2_src_ck = { + .name = "auxclk2_src_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_omap2_dflt, - .clksel = auxclk_sel, + .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK2, .clksel_mask = OMAP4_SRCSELECT_MASK, .recalc = &omap2_clksel_recalc, @@ -2820,12 +2874,29 @@ static struct clk auxclk2_ck = { .enable_bit = OMAP4_ENABLE_SHIFT, }; -static struct clk auxclk3_ck = { - .name = "auxclk3_ck", +static const struct clksel auxclk2_sel[] = { + { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk2_ck = { + .name = "auxclk2_ck", + .parent = &auxclk2_src_ck, + .clksel = auxclk2_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK2, + .clksel_mask = OMAP4_CLKDIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk auxclk3_src_ck = { + .name = "auxclk3_src_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_omap2_dflt, - .clksel = auxclk_sel, + .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK3, .clksel_mask = OMAP4_SRCSELECT_MASK, .recalc = &omap2_clksel_recalc, @@ -2833,12 +2904,29 @@ static struct clk auxclk3_ck = { .enable_bit = OMAP4_ENABLE_SHIFT, }; -static struct clk auxclk4_ck = { - .name = "auxclk4_ck", +static const struct clksel auxclk3_sel[] = { + { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk3_ck = { + .name = "auxclk3_ck", + .parent = &auxclk3_src_ck, + .clksel = auxclk3_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK3, + .clksel_mask = OMAP4_CLKDIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk auxclk4_src_ck = { + .name = "auxclk4_src_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_omap2_dflt, - .clksel = auxclk_sel, + .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK4, .clksel_mask = OMAP4_SRCSELECT_MASK, .recalc = &omap2_clksel_recalc, @@ -2846,12 +2934,29 @@ static struct clk auxclk4_ck = { .enable_bit = OMAP4_ENABLE_SHIFT, }; -static struct clk auxclk5_ck = { - .name = "auxclk5_ck", +static const struct clksel auxclk4_sel[] = { + { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk4_ck = { + .name = "auxclk4_ck", + .parent = &auxclk4_src_ck, + .clksel = auxclk4_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK4, + .clksel_mask = OMAP4_CLKDIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk auxclk5_src_ck = { + .name = "auxclk5_src_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, .ops = &clkops_omap2_dflt, - .clksel = auxclk_sel, + .clksel = auxclk_src_sel, .clksel_reg = OMAP4_SCRM_AUXCLK5, .clksel_mask = OMAP4_SRCSELECT_MASK, .recalc = &omap2_clksel_recalc, @@ -2859,6 +2964,23 @@ static struct clk auxclk5_ck = { .enable_bit = OMAP4_ENABLE_SHIFT, }; +static const struct clksel auxclk5_sel[] = { + { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates }, + { .parent = NULL }, +}; + +static struct clk auxclk5_ck = { + .name = "auxclk5_ck", + .parent = &auxclk5_src_ck, + .clksel = auxclk5_sel, + .clksel_reg = OMAP4_SCRM_AUXCLK5, + .clksel_mask = OMAP4_CLKDIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + static const struct clksel auxclkreq_sel[] = { { .parent = &auxclk0_ck, .rates = div_1_0_rates }, { .parent = &auxclk1_ck, .rates = div_1_1_rates }, @@ -3150,17 +3272,23 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), -- cgit v1.2.3 From 665d001338b494d6d62810aa99b4c0fa1a0884b9 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Sun, 10 Jul 2011 05:57:07 -0600 Subject: OMAP2+: hwmod: Follow the recommended PRCM module enable sequence On OMAP4, the PRCM recommended sequence for enabling a module after power-on-reset is: -1- Force clkdm to SW_WKUP -2- Enabling the clocks -3- Configure desired module mode to "enable" or "auto" -4- Wait for the desired module idle status to be FUNC -5- Program clkdm in HW_AUTO(if supported) This sequence applies to all older OMAPs' as well, however since they use autodeps, it makes sure that no clkdm is in IDLE, and hence not requiring a force SW_WKUP when a module is being enabled. OMAP4 does not need to support autodeps, because of the dyanamic dependency feature, wherein the HW takes care of waking up a clockdomain from idle and hence the module, whenever an interconnect access happens to the given module. Implementing the sequence for OMAP4 requires the clockdomain handling that is currently done in clock framework to be done as part of hwmod framework since the step -4- above to "Wait for the desired module idle status to be FUNC" is done as part of hwmod framework. Signed-off-by: Rajendra Nayak [b-cousson@ti.com: Adapt it to the new clkdm hwmod attribute and API] Signed-off-by: Benoit Cousson Cc: Paul Walmsley [paul@pwsan.com: dropped mach-omap2/clock.c changes; modified to only call the clockdomain code if oh->clkdm is set; disable clock->clockdomain interaction on OMAP4] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock44xx_data.c | 1 + arch/arm/mach-omap2/omap_hwmod.c | 70 +++++++++++++++++++++++++----------- 2 files changed, 51 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-omap2/clock44xx_data.c') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 257882028492..dc79b39abb8f 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3212,6 +3212,7 @@ int __init omap4xxx_clk_init(void) } clk_init(&omap2_clk_functions); + omap2_clk_disable_clkdm_control(); for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); c++) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 4424fee5cd5a..84cc0bdda3ae 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1437,6 +1437,7 @@ static int _reset(struct omap_hwmod *oh) static int _enable(struct omap_hwmod *oh) { int r; + int hwsup = 0; pr_debug("omap_hwmod: %s: enabling\n", oh->name); @@ -1448,14 +1449,6 @@ static int _enable(struct omap_hwmod *oh) return -EINVAL; } - /* Mux pins for device runtime if populated */ - if (oh->mux && (!oh->mux->enabled || - ((oh->_state == _HWMOD_STATE_IDLE) && - oh->mux->pads_dynamic))) - omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); - - _add_initiator_dep(oh, mpu_oh); - _enable_clocks(oh); /* * If an IP contains only one HW reset line, then de-assert it in order @@ -1466,23 +1459,56 @@ static int _enable(struct omap_hwmod *oh) oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) _deassert_hardreset(oh, oh->rst_lines[0].name); - r = _wait_target_ready(oh); - if (r) { - pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", - oh->name, r); - _disable_clocks(oh); + /* Mux pins for device runtime if populated */ + if (oh->mux && (!oh->mux->enabled || + ((oh->_state == _HWMOD_STATE_IDLE) && + oh->mux->pads_dynamic))) + omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); + + _add_initiator_dep(oh, mpu_oh); - return r; + if (oh->clkdm) { + /* + * A clockdomain must be in SW_SUP before enabling + * completely the module. The clockdomain can be set + * in HW_AUTO only when the module become ready. + */ + hwsup = clkdm_in_hwsup(oh->clkdm); + r = clkdm_hwmod_enable(oh->clkdm, oh); + if (r) { + WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", + oh->name, oh->clkdm->name, r); + return r; + } } + + _enable_clocks(oh); _enable_module(oh); - oh->_state = _HWMOD_STATE_ENABLED; + r = _wait_target_ready(oh); + if (!r) { + /* + * Set the clockdomain to HW_AUTO only if the target is ready, + * assuming that the previous state was HW_AUTO + */ + if (oh->clkdm && hwsup) + clkdm_allow_idle(oh->clkdm); - /* Access the sysconfig only if the target is ready */ - if (oh->class->sysc) { - if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) - _update_sysc_cache(oh); - _enable_sysc(oh); + oh->_state = _HWMOD_STATE_ENABLED; + + /* Access the sysconfig only if the target is ready */ + if (oh->class->sysc) { + if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) + _update_sysc_cache(oh); + _enable_sysc(oh); + } + } else { + _disable_clocks(oh); + pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", + oh->name, r); + + if (oh->clkdm) + clkdm_hwmod_disable(oh->clkdm, oh); } return r; @@ -1523,6 +1549,8 @@ static int _idle(struct omap_hwmod *oh) * transition to complete properly. */ _disable_clocks(oh); + if (oh->clkdm) + clkdm_hwmod_disable(oh->clkdm, oh); /* Mux pins for device idle if populated */ if (oh->mux && oh->mux->pads_dynamic) @@ -1620,6 +1648,8 @@ static int _shutdown(struct omap_hwmod *oh) pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", oh->name); _disable_clocks(oh); + if (oh->clkdm) + clkdm_hwmod_disable(oh->clkdm, oh); } /* XXX Should this code also force-disable the optional clocks? */ -- cgit v1.2.3