From 23759dc6430428897a36c4d493f611eca55c9481 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 2 Apr 2006 00:07:39 +0100 Subject: [ARM] 3439/2: xsc3: add I/O coherency support Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ixp23xx/pci.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-ixp23xx') diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index ba6b4367a1d5..ac72f94c5b4d 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -219,6 +219,12 @@ static void __init ixp23xx_pci_common_init(void) *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1); } else { *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1); + + /* + * Enable coherency on A2 silicon. + */ + if (arch_is_coherent()) + *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF; } } -- cgit v1.2.3