From 9fbbe6890c88aa332efe61d5894108dd8b932530 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 6 Sep 2011 14:39:44 +0800 Subject: arm/imx6q: add core drivers clock, gpc, mmdc and src It adds a number of core drivers support for imx6q, including clock, General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and System Reset Controller (src). Signed-off-by: Ranjani Vaidyanathan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/src.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 arch/arm/mach-imx/src.c (limited to 'arch/arm/mach-imx/src.c') diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c new file mode 100644 index 000000000000..36cacbd0dcc2 --- /dev/null +++ b/arch/arm/mach-imx/src.c @@ -0,0 +1,49 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#define SRC_SCR 0x000 +#define SRC_GPR1 0x020 +#define BP_SRC_SCR_CORE1_RST 14 +#define BP_SRC_SCR_CORE1_ENABLE 22 + +static void __iomem *src_base; + +void imx_enable_cpu(int cpu, bool enable) +{ + u32 mask, val; + + mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_SCR); + val = enable ? val | mask : val & ~mask; + writel_relaxed(val, src_base + SRC_SCR); +} + +void imx_set_cpu_jump(int cpu, void *jump_addr) +{ + writel_relaxed(BSYM(virt_to_phys(jump_addr)), + src_base + SRC_GPR1 + cpu * 8); +} + +void __init imx_src_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); + src_base = of_iomap(np, 0); + WARN_ON(!src_base); +} -- cgit v1.2.3