From ca61452bd74683e2b79fe5bbd3670e4e796ec8d3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 18 Jan 2021 11:08:47 +0530 Subject: ARM: qcom_defconfig: Enable DWC3 controller and PHYs Enable DWC3 controller, QMP PHY and SNPS HS PHY for using with platforms like SDX55. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210118053853.56224-8-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/configs/qcom_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/configs') diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 51eeefd264d3..77f234bf84c8 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -196,6 +196,7 @@ CONFIG_USB_CONFIGFS_ECM=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_ULPI_BUS=y CONFIG_USB_ETH=m +CONFIG_USB_DWC3=y CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -263,6 +264,8 @@ CONFIG_PHY_QCOM_APQ8064_SATA=y CONFIG_PHY_QCOM_IPQ806X_SATA=y CONFIG_PHY_QCOM_USB_HS=y CONFIG_PHY_QCOM_USB_HSIC=y +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_QCOM_QFPROM=y CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_QCOM=y -- cgit v1.2.3