From 4bf04fc458dfd2a3301a1b76b0dfa4741f7e59fe Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 3 Oct 2018 17:11:03 +0200 Subject: ARM: dts: stm32: Add dmas to timer on stm32mp157c Add DMAs to enable PWM input capture using STM32 timers on stm32mp157c. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 58 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 8bf1c17f8cef..2e9df63f9997 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -98,6 +98,12 @@ reg = <0x40000000 0x400>; clocks = <&rcc TIM2_K>; clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; status = "disabled"; pwm { @@ -119,6 +125,13 @@ reg = <0x40001000 0x400>; clocks = <&rcc TIM3_K>; clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm { @@ -140,6 +153,11 @@ reg = <0x40002000 0x400>; clocks = <&rcc TIM4_K>; clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; status = "disabled"; pwm { @@ -161,6 +179,13 @@ reg = <0x40003000 0x400>; clocks = <&rcc TIM5_K>; clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm { @@ -182,6 +207,8 @@ reg = <0x40004000 0x400>; clocks = <&rcc TIM6_K>; clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; status = "disabled"; timer@5 { @@ -198,6 +225,8 @@ reg = <0x40005000 0x400>; clocks = <&rcc TIM7_K>; clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; status = "disabled"; timer@6 { @@ -465,6 +494,15 @@ reg = <0x44000000 0x400>; clocks = <&rcc TIM1_K>; clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled"; pwm { @@ -486,6 +524,15 @@ reg = <0x44001000 0x400>; clocks = <&rcc TIM8_K>; clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled"; pwm { @@ -543,6 +590,11 @@ reg = <0x44006000 0x400>; clocks = <&rcc TIM15_K>; clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; status = "disabled"; pwm { @@ -564,6 +616,9 @@ reg = <0x44007000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled"; pwm { @@ -584,6 +639,9 @@ reg = <0x44008000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled"; pwm { -- cgit v1.2.3 From 1f3250f397f683e713439d4ff6a524386646a328 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 3 Oct 2018 17:11:04 +0200 Subject: ARM: dts: stm32: don't use timers dmas on stm32mp157c-ed1 Spare dmas when using timer6 on stm32mp157c-ed1. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index f77bea49c079..c3ecb1e10d94 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -72,6 +72,9 @@ &timers6 { status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; timer@5 { status = "okay"; }; -- cgit v1.2.3 From 5ae71cea1aec476a115dcf931807548cd26160ec Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 3 Oct 2018 17:11:05 +0200 Subject: ARM: dts: stm32: don't use timers dmas on stm32mp157c-ev1 Spare dmas when using timers on stm32mp157c-ev1. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 063ee8ac5dcb..e911527c80d0 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -161,6 +161,9 @@ }; &timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm2_pins_a>; @@ -173,6 +176,8 @@ }; &timers8 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm8_pins_a>; @@ -185,6 +190,8 @@ }; &timers12 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm12_pins_a>; -- cgit v1.2.3 From d44d6e021301b6a8d95bf6a92e8aae640de2770a Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Thu, 15 Nov 2018 08:52:29 +0000 Subject: ARM: dts: stm32: change CAN RAM mapping on stm32mp157c Split the 10Kbytes CAN message RAM to be able to use simultaneously FDCAN1 and FDCAN2 instances. First 5Kbytes are allocated to FDCAN1 and last 5Kbytes are used for FDCAN2. To do so, set the offset to 0x1400 in mram-cfg for FDCAN2. Signed-off-by: Bich Hemon Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 2e9df63f9997..b0961cccfd14 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -742,14 +742,14 @@ m_can1: can@4400e000 { compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; reg-names = "m_can", "message_ram"; interrupts = , ; interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; -- cgit v1.2.3 From bb4857cd0060b16cb3e84ad258c334717db94acd Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Thu, 15 Nov 2018 08:52:29 +0000 Subject: ARM: dts: stm32: add can1 sleep pins muxing Add can1 pinctrl definition for low-power mode Signed-off-by: Bich Hemon Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index c4851271e810..9ec4694e93a7 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -246,6 +246,13 @@ }; }; + m_can1_sleep_pins_a: m_can1-sleep@0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ -- cgit v1.2.3 From e3b3d0b19bd7b1eb7e5ab1c5d2b12c96fe0f5500 Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Thu, 15 Nov 2018 08:52:29 +0000 Subject: ARM: dts: stm32: add can1 sleep pins muxing on stm32mp157c-ev1 board Add pinctrl sleep state for can1 on stm32mp157c-ev1. Signed-off-by: Bich Hemon Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index e911527c80d0..b6aca40b9b90 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -124,8 +124,9 @@ }; &m_can1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; }; -- cgit v1.2.3 From 8914b63bab3c43a529316ba2858137bc57b74fa1 Mon Sep 17 00:00:00 2001 From: David Hernandez Sanchez Date: Mon, 3 Dec 2018 10:42:24 +0100 Subject: ARM: dts: stm32: add thermal sensor support on STM32MP157c Add configuration on DT for thermal sensor driver. Signed-off-by: David Hernandez Sanchez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index b0961cccfd14..f8bbfff5950b 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -84,6 +84,31 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -966,6 +991,16 @@ status = "disabled"; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = ; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + cryp1: cryp@54001000 { compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; -- cgit v1.2.3 From e3b382c1075e967cf1a95db881f575eef3a8f007 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 21 Nov 2018 22:05:15 +0100 Subject: ARM: dts: am335x-chiliboard: Add stdout-path property Add stdout-path property in /chosen node so that earlycon can be used by just adding earlycon in bootargs. Signed-off-by: Marcin Niestroj Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-chiliboard.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index 9c2a947aacf5..b50d5d2e71ff 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -14,6 +14,10 @@ compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", "ti,am33xx"; + chosen { + stdout-path = &uart0; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; -- cgit v1.2.3 From c6e967ad5a04d307836c927ae6300f62e7603dd7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Dec 2018 15:02:45 -0800 Subject: ARM: dts: Add wlcore wakeirq for omap3-evm With wlcore supporting optional wakeirqs, let's configure it for omap3-evm and update the related pin muxing as some pins are left unmuxed. Let's configure a wakeirq both for the wlcore GPIO and the SDIO dat1 pin in case wlcore starts supporting SDIO dat1 interrupt at some point. Note that for off-mode, the wlcore reset GPIO will have a glitch meaning wlcore will reset. The only way to workaround for this currently is to configure the reset pin with SAFE_MODE + PULL. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-common.dtsi | 7 +++++-- arch/arm/boot/dts/omap3-evm-processor-common.dtsi | 10 +++++++++- 2 files changed, 14 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 4c1227d1e79b..17c89df6ce6b 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -122,6 +122,7 @@ }; &mmc2 { + interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; vmmc-supply = <&wl12xx_vmmc>; non-removable; bus-width = <4>; @@ -132,8 +133,10 @@ wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */ + /* gpio_149 with uart1_rts pad as wakeirq */ + interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, + <&omap3_pmx_core 0x14e>; + interrupt-names = "irq", "wakeup"; ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi index ce7f42f9448c..b4109f48ec18 100644 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -86,6 +86,10 @@ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ >; }; @@ -127,9 +131,13 @@ >; }; + /* + * Note that gpio_150 pulled high with internal pull to prevent wlcore + * reset on return from off mode in idle. + */ wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ >; }; -- cgit v1.2.3 From 2f60f258e0f533013042f624fb8af4fca165b646 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Dec 2018 15:03:04 -0800 Subject: ARM: dts: Configure wlcore wakeirq for pandaboard With wlcore supporting optional wakeirqs, we can configure it for pandaboard. This makes ssh connection usable with the SoC entering deeper idle states. Note that pandaboard already has a wakeirq configured for SDIO dat1 pin although that is not currently used by wlcore. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 27895c1604b9..926f018823a4 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -485,8 +485,10 @@ wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ + /* gpio_53 with gpmc_ncs3 pad as wakeup */ + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>, + <&omap4_pmx_core 0x3a>; + interrupt-names = "irq", "wakeup"; ref-clock-frequency = <38400000>; }; }; -- cgit v1.2.3 From 7c695e87bd7a88298d2c00b5e14cf71d0a2a8663 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Dec 2018 15:03:21 -0800 Subject: ARM: dts: omap4-droid4: Configure wlcore wakeirq With wlcore supporting optional wakeirqs, we can configure it for droid 4. This makes ssh connection usable with the SoC entering deeper idle states. Let's configure a wakeirq both for the wlcore GPIO and the SDIO dat1 pin in case wlcore starts supporting SDIO dat1 interrupt at some point. And let's also add the missing keep-power-in-suspend while at it. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 04758a2a87f0..838aa3445fbe 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -359,20 +359,24 @@ &mmc3 { vmmc-supply = <&wl12xx_vmmc>; + /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core 0xde>; - + interrupt-names = "irq", "wakeup"; non-removable; bus-width = <4>; cap-power-off-card; + keep-power-in-suspend; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */ + /* gpio_100 with gpmc_wait2 pad as wakeirq */ + interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>, + <&omap4_pmx_core 0x4e>; + interrupt-names = "irq", "wakeup"; ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; -- cgit v1.2.3 From 78720aceacf0932d8475ba249535ce8e4fbbdfda Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 24 Dec 2018 09:17:45 +0100 Subject: ARM: dts: rockchip: move rk3036 i2s sound-dail-cells into soc dtsi The Rockchip i2s controller always only has one output connection hence #sound-dai-cells is always 0. Therefore define it in the soc dtsi itself instead of in individual boards. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 1 - arch/arm/boot/dts/rk3036.dtsi | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 0fd19f9723df..0173eb11ec28 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -310,7 +310,6 @@ }; &i2s { - #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index d560fc4051c5..59c90863b0e7 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -289,6 +289,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&i2s_bus>; + #sound-dai-cells = <0>; status = "disabled"; }; -- cgit v1.2.3 From 5286abda83afeed717971724365245fb1f42f50d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 29 Dec 2018 14:33:12 +0100 Subject: ARM: dts: rockchip: add HCLK_HDMI to rk3066 vio power-domain A MK808 TV stick with rk3066 processor boots normal with logo and console, but after booting the monitor remains black. This patch fixes a vblank wait time out by adding HCLK_HDMI to the vio power-domain node. The HCLK_HDMI clock is now part of the logic that enables the RK3066_PD_VIO power domain. Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 30dc8af0bdcb..b6b3a77da50a 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -669,6 +669,7 @@ <&cru SCLK_CIF0>, <&cru ACLK_CIF0>, <&cru HCLK_CIF0>, + <&cru HCLK_HDMI>, <&cru ACLK_IPP>, <&cru HCLK_IPP>, <&cru ACLK_RGA>, -- cgit v1.2.3 From 95e50af34d47f7496fee72d35aaefe25e23878db Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 2 Jan 2019 20:41:02 +0100 Subject: ARM: dts: rockchip: fix cif1_pdn pin on rk3188-bqedison2qc The powerdown pin for the second camera is gpio3_b5 not b4, so fix that. We don't have a working camera setup yet, so this is not really critical, but nevertheless better to have fixed already. Fixes: 36ead9149916 ("ARM: dts: rockchip: add BQ Edison 2 QC devicetree") Reported-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index a7477a09fbe8..2b5abfb48dd0 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -526,7 +526,7 @@ }; cif1_pdn: cif1-pdn { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; cif_avdd_en: cif-avdd-en { -- cgit v1.2.3 From 321514a385fa531b08f8c555e8e63fe66bfeb146 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 21 Dec 2018 17:10:12 +0100 Subject: ARM: dts: rockchip: add focaltech touchscreen to rk3188-bqedison2qc The Edison tablet uses a Focaltech touchscreen, with one speciality that the touchscreen resolution doesn't match the display resolution (1024x768 vs. 1280x600) which userspace will have to compensate for. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 2b5abfb48dd0..887d1aa8d0e1 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -408,6 +408,21 @@ &i2c2 { clock-frequency = <400000>; status = "okay"; + + ft5606: touchscreen@3e { + compatible = "edt,edt-ft5506"; + reg = <0x3e>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int &tp_rst>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + touchscreen-inverted-y; + /* hw ts resolution does not match display */ + touchscreen-size-y = <1024>; + touchscreen-size-x = <768>; + touchscreen-swapped-x-y; + }; }; &i2c3 { -- cgit v1.2.3 From 7e345d25c796abc8561786baaf59f30bc082ef1f Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Sun, 16 Dec 2018 09:25:24 +0000 Subject: ARM: dts: sun4i-a10: Add PMU node This is necessary to use 'perf' for cache profiling etc. Tested on cubieboard with 'perf stat echo foo'. Signed-off-by: Harald Geyer Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 5d46bb0139fa..a2fb473cbb9d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -184,6 +184,11 @@ status = "disabled"; }; + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From 09c6572290f018d73ec2e812e28bada34d41815f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 6 Dec 2018 15:02:04 +0100 Subject: ARM: dts: sun7i: bananapi: Add GPIO banks regulators The bananapi has all its bank regulators tied to the 3v3 static regulator. Make sure it's properly represented. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 556b1b591c5d..81bc85d398c1 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -191,6 +191,11 @@ }; &pio { + vcc-pa-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; gpio-line-names = /* PA */ "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", -- cgit v1.2.3 From 7aa69a47ecedb5368d862d0d8a2d6537b48e5501 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Dec 2018 16:12:41 +0100 Subject: ARM: dts: stout: Convert to new LVDS DT bindings As of commit 6d2ca85279becdff ("dt-bindings: display: renesas: Deprecate LVDS support in the DU bindings"), the internal LVDS encoder has DT bindings separate from the DU. The Lager device tree was ported over to the new model, but the Stout device tree was forgotten. Fixes: 15a1ff30d8f9bd83 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings") Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Tested-by: Marek Vasut Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-stout.dts | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts index 629da4cee1b9..7a7d3b84d1a6 100644 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ b/arch/arm/boot/dts/r8a7790-stout.dts @@ -94,9 +94,8 @@ status = "okay"; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&osc1_clk>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0"; + clock-names = "du.0", "du.1", "du.2", "dclkin.0"; ports { port@0 { @@ -104,11 +103,21 @@ remote-endpoint = <&adv7511_in>; }; }; + }; +}; + +&lvds0 { + ports { port@1 { lvds_connector0: endpoint { }; }; - port@2 { + }; +}; + +&lvds1 { + ports { + port@1 { lvds_connector1: endpoint { }; }; -- cgit v1.2.3 From 55327bff832c9903a9133cdad56783b54bd8596a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 7 Dec 2018 11:27:46 +0000 Subject: ARM: dts: iwg23s-sbc: Enable RTC Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 40b7f98d6013..77d18242ef59 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -84,12 +84,30 @@ clock-frequency = <20000000>; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii_tx_rx"; function = "avb"; }; + i2c3_pins: i2c3 { + groups = "i2c3_c"; + function = "i2c3"; + }; + mmc_pins_uhs: mmc_uhs { groups = "mmc_data8", "mmc_ctrl"; function = "mmc"; -- cgit v1.2.3 From 35713c782ef7c715eb0bc2f43d9f31cc7ec08063 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 5 Dec 2018 09:06:55 +0000 Subject: ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes This patch fixes sorting of vsp and msiof nodes. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 150 ++++++++++++++++++++--------------------- 1 file changed, 75 insertions(+), 75 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 04148d608fc4..8d25a0a0594a 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -998,6 +998,54 @@ status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; @@ -1068,54 +1116,6 @@ status = "disabled"; }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - can0: can@e6e80000 { compatible = "renesas,can-r8a7744", "renesas,rcar-gen2-can"; @@ -1589,33 +1589,6 @@ resets = <&cpg 408>; }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - pciec: pcie@fe000000 { compatible = "renesas,pcie-r8a7744", "renesas,pcie-rcar-gen2"; @@ -1644,6 +1617,33 @@ status = "disabled"; }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + du: display@feb00000 { reg = <0 0xfeb00000 0 0x40000>, <0 0xfeb90000 0 0x1c>; -- cgit v1.2.3 From 072b817589b17660ef19c31d89f7b981dbed3fd2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Dec 2018 11:57:57 +0000 Subject: ARM: dts: r8a7743: Remove generic compatible string from iic3 The iic3 block on RZ/G1M does not support automatic transmission, unlike other R-Car SoC's. So dropping the compatibility with the generic version. Fixes: f523405f2a22cc0c307 ("ARM: dts: r8a7743: Add IIC cores to dtsi") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 3cc33f7ff7fe..169fddc33229 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -564,9 +564,7 @@ /* doesn't need pinmux */ #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7743"; reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&cpg CPG_MOD 926>; -- cgit v1.2.3 From aeefe7394ca9a77b264963beaba01b4e85a9142c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Dec 2018 12:07:03 +0000 Subject: ARM: dts: r8a7743: Remove aliases from SoC dtsi This patch removes aliases from SoC dtsi tree. Device aliases are board-specific, if needed define it in board dts rather than SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 169fddc33229..19e96e2e2e55 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -15,25 +15,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic0; - i2c7 = &iic1; - i2c8 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. -- cgit v1.2.3 From 383f6024981d32425fa453bf2e66b546fdbc1314 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Dec 2018 11:52:30 +0000 Subject: ARM: dts: r8a7743: Fix sorting of rwdt node Watchdog node is incorrectly placed on r8a7743 SoC dtsi. This patch fixes the sorting order. Fixes: b5beb5d4c81c358f50a8310108 ("ARM: dts: r8a7743: Add watchdog support to SoC dtsi") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 19e96e2e2e55..24e6c2b67473 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -135,6 +135,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7743-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", "renesas,rcar-gen2-gpio"; @@ -291,16 +301,6 @@ reg = <0 0xe6160000 0 0x100>; }; - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7743-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7743-sysc"; reg = <0 0xe6180000 0 0x200>; -- cgit v1.2.3 From 0bb677d9e552533e8365892c7bd9426b5a6d5d54 Mon Sep 17 00:00:00 2001 From: Paweł Chmiel Date: Wed, 19 Dec 2018 16:57:04 +0100 Subject: ARM: dts: s5pv210: Add node for exynos-rotator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for Exynos Rorator device, so it can be used on all S5Pv210 based devices. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 12eac8930eac..d715d184bc56 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -542,6 +542,15 @@ #dma-requests = <1>; }; + rotator: rotator@fa300000 { + compatible = "samsung,s5pv210-rotator"; + reg = <0xfa300000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <4>; + clocks = <&clocks CLK_ROTATOR>; + clock-names = "rotator"; + }; + i2c1: i2c@fab00000 { compatible = "samsung,s3c2440-i2c"; reg = <0xfab00000 0x1000>; -- cgit v1.2.3 From 9563793d15878f457aecf3dd30b19572809a1c34 Mon Sep 17 00:00:00 2001 From: Paweł Chmiel Date: Fri, 28 Dec 2018 17:18:14 +0100 Subject: ARM: dts: s5pv210: Use correct fimd variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we have separate compatible for S5Pv210 FIMD, let's use it rather than using one from Exynos4210. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index d715d184bc56..cc22c9db80d2 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -511,7 +511,7 @@ }; fimd: fimd@f8000000 { - compatible = "samsung,exynos4210-fimd"; + compatible = "samsung,s5pv210-fimd"; interrupt-parent = <&vic2>; reg = <0xf8000000 0x20000>; interrupt-names = "fifo", "vsync", "lcd_sys"; -- cgit v1.2.3 From f143f8d68077d8d363cabd7412ecc86cede25bdc Mon Sep 17 00:00:00 2001 From: Paweł Chmiel Date: Fri, 28 Dec 2018 17:18:15 +0100 Subject: ARM: dts: s5pv210: Remove hardcoded bootargs on Galaxy S and Fascinate 4G MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we have U-Boot (flashed in place of stock kernel), it's not needed anymore to hardcode bootargs on every Aries-family board. Signed-off-by: Paweł Chmiel [krzk: Squash changes to fascinate4g and galaxys into one commit] Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-fascinate4g.dts | 7 ------- arch/arm/boot/dts/s5pv210-galaxys.dts | 7 ------- 2 files changed, 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index ccf761b1babf..07a8d9bbe5b8 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -11,13 +11,6 @@ chosen { stdout-path = &uart2; - /* - * It's hard to change those parameters in stock bootloader, - * since it requires special hardware/cable. - * Let's hardocde bootargs for now, till u-boot port is finished, - * with which it should be easier. - */ - bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk"; }; gpio-keys { diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index 842276749717..cf161bbfbacf 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -11,13 +11,6 @@ chosen { stdout-path = &uart2; - /* - * It's hard to change those parameters in stock bootloader, - * since it requires special hardware/cable. - * Let's hardocde bootargs for now, till u-boot port is finished, - * with which it should be easier. - */ - bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk"; }; nand_pwrseq: nand-pwrseq { -- cgit v1.2.3 From 26b933b9436b9205787f9058683f3a1f09089876 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 12 Dec 2018 16:31:08 +0000 Subject: ARM: dts: at91: at91-sama5d27_som1: add QSPI1 + SPI NOR memory nodes Configure the QSPI1 controller pin muxing and declare the jedec,spi-nor memory (SST26VF064). Signed-off-by: Claudiu Beznea [tudor.ambarus@microchip.com: add spi-rx/tx-bus-width, drop partitions, reword commit.] Signed-off-by: Tudor Ambarus Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index cf0087b4c9e1..33a159c0163f 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -62,6 +62,20 @@ ahb { apb { + qspi1: spi@f0024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; + }; + macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; @@ -78,6 +92,22 @@ pinctrl@fc038000 { + pinctrl_qspi1_default: qspi1_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + pinctrl_macb0_default: macb0_default { pinmux = , , -- cgit v1.2.3 From c2dfab7e40095b29668a4022a5558549e544e3cd Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 12 Dec 2018 16:31:11 +0000 Subject: ARM: dts: at91: at91-sama5d27_som1_ek: enable qspi1 memory Enable qspi1. Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 4a258867ddf1..a48180555ef5 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -109,6 +109,10 @@ status = "okay"; }; + qspi1: spi@f0024000 { + status = "okay"; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; -- cgit v1.2.3 From 31f031f73a01fb83fd6f4abfff04a79b360219e1 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:11:49 +0000 Subject: ARM: dts: at91: replace gpio-key,wakeup with wakeup-source property Most of the legacy "gpio-key,wakeup" property are already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Almost all of those were remove couple of years back. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Alexandre Belloni Cc: Peter Rosin Cc: Nicolas Ferre Signed-off-by: Sudeep Holla Acked-by: Peter Rosin Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-nattis-2-natte-2.dts | 2 +- arch/arm/boot/dts/at91-wb45n.dts | 2 +- arch/arm/boot/dts/at91-wb50n.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts index 0f6d335125e2..f245944bd5d7 100644 --- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts +++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts @@ -22,7 +22,7 @@ wakeup { label = "Wakeup"; linux,code = <10>; - gpio-key,wakeup; + wakeup-source; gpios = <&pioB 27 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts index 5b9512a6c89c..54d130c92185 100644 --- a/arch/arm/boot/dts/at91-wb45n.dts +++ b/arch/arm/boot/dts/at91-wb45n.dts @@ -22,7 +22,7 @@ label = "IRQBTN"; linux,code = <99>; gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - gpio-key,wakeup = <1>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index 8cecc7051a86..a5e45bb95c04 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -23,7 +23,7 @@ label = "BTNESC"; linux,code = <1>; /* ESC button */ gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - gpio-key,wakeup = <1>; + wakeup-source; }; irqbtn@31 { @@ -31,7 +31,7 @@ label = "IRQBTN"; linux,code = <99>; /* SysReq button */ gpios = <&pioE 31 GPIO_ACTIVE_LOW>; - gpio-key,wakeup = <1>; + wakeup-source; }; }; -- cgit v1.2.3 From 26e9ffeb2c04f0f577d0179e7eca8e1d54f9e050 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:53 +0800 Subject: ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup UART3 on the PG pingroup on the R40 SoC is commonly used to connect the bluetooth controller in a WiFi+Bluetooth combo chip, with the WiFi bits also on the PG pingroup. This patch adds two device nodes for UART3 on PG pingroup, one for the RX/TX pins, and one for the RTS/CTS pins. Consumers can reference either just the RX/TX pinmux setting or both, depending on the application. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 89762dbefe42..f1fcfa0bdce0 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -389,6 +389,16 @@ pins = "PB22", "PB23"; function = "uart0"; }; + + uart3_pg_pins: uart3-pg-pins { + pins = "PG6", "PG7"; + function = "uart3"; + }; + + uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { + pins = "PG8", "PG9"; + function = "uart3"; + }; }; wdt: watchdog@1c20c90 { -- cgit v1.2.3 From a5a4bc14914faf219336d71c71595975b8112ff7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:54 +0800 Subject: ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_A CLK_OUT_A, an external clock output function driven from the clock control unit, on the R40 is sometimes used to provide a low rate low power clock to a WiFi or Bluetooth controller. This patch adds a pinmux setting for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index f1fcfa0bdce0..06b685869f52 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -342,6 +342,11 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + clk_out_a_pin: clk-out-a-pin { + pins = "PI12"; + function = "clk_out_a"; + }; + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", -- cgit v1.2.3 From e5c6e693be831c1bba9b4f8f1da597fb5514deca Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:55 +0800 Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix WiFi regulator definitions The design of the Bananapi M2 Ultra has both DLDO1 and DLDO2 regulators provide power to the WiFi+BT module, which is based on the Broadcom BCM43438 or BCM43430 chip. Each regulator output from the PMIC can supply up to 200 mA. The datasheet of the chip suggests a maximum power draw of up to 360 mA when transmitting, thus requiring two outputs from the PMIC to handle the load. However the device tree only references one of them, leaving the other unused and possibly turned off. This patch marks both as always-on, since we don't have a proper binding to specify two regulators as "bound together". The name and constraints of DLDO2 are also added. Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 438b7b44dab3..1a6794e63b90 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -250,12 +250,27 @@ regulator-name = "vcc-wifi-io"; }; +/* + * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same + * time, with the two being in sync, to be able to meet maximum power + * consumption during transmits. Since this is not really supported + * right now, just use the two as always on, and we will fix it later. + */ + ®_dldo2 { + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-wifi"; }; +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +}; + ®_dldo4 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; -- cgit v1.2.3 From 1e5f1db4ccd8348a21da55bff82f4263000879ef Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:56 +0800 Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side identifies as BCM43430, while the Bluetooth side identifies as BCM43438. The Bluetooth side is connected to UART3 in a 4 wire configuration. Same as the WiFi side, due to being the same chip and package, DLDO1 and DLDO2 regulator outputs from the PMIC provide overall power via VBAT and I/O power via VDDIO. The CLK_OUT_A clock output from the SoC provides the LPO low power clock at 32.768 kHz. This patch enables Bluetooth on this board, and also adds the missing LPO clock on the WiFi side. There is also a PCM connection for Bluetooth, but this is not covered here. The LPO clock is fed from CLK_OUT_A, which needs to be muxed on pin PI12. This can be represented in multiple ways. This patch puts the pinctrl property in the pin controller node. This is due to limitations in Linux, where pinmux settings, even the same one, can not be shared by multiple devices. Thus we cannot put it in both the WiFi and Bluetooth device nodes. Putting it the CCU node is another option, but Linux's CCU driver does not handle pinctrl. Also the pin controller is guaranteed to be initialized after the CCU, when clocks are available. And any other devices that use muxed pins are guaranteed to be initialized after the pin controller. Thus having the CLK_OUT_A pinmux reference be in the pin controller node is a good choice without having to deal with implementation issues. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 1a6794e63b90..c488aaacbd68 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -102,6 +102,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; }; }; @@ -196,6 +198,11 @@ status = "okay"; }; +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <2500000>; @@ -293,6 +300,25 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ccu CLK_OUTA>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + /* TODO host wake line connected to PMIC GPIO pins */ + shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + max-speed = <1500000>; + }; +}; + &usbphy { usb1_vbus-supply = <®_vcc5v0>; usb2_vbus-supply = <®_vcc5v0>; -- cgit v1.2.3 From c322e85ad1d4c4459e0c722d6467772a39a7743d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:57 +0800 Subject: ARM: dts: sunxi: bananapi-m2-plus: Add Bluetooth device node The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side identifies as BCM43430, while the Bluetooth side identifies as BCM43438. The Bluetooth side is connected to UART1 in a 4 wire configuration. Same as the WiFi side, due to being the same chip and package, the board's fixed 3.3V power regulator provides overall power via VBAT and I/O power via VDDIO. The RTC clock output from the SoC provides the LPO low power clock at 32.768 kHz. This patch enables Bluetooth on this board, and also adds the missing LPO clock on the WiFi side. There is also a PCM connection for Bluetooth, but this is not covered here. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index b3283aeb5b7d..3bed375b9c03 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -103,6 +103,8 @@ compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; @@ -215,7 +217,19 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - status = "okay"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + }; }; &usb_otg { -- cgit v1.2.3 From d031ee5374b6eb66af7ef131d6bd7b1a9924c7af Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 15 Dec 2018 08:31:52 +0530 Subject: ARM: dts: Add support for 96Boards Chameleon96 board Add devicetree support for 96Boards Chameleon96 board from Novtech, Inc. based on Altera CycloneV SoC FPGA. This board is one of the Consumer Edition boards of the 96Boards family and has the following key features: * SoC - Intel Cyclone V SoC FPGA * GPU - Graphics based on Intel Video Suite for FPGA * RAM - 512MB DDR3L * USB - 2x USB2.0 Host, 1x USB2.0 OTG * Wireless - Wifi, BT More information about this board can be found in 96Boards product page: https://www.96boards.org/product/chameleon96/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts | 130 +++++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..e21d4bb42494 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -919,6 +919,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_chameleon96.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts new file mode 100644 index 000000000000..f6561766d83f --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Chameleon96 + * + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Novetech Chameleon96"; + compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x20000000>; /* 512MB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "green:user1"; + gpios = <&porta 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "green:user2"; + gpios = <&porta 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "green:user3"; + gpios = <&porta 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + user_led4 { + label = "green:user4"; + gpios = <&portb 3 GPIO_ACTIVE_LOW>; + panic-indicator; + linux,default-trigger = "none"; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&spi0 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; + +&spi1 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&uart0 { + /* On Low speed expansion */ + label = "LS-UART1"; + status = "okay"; +}; + +&uart1 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- cgit v1.2.3 From 34948b77bb09b8ad3b3365c3b2b87278ce4473de Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:12 +0530 Subject: ARM: dts: mt7623: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 98f115966391..a79f0b6c3429 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -187,17 +187,26 @@ cooling-maps { map0 { trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map2 { trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit v1.2.3 From 13c033bc630a2df51931d16ea5fb81710ad2e0b2 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 7 Dec 2018 10:03:39 +0000 Subject: ARM: dts: imx7ulp: add HSRUN mode clocks i.MX7ULP can switch CPU between RUN mode and HSRUN mode by programming SMC1 register, different clock sources will be used for CPU in different modes, so SMC1 can be abstracted as a clock controller for CPU clock switch, this patch adds support for it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 931b2754b099..b86daf73bb89 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -199,9 +199,13 @@ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; - smc1: smc1@40410000 { + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; + clock-names = "divcore", "hsrun_divcore"; }; pcc3: clock-controller@40b30000 { -- cgit v1.2.3 From 02f95c355122d5a93d2663df867aa8e2bde5480a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Dec 2018 10:03:47 -0200 Subject: ARM: dts: vf610-zii-cfu1: Run I2C0 at 400 kHz All the I2C devices connected to the I2C0 bus are capable of running at 400kHz, so run it at a higher frequency. Signed-off-by: Fabio Estevam Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 7cdcc5fe8282..445c7dc306b2 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -207,7 +207,7 @@ }; &i2c0 { - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; -- cgit v1.2.3 From cd8281acdf91379dfa001e2e523ca192360c1d02 Mon Sep 17 00:00:00 2001 From: Patrick Havelange Date: Tue, 11 Dec 2018 16:48:34 +0100 Subject: ARM: dts: ls1021a: Add memory controller The LS1021A has a memory controller that supports EDAC. This commit adds an entry for it. Signed-off-by: Patrick Havelange Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index ed0941292172..6df6a291f4d0 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -125,6 +125,13 @@ interrupt-parent = <&gic>; ranges; + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + big-endian; + }; + gic: interrupt-controller@1400000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; -- cgit v1.2.3 From 65441e1ffc21b950d7bcb697e7cc2424fc14fa8d Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Tue, 11 Dec 2018 17:40:10 +0100 Subject: ARM: dts: imx6q-tbs2910: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Soeren Moch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-tbs2910.dts | 49 +++---------------------------------- 1 file changed, 3 insertions(+), 46 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 279b15e9ae2e..2ce8399a10ba 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -1,49 +1,6 @@ -/* - * Copyright 2014 Soeren Moch - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2014 Soeren Moch /dts-v1/; -- cgit v1.2.3 From 7dd2e8f8a5dc6266a4df4ed6f269ab7bacae596c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 19 Dec 2018 13:47:27 +0200 Subject: ARM: dts: da850-lcdk: Enable the analog mic input The LCDK board have additional analog mic jack. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lcdk.dts | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 0177e3ed20fe..320ae9d13f6f 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -44,12 +44,16 @@ simple-audio-card,name = "DA850/OMAP-L138 LCDK"; simple-audio-card,widgets = "Line", "Line In", - "Line", "Line Out"; + "Line", "Line Out", + "Microphone", "Mic Jack"; simple-audio-card,routing = "LINE1L", "Line In", "LINE1R", "Line In", "Line Out", "LLOUT", - "Line Out", "RLOUT"; + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&link0_codec>; simple-audio-card,frame-master = <&link0_codec>; @@ -220,6 +224,8 @@ #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x18>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ status = "okay"; }; }; -- cgit v1.2.3 From b724cad74c7a122a8496518a157c548f97f1821b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 29 Jan 2018 14:28:59 +0100 Subject: ARM: dts: Augment panel setting for Integrator/CP This adds the actual VGA DAC bridge that is used in the Versatile AB, and sets the mode to 640x480 VGA and routes the CLCD pads appropriately. Cc: Liviu Dudau Cc: Mali DP Maintainers Signed-off-by: Linus Walleij --- arch/arm/boot/dts/integratorcp.dts | 89 ++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 32 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index a185ab8759fa..01fa229e1bd0 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -192,6 +192,43 @@ interrupts = <27>; }; + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + fpga { /* * These PrimeCells are at the same location and using @@ -254,39 +291,27 @@ interrupts = <22>; clocks = <&auxosc>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; - port { - /* - * The VGA connected is implemented with a - * THS8134A triple DAC that can be run in 24bit - * or 16bit RGB mode. - */ - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <1 7 13>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; + /* + * This port is routed through a PLD (Programmable + * Logic Device) that routes the output from the CLCD + * (after transformations) to the VGA DAC and also an + * external panel connector. The PLD is essential for + * supporting RGB565/BGR565. + * + * The signals from the port thus reaches two endpoints. + * The PLD is managed through a few special bits in the + * FPGA "sysreg". + * + * This arrangement can be clearly seen in + * ARM DUI 0225D, page 3-41, figure 3-19. + */ + port@0 { + clcd_pads_vga_dac: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; }; -- cgit v1.2.3 From cf91ce9696a019de74135b7a2ee21466c680ff4e Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Sun, 9 Dec 2018 22:50:56 +0100 Subject: ARM: dts: vf610-bk4: Provide support for reading ID code from MVB device The procedure to read this ID value is as follows: rmmod spi_fsl_dspi insmod spi-gpio.ko echo 504 > /sys/class/gpio/export cat /sys/class/gpio/gpio504/value ... echo 511 > /sys/class/gpio/export cat /sys/class/gpio/gpio511/value rmmod spi-gpio.ko insmod spi_fsl_dspi Signed-off-by: Lukasz Majewski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-bk4.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts index 689c8930dce3..fe496f220871 100644 --- a/arch/arm/boot/dts/vf610-bk4.dts +++ b/arch/arm/boot/dts/vf610-bk4.dts @@ -60,6 +60,29 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + spi-gpio { + compatible = "spi-gpio"; + pinctrl-0 = <&pinctrl_gpio_spi>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + /* PTD12 ->RPIO[91] */ + sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + /* PTD10 ->RPIO[89] */ + miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + num-chipselects = <0>; + + gpio@0 { + compatible = "pisosr-gpio"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + /* PTB18 -> RGPIO[40] */ + load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + spi-max-frequency = <100000>; + }; + }; }; &adc0 { @@ -431,6 +454,14 @@ >; }; + pinctrl_gpio_spi: pinctrl-gpio-spi { + fsl,pins = < + VF610_PAD_PTB18__GPIO_40 0x1183 + VF610_PAD_PTD10__GPIO_89 0x1183 + VF610_PAD_PTD12__GPIO_91 0x1183 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < VF610_PAD_PTA22__I2C2_SCL 0x34df -- cgit v1.2.3 From 657846f75670cb895672e48c61040c7d24d7361e Mon Sep 17 00:00:00 2001 From: Paweł Chmiel Date: Tue, 8 Jan 2019 17:55:58 +0100 Subject: ARM: dts: s5pv210: Add reserved memory for MFC on Aries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit THis commit adds memory reservation required by MFC (Multi Format Codec) to run. On S5PV210 both regions needs to be on separate memory banks. Size of both regions is taken from vendor Linux kernel sources. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 575094ea7024..89525e56cc7c 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -23,6 +23,24 @@ 0x50000000 0x08000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mfc_left: region@43000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x43000000 0x2000000>; + }; + + mfc_right: region@51000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x51000000 0x2000000>; + }; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; @@ -329,6 +347,10 @@ status = "okay"; }; +&mfc { + memory-region = <&mfc_left>, <&mfc_right>; +}; + &pinctrl0 { wlan_bt_en: wlan-bt-en { samsung,pins = "gpb-5"; -- cgit v1.2.3 From c7985d8cb4c28390a95992f20c99e6d2ca0e9126 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Tue, 8 Jan 2019 17:55:59 +0100 Subject: ARM: dts: s5pv210: Add support for more devices present on Aries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit enables following devices present on Aries based phones: - pwm-vibrator attached to PWM 1 - poweroff support - Atmel maXTouch touchscreen, connected to I2C-2 - Broadcom BCM4329 Bluetooth over UART-0 Signed-off-by: Jonathan Bakker Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 68 ++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 89525e56cc7c..8ff70b856334 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -41,6 +41,13 @@ }; }; + vibrator_pwr: regulator-fixed-0 { + compatible = "regulator-fixed"; + regulator-name = "vibrator-en"; + enable-active-high; + gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; @@ -314,6 +321,22 @@ reg = <0x36>; }; }; + + vibrator: pwm-vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm 1 44642 0>; + pwm-names = "enable"; + vcc-supply = <&vibrator_pwr>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; + }; + + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_syscon>; + offset = <0x681c>; /* PS_HOLD_CONTROL */ + value = <0x5200>; + }; }; &fimd { @@ -347,6 +370,23 @@ status = "okay"; }; +&i2c2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + samsung,i2c-slave-addr = <0x10>; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpj0>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq>; + reset-gpios = <&gpj1 3 GPIO_ACTIVE_HIGH>; + }; +}; + &mfc { memory-region = <&mfc_left>, <&mfc_right>; }; @@ -372,6 +412,13 @@ samsung,pin-drv = ; }; + bt_host_wake: bt-host-wake { + samsung,pins = "gph2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + tf_detect: tf-detect { samsung,pins = "gph3-4"; samsung,pin-function = ; @@ -384,6 +431,17 @@ samsung,pin-function = ; samsung,pin-pud = ; }; + + ts_irq: ts-irq { + samsung,pins = "gpj0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + samsung,pwm-outputs = <1>; }; &sdhci1 { @@ -421,6 +479,16 @@ &uart0 { status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake>; + shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gph2 5 GPIO_ACTIVE_HIGH>; + }; }; &uart1 { -- cgit v1.2.3 From b99f1870b689183ce3674ebc1a32d57ba925d5fc Mon Sep 17 00:00:00 2001 From: Paweł Chmiel Date: Tue, 8 Jan 2019 21:05:06 +0100 Subject: ARM: dts: s5pv210: Add DMC nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds DMC (Dynamic Memory Controller) nodes, which are needed by S5Pv210 cpufreq driver to work. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index cc22c9db80d2..b2ecbe6f4453 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -25,6 +25,8 @@ aliases { csis0 = &csis0; + dmc0 = &dmc0; + dmc1 = &dmc1; fimc0 = &fimc0; fimc1 = &fimc1; fimc2 = &fimc2; @@ -521,6 +523,16 @@ status = "disabled"; }; + dmc0: dmc@f0000000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf0000000 0x1000>; + }; + + dmc1: dmc@f1400000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf1400000 0x1000>; + }; + g2d: g2d@fa000000 { compatible = "samsung,s5pv210-g2d"; reg = <0xfa000000 0x1000>; -- cgit v1.2.3 From be6a95a55a095686455307d9437a9a25cf0233ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Jan 2019 14:43:03 +0100 Subject: ARM: dts: s5pv210: Fix onenand's unit address format warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Devicetree specification, the unit-address must match the first address specified in the reg property of the node. Fix the DTC warning onenand node: arch/arm/boot/dts/s5pv210.dtsi:81.29-93.5: Warning (simple_bus_reg): /soc/onenand@b0000000: simple-bus unit address format error, expected "b0600000" Signed-off-by: Krzysztof Kozlowski Tested-by: Paweł Chmiel --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index b2ecbe6f4453..a44d5eb56bed 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -80,7 +80,7 @@ }; }; - onenand: onenand@b0000000 { + onenand: onenand@b0600000 { compatible = "samsung,s5pv210-onenand"; reg = <0xb0600000 0x2000>, <0xb0000000 0x20000>, -- cgit v1.2.3 From 4de3f59c51f990b99691923c9e5c11928aea196d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Jan 2019 14:52:48 +0100 Subject: ARM: dts: s3c2416: Fix xti node's missing reg property warning Fix the DTC warning for xti node: arch/arm/boot/dts/s3c2416-smdk2416.dts:23.12-28.5: Warning (simple_bus_reg): /clocks/xti: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s3c2416-smdk2416.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 5164386aff3a..cb371bf72f64 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -19,9 +19,12 @@ clocks { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - xti: xti { + xti: xti@0 { compatible = "fixed-clock"; + reg = <0>; clock-frequency = <12000000>; clock-output-names = "xti"; #clock-cells = <0>; -- cgit v1.2.3 From 04aacc64ca38ab63863c2798c2fc3fc52718aae6 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 9 Jan 2019 10:48:23 +0100 Subject: ARM: dts: exynos: Fix conflicting fixed-regulator GPIO flags and properties Bindings of the fixed-regulator, which precedes support for GPIO flags passed via phandle descriptor, introduced its own method annotating that the given GPIO line is active low or high - by using 'enable-active-high' property. The driver always ignored flags passed via GPIO descriptor. Fix the conflicting GPIO flags to match the status forced by the 'enable-active-high' property to avoid future confusion. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 348556fcdd9d..a2251581f6b6 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -53,7 +53,7 @@ regulator-name = "p3v3_en"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpa1 1 GPIO_ACTIVE_LOW>; + gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 2ca9319f48f2..b44f03ef3b27 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -100,7 +100,7 @@ regulator-name = "VDD_33ON_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_LOW>; + gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; -- cgit v1.2.3 From 0b94260ac1e11e37f546d06bfae5c5bf13e0ad33 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 9 Jan 2019 10:55:57 +0100 Subject: ARM: dts: exynos: Fix eMMC regulator properties on Odroid U3 boards LDO20 regulator provides power for the MMC card on Odroid U3 boards. That regulator has been marked as 'boot-on' since the beginning of Odroid X/U3 support, but such flag is not really needed for it. That regulator is correctly described as supply for eMMC card and controlled by its driver. Commit 05f224ca6693 ("regulator: core: Clean enabling always-on regulators + their supplies") changed the way the boot-on regulators are handled and since then regulators marked as 'boot-on' got increased reference count and are not turned off for the system suspend time. The new approach turned out to break suspend/resume support on Odroid U3 with eMMC card, because the card is not properly shutdown due to missing of power cycle. Fix this by removing excessive 'boot-on' flag and let MMC driver to control turning power on and off. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 3a9eb1e91c45..24bcad3dfba9 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -390,7 +390,6 @@ regulator-name = "LDO20_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; }; ldo21_reg: LDO21 { -- cgit v1.2.3 From 2fc6f3773733f2a6322ede65abbbe76c9f1908fa Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:23 +0100 Subject: ARM: dts: meson6: add the APB2 bus The Mali GPU and the DVB demulator are located in the APB2 bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index ca978ab952cd..65585255910a 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -70,6 +70,14 @@ }; }; + apb2: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x40000>; + }; + xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; -- cgit v1.2.3 From 7e22d72834870af1396f90d31cbff38f36bbfa3d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:24 +0100 Subject: ARM: dts: meson8: add the APB bus Various peripherals (Mali GPU, NAND controller, VPU, etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index e5cd325d7ea8..3fd8260eba92 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -201,6 +201,14 @@ no-map; }; }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; }; /* end of / */ &aobus { -- cgit v1.2.3 From e402d24d884130ed308ff1d04fdababffcf0fa86 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:25 +0100 Subject: ARM: dts: meson8b: add the APB bus Various peripherals (Mali GPU, NAND controller, VPU; etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 22d775460767..5d036842c355 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -178,6 +178,14 @@ no-map; }; }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; }; /* end of / */ &aobus { -- cgit v1.2.3 From 7d3f6b536e72c94bd19585a3283e8d141614fee0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:46 +0100 Subject: ARM: dts: meson8: add the Mali-450 MP6 GPU Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the latter inherits meson8.dtsi). These SoCs have a Mali-450 GPU with six pixel processors. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV7 | 1, /* 182.1 Mhz */ FCLK_DEV4 | 1, /* 318.7 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 3fd8260eba92..1ea5a36c5040 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -166,6 +166,32 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-182150000 { + opp-hz = /bits/ 64 <182150000>; + opp-microvolt = <1150000>; + }; + opp-318750000 { + opp-hz = /bits/ 64 <318750000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = , @@ -208,6 +234,38 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2", "pp4", "ppmmu4", + "pp5", "ppmmu5", "pp6", "ppmmu6"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + switch-delay = <0xffff>; + }; }; }; /* end of / */ -- cgit v1.2.3 From c3ea80b6138caea8a6010fe37c6c3e57cb805b7d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:47 +0100 Subject: ARM: dts: meson8b: add the Mali-450 MP2 GPU Add the Mali-450 GPU and it's OPP table for Meson8. The GPU uses two pixel processors in this configuration. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV5 | 1, /* 255 Mhz */ FCLK_DEV7 | 0, /* 364 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 5d036842c355..dd498e681939 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -158,6 +158,32 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-255000000 { + opp-hz = /bits/ 64 <255000000>; + opp-microvolt = <1150000>; + }; + opp-364300000 { + opp-hz = /bits/ 64 <364300000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + pmu { compatible = "arm,cortex-a5-pmu"; interrupts = , @@ -185,6 +211,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8b-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + switch-delay = <0xffff>; + }; }; }; /* end of / */ -- cgit v1.2.3 From 5ddb78d6b14954b677436f6acf802303d4414d57 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 18 Dec 2018 04:19:26 +0000 Subject: ARM: dts: ls1021a: add num-viewport property for PCIe DT nodes Add num-viewport property for PCIe DT nodes to specify how many viewports are implemented. Signed-off-by: Hou Zhiqiang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 6df6a291f4d0..424700061fa0 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -831,6 +831,7 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -855,6 +856,7 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- cgit v1.2.3 From 0ce7b4a7741218465e492d30e4cf90a835fb7dfa Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 19 Dec 2018 05:41:31 +0000 Subject: ARM: dts: imx6sl: correct PWM ipg clock source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From i.MX6SL Reference Manual, the PWMx's ipg clock for registers access is from perclk, correct them. Signed-off-by: Anson Huang Acked-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index e7524e73efb4..4b4813f176cd 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -338,7 +338,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM1>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM1>; clock-names = "ipg", "per"; }; @@ -348,7 +348,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM2>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM2>; clock-names = "ipg", "per"; }; @@ -358,7 +358,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM3>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM3>; clock-names = "ipg", "per"; }; @@ -368,7 +368,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM4>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM4>; clock-names = "ipg", "per"; }; -- cgit v1.2.3 From cffbb02dafa374fea7adf9f79b009fa1d14c2531 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Jun 2018 20:21:06 +0200 Subject: ARM: dts: nomadik: Augment NHK15 panel setting The NHK15 panel is specified inside the display controller, which works for the DPI-type DT parsing the old fbdev code used, but for the DRM driver it needs to be spawn as its own device, so we move it out of the display controller. We also drop the panel timings: this should be determined by the hardware or a device-specific compatible string, not by this type of encoding into the device tree. It turns out that this hardware is strapped to the right configuration at boot already and we the driver just reads out the hardware-specified resolution and timings. Drop the "panel,dpi" compatible string altogether. Fix a comment error in the DTS file while we're at it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 85 ++++++++++++++++++++------------- 1 file changed, 51 insertions(+), 34 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 12afdc7467e7..04066f9cb8a3 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree for the ST-Ericsson Nomadik S8815 board - * Produced by Calao Systems + * Device Tree for the ST Microelectronics Nomadik NHK8815 board */ /dts-v1/; @@ -182,43 +181,12 @@ pinctrl-names = "default"; pinctrl-0 = <&clcd_24bit_mux>; port { - nomadik_clcd_pads: endpoint { + nomadik_clcd: endpoint { remote-endpoint = <&nomadik_clcd_panel>; arm,pl11x,tft-r0g0b0-pads = <16 8 0>; }; }; - /* - * WVGA connector 21 - * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB - * with TPO touch screen. - */ - panel { - compatible = "tpo,tpg110", "panel-dpi"; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - backlight = <&bl>; - - port { - nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <33200000>; - hactive = <800>; - hback-porch = <216>; - hfront-porch = <40>; - hsync-len = <1>; - vactive = <480>; - vback-porch = <35>; - vfront-porch = <10>; - vsync-len = <1>; - }; - }; }; /* Activate RX/TX and CTS/RTS on UART 0 */ @@ -233,6 +201,55 @@ }; }; + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* + * As we're dealing with 3wire SPI, we only define SCK + * and MOSI (in the spec MOSI is called "SDA"). + */ + gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>; + /* + * It's not actually active high, but the frameworks assume + * the polarity of the passed-in GPIO is "normal" (active + * high) then actively drives the line low to select the + * chip. + */ + cs-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + /* + * WVGA connector 21 + * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB + * with TPO touch screen. + */ + panel: display@0 { + /* + * The TPO display driver is connected to a + * 5.7" OSD OSD057VA01CT TFT display. + */ + compatible = "tpo,tpg110"; + reg = <0>; + spi-3wire; + /* 320 ns min period ~= 3 MHz */ + spi-max-frequency = <3000000>; + /* Width and height from the OSD data sheet */ + width-mm = <116>; + height-mm = <87>; + grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; + backlight = <&bl>; + + port { + nomadik_clcd_panel: endpoint { + remote-endpoint = <&nomadik_clcd>; + }; + }; + }; + }; + bl: backlight { compatible = "pwm-backlight"; pwms = <&stmpe0_pwm 0 500000>; -- cgit v1.2.3 From c4f70b4f93b092703eae1dc67ef262fb0112fbf5 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Wed, 19 Dec 2018 17:41:09 +0800 Subject: ARM: dts: ls1021a: Add incr-burst-byte-adjustment property to USB3 node Add this property to improve USB read write performance. Signed-off-by: Ran Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 424700061fa0..c93971e721bc 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -818,6 +818,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; pcie@3400000 { -- cgit v1.2.3 From e0b22fa041a6d5aad20650fe284e4b96cd32d05c Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 19 Dec 2018 18:56:39 +0300 Subject: ARM: dts: imx: Change i.MX27 interrupt controller unit name The interrupt controller is located at the physical address 0x10040000. This patch changes the unit name of the controller to reflect the actual address. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 26ff5d419bfc..3652f5556b29 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -40,7 +40,7 @@ spi2 = &cspi3; }; - aitc: aitc-interrupt-controller@e0000000 { + aitc: aitc-interrupt-controller@10040000 { compatible = "fsl,imx27-aitc", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; -- cgit v1.2.3 From 1fded78a67cb4fb371be02195369f1552a51c6ea Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 23 Dec 2018 09:03:40 +0300 Subject: ARM: dts: i.MX51: digi-connectcore: Move RTC from SOM to JSK In fact, the RTC battery can only be connected outside the module, so this patch moves the PMIC RTC property and its power from SOM dts to JSK. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 12 ++++++++++++ arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 7 ------- 2 files changed, 12 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index 2967a748d859..a5010e9e343b 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -27,6 +27,18 @@ status = "okay"; }; +&pmic { + fsl,mc13xxx-uses-rtc; + + regulators { + vcoincell_reg: vcoincell { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 82d8df097ef1..e9421b851ad5 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -37,7 +37,6 @@ reg = <0>; interrupt-parent = <&gpio1>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-rtc; regulators { sw1_reg: sw1 { @@ -142,12 +141,6 @@ pwgt2spi_reg: pwgt2spi { regulator-always-on; }; - - vcoincell_reg: vcoincell { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; }; }; }; -- cgit v1.2.3 From 526f56a359c5f7681ba640e8c797d97c98b1b259 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 23 Dec 2018 09:03:41 +0300 Subject: ARM: dts: i.MX51: imx51-digi-connectcore: Enable ESDHC1 This patch adds definitions for ESDHC1 for Digi Connectore SOM & JSK. This interface can be used to boot a module. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 4 ++++ arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 15 +++++++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index a5010e9e343b..a2eea58510dc 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -21,6 +21,10 @@ }; }; +&esdhc1 { + status = "okay"; +}; + &owire { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_owire>; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index e9421b851ad5..a2a6408203e3 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -145,6 +145,13 @@ }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + max-frequency = <50000000>; + bus-width = <1>; +}; + &esdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc2>; @@ -234,6 +241,14 @@ >; }; + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 + >; + }; + pinctrl_esdhc2: esdhc2grp { fsl,pins = < MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 -- cgit v1.2.3 From 0d422e670b6f9c26a2ef54700a6baa03230a4283 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 23 Dec 2018 09:03:42 +0300 Subject: ARM: dts: i.MX51: digi-connectcore-som: Add support for I2C bus recovery Define the required properties to enable I2C bus recovery supported by the I2C subsystem. This patch adds GPIO based I2C fault injector for Digi Connectcore SOM. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index a2a6408203e3..d90ba5fe4f1b 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -174,9 +174,12 @@ }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; clock-frequency = <400000>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; status = "okay"; mma7455l@1d { @@ -290,6 +293,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed + MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed + >; + }; + pinctrl_nfc: nfcgrp { fsl,pins = < MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 -- cgit v1.2.3 From 58bcc8d95545b5300a693d039516e45003e7455d Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Sat, 29 Dec 2018 14:33:16 +0100 Subject: ARM: dts: rockchip: add rk3066 vop display nodes This patch adds the core display subsystem and vop nodes to rk3066. Signed-off-by: Mark Yao Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b6b3a77da50a..653127a377fa 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -44,6 +44,11 @@ }; }; + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; @@ -57,6 +62,48 @@ }; }; + vop0: vop@1010c000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010c000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, + <&cru DCLK_LCDC0>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, + <&cru SRST_LCDC0_AHB>, + <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010e000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2s0: i2s@10118000 { compatible = "rockchip,rk3066-i2s"; reg = <0x10118000 0x2000>; -- cgit v1.2.3 From a4b0e36d694d0e9bc4c064e3a597294a84f5dca8 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:20 -0200 Subject: ARM: dts: rockchip: Add missing dma-names SPI support for rv1108 Pass the 'dma-names' property to the SPI ports so that DMA can be supported. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index d31370ff28f4..cb26d9d98c34 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -207,6 +207,7 @@ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; clock-names = "spiclk", "apb_pclk"; dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; #dma-cells = <2>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From fa2b56e7af4682d58bf609f5d655a390195e7c96 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:21 -0200 Subject: ARM: dts: rockchip: rv1108: Add spim0 and spim1 pinctrl groups Add the pin settings for the SPI pins so they can be used across multiple boards. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index cb26d9d98c34..f47ac86d2852 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -834,6 +834,42 @@ }; }; + spim0 { + spim0_clk: spim0-clk { + rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_up>; + }; + + spim0_cs0: spim0-cs0 { + rockchip,pins = <1 RK_PD1 RK_FUNC_2 &pcfg_pull_up>; + }; + + spim0_tx: spim0-tx { + rockchip,pins = <1 RK_PD3 RK_FUNC_2 &pcfg_pull_up>; + }; + + spim0_rx: spim0-rx { + rockchip,pins = <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spim1 { + spim1_clk: spim1-clk { + rockchip,pins = <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; + }; + + spim1_cs0: spim1-cs0 { + rockchip,pins = <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; + }; + + spim1_rx: spim1-rx { + rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + }; + + spim1_tx: spim1-tx { + rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + tsadc { otp_out: otp-out { rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; -- cgit v1.2.3 From 4a26c1602927c79dba91de195c3908d786addf64 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:23 -0200 Subject: ARM: dts: rv1108: Add support for rv1108-elgin-r1 board rv1108-elgin-r1 board is based on Rockchip RV1108 SoC. Signed-off-by: Otavio Salvador Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 5 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rv1108-elgin-r1.dts | 206 +++++++++++++++++++++ 3 files changed, 212 insertions(+) create mode 100644 arch/arm/boot/dts/rv1108-elgin-r1.dts (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index b12958bda09c..d30fff4b4676 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -60,6 +60,11 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Elgin RV1108 R1 + items: + - const: elgin,rv1108-r1 + - const: rockchip,rv1108 + - description: Firefly Firefly-RK3288 items: - enum: diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d9a5649b322b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r9a06g032-rzn1d400-db.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts new file mode 100644 index 000000000000..658057d871af --- /dev/null +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (C) 2018 O.S. Systems Software LTDA. + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Elgin RV1108 R1 board"; + compatible = "elgin,rv1108-r1", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + no-sd; + no-sdio; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = ; + rockchip,system-power-controller; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_core: DCDC_REG1 { + regulator-name= "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <900000>; + }; + }; + + vdd_cam: DCDC_REG2 { + regulator-name= "vdd_cam"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2000000>; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name= "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name= "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <3300000>; + }; + }; + + vdd_10: LDO_REG1 { + regulator-name= "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vcc_18: LDO_REG2 { + regulator-name= "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vdd10_pmu: LDO_REG3 { + regulator-name= "vdd10_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <1000000>; + }; + }; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>; + status = "okay"; + + dh2228fv: dac@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-cpha; + spi-cpol; + }; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; -- cgit v1.2.3 From b7f264fa496eb2a6dd1d67dc91dbe8ffcb142487 Mon Sep 17 00:00:00 2001 From: Dan Haab Date: Sun, 2 Dec 2018 17:00:15 -0700 Subject: ARM: dts: BCM53573: Relicense Luxul files to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches licensing used by other BCM53573 files and BCM5301X. Signed-off-by: Dan Haab Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 3 +-- arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 74c83b0ca54e..3902f69f7f1a 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2017 Luxul Inc. - * - * Licensed under the ISC license. */ /dts-v1/; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 214df18f3a75..4a522deb2d52 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2017 Luxul Inc. - * - * Licensed under the ISC license. */ /dts-v1/; -- cgit v1.2.3 From 37f7453a4b7aa3e1d1608edeb500b105257ee945 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 14 Jan 2019 17:52:50 -0600 Subject: ARM: dts: socfpga: update missing reset property peripherals Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 12 ++++++++++++ arch/arm/boot/dts/socfpga_arria10.dtsi | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index dcb8fba3d709..f365003f0102 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -585,6 +585,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -605,6 +606,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -625,6 +627,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -735,6 +738,7 @@ #size-cells = <0>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -748,6 +752,7 @@ interrupts = <0x0 0x90 0x4>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -767,6 +772,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -801,6 +807,7 @@ interrupts = <0 154 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -812,6 +819,7 @@ interrupts = <0 155 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -878,6 +886,7 @@ dmas = <&pdma 28>, <&pdma 29>; dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; }; uart1: serial1@ffc03000 { @@ -890,6 +899,7 @@ dmas = <&pdma 30>, <&pdma 31>; dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; }; usbphy0: usbphy { @@ -929,6 +939,7 @@ reg = <0xffd02000 0x1000>; interrupts = <0 171 4>; clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -937,6 +948,7 @@ reg = <0xffd03000 0x1000>; interrupts = <0 172 4>; clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index e41fa23481c3..ae24599d5829 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -470,6 +470,7 @@ tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; + resets = <&rst EMAC2_RESET>; clock-names = "stmmaceth"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; @@ -480,6 +481,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02900 0x100>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -499,6 +501,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02a00 0x100>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -518,6 +521,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02b00 0x100>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -548,6 +552,7 @@ reg = <0xffc02200 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C0_RESET>; status = "disabled"; }; @@ -558,6 +563,7 @@ reg = <0xffc02300 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C1_RESET>; status = "disabled"; }; @@ -568,6 +574,7 @@ reg = <0xffc02400 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C2_RESET>; status = "disabled"; }; @@ -578,6 +585,7 @@ reg = <0xffc02500 0x100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C3_RESET>; status = "disabled"; }; @@ -588,6 +596,7 @@ reg = <0xffc02600 0x100>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C4_RESET>; status = "disabled"; }; @@ -600,6 +609,7 @@ num-cs = <4>; /*32bit_access;*/ clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -614,6 +624,7 @@ tx-dma-channel = <&pdma 16>; rx-dma-channel = <&pdma 17>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -642,6 +653,7 @@ fifo-depth = <0x400>; clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -655,6 +667,7 @@ interrupts = <0 99 4>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -739,6 +752,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -815,6 +829,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -825,6 +840,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART1_RESET>; status = "disabled"; }; @@ -865,6 +881,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -873,6 +890,7 @@ reg = <0xffd00300 0x100>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; -- cgit v1.2.3 From 869d1375a495e6217fdfda6a59b13812d2f3a569 Mon Sep 17 00:00:00 2001 From: Xiaoting Liu Date: Thu, 10 Jan 2019 10:29:13 +0800 Subject: ARM: dts: aspeed: stardragon4800: Add power supply Add Delta Electronics power supply DPS-650-AB. Signed-off-by: Xiaoting Liu Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index bdfd8c9f3a7c..521afbea2c5b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -173,6 +173,16 @@ }; }; }; + + dps650ab@58 { + compatible = "delta,dps650ab"; + reg = <0x58>; + }; + + dps650ab@59 { + compatible = "delta,dps650ab"; + reg = <0x59>; + }; }; &i2c9 { -- cgit v1.2.3 From 80baf890da963782f0d84f45a44700fb3530a03c Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 27 Aug 2018 16:16:01 -0700 Subject: ARM: dts: aspeed-palmetto: Add i2c OCC hwmon node Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index 9aa1d4467453..b854ac0bae9a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -169,6 +169,11 @@ &i2c3 { status = "okay"; + + occ-hwmon@50 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x50>; + }; }; &i2c4 { -- cgit v1.2.3 From 8b88029380af76f1bdb1d0534c789ad150c32efa Mon Sep 17 00:00:00 2001 From: Mark Walton Date: Fri, 14 Dec 2018 12:07:07 +0000 Subject: ARM: dts: aspeed: Add #interrupt-cells property to gpio controllers Allows the GPIO controller to be used as an interrupt parent. of_irq_find_parent() skips interrupt controller nodes that do not have the #interrupt-cells property. Signed-off-by: Mark Walton Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 69f6b9d2e7e7..9549f867aa1e 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -197,6 +197,7 @@ gpio-ranges = <&pinctrl 0 0 220>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; + #interrupt-cells = <2>; }; timer: timer@1e782000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d107459fc0f8..a1999f3fe330 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -250,6 +250,7 @@ gpio-ranges = <&pinctrl 0 0 220>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; + #interrupt-cells = <2>; }; timer: timer@1e782000 { -- cgit v1.2.3 From 9e9a6ad1d7f2f70be80388308d10a09aa985edc5 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 17 Dec 2018 12:04:03 -0800 Subject: ARM: dts: aspeed: Add KCS support for LPC BMC This adds the description of the four Keyboard Controller Style (KCS) IPMI communication channels present in the ASPEED BMC. They are disabled by default. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index a1999f3fe330..3e4ed081505c 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -331,8 +331,32 @@ ranges = <0x0 0x1e789000 0x1000>; lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; + compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon"; reg = <0x0 0x80>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x80>; + + kcs1: kcs1@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <1>; + status = "disabled"; + }; + kcs2: kcs2@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <2>; + status = "disabled"; + }; + kcs3: kcs3@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <3>; + status = "disabled"; + }; }; lpc_host: lpc-host@80 { @@ -344,6 +368,13 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; + kcs4: kcs4@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <4>; + status = "disabled"; + }; + lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2500-lpc-ctrl"; reg = <0x0 0x80>; -- cgit v1.2.3 From e7b66ba2db01997e8f75548389b93eec4db61059 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 17 Dec 2018 12:04:04 -0800 Subject: ARM: dts: aspeed: tiogapass: Enable KCS Tiogapass uses two KCS channels. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index f8e7b71af7e6..a4c7e205ca96 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -56,6 +56,18 @@ status = "okay"; }; +&kcs2 { + // BMC KCS channel 2 + status = "okay"; + kcs_addr = <0xca8>; +}; + +&kcs3 { + // BMC KCS channel 3 + status = "okay"; + kcs_addr = <0xca2>; +}; + &mac0 { status = "okay"; -- cgit v1.2.3 From 1a5ebcd4356d5354e001898595ce9c50f3e8d09f Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 17 Dec 2018 12:04:02 -0800 Subject: ARM: dts: aspeed: tiogapass: Add sensors Added ADC and other sensor devices present in the Facebook Tiogapass machine. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 23 ++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index a4c7e205ca96..73e58a821613 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -21,6 +21,17 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; }; &fmc { @@ -76,6 +87,10 @@ use-ncsi; }; +&adc { + status = "okay"; +}; + &i2c0 { status = "okay"; //Airmax Conn B, CPU0 PIROM, CPU1 PIROM @@ -134,6 +149,10 @@ &i2c8 { status = "okay"; + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; //Mezz Sensor SMBus }; @@ -152,7 +171,7 @@ }; fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; }; }; -- cgit v1.2.3 From adbb78e1104a006275e0e8e37526f617bb2a3d91 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 10 Jan 2019 16:32:32 +0100 Subject: ARM: dts: r8a7778: Add HSCIF0/1 support Add HSCIF0/1 clocks and device nodes, based on Rev. 1.00 of the R-Car M1A datasheet. Signed-off-by: Ulrich Hecht [geert: Squashed two patches] [geert: Correct HSCIF1 module clock index] [geert: Correct reg properties for non-LPAE] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 28 ++++++++++++++++++++++++++++ include/dt-bindings/clock/r8a7778-clock.h | 2 ++ 2 files changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 05db0ccad7a6..10d996d2941f 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -367,6 +367,30 @@ status = "disabled"; }; + hscif0: serial@ffe48000 { + compatible = "renesas,hscif-r8a7778", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe48000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, + <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif1: serial@ffe49000 { + compatible = "renesas,hscif-r8a7778", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe49000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, + <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + mmcif: mmc@ffe4e000 { compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; @@ -535,6 +559,8 @@ <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_S>, <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, @@ -551,6 +577,7 @@ R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 + R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 @@ -560,6 +587,7 @@ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", + "hscif0", "hscif1", "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", "ssi2", "ssi3", "sru", "hspi"; }; diff --git a/include/dt-bindings/clock/r8a7778-clock.h b/include/dt-bindings/clock/r8a7778-clock.h index f6b07c5399de..d0bff9ec5c66 100644 --- a/include/dt-bindings/clock/r8a7778-clock.h +++ b/include/dt-bindings/clock/r8a7778-clock.h @@ -30,6 +30,8 @@ #define R8A7778_CLK_SCIF3 23 #define R8A7778_CLK_SCIF4 22 #define R8A7778_CLK_SCIF5 21 +#define R8A7778_CLK_HSCIF0 19 +#define R8A7778_CLK_HSCIF1 18 #define R8A7778_CLK_TMU0 16 #define R8A7778_CLK_TMU1 15 #define R8A7778_CLK_TMU2 14 -- cgit v1.2.3 From 055d15a88f66b096ca4df7cde83a80b80cd22dff Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 18 Jan 2019 11:48:15 +0100 Subject: ARM: dts: r8a7779: Add HSCIF0/1 device nodes Based on Rev. 1.00 of the R-Car H1 datasheet. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 3bc133d9489c..3ff259207527 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -287,6 +287,32 @@ status = "disabled"; }; + hscif0: serial@ffe48000 { + compatible = "renesas,hscif-r8a7779", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe48000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, + <&cpg_clocks R8A7779_CLK_S>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif1: serial@ffe49000 { + compatible = "renesas,hscif-r8a7779", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe49000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, + <&cpg_clocks R8A7779_CLK_S>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + pfc: pin-controller@fffc0000 { compatible = "renesas,pfc-r8a7779"; reg = <0xfffc0000 0x23c>; -- cgit v1.2.3 From 890c506735864dfcd172ea4d57d4378bbe66a06c Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 18 Jan 2019 15:57:29 +0100 Subject: ARM: dts: sun4i: Add support for the C1 SRAM region with the SRAM controller This adds support for the C1 SRAM region (to be used with the SRAM controller driver) for the A10 platform. The region is shared between the Video Engine and the CPU. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a2fb473cbb9d..c3a74024ca0f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -229,6 +229,19 @@ status = "disabled"; }; }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; }; dma: dma-controller@1c02000 { -- cgit v1.2.3 From 5949bc5602ccd88161982e646432944eb318fa6e Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 18 Jan 2019 15:57:30 +0100 Subject: ARM: dts: sun4i-a10: Add Video Engine and reserved memory nodes This adds nodes for the Video Engine and the associated reserved memory for the A10. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index c3a74024ca0f..73c3ac42095f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -189,6 +189,21 @@ interrupts = <3>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + default-pool { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x4a000000 0x6000000>; + reusable; + linux,cma-default; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -412,6 +427,17 @@ }; }; + video-codec@1c0e000 { + compatible = "allwinner,sun4i-a10-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + interrupts = <53>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c0f000 0x1000>; -- cgit v1.2.3 From 43d78e726a2b5fef0c0e0f07e2bed0faa4918d1b Mon Sep 17 00:00:00 2001 From: John Wang Date: Thu, 17 Jan 2019 17:32:42 +0800 Subject: ARM: dts: aspeed: Add Inspur on5263m5 BMC The Inspur on5263m5 is an Intel Xeon OCP server that uses the ASPEED AST2500 BMC. Signed-off-by: John Wang Reviewed-by: Andrew Jeffery [joel: Rework commit message] Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts | 145 +++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts new file mode 100644 index 000000000000..2337ee23f5c4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Inspur Corporation +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "ON5263M5 BMC"; + compatible = "inspur,on5263m5-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "earlyprintk"; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c6 { + status = "okay"; + + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2c7 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; +}; + +&adc { + status = "okay"; +}; -- cgit v1.2.3 From fc71f69ceccf64cb198c0301d982e0a21c3181ae Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 21 Jan 2019 10:35:39 +0000 Subject: ARM: dts: mps2: use list instead of tuple for uart interrupts MPS2 UART requires dedicated interrupts for RX, TX and overflow, which obviously should be expressed as a list. Current form uses tuple and it has worked so far because NVIC has interrupt-cells equal to 1. Signed-off-by: Vladimir Murzin Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/mps2.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index 23467390558d..96fb5a5cf4d3 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -171,7 +171,7 @@ uart0: serial@4000 { compatible = "arm,mps2-uart"; reg = <0x4000 0x1000>; - interrupts = <0 1 12>; + interrupts = <0>, <1>, <12>; clocks = <&sysclk>; status = "disabled"; }; @@ -179,7 +179,7 @@ uart1: serial@5000 { compatible = "arm,mps2-uart"; reg = <0x5000 0x1000>; - interrupts = <2 3 12>; + interrupts = <2>, <3>, <12>; clocks = <&sysclk>; status = "disabled"; }; @@ -187,7 +187,7 @@ uart2: serial@6000 { compatible = "arm,mps2-uart"; reg = <0x6000 0x1000>; - interrupts = <4 5 12>; + interrupts = <4>, <5>, <12>; clocks = <&sysclk>; status = "disabled"; }; -- cgit v1.2.3 From 01980aa7b0d7fde864899787510ddc01c1657c9a Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 22 Jan 2019 12:00:59 +0000 Subject: ARM: dts: vexpress: use list instead of tuple for mmci interrupts Vexpress motherboard MMCI requires dedicated interrupts for CMD and PIO, which obviously should be expressed as a list. Current form uses tuple and it works fine since interrupt-cells equal to 1. Reported-by: Vladimir Murzin Reviewed-by: Vladimir Murzin Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 +- arch/arm/boot/dts/vexpress-v2m.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index a9569d15de41..d3963e9eaf48 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -133,7 +133,7 @@ mmci@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; - interrupts = <9 10>; + interrupts = <9>, <10>; cd-gpios = <&v2m_mmc_gpios 0 0>; wp-gpios = <&v2m_mmc_gpios 1 0>; max-frequency = <12000000>; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index fd42e1194179..798c97aff7fa 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -133,7 +133,7 @@ mmci@5000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x05000 0x1000>; - interrupts = <9 10>; + interrupts = <9>, <10>; cd-gpios = <&v2m_mmc_gpios 0 0>; wp-gpios = <&v2m_mmc_gpios 1 0>; max-frequency = <12000000>; -- cgit v1.2.3 From 76c27054ebb90302eb819e7ae76f3a04ed70ae78 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Nov 2018 11:58:00 +0100 Subject: ARM: dts: msm8660: Mark two GSBI blocks "disabled" The GSBI module complains: gsbi 16500000.gsbi: missing mode configuration gsbi: probe of 16500000.gsbi failed with error -22 gsbi 16600000.gsbi: missing mode configuration gsbi: probe of 16600000.gsbi failed with error -22 gsbi 19800000.gsbi: GSBI port protocol: 2 crci: 0 So we should mark these GSBIs as "disabled" in the SoC file by default. If boards appear that make use of them, we can simply set status = "ok" in the DTS for them. Signed-off-by: Linus Walleij Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 70698941f64c..9b1cf00d8ca3 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -133,6 +133,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + status = "disabled"; syscon-tcsr = <&tcsr>; @@ -167,6 +168,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + status = "disabled"; syscon-tcsr = <&tcsr>; -- cgit v1.2.3 From 57c23241be8490c9db5c1d8c4496e7f13f2236ae Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Nov 2018 12:08:21 +0100 Subject: ARM: dts: msm8660: Fix up GIC IRQ flags All the GSBI blocks are marking their GIC IRQ lines as "IRQ_TYPE_NONE" but there is no such thing: all GIC IRQ lines have a trigger type. That yields the following warning from the GIC driver: WARNING: CPU: 0 PID: 1 at ../drivers/irqchip/irq-gic.c:1016 gic_irq_domain_translate+0xdc/0xe4 (...) Mark all of these IRQ_TYPE_LEVEL_HIGH as is common so this warning goes away. Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 9b1cf00d8ca3..e5da87036dbb 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -141,7 +141,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x1000>, <0x16500000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -150,7 +150,7 @@ gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16580000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -176,7 +176,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -185,7 +185,7 @@ gsbi7_i2c: i2c@16680000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16680000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -209,7 +209,7 @@ gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19880000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -234,7 +234,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_NONE>; + interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -243,7 +243,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_NONE>; + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; -- cgit v1.2.3 From ec4c6c57af576e10c70547b782db04eb3602f5f4 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Sun, 4 Nov 2018 16:50:34 -0500 Subject: ARM: dts: qcom: msm8974-hammerhead: add WiFi support This patch adds WiFi support to the LG Nexus 5 (hammerhead) phone. Signed-off-by: Jonathan Marek [masneyb@onstation.org: Enabled wlan_regulator_pin and wlan_sleep_clk_pin] Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 51444c53fc72..5cf9c7e20f2e 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -220,6 +220,20 @@ }; }; }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; }; &soc { @@ -242,6 +256,20 @@ }; }; + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + i2c3_pins: i2c3 { mux { pins = "gpio10", "gpio11"; @@ -283,6 +311,32 @@ pinctrl-0 = <&sdhc1_pin_a>; }; + sdhci@f98a4900 { + status = "ok"; + + max-frequency = <100000000>; + bus-width = <4>; + non-removable; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "gpio-keys"; @@ -371,6 +425,22 @@ bias-pull-up; power-source = ; }; + + wlan_sleep_clk_pin: wl-sleep-clk { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active { + pins = "gpio17"; + function = "normal"; + + bias-disable; + power-source = ; + }; }; }; }; -- cgit v1.2.3 From cdd3d64d843a2a4c658a182b744bfefbd021d542 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 31 Oct 2018 20:11:48 -0400 Subject: ARM: dts: qcom: msm8974: add gpio-ranges This adds the gpio-ranges property to pm8941_gpios so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency so GPIO hogging can be used on this board. Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-pm8941.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index 2515c5c217ac..9a91b758f7aa 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -63,6 +63,7 @@ compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8941_gpios 0 0 36>; #gpio-cells = <2>; interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, <0 0xc1 0 IRQ_TYPE_NONE>, -- cgit v1.2.3 From fb143fcbb9ad361004f2818e9dcb52b2556bfec1 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 31 Oct 2018 20:11:49 -0400 Subject: ARM: dts: qcom: msm8974-hammerhead: add USB OTG support Add the device tree bindings for USB OTG support. Driver was tested using on a LG Nexus 5 (hammerhead) phone. This patch is based on work from Jonathan Marek and from the other msm8974 devices. Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 60 ++++++++++++++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 11 ++++ 2 files changed, 71 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 5cf9c7e20f2e..b3b04736a159 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -270,6 +270,16 @@ }; }; + i2c1_pins: i2c1 { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c3_pins: i2c3 { mux { pins = "gpio10", "gpio11"; @@ -396,6 +406,24 @@ }; }; + i2c@f9923000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + qcom,src-freq = <50000000>; + + charger: bq24192@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; + + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; + }; + }; + i2c@f9925000 { status = "ok"; pinctrl-names = "default"; @@ -413,6 +441,31 @@ amstaos,proximity-diodes = <0>; }; }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + extcon = <&charger>, <&usb_id>; + vbus-supply = <&usb_otg_vbus>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; }; &spmi_bus { @@ -441,6 +494,13 @@ bias-disable; power-source = ; }; + + otg { + gpio-hog; + gpios = <35 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "otg-gpio"; + }; }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ca266a5f021d..05b86f21d41b 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -706,6 +706,17 @@ interrupts = ; }; + i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@f9924000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; -- cgit v1.2.3 From 40122db87778970c96062c9f49b42cdf6809bf94 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 18 Dec 2018 21:42:04 +0100 Subject: ARM: dts: ipq4019: Remove skeleton.dtsi The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 2d56008d8d6b..19635f91e2c4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -13,12 +13,14 @@ /dts-v1/; -#include "skeleton.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; -- cgit v1.2.3 From bbbcd02b825529076951a37ee632cdb33df414c7 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Tue, 18 Dec 2018 12:05:54 -0500 Subject: ARM: dts: r7s9210: Initial SoC device tree Basic support for the RZ/A2 (R7S9210) SoC. Signed-off-by: Chris Brandt Reviewed-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s9210.dtsi | 218 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 218 insertions(+) create mode 100644 arch/arm/boot/dts/r7s9210.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi new file mode 100644 index 000000000000..22baa96f5974 --- /dev/null +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R7S9210 SoC + * + * Copyright (C) 2018 Renesas Electronics Corporation + * + */ + +#include +#include + +/ { + compatible = "renesas,r7s9210"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* Value must be set by board */ + clock-frequency = <0>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value (32678) must be set by board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <528000000>; + next-level-cache = <&L2>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + L2: cache-controller@1f003000 { + compatible = "arm,pl310-cache"; + reg = <0x1f003000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 47>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007800 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 46>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 45>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008800 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 44>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8009000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 43>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm0: timer@e803b000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803b000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 36>; + clock-names = "ostm0"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@e803c000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803c000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 35>; + clock-names = "ostm1"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@e803d000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803d000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 34>; + clock-names = "ostm2"; + power-domains = <&cpg>; + status = "disabled"; + }; + + gic: interrupt-controller@e8221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8221000 0x1000>, + <0xe8222000 0x1000>; + }; + + cpg: clock-controller@fcfe0010 { + compatible = "renesas,r7s9210-cpg-mssr"; + reg = <0xfcfe0010 0x455>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + wdt: watchdog@fcfe7000 { + compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; + reg = <0xfcfe7000 0x26>; + interrupts = ; + clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; + }; + + bsid: chipid@fcfe8004 { + compatible = "renesas,bsid"; + reg = <0xfcfe8004 4>; + }; + + pinctrl: pin-controller@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + }; +}; -- cgit v1.2.3 From 3a62c2d2581497de89abbb2d7e0d2ade9b39433e Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Tue, 18 Dec 2018 12:05:55 -0500 Subject: ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB Add support for Renesas RZ/A2M evaluation board. Signed-off-by: Chris Brandt Reviewed-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r7s9210-rza2mevb.dts | 82 ++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm/boot/dts/r7s9210-rza2mevb.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..3a3a931b431e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -843,6 +843,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb \ r7s72100-rskrza1.dtb \ + r7s9210-rza2mevb.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-iwg20d-q7.dtb \ diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts new file mode 100644 index 000000000000..991e09de1219 --- /dev/null +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZA2MEVB board + * + * Copyright (C) 2018 Renesas Electronics + * + */ + +/dts-v1/; +#include "r7s9210.dtsi" +#include +#include + +/ { + model = "RZA2MEVB"; + compatible = "renesas,rza2mevb", "renesas,r7s9210"; + + aliases { + serial0 = &scif4; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x00800000>; /* HyperRAM */ + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + leds { + compatible = "gpio-leds"; + + red { + gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; + }; + green { + gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* EXTAL */ +&extal_clk { + clock-frequency = <24000000>; /* 24MHz */ +}; + +/* RTC_X1 */ +&rtc_x1_clk { + clock-frequency = <32768>; +}; + +&pinctrl { + /* Serial Console */ + scif4_pins: serial4 { + pinmux = , /* TxD4 */ + ; /* RxD4 */ + }; +}; + +/* High resolution System tick timers */ +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +/* Serial Console */ +&scif4 { + pinctrl-names = "default"; + pinctrl-0 = <&scif4_pins>; + + status = "okay"; +}; -- cgit v1.2.3 From 4abf8049fbd5a783b699e99c92f336aa6e42e17b Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 22 Jan 2019 07:46:46 +0000 Subject: ARM: dts: sun8i-h3: nanopi-m1-plus: enable HDMI This patch enable HDMI output on sun8i-h3-nanopi-m1-plus. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 65cba1050802..4ec94d72f021 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -67,6 +67,21 @@ pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; }; &ehci1 { @@ -94,6 +109,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; -- cgit v1.2.3 From 4d1796ef5e01b665747db1a876abe160d1cdad9c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 30 Nov 2018 15:58:46 +0800 Subject: ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controller The CSI controller found on the H3 (and H5) is a reduced version of the one found on the A31. It only has 1 channel, instead of 4 channels for time-multiplexed BT.656. Since the H3 is a reduced version, it cannot "fallback" to a compatible that implements more features than it supports. Drop the A31 fallback compatible. Fixes: f89120b6f554 ("ARM: dts: sun8i: Add the H3/H5 CSI controller") Reviewed-by: Jagan Teki Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index a4c757c0b741..d74a6cbbfdf4 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -740,8 +740,7 @@ }; csi: camera@1cb0000 { - compatible = "allwinner,sun8i-h3-csi", - "allwinner,sun6i-a31-csi"; + compatible = "allwinner,sun8i-h3-csi"; reg = <0x01cb0000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_CSI>, -- cgit v1.2.3 From 7da10df988ca3bf9a07a21ae1f7bc58ac20a600e Mon Sep 17 00:00:00 2001 From: Felix Brack Date: Tue, 18 Dec 2018 15:39:31 +0100 Subject: ARM: dts: am33xx: Remove unnecessary properties Remove the unnecessary properties #address-cells and #size-cells of node pinmux as there are no child-nodes with property reg. Signed-off-by: Felix Brack Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 7b818d9d2eab..e957370f8aec 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -288,8 +288,6 @@ am33xx_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x238>; - #address-cells = <1>; - #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; -- cgit v1.2.3 From a4aaf1242c2b3975437068d718142cb5ebf26e07 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:12:20 +0000 Subject: ARM: dts: am437x: replace linux,wakeup with wakeup-source property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the legacy "linux,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit aeda5003d0b9 ("Input: matrix_keypad - change name of wakeup property to "wakeup-source"") Cc: "Benoît Cousson" Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Sudeep Holla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index f4a20cade808..4c6ee37ea573 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -71,7 +71,7 @@ pinctrl-0 = <&matrix_keypad_default>; pinctrl-1 = <&matrix_keypad_sleep>; - linux,wakeup; + wakeup-source; row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ -- cgit v1.2.3 From dc81e8465d4a10deba37f5e62368a7d801e3dc0a Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 22 Jan 2019 06:26:22 +0100 Subject: ARM: dts: am335x-shc.dts: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Heiko Schocher Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-shc.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index d0fd68873689..5cdaf0cd9401 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * support for the bosch am335x based shc c3 board * * Copyright, C) 2015 Heiko Schocher * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; -- cgit v1.2.3 From b4c30df0eb354d8e081132b7b7449f6d17619614 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 13 Dec 2018 15:58:45 +0200 Subject: ARM: dts: omap4-sdp: Make ethernet working even if booted with latest u-boot The ethernet works in kernel only if we use some binary u-boot from the past which have support for KS8851. The u-boot sources are not available for this mysterious u-boot image people tends to hold on... Mainline u-bott does not have ethernet support for sdp4430 and if we use that the ethernet is not working. After some debugging I have managed to get the ethernet working with mainline u-boot while not breaking the networking with the case when we boot with the mysterious binary u-boot. Basically we were missing bunch of pinmux settings and the 'magic' gpio_138 handling in kernel. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-sdp.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 9dc7ec7655cb..c88817bdcc56 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -26,6 +26,9 @@ }; vdd_eth: fixedregulator-vdd-eth { + pinctrl-names = "default"; + pinctrl-0 = <&enet_enable_gpio>; + compatible = "regulator-fixed"; regulator-name = "VDD_ETH"; regulator-min-microvolt = <3300000>; @@ -352,6 +355,29 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; + + /* gpio_48 for ENET_ENABLE */ + enet_enable_gpio: pinmux_enet_enable_gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ + >; + }; + + ks8851_pins: pinmux_ks8851_pins { + pinctrl-single,pins = < + /* ENET_INT */ + OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ + /* + * Misterious pin which makes the ethernet working + * The legacy board file requested this pin on boot + * (ETH_KS8851_QUART) and set it to high, similarly to + * the ENET_ENABLE pin. + * We could use gpio-hog to keep it high, but let's use + * it as a reset GPIO for ks8851. + */ + OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */ + >; + }; }; &i2c1 { @@ -452,12 +478,16 @@ pinctrl-0 = <&mcspi1_pins>; eth@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ks8851_pins>; + compatible = "ks8851"; spi-max-frequency = <24000000>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ vdd-supply = <&vdd_eth>; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; }; }; -- cgit v1.2.3 From 417992d5744fe943d79f6681e29e7a54bb97e2e0 Mon Sep 17 00:00:00 2001 From: Graeme Smecher Date: Thu, 3 Jan 2019 15:16:27 -0800 Subject: ARM: dts: ti81xx: Add dts boilerplate for all GPIO and SPI peripherals GPIO3/4 and MCSPI2/3/4 are now present. Lightly tested on am3874 platform. Signed-off-by: Graeme Smecher [tony@atomide.com: split to apply hwmod and dts changes separately] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 601c57afd4fe..f044abd64b7e 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -222,6 +222,30 @@ #interrupt-cells = <2>; }; + gpio3: gpio@1ac000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + ti,gpio-always-on; + reg = <0x1ac000 0x2000>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@1ae000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + ti,gpio-always-on; + reg = <0x1ae000 0x2000>; + interrupts = <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + i2c2: i2c@2a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; @@ -240,10 +264,48 @@ ti,spi-num-cs = <4>; ti,hwmods = "mcspi1"; dmas = <&edma 16 0 &edma 17 0 - &edma 18 0 &edma 19 0>; + &edma 18 0 &edma 19 0 + &edma 20 0 &edma 21 0 + &edma 22 0 &edma 23 0>; + + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mcspi2: spi@1a0000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <125>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi2"; + dmas = <&edma 42 0 &edma 43 0 + &edma 44 0 &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; + /* Board must configure dmas with edma_xbar for EDMA */ + mcspi3: spi@1a2000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a2000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <126>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi3"; + }; + + mcspi4: spi@1a4000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <127>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi4"; + }; + timer1: timer@2e000 { compatible = "ti,dm814-timer"; reg = <0x2e000 0x2000>; -- cgit v1.2.3 From d031773169df2de868c1b6ff75679ddac5d4a7ec Mon Sep 17 00:00:00 2001 From: Graeme Smecher Date: Thu, 24 Jan 2019 10:15:58 -0800 Subject: ARM: dts: Adds device tree file for McGill's IceBoard, based on TI AM3874 This is an ARM + FPGA instrumentation board used at telescopes in Antarctica, Chile, and Canada: https://pole.uchicago.edu/ https://arxiv.org/abs/1608.03025 https://chime-experiment.ca/ With these commits and a suitable userspace, we can boot the board, load a FPGA bitstream, and communicate with the RTL design. Most of the board's telemetry sensors (temperatures, voltages) are functional but detailed testing is to follow. We are weaning ourselves off TI's "official" kernel for this SOC, which has been stuck at 2.6.37 and is not really fit for use. To anyone at TI: despite good silicon and some dedicated support enginers, your open-source software strategy for these parts has not worked well. Please get in touch with me if you'd like to have a constructive discussion about ways to improve it. Signed-off-by: Graeme Smecher [tony@atomide.com: dropped fpga@1 as linux,spidev is still undocumented] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am3874-iceboard.dts | 496 ++++++++++++++++++++++++++++++++++ 2 files changed, 497 insertions(+) create mode 100644 arch/arm/boot/dts/am3874-iceboard.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d87a165abebd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -700,6 +700,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-thunder.dtb \ omap3-zoom3.dtb dtb-$(CONFIG_SOC_TI81XX) += \ + am3874-iceboard.dtb \ dm8148-evm.dtb \ dm8148-t410.dtb \ dm8168-evm.dtb \ diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts new file mode 100644 index 000000000000..883fb85135d4 --- /dev/null +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Winterland IceBoard + * + * http://mcgillcosmology.com + * http://threespeedlogic.com + * + * This is an ARM + FPGA instrumentation board used at telescopes in + * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO + * observatory in British Columbia (CHIME). + * + * Copyright (c) 2019 Three-Speed Logic, Inc. + */ + +/dts-v1/; + +#include "dm814x.dtsi" +#include + +/ { + model = "Winterland IceBoard"; + compatible = "ti,dm8148", "ti,dm814"; + + chosen { + stdout-path = "serial1:115200n8"; + bootargs = "earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* The MAC provides internal delay for the transmit path ONLY, which is enabled + * provided no -id/-txid/-rxid suffix is provided to "phy-mode". + * + * The receive path is delayed at the PHY. The recommended register settings + * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the + * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, + * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to + * obtain the correct register settings. + */ +&mac { dual_emac = <1>; }; +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; +&cpsw_emac1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + ethphy0: ethernet-phy@0 { + reg = <0x2>; + + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + + rxd3-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd0-skew-ps = <0>; + + phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@1 { + reg = <0x1>; + + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + + rxd3-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd0-skew-ps = <0>; + + phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc1 { status = "disabled"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; +&mmc3 { status = "disabled"; }; + +&i2c1 { + /* Most I2C activity happens through this port, with the sole exception + * of the backplane. Since there are multiply assigned addresses, the + * "i2c-mux-idle-disconnect" is important. + */ + + pca9548@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + /* FMC A */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + i2c-mux-idle-disconnect; + }; + + i2c@1 { + /* FMC B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + i2c-mux-idle-disconnect; + }; + + i2c@2 { + /* QSFP A */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + i2c-mux-idle-disconnect; + }; + + i2c@3 { + /* QSFP B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + i2c-mux-idle-disconnect; + }; + + i2c@4 { + /* SFP */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + i2c-mux-idle-disconnect; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + i2c-mux-idle-disconnect; + + ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; + ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; + ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; + + ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; + ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; + ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; + + ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; + ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; + ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; + ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; + ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; + ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; + ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; + ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; + ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; + }; + + i2c@6 { + /* Backplane */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + i2c-mux-idle-disconnect; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + i2c-mux-idle-disconnect; + + u41: pca9575@20 { + compatible = "nxp,pca9575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", + "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", + "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", + "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u42: pca9575@21 { + compatible = "nxp,pca9575"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", + "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", + "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", + "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u48: pca9575@22 { + compatible = "nxp,pca9575"; + reg=<0x22>; + gpio-controller; + #gpio-cells = <2>; + + sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, + <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; + led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, + <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; + + gpio-line-names = + "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", + "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", + "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", + "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u59: pca9575@23 { + compatible = "nxp,pca9575"; + reg=<0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", + "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", + "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", + "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; + tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; + tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; + tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; + + /* EEPROM bank and serial number are treated as separate devices */ + at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; + at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; + }; + }; +}; + +&i2c2 { + pca9548@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@6 { + /* Backplane */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + multi-master; + + /* All backplanes should have this -- it's how we know they're there. */ + at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; + at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; + + /* 16 slot backplane */ + tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; + tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; + ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; + amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; + + /* Single slot backplane */ + }; + }; +}; + +&pincntl { + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ + DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ + DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ + DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ + DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ + DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ + DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ + DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ + DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ + >; + }; + + usb0_pins: pinmux_usb0_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ + >; + }; + + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ + DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ + DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ + + DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ + DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ + DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ + DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ + DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ + + DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ + DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ + DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ + DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ + DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ + + DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ + DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ + DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ + DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ + >; + }; + + gpio2_pins: pinmux_gpio2_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ + DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ + DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ + DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ + + //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ + //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ + DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ + >; + }; + + gpio4_pins: pinmux_gpio4_pins { + pinctrl-single,pins = < + /* The PLL doesn't react well to the SPI controller reset, so + * we force the CS lines to pull up as GPIOs until we're ready. + * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 + */ + DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ + DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ + DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ + DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ + DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ + DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ + >; + }; + + spi2_pins: pinmux_spi2_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ + DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ + >; + }; + + spi4_pins: pinmux_spi4_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0a7c, 0x20) + DM814X_IOPAD(0x0b74, 0x20) + DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) + DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) + DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) + >; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; + gpio-line-names = + "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ + "", "", "", "FMCA_TRST", /* 12-15 */ + "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ + "FMCB_TRST", "", "", "", /* 20-23 */ + "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ + "", "", "", ""; /* 28-31 */ +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_pins>; + gpio-line-names = + "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ + "", "", "", "PHYB_IRQ_N", /* 4-7 */ + "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ +}; + +&gpio3 { + pinctrl-names = "default"; + /*pinctrl-0 = <&gpio3_pins>;*/ + gpio-line-names = + "", "", "ARMClkSel0", "", /* 0-3 */ + "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio4_pins>; + gpio-line-names = + "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", + "BP_ARM_GPIO4", "BP_ARM_GPIO5"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; +}; + +&mcspi1 { + s25fl256@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + + fsbl@0 { + /* 256 kB */ + label = "U-Boot-min"; + reg = <0 0x40000>; + }; + ssbl@1 { + /* 512 kB */ + label = "U-Boot"; + reg = <0x40000 0x80000>; + }; + bootenv@2 { + /* 256 kB */ + label = "U-Boot Env"; + reg = <0xc0000 0x40000>; + }; + kernel@3 { + /* 4 MB */ + label = "Kernel"; + reg = <0x100000 0x400000>; + }; + ipmi@4 { + label = "IPMI FRU"; + reg = <0x500000 0x40000>; + }; + fs@5 { + label = "File System"; + reg = <0x540000 0x1ac0000>; + }; + }; +}; + +&mcspi3 { + /* DMA event numbers stolen from MCASP */ + dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 + &edma_xbar 10 0 18 &edma_xbar 11 0 19>; + dma-names = "tx0", "rx0", "tx1", "rx1"; +}; + +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + + /* DMA event numbers stolen from MCASP, MCBSP */ + dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; + dma-names = "tx0", "rx0"; +}; -- cgit v1.2.3 From d027521497592773cd23d016d36975574d3452db Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:10 +0800 Subject: ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by address The NAND controller device node was inserted into the wrong position, probably due to a rebase or merge, as the file's structure does not provide enough context for git to accurately match the previous device node block. Fixes: d7b843df13ea ("ARM: dts: sun8i: add NAND controller node for A23/A33") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a9c123de5d2c..97ec8b8cec09 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -155,6 +155,19 @@ #dma-cells = <1>; }; + nfc: nand@1c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -214,21 +227,6 @@ #size-cells = <0>; }; - nfc: nand@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_NAND>; - reset-names = "ahb"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - usb_otg: usb@1c19000 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c19000 0x0400>; -- cgit v1.2.3 From 437262c0db5de0f3d351592fe92b581dcaf91869 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:11 +0800 Subject: ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi The display pipeline has the same structure, resources and connections on both the A23 and A33. The differences include: - compatible strings - extra clock, reset control, and IO region for SAT in the backend only found on the A33 - missing ch1 clock for the TCON However, while the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). As the MIPI DSI output device is not officially documented, and there are no A23 reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 147 ++++++++++++++++++++++++++ arch/arm/boot/dts/sun8i-a33.dtsi | 194 +++++++---------------------------- 2 files changed, 185 insertions(+), 156 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 97ec8b8cec09..43fe215e83ea 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -68,6 +68,12 @@ }; }; + de: display-engine { + /* compatible gets set in SoC specific dtsi file */ + allwinner,pipelines = <&fe0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -168,6 +174,42 @@ #size-cells = <0>; }; + tcon0: lcd-controller@1c0c000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD>, + <&ccu CLK_LCD_CH0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_LCD>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -570,6 +612,111 @@ interrupts = ; }; + fe0: display-frontend@1e00000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e00000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_FE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e60000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_BE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@1e70000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e70000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, + <&ccu CLK_DRAM_DRC>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_DRC>; + + assigned-clocks = <&ccu CLK_DRC>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun8i-a23-rtc"; reg = <0x01f00000 0x400>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 626152c30f50..1111a6498102 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -159,12 +159,6 @@ }; }; - de: display-engine { - compatible = "allwinner,sun8i-a33-display-engine"; - allwinner,pipelines = <&fe0>; - status = "disabled"; - }; - iio-hwmon { compatible = "iio-hwmon"; io-channels = <&ths>; @@ -209,47 +203,6 @@ }; soc { - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-a33-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD>, - <&ccu CLK_LCD_CH0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - resets = <&ccu RST_BUS_LCD>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon0>; - }; - }; - }; - }; - video-codec@1c0e000 { compatible = "allwinner,sun8i-a33-video-engine"; reg = <0x01c0e000 0x1000>; @@ -339,115 +292,6 @@ status = "disabled"; #phy-cells = <0>; }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun8i-a33-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_FE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun8i-a33-display-backend"; - reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; - reg-names = "be", "sat"; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; - clock-names = "ahb", "mod", - "ram", "sat"; - resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; - reset-names = "be", "sat"; - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@1e70000 { - compatible = "allwinner,sun8i-a33-drc"; - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, - <&ccu CLK_DRAM_DRC>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_DRC>; - - assigned-clocks = <&ccu CLK_DRC>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - drc0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; }; thermal-zones { @@ -524,10 +368,37 @@ }; }; +&be0 { + compatible = "allwinner,sun8i-a33-display-backend"; + /* A33 has an extra "SAT" module packed inside the display backend */ + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + assigned-clocks = <&ccu CLK_DE_BE>; + assigned-clock-rates = <300000000>; +}; + &ccu { compatible = "allwinner,sun8i-a33-ccu"; }; +&de { + compatible = "allwinner,sun8i-a33-display-engine"; +}; + +&drc0 { + compatible = "allwinner,sun8i-a33-drc"; +}; + +&fe0 { + compatible = "allwinner,sun8i-a33-display-frontend"; +}; + &mali { operating-points-v2 = <&mali_opp_table>; }; @@ -544,6 +415,17 @@ }; +&tcon0 { + compatible = "allwinner,sun8i-a33-tcon"; +}; + +&tcon0_out { + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + }; +}; + &usb_otg { compatible = "allwinner,sun8i-a33-musb"; }; -- cgit v1.2.3 From 4672f69561898d7e1e179608f6db164f9f8e82fa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:12 +0800 Subject: ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodes Now that the compatible strings for the display pipeline on the A23 have been added to the bindings, add the corresponding compatibles to the device nodes already in the A23/A33 shared dtsi. While the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). Hence the ch1 clock is left out. As the MIPI DSI output device is not officially documented, and there are no reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index d00055e9eef5..a5e884a8b2ae 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -62,10 +62,26 @@ }; }; +&be0 { + compatible = "allwinner,sun8i-a23-display-backend"; +}; + &ccu { compatible = "allwinner,sun8i-a23-ccu"; }; +&de { + compatible = "allwinner,sun8i-a23-display-engine"; +}; + +&drc0 { + compatible = "allwinner,sun8i-a23-drc"; +}; + +&fe0 { + compatible = "allwinner,sun8i-a23-display-frontend"; +}; + &pio { compatible = "allwinner,sun8i-a23-pinctrl"; interrupts = , @@ -73,6 +89,10 @@ ; }; +&tcon0 { + compatible = "allwinner,sun8i-a23-tcon"; +}; + &usb_otg { compatible = "allwinner,sun6i-a31-musb"; }; -- cgit v1.2.3 From fe244e4c6a0b5acb2b2049fe792c538e70a0d10b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:13 +0800 Subject: ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panel The Q8 design for A23/A33 tablets have an 18-bit RGB LCD panel connected to the LCD interface on the SoC, the DC1SW output on the PMIC providing power for the LCD, and PH7 toggling the reset pin for the panel. This patch adds a device node for the panel, describing the above, and enables the display pipeline. The actual model or compatible string for the panel should be added in the tablet device tree file. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-q8-common.dtsi | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 719ad769b837..53104f4ccacc 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -49,6 +49,26 @@ ethernet0 = &sdio_wifi; }; + panel: panel { + /* Tablet dts should provide panel compatible */ + backlight = <&backlight>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_dc1sw>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; /* @@ -64,6 +84,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -90,6 +114,19 @@ }; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; -- cgit v1.2.3 From 55533921301e83162584f87fe571545056d03e09 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:14 +0800 Subject: ARM: dts: sun8i-a23-q8: Set compatible string for LCD panel The Q8 tablets follow the A23/A33 tablet reference design, and normally use a "generic" 800x480 LCD panel. The actual panel may vary between production runs, and there are no visible markings denoting its model. This patch uses a panel that has the same dimensions and timings that are close to what was provided in the vendor fex files. Since there are also A33 Q8 tablets with 1024x600 panels, this patch only sets the compatible string for A23 Q8 tablets. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts index b6958e8f2f01..d4dab7c28398 100644 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts @@ -61,3 +61,7 @@ "Headset Mic", "HBIAS"; status = "okay"; }; + +&panel { + compatible = "bananapi,s070wv20-ct16", "simple-panel"; +}; -- cgit v1.2.3 From ec33745bccc8f336957c751f4153421cc9ef5a54 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 24 Jan 2019 13:22:57 +0100 Subject: ARM: dts: exynos: Fix pinctrl definition for eMMC RTSN line on Odroid X2/U3 Commit 225da7e65a03 ("ARM: dts: add eMMC reset line for exynos4412-odroid-common") added MMC power sequence for eMMC card of Odroid X2/U3. It reused generic sd1_cd pin control configuration node and only disabled pull-up. However that time the pinctrl configuration was not applied during MMC power sequence driver initialization. This has been changed later by commit d97a1e5d7cd2 ("mmc: pwrseq: convert to proper platform device"). It turned out then, that the provided pinctrl configuration is not correct, because the eMMC_RTSN line is being re-configured as 'special function/card detect function for mmc1 controller' not the simple 'output', thus the power sequence driver doesn't really set the pin value. This in effect broke the reboot of Odroid X2/U3 boards. Fix this by providing separate node with eMMC_RTSN pin configuration. Cc: Reported-by: Markus Reichl Suggested-by: Ulf Hansson Fixes: 225da7e65a03 ("ARM: dts: add eMMC reset line for exynos4412-odroid-common") Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 24bcad3dfba9..08d3a0a7b4eb 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -49,7 +49,7 @@ }; emmc_pwrseq: pwrseq { - pinctrl-0 = <&sd1_cd>; + pinctrl-0 = <&emmc_rstn>; pinctrl-names = "default"; compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; @@ -165,12 +165,6 @@ cpu0-supply = <&buck2_reg>; }; -/* RSTN signal for eMMC */ -&sd1_cd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; @@ -188,6 +182,11 @@ samsung,pins = "gpx3-7"; samsung,pin-pud = ; }; + + emmc_rstn: emmc-rstn { + samsung,pins = "gpk1-2"; + samsung,pin-pud = ; + }; }; &ehci { -- cgit v1.2.3 From ee65af7f9f425078147107a92e3dc268cad1d591 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 17 Nov 2016 04:06:15 +0200 Subject: ARM: dts: lpc435x: remove address and size cells from gpio-keys-polled nodes The change removes redundant #address-cells and #size-cells properties from gpio-keys-polled compatible device nodes found in lpc4357-ea4357-devkit and lpc4350-hitex-eval board DTS files. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 2 -- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index 8b973f537d3a..93d0c2e99e7c 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -40,8 +40,6 @@ pca_buttons { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; autorepeat; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 02b23fa29d75..224f80a4a31d 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -57,8 +57,6 @@ compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&gpio_joystick_pins>; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; autorepeat; -- cgit v1.2.3 From e6b97a47b5b9512828859778acafd3fe107b395e Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 22 Jan 2019 16:35:47 +0800 Subject: ARM: dts: rockchip: clean up the abuse of disable-wp The mmc.txt didn't explicitly say disable-wp is for SD card slot only, but that is what it was designed for in the first place. Remove all disable-wp from emmc or sdio controller. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 1 - arch/arm/boot/dts/rk3066a-mk808.dts | 1 - arch/arm/boot/dts/rk3066a-rayeager.dts | 2 -- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 1 - arch/arm/boot/dts/rk3188-px3-evb.dts | 1 - arch/arm/boot/dts/rk3229-evb.dts | 1 - arch/arm/boot/dts/rk3288-fennec.dts | 1 - arch/arm/boot/dts/rk3288-firefly-reload.dts | 1 - arch/arm/boot/dts/rk3288-miqi.dts | 1 - arch/arm/boot/dts/rk3288-popmetal.dts | 1 - arch/arm/boot/dts/rk3288-rock2-square.dts | 1 - arch/arm/boot/dts/rk3288-tinker-s.dts | 1 - arch/arm/boot/dts/rk3288-vyasa.dts | 1 - 13 files changed, 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 1c925f20dba0..0a56a2f1bc4d 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -171,7 +171,6 @@ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; bus-width = <4>; - disable-wp; }; &pwm3 { diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index b6a8a82d219e..9d2216d71f70 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -101,7 +101,6 @@ &mmc1 { bus-width = <4>; - disable-wp; non-removable; pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index cd126b927ba8..949fa800582d 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -147,7 +147,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; @@ -309,7 +308,6 @@ &mmc1 { bus-width = <4>; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 887d1aa8d0e1..cc66abb22170 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -227,7 +227,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd>; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 9ae65c767c90..c0eaa9c5490b 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -62,7 +62,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 4df7accc3ad7..350497a3ca86 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -137,7 +137,6 @@ &emmc { cap-mmc-highspeed; - disable-wp; non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index b1b56dfdfdba..29af26e6d442 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -37,7 +37,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 58ea8bed040a..3a646c5f4fcf 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -254,7 +254,6 @@ bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; - disable-wp; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 504ab1177aa7..fb7365b604bb 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -87,7 +87,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 596435e03132..6a51940398b5 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -109,7 +109,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; mmc-ddr-1_8v; mmc-hs200-1_8v; non-removable; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 6a30cadad88a..5b7e1c9e92e1 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -133,7 +133,6 @@ bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; - disable-wp; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts index 37093922b482..d97da89bcd51 100644 --- a/arch/arm/boot/dts/rk3288-tinker-s.dts +++ b/arch/arm/boot/dts/rk3288-tinker-s.dts @@ -15,7 +15,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 4856a9fc0aea..40b232eb5011 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -121,7 +121,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; -- cgit v1.2.3 From 4199ca2a49c6dd47a436a11243676d879c152677 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:34 +0800 Subject: ARM: dts: sun5i: Add backlight GPIO for reference design tablet Now that we support the GPIOs on the AXP209, we can control the LCD backlight with them. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 6202aabedbfe..5b1f0e198eb6 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -54,7 +54,7 @@ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ }; chosen { -- cgit v1.2.3 From 0a03cd9924dcf09b4c0945776df90546a64c82df Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:35 +0800 Subject: ARM: dts: sun5i: q8-tablet: Move panel properties to correct node level The panel backlight and enable GPIO comments were incorrectly placed in the input port, while it should have been in the panel node itself. Move them to the correct position. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index a89f29fa3e40..3a844dae26f7 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -50,13 +50,13 @@ panel: panel { compatible = "urt,umsh-8596md-t", "simple-panel"; + /* TODO: lcd panel uses axp gpio0 as enable pin */ + backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - /* TODO: lcd panel uses axp gpio0 as enable pin */ - backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 4d58c8cc93bce6ed8180c6ec8da216bfdca397dd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:36 +0800 Subject: ARM: dts: sun5i: q8-tablet: Add LCD Panel enable GPIO Now that we support the AXP209 GPIOs, we can toggle the LCD panel enable line. Add the GPIO phandle to the panel. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index 3a844dae26f7..ead159f89e74 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -50,7 +50,7 @@ panel: panel { compatible = "urt,umsh-8596md-t", "simple-panel"; - /* TODO: lcd panel uses axp gpio0 as enable pin */ + enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 64af290124fc067f248d1f667cd04e77578b4877 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:37 +0800 Subject: ARM: dts: sun5i: q8-tablet: Add LCD Panel power supply The A13 Q8 tablet, following the A13 reference tablet design, has the system's fixed 3.3V rail feed the VCC supply of the LCD panel. Additional voltage rails used by the panel are generated using a regulator fed from the unregulated IPSOUT output of the PMIC. The latter is unrepresentable in the device tree. Both are controlled with MOSFETs by the enable GPIO added in the previous patch. The actual enable or reset pin for the panel is tied directly to LCD-VCC after the MOSFET. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index ead159f89e74..c77c0758145a 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -50,6 +50,7 @@ panel: panel { compatible = "urt,umsh-8596md-t", "simple-panel"; + power-supply = <®_vcc3v3>; enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; #address-cells = <1>; -- cgit v1.2.3 From 8f855dbfaf5d0c63f1a6fd7aaeea61ba21e886d2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:38 +0800 Subject: ARM: dts: sun5i: q8-tablet: Use bananapi,s070wv20-ct16 panel compatible The compatible string for the LCD panel used for the Q8 tablets are just a placeholder that was shown to be compatible with the actual panels found on these devices. The real panels do not have any identifiable markings and vary between production runs. The compatibe string previously used had a pixel clock that could not be accurately reproduced on Allwinner hardware, and discussions on whether a margin should be added to the display drivers and how large a margin was acceptable had stalled. Now that we have a panel model that is actually used with Allwinner hardware, has the same dimensions, and the timings have been shown to work with the nameless panels, we can use that one instead. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index c77c0758145a..7257f39b31ce 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -49,7 +49,7 @@ compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; panel: panel { - compatible = "urt,umsh-8596md-t", "simple-panel"; + compatible = "bananapi,s070wv20-ct16", "simple-panel"; power-supply = <®_vcc3v3>; enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; -- cgit v1.2.3 From cc0dbf43668db407692deaf2023d4adbeeef9633 Mon Sep 17 00:00:00 2001 From: Dietmar Eggemann Date: Mon, 28 Jan 2019 16:55:22 +0000 Subject: arm: dts: vexpress-v2p-ca15_a7: Add cpu dynamic-power-coefficient information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A CPUfreq driver, like the ARM big.LITTLE driver used on the TC2 board, which provide the Energy Model with power cost information via the PM_OPP of_dev_pm_opp_get_cpu_power() function, do need the dynamic-power-coefficient (C) in the device tree. Method used to obtain the C value: C is computed by measuring energy (E) consumption of a frequency domain (FD) over a 10s runtime (t) sysbench workload running at each Operating Performance Point (OPP) affine to 1 or 2 CPUs of that FD while the other CPUs of the system are hotplugged out. By definition all CPUs of a FD have the the same micro-architecture. An OPP is characterized by a certain frequency (f) and voltage (V) value. The corresponding power values (P) are calculated by dividing the delta of the E values between the runs with 2 and 1 CPUs by t. With n data tuples (P, f, V), n equal to number of OPPs for this frequency domain, we can solve C by: P = Pstat + Pdyn P = Pstat + CV²f Cx = (Px - P1)/(Vx²fx - V1²f1) with x = {2, ..., n} The C value is the arithmetic mean out of {C2, ..., Cn}. Signed-off-by: Dietmar Eggemann Signed-off-by: Quentin Perret Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index a2ccacd07f4f..00cd9f5bef2e 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -42,6 +42,7 @@ cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <990>; }; cpu1: cpu@1 { @@ -51,6 +52,7 @@ cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <990>; }; cpu2: cpu@2 { @@ -60,6 +62,7 @@ cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; }; cpu3: cpu@3 { @@ -69,6 +72,7 @@ cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; }; cpu4: cpu@4 { @@ -78,6 +82,7 @@ cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; }; idle-states { -- cgit v1.2.3 From 1c909b2dfe6a21de2c24dc1c1405593e40e3a88c Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 29 Jan 2019 20:46:25 +0100 Subject: ARM: dts: socfpga: update more missing reset properties Add reset property for dma, can and sdram on socfpga gen5. Signed-off-by: Simon Goldschmidt Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f365003f0102..ec1966480f2f 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -84,6 +84,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; }; }; @@ -100,6 +101,7 @@ reg = <0xffc00000 0x1000>; interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; status = "disabled"; }; @@ -108,6 +110,7 @@ reg = <0xffc01000 0x1000>; interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; status = "disabled"; }; @@ -791,6 +794,7 @@ sdr: sdr@ffc25000 { compatible = "altr,sdr-ctl", "syscon"; reg = <0xffc25000 0x1000>; + resets = <&rst SDR_RESET>; }; sdramedac { -- cgit v1.2.3 From c91d27bba78fa667b020ad08d66d8f16e5dba0ae Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Wed, 23 Jan 2019 15:07:32 -0800 Subject: ARM: dts: aspeed: tiogapass: Add LPC devices Added lpc control for enabling lpc clock and lpc snoop devices to Facebook Tiogapass device tree. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 73e58a821613..8040fa7c007f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -54,6 +54,16 @@ }; }; +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&lpc_ctrl { + // Enable lpc clock + status = "okay"; +}; + &uart1 { // Host Console status = "okay"; -- cgit v1.2.3 From e786eff92838f59a06932c56f0a64c7c050a3418 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Wed, 23 Jan 2019 15:07:33 -0800 Subject: ARM: dts: aspeed: tiogapass: Add uarts for SoL Added uart2 and uart3 in Facebook Tiogapass for routing serial input from Host to BMC for SoL via LPC. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 8040fa7c007f..4c2dcac738e8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -72,6 +72,16 @@ &pinctrl_rxd1_default>; }; +&uart2 { + // SoL Host Console + status = "okay"; +}; + +&uart3 { + // SoL BMC Console + status = "okay"; +}; + &uart5 { // BMC Console status = "okay"; -- cgit v1.2.3 From 95779307d7e8a730b8327eeca429736f6a8efb05 Mon Sep 17 00:00:00 2001 From: Patrick Venture Date: Tue, 29 Jan 2019 13:46:24 -0800 Subject: ARM: dts: aspeed: quanta-q71l: enable lpc_ctrl node Enable the lpc_ctrl node in the quanta-q71l dts such that the LPC_CLK is enabled. Signed-off-by: Patrick Venture Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index 385c0f4b69ee..999679b5ef55 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -116,6 +116,10 @@ status = "okay"; }; +&lpc_ctrl { + status = "okay"; +}; + &lpc_snoop { status = "okay"; snoop-ports = <0x80>; -- cgit v1.2.3 From e1542521499070f88b18846f676b4cd2a166aee5 Mon Sep 17 00:00:00 2001 From: Patrick Venture Date: Tue, 29 Jan 2019 13:47:02 -0800 Subject: ARM: dts: aspeed: quanta-q71l: enable uart1 Enable the uart1 node such that the clock will be enabled. Signed-off-by: Patrick Venture Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index 999679b5ef55..0d7c6339da46 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -138,6 +138,10 @@ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; }; +&uart1 { + status = "okay"; +}; + &uart5 { status = "okay"; }; -- cgit v1.2.3 From abe60a3a7afb4058278864aa18c5faf62094c11a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 9 Jan 2019 10:26:14 -0600 Subject: ARM: dts: Kill off skeleton{64}.dtsi Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij Reviewed-by: Florian Fainelli Reviewed-by: Matthias Brugger Acked-by: Viresh Kumar Acked-by: Alexandre Belloni Acked-by: Neil Armstrong Acked-by: Antoine Tenart Acked-by: Alexandre TORGUE Acked-by: Robert Jarzmik Acked-by: Vladimir Zapolskiy Tested-by: Kevin Hilman Reviewed-by: Kevin Hilman Tested-by: Martin Blumenstingl Reviewed-by: Martin Blumenstingl Signed-off-by: Rob Herring Reviewed-by: Gregory CLEMENT Tested-by: Gregory CLEMENT Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/alphascale-asm9260.dtsi | 3 ++- arch/arm/boot/dts/alpine.dtsi | 8 +++++++- arch/arm/boot/dts/arm-realview-eb.dtsi | 4 +++- arch/arm/boot/dts/arm-realview-pb1176.dts | 4 +++- arch/arm/boot/dts/arm-realview-pb11mp.dts | 4 +++- arch/arm/boot/dts/arm-realview-pbx.dtsi | 4 +++- arch/arm/boot/dts/armada-38x.dtsi | 4 +++- arch/arm/boot/dts/armada-39x.dtsi | 3 ++- arch/arm/boot/dts/artpec6.dtsi | 3 ++- arch/arm/boot/dts/at91rm9200.dtsi | 4 +++- arch/arm/boot/dts/at91sam9260.dtsi | 4 +++- arch/arm/boot/dts/at91sam9261.dtsi | 4 +++- arch/arm/boot/dts/at91sam9263.dtsi | 4 +++- arch/arm/boot/dts/at91sam9g45.dtsi | 4 +++- arch/arm/boot/dts/at91sam9n12.dtsi | 4 +++- arch/arm/boot/dts/at91sam9rl.dtsi | 4 +++- arch/arm/boot/dts/at91sam9x5.dtsi | 4 +++- arch/arm/boot/dts/atlas6-evb.dts | 1 + arch/arm/boot/dts/atlas6.dtsi | 1 - arch/arm/boot/dts/atlas7.dtsi | 1 - arch/arm/boot/dts/axm55xx.dtsi | 4 ++-- arch/arm/boot/dts/bcm-cygnus.dtsi | 9 +++++++-- arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++-- arch/arm/boot/dts/bcm11351.dtsi | 4 ++-- arch/arm/boot/dts/bcm21664-garnet.dts | 1 + arch/arm/boot/dts/bcm21664.dtsi | 4 ++-- arch/arm/boot/dts/bcm23550-sparrow.dts | 1 + arch/arm/boot/dts/bcm23550.dtsi | 4 ++-- arch/arm/boot/dts/bcm28155-ap.dts | 1 + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 1 + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 1 + arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 1 + arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 1 + arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 1 + arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 1 + arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 + arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 1 + arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 1 + arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 1 + arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 1 + arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 1 + arch/arm/boot/dts/bcm5301x.dtsi | 3 ++- arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts | 1 + arch/arm/boot/dts/bcm53573.dtsi | 3 ++- arch/arm/boot/dts/bcm63138.dtsi | 4 ++-- arch/arm/boot/dts/bcm7445.dtsi | 2 -- arch/arm/boot/dts/bcm947189acdbmr.dts | 1 + arch/arm/boot/dts/bcm953012er.dts | 1 + arch/arm/boot/dts/bcm953012hr.dts | 1 + arch/arm/boot/dts/bcm953012k.dts | 1 + arch/arm/boot/dts/cx92755.dtsi | 4 ++-- arch/arm/boot/dts/dove.dtsi | 4 ++-- arch/arm/boot/dts/ep7209.dtsi | 4 ++-- arch/arm/boot/dts/ep7211-edb7211.dts | 1 + arch/arm/boot/dts/integrator.dtsi | 10 ++++++++-- arch/arm/boot/dts/kirkwood.dtsi | 3 ++- arch/arm/boot/dts/lpc32xx.dtsi | 4 ++-- arch/arm/boot/dts/ls1021a.dtsi | 8 +++++++- arch/arm/boot/dts/meson.dtsi | 3 ++- arch/arm/boot/dts/meson6-atv1200.dts | 1 + arch/arm/boot/dts/meson8-minix-neo-x8.dts | 1 + arch/arm/boot/dts/meson8b-ec100.dts | 1 + arch/arm/boot/dts/meson8b-mxq.dts | 1 + arch/arm/boot/dts/meson8b-odroidc1.dts | 1 + arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 1 + arch/arm/boot/dts/mmp2-brownstone.dts | 1 + arch/arm/boot/dts/mmp2.dtsi | 4 +++- arch/arm/boot/dts/moxart.dtsi | 3 ++- arch/arm/boot/dts/mt2701-evb.dts | 1 + arch/arm/boot/dts/mt2701.dtsi | 3 ++- arch/arm/boot/dts/mt6580-evbp1.dts | 1 + arch/arm/boot/dts/mt6580.dtsi | 1 - arch/arm/boot/dts/mt6589-aquaris5.dts | 1 + arch/arm/boot/dts/mt6589.dtsi | 3 ++- arch/arm/boot/dts/mt6592-evb.dts | 2 +- arch/arm/boot/dts/mt6592.dtsi | 3 ++- arch/arm/boot/dts/mt8127-moose.dts | 1 + arch/arm/boot/dts/mt8127.dtsi | 3 ++- arch/arm/boot/dts/mt8135-evbp1.dts | 1 + arch/arm/boot/dts/mt8135.dtsi | 3 ++- arch/arm/boot/dts/nspire.dtsi | 4 ++-- arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 1 + .../boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 1 + arch/arm/boot/dts/orion5x-lswsgl.dts | 1 + arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts | 1 + arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 1 + arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 1 + arch/arm/boot/dts/orion5x.dtsi | 4 ++-- arch/arm/boot/dts/ox810se.dtsi | 4 +++- arch/arm/boot/dts/ox820.dtsi | 4 +++- arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 1 - arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 1 - arch/arm/boot/dts/prima2-evb.dts | 1 + arch/arm/boot/dts/prima2.dtsi | 1 - arch/arm/boot/dts/pxa168.dtsi | 4 +++- arch/arm/boot/dts/pxa2xx.dtsi | 3 ++- arch/arm/boot/dts/pxa910.dtsi | 4 +++- arch/arm/boot/dts/qcom-apq8064.dtsi | 8 +++++++- arch/arm/boot/dts/qcom-apq8084.dtsi | 9 +++++++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 +++++++- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++++- arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 1 + arch/arm/boot/dts/qcom-mdm9615.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8660.dtsi | 9 +++++++-- arch/arm/boot/dts/qcom-msm8960.dtsi | 9 +++++++-- arch/arm/boot/dts/qcom-msm8974.dtsi | 8 +++++++- arch/arm/boot/dts/sama5d2.dtsi | 4 +++- arch/arm/boot/dts/sama5d3.dtsi | 4 +++- arch/arm/boot/dts/sama5d4.dtsi | 4 +++- arch/arm/boot/dts/skeleton.dtsi | 18 ------------------ arch/arm/boot/dts/skeleton64.dtsi | 14 -------------- arch/arm/boot/dts/spear13xx.dtsi | 4 ++-- arch/arm/boot/dts/spear3xx.dtsi | 4 ++-- arch/arm/boot/dts/spear600.dtsi | 4 ++-- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 2 +- arch/arm/boot/dts/ste-u300.dts | 2 +- arch/arm/boot/dts/stm32429i-eval.dts | 1 + arch/arm/boot/dts/stm32746g-eval.dts | 1 + arch/arm/boot/dts/stm32f429-disco.dts | 1 + arch/arm/boot/dts/stm32f429.dtsi | 4 +++- arch/arm/boot/dts/stm32f469-disco.dts | 1 + arch/arm/boot/dts/stm32f746-disco.dts | 1 + arch/arm/boot/dts/stm32f746.dtsi | 4 +++- arch/arm/boot/dts/stm32f769-disco.dts | 1 + arch/arm/boot/dts/stm32h743.dtsi | 4 +++- arch/arm/boot/dts/stm32h743i-disco.dts | 1 + arch/arm/boot/dts/stm32h743i-eval.dts | 1 + arch/arm/boot/dts/stm32mp157c-ed1.dts | 1 + arch/arm/boot/dts/versatile-ab.dts | 2 +- arch/arm/boot/dts/vt8500.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8505.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8650.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8750.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8850.dtsi | 9 +++++++-- arch/arm/boot/dts/zx296702-ad1.dts | 1 + arch/arm/boot/dts/zx296702.dtsi | 4 +++- 141 files changed, 309 insertions(+), 141 deletions(-) delete mode 100644 arch/arm/boot/dts/skeleton.dtsi delete mode 100644 arch/arm/boot/dts/skeleton64.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale-asm9260.dtsi index 907fc7bfc418..2ce6038536fd 100644 --- a/arch/arm/boot/dts/alphascale-asm9260.dtsi +++ b/arch/arm/boot/dts/alphascale-asm9260.dtsi @@ -4,10 +4,11 @@ * Licensed under the X11 license or the GPL v2 (or later) */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&icoll>; memory { diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index 731df7a8c4e6..d3036ea823d1 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -25,12 +25,18 @@ */ #include -#include "skeleton64.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; /* SOC compatibility */ compatible = "al,alpine"; + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + /* CPU Configuration */ cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 0e4c7c4c8c09..610506723ea5 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -22,9 +22,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "arm,realview-eb"; chosen { }; @@ -38,6 +39,7 @@ }; memory { + device_type = "memory"; /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 83e0fbc4a1a1..cbbb8878daa3 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -23,9 +23,10 @@ /dts-v1/; #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; model = "ARM RealView PB1176"; compatible = "arm,realview-pb1176"; @@ -40,6 +41,7 @@ }; memory { + device_type = "memory"; /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 2f6aa24a0b67..2015619ca22c 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -23,9 +23,10 @@ /dts-v1/; #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; model = "ARM RealView PB11MPcore"; compatible = "arm,realview-pb11mp"; @@ -39,6 +40,7 @@ }; memory { + device_type = "memory"; /* * The PB11MPCore has 512 MiB memory @ 0x70000000 * and the first 256 are also remapped @ 0x00000000 diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index 916a97734f84..a81e9c282432 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -22,9 +22,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "arm,realview-pbx"; chosen { }; @@ -39,6 +40,7 @@ }; memory { + device_type = "memory"; /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 929459c42760..746887f7be5a 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -9,13 +9,15 @@ * Thomas Petazzoni */ -#include "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 38x family SoC"; compatible = "marvell,armada380"; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index f0c949831efb..b1b86934c688 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -7,13 +7,14 @@ * Thomas Petazzoni */ -#include "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; model = "Marvell Armada 39x family SoC"; compatible = "marvell,armada390"; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3e4115c2cd75..037157e6c5ee 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -43,9 +43,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "axis,artpec6"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 2ad69a7fbc00..5a882a053816 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -10,13 +10,14 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91RM9200 family SoC"; compatible = "atmel,at91rm9200"; interrupt-parent = <&aic>; @@ -49,6 +50,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7cd9c3bc4dfb..3b58b94b53c9 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -8,13 +8,14 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9260 family SoC"; compatible = "atmel,at91sam9260"; interrupt-parent = <&aic>; @@ -46,6 +47,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 01d700b63b45..a907a1fdd24c 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -6,13 +6,14 @@ * Licensed under GPLv2 only. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9261 family SoC"; compatible = "atmel,at91sam9261"; interrupt-parent = <&aic>; @@ -43,6 +44,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index c5766da4e54e..3fb63d81f18e 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -6,13 +6,14 @@ * Licensed under GPLv2 only. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9263 family SoC"; compatible = "atmel,at91sam9263"; interrupt-parent = <&aic>; @@ -45,6 +46,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index d16db1fa7e15..f36819607131 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -9,7 +9,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -17,6 +16,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9G45 family SoC"; compatible = "atmel,at91sam9g45"; interrupt-parent = <&aic>; @@ -51,6 +52,7 @@ }; memory { + device_type = "memory"; reg = <0x70000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 37cb81f457b5..f71d65e6e510 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -7,7 +7,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -15,6 +14,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9N12 SoC"; compatible = "atmel,at91sam9n12"; interrupt-parent = <&aic>; @@ -47,6 +48,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 3862ff2f26e0..6b5777f3c20b 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -7,7 +7,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -15,6 +14,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9RL family SoC"; compatible = "atmel,at91sam9rl", "atmel,at91sam9"; interrupt-parent = <&aic>; @@ -48,6 +49,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 07443a387a8f..79c4956d3902 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -9,7 +9,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -17,6 +16,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9x5 family SoC"; compatible = "atmel,at91sam9x5"; interrupt-parent = <&aic>; @@ -49,6 +50,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts index ab042ca8dea1..40882419309d 100644 --- a/arch/arm/boot/dts/atlas6-evb.dts +++ b/arch/arm/boot/dts/atlas6-evb.dts @@ -15,6 +15,7 @@ compatible = "sirf,atlas6-cb", "sirf,atlas6"; memory { + device_type = "memory"; reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 29598667420b..5587b98032a3 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" / { compatible = "sirf,atlas6"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi index 83449b33de6b..f3de9af35b4d 100644 --- a/arch/arm/boot/dts/atlas7.dtsi +++ b/arch/arm/boot/dts/atlas7.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" / { compatible = "sirf,atlas7"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi index 47799f59faa5..2a93d3ee3b66 100644 --- a/arch/arm/boot/dts/axm55xx.dtsi +++ b/arch/arm/boot/dts/axm55xx.dtsi @@ -12,9 +12,9 @@ #include #include -#include "skeleton64.dtsi" - / { + #address-cells = <2>; + #size-cells = <2>; interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 253df7170a4e..5f7b46503a51 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -34,9 +34,9 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "brcm,cygnus"; model = "Broadcom Cygnus SoC"; interrupt-parent = <&gic>; @@ -45,6 +45,11 @@ ethernet0 = ð0; }; + memory { + device_type = "memory"; + reg = <0 0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 0d2538b46139..6925b30c2253 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -34,9 +34,9 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "brcm,nsp"; model = "Broadcom Northstar Plus SoC"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index db7cded1b7ad..b99c2e579622 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -16,9 +16,9 @@ #include "dt-bindings/clock/bcm281xx.h" -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; model = "BCM11351 SoC"; compatible = "brcm,bcm11351"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index e87cb26ddf84..8b045cfab64b 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -22,6 +22,7 @@ compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 266f2611dc22..758daa334148 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -16,9 +16,9 @@ #include "dt-bindings/clock/bcm21664.h" -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; model = "BCM21664 SoC"; compatible = "brcm,bcm21664"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts index 4d525ccb48c8..1c66b15f3013 100644 --- a/arch/arm/boot/dts/bcm23550-sparrow.dts +++ b/arch/arm/boot/dts/bcm23550-sparrow.dts @@ -46,6 +46,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; }; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index a7a643f38385..701198f5f498 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -36,9 +36,9 @@ /* BCM23550 and BCM21664 have almost identical clocks */ #include "dt-bindings/clock/bcm21664.h" -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; model = "BCM23550 SoC"; compatible = "brcm,bcm23550"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index 9ce91dd60cb6..fbfca83bd28f 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -22,6 +22,7 @@ compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index 76a2bab3bc6f..fe842f2f1ca7 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 69e3570e03dd..6fcbb0509ba0 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 0f6f0fe13bfb..b3e8cc90b13f 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index f77089744996..fdeaa895512f 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 4d427863756f..0d510cb15ec3 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 189cc3dcd6ef..962e89edba11 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 03c1ab188576..658a56ff8a5c 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 36efe410dcd7..5fd47eec4407 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index 3e5e9972cd97..6604be6ff0a0 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 7fd85475893d..567ebbd5a0e9 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 7acbecd42950..ac2d136ed334 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index f4558d9d2769..74371e821b1a 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index bdad7267255a..b44af63ee310 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 30719380b6c0..eebc0d43e220 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 74c83b0ca54e..1a5ec22a172c 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 214df18f3a75..42c1e1f3a4d5 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index e15e2a1e9d8c..5ad53ea52d0a 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index fd7af943fb0b..ac5266ee8d4c 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -13,9 +13,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; chipcommonA { diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts index 431cda514230..2e7fda9b998c 100644 --- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -20,6 +20,7 @@ }; memory@0 { + device_type = "memory"; reg = <0x00000000 0x08000000>, <0x68000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 5054fa9eb0d0..b29695bd4855 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -7,9 +7,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index f59764008b9c..e6a41e1b27fd 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -6,9 +6,9 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "brcm,bcm63138"; model = "Broadcom BCM63138 DSL SoC"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index c859aa6f358c..504a63236a5e 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -1,8 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include "skeleton.dtsi" - / { #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index ef263412fea5..4991700ae6b0 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -18,6 +18,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 17f63c7a0437..250a1d6f2d05 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -40,6 +40,7 @@ compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; memory { + device_type = "memory"; reg = <0x00000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 11b0f5ed99e6..9140be7ec053 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -46,6 +46,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index e798055d6989..52c4c6c9d3f1 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -44,6 +44,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi index a5a23c376418..d2e8f36f8c60 100644 --- a/arch/arm/boot/dts/cx92755.dtsi +++ b/arch/arm/boot/dts/cx92755.dtsi @@ -44,9 +44,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "cnxt,cx92755"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 250ad0535e8c..2e8a3977219f 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 -/include/ "skeleton.dtsi" - #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/ep7209.dtsi index aaf1261d2ee4..0e74222a5eae 100644 --- a/arch/arm/boot/dts/ep7209.dtsi +++ b/arch/arm/boot/dts/ep7209.dtsi @@ -6,11 +6,11 @@ /dts-v1/; -#include "skeleton.dtsi" - #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Cirrus Logic EP7209"; compatible = "cirrus,ep7209"; diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts index bc9d5b697452..3475c7777cbc 100644 --- a/arch/arm/boot/dts/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/ep7211-edb7211.dts @@ -12,6 +12,7 @@ compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; memory { + device_type = "memory"; reg = <0xc0000000 0x02000000>; }; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 4d58638d104b..1612a869a4f7 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -3,9 +3,15 @@ * SoC core Device Tree for the ARM Integrator platforms */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + core-module@10000000 { compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 81c7eda2c442..2161e23bd98e 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 -/include/ "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; compatible = "marvell,kirkwood"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index b7303a4e4236..44b468e4c37a 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -11,12 +11,12 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" - #include #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "nxp,lpc3220"; interrupt-parent = <&mic>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index ed0941292172..97c1e37e9997 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -45,11 +45,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton64.dtsi" #include #include / { + #address-cells = <2>; + #size-cells = <2>; compatible = "fsl,ls1021a"; interrupt-parent = <&gic>; @@ -88,6 +89,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e4645f612712..5c303092520a 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -47,9 +47,10 @@ #include #include -/include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; L2: l2-cache-controller@c4200000 { diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index fc48cff71ddf..997e69c5963e 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -61,6 +61,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 55fb090a40ef..8686abd5de7f 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -57,6 +57,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0872f6e3abf5..7b6bfb9e805d 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -23,6 +23,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index 5c9b76af8d42..08ddd7fb0bf8 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -60,6 +60,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 58669abda259..4de2b973513d 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -62,6 +62,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index f5853610b20b..32c7a460f21b 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -28,6 +28,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts index 350208c5e1ed..3da038ba5733 100644 --- a/arch/arm/boot/dts/mmp2-brownstone.dts +++ b/arch/arm/boot/dts/mmp2-brownstone.dts @@ -19,6 +19,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index ee03e0846740..f02fb97f515c 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi index da7b3237bfe9..cbf17656bcc7 100644 --- a/arch/arm/boot/dts/moxart.dtsi +++ b/arch/arm/boot/dts/moxart.dtsi @@ -5,10 +5,11 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "moxa,moxart"; model = "MOXART"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index be0edb3dae6c..88f8fd22302a 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -13,6 +13,7 @@ compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; memory { + device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 180377e56ef4..51e1305c6471 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -12,10 +12,11 @@ #include #include #include -#include "skeleton64.dtsi" #include "mt2701-pinfunc.h" / { + #address-cells = <2>; + #size-cells = <2>; compatible = "mediatek,mt2701"; interrupt-parent = <&cirq>; diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mt6580-evbp1.dts index ca137897ed60..755a0774a8ee 100644 --- a/arch/arm/boot/dts/mt6580-evbp1.dts +++ b/arch/arm/boot/dts/mt6580-evbp1.dts @@ -22,6 +22,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi index 2bdc5ed12fca..9e17698c0609 100644 --- a/arch/arm/boot/dts/mt6580.dtsi +++ b/arch/arm/boot/dts/mt6580.dtsi @@ -7,7 +7,6 @@ #include #include -#include "skeleton.dtsi" / { compatible = "mediatek,mt6580"; diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts index 7bbaa1279a26..1e7079a3b449 100644 --- a/arch/arm/boot/dts/mt6589-aquaris5.dts +++ b/arch/arm/boot/dts/mt6589-aquaris5.dts @@ -18,6 +18,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 28df8495686a..f3ccb70c0779 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -7,9 +7,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "mediatek,mt6589"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts index 02849f6548e3..5e00c1cca2d1 100644 --- a/arch/arm/boot/dts/mt6592-evb.dts +++ b/arch/arm/boot/dts/mt6592-evb.dts @@ -13,7 +13,7 @@ compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; - diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi index 8696ac891d60..3716f8db951c 100644 --- a/arch/arm/boot/dts/mt6592.dtsi +++ b/arch/arm/boot/dts/mt6592.dtsi @@ -7,9 +7,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "mediatek,mt6592"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts index 308829b2da86..560687af87dc 100644 --- a/arch/arm/boot/dts/mt8127-moose.dts +++ b/arch/arm/boot/dts/mt8127-moose.dts @@ -13,6 +13,7 @@ compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; memory { + device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi index 3adfc6f7859c..aced173c2a52 100644 --- a/arch/arm/boot/dts/mt8127.dtsi +++ b/arch/arm/boot/dts/mt8127.dtsi @@ -7,9 +7,10 @@ #include #include -#include "skeleton64.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; compatible = "mediatek,mt8127"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts index 0ace7a40a60d..f6147fe62f41 100644 --- a/arch/arm/boot/dts/mt8135-evbp1.dts +++ b/arch/arm/boot/dts/mt8135-evbp1.dts @@ -13,6 +13,7 @@ compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; memory { + device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 688069dc1533..0e4e835026db 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -9,10 +9,11 @@ #include #include #include -#include "skeleton64.dtsi" #include "mt8135-pinfunc.h" / { + #address-cells = <2>; + #size-cells = <2>; compatible = "mediatek,mt8135"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index 1a5ae4cd107f..5a3c1f9d1832 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -9,9 +9,9 @@ * */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&intc>; cpus { diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts index 8c2449da6f00..422958d13d42 100644 --- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts @@ -19,6 +19,7 @@ compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index b545d0f228a5..0043e0040153 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -25,6 +25,7 @@ compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts index 0d97ded66257..2fbc17d6dfa4 100644 --- a/arch/arm/boot/dts/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/orion5x-lswsgl.dts @@ -55,6 +55,7 @@ compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x8000000>; /* 128 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts index 0324cb54939d..0ca6208a267d 100644 --- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts @@ -19,6 +19,7 @@ compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts index 9f6ae4e1de06..ea081afa469d 100644 --- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -21,6 +21,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x2000000>; /* 32 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts index d1817af53e0b..487324f7c54e 100644 --- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts @@ -16,6 +16,7 @@ compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index fbccfbbab223..61e631b3fd8b 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -6,11 +6,11 @@ * warranty of any kind, whether express or implied. */ -#include "skeleton.dtsi" - #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; model = "Marvell Orion5x SoC"; compatible = "marvell,orion5x"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index c2b48a1838eb..3a26650de4eb 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -6,11 +6,12 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "oxsemi,ox810se"; cpus { @@ -25,6 +26,7 @@ }; memory { + device_type = "memory"; /* Max 256MB @ 0x48000000 */ reg = <0x48000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index 085bbd33eadc..f3239586f38d 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -6,12 +6,13 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "oxsemi,ox820"; cpus { @@ -35,6 +36,7 @@ }; memory { + device_type = "memory"; /* Max 512MB @ 0x60000000 */ reg = <0x60000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index a1266cf8776c..291a28f34762 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -10,7 +10,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -/include/ "skeleton.dtsi" / { model = "Picochip picoXcell PC3X2"; compatible = "picochip,pc3x2"; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index d78cd207eca1..bf9a39ea76b0 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -10,7 +10,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -/include/ "skeleton.dtsi" / { model = "Picochip picoXcell PC3X3"; compatible = "picochip,pc3x3"; diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts index 57286b4e7b87..55594b3bbc99 100644 --- a/arch/arm/boot/dts/prima2-evb.dts +++ b/arch/arm/boot/dts/prima2-evb.dts @@ -15,6 +15,7 @@ compatible = "sirf,prima2", "sirf,prima2-cb"; memory { + device_type = "memory"; reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 1ca1a9aa953f..54d4f8850e22 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" / { compatible = "sirf,prima2"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index b899e25cbb1b..7137f3550183 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index e83879d97aea..bd6bf6d9300f 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include "dt-bindings/clock/pxa-clock.h" #define PMGROUP(pin) #pin @@ -29,6 +28,8 @@ } / { + #address-cells = <1>; + #size-cells = <1>; model = "Marvell PXA2xx family SoC"; compatible = "marvell,pxa2xx"; interrupt-parent = <&pxairq>; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index 0868f6729be1..c88553a8ee29 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf427610..1374c2e52c20 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "skeleton.dtsi" #include #include #include @@ -10,6 +9,8 @@ #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; interrupt-parent = <&intc>; @@ -94,6 +95,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + thermal-zones { cpu-thermal0 { polling-delay-passive = <250>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 899f28533ed7..0a0fb147ebb9 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "skeleton.dtsi" - #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm APQ 8084"; compatible = "qcom,apq8084"; interrupt-parent = <&intc>; @@ -87,6 +87,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + firmware { scm { compatible = "qcom,scm"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 2d56008d8d6b..707017412be2 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -13,12 +13,13 @@ /dts-v1/; -#include "skeleton.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; @@ -133,6 +134,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = #include #include @@ -11,6 +10,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm IPQ8064"; compatible = "qcom,ipq8064"; interrupt-parent = <&intc>; @@ -45,6 +46,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = ; }; }; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c852b69229c9..e49f67ad5dbc 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -45,8 +45,6 @@ /dts-v1/; -/include/ "skeleton.dtsi" - #include #include #include @@ -54,6 +52,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MDM9615"; compatible = "qcom,mdm9615"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 70698941f64c..1c1a863fa0c2 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" - #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8660"; compatible = "qcom,msm8660"; interrupt-parent = <&intc>; @@ -39,6 +39,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; interrupts = <1 9 0x304>; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 1733d8f40ab1..f2aeaccdc1ad 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" - #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8960"; compatible = "qcom,msm8960"; interrupt-parent = <&intc>; @@ -44,6 +44,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ca266a5f021d..aa5ced5859c7 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -6,9 +6,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8974"; compatible = "qcom,msm8974"; interrupt-parent = <&intc>; @@ -130,6 +131,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + thermal-zones { cpu-thermal0 { polling-delay-passive = <250>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index dc2280d9127f..d159ee42ef29 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -43,13 +43,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel SAMA5D2 family SoC"; compatible = "atmel,sama5d2"; interrupt-parent = <&aic>; @@ -113,6 +114,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 1408fa4a62e4..02198772eb81 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -8,7 +8,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -16,6 +15,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel SAMA5D3 family SoC"; compatible = "atmel,sama5d3", "atmel,sama5"; interrupt-parent = <&aic>; @@ -56,6 +57,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2604fd07dd53..6c1e41f94549 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -43,7 +43,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include #include @@ -51,6 +50,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel SAMA5D4 family SoC"; compatible = "atmel,sama5d4"; interrupt-parent = <&aic>; @@ -90,6 +91,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi deleted file mode 100644 index 34eda68d9ea2..000000000000 --- a/arch/arm/boot/dts/skeleton.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This file is deprecated, and will be removed once existing users have been - * updated. New dts{,i} files should *not* include skeleton.dtsi, and should - * instead explicitly provide the below nodes only as required. - * - * Skeleton device tree; the bare minimum needed to boot; just include and - * add a compatible value. The bootloader will typically populate the memory - * node. - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0>; }; -}; diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi deleted file mode 100644 index 54e637752b9d..000000000000 --- a/arch/arm/boot/dts/skeleton64.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Skeleton device tree in the 64 bits version; the bare minimum - * needed to boot; just include and add a compatible value. The - * bootloader will typically populate the memory node. - */ - -/ { - #address-cells = <2>; - #size-cells = <2>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0 0>; }; -}; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 086b4b333249..390df643a174 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -11,9 +11,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; cpus { diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index 118135d75899..c47380763cae 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -11,9 +11,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&vic>; cpus { diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 00166eb9be86..0a634fb07452 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -9,9 +9,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "st,spear600"; cpus { diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index fca76a696d9d..f78b4eabd68c 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -4,13 +4,13 @@ */ #include -#include "skeleton.dtsi" / { #address-cells = <1>; #size-cells = <1>; memory { + device_type = "memory"; reg = <0x00000000 0x04000000>, <0x08000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 1bd1aba3322f..f4e7660fead7 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -4,7 +4,6 @@ */ /dts-v1/; -/include/ "skeleton.dtsi" / { model = "ST-Ericsson U300"; @@ -22,6 +21,7 @@ }; memory { + device_type = "memory"; reg = <0x48000000 0x03c00000>; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index ed7d7f46465e..73ea84df7bf4 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -61,6 +61,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 8c081eaf20fe..d90b0d1e18c7 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -55,6 +55,7 @@ }; memory { + device_type = "memory"; reg = <0xc0000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 5ceb2cf3777f..e19d0fe7dbda 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -60,6 +60,7 @@ }; memory { + device_type = "memory"; reg = <0x90000000 0x800000>; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8d6f028ae285..c29aa9d2f6d3 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -45,12 +45,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 7937b43d7788..a3ff04940aec 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -61,6 +61,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index e3a7bd338d61..0ba9c5b08ab9 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -56,6 +56,7 @@ }; memory { + device_type = "memory"; reg = <0xC0000000 0x800000>; }; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index f48d06a80d1d..a25b7000a3a1 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -40,12 +40,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 483d896e2bc1..3c7216844a9b 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -56,6 +56,7 @@ }; memory { + device_type = "memory"; reg = <0xC0000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index cbdd69ca9e7a..299af0723790 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -40,13 +40,15 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index 45e088c55741..f8040356fe2d 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -54,6 +54,7 @@ }; memory { + device_type = "memory"; reg = <0xd0000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 3f8e0c4a998d..ef34fa2f79ea 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -54,6 +54,7 @@ }; memory { + device_type = "memory"; reg = <0xd0000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index c3ecb1e10d94..2890204680ba 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -17,6 +17,7 @@ }; memory@c0000000 { + device_type = "memory"; reg = <0xC0000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 6f4f60ba5429..269e6bf99ccb 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" / { model = "ARM Versatile AB"; @@ -21,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x0 0x08000000>; }; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index 1929ad390d88..8b5af039b072 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "via,vt8500"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index e9ef539e13d3..cca6747304c4 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8505"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index e12213d16693..00d01769a68f 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8650"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi index 46d076d7302b..54d8f7d9bb33 100644 --- a/arch/arm/boot/dts/wm8750.dtsi +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8750"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 8fbccfbe75f3..c572d777077f 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8850"; cpus { @@ -22,6 +22,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts index eedd3fcbc002..bd9400840023 100644 --- a/arch/arm/boot/dts/zx296702-ad1.dts +++ b/arch/arm/boot/dts/zx296702-ad1.dts @@ -14,6 +14,7 @@ }; memory { + device_type = "memory"; reg = <0x50000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi index 240e7a23d81f..afd98de029be 100644 --- a/arch/arm/boot/dts/zx296702.dtsi +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 -#include "skeleton.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 40a17923367118e32e5e413a952736dd83635b32 Mon Sep 17 00:00:00 2001 From: Hao Dong Date: Sun, 20 Jan 2019 23:33:27 +0100 Subject: ARM: dts: BCM5301X: Add basic DT for Phicomm K3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This router has BCM4709C0 SoC, 128 MiB NAND flash (MX30LF1G18AC-TI), 512 MiB memory and 3 x LAN and 1 x WAN ports. WiFi chips are BCM4366C0 x 2. The router has a small LCD and 3 capactive keys driven by a PIC microcontroller, which is in turn wired to UART1 of main board. Signed-off-by: Hao Dong [rmilecki: drop chosen { }, fix whitespaces, update commit message] Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm47094-phicomm-k3.dts | 71 +++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47094-phicomm-k3.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..bbc0f4527c39 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-luxul-xwr-3100.dtb \ bcm47094-luxul-xwr-3150-v1.dtb \ bcm47094-netgear-r8500.dtb \ + bcm47094-phicomm-k3.dtb \ bcm94708.dtb \ bcm94709.dtb \ bcm953012er.dtb \ diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts new file mode 100644 index 000000000000..ec09c0426d16 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Hamster Tian + * Copyright (C) 2019 Hao Dong + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; + model = "Phicomm K3"; + + memory { + reg = <0x00000000 0x08000000 + 0x88000000 0x18000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x0080000 0x0100000>; + }; + + partition@180000{ + label = "phicomm"; + reg = <0x0180000 0x0280000>; + read-only; + }; + + partition@400000 { + label = "firmware"; + reg = <0x0400000 0x7C00000>; + compatible = "brcm,trx"; + }; + }; +}; -- cgit v1.2.3 From 560ff039b521712f8cd73b544e1bfe0412a91d71 Mon Sep 17 00:00:00 2001 From: Cezary Gapinski Date: Fri, 1 Feb 2019 11:45:00 +0100 Subject: ARM: dts: stm32: add SPI support on STM32F429 SoC This patch adds all SPI instances of the STM32F429 SoC. Signed-off-by: Cezary Gapinski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8d6f028ae285..0b1b77e59c41 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -314,6 +314,26 @@ status = "disabled"; }; + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32-uart"; reg = <0x40004400 0x400>; @@ -523,6 +543,26 @@ status = "disabled"; }; + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; @@ -587,6 +627,26 @@ }; }; + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + status = "disabled"; + }; + + spi6: spi@40015400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015400 0x400>; + interrupts = <86>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; -- cgit v1.2.3 From 38576a320578392d8ba7aaf4ca723450dc2430c3 Mon Sep 17 00:00:00 2001 From: David Hernandez Sanchez Date: Fri, 1 Feb 2019 11:48:10 +0100 Subject: ARM: dts: stm32: Enable thermal sensor support on STM32MP157c-ed1 Enable STM32 Digital Thermal Sensor (dts) driver for STM32MP157c-ed1 board. Signed-off-by: David Hernandez Sanchez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index c3ecb1e10d94..98ef7a061230 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -49,6 +49,10 @@ }; }; +&dts { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; -- cgit v1.2.3 From 0040cf8dc9257049f9d4c11f1d38c82886cd391f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 28 Dec 2018 23:09:26 +0100 Subject: ARM: dts: add Raspberry Pi 3 A+ The Raspberry Pi 3 A+ is similar to the Pi 3 B+ but has only 512 MB RAM, 1 USB 2.0 port and no Ethernet. Compared to the Raspberry Pi 3 B it isn't possible to control BT_ON and WL_ON separately. Signed-off-by: Stefan Wahren Acked-by: Eric Anholt --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 175 +++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d98d51d358f7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-cm1-io1.dtb \ bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 000000000000..e9fadd338227 --- /dev/null +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model A+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory { + reg = <0 0x20000000>; + }; + + leds { + act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", + "BT_WL_ON", + "STATUS_LED_R", + "", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * This is mostly based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "", /* GPIO42 */ + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* + * SDHCI is used to control the SDIO for wireless + * + * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven + * by a single GPIO. We can't give GPIO control to one of the drivers, + * otherwise the other part would get unexpectedly disturbed. + */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + status = "okay"; + bus-width = <4>; + non-removable; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; -- cgit v1.2.3 From f090e1bd7b05f17d35b6e2d0e946d8a8085d264f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 11:51:22 +0100 Subject: ARM: dts: bcm283x: Fix DTC warning for memory node Compiling the bcm283x DTS with W=1 leads to the following warning: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Fix this by adding the unit address. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 29f970f864dc..a8b175a9e229 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -1,7 +1,7 @@ #include / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x10000000>; }; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index ac4408b34b58..871fc4a558cf 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -9,7 +9,7 @@ compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; model = "Raspberry Pi 2 Model B"; - memory { + memory@0 { reg = <0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index e9fadd338227..7f4437a8eedb 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -13,7 +13,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x20000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 42bb09044cc7..7d65013f5a4b 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -14,7 +14,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 0c155dd4f396..9abb9c55e6e4 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -14,7 +14,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 4a89a1885a3d..81399b2c5af9 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -4,7 +4,7 @@ #include "bcm2836-rpi.dtsi" / { - memory { + memory@0 { reg = <0 0x40000000>; }; -- cgit v1.2.3 From 592f50f0f97ae790650219d682f9c88e4f999267 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 12:07:16 +0100 Subject: ARM: dts: bcm2835-rpi: Drop unnecessary #address-cells/#size-cells Compiling the bcm2835-rpi.dtsi with W=1 leads to the following warning: Warning (avoid_unnecessary_addr_size): /soc/firmware: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Fix this by removing these unnecessary properties. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index a8b175a9e229..9d11cb759b5b 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -19,8 +19,6 @@ soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; - #address-cells = <0>; - #size-cells = <0>; mboxes = <&mailbox>; }; -- cgit v1.2.3 From b02d6197c28e157f5839d8ebf87e758095cc4944 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 17:28:35 +0100 Subject: ARM: dts: bcm2835: Fix labels for GPIO 0,1 According to the schematics for all RPis with a 40 pin header, the GPIOs 0 and 1 are labeled as ID_SD and ID_SC. In order to clarify that is a I2C bus, append the third letter. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 2cd9c5e4f892..db8a6017f220 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -31,8 +31,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index cfbdaacbaeba..1e40d672b055 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -33,8 +33,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 644d907bafbb..5765d3411fd6 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -40,8 +40,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "GPIO0", - "GPIO1", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 00323ba8f7de..3b35a8a4a55f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -28,8 +28,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", -- cgit v1.2.3 From 74a04e07f9d5add08920d8db0779ddd676f392a0 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 12:50:30 +0100 Subject: ARM: dts: bcm2837-rpi-3-b: Use consistent label for HDMI hotplug This make the GPIO label for HDMI hotplug more consistent to the other boards. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 9abb9c55e6e4..31b1c03e0ff7 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -39,7 +39,7 @@ "WL_ON", "STATUS_LED", "LAN_RUN", - "HPD_N", + "HDMI_HPD_N", "CAM_GPIO0", "CAM_GPIO1", "PWR_LOW_N"; -- cgit v1.2.3 From ef528c37e4c5e6c00e2f211559569002786bd6a2 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Thu, 10 Jan 2019 20:22:55 +0100 Subject: ARM: dts: bcm2837-rpi-3-b-plus: Clarify label for STATUS_LED The RPI 3 B+ provides control to both LEDs (PWR and ACT). So append the first letter of the LED color (like in the schematics) in order to clarify this. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 7d65013f5a4b..d3ec6cd86bfc 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -42,7 +42,7 @@ #gpio-cells = <2>; gpio-line-names = "BT_ON", "WL_ON", - "STATUS_LED", + "STATUS_LED_R", "LAN_RUN", "", "CAM_GPIO0", -- cgit v1.2.3 From 0b559d5c5baf2577bc23cc9e323e3dad45fef99d Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 1 Jan 2019 18:29:08 +0100 Subject: ARM: dts: bcm283x: Add missing GPIO line names The GPIO sysfs is deprecated and disabled in the defconfig files. So in order to motivate the usage of the new GPIO character device API add the missing GPIO line names for Raspberry Pi 2 and 3. In the lack of full schematics i would leave all undocumented pins as unnamed. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 66 ++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 70 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 70 ++++++++++++++++++++++++++++++ 3 files changed, 206 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 871fc4a558cf..7b4e651bafdd 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -28,6 +28,72 @@ }; &gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", + "", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETHCLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index d3ec6cd86bfc..c6fa34c24100 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -52,6 +52,76 @@ }; }; +&gpio { + /* + * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETHCLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + &hdmi { hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 31b1c03e0ff7..ce71f578c51a 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -47,6 +47,76 @@ }; }; +&gpio { + /* + * Taken from rpi_SCH_3b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "", /* GPIO 28 */ + "LAN_RUN_BOOT", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETHCLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; -- cgit v1.2.3 From ab1b4ef966af90ad79fa3c4c124e47915cddde10 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 19 Jan 2019 17:35:47 +0100 Subject: ARM: dts: bcm2835-rpi-zero-w: Drop unnecessary pinctrl There is no need to specify a pinctrl for the reset GPIO. So we better remove this avoid a potential conflict between pinctrl and pwrseq after the pinmux driver has been changed to strict: pinctrl-bcm2835 20200000.gpio: pin gpio41 already requested by wifi-pwrseq; cannot claim for pinctrl-bcm2835:499 pinctrl-bcm2835 20200000.gpio: pin-41 (pinctrl-bcm2835:499) status -22 pwrseq_simple: probe of wifi-pwrseq failed with error -22 Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 5765d3411fd6..ba0167df6c5f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -25,8 +25,6 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wl_on>; reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; }; }; @@ -98,11 +96,6 @@ "SD_DATA3_R"; pinctrl-0 = <&gpioout &alt0>; - - wl_on: wl-on { - brcm,pins = <41>; - brcm,function = ; - }; }; &hdmi { -- cgit v1.2.3 From b86e2f24414259413b193647e3634f9391747ea6 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 31 Jan 2019 10:47:07 -0200 Subject: ARM: dts: rockchip: Fix vcc5/6-supply representation on rv1108-elgin On rv1108-elgin-r1 board the RK805 VCC5 and VCC6 supplies come from the BUCK2 regulator at 2.2V, so fix the representation in the device tree. While at it, rename it from vdd_cam to vdd_buck2, which is a better name for the regulator label. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-elgin-r1.dts | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index 658057d871af..66688fdf4fd8 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -74,8 +74,8 @@ vcc2-supply = <&vcc_sys>; vcc3-supply = <&vcc_sys>; vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; + vcc5-supply = <&vdd_buck2>; + vcc6-supply = <&vdd_buck2>; regulators { vdd_core: DCDC_REG1 { @@ -90,10 +90,12 @@ }; }; - vdd_cam: DCDC_REG2 { - regulator-name= "vdd_cam"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2000000>; + vdd_buck2: DCDC_REG2 { + regulator-name= "vdd_buck2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-state-disabled; }; -- cgit v1.2.3 From fac33118110029402faa68d5ddfce21d771407c5 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 31 Jan 2019 10:47:08 -0200 Subject: ARM: dts: rockchip: Use the correct regulator properties on rv1108-elgin The following properties: - regulator-state-enabled - regulator-state-disabled - regulator-state-uv are not valid ones as per Documentation/devicetree/bindings/regulator/regulator.txt Fix it by using the correct properties as per the dt bindings. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-elgin-r1.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index 66688fdf4fd8..1c4507b66fdd 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -85,8 +85,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <900000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; }; }; @@ -97,7 +97,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -106,7 +106,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; + regulator-on-in-suspend; }; }; @@ -117,8 +117,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <3300000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; }; }; @@ -129,7 +129,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -140,7 +140,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -151,8 +151,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <1000000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; }; }; }; -- cgit v1.2.3 From 085e42fbbd34419f95c4a3a26eca59a1a39a730c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 31 Jan 2019 10:47:09 -0200 Subject: ARM: dts: rockchip: Use the correct regulator properties on rv1108-evb The following properties: - regulator-state-enabled - regulator-state-disabled - regulator-state-uv are not valid ones as per Documentation/devicetree/bindings/regulator/regulator.txt Fix it by using the correct properties as per the dt bindings. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-evb.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 203d83e3bbf5..30f3d0470ad9 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -97,8 +97,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <900000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; }; }; @@ -107,7 +107,7 @@ regulator-min-microvolt = <700000>; regulator-max-microvolt = <2000000>; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -116,7 +116,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; + regulator-on-in-suspend; }; }; @@ -127,8 +127,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <3300000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; }; }; @@ -139,7 +139,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -150,7 +150,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -161,8 +161,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <1000000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; }; }; }; -- cgit v1.2.3 From 3e3380d0675d5e20b0af067d60cb947a4348bf9b Mon Sep 17 00:00:00 2001 From: Mathieu Malaterre Date: Fri, 15 Dec 2017 13:46:39 +0100 Subject: ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation Improve the DTS files by removing all the leading "0x" and zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading "0x" and Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} + For simplicity, two sed expressions were used to solve each warnings separately. To make the regex expression more robust a few other issues were resolved, namely setting unit-address to lower case, and adding a whitespace before the opening curly brace: https://elinux.org/Device_Tree_Linux#Linux_conventions This will solve as a side effect warning: Warning (simple_bus_reg): Node /XXX@ simple-bus unit address format error, expected "" This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation") Reported-by: David Daney Suggested-by: Rob Herring Signed-off-by: Mathieu Malaterre [vzapolskiy: fixed commit message to pass checkpatch.pl test] Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index b7303a4e4236..ed0d6fb20122 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -230,7 +230,7 @@ status = "disabled"; }; - i2s1: i2s@2009C000 { + i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009C000 0x1000>; }; @@ -273,7 +273,7 @@ status = "disabled"; }; - i2c1: i2c@400A0000 { + i2c1: i2c@400a0000 { compatible = "nxp,pnx-i2c"; reg = <0x400A0000 0x100>; interrupt-parent = <&sic1>; @@ -284,7 +284,7 @@ clocks = <&clk LPC32XX_CLK_I2C1>; }; - i2c2: i2c@400A8000 { + i2c2: i2c@400a8000 { compatible = "nxp,pnx-i2c"; reg = <0x400A8000 0x100>; interrupt-parent = <&sic1>; @@ -295,7 +295,7 @@ clocks = <&clk LPC32XX_CLK_I2C2>; }; - mpwm: mpwm@400E8000 { + mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400E8000 0x78>; status = "disabled"; @@ -394,7 +394,7 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; - timer4: timer@4002C000 { + timer4: timer@4002c000 { compatible = "nxp,lpc3220-timer"; reg = <0x4002C000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; @@ -412,7 +412,7 @@ status = "disabled"; }; - watchdog: watchdog@4003C000 { + watchdog: watchdog@4003c000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; clocks = <&clk LPC32XX_CLK_WDOG>; @@ -451,7 +451,7 @@ status = "disabled"; }; - timer1: timer@4004C000 { + timer1: timer@4004c000 { compatible = "nxp,lpc3220-timer"; reg = <0x4004C000 0x1000>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; @@ -475,7 +475,7 @@ status = "disabled"; }; - pwm1: pwm@4005C000 { + pwm1: pwm@4005c000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>; clocks = <&clk LPC32XX_CLK_PWM1>; @@ -484,7 +484,7 @@ status = "disabled"; }; - pwm2: pwm@4005C004 { + pwm2: pwm@4005c004 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C004 0x4>; clocks = <&clk LPC32XX_CLK_PWM2>; -- cgit v1.2.3 From 623cdcc76d2fb50696c6d7523029b6aeebbb19b7 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 11 Oct 2018 15:31:03 +0300 Subject: ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development Board Add support for MYIR Tech MYD-LPC4357 Development Board and MY-LCD70TP-C 7" TFT LCD module with Innolux AT070TN82 panel. The board contains quite rich periferals, the list features NXP LPC4357 SoC, 32 MB SDRAM, 4 MB SPI Flash, audio input/output interface, LCD panel, micro SD card slot, USB, USB OTG, Ethernet, 2 CAN ports, 4 UARTs, I2C and SPI interfaces routed to external interface. More information can be found on http://www.myirtech.com/list.asp?id=422 Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/lpc4357-myd-lpc4357.dts | 619 ++++++++++++++++++++++++++++++ 2 files changed, 621 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/lpc4357-myd-lpc4357.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..a30a912f0282 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -313,7 +313,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ dtb-$(CONFIG_ARCH_LPC18XX) += \ lpc4337-ciaa.dtb \ lpc4350-hitex-eval.dtb \ - lpc4357-ea4357-devkit.dtb + lpc4357-ea4357-devkit.dtb \ + lpc4357-myd-lpc4357.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb diff --git a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts new file mode 100644 index 000000000000..1f84654df50c --- /dev/null +++ b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel + * + * Copyright (C) 2016-2018 Vladimir Zapolskiy + */ + +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include + +/ { + model = "MYIR Tech LPC4357 Development Board"; + compatible = "myir,myd-lpc4357", "nxp,lpc4357"; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@28000000 { + device_type = "memory"; + reg = <0x28000000 0x2000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led4 { + gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led5 { + gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led6 { + gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + panel: panel { + compatible = "innolux,at070tn92"; + + port { + panel_input: endpoint { + remote-endpoint = <&lcdc_output>; + }; + }; + }; + + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vcc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pinctrl { + can0_pins: can0-pins { + can_rd_cfg { + pins = "p3_1"; + function = "can0"; + input-enable; + }; + + can_td_cfg { + pins = "p3_2"; + function = "can0"; + }; + }; + + can1_pins: can1-pins { + can_rd_cfg { + pins = "pe_1"; + function = "can1"; + input-enable; + }; + + can_td_cfg { + pins = "pe_0"; + function = "can1"; + }; + }; + + emc_pins: emc-pins { + emc_addr0_22_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_data0_15_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3"; + function = "emc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_cs0_cfg { + pins = "p1_5"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_dqm0_1_cfg { + pins = "p6_12", "p6_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0"; + function = "emc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + }; + + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + input-enable; + input-schmitt-disable; + bias-disable; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + i2c1_pins_cfg { + pins = "pe_15", "pe_13"; + function = "i2c1"; + input-enable; + }; + }; + + lcd_pins: lcd-pins { + lcd_vd0_23_cfg { + pins = "p4_1", "p4_4", "p4_3", "p4_2", + "p8_7", "p8_6", "p8_5", "p8_4", + "p7_5", "p4_8", "p4_10", "p4_9", + "p8_3", "pb_6", "pb_5", "pb_4", + "p7_4", "p7_3", "p7_2", "p7_1", + "pb_3", "pb_2", "pb_1", "pb_0"; + function = "lcd"; + }; + + lcd_vsync_en_dclk_lp_pwr_cfg { + pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; + function = "lcd"; + }; + }; + + led_pins: led-pins { + led_1_6_cfg { + pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; + function = "gpio"; + bias-pull-down; + }; + }; + + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + input-enable; + bias-pull-down; + }; + }; + + spifi_pins: spifi-pins { + spifi_sck_cfg { + pins = "p3_3"; + function = "spifi"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + spifi_mosi_miso_sio2_sio3_cfg { + pins = "p3_7", "p3_6", "p3_5", "p3_4"; + function = "spifi"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + spifi_cs_cfg { + pins = "p3_8"; + function = "spifi"; + bias-disable; + }; + }; + + ssp1_pins: ssp1-pins { + ssp1_sck_cfg { + pins = "pf_4"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_miso_cfg { + pins = "pf_6"; + function = "ssp1"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_mosi_cfg { + pins = "pf_7"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_ssel_cfg { + pins = "pf_5"; + function = "gpio"; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rxd_cfg { + pins = "pf_11"; + function = "uart0"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + uart0_clk_dir_txd_cfg { + pins = "pf_8", "pf_9", "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; + + uart1_pins: uart1-pins { + uart1_rxd_cfg { + pins = "pc_14"; + function = "uart1"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart1_dtr_txd_cfg { + pins = "pc_12", "pc_13"; + function = "uart1"; + bias-pull-down; + }; + }; + + uart2_pins: uart2-pins { + uart2_rxd_cfg { + pins = "pa_2"; + function = "uart2"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart2_txd_cfg { + pins = "pa_1"; + function = "uart2"; + bias-pull-down; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart3_tx_cfg { + pins = "p2_3"; + function = "uart3"; + bias-pull-down; + }; + }; + + usb0_pins: usb0-pins { + usb0_pwr_enable_cfg { + pins = "p6_3"; + function = "usb0"; + }; + + usb0_pwr_fault_cfg { + pins = "p8_0"; + function = "usb0"; + bias-disable; + input-enable; + }; + }; +}; + +&adc1 { + status = "okay"; + vref-supply = <&vcc>; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; +}; + +/* Pin conflict with EMC, muxed by JP5 and JP6 */ +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + /* SST/Microchip SST39VF1601 */ + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + sensor@49 { + compatible = "lm75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + }; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + max-memory-bandwidth = <92240000>; + + port { + lcdc_output: endpoint { + remote-endpoint = <&panel_input>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; + phy-handle = <&phy1>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&mmcsd { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; + bus-width = <4>; + vmmc-supply = <&vmmc>; +}; + +/* Pin conflict with SSP0, the latter is routed to J17 pin header */ +&spifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifi_pins>; + + /* Atmel AT25DF321A */ + flash { + compatible = "jedec,spi-nor"; + spi-max-frequency = <51000000>; + spi-cpol; + spi-cpha; + }; +}; + +&ssp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_pins>; + num-cs = <1>; + cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; +}; + +/* Routed to J17 pin header */ +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +/* RS485 */ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +/* Routed to J17 pin header */ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; +}; -- cgit v1.2.3 From 3e88bc38b9f6fe4b69cecf81badd3c19fde97f97 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 26 Jan 2019 16:29:20 +0200 Subject: ARM: dts: lpc32xx: add required clocks property to keypad device node NXP LPC32xx keypad controller requires a clock property to be defined. The change fixes the driver initialization problem: lpc32xx_keys 40050000.key: failed to get clock lpc32xx_keys: probe of 40050000.key failed with error -2 Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index ed0d6fb20122..d4368eeff1b9 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -462,6 +462,7 @@ key: key@40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; + clocks = <&clk LPC32XX_CLK_KEY>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; -- cgit v1.2.3 From 489261c45f0ebbc1c2813f337bbdf858267f5033 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 26 Jan 2019 16:29:21 +0200 Subject: ARM: dts: lpc32xx: reparent keypad controller to SIC1 After switching to a new interrupt controller scheme by separating SIC1 and SIC2 from MIC interrupt controller just one SoC keypad controller was not taken into account, fix it now: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:524 irq_domain_associate+0x50/0x1b0 error: hwirq 0x36 is too large for interrupt-controller@40008000 ... lpc32xx_keys 40050000.key: failed to get platform irq lpc32xx_keys: probe of 40050000.key failed with error -22 Fixes: 9b8ad3fb81ae ("ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index d4368eeff1b9..4f8f671c3343 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -463,7 +463,8 @@ compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; clocks = <&clk LPC32XX_CLK_KEY>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; -- cgit v1.2.3 From 7a0790a4121cbcd111cc537cdc801c46ccb789ee Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:39 +0200 Subject: ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variant ARM PrimeCell PL111 LCD controller is found on On NXP LPC3230 and LPC3250 SoCs variants, the original reference in compatible property to an older one ARM PrimeCell PL110 is invalid. Fixes: e04920d9efcb3 ("ARM: LPC32xx: DTS files for device tree conversion") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 4f8f671c3343..cfd422e7f774 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -139,7 +139,7 @@ }; clcd: clcd@31040000 { - compatible = "arm,pl110", "arm,primecell"; + compatible = "arm,pl111", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_LCD>; -- cgit v1.2.3 From 30fc01bae3cda747e7d9c352b1aa51ca113c8a9d Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:40 +0200 Subject: ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks property The originally added ARM PrimeCell PL111 clocks property misses the required "clcdclk" clock, which is the same as a clock to enable the LCD controller on NXP LPC3230 and NXP LPC3250 SoCs. Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index cfd422e7f774..9ad3df11db0d 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -142,8 +142,8 @@ compatible = "arm,pl111", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_LCD>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; + clock-names = "clcdclk", "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3 From dc141b99fc36cf910a1d8d5ee30f43f2442fd1bd Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:41 +0200 Subject: ARM: dts: lpc32xx: phy3250: fix SD card regulator voltage The fixed voltage regulator on Phytec phyCORE-LPC3250 board, which supplies SD/MMC card's power, has a constant output voltage level of either 3.15V or 3.3V, the actual value depends on JP4 position, the power rail is referenced as VCC_SDIO in the board hardware manual. Fixes: d06670e96267 ("arm: dts: phy3250: add SD fixed regulator") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index 1e1c2f517a82..ffcf78631b22 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -49,8 +49,8 @@ sd_reg: regulator@2 { compatible = "regulator-fixed"; regulator-name = "sd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; gpio = <&gpio 5 5 0>; enable-active-high; }; -- cgit v1.2.3 From 55ff232497703501ace5d1bb109a90d480724fd8 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:43 +0200 Subject: ARM: dts: lpc32xx: phy3250: remove regulators umbrella device node The originally added 'regulators' device node has a number of flaws, to name a few its children has unit addresses but no reg properties, the regulators are not captured by a device driver due to a missing 'simple-bus' compatible, the regulator names are selected by killing either alphabetical order or device node grouping property. The change removes 'regulators' device node and renames the regulators and labels. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 63 +++++++++++++++++------------------ 1 file changed, 31 insertions(+), 32 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index ffcf78631b22..d2dad2b541ff 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -25,37 +25,6 @@ reg = <0x80000000 0x4000000>; }; - regulators { - backlight_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "backlight_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 4 0>; - enable-active-high; - regulator-boot-on; - }; - - lcd_reg: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "lcd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 0 0>; - enable-active-high; - regulator-boot-on; - }; - - sd_reg: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "sd_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 5 5 0>; - enable-active-high; - }; - }; - leds { compatible = "gpio-leds"; @@ -69,6 +38,36 @@ linux,default-trigger = "heartbeat"; }; }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 4 0>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 0 0>; + enable-active-high; + regulator-boot-on; + }; + + reg_sd: regulator-sd { + compatible = "regulator-fixed"; + regulator-name = "sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 5 5 0>; + enable-active-high; + regulator-boot-on; + }; }; &clcd { @@ -130,7 +129,7 @@ cd-gpios = <&gpio 3 1 0>; cd-inverted; bus-width = <4>; - vmmc-supply = <&sd_reg>; + vmmc-supply = <®_sd>; status = "okay"; }; -- cgit v1.2.3 From 3d48cda9dce15a6562de210596424f14e7a16d62 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:44 +0200 Subject: ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interface The change adds description of Sharp LQ035Q7DB03 3.5" 320x240 TFT panel, which is connected to Phytec phyCORE-LPC3250 board, ARM PrimeCell PL111 LCD controller on NXP LPC3250 SoC gets its configuration appropriately to support graphics output to the panel. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index d2dad2b541ff..aff72f14ad83 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -39,6 +39,17 @@ }; }; + panel: panel { + compatible = "sharp,lq035q7db03"; + power-supply = <®_lcd>; + + port { + panel_input: endpoint { + remote-endpoint = <&cldc_output>; + }; + }; + }; + reg_backlight: regulator-backlight { compatible = "regulator-fixed"; regulator-name = "backlight"; @@ -71,7 +82,15 @@ }; &clcd { + max-memory-bandwidth = <18710000>; status = "okay"; + + port { + cldc_output: endpoint { + remote-endpoint = <&panel_input>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; }; &i2c1 { -- cgit v1.2.3 From e5d48e7db11f717629b21291128e13c99d28eb94 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:45 +0200 Subject: ARM: dts: lpc32xx: phy3250: add unit address to memory device node The change adds a unit address to memory device node, the issue was reported as a unit_address_vs_reg warning by dtc. Root device node properties #address-cells and #size-cells were removed as inherited from lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index aff72f14ad83..ebd19258e22b 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -1,6 +1,7 @@ /* * PHYTEC phyCORE-LPC3250 board * + * Copyright (C) 2015-2019 Vladimir Zapolskiy * Copyright 2012 Roland Stigge * * The code contained herein is licensed under the GNU General Public @@ -17,10 +18,8 @@ / { model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; compatible = "phytec,phy3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; -- cgit v1.2.3 From ec54b138b170649ac33dfaaf7ade69727aef6ad1 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:46 +0200 Subject: ARM: dts: lpc32xx: ea3250: add unit address to memory device node The change adds a unit address to memory device node, the issue was reported as a unit_address_vs_reg warning by dtc. Root device node properties #address-cells and #size-cells were removed as inherited from lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-ea3250.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index 58ea0a4e7afa..ef6b3e74cd9f 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -17,10 +17,8 @@ / { model = "Embedded Artists LPC3250 board based on NXP LPC3250"; compatible = "ea,ea3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; -- cgit v1.2.3 From 0293adf76ae96cea6e1690e79d9912c690bccde3 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:47 +0200 Subject: ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodes Regarding the 'gpio_keys' device node a dtc reports a couple of warnings: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Warning (unit_address_vs_reg): /gpio_keys/button@21: node has a unit name, but no reg property The change fixes these issues and adds empty lines between adjacent children device nodes. The device node itself is renamed by substituting an underscore by hyphen to follow the standard naming convention of device tree nodes. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-ea3250.dts | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index ef6b3e74cd9f..f46a11827ef6 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -23,56 +23,64 @@ reg = <0x80000000 0x4000000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@21 { + + button { label = "Interrupt Key"; linux,code = <103>; gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; + key1 { label = "KEY1"; linux,code = <1>; gpios = <&pca9532 0 0>; }; + key2 { label = "KEY2"; linux,code = <2>; gpios = <&pca9532 1 0>; }; + key3 { label = "KEY3"; linux,code = <3>; gpios = <&pca9532 2 0>; }; + key4 { label = "KEY4"; linux,code = <4>; gpios = <&pca9532 3 0>; }; + joy0 { label = "Joystick Key 0"; linux,code = <10>; gpios = <&gpio 2 0 0>; /* P2.0 */ }; + joy1 { label = "Joystick Key 1"; linux,code = <11>; gpios = <&gpio 2 1 0>; /* P2.1 */ }; + joy2 { label = "Joystick Key 2"; linux,code = <12>; gpios = <&gpio 2 2 0>; /* P2.2 */ }; + joy3 { label = "Joystick Key 3"; linux,code = <13>; gpios = <&gpio 2 3 0>; /* P2.3 */ }; + joy4 { label = "Joystick Key 4"; linux,code = <14>; -- cgit v1.2.3 From de45b787dab563d4d62b0457e89525be945dae96 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 16 Aug 2015 08:13:25 +0200 Subject: ARM: tegra: add "jedec,spi-nor" flash compatible binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting with commit 8947e396a829 ("Documentation: dt: mtd: replace "nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor" binding indicating support for JEDEC identification. Use it for all flashes that are supposed to support READ ID op according to the datasheets. Signed-off-by: Rafał Miłecki Acked-by: Brian Norris Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 1788556b4977..97a5c3504bbe 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1087,7 +1087,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 9151b3ebb839..33bbb1c5285d 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1656,7 +1656,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index d5f11d6d987e..4dd4d13aa8f5 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -355,7 +355,7 @@ spi-max-frequency = <25000000>; flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 82d139648ef1..4882b61fb680 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -879,7 +879,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9eb26dc15f6b..3e5ac096d85e 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -287,7 +287,7 @@ status = "okay"; spi-max-frequency = <48000000>; spi-flash@0 { - compatible = "winbond,w25q80bl"; + compatible = "winbond,w25q80bl", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <48000000>; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index b0d40ac8ac6e..a3b0f3555cd2 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1886,7 +1886,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@1 { - compatible = "winbond,w25q32"; + compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index fb9222b479d2..7ce61edd52f5 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -360,7 +360,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@1 { - compatible = "winbond,w25q32"; + compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; }; -- cgit v1.2.3 From 97131f85c08e024df49480ed499aae8fb754067f Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 24 Jan 2019 14:00:47 +0100 Subject: ARM: dts: qcom: ipq4019: Fix MSI IRQ type The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level triggered interrupt. The msi_ctrl_int will be high for as long as any MSI status bit is set, thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the IRQ handler to keep getting called, as long as any MSI status bit is set. A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has configured this IRQ incorrectly. Not having the correct IRQ type defined will cause us to lose interrupts, which in turn causes timeouts in the PCIe endpoint drivers. Signed-off-by: Niklas Cassel Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 19635f91e2c4..48b3cb474ba0 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -398,7 +398,7 @@ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 0x82000000 0 0x40300000 0x40300000 0 0x400000>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; -- cgit v1.2.3 From 705f95153bd466f8be71b5edc69b21331cf01db5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:32 +0800 Subject: ARM: dts: sun9i: a80-optimus: Add node for AXP809's unused dc1sw regulator The DC1SW output from the AXP809 is unused. Unused regulators should still be listed so as to be considered to be fully constrained. Fixes: aa4a27bc819e ("ARM: dts: sun9i: a80-optimus: Add AXP809 PMIC device node and regulators") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 58a199b0e494..1ee2792b3a27 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -213,6 +213,10 @@ regulator-name = "vdd-cpus-09-usbh"; }; + dc1sw { + /* unused */ + }; + reg_dcdc1: dcdc1 { regulator-always-on; regulator-min-microvolt = <3000000>; -- cgit v1.2.3 From 507b1784b4079d37f506eff94d93ac1788e0fc50 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:33 +0800 Subject: ARM: dts: sun9i: a80-optimus: Add GPIO pin-bank regulator supplies The A80 Optimus has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs. All pin-banks that have supply rails are accounted for. PN pin-bank does not have a supply rail. Also remove any "regulator-always-on" properties from regulators that were only marked to provide pin-bank power. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 1ee2792b3a27..9c25176e69dc 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -172,10 +172,26 @@ clocks = <&ac100_rtc 0>; }; +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_ir { status = "okay"; }; +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + &r_rsb { status = "okay"; @@ -264,7 +280,6 @@ }; reg_dldo2: dldo2 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pl"; @@ -283,14 +298,12 @@ }; reg_eldo3: eldo3 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pm-codec-io1"; }; reg_ldo_io0: ldo_io0 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pg"; -- cgit v1.2.3 From b3e1f4be1e4b3f762ba589abb5da1fc4b6faa98f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:34 +0800 Subject: ARM: dts: sun9i: cubieboard4: Add GPIO pin-bank regulator supplies The Cubieboard 4 has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs. All pin-banks that have supply rails are accounted for. PN pin-bank does not have a supply rail. Also remove any "regulator-always-on" properties from regulators that were only marked to provide pin-bank power. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 85da85faf869..0daab9b374e6 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -183,10 +183,26 @@ clocks = <&ac100_rtc 0>; }; +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dc1sw>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_ir { status = "okay"; }; +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + &r_rsb { status = "okay"; @@ -217,6 +233,10 @@ /* unused */ }; + reg_dc1sw: dc1sw { + regulator-name = "vcc-pd"; + }; + reg_dc5ldo: dc5ldo { regulator-always-on; regulator-min-microvolt = <800000>; @@ -271,7 +291,6 @@ }; reg_dldo2: dldo2 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pl"; @@ -290,14 +309,12 @@ }; reg_eldo3: eldo3 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pm-codec-io1"; }; reg_ldo_io0: ldo_io0 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pg"; -- cgit v1.2.3 From e78adcfe48daf7b322c09aa19930b8051adf04c8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:35 +0800 Subject: ARM: dts: sun9i: Add GMAC clock node The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The accompanying GMAC clock register has been moved into the "System Control" area. Add a clock node for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index d9532fb1ef65..724ca3b850c8 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -183,6 +183,37 @@ clock-output-names = "osc32k"; }; + /* + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. + */ + mii_phy_tx_clk: mii_phy_tx_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: gmac_int_tx_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@800030 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x00800030 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + cpus_clk: clk@8001410 { compatible = "allwinner,sun9i-a80-cpus-clk"; reg = <0x08001410 0x4>; -- cgit v1.2.3 From 6fa39a5405db9a2e8621b49fd2d46fd585225853 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:36 +0800 Subject: ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller node The A80 has the same GMAC found on the A31 SoC. Add a device node, and an alias for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 724ca3b850c8..f0c7acf2d0a4 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -56,6 +56,10 @@ #size-cells = <2>; interrupt-parent = <&gic>; + aliases { + ethernet0 = &gmac; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -314,6 +318,23 @@ }; }; + gmac: ethernet@830000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x00830000 0x1054>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + resets = <&ccu RST_BUS_GMAC>; + reset-names = "stmmaceth"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ehci0: usb@a00000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a00000 0x100>; -- cgit v1.2.3 From 72acaa1343ea2c5c401649e39c21ed83192f8cf3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:37 +0800 Subject: ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting The GMAC (gigabit ethernet controller) supports RGMII to connect to the ethernet PHY, for gigabit network speeds. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f0c7acf2d0a4..6fb292e0b662 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -1000,6 +1000,19 @@ #size-cells = <0>; #gpio-cells = <3>; + gmac_rgmii_pins: gmac-rgmii-pins { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA7", "PA8", + "PA9", "PA10", "PA12", "PA13", + "PA15", "PA16", "PA17"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + i2c3_pins: i2c3-pins { pins = "PG10", "PG11"; function = "i2c3"; -- cgit v1.2.3 From bc9bd03a44f900ae30a1d0f425a2fd092444e335 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:38 +0800 Subject: ARM: dts: sun9i: a80-optimus: Enable GMAC The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's core logic and gpio1-ldo for I/O. The latter also powers the SoC side pins. As there is no binding to model a second regulator supply for the PHY, it is omitted. It is however properly modeled for the PIO. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 9c25176e69dc..864715ec3cb0 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -120,6 +120,19 @@ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_cldo1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -391,6 +404,14 @@ */ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; regulator-name = "vcc-gmac-phy"; }; -- cgit v1.2.3 From 98048143b7f83ee3fc70f4522ff9b8fa11f8b0a5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:39 +0800 Subject: ARM: dts: sun9i: cubieboard4: Enable GMAC The Cubieboard4 has a Realtek RTL8211E ethernet PHY which uses RGMII to talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's core logic and gpio1-ldo for I/O. The latter also powers the SoC side pins. As there is no binding to model a second regulator supply for the PHY, it is omitted. It is however properly modeled for the PIO. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 0daab9b374e6..28c034928d67 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -133,6 +133,19 @@ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_cldo1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; @@ -402,6 +415,14 @@ */ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; regulator-name = "vcc-gmac-phy"; }; -- cgit v1.2.3 From 185401e1dd1656f8a1dff42bb2e4863493fd51f0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 Feb 2019 23:00:39 +0800 Subject: ARM: dts: sun8i: a83t: Enable PMIC power supplies on various boards On the Bananapi M3 and Cubietruck Plus, the DC input jacks are wired to the ACIN pins, which is represented by the AC power supply. Both boards have connectors for LiPo batteries, which are represented by the battery power supply. The H8 Homlet is a set-top box design. The DC input jack is wired to the ACIN pins, but there are no battery connectors. Enable these power supplies in the device tree. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 4 ++++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 8 ++++++++ 3 files changed, 20 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 1c012a4def16..9c006fc18821 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -154,6 +154,10 @@ #include "axp81x.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 7d30d3e530fb..838be7b3715f 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -237,6 +237,14 @@ #include "axp81x.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index a5a9f5a0603e..fcbec3d7ccd7 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -247,6 +247,14 @@ #include "axp81x.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; -- cgit v1.2.3 From dd80f10320c6d4d57c632ee1f3f9c40d3bad9855 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 29 Jan 2019 15:45:18 +0100 Subject: ARM: dts: omap3-gta04a5: Replace LXR reference with a local one MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need to use an external link when the file is already here. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04a5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index bd232b1b24cb..223b47ac596e 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -82,7 +82,7 @@ /* * for WL183x module see - * http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt + * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt */ &wifi_pwrseq { -- cgit v1.2.3 From a3f9c8c78abd283d840d4b22d6e19059ae953d7a Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 31 Jan 2019 07:23:38 +0100 Subject: ARM: dts: gta04: add pinctrl settings for wkup domain There is one button and a notifier for incoming phone calls/text messages for which we should wakeup from suspend. Signed-off-by: Andreas Kemnade Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index e53d32691308..2dfa85e2f608 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -224,6 +224,15 @@ }; }; +&omap3_pmx_wkup { + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ + OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ + >; + }; +}; + &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < @@ -636,6 +645,11 @@ status = "disabled"; }; +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; -- cgit v1.2.3 From 0db02b3bee2a8aa4a2dddff02cbbc578c53e5d2f Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 31 Jan 2019 19:06:39 +0100 Subject: ARM: dts: gta04: add ldo 3v3 regulator Required for completeness sake to be able to specify a regulator for devices having a non-optional regulator property. It corresponds to the "3V3" net in the schematics. Signed-off-by: Andreas Kemnade Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 2dfa85e2f608..666dd0288b69 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -32,6 +32,14 @@ display1 = &tv0; }; + ldo_3v3: fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "ldo_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + /* fixed 26MHz oscillator */ hfclk_26m: oscillator { #clock-cells = <0>; -- cgit v1.2.3 From 1f4f84e955342ebba3295f100693073a412c8f46 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 31 Jan 2019 19:06:40 +0100 Subject: ARM: dts: gta04: add gps support The GTA04 has a w2sg0004 or w2sg0084 gps chip. Not detectable which one is mounted so use the compatibility entry for w2sg0004 for all which will work for both. Signed-off-by: Andreas Kemnade Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 666dd0288b69..843d8795118d 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -329,6 +329,12 @@ >; }; + gps_pins: pinmux_gps_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ + >; + }; + hdq_pins: hdq_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ @@ -666,6 +672,14 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; + gnss: gnss { + compatible = "wi2wi,w2sg0004"; + pinctrl-names = "default"; + pinctrl-0 = <&gps_pins>; + sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + lna-supply = <&vsim>; + vcc-supply = <&ldo_3v3>; + }; }; &uart3 { -- cgit v1.2.3 From 5f152018d340d90c185ced8ef6230b7044ea5540 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 22 Jan 2019 15:25:48 +0000 Subject: ARM: dts: r8a7744: Add DU support Add du node to r8a7744 SoC DT. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 8d25a0a0594a..83804aa042c6 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1645,8 +1645,14 @@ }; du: display@feb00000 { - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; + compatible = "renesas,du-r8a7744"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; ports { #address-cells = <1>; @@ -1663,7 +1669,6 @@ }; }; }; - /* placeholder */ }; prr: chipid@ff000044 { -- cgit v1.2.3 From 1feef0ac19a8376d36909af677b531b21bc92bb7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 22 Jan 2019 15:25:49 +0000 Subject: ARM: dts: r8a7744: Add LVDS support Add LVDS encoder node to r8a7744 SoC DT. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 83804aa042c6..fa74a262107b 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1666,6 +1666,33 @@ port@1 { reg = <1>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7744-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; -- cgit v1.2.3 From cb92e40411ef8a773675b522d29b6ea82e5fb8e0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 6 Feb 2019 19:05:26 +0100 Subject: arch: arm: dts: Remove disabled marvell,dsa properties These have been disable since the change to probe Marvell Ethernet switches as MDIO devices. Remove the properties now that the code to suppport them will also be removed soon. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-rd.dts | 42 ------------------- arch/arm/boot/dts/armada-388-clearfog.dts | 58 -------------------------- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 47 --------------------- arch/arm/boot/dts/kirkwood-dir665.dts | 47 --------------------- arch/arm/boot/dts/kirkwood-linksys-viper.dts | 47 --------------------- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 47 --------------------- arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 41 ------------------ 7 files changed, 329 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 2bfb3108b5b2..c910d157a686 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -114,48 +114,6 @@ }; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &pciec { diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 89a354b43978..20f8d4667753 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -30,64 +30,6 @@ }; }; - dsa@0 { - status = "disabled"; - - compatible = "marvell,dsa"; - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; - pinctrl-names = "default"; - #address-cells = <2>; - #size-cells = <0>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4 0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&rear_button_pins>; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 7a2606c3b62e..8480a16919a0 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -210,53 +210,6 @@ compatible = "pwm-fan"; pwms = <&gpio0 24 4000>; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &pciec { diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index 31ceacd841de..b3ad3f607d31 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -190,53 +190,6 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - }; - }; - }; }; &mdio { diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts index a7d659b7145a..2f9660f3b457 100644 --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts @@ -66,53 +66,6 @@ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@16,0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <16 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "ethernet1"; - }; - - port@1 { - reg = <1>; - label = "ethernet2"; - }; - - port@2 { - reg = <2>; - label = "ethernet3"; - }; - - port@3 { - reg = <3>; - label = "ethernet4"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &pinctrl { diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 86d532916d56..2e1a75348908 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -107,53 +107,6 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <1>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &mdio { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index 0f22f0e6f56b..f1f8eee132e8 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -48,47 +48,6 @@ cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; /* No WP GPIO */ }; - }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; }; }; -- cgit v1.2.3 From ae88c9e783fa1a4dbfc00b81a770d954ed904730 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 7 Jan 2019 13:28:48 +0000 Subject: ARM: dts: imx6sx: Add DISPLAY power domain support This was implemented in the driver but not actually defined and referenced in dts. This makes it always on. From reference manual in section "10.4.1.4.1 Power Distribution": "Display domain - The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe, DCIC, and LDB. It is supplied by internal regulator." The current pd_pcie is actually only for PCIE_PHY, the PCIE ip block is actually inside the DISPLAY domain. Handle this by adding the pcie node in both power domains. Signed-off-by: Leonard Crestez Acked-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 272ff6133ec1..ecf3f3e5c0a0 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -785,6 +785,18 @@ clocks = <&clks IMX6SX_CLK_GPU>; }; + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + }; + pd_pci: power-domain@3 { reg = <3>; #power-domain-cells = <0>; @@ -1205,6 +1217,7 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_PXP_AXI>; clock-names = "axi"; + power-domains = <&pd_disp>; status = "disabled"; }; @@ -1226,6 +1239,7 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; @@ -1237,6 +1251,7 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; @@ -1246,6 +1261,7 @@ clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; + power-domains = <&pd_disp>; status = "disabled"; }; }; @@ -1370,7 +1386,8 @@ <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; - power-domains = <&pd_pci>; + power-domains = <&pd_disp>, <&pd_pci>; + power-domain-names = "pcie", "pcie_phy"; status = "disabled"; }; }; -- cgit v1.2.3 From f243bc821ee372ab499302c5ceacfd8dff8c438f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 11 Dec 2018 14:51:13 +0100 Subject: ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatible Since imx6ulz.dtsi includes imx6ull.dtsi, we only need to fix the compatible string here to achieve the correct OTP size for both SoCs. Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index f3668fe69eac..9cd1a48dc2ef 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -30,6 +30,10 @@ >; }; +&ocotp { + compatible = "fsl,imx6ull-ocotp", "syscon"; +}; + / { soc { aips3: aips-bus@2200000 { -- cgit v1.2.3 From 143c3870ffd2d93204f7cb5d2784041bcaa4cbb2 Mon Sep 17 00:00:00 2001 From: BOUGH CHEN Date: Fri, 28 Dec 2018 03:26:16 +0000 Subject: ARM: dts: imx6ull: change to use new compatible "fsl,imx6ull-usdhc" for usdhc i.MX6ULL has errata ERR010450, there is I/O timing limitation, for SDR mode, SD card clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. This patch change to use the new compatible "fsl,imx6ull-usdhc" to follow this limitation. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 9cd1a48dc2ef..22e4a307fa59 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -34,6 +34,14 @@ compatible = "fsl,imx6ull-ocotp", "syscon"; }; +&usdhc1 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + / { soc { aips3: aips-bus@2200000 { -- cgit v1.2.3 From cc077d00fd39cc27f3d7e1927f55c4e3cc64fd69 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 11 Jan 2019 06:22:55 +0000 Subject: ARM: dts: imx7ulp: add sim node i.MX7ULP SoC revision info is inside the SIM mode's JTAG_ID register, add sim node to support SoC revision check. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index b86daf73bb89..fca6e50f37c8 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -347,4 +347,17 @@ gpio-ranges = <&iomuxc1 0 96 32>; }; }; + + m4aips1: bus@41080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x41080000 0x80000>; + ranges; + + sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; + }; }; -- cgit v1.2.3 From 87489ec3a77f3e01bcf0d46e353ae7112ec8c4f0 Mon Sep 17 00:00:00 2001 From: Vokáč Michal Date: Tue, 15 Jan 2019 14:22:45 +0000 Subject: ARM: dts: imx: Add Y Soft IOTA Draco, Hydra and Ursa boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are i.MX6S/DL based SBCs embedded in various Y Soft products. All share the same board design but have slightly different HW configuration. Ursa - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 1x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) Draco - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 2x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) Hydra - i.MX6DL SoC, 2GB RAM DDR3, 4GB eMMC, microSD - I2C OLED display, capacitive matrix keys - 2x Eth (QCA8334 switch) - USB OTG - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) - HDMI - miniPCIe slot Cc: Andrew Lunn Signed-off-by: Michal Vokáč Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 595 +++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6dl-yapp4-draco.dts | 58 +++ arch/arm/boot/dts/imx6dl-yapp4-hydra.dts | 50 +++ arch/arm/boot/dts/imx6dl-yapp4-ursa.dts | 54 +++ 5 files changed, 760 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-common.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-draco.dts create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-hydra.dts create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-ursa.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..c0a9b89b7670 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -445,6 +445,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ imx6dl-wandboard-revd1.dtb \ + imx6dl-yapp4-draco.dtb \ + imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-ursa.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi new file mode 100644 index 000000000000..b715ab0fa1ff --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +#include +#include +#include + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 32 64 128 255>; + default-brightness-level = <32>; + num-interpolated-steps = <8>; + power-supply = <&sw2_reg>; + status = "disabled"; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + compatible = "dataimage,scf0700c48ggu18"; + power-supply = <&sw2_reg>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "okay"; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-reset-duration = <20>; + phy-supply = <&sw2_reg>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + switch@0 { + compatible = "qca,qca8334"; + reg = <0>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "rgmii"; + ethernet = <&fec>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@2 { + reg = <2>; + label = "eth2"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "eth1"; + phy-handle = <&phy_port3>; + }; + }; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c2>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze200"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vsnvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + leds: led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + clock-mode = /bits/ 8 <1>; + status = "disabled"; + + chan0 { + chan-name = "R"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan1 { + chan-name = "G"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan2 { + chan-name = "B"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan3 { + chan-name = "W"; + led-cur = /bits/ 8 <0x0>; + max-cur = /bits/ 8 <0x0>; + }; + }; + + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + pagesize = <64>; + status = "okay"; + }; + + touchscreen: touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + status = "disabled"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + oled: oled@3d { + compatible = "solomon,ssd1305fb-i2c"; + reg = <0x3d>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_oled: gpio@41 { + compatible = "nxp,pca9536"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x41>; + vcc-supply = <&sw2_reg>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "disabled"; +}; + +&pwm1 { + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <109>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&sw2_reg>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts new file mode 100644 index 000000000000..a38c407fd837 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Draco i.MX6Solo board"; + compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchscreen { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts new file mode 100644 index 000000000000..f97927064750 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Hydra i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +®_pcie { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts new file mode 100644 index 000000000000..0d594e4bd559 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Ursa i.MX6Solo board"; + compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&switch_ports { + /delete-node/ port@2; +}; + +&touchscreen { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; -- cgit v1.2.3 From 69ab17b53e35779122c7e7e198aa2868a993f855 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Jan 2019 16:55:53 -0200 Subject: ARM: dts: vf610-zii-ssmb-spu3: Pass "no-sdio"/"no-sd" properties esdhc0 is connected to an eMMC, so it is safe to pass the "no-sdio"/"no-sd" properties. esdhc1 is wired to a standard SD socket, so pass the "no-sdio" property. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 757af56e8ee7..0d9fe5ac83a3 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -99,6 +99,8 @@ non-removable; no-1-8-v; keep-power-in-suspend; + no-sdio; + no-sd; status = "okay"; }; @@ -106,6 +108,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; bus-width = <4>; + no-sdio; status = "okay"; }; -- cgit v1.2.3 From d2b91ab1480618885fe0a7f240b7e7710344a066 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 18 Jan 2019 14:31:13 +0100 Subject: ARM: dts: imx6*-apalis/-colibri: mark I2C recovery GPIOs as open drain Since commit d2d0ad2aec4a ("i2c: imx: use open drain for recovery GPIO") GPIO lib expects this GPIO to be configured as open drain. Make sure we define this GPIO as open drain in the device tree. This gets rid of the following warning: gpio-81 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Note that currently the i.MX pinctrl driver does not support enabling open drain directly, so this patch has no effect in practice. Open drain is enabled by the fixed pinmux entry. Signed-off-by: Stefan Agner Reviewed-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 4 ++-- arch/arm/boot/dts/imx6ull-colibri.dtsi | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 8380f1b26826..5e6cec92e090 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -369,8 +369,8 @@ pinctrl-names = "default", "recovery"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 87e15e7cb32b..8a27c2a05678 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -298,8 +298,8 @@ pinctrl-names = "default", "recovery"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 6c63a7384611..9ad1da159768 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -94,16 +94,16 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c2 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; ad7879@2c { -- cgit v1.2.3 From 82ae9038ddccbda9a9d7dc06a2a5c65e9a34f281 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 21 Jan 2019 09:57:05 +0000 Subject: ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi | 148 +++++++++ arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi | 55 ++++ .../boot/dts/imx6ul-phytec-phyboard-segin-full.dts | 89 ++++++ .../arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi | 329 +++++++++++++++++++++ 5 files changed, 622 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts create mode 100644 arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c0a9b89b7670..ac1eeb9afdb7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -564,6 +564,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-opos6uldev.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb \ + imx6ul-phytec-phyboard-segin-full.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi b/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi new file mode 100644 index 000000000000..fc2997449b49 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +#include +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "Phytec phyCORE i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + gpio_leds_som: leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds_som>; + compatible = "gpio-leds"; + + led_green { + label = "phycore:green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + eeprom@52 { + compatible = "catalyst,24c32", "atmel,24c32"; + reg = <0x52>; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 + >; + }; + + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = ; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi new file mode 100644 index 000000000000..e2f38f39a6ad --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + user_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + led_yellow { + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led_red { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts new file mode 100644 index 000000000000..b6a1407a9d44 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6ul-phytec-pcl063.dtsi" +#include "imx6ul-phytec-phyboard-segin.dtsi" +#include "imx6ul-phytec-peb-eval-01.dtsi" + +/ { + model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured"; + compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi new file mode 100644 index 000000000000..7bf439a77d2c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/ { + model = "Phytec phyBOARD-Segin i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "disabled"; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + + reg_can1_en: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&princtrl_flexcan1_en>; + regulator-name = "Can"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&tlv320>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; + +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_adc1_vref_3v3>; + /* + * driver can not separate a specific channel so we request 4 channels + * here - we need only the fourth channel + */ + num-channels = <4>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_en>; + status = "disabled"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "disabled"; +}; + +&i2c1 { + tlv320: codec@18 { + compatible = "ti,tlv320aic3007"; + #sound-dai-cells = <0>; + reg = <0x18>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + status = "disabled"; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x = <1>; + touchscreen-inverted-y = <1>; + }; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; +}; + +&mdio { + ethphy1: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <19200000>; + fsl,sai-mclk-direction-output; + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "disabled"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "disabled"; +}; + +&iomuxc { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1 { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + princtrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; -- cgit v1.2.3 From 063182a4c85673c735508dc01dd07fffbe7defb1 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 21 Jan 2019 16:53:27 +0100 Subject: ARM: dts: colibri: use valid range configuration for weim A valid WEIM range configuration must specify range entries for all four chip selects. This fixes an error on boot: imx-weim: probe of 21b8000.weim failed with error -22 Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index d5f7a1703aae..9a5d6c94cca4 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -228,10 +228,11 @@ &weim { status = "okay"; - /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */ + /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ ranges = <0 0 0x08000000 0x02000000 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000>; + 2 0 0x0c000000 0x02000000 + 3 0 0x0e000000 0x02000000>; /* SRAM on Colibri nEXT_CS0 */ sram@0,0 { -- cgit v1.2.3 From da8782f673a1986bc8691461d3e6ccea988257da Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:44 +0530 Subject: ARM: dts: Add devicetree compatibles for LS1021A based boards Add missing devicetree compatibles for the following LS1021A based boards: ls1021a-moxa-uc-8410a.dts ls1021a-qds.dts ls1021a-twr.dts Signed-off-by: Manivannan Sadhasivam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 + arch/arm/boot/dts/ls1021a-qds.dts | 1 + arch/arm/boot/dts/ls1021a-twr.dts | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index 6a83f30029ea..ba1ddd93b8f8 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -18,6 +18,7 @@ / { model = "Moxa UC-8410A"; + compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; aliases { enet0_rgmii_phy = &rgmii_phy0; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 923a25760516..ca60730dda40 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -51,6 +51,7 @@ / { model = "LS1021A QDS Board"; + compatible = "fsl,ls1021a-qds", "fsl,ls1021a"; aliases { enet0_rgmii_phy = &rgmii_phy1; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 8b48c3c7cd21..97e1fb7ea932 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -51,6 +51,7 @@ / { model = "LS1021A TWR Board"; + compatible = "fsl,ls1021a-twr", "fsl,ls1021a"; aliases { enet2_rgmii_phy = &rgmii_phy1; -- cgit v1.2.3 From a822029a0cc0b838bff043482629f5fb9c2deb32 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 22 Jan 2019 14:21:34 +0100 Subject: ARM: dts: Add stmpe-adc DT node to Toradex iMX6 modules Add the stmpe-adc DT node as found on Toradex iMX6 modules Signed-off-by: Philippe Schenker Reviewed-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 22 ++++++++++++++-------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 22 ++++++++++++++-------- 2 files changed, 28 insertions(+), 16 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 5e6cec92e090..7c4ad541c3f5 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -332,11 +332,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -346,17 +352,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 8a27c2a05678..1beac22266ed 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -262,11 +262,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -276,17 +282,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; }; -- cgit v1.2.3 From 29f0023d01f063feacfc404f0446905aee4f82ee Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 29 Dec 2018 15:35:56 +0100 Subject: ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the Odroid-C1+ schematics the Ethernet TXD1 signal is routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and TXD1 can be routed to DIF_2_N instead. The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured as TXD0 and TXD1 data lines as well. This results in a bad Ethernet receive performance. Presumably this is due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. As a result of that data can only be transmitted on eth_txd2 and eth_txd3. However, I have no scope to fully confirm this assumption. The vendor u-boot sources for Odroid-C1 use the following Ethernet pinmux configuration: SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); This translates to the following pin groups in the mainline kernel: - register 6 bit 0: eth_rxd1 (DIF_0_P) - register 6 bit 1: eth_rxd0 (DIF_0_N) - register 6 bit 2: eth_rx_dv (DIF_1_P) - register 6 bit 3: eth_rx_clk (DIF_1_N) - register 6 bit 6: eth_tx_en (DIF_3_P) - register 6 bit 8: eth_ref_clk (DIF_3_N) - register 6 bit 9: eth_mdc (DIF_4_P) - register 6 bit 10: eth_mdio_en (DIF_4_N) - register 6 bit 11: eth_tx_clk (GPIOH_9) - register 6 bit 12: eth_txd2 (GPIOH_8) - register 6 bit 13: eth_txd3 (GPIOH_7) - register 7 bit 20: eth_txd0_0 (GPIOH_6) - register 7 bit 21: eth_txd1_0 (GPIOH_5) - register 7 bit 22: eth_rxd3 (DIF_2_P) - register 7 bit 23: eth_rxd2 (DIF_2_N) Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and eth_rxd3 groups so we don't rely on the bootloader to set them up. iperf3 statistics before this change: - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) iperf3 statistics after this change: - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) - receiving on Odroid-C1: 750 Mbits/sec (0 retries) Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") Signed-off-by: Martin Blumenstingl Cc: Emiliano Ingrassia Cc: Linus Lüssing Tested-by: Emiliano Ingrassia Reviewed-by: Emiliano Ingrassia Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index dd498e681939..9fca77478fec 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -324,9 +324,7 @@ groups = "eth_tx_clk", "eth_tx_en", "eth_txd1_0", - "eth_txd1_1", "eth_txd0_0", - "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", "eth_rxd1", @@ -335,7 +333,9 @@ "eth_mdc", "eth_ref_clk", "eth_txd2", - "eth_txd3"; + "eth_txd3", + "eth_rxd3", + "eth_rxd2"; function = "ethernet"; bias-disable; }; -- cgit v1.2.3 From b6db3936f2833c9f27aa9d868bb7bb6e87401b40 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:21 +0100 Subject: ARM: dts: meson: switch the clock controller to the HHI register area The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 15 ++++++++------- arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++------- 3 files changed, 23 insertions(+), 14 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e4645f612712..536d6314d97e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -72,6 +72,13 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hhi: system-controller@4000 { + compatible = "amlogic,meson-hhi-sysctrl", + "simple-mfd", + "syscon"; + reg = <0x4000 0x400>; + }; + assist: assist@7c00 { compatible = "amlogic,meson-mx-assist", "syscon"; reg = <0x7c00 0x200>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1ea5a36c5040..66b167537aaa 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -327,13 +327,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -468,6 +461,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9fca77478fec..9faf70a6ed9a 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -276,13 +276,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8b-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -437,6 +430,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; -- cgit v1.2.3 From c0ad99a2deacc7eab5f9bd9dd176bd4cbeea91e2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:22 +0100 Subject: ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible The SAR ADC on Meson8m2 is slightly different compared to Meson8. The ADC functionality is identical but the calibration of the internal thermal sensor is different. Use the Meson8m2 specific compatible so the temperature sensor is calibrated correctly on boards using the Meson8m2 SoC. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8m2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index d1a28c2adac5..bb87b251e16d 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -50,6 +50,10 @@ }; }; +&saradc { + compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; -- cgit v1.2.3 From f4c6e8e223c2c77cd3bdde4c9da280fb2338aa5b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:23 +0100 Subject: ARM: dts: meson8: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 66b167537aaa..a9781243453e 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -449,6 +449,11 @@ compatible = "amlogic,meson8-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -536,6 +541,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { -- cgit v1.2.3 From bbbcf64360bb32c8eab46020b78a0c0e0de4c40c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:24 +0100 Subject: ARM: dts: meson8b: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9faf70a6ed9a..fe84a8c3ce81 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -407,6 +407,11 @@ compatible = "amlogic,meson8b-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -505,6 +510,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { -- cgit v1.2.3 From 1a4f28ab2556deacd34b925bf419432a59670af6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:25 +0100 Subject: ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0872f6e3abf5..0cebe849a920 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -64,6 +64,11 @@ timeout-ms = <20000>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + leds { compatible = "gpio-leds"; -- cgit v1.2.3 From a6c94928261a307002c4f8f3c0875c4a655a3a50 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:26 +0100 Subject: ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 58669abda259..9251dc102fcc 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -118,6 +118,11 @@ 1800000 1>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_1v8: regulator-vcc-1v8 { /* * RICHTEK RT9179 configured for a fixed output voltage of -- cgit v1.2.3 From e7e871b50f80145d37d13e8fbdc73a7dd52c4d88 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:27 +0100 Subject: ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index f5853610b20b..d1d3c828c039 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -44,6 +44,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_3v3: regulator-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "VCC3V3"; -- cgit v1.2.3 From b7d10841e5d7003bb8bc57c122494b4fb47836c0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:37 +0100 Subject: ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad on the SoC. Enable the interrupt function of the PHY's INTR32 pin to switch it from it's default "receive error" mode to "interrupt pin" mode. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0cebe849a920..74b726fc0d30 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -169,6 +169,10 @@ eth_phy0: ethernet-phy@0 { /* IC Plus IP101A/G (0x02430c54) */ reg = <0>; + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; }; -- cgit v1.2.3 From 3e7db1c1b7a32dfbf1f9fc33d444c83e64dd3513 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:38 +0100 Subject: ARM: dts: meson8b: ec100: improve the description of the regulators USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN. VCC5V is supplied by the main power input called PWR_5V_STB. The name of it's enable GPIO signal is 3V3_5V_EN. VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the voltage of VCCK can be changed by changing it's feedback voltage via PWM_C. VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is supplied by VCC3V3. VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It is supplied by either VCC3V3 (when the board is powered) or the RTC coin cell battery. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 68 +++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 74b726fc0d30..34cd72911d63 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -88,6 +88,9 @@ }; usb_vbus: regulator-usb-vbus { + /* + * Silergy SY6288CCAC-GP 2A Power Distribution Switch. + */ compatible = "regulator-fixed"; regulator-name = "USB_VBUS"; @@ -95,11 +98,20 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* + * signal name from the schematics: USB_PWR_EN + */ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; enable-active-high; }; vcc_5v: regulator-vcc5v { + /* + * supplied by the main power input which called PWR_5V_STB + * in the schematics + */ compatible = "regulator-fixed"; regulator-name = "VCC5V"; @@ -107,6 +119,9 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + /* + * signal name from the schematics: 3V3_5V_EN + */ gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; regulator-boot-on; @@ -114,12 +129,18 @@ }; vcck: regulator-vcck { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. + */ compatible = "pwm-regulator"; regulator-name = "VCCK"; regulator-min-microvolt = <860000>; regulator-max-microvolt = <1140000>; + vin-supply = <&vcc_5v>; + pwms = <&pwm_cd 0 1148 0>; pwm-dutycycle-range = <100 0>; @@ -128,19 +149,66 @@ }; vcc_1v8: regulator-vcc1v8 { + /* + * ABLIC S-1339D18-M5001-GP + */ compatible = "regulator-fixed"; regulator-name = "VCC1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + vin-supply = <&vcc_3v3>; }; vcc_3v3: regulator-vcc3v3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * VDDIO_AO3.3V in the schematics. + */ compatible = "regulator-fixed"; regulator-name = "VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v>; + }; + + vcc_ddr3: regulator-vcc-ddr3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * DDR3_1.5V in the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_DDR3_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&vcc_5v>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_rtc: regulator-vcc-rtc { + /* + * Global Mixed-mode Technology Inc. G918T12U-GP + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_RTC"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + /* + * When the board is powered then the input is VCC3V3, + * otherwise power is taken from the coin cell battery. + */ + vin-supply = <&vcc_3v3>; }; }; -- cgit v1.2.3 From 99f0619b0d0d87f921b05f0b7e43ff2e080a4fcc Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:39 +0100 Subject: ARM: dts: meson8b: ec100: add the GPIO line names This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 50 +++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 34cd72911d63..889fdc31fb78 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -289,6 +289,56 @@ }; }; +&gpio_ao { + gpio-line-names = "Linux_TX", "Linux_RX", + "SLP_S5_N", "USB2_OC_FLAG#", + "HUB_RST", "USB_PWR_EN", + "I2S_IN", "SLP_S1_N", + "TCK", "TMS", "TDI", "TDO", + "HDMI_CEC", "5640_IRQ", + "MUTE", "S805_TEST#"; +}; + +&gpio { + gpio-line-names = /* Bank GPIOX */ + "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", + "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", + "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", + "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", + "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", + "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", + /* Bank GPIOY */ + "", "", "", "", "", "", "", "", "", "", + "", "", + /* Bank GPIODV */ + "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", + "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", + "VDDEE_PWM 3V3_5V_EN", + /* Bank GPIOH */ + "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", + "RMII_IRQ", "RMII_RST#", "RMII_TXD1", + "RMII_TXD0", "AV_select_1", "AV_select_2", + "MCU_Control_S", + /* Bank CARD */ + "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", + "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", + "CARD_EN_DET (CARD_DET)", + /* Bank BOOT */ + "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", + "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", + "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", + "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", + "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", + "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", + "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", + "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", + /* Bank DIF */ + "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", + "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", + "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", + "RMII_MDIO"; +}; + &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_c1_pins>; -- cgit v1.2.3 From bffe0d85e51a657d504cfd28345959e2fd28fc7b Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 4 Feb 2019 14:33:33 +0100 Subject: ARM: dts: imx6qdl-phytec-pfla02: add missing interrupt-controller property The DA9063 device need the required "interrupt-controller" property as documented by the bindings [1]. [1] Documentation/devicetree/bindings/mfd/da9063.txt Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1b50b01e9bac..1bfa41e01a0c 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -117,6 +117,7 @@ reg = <0x58>; interrupt-parent = <&gpio2>; interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ + interrupt-controller; regulators { vddcore_reg: bcore1 { -- cgit v1.2.3 From 8de81c89d0a1aff777057dd78c3f5e4c654494f1 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 4 Feb 2019 16:29:56 +0100 Subject: ARM: dts: pfla02: add ksz9031 clock skew values The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC, which needs RX and TX clock skew settings to compensate for differences in line length. The skew values are taken from barebox commit 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which is based on patches originally provided by Phytec: TX_CLK line is approx. 54mm longer than other TX lines which adds a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by setting GTX pad skew value to 11100 Also add a delay for the RX delay lines, needed for the Duallite variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F. Cc: Christian Hemp Signed-off-by: Philipp Zabel Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1bfa41e01a0c..433bf09a1954 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -89,10 +89,23 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; phy-supply = <&vdd_eth_io_reg>; status = "disabled"; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; }; &gpmi { -- cgit v1.2.3 From 4a2c25961aa331e1a2574e6b323fb692d34f9e27 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 6 Feb 2019 00:16:41 +0100 Subject: ARM: dts: vf610: Add ZII SSMB DTU board Add the Zodiac Digital Tapping Unit, a VF610 based network device with 5 Ethernet ports. One of these ports supports 1000Base-T2. Signed-off-by: Andrew Lunn Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 311 +++++++++++++++++++++++++++++++ 2 files changed, 312 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ac1eeb9afdb7..351fadf05c9d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -603,6 +603,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ vf610-zii-scu4-aib.dtb \ + vf610-zii-ssmb-dtu.dtb \ vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts new file mode 100644 index 000000000000..2b10672fadbd --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB DTU board + * + * SSMB - SPU3 Switch Management Board + * DTU - Digital Tapping Unit + * + * Copyright (C) 2015-2019 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB DTU Board"; + compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_100_3"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_4"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_5"; + }; + + port@8 { + reg = <8>; + label = "eth_cu_1000_1"; + }; + + port@9 { + reg = <9>; + label = "eth_cu_1000_2"; + phy-handle = <&phy9>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + + mdio1 { + compatible = "marvell,mv88e6xxx-mdio-external"; + #address-cells = <1>; + #size-cells = <0>; + + phy9: phy9@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + pinctrl-0 = <&pinctrl_gpio_phy9>; + pinctrl-names = "default"; + interrupt-parent = <&gpio2>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* On SSMB */ + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + /* On DSB */ + temperature-sensor@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_phy9: pinctrl-gpio-phy9 { + fsl,pins = < + VF610_PAD_PTB24__GPIO_94 0x219d + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; -- cgit v1.2.3 From 1e797150e02629c6617efd9bd81914667090ffe7 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:30 +0000 Subject: ARM: dts: imx6qdl-sabresd: add regulator control for isl29023 sensor The isl29023 light sensor driver has supported regulator control, assign the power supply for isl29023 to enable the control. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 8930aec6464c..21e03b1b31a9 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -449,6 +449,7 @@ pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; interrupt-parent = <&gpio3>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_sensors>; }; }; -- cgit v1.2.3 From 72af502f17b8ed851c13f4dbb00aa00c1288f321 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:34 +0000 Subject: ARM: dts: imx6qdl-sabresd: add regulators control for mag3110 sensor The mag3110 sensor driver has supported regulators control, assign the power supplies for mag3110 to enable the control. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 21e03b1b31a9..618f186a3370 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -440,6 +440,8 @@ pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; interrupt-parent = <&gpio3>; interrupts = <16 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <®_sensors>; + vddio-supply = <®_sensors>; }; light-sensor@44 { -- cgit v1.2.3 From 14cc68e143b3f8bf712cb93e665ed3e135e22d25 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:38 +0000 Subject: ARM: dts: imx6qdl-sabresd: add regulators control for mma8451 sensor The mma8451 sensor driver has supported regulators control, assign the power supplies for mma8451 to enable the control. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 618f186a3370..80b990150756 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -250,6 +250,8 @@ pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; interrupt-parent = <&gpio1>; interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <®_sensors>; + vddio-supply = <®_sensors>; }; ov5642: camera@3c { -- cgit v1.2.3 From ee9ec3ea79c6b3a2c49ac0b406e401a8d0002abb Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:42 +0000 Subject: ARM: dts: imx6qdl-sabresd: remove reg_sensors' regulator-always-on Now that all sensors supplied by reg_sensors have supported regulator control, reg_sensors does NOT need to be always ON, remove "regulator-always-on" to save power. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 80b990150756..a0705066ccba 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -64,7 +64,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; }; gpio-keys { -- cgit v1.2.3 From 1c207f911fe9c8e78efc5a4803a0aa8a18102a23 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Feb 2019 14:57:23 -0600 Subject: ARM: dts: imx: Add support for Logic PD i.MX6QD EVM The EVM consists of a system on module (SOM) and baseboard, and LCD. This patch adds a DTSI file for the SOM and baseboard separately, then a wrapper to combine them and specify processor type and a LCD information. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi | 555 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6-logicpd-som.dtsi | 365 +++++++++++++++++ arch/arm/boot/dts/imx6q-logicpd.dts | 120 ++++++ 3 files changed, 1040 insertions(+) create mode 100644 arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi create mode 100644 arch/arm/boot/dts/imx6-logicpd-som.dtsi create mode 100644 arch/arm/boot/dts/imx6q-logicpd.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi new file mode 100644 index 000000000000..fb01fa6e4224 --- /dev/null +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +/ { + keyboard { + compatible = "gpio-keys"; + + btn0 { + gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; + label = "btn0"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn1 { + gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; + label = "btn1"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn2 { + gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; + label = "btn2"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn3 { + gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; + label = "btn3"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + }; + + leds { + compatible = "gpio-leds"; + + gen-led0 { + label = "led0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led0>; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + }; + + gen-led1 { + label = "led1"; + gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; + }; + + gen-led2 { + label = "led2"; + gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + gen-led3 { + label = "led3"; + gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_3v3: regulator-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_3v3>; + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet: regulator-ethernet { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_enet>; + compatible = "regulator-fixed"; + regulator-name = "ethernet-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&sw4_reg>; + }; + + reg_audio: regulator-audio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_audio>; + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_hdmi: regulator-hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_hdmi>; + compatible = "regulator-fixed"; + regulator-name = "hdmi-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_uart3: regulator-uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_uart3>; + compatible = "regulator-fixed"; + regulator-name = "uart3-supply"; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_1v8: regulator-1v8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_1v8>; + compatible = "regulator-fixed"; + regulator-name = "1v8-supply"; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mipi: regulator-mipi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_mipi>; + regulator-name = "mipi_pwr_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + phy-supply = <®_enet>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&i2c3 { + ov5640: camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_mipi>; + AVDD-supply = <®_mipi>; + DVDD-supply = <®_mipi>; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + pcf8575: gpio@20 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf8574>; + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + lines-initial-states = <0x0710>; + wakeup-source; + }; +}; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&ssi2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_3v3>; + no-1-8-v; + keep-power-in-suspend; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_led0: led0grp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 + >; + }; + + pinctrl_pcf8574: pcf8575grp { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_1v8: reg1v8grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_reg_3v3: reg3v3grp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + >; + }; + + pinctrl_reg_audio: reg-audiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_reg_enet: reg-enetgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_reg_hdmi: reg-hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_reg_mipi: reg-mipigrp { + fsl,pins = ; + }; + + pinctrl_reg_pcie: reg-pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_reg_uart3: reguart3grp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_reg_usb_h1_vbus: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_reg_usb_otg: reg-usb-otggrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 + >; + }; + + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + +}; diff --git a/arch/arm/boot/dts/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/imx6-logicpd-som.dtsi new file mode 100644 index 000000000000..7ceae3573248 --- /dev/null +++ b/arch/arm/boot/dts/imx6-logicpd-som.dtsi @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1837"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddcore"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddsoc"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_3v3"; + regulator-boot-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "sw3a_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "sw3b_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_rgmii"; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-name = "gen_5v0"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "gen_vsns"; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "gen_1v5"; + }; + + vgen2_reg: vgen2 { + regulator-name = "vgen2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-name = "gen_vadj_0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-name = "gen_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "gen_vadj_1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "gen_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + coin_reg: coin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp102"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +/* Reroute power feeding the CPU to come from the external PMIC */ +®_arm +{ + vin-supply = <&sw1a_reg>; +}; + +®_soc +{ + vin-supply = <&sw1c_reg>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpmi_nand: gpmi-nandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < /* Enable ARM Debugger */ + MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ + >; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wl18xx_vmmc>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts new file mode 100644 index 000000000000..45eb0b7f75f8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-logicpd.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6-logicpd-som.dtsi" +#include "imx6-logicpd-baseboard.dtsi" + +/ { + model = "Logic PD i.MX6QD SOM-M3"; + compatible = "fsl,imx6q"; + + backlight: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 20000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_lcd>; + }; + + panel-lvds0 { + compatible = "okaya,rs800480t-7x0gp"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_lcd: regulator-lcd { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reg>; + compatible = "regulator-fixed"; + regulator-name = "lcd_panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + startup-delay-us = <500000>; + }; + + reg_lcd_reset: regulator-lcd-reset { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reset>; + compatible = "regulator-fixed"; + regulator-name = "nLCD_RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_lcd>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + +}; + +&pwm3 { + status = "okay"; +}; + +®_hdmi { + regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ +}; + +&iomuxc { + pinctrl_lcd_reg: lcdreg { + fsl,pins = < + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ + >; + }; + + pinctrl_lcd_reset: lcdreset { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ + >; + }; +}; -- cgit v1.2.3 From 1241c72b6db13a1e294f9ea25577a3677733582e Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:12:13 +0000 Subject: ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Michal Simek Signed-off-by: Sudeep Holla Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zturn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts index b38704657960..5ec616ebca08 100644 --- a/arch/arm/boot/dts/zynq-zturn.dts +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -54,7 +54,7 @@ label = "K1"; gpios = <&gpio0 0x32 0x1>; linux,code = <0x66>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; -- cgit v1.2.3 From 361df77976664ae862620bf63b05604323687f6f Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 11 Feb 2019 12:27:27 +0000 Subject: ARM: dts: am335x: Add support for Bosch Guardian The Bosch Guardian is a TI am335x based device. It's hardware specifications are as follows: * 256 MB DDR3 memory * 512 MB NAND Flash * USB OTG * RS232 * MicroSD external storage * LCD Display interface Signed-off-by: Martyn Welch [tony@atomide.com: updated to use #include] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-guardian.dts | 511 ++++++++++++++++++++++++++++++++++ 2 files changed, 512 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-guardian.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..1ad9a6307b0a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -719,6 +719,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-cm-t335.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ + am335x-guardian.dtb \ am335x-icev2.dtb \ am335x-lxm.dtb \ am335x-moxa-uc-2101.dtb \ diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts new file mode 100644 index 000000000000..c9611ea4b884 --- /dev/null +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "Bosch AM335x Guardian"; + compatible = "bosch,am335x-guardian", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + button21 { + label = "guardian-power-button"; + linux,code = ; + gpios = <&gpio2 21 0>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + led1 { + label = "green:heartbeat"; + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:mmc0"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; + pinctrl-1 = <&lcd_pins_sleep>; + + display-timings { + 320x240 { + hactive = <320>; + vactive = <240>; + hback-porch = <68>; + hfront-porch = <20>; + hsync-len = <1>; + vback-porch = <18>; + vfront-porch = <4>; + vsync-len = <1>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <24>; + bus-width = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + }; + + pwm7: dmtimer-pwm { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer7>; + pinctrl-names = "default"; + pinctrl-0 = <&dmtimer7_pins>; + }; + + vmmcsd_fixed: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cppi41dma { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ + status = "okay"; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + /* + * MTD partition table + * + * All SPL-* partitions are sized to minimal length which can + * be independently programmable. For NAND flash this is equal + * to size of erase-block. + */ + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0x0 0x40000>; + }; + + partition@1 { + label = "SPL.backup1"; + reg = <0x40000 0x40000>; + }; + + partition@2 { + label = "SPL.backup2"; + reg = <0x80000 0x40000>; + }; + + partition@3 { + label = "SPL.backup3"; + reg = <0xc0000 0x40000>; + }; + + partition@4 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + + partition@5 { + label = "u-boot.backup1"; + reg = <0x200000 0x100000>; + }; + + partition@6 { + label = "u-boot-env"; + reg = <0x300000 0x40000>; + }; + + partition@7 { + label = "u-boot-env.backup1"; + reg = <0x340000 0x40000>; + }; + + partition@8 { + label = "UBI"; + reg = <0x380000 0x1fc80000>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tps: tps@24 { + reg = <0x24>; + }; +}; + +&lcdc { + blue-and-red-wiring = "crossed"; + status = "okay"; +}; + +&mmc1 { + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vmmcsd_fixed>; + status = "okay"; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; + system-power-controller; +}; + +&spi0 { + ti,pindir-d0-out-d1-in; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; +}; + +#include "tps65217.dtsi" + +&tps { + ti,pmic-shutdown-controller; + interrupt-parent = <&intc>; + interrupts = <7>; /* NMI */ + + backlight { + isel = <1>; /* 1 - ISET1, 2 ISET2 */ + fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ + default-brightness = <100>; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin &gpio_pins>; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; + + dmtimer7_pins: pinmux_dmtimer7_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) + >; + }; + + gpio_keys_pins: pinmux_gpio_keys_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) + >; + }; + + gpio_pins: pinmux_gpio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + lcd_disen_pins: pinmux_lcd_disen_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) + >; + }; + + lcd_pins_default: pinmux_lcd_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + >; + }; + + lcd_pins_sleep: pinmux_lcd_pins_sleep { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + nandflash_pins: pinmux_nandflash_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) + >; + }; +}; -- cgit v1.2.3 From 947b7802597106dcbef2ddca23d386f9339ba334 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Mon, 11 Feb 2019 17:20:07 +0100 Subject: ARM: dts: omap3-gta04: declare backlight in lcd node The lcd display of the gta04 has a backlight but the backlight was not referenced in the lcd node, so screen blanking did not turn off the backlight. Fix that. Signed-off-by: Andreas Kemnade Tested-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 843d8795118d..2a8fcc09094d 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -124,6 +124,7 @@ spi-cpol; spi-cpha; + backlight= <&backlight>; label = "lcd"; port { lcd_in: endpoint { @@ -133,7 +134,7 @@ }; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm11 0 12000000 0>; pwm-names = "backlight"; -- cgit v1.2.3 From 51b99b39052854fd7424a3e9d9c47abfde5a1c15 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Feb 2019 20:34:29 +0100 Subject: ARM: dts: rockchip: remove cap-mmc-highspeed from rk3188-bqedison2qc mmc1 node The mmc1 pins are used for SDIO with a wifi chip. The function mmc_sdio_switch_hs() only checks for MMC_CAP_SD_HIGHSPEED and not for MMC_CAP_MMC_HIGHSPEED, so cap-mmc-highspeed can be removed. Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index cc66abb22170..c8b62bbd6a4a 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -460,7 +460,6 @@ &mmc1 { bus-width = <4>; cap-sd-highspeed; - cap-mmc-highspeed; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; -- cgit v1.2.3 From 5aed37a5cdef6453eb3bf307574e19e547ca0432 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Feb 2019 12:51:50 +0100 Subject: ARM: dts: rockchip: add chosen node on veyron devices In order to use earlycon, the stdout-path property needs to be set in the chosen node. All veyron devices use uart2 for debugging, so add it to the core veyron dtsi. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index d8bf939a3aff..0bc2409f6903 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -10,6 +10,10 @@ #include "rk3288.dtsi" / { + chosen { + stdout-path = "serial2:115200n8"; + }; + /* * The default coreboot on veyron devices ignores memory@0 nodes * and would instead create another memory node. -- cgit v1.2.3 From e653eaed97ac925553b7e0adaf0d65170bfd6ef0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 9 Feb 2019 00:05:57 +0100 Subject: ARM: dts: exynos: Enable ADC on Odroid HC1 Odroid HC1 uses the exynos5422-odroid-core.dtsi file as a base. All other Exynos5422 Odroids use the "common". The ADC node was defined only in the latter. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index bf09eab90f8a..9b0bccb77be5 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -36,6 +36,11 @@ }; }; +&adc { + vdd-supply = <&ldo4_reg>; + status = "okay"; +}; + &bus_wcore { devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, <&nocp_mem1_0>, <&nocp_mem1_1>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index b299e541cac0..5f195ad7e467 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -362,11 +362,6 @@ }; }; -&adc { - vdd-supply = <&ldo4_reg>; - status = "okay"; -}; - &hdmi { status = "okay"; ddc = <&i2c_2>; -- cgit v1.2.3 From a66352e005488ecb4b534ba1af58a9f671eba9b8 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 15 Feb 2019 11:36:50 +0100 Subject: ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU Add minimal parameters needed by the Exynos CLKOUT driver to Exynos3250 PMU node. This fixes the following warning on boot: exynos_clkout_init: failed to register clkout clock Fixes: d19bb397e19e ("ARM: dts: exynos: Update PMU node with CLKOUT related data") Cc: Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 608d17454179..5892a9f7622f 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -168,6 +168,9 @@ interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; + clock-names = "clkout8"; + clocks = <&cmu CLK_FIN_PLL>; + #clock-cells = <1>; }; mipi_phy: video-phy { -- cgit v1.2.3 From 8e0861fd7f83760209dff517b4c52acd7c1db4d9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 15 Feb 2019 12:27:45 +0100 Subject: ARM: dts: exynos: Add stdout path property to Arndale board Replace bootargs and kernel console parameter with 'stdout-path' property in 'chosen' node to instruct kernel which serial driver should be used for the kernel console and logs. This allows to enable earlycon messages by adding just 'earlycon' parameter to kernel command line. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b44f03ef3b27..dc6fa6fe83f1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -23,7 +23,7 @@ }; chosen { - bootargs = "console=ttySAC2,115200"; + stdout-path = "serial2:115200n8"; }; gpio_keys { -- cgit v1.2.3 From 4dc185ccc72974222948ccf2eb5fc889ea048fbd Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 18 Feb 2019 14:22:57 +0100 Subject: ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite ARM Performance Monitoring Units (PMUs) are permanently disabled in the Exynos5422 SoC version used on Odroid XU3-lite boards. Disable them in boards dtb to avoid confusing user and getting following warning on boot: hw-breakpoint: Failed to enable monitor mode on CPU 0 Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 0db935f2b836..c19b5a51ca44 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -18,6 +18,14 @@ compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; }; +&arm_a7_pmu { + status = "disabled"; +}; + +&arm_a15_pmu { + status = "disabled"; +}; + &pwm { /* * PWM 0 -- fan -- cgit v1.2.3 From 885b005d232c67025e28e4ada1227248ce290f11 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Tue, 12 Feb 2019 19:03:41 +0100 Subject: ARM: dts: exynos: Add support for secondary DAI to Odroid XU3 This patch extends DAPM routing and adds secondary CPU DAI entry to support the secondary audio PCM interface on Odroid XU3. Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index e84544b220b9..51a843bd65ed 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -24,7 +24,9 @@ "Headphone Jack", "MICBIAS", "IN1", "Headphone Jack", "Speakers", "SPKL", - "Speakers", "SPKR"; + "Speakers", "SPKR", + "I2S Playback", "Mixer DAI TX", + "HiFi Playback", "Mixer DAI TX"; assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, @@ -51,7 +53,7 @@ <196608000>; cpu { - sound-dai = <&i2s0 0>; + sound-dai = <&i2s0 0>, <&i2s0 1>; }; codec { sound-dai = <&hdmi>, <&max98090>; -- cgit v1.2.3 From 625c731d1b2af487fc6be10b9a505699c045813a Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Tue, 12 Feb 2019 19:03:42 +0100 Subject: ARM: dts: exynos: Add support for secondary DAI to Odroid XU4 This patch extends DAPM routing and adds secondary CPU DAI entry to support the secondary audio PCM interface on Odroid XU4. Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 122174ea9e0a..892d389d6d09 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -33,6 +33,8 @@ compatible = "samsung,odroid-xu3-audio"; model = "Odroid-XU4"; + samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; + assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_USER_MAU_EPLL>, @@ -58,7 +60,7 @@ <196608000>; cpu { - sound-dai = <&i2s0 0>; + sound-dai = <&i2s0 0>, <&i2s0 1>; }; codec { -- cgit v1.2.3 From 6a3b25173cd4c6c2cd1ad6f1a3a0a85b488597ed Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 19 Feb 2019 17:12:47 +0100 Subject: arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference marvell,dsa properties has been removed from kirkwood-rd88f6281.dtsi while cleanuping the dsa binding, but the dsa reference in kirkwood-rd88f6281-z0.dts has been missed causing the following errors: arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:21.4-16: Warning (reg_format): /dsa/switch@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:23.5-15: Warning (reg_format): /dsa/switch@0/port@4:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:20.12-26.5: Warning (avoid_default_addr_size): /dsa/switch@0: Relying on default #address-cells value arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:20.12-26.5: Warning (avoid_default_addr_size): /dsa/switch@0: Relying on default #size-cells value arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:22.11-25.6: Warning (avoid_default_addr_size): /dsa/switch@0/port@4: Relying on default #address-cells value arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:22.11-25.6: Warning (avoid_default_addr_size): /dsa/switch@0/port@4: Relying on default #size-cells value So remove the dsa reference too in order to fix this issue. Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts index a9fee2c2bcaf..9d88301daf0e 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts @@ -16,15 +16,6 @@ model = "Marvell RD88f6281 Reference design, with Z0 SoC"; compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - dsa { - switch@0 { - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - port@4 { - reg = <4>; - label = "wan"; - }; - }; - }; }; ð1 { -- cgit v1.2.3 From e8acd8564b96480be21697ed93fbcc69a355ef9a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:14 +0200 Subject: ARM: dts: dra7: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index bb45cb7fc3b6..414f1cd68733 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -77,18 +77,18 @@ }; }; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dra7xx-phy-gmii-sel"; + reg = <0x554 0x4>; + #phy-cells = <1>; + }; + scm_conf_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; - phy_sel: cpsw-phy-sel@554 { - compatible = "ti,dra7xx-cpsw-phy-sel"; - reg= <0x554 0x4>; - reg-names = "gmii-sel"; - }; - dra7_pmx_core: pinmux@1400 { compatible = "ti,dra7-padconf", "pinctrl-single"; @@ -3099,7 +3099,6 @@ ; ranges = <0 0 0x4000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; status = "disabled"; davinci_mdio: mdio@1000 { @@ -3114,11 +3113,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; }; }; }; -- cgit v1.2.3 From 837143940d895ddc55d6ab523aad3fd35375b816 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:15 +0200 Subject: ARM: dts: dm814x: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 601c57afd4fe..413ae19dd5f0 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -343,6 +343,12 @@ #size-cells = <1>; ranges = <0 0 0x800>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dm814-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <1>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -549,17 +555,14 @@ cpsw_emac0: slave@4a100200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + }; cpsw_emac1: slave@4a100300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@48140650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x48140650 0x4>; - reg-names = "gmii-sel"; + phys = <&phy_gmii_sel 2>; }; }; -- cgit v1.2.3 From dab2da84d5db260d8b8edf450ccb67c5660dc5ee Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:16 +0200 Subject: ARM: dts: am4372: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 17 +++++++++-------- arch/arm/boot/dts/am43x-epos-evm.dts | 5 +---- 2 files changed, 10 insertions(+), 12 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ca0896f80248..85c6f4ff1824 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -280,12 +280,6 @@ #size-cells = <1>; ranges = <0 0 0x4000>; - phy_sel: cpsw-phy-sel@650 { - compatible = "ti,am43xx-cpsw-phy-sel"; - reg= <0x650 0x4>; - reg-names = "gmii-sel"; - }; - am43xx_pinmux: pinmux@800 { compatible = "ti,am437-padconf", "pinctrl-single"; @@ -300,11 +294,17 @@ }; scm_conf: scm_conf@0 { - compatible = "syscon"; + compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am43xx-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -555,7 +555,6 @@ cpts_clock_shift = <29>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; davinci_mdio: mdio@1000 { compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; @@ -572,11 +571,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 4ea753b3ee43..9dfd80e3b76e 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -584,10 +584,7 @@ &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; + phys = <&phy_gmii_sel 1 1>; }; &i2c0 { -- cgit v1.2.3 From fcfa0e84eaf71537cffd0749f115be7024556a7f Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:17 +0200 Subject: ARM: dts: am335x: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-ir2110.dts | 4 ---- arch/arm/boot/dts/am335x-baltos-ir3220.dts | 4 ---- arch/arm/boot/dts/am335x-baltos-ir5221.dts | 4 ---- arch/arm/boot/dts/am335x-chiliboard.dts | 4 ---- arch/arm/boot/dts/am335x-icev2.dts | 4 ---- arch/arm/boot/dts/am335x-igep0033.dtsi | 4 ---- arch/arm/boot/dts/am335x-lxm.dts | 4 ---- arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 5 ----- arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 5 ----- arch/arm/boot/dts/am335x-phycore-som.dtsi | 4 ---- arch/arm/boot/dts/am33xx-l4.dtsi | 15 ++++++++------- 11 files changed, 8 insertions(+), 49 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 75de1e723303..50dcf1290ac6 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -72,7 +72,3 @@ dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index 1b215c425c57..f3f1abd26470 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -114,7 +114,3 @@ dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 832ead864dc5..42f473f0ed77 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -133,10 +133,6 @@ phy-handle = <&phy1>; }; -&phy_sel { - rmii-clock-ext = <1>; -}; - &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index b50d5d2e71ff..bffa5dce54ec 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -155,10 +155,6 @@ phy-mode = "rmii"; }; -&phy_sel { - rmii-clock-ext; -}; - /* USB */ &usb { status = "okay"; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index f2005ecca74f..9ac775c71072 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -484,10 +484,6 @@ dual_emac; }; -&phy_sel { - rmii-clock-ext; -}; - &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 55b4c94cfafb..cbd22f25de95 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -123,10 +123,6 @@ phy-mode = "rmii"; }; -&phy_sel { - rmii-clock-ext; -}; - &elm { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index 481edcfaf121..d0e8e720a4d6 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -328,10 +328,6 @@ dual_emac_res_vlan = <3>; }; -&phy_sel { - rmii-clock-ext; -}; - &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 14f781953475..cb5913a69837 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -159,11 +159,6 @@ status = "okay"; }; -&phy_sel { - reg= <0x44e10650 0xf5>; - rmii-clock-ext; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index 5a58efc0c874..e562ce40f290 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -446,11 +446,6 @@ dual_emac_res_vlan = <2>; }; -&phy_sel { - reg= <0x44e10650 0xf5>; - rmii-clock-ext; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 428a25e952b0..015adb626b03 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -100,10 +100,6 @@ status = "okay"; }; -&phy_sel { - rmii-clock-ext; -}; - /* I2C Busses */ &am33xx_pinmux { i2c0_pins: pinmux_i2c0 { diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index e957370f8aec..f459ec316a22 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -279,12 +279,6 @@ #pinctrl-cells = <1>; ranges = <0 0 0x2000>; - phy_sel: cpsw-phy-sel@650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x650 0x4>; - reg-names = "gmii-sel"; - }; - am33xx_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x238>; @@ -300,6 +294,12 @@ #size-cells = <1>; ranges = <0 0 0x800>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am3352-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -715,7 +715,6 @@ interrupts = <40 41 42 43>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; status = "disabled"; davinci_mdio: mdio@1000 { @@ -731,11 +730,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 1>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 1>; }; }; }; -- cgit v1.2.3 From a3238924a820c1d7c977b632b769f3b5690cba09 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 25 Feb 2019 19:42:52 +0100 Subject: ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4 The maximum voltage value for buck8 regulator on Odroid XU3/XU4 boards is set too low. Increase it to the 2000mV as specified on the board schematic. So far the board worked fine, because of the bug in the PMIC driver, which used incorrect step value for that regulator. It interpreted the voltage value set by the bootloader as 1225mV and kept it unchanged. The regulator driver has been however fixed recently in the commit 56b5d4ea778c ("regulator: s2mps11: Fix steps for buck7, buck8 and LDO35"), what results in reading the proper buck8 value and forcing it to 1500mV on boot. This is not enough for proper board operation and results in eMMC errors during heavy IO traffic. Increasing maximum voltage value for buck8 restores original driver behavior and fixes eMMC issues. Signed-off-by: Marek Szyprowski Fixes: 86a2d2ac5e5d ("ARM: dts: Add dts file for Odroid XU3 board") Fixes: 56b5d4ea778c ("regulator: s2mps11: Fix steps for buck7, buck8 and LDO35") Cc: Signed-off-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 9b0bccb77be5..25d95de15c9b 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -473,7 +473,7 @@ buck8_reg: BUCK8 { regulator-name = "vdd_1.8v_ldo"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; regulator-always-on; regulator-boot-on; }; -- cgit v1.2.3