From 209f4d7a3d50ae6e162e6d61765d722bb26a686b Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sun, 10 Apr 2016 21:30:00 +0200 Subject: ARM: dts: pxa: add pxa25x .dtsi file This file describes pxa25x SoCs. Not all devices are listed yet, only the subset which was already tested with a lubbock board. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa25x.dtsi | 92 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/pxa25x.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi new file mode 100644 index 000000000000..0d1e012178c4 --- /dev/null +++ b/arch/arm/boot/dts/pxa25x.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2016 Robert Jarzmik + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa-clock.h" + +/ { + model = "Marvell PXA25x family SoC"; + compatible = "marvell,pxa250"; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa250-core-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + + /* timer oscillator */ + clktimer: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3686400>; + clock-output-names = "ostimer"; + }; + }; + + pxabus { + pdma: dma-controller@40000000 { + compatible = "marvell,pdma-1.0"; + reg = <0x40000000 0x10000>; + interrupts = <25>; + #dma-channels = <16>; + #dma-cells = <2>; + #dma-requests = <40>; + status = "okay"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <32>; + }; + + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa25x-pinctrl"; + }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa25x-gpio"; + gpio-ranges = <&pinctrl 0 0 84>; + clocks = <&clks CLK_NONE>; + }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clktimer>; + status = "okay"; + }; +}; -- cgit v1.2.3 From 4852a25eab45f375d6e8563aa3192a0a8064011a Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Mon, 26 Sep 2016 09:22:11 +0200 Subject: ARM: dts: pxa: fix gpio0 and gpio1 interrupts Since gpio-pxa was redesigned to differenciate gpio0, gpio1 and the gpio-mux interrupt as in the hardware IP, the device-tree description should be amended so that interrupts from gpio0 and gpio1 can be mapped to consumers. This is especially true on lubbock and mainstone devices where gpio0 is multiplexed on pxa_cplds for ethernet, sa1111, usb udc, and other devices. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa2xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 3ff077ca4400..e4ebcde17837 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -54,8 +54,8 @@ reg = <0x40e00000 0x10000>; gpio-controller; #gpio-cells = <0x2>; - interrupts = <10>; - interrupt-names = "gpio_mux"; + interrupts = <8>, <9>, <10>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; interrupt-controller; #interrupt-cells = <0x2>; ranges; -- cgit v1.2.3 From 93ab7c84863e31f58d896174a19793cab7bda8de Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Mon, 31 Oct 2016 20:54:54 +0100 Subject: ARM: dts: pxa: add pxa25x cpu operating points Add the relevant data taken from the PXA 25x Electrical, Mechanical, and Thermal Specfication. This will be input data for cpufreq-dt driver. Signed-off-by: Robert Jarzmik Acked-by: Viresh Kumar --- arch/arm/boot/dts/pxa25x.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi index 0d1e012178c4..f9f4726396a0 100644 --- a/arch/arm/boot/dts/pxa25x.dtsi +++ b/arch/arm/boot/dts/pxa25x.dtsi @@ -89,4 +89,29 @@ clocks = <&clktimer>; status = "okay"; }; + + pxa250_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@99532800 { + opp-hz = /bits/ 64 <99532800>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp@199065600 { + opp-hz = /bits/ 64 <199065600>; + opp-microvolt = <1000000 950000 1650000>; + clock-latency-ns = <20>; + }; + opp@298598400 { + opp-hz = /bits/ 64 <298598400>; + opp-microvolt = <1100000 1045000 1650000>; + clock-latency-ns = <20>; + }; + opp@398131200 { + opp-hz = /bits/ 64 <398131200>; + opp-microvolt = <1300000 1235000 1650000>; + clock-latency-ns = <20>; + }; + }; }; -- cgit v1.2.3 From 74e382b870caf297f4e1a727010c9a26cce6b6af Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Mon, 31 Oct 2016 20:54:55 +0100 Subject: ARM: dts: pxa: add pxa27x cpu operating points Add the relevant data taken from the PXA27x Electrical, Mechanical, and Thermal Specfication. This will be input data for cpufreq-dt driver. Signed-off-by: Robert Jarzmik Acked-by: Viresh Kumar --- arch/arm/boot/dts/pxa27x.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 9e73dc6b3ed3..e0fab48ba6fa 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -137,4 +137,44 @@ clocks = <&clks CLK_OSTIMER>; status = "okay"; }; + + pxa270_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@104000000 { + opp-hz = /bits/ 64 <104000000>; + opp-microvolt = <900000 900000 1705000>; + clock-latency-ns = <20>; + }; + opp@156000000 { + opp-hz = /bits/ 64 <156000000>; + opp-microvolt = <1000000 1000000 1705000>; + clock-latency-ns = <20>; + }; + opp@208000000 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1180000 1180000 1705000>; + clock-latency-ns = <20>; + }; + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1250000 1250000 1705000>; + clock-latency-ns = <20>; + }; + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <1350000 1350000 1705000>; + clock-latency-ns = <20>; + }; + opp@520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1450000 1450000 1705000>; + clock-latency-ns = <20>; + }; + opp@624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <1550000 1550000 1705000>; + clock-latency-ns = <20>; + }; + }; }; -- cgit v1.2.3