From 6de663fe33b35fc95e751f907aa28e608c38f121 Mon Sep 17 00:00:00 2001 From: Alex Wilson Date: Fri, 17 Jul 2015 20:23:55 -0600 Subject: ARM: zynq: DT: Add missing interrupt for L2 pl310 Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/zynq-7000.dtsi') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index d373b3860333..ac0a6a09b652 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -139,6 +139,7 @@ L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; + interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; -- cgit v1.2.3