From 5fd98eb7e8ce0f7d7e4f3c138e5b46fc98389804 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 28 Nov 2018 11:42:30 +0900 Subject: ARM: dts: uniphier: add MIO DMAC nodes Add MIO-DMAC (Media IO DMA Controller) nodes, and use them as the DMA engine of SD/eMMC controllers. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts/uniphier-ld4.dtsi') diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index b73d594b6dcd..c2706cef0b8a 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -235,6 +235,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -246,6 +256,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -263,6 +275,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; -- cgit v1.2.3