From 090e563c91e6cea86e79659868ad70ef313a884a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 10:58:01 +0100 Subject: ARM: dts: sun8i: a23/a33: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi') diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 6838bce7dd4e..12a2ad67844e 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -62,6 +62,7 @@ }; &i2c0 { + pinctrl-0 = <&i2c0_pins>; /* * The gsl1680 is rated at 400KHz and it will not work reliable at * 100KHz, this has been confirmed on multiple different q8 tablets. @@ -79,9 +80,13 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; +}; + &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -96,6 +101,10 @@ }; }; +&pwm { + pinctrl-0 = <&pwm0_pin>; +}; + &r_rsb { status = "okay"; -- cgit v1.2.3