From b77d43943ea83997c6c37b8831d1561981d499c5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 22 Nov 2014 16:23:28 +0100 Subject: ARM: dts: rockchip: temporarily disable smp on rk3288 Stock firmware on rk3288 does not initizalize the CNTVOFF registers of the architected timer correctly. This introduces issues with the newly added SMP support for rk3288, resulting in rcu stalls due to differing timer values per core. There exist preliminary and tested patches for u-boot for this problem, but there are a minority of boards using other bootloaders like coreboot. There also is currently a second solution for miss-initialized architected timers in the works: - clocksource: arch_timer: Fix code to use physical timers when requested - clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers Therefore disable smp on rk3288 again till these are finalized, also allowing coreboot-based boards to boot again. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot/dts/rk3288.dtsi') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 0f50d5d44345..ebcd2d2eef74 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -46,7 +46,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; rockchip,pmu = <&pmu>; cpu0: cpu@500 { -- cgit v1.2.3