From 30499186602afa1d62c2e5d354d02214a0ee00b7 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Sat, 15 Jun 2013 10:21:51 +0530 Subject: ARC: cache detection code bitrot * Number of (i|d)cache ways can be retrieved from BCRs and hence no need to cross check with with built-in constants * Use of IS_ENABLED() to check for a Kconfig option * is_not_cache_aligned() not used anymore Signed-off-by: Vineet Gupta --- arch/arc/include/asm/cache.h | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) (limited to 'arch/arc/include/asm/cache.h') diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 44eb07eb92e5..5802849a6cae 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -18,22 +18,13 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define ARC_ICACHE_WAYS 2 -#define ARC_DCACHE_WAYS 4 - -/* Helpers */ +/* For a rare case where customers have differently config I/D */ #define ARC_ICACHE_LINE_LEN L1_CACHE_BYTES #define ARC_DCACHE_LINE_LEN L1_CACHE_BYTES #define ICACHE_LINE_MASK (~(ARC_ICACHE_LINE_LEN - 1)) #define DCACHE_LINE_MASK (~(ARC_DCACHE_LINE_LEN - 1)) -#if ARC_ICACHE_LINE_LEN != ARC_DCACHE_LINE_LEN -#error "Need to fix some code as I/D cache lines not same" -#else -#define is_not_cache_aligned(p) ((unsigned long)p & (~DCACHE_LINE_MASK)) -#endif - /* * ARC700 doesn't cache any access in top 256M. * Ideal for wiring memory mapped peripherals as we don't need to do -- cgit v1.2.3