From aeb99c85c1c493bfe8a4f53b68af8e68fc1ed7bc Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 11 May 2016 09:34:22 +0200 Subject: dt-bindings: Add Oxford Semiconductor OXNAS pinctrl and gpio bindings Add pinctrl and gpio DT bindings for Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ++++++++++++++++++ .../devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 57 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 000000000000..928ed4f43907 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,47 @@ +* Oxford Semiconductor OXNAS SoC GPIO Controller + +Please refer to gpio.txt for generic information regarding GPIO bindings. + +Required properties: + - compatible: "oxsemi,ox810se-gpio" + - reg: Base address and length for the device. + - interrupts: The port interrupt shared by all pins. + - gpio-controller: Marks the port as GPIO controller. + - #gpio-cells: Two. The first cell is the pin number and + the second cell is used to specify the gpio polarity as defined in + defined in : + 0 = GPIO_ACTIVE_HIGH + 1 = GPIO_ACTIVE_LOW + - interrupt-controller: Marks the device node as an interrupt controller. + - #interrupt-cells: Two. The first cell is the GPIO number and second cell + is used to specify the trigger type as defined in + : + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the + gpio base and count, should be in the format of numeric-gpio-range as + specified in the gpio.txt file. + +Example: + +gpio0: gpio@0 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; +}; + +keys { + ... + + button-esc { + label = "ESC"; + linux,code = <1>; + gpios = <&gpio0 12 0>; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt new file mode 100644 index 000000000000..d6074321f730 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt @@ -0,0 +1,57 @@ +* Oxford Semiconductor OXNAS SoC Family Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +OXNAS 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "oxsemi,ox810se-pinctrl" + - oxsemi,sys-ctrl: a phandle to the system controller syscon node + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + +Example: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + pinctrl_uart2: pinctrl_uart2 { + uart2a { + pins = "gpio31"; + function = "fct3"; + }; + uart2b { + pins = "gpio32"; + function = "fct3"; + }; + }; +}; + +uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; -- cgit v1.2.3 From 7916c0c3c65eae12ce7528031e0c015c85b034c9 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Fri, 13 May 2016 10:49:13 +0530 Subject: pinctrl: add DT binding doc for pincontrol of PMIC max77620/max20024 Maxim Semiconductor's PMIC MAX77620/MAX20024 has 8 GPIO pins which act as GPIO as well as special function mode. Add DT binding document to configure pins in function mode as well as pin configuration parameters. Signed-off-by: Laxman Dewangan Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-max77620.txt | 127 +++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt new file mode 100644 index 000000000000..ad4fce3552bb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt @@ -0,0 +1,127 @@ +Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor. + +Device has 8 GPIO pins which can be configured as GPIO as well as the +special IO functions. + +Please refer file +for details of the common pinctrl bindings used by client devices, +including the meaning of the phrase "pin configuration node". + +Optional Pinmux properties: +-------------------------- +Following properties are required if default setting of pins are required +at boot. +- pinctrl-names: A pinctrl state named per . +- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per + . + +The pin configurations are defined as child of the pinctrl states node. Each +sub-node have following properties: + +Required properties: +------------------ +- pins: List of pins. Valid values of pins properties are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7. + +Optional properties: +------------------- +Following are optional properties defined as pinmux DT binding document +. Absence of properties will leave the configuration +on default. + function, + drive-push-pull, + drive-open-drain, + bias-pull-up, + bias-pull-down. + +Valid values for function properties are: + gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, + reference-out + +Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These +customised properties are required to configure FPS configuration parameters +of these GPIOs. Please refer for more +detail of Flexible Power Sequence (FPS). + +- maxim,active-fps-source: FPS source for the GPIOs to get + enabled/disabled when system is in + active state. Valid values are: + - MAX77620_FPS_SRC_0, + FPS source is FPS0. + - MAX77620_FPS_SRC_1, + FPS source is FPS1 + - MAX77620_FPS_SRC_2 and + FPS source is FPS2 + - MAX77620_FPS_SRC_NONE. + GPIO is not controlled + by FPS events and it gets + enabled/disabled by register + access. + Absence of this property will leave + the FPS configuration register for that + GPIO to default configuration. + +- maxim,active-fps-power-up-slot: Sequencing event slot number on which + the GPIO get enabled when + master FPS input event set to HIGH. + Valid values are 0 to 7. + This is applicable if FPS source is + selected as FPS0, FPS1 or FPS2. + +- maxim,active-fps-power-down-slot: Sequencing event slot number on which + the GPIO get disabled when master + FPS input event set to LOW. + Valid values are 0 to 7. + This is applicable if FPS source is + selected as FPS0, FPS1 or FPS2. + +- maxim,suspend-fps-source: This is same as property + "maxim,active-fps-source" but value + get configured when system enters in + to suspend state. + +- maxim,suspend-fps-power-up-slot: This is same as property + "maxim,active-fps-power-up-slot" but + this value get configured into FPS + configuration register when system + enters into suspend. + This is applicable if suspend state + FPS source is selected as FPS0, FPS1 or + +- maxim,suspend-fps-power-down-slot: This is same as property + "maxim,active-fps-power-down-slot" but + this value get configured into FPS + configuration register when system + enters into suspend. + This is applicable if suspend state + FPS source is selected as FPS0, FPS1 or + FPS2. + +Example: +-------- +#include +... +max77620@3c { + + pinctrl-names = "default"; + pinctrl-0 = <&spmic_default>; + + spmic_default: pinmux@0 { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + }; +}; -- cgit v1.2.3 From 191a79fff8ea88259d94714158cdf7a51c5bf6d3 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Fri, 10 Jun 2016 16:46:34 +0930 Subject: pinctrl: Fix grammar in pinmux request list Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij --- Documentation/pinctrl.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 4976389e432d..cefcf5d88a1c 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -493,12 +493,12 @@ Definitions: - The combination of a FUNCTION and a PIN GROUP determine a certain function for a certain set of pins. The knowledge of the functions and pin groups and their machine-specific particulars are kept inside the pinmux driver, - from the outside only the enumerators are known, and the driver core can: + from the outside only the enumerators are known, and the driver core can + request: - - Request the name of a function with a certain selector (>= 0) + - The name of a function with a certain selector (>= 0) - A list of groups associated with a certain function - - Request that a certain group in that list to be activated for a certain - function + - That a certain group in that list to be activated for a certain function As already described above, pin groups are in turn self-descriptive, so the core will retrieve the actual pin range in a certain group from the -- cgit v1.2.3 From eef06737e5dd9baa1ec8606f74356575ab15291d Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Fri, 10 Jun 2016 16:46:35 +0930 Subject: pinctrl: s/have/has/ in GPIO driver interaction description Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij --- Documentation/pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index cefcf5d88a1c..07d102c3d05a 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -286,7 +286,7 @@ see the section named "pin control requests from drivers" and "drivers needing both pin control and GPIOs" below for details. But in some situations a cross-subsystem mapping between pins and GPIOs is needed. -Since the pin controller subsystem have its pinspace local to the pin +Since the pin controller subsystem has its pinspace local to the pin controller we need a mapping so that the pin control subsystem can figure out which pin controller handles control of a certain GPIO pin. Since a single pin controller may be muxing several GPIO ranges (typically SoCs that have -- cgit v1.2.3 From 73f8fed031d51868b57835cb1616c6aeea20a8d0 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Fri, 10 Jun 2016 16:46:36 +0930 Subject: pinctrl: Reflow/wrap paragraph describing GPIO interaction Signed-off-by: Andrew Jeffery Signed-off-by: Linus Walleij --- Documentation/pinctrl.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 07d102c3d05a..6414a613cb8a 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -286,13 +286,13 @@ see the section named "pin control requests from drivers" and "drivers needing both pin control and GPIOs" below for details. But in some situations a cross-subsystem mapping between pins and GPIOs is needed. -Since the pin controller subsystem has its pinspace local to the pin -controller we need a mapping so that the pin control subsystem can figure out -which pin controller handles control of a certain GPIO pin. Since a single -pin controller may be muxing several GPIO ranges (typically SoCs that have -one set of pins, but internally several GPIO silicon blocks, each modelled as -a struct gpio_chip) any number of GPIO ranges can be added to a pin controller -instance like this: +Since the pin controller subsystem has its pinspace local to the pin controller +we need a mapping so that the pin control subsystem can figure out which pin +controller handles control of a certain GPIO pin. Since a single pin controller +may be muxing several GPIO ranges (typically SoCs that have one set of pins, +but internally several GPIO silicon blocks, each modelled as a struct +gpio_chip) any number of GPIO ranges can be added to a pin controller instance +like this: struct gpio_chip chip_a; struct gpio_chip chip_b; -- cgit v1.2.3 From 7075b30d04fa2df370ba5f904cd5c41271f45131 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 10 Jun 2016 17:11:25 +0200 Subject: pinctrl: sh-pfc: fix property name in bindings doc It must be "drive-strength", with a hyphen. Signed-off-by: Wolfram Sang Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 74e6ec0339d6..e4cf022c992e 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -72,7 +72,7 @@ Pin Configuration Node Properties: The pin configuration parameters use the generic pinconf bindings defined in pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down, drive strength and power-source. For +bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For pins that have a configurable I/O voltage, the power-source value should be the nominal I/O voltage in millivolts. -- cgit v1.2.3 From 38c1e5e7b91dfa82547657269cabf5fba66c7a2b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 3 Jun 2016 13:55:00 +0200 Subject: pinctrl: qcom-ssbi: support for PM8058 The PM8058 is found in connection to the APQ8060 on the APQ8060 Dragonboard. Works the same as all others, just add the compatible string for this variant. Cc: Bjorn Andersson Cc: Andy Gross Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 1 + drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index d74e631e10da..b484ba1af78c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -9,6 +9,7 @@ of PMIC's from Qualcomm. Definition: Should contain one of: "qcom,pm8018-mpp", "qcom,pm8038-mpp", + "qcom,pm8058-mpp", "qcom,pm8821-mpp", "qcom,pm8841-mpp", "qcom,pm8916-mpp", diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 9191727aff5e..0d1392fc32dd 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -744,6 +744,7 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, static const struct of_device_id pm8xxx_mpp_of_match[] = { { .compatible = "qcom,pm8018-mpp" }, { .compatible = "qcom,pm8038-mpp" }, + { .compatible = "qcom,pm8058-mpp" }, { .compatible = "qcom,pm8917-mpp" }, { .compatible = "qcom,pm8821-mpp" }, { .compatible = "qcom,pm8921-mpp" }, -- cgit v1.2.3 From 7440926ed9623dceca3310c5f437d06c859dc02b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 21 Jun 2016 01:40:48 +0300 Subject: pinctrl: Flag strict is a field in struct pinmux_ops Documentation incorrectly refers to struct pinctrl_desc, where no such flag is available. Replace the name of the struct. Fixes: commit 8c4c2016345f ("pinctrl: move strict option to pinmux_ops") Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- Documentation/pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 6414a613cb8a..0d3b9ce0a0b9 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -831,7 +831,7 @@ separate memory range only intended for GPIO driving, and the register range dealing with pin config and pin multiplexing get placed into a different memory range and a separate section of the data sheet. -A flag "strict" in struct pinctrl_desc is available to check and deny +A flag "strict" in struct pinmux_ops is available to check and deny simultaneous access to the same pin from GPIO and pin multiplexing consumers on hardware of this type. The pinctrl driver should set this flag accordingly. -- cgit v1.2.3 From af3f1de4e713062252b58c1cd481592d9e5211bf Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Thu, 23 Jun 2016 13:35:06 -0400 Subject: pinctrl: Broadcom NSP pinctrl device tree bindings Device tree binding documentation for Broadcom NSP IOMUX driver Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,nsp-pinmux.txt | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt new file mode 100644 index 000000000000..603564e5fe6f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt @@ -0,0 +1,79 @@ +Broadcom NSP (Northstar plus) IOMUX Controller + +The NSP IOMUX controller supports group based mux configuration. In +addition, certain pins can be muxed to GPIO function individually. + +Required properties: +- compatible: + Must be "brcm,nsp-pinmux" + +- reg: + Should contain the register physical address and length for each of + GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers + +Properties in subnodes: +- function: + The mux function to select + +- groups: + The list of groups to select with a given function + +For more details, refer to +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +For example: + + pinmux: pinmux@1803f1c0 { + compatible = "brcm,nsp-pinmux"; + reg = <0x1803f1c0 0x04>, + <0x18030028 0x04>, + <0x1803f408 0x04>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm &gpio_b &nand_sel>; + + pwm: pwm { + function = "pwm"; + groups = "pwm0_grp", "pwm1_grp"; + }; + + gpio_b: gpio_b { + function = "gpio_b"; + groups = "gpio_b_0_grp", "gpio_b_1_grp"; + }; + + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; + }; + +List of supported functions and groups in Northstar Plus: + +"spi": "spi_grp" + +"i2c": "i2c_grp" + +"mdio": "mdio_grp" + +"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" + +"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp" + +"uart1": "uart1_grp" + +"uart2": "uart2_grp" + +"synce": "synce_grp" + +"sata_led_grps": "sata0_led_grp", "sata1_led_grp" + +"xtal_out": "xtal_out_grp" + +"sdio": "sdio_pwr_grp", "sdio_1p8v_grp" + +"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp" + +"nand": "nand_grp" + +"emmc": "emmc_grp" -- cgit v1.2.3 From cdd5b3485cd59cb7d9004874d2ac99522da5e624 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Jun 2016 12:15:35 +0200 Subject: dt-bindings: pinctrl: Add MDM9615 TLMM bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Neil Armstrong Acked-by: Rob Herring Acked-by: Björn Andersson Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,mdm9615-pinctrl.txt | 152 +++++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt new file mode 100644 index 000000000000..1b52f01ddcb7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt @@ -0,0 +1,152 @@ +Qualcomm MDM9615 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MDM9615 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,mdm9615-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio87 + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. + Valid values are: + gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart, + sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, + cdc_mclk + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 0x4>; + + gsbi8_uart: gsbi8-uart { + mux { + pins = "gpio34", "gpio35"; + function = "gsbi8"; + }; + + tx { + pins = "gpio34"; + drive-strength = <4>; + bias-disable; + }; + + rx { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; -- cgit v1.2.3 From a1c166aca3d555c6171e9027b81244d4c09099fa Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Sat, 25 Jun 2016 22:21:32 -0700 Subject: pinctrl: qcom: msm8974: Add hsic_ctl pinmux The msm8974 pinctrl variant has a couple USB HSIC "glue" registers that let us mux between the pinctrl register settings or the HSIC core settings for the HSIC pins (gpio 144 and gpio 145). Support this method of operation by adding hsic_data and hsic_strobe pins that can select between hsic_ctl and gpio functions. This allows us to toggle the hsic pin configuration over to the HSIC core at runtime. Cc: Bjorn Andersson Signed-off-by: Stephen Boyd Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,msm8974-pinctrl.txt | 5 ++- drivers/pinctrl/qcom/pinctrl-msm8x74.c | 43 +++++++++++++++++++++- 2 files changed, 46 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt index e4d6a9d20f7d..453bd7c76d6b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt @@ -49,6 +49,9 @@ Valid values for pins are: sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data Supports bias and drive-strength + hsic_data, hsic_strobe + Supports only mux + Valid values for function are: cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm, blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, @@ -70,7 +73,7 @@ Valid values for function are: cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s, - ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio + ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio (Note that this is not yet the complete list of functions) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 46fe6ad5f97e..9eb63d3403d4 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -172,6 +172,8 @@ static const struct pinctrl_pin_desc msm8x74_pins[] = { PINCTRL_PIN(149, "SDC2_CLK"), PINCTRL_PIN(150, "SDC2_CMD"), PINCTRL_PIN(151, "SDC2_DATA"), + PINCTRL_PIN(152, "HSIC_STROBE"), + PINCTRL_PIN(153, "HSIC_DATA"), }; #define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } @@ -328,6 +330,8 @@ static const unsigned int sdc1_data_pins[] = { 148 }; static const unsigned int sdc2_clk_pins[] = { 149 }; static const unsigned int sdc2_cmd_pins[] = { 150 }; static const unsigned int sdc2_data_pins[] = { 151 }; +static const unsigned int hsic_strobe_pins[] = { 152 }; +static const unsigned int hsic_data_pins[] = { 153 }; #define FUNCTION(fname) \ [MSM_MUX_##fname] = { \ @@ -399,6 +403,37 @@ static const unsigned int sdc2_data_pins[] = { 151 }; .intr_detection_width = -1, \ } +#define HSIC_PINGROUP(pg_name, ctl) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_gpio, \ + MSM_MUX_hsic_ctl, \ + }, \ + .nfuncs = 2, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = 25, \ + .pull_bit = -1, \ + .drv_bit = -1, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + /* * TODO: Add the rest of the possible functions and fill out * the pingroup table below. @@ -509,6 +544,7 @@ enum msm8x74_functions { MSM_MUX_fm, MSM_MUX_wlan, MSM_MUX_slimbus, + MSM_MUX_hsic_ctl, MSM_MUX_NA, }; @@ -534,7 +570,8 @@ static const char * const gpio_groups[] = { "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", - "gpio141", "gpio142", "gpio143", "gpio144", "gpio145" + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "hsic_data", + "hsic_strobe", }; static const char * const blsp_uart1_groups[] = { @@ -754,6 +791,7 @@ static const char * const wlan_groups[] = { }; static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; +static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" }; static const struct msm_function msm8x74_functions[] = { FUNCTION(gpio), @@ -861,6 +899,7 @@ static const struct msm_function msm8x74_functions[] = { FUNCTION(fm), FUNCTION(wlan), FUNCTION(slimbus), + FUNCTION(hsic_ctl), }; static const struct msm_pingroup msm8x74_groups[] = { @@ -1016,6 +1055,8 @@ static const struct msm_pingroup msm8x74_groups[] = { SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), + HSIC_PINGROUP(hsic_strobe, 0x2050), + HSIC_PINGROUP(hsic_data, 0x2054), }; #define NUM_GPIO_PINGROUPS 146 -- cgit v1.2.3 From 8e40439b068e436105cde4751109b957c6875a4a Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Tue, 5 Jul 2016 15:40:17 +0200 Subject: Documentation: dt: Add new compatible to STM32 pinctrl driver bindings Signed-off-by: Alexandre TORGUE Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 7b4800cc251e..587bffb9cbc6 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,6 +9,7 @@ Pin controller node: Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" + (b) "st,stm32f746-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to -- cgit v1.2.3 From 14672f43acf475fd3dff2b552c07f4d482ee6a20 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 8 Jul 2016 19:39:03 +0200 Subject: pinctrl: qcom: update DT bindings with ebi2 groups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the ebi2 and ebi2cs groups to the MSM8660 pin control documentation document. Cc: devicetree@vger.kernel.org Cc: Andy Gross Cc: Björn Andersson Cc: Stephen Boyd Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt index 77aa11790163..df9a838ec5f9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt @@ -52,7 +52,7 @@ Valid values for function are: gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, - usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, + usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs Example: -- cgit v1.2.3 From 418af4a88ed41cd38aa817b585b857b8bd5f7fd9 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 18 Jul 2016 10:20:17 -0700 Subject: pinctrl: Update iProc GPIO DT bindings Update the iProc GPIO binding document to add new compatible strings "brcm,iproc-nsp-gpio" and "brcm,iproc-stingray-gpio" to support the iProc based GPIO controller used in the NSP and Stingray SoCs, respectively Signed-off-by: Ray Jui Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/brcm,iproc-gpio.txt | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt index e4277921f3e3..a73cbeb0f309 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt @@ -3,8 +3,22 @@ Broadcom iProc GPIO/PINCONF Controller Required properties: - compatible: - Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", - "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio" + "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that + supports full-featured pinctrl and GPIO functions used in various iProc + based SoCs + + May contain an SoC-specific compatibility string to accommodate any + SoC-specific features + + "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or + "brcm,cygnus-crmu-gpio" for Cygnus SoCs + + "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support + disabled + + "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general + pinctrl support completely disabled in this IP block. In Stingray, a + different IP block is used to handle pinctrl related functions - reg: Define the base and range of the I/O address space that contains SoC -- cgit v1.2.3