From 182d919b84902eece162c63ed3d476c8016b4197 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 19 Feb 2015 23:47:31 +0000 Subject: FS-Cache: Count culled objects and objects rejected due to lack of space Count the number of objects that get culled by the cache backend and the number of objects that the cache backend declines to instantiate due to lack of space in the cache. These numbers are made available through /proc/fs/fscache/stats Signed-off-by: David Howells Reviewed-by: Steve Dickson Acked-by: Jeff Layton --- Documentation/filesystems/caching/backend-api.txt | 23 +++++++++++++++++++++++ Documentation/filesystems/caching/fscache.txt | 4 ++++ 2 files changed, 27 insertions(+) (limited to 'Documentation') diff --git a/Documentation/filesystems/caching/backend-api.txt b/Documentation/filesystems/caching/backend-api.txt index 277d1e810670..c0bd5677271b 100644 --- a/Documentation/filesystems/caching/backend-api.txt +++ b/Documentation/filesystems/caching/backend-api.txt @@ -676,6 +676,29 @@ FS-Cache provides some utilities that a cache backend may make use of: as possible. + (*) Indicate that a stale object was found and discarded: + + void fscache_object_retrying_stale(struct fscache_object *object); + + This is called to indicate that the lookup procedure found an object in + the cache that the netfs decided was stale. The object has been + discarded from the cache and the lookup will be performed again. + + + (*) Indicate that the caching backend killed an object: + + void fscache_object_mark_killed(struct fscache_object *object, + enum fscache_why_object_killed why); + + This is called to indicate that the cache backend preemptively killed an + object. The why parameter should be set to indicate the reason: + + FSCACHE_OBJECT_IS_STALE - the object was stale and needs discarding. + FSCACHE_OBJECT_NO_SPACE - there was insufficient cache space + FSCACHE_OBJECT_WAS_RETIRED - the object was retired when relinquished. + FSCACHE_OBJECT_WAS_CULLED - the object was culled to make space. + + (*) Get and release references on a retrieval record: void fscache_get_retrieval(struct fscache_retrieval *op); diff --git a/Documentation/filesystems/caching/fscache.txt b/Documentation/filesystems/caching/fscache.txt index 770267af5b3e..66fa7fbccfa4 100644 --- a/Documentation/filesystems/caching/fscache.txt +++ b/Documentation/filesystems/caching/fscache.txt @@ -303,6 +303,10 @@ proc files. wrp=N Number of in-progress write_page() cache ops ucp=N Number of in-progress uncache_page() cache ops dsp=N Number of in-progress dissociate_pages() cache ops + CacheEv nsp=N Number of object lookups/creations rejected due to lack of space + stl=N Number of stale objects deleted + rtr=N Number of objects retired when relinquished + cul=N Number of objects culled (*) /proc/fs/fscache/histogram -- cgit v1.2.3 From 03cdd0e4b9a98ae995b81cd8f58e992ec3f44ae2 Mon Sep 17 00:00:00 2001 From: David Howells Date: Wed, 25 Feb 2015 13:21:15 +0000 Subject: FS-Cache: Count the number of initialised operations Count and display through /proc/fs/fscache/stats the number of initialised operations. Signed-off-by: David Howells Reviewed-by: Steve Dickson Acked-by: Jeff Layton --- Documentation/filesystems/caching/fscache.txt | 3 ++- fs/fscache/internal.h | 1 + fs/fscache/operation.c | 1 + fs/fscache/stats.c | 4 +++- 4 files changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/caching/fscache.txt b/Documentation/filesystems/caching/fscache.txt index 66fa7fbccfa4..50f0a5757f48 100644 --- a/Documentation/filesystems/caching/fscache.txt +++ b/Documentation/filesystems/caching/fscache.txt @@ -284,8 +284,9 @@ proc files. enq=N Number of times async ops queued for processing can=N Number of async ops cancelled rej=N Number of async ops rejected due to object lookup/create failure + ini=N Number of async ops initialised dfr=N Number of async ops queued for deferred release - rel=N Number of async ops released + rel=N Number of async ops released (should equal ini=N when idle) gc=N Number of deferred-release async ops garbage collected CacheOp alo=N Number of in-progress alloc_object() cache ops luo=N Number of in-progress lookup_object() cache ops diff --git a/fs/fscache/internal.h b/fs/fscache/internal.h index 87c4544ec912..a63225116db6 100644 --- a/fs/fscache/internal.h +++ b/fs/fscache/internal.h @@ -165,6 +165,7 @@ extern atomic_t fscache_n_op_pend; extern atomic_t fscache_n_op_run; extern atomic_t fscache_n_op_enqueue; extern atomic_t fscache_n_op_deferred_release; +extern atomic_t fscache_n_op_initialised; extern atomic_t fscache_n_op_release; extern atomic_t fscache_n_op_gc; extern atomic_t fscache_n_op_cancelled; diff --git a/fs/fscache/operation.c b/fs/fscache/operation.c index 61a6e78b85fa..9761df4fc2ab 100644 --- a/fs/fscache/operation.c +++ b/fs/fscache/operation.c @@ -39,6 +39,7 @@ void fscache_operation_init(struct fscache_operation *op, op->processor = processor; op->release = release; INIT_LIST_HEAD(&op->pend_link); + fscache_stat(&fscache_n_op_initialised); } EXPORT_SYMBOL(fscache_operation_init); diff --git a/fs/fscache/stats.c b/fs/fscache/stats.c index 3a722e8f2307..7cfa0aacdf6d 100644 --- a/fs/fscache/stats.c +++ b/fs/fscache/stats.c @@ -23,6 +23,7 @@ atomic_t fscache_n_op_run; atomic_t fscache_n_op_enqueue; atomic_t fscache_n_op_requeue; atomic_t fscache_n_op_deferred_release; +atomic_t fscache_n_op_initialised; atomic_t fscache_n_op_release; atomic_t fscache_n_op_gc; atomic_t fscache_n_op_cancelled; @@ -251,7 +252,8 @@ static int fscache_stats_show(struct seq_file *m, void *v) atomic_read(&fscache_n_op_enqueue), atomic_read(&fscache_n_op_cancelled), atomic_read(&fscache_n_op_rejected)); - seq_printf(m, "Ops : dfr=%u rel=%u gc=%u\n", + seq_printf(m, "Ops : ini=%u dfr=%u rel=%u gc=%u\n", + atomic_read(&fscache_n_op_initialised), atomic_read(&fscache_n_op_deferred_release), atomic_read(&fscache_n_op_release), atomic_read(&fscache_n_op_gc)); -- cgit v1.2.3 From c8a8585431efba0faaf41167f8f7c27c48307ca6 Mon Sep 17 00:00:00 2001 From: Vianney le Clément de Saint-Marcq Date: Mon, 30 Mar 2015 10:34:58 +0200 Subject: iio: core: Introduce IIO_CHAN_INFO_CALIBEMISSIVITY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Contact-less IR temperature sensors measure the temperature of an object by using its thermal radiation. Surfaces with different emissivity ratios emit different amounts of energy at the same temperature. IIO_CHAN_INFO_CALIBEMISSIVITY allows the user to inform the sensor of the emissivity of the object in front of it, in order to effectively measure its temperature. A device providing such setting is Melexis's MLX90614: http://melexis.com/Assets/IR-sensor-thermometer-MLX90614-Datasheet-5152.aspx. Signed-off-by: Vianney le Clément de Saint-Marcq Cc: Arnout Vandecappelle (Essensium/Mind) Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 11 +++++++++++ drivers/iio/industrialio-core.c | 1 + include/linux/iio/iio.h | 1 + 3 files changed, 13 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 3befcb19f414..866b4ec4aab6 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -1364,3 +1364,14 @@ Description: hwfifo_watermak_min but not equal to any of the values in this list, the driver will chose an appropriate value for the hardware fifo watermark level. + +What: /sys/bus/iio/devices/iio:deviceX/in_temp_calibemissivity +What: /sys/bus/iio/devices/iio:deviceX/in_tempX_calibemissivity +What: /sys/bus/iio/devices/iio:deviceX/in_temp_object_calibemissivity +What: /sys/bus/iio/devices/iio:deviceX/in_tempX_object_calibemissivity +KernelVersion: 4.1 +Contact: linux-iio@vger.kernel.org +Description: + The emissivity ratio of the surface in the field of view of the + contactless temperature sensor. Emissivity varies from 0 to 1, + with 1 being the emissivity of a black body. diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 4df97f650e44..7c98bc1504e6 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -128,6 +128,7 @@ static const char * const iio_chan_info_postfix[] = { [IIO_CHAN_INFO_CALIBWEIGHT] = "calibweight", [IIO_CHAN_INFO_DEBOUNCE_COUNT] = "debounce_count", [IIO_CHAN_INFO_DEBOUNCE_TIME] = "debounce_time", + [IIO_CHAN_INFO_CALIBEMISSIVITY] = "calibemissivity", }; /** diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index d86b753e9b30..b1e46ae89aa7 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -43,6 +43,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_CALIBWEIGHT, IIO_CHAN_INFO_DEBOUNCE_COUNT, IIO_CHAN_INFO_DEBOUNCE_TIME, + IIO_CHAN_INFO_CALIBEMISSIVITY, }; enum iio_shared_by { -- cgit v1.2.3 From 5147b21a61806b0ff2c29ccb3f8bc37495d5c2ff Mon Sep 17 00:00:00 2001 From: Vianney le Clément de Saint-Marcq Date: Mon, 30 Mar 2015 10:34:59 +0200 Subject: iio: mlx90614: Add devicetree bindings documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also introduce "melexis" as a vendor prefix for device tree bindings. Signed-off-by: Vianney le Clément de Saint-Marcq Cc: Arnout Vandecappelle (Essensium/Mind) Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/temperature/mlx90614.txt | 15 +++++++++++++++ Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/temperature/mlx90614.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt new file mode 100644 index 000000000000..4c959f3b8663 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt @@ -0,0 +1,15 @@ +* Melexis MLX90614 contactless IR temperature sensor + +http://melexis.com/Infrared-Thermometer-Sensors/Infrared-Thermometer-Sensors/MLX90614-615.aspx + +Required properties: + + - compatible: should be "melexis,mlx90614" + - reg: the I2C address of the sensor + +Example: + +mlx90614@5a { + compatible = "melexis,mlx90614"; + reg = <0x5a>; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index fae26d014aaf..c8db30cc59a3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -110,6 +110,7 @@ lltc Linear Technology Corporation marvell Marvell Technology Group Ltd. maxim Maxim Integrated Products mediatek MediaTek Inc. +melexis Melexis N.V. merrii Merrii Technology Co., Ltd. micrel Micrel Inc. microchip Microchip Technology Inc. -- cgit v1.2.3 From eb4b07dae4d4b7915333f687675209f677f72fc6 Mon Sep 17 00:00:00 2001 From: Vianney le Clément de Saint-Marcq Date: Mon, 30 Mar 2015 10:35:01 +0200 Subject: iio: mlx90614: Add power management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for system sleep and runtime power management. To wake up the device, the SDA line should be held low for at least 33ms while SCL is high. As this is not possible using the i2c API (and not supported by all i2c adapters), a GPIO connected to the SDA line is needed. The GPIO is named "wakeup" and can be specified in a device tree with the "wakeup-gpios" binding. If the wake-up GPIO is not given, disable power management for the device. Entering sleep requires an SMBus byte access, hence power management is also disabled if byte access is not supported by the adapter. Signed-off-by: Vianney le Clément de Saint-Marcq Cc: Arnout Vandecappelle (Essensium/Mind) Signed-off-by: Jonathan Cameron --- .../bindings/iio/temperature/mlx90614.txt | 9 + drivers/iio/temperature/mlx90614.c | 246 ++++++++++++++++++++- 2 files changed, 253 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt index 4c959f3b8663..9be57b036092 100644 --- a/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt +++ b/Documentation/devicetree/bindings/iio/temperature/mlx90614.txt @@ -7,9 +7,18 @@ Required properties: - compatible: should be "melexis,mlx90614" - reg: the I2C address of the sensor +Optional properties: + + - wakeup-gpios: device tree identifier of the GPIO connected to the SDA line + to hold low in order to wake up the device. In normal operation, the + GPIO is set as input and will not interfere in I2C communication. There + is no need for a GPIO driving the SCL line. If no GPIO is given, power + management is disabled. + Example: mlx90614@5a { compatible = "melexis,mlx90614"; reg = <0x5a>; + wakeup-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; }; diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c index a307d8c9da89..73ec7677496f 100644 --- a/drivers/iio/temperature/mlx90614.c +++ b/drivers/iio/temperature/mlx90614.c @@ -12,13 +12,24 @@ * * (7-bit I2C slave address 0x5a, 100KHz bus speed only!) * - * TODO: sleep mode, filter configuration + * To wake up from sleep mode, the SDA line must be held low while SCL is high + * for at least 33ms. This is achieved with an extra GPIO that can be connected + * directly to the SDA line. In normal operation, the GPIO is set as input and + * will not interfere in I2C communication. While the GPIO is driven low, the + * i2c adapter is locked since it cannot be used by other clients. The SCL line + * always has a pull-up so we do not need an extra GPIO to drive it high. If + * the "wakeup" GPIO is not given, power management will be disabled. + * + * TODO: filter configuration */ #include #include #include #include +#include +#include +#include #include @@ -52,9 +63,13 @@ #define MLX90614_TIMING_WAKEUP 34 /* time to hold SDA low for wake-up */ #define MLX90614_TIMING_STARTUP 250 /* time before first data after wake-up */ +#define MLX90614_AUTOSLEEP_DELAY 5000 /* default autosleep delay */ + struct mlx90614_data { struct i2c_client *client; struct mutex lock; /* for EEPROM access only */ + struct gpio_desc *wakeup_gpio; /* NULL to disable sleep/wake-up */ + unsigned long ready_timestamp; /* in jiffies */ }; /* @@ -95,6 +110,54 @@ static s32 mlx90614_write_word(const struct i2c_client *client, u8 command, return ret; } +#ifdef CONFIG_PM +/* + * If @startup is true, make sure MLX90614_TIMING_STARTUP ms have elapsed since + * the last wake-up. This is normally only needed to get a valid temperature + * reading. EEPROM access does not need such delay. + * Return 0 on success, <0 on error. + */ +static int mlx90614_power_get(struct mlx90614_data *data, bool startup) +{ + unsigned long now; + + if (!data->wakeup_gpio) + return 0; + + pm_runtime_get_sync(&data->client->dev); + + if (startup) { + now = jiffies; + if (time_before(now, data->ready_timestamp) && + msleep_interruptible(jiffies_to_msecs( + data->ready_timestamp - now)) != 0) { + pm_runtime_put_autosuspend(&data->client->dev); + return -EINTR; + } + } + + return 0; +} + +static void mlx90614_power_put(struct mlx90614_data *data) +{ + if (!data->wakeup_gpio) + return; + + pm_runtime_mark_last_busy(&data->client->dev); + pm_runtime_put_autosuspend(&data->client->dev); +} +#else +static inline int mlx90614_power_get(struct mlx90614_data *data, bool startup) +{ + return 0; +} + +static inline void mlx90614_power_put(struct mlx90614_data *data) +{ +} +#endif + static int mlx90614_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel, int *val, int *val2, long mask) @@ -125,7 +188,12 @@ static int mlx90614_read_raw(struct iio_dev *indio_dev, return -EINVAL; } + ret = mlx90614_power_get(data, true); + if (ret < 0) + return ret; ret = i2c_smbus_read_word_data(data->client, cmd); + mlx90614_power_put(data); + if (ret < 0) return ret; *val = ret; @@ -138,10 +206,12 @@ static int mlx90614_read_raw(struct iio_dev *indio_dev, *val = 20; return IIO_VAL_INT; case IIO_CHAN_INFO_CALIBEMISSIVITY: /* 1/65535 / LSB */ + mlx90614_power_get(data, false); mutex_lock(&data->lock); ret = i2c_smbus_read_word_data(data->client, MLX90614_EMISSIVITY); mutex_unlock(&data->lock); + mlx90614_power_put(data); if (ret < 0) return ret; @@ -172,10 +242,12 @@ static int mlx90614_write_raw(struct iio_dev *indio_dev, return -EINVAL; val = val * 65535 + val2 / 15259; /* 1/65535 ~ 0.000015259 */ + mlx90614_power_get(data, false); mutex_lock(&data->lock); ret = mlx90614_write_word(data->client, MLX90614_EMISSIVITY, val); mutex_unlock(&data->lock); + mlx90614_power_put(data); if (ret < 0) return ret; @@ -235,6 +307,98 @@ static const struct iio_info mlx90614_info = { .driver_module = THIS_MODULE, }; +#ifdef CONFIG_PM +static int mlx90614_sleep(struct mlx90614_data *data) +{ + s32 ret; + + if (!data->wakeup_gpio) { + dev_dbg(&data->client->dev, "Sleep disabled"); + return -ENOSYS; + } + + dev_dbg(&data->client->dev, "Requesting sleep"); + + mutex_lock(&data->lock); + ret = i2c_smbus_xfer(data->client->adapter, data->client->addr, + data->client->flags | I2C_CLIENT_PEC, + I2C_SMBUS_WRITE, MLX90614_OP_SLEEP, + I2C_SMBUS_BYTE, NULL); + mutex_unlock(&data->lock); + + return ret; +} + +static int mlx90614_wakeup(struct mlx90614_data *data) +{ + if (!data->wakeup_gpio) { + dev_dbg(&data->client->dev, "Wake-up disabled"); + return -ENOSYS; + } + + dev_dbg(&data->client->dev, "Requesting wake-up"); + + i2c_lock_adapter(data->client->adapter); + gpiod_direction_output(data->wakeup_gpio, 0); + msleep(MLX90614_TIMING_WAKEUP); + gpiod_direction_input(data->wakeup_gpio); + i2c_unlock_adapter(data->client->adapter); + + data->ready_timestamp = jiffies + + msecs_to_jiffies(MLX90614_TIMING_STARTUP); + + /* + * Quirk: the i2c controller may get confused right after the + * wake-up signal has been sent. As a workaround, do a dummy read. + * If the read fails, the controller will probably be reset so that + * further reads will work. + */ + i2c_smbus_read_word_data(data->client, MLX90614_CONFIG); + + return 0; +} + +/* Return wake-up GPIO or NULL if sleep functionality should be disabled. */ +static struct gpio_desc *mlx90614_probe_wakeup(struct i2c_client *client) +{ + struct gpio_desc *gpio; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_BYTE)) { + dev_info(&client->dev, + "i2c adapter does not support SMBUS_WRITE_BYTE, sleep disabled"); + return NULL; + } + + gpio = devm_gpiod_get_optional(&client->dev, "wakeup", GPIOD_IN); + + if (IS_ERR(gpio)) { + dev_warn(&client->dev, + "gpio acquisition failed with error %ld, sleep disabled", + PTR_ERR(gpio)); + return NULL; + } else if (!gpio) { + dev_info(&client->dev, + "wakeup-gpio not found, sleep disabled"); + } + + return gpio; +} +#else +static inline int mlx90614_sleep(struct mlx90614_data *data) +{ + return -ENOSYS; +} +static inline int mlx90614_wakeup(struct mlx90614_data *data) +{ + return -ENOSYS; +} +static inline struct gpio_desc *mlx90614_probe_wakeup(struct i2c_client *client) +{ + return NULL; +} +#endif + /* Return 0 for single sensor, 1 for dual sensor, <0 on error. */ static int mlx90614_probe_num_ir_sensors(struct i2c_client *client) { @@ -266,6 +430,9 @@ static int mlx90614_probe(struct i2c_client *client, i2c_set_clientdata(client, indio_dev); data->client = client; mutex_init(&data->lock); + data->wakeup_gpio = mlx90614_probe_wakeup(client); + + mlx90614_wakeup(data); indio_dev->dev.parent = &client->dev; indio_dev->name = id->name; @@ -288,12 +455,30 @@ static int mlx90614_probe(struct i2c_client *client, return ret; } + if (data->wakeup_gpio) { + pm_runtime_set_autosuspend_delay(&client->dev, + MLX90614_AUTOSLEEP_DELAY); + pm_runtime_use_autosuspend(&client->dev); + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + } + return iio_device_register(indio_dev); } static int mlx90614_remove(struct i2c_client *client) { - iio_device_unregister(i2c_get_clientdata(client)); + struct iio_dev *indio_dev = i2c_get_clientdata(client); + struct mlx90614_data *data = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + + if (data->wakeup_gpio) { + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + mlx90614_sleep(data); + pm_runtime_set_suspended(&client->dev); + } return 0; } @@ -304,10 +489,67 @@ static const struct i2c_device_id mlx90614_id[] = { }; MODULE_DEVICE_TABLE(i2c, mlx90614_id); +#ifdef CONFIG_PM_SLEEP +static int mlx90614_pm_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct mlx90614_data *data = iio_priv(indio_dev); + + if (data->wakeup_gpio && pm_runtime_active(dev)) + return mlx90614_sleep(data); + + return 0; +} + +static int mlx90614_pm_resume(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct mlx90614_data *data = iio_priv(indio_dev); + int err; + + if (data->wakeup_gpio) { + err = mlx90614_wakeup(data); + if (err < 0) + return err; + + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + } + + return 0; +} +#endif + +#ifdef CONFIG_PM +static int mlx90614_pm_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct mlx90614_data *data = iio_priv(indio_dev); + + return mlx90614_sleep(data); +} + +static int mlx90614_pm_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct mlx90614_data *data = iio_priv(indio_dev); + + return mlx90614_wakeup(data); +} +#endif + +static const struct dev_pm_ops mlx90614_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mlx90614_pm_suspend, mlx90614_pm_resume) + SET_RUNTIME_PM_OPS(mlx90614_pm_runtime_suspend, + mlx90614_pm_runtime_resume, NULL) +}; + static struct i2c_driver mlx90614_driver = { .driver = { .name = "mlx90614", .owner = THIS_MODULE, + .pm = &mlx90614_pm_ops, }, .probe = mlx90614_probe, .remove = mlx90614_remove, -- cgit v1.2.3 From 04a34d4680e75e9be63204b3a7b51a6abe3ce35a Mon Sep 17 00:00:00 2001 From: LEROY Christophe Date: Fri, 17 Apr 2015 16:32:22 +0200 Subject: crypto: talitos - Update DT bindings with SEC1 This patch updates the documentation by including SEC1 into SEC2/3 doc Signed-off-by: Christophe Leroy Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt index 38988ef1336b..f0d926bf9f36 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt @@ -1,9 +1,11 @@ -Freescale SoC SEC Security Engines versions 2.x-3.x +Freescale SoC SEC Security Engines versions 1.x-2.x-3.x Required properties: - compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" + SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) + e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) + warning: SEC1 and SEC2 are mutually exclusive - reg : Offset and length of the register set for the device - interrupts : the SEC's interrupt number - fsl,num-channels : An integer representing the number of channels -- cgit v1.2.3 From cb6d08a2b61fc0025a0148d06b71b8a7d0920e98 Mon Sep 17 00:00:00 2001 From: Ryo Kataoka Date: Sun, 5 Apr 2015 01:55:12 +0900 Subject: ARM: shmobile: r8a7791: Remove MSIOF address from device tree MSIOF Base Address H'E6xx can be accessed by CPU and DMAC. MSIOF Base Address H'E7xx for DMAC was removed from H/W manual. Signed-off-by: Ryo Kataoka Signed-off-by: Yoshihiro Kaneko Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 2 +- arch/arm/boot/dts/r8a7791.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index 4c388bb2f0a2..8f771441be60 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -60,7 +60,7 @@ Example: msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 4696062f6dde..3e9f824797e7 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1288,7 +1288,7 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; @@ -1300,7 +1300,7 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; dmas = <&dmac0 0x55>, <&dmac0 0x56>; @@ -1312,7 +1312,7 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; dmas = <&dmac0 0x41>, <&dmac0 0x42>; -- cgit v1.2.3 From 7917d14129a5a7241289f06d2c5299c5d03ed529 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 18 Mar 2015 11:24:01 +0800 Subject: ARM: sun8i: Add SMP support for the Allwinner A23 The A23 is a dual Cortex-A7. Add the logic to use the IPs used to control the CPU configuration and the CPU power so that we can bring up secondary CPUs at boot. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm/mach-sunxi/platsmp.c | 69 ++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 6aa331d11c5e..d6b794cef0b8 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -188,6 +188,7 @@ nodes to be present and contain the properties described below. # On ARM 32-bit systems this property is optional and can be one of: "allwinner,sun6i-a31" + "allwinner,sun8i-a23" "arm,psci" "brcm,brahma-b15" "marvell,armada-375-smp" diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c index 587b0468efcc..e8483ec79d67 100644 --- a/arch/arm/mach-sunxi/platsmp.c +++ b/arch/arm/mach-sunxi/platsmp.c @@ -121,3 +121,72 @@ static struct smp_operations sun6i_smp_ops __initdata = { .smp_boot_secondary = sun6i_smp_boot_secondary, }; CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops); + +static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm"); + if (!node) { + pr_err("Missing A23 PRCM node in the device tree\n"); + return; + } + + prcm_membase = of_iomap(node, 0); + if (!prcm_membase) { + pr_err("Couldn't map A23 PRCM registers\n"); + return; + } + + node = of_find_compatible_node(NULL, NULL, + "allwinner,sun8i-a23-cpuconfig"); + if (!node) { + pr_err("Missing A23 CPU config node in the device tree\n"); + return; + } + + cpucfg_membase = of_iomap(node, 0); + if (!cpucfg_membase) + pr_err("Couldn't map A23 CPU config registers\n"); + +} + +static int sun8i_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + u32 reg; + + if (!(prcm_membase && cpucfg_membase)) + return -EFAULT; + + spin_lock(&cpu_lock); + + /* Set CPU boot address */ + writel(virt_to_phys(secondary_startup), + cpucfg_membase + CPUCFG_PRIVATE0_REG); + + /* Assert the CPU core in reset */ + writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); + + /* Assert the L1 cache in reset */ + reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); + + /* Clear CPU power-off gating */ + reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); + writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); + mdelay(1); + + /* Deassert the CPU core reset */ + writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); + + spin_unlock(&cpu_lock); + + return 0; +} + +struct smp_operations sun8i_smp_ops __initdata = { + .smp_prepare_cpus = sun8i_smp_prepare_cpus, + .smp_boot_secondary = sun8i_smp_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops); -- cgit v1.2.3 From 8a9cbf5ead43b6b23e11d74d10ac79904d5bc57d Mon Sep 17 00:00:00 2001 From: Tyler Baker Date: Fri, 6 Mar 2015 15:35:05 -0800 Subject: ARM: dts: add vendor prefix for cubietech Add a cubietech vendor prefix, as it is missing. The cubietruck, cubieboard2, and cubieboard all already reference this prefix. Signed-off-by: Tyler Baker Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..9aa8abd4cee4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -52,6 +52,7 @@ cnxt Conexant Systems, Inc. cortina Cortina Systems, Inc. cosmic Cosmic Circuits crystalfontz Crystalfontz America, Inc. +cubietech Cubietech, Ltd. dallas Maxim Integrated Products (formerly Dallas Semiconductor) davicom DAVICOM Semiconductor, Inc. denx Denx Software Engineering -- cgit v1.2.3 From 6554afd218f931021c5e9fbd7b5a236c0d08f4ed Mon Sep 17 00:00:00 2001 From: Aleksei Mamlin Date: Sun, 8 Mar 2015 14:58:16 +0300 Subject: dt-bindings: Add vendor-prefix for Wexler This patch adds vendor-prefix for Wexler. WEXLER trademark owned by AVIRSA Electronics, a member of the diversified holding AVIRSA. Signed-off-by: Aleksei Mamlin Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 9aa8abd4cee4..6a99ddaf212b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -203,6 +203,7 @@ variscite Variscite Ltd. via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium voipac Voipac Technologies s.r.o. +wexler Wexler winbond Winbond Electronics corp. wlf Wolfson Microelectronics wm Wondermedia Technologies, Inc. -- cgit v1.2.3 From 64fcc1fd323835a9185baafa50d2087603c4051c Mon Sep 17 00:00:00 2001 From: Pascal Huerst Date: Mon, 20 Apr 2015 11:12:03 +0200 Subject: ASoC: adau1701: add regulator consumer support The adau1701 has two power domains, DVDD and AVDD. Enable them both as long as the codec is in use. Signed-off-by: Pascal Huerst Acked-by: Lars-Peter Clausen Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/adi,adau1701.txt | 4 + sound/soc/codecs/adau1701.c | 125 ++++++++++++++++++--- 2 files changed, 114 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/adi,adau1701.txt b/Documentation/devicetree/bindings/sound/adi,adau1701.txt index 547a49b56a62..0d1128ce2ea7 100644 --- a/Documentation/devicetree/bindings/sound/adi,adau1701.txt +++ b/Documentation/devicetree/bindings/sound/adi,adau1701.txt @@ -20,6 +20,8 @@ Optional properties: pin configurations as described in the datasheet, table 53. Note that the value of this property has to be prefixed with '/bits/ 8'. + - avdd-supply: Power supply for AVDD, providing 3.3V + - dvdd-supply: Power supply for DVDD, providing 3.3V Examples: @@ -28,6 +30,8 @@ Examples: compatible = "adi,adau1701"; reg = <0x34>; reset-gpio = <&gpio 23 0>; + avdd-supply = <&vdd_3v3_reg>; + dvdd-supply = <&vdd_3v3_reg>; adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4>; diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c index d4e219b6b98f..ca94ae84b916 100644 --- a/sound/soc/codecs/adau1701.c +++ b/sound/soc/codecs/adau1701.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -101,6 +102,10 @@ #define ADAU1701_FIRMWARE "adau1701.bin" +static const char * const supply_names[] = { + "dvdd", "avdd" +}; + struct adau1701 { int gpio_nreset; int gpio_pll_mode[2]; @@ -112,6 +117,7 @@ struct adau1701 { u8 pin_config[12]; struct sigmadsp *sigmadsp; + struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; }; static const struct snd_kcontrol_new adau1701_controls[] = { @@ -669,6 +675,13 @@ static int adau1701_probe(struct snd_soc_codec *codec) if (ret) return ret; + ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies), + adau1701->supplies); + if (ret < 0) { + dev_err(codec->dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + /* * Let the pll_clkdiv variable default to something that won't happen * at runtime. That way, we can postpone the firmware download from @@ -680,7 +693,7 @@ static int adau1701_probe(struct snd_soc_codec *codec) /* initalize with pre-configured pll mode settings */ ret = adau1701_reset(codec, adau1701->pll_clkdiv, 0); if (ret < 0) - return ret; + goto exit_regulators_disable; /* set up pin config */ val = 0; @@ -696,10 +709,60 @@ static int adau1701_probe(struct snd_soc_codec *codec) regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val); return 0; + +exit_regulators_disable: + + regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies); + return ret; } +static int adau1701_remove(struct snd_soc_codec *codec) +{ + struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); + + if (gpio_is_valid(adau1701->gpio_nreset)) + gpio_set_value_cansleep(adau1701->gpio_nreset, 0); + + regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies); + + return 0; +} + +#ifdef CONFIG_PM +static int adau1701_suspend(struct snd_soc_codec *codec) +{ + struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); + + regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), + adau1701->supplies); + + return 0; +} + +static int adau1701_resume(struct snd_soc_codec *codec) +{ + struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies), + adau1701->supplies); + if (ret < 0) { + dev_err(codec->dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + + return adau1701_reset(codec, adau1701->pll_clkdiv, 0); +} +#else +#define adau1701_resume NULL +#define adau1701_suspend NULL +#endif /* CONFIG_PM */ + static struct snd_soc_codec_driver adau1701_codec_drv = { .probe = adau1701_probe, + .remove = adau1701_remove, + .resume = adau1701_resume, + .suspend = adau1701_suspend, .set_bias_level = adau1701_set_bias_level, .idle_bias_off = true, @@ -730,32 +793,58 @@ static int adau1701_i2c_probe(struct i2c_client *client, struct device *dev = &client->dev; int gpio_nreset = -EINVAL; int gpio_pll_mode[2] = { -EINVAL, -EINVAL }; - int ret; + int ret, i; adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL); if (!adau1701) return -ENOMEM; + for (i = 0; i < ARRAY_SIZE(supply_names); i++) + adau1701->supplies[i].supply = supply_names[i]; + + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(adau1701->supplies), + adau1701->supplies); + if (ret < 0) { + dev_err(dev, "Failed to get regulators: %d\n", ret); + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies), + adau1701->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + adau1701->client = client; adau1701->regmap = devm_regmap_init(dev, NULL, client, &adau1701_regmap); - if (IS_ERR(adau1701->regmap)) - return PTR_ERR(adau1701->regmap); + if (IS_ERR(adau1701->regmap)) { + ret = PTR_ERR(adau1701->regmap); + goto exit_regulators_disable; + } + if (dev->of_node) { gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0); - if (gpio_nreset < 0 && gpio_nreset != -ENOENT) - return gpio_nreset; + if (gpio_nreset < 0 && gpio_nreset != -ENOENT) { + ret = gpio_nreset; + goto exit_regulators_disable; + } gpio_pll_mode[0] = of_get_named_gpio(dev->of_node, "adi,pll-mode-gpios", 0); - if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT) - return gpio_pll_mode[0]; + if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT) { + ret = gpio_pll_mode[0]; + goto exit_regulators_disable; + } gpio_pll_mode[1] = of_get_named_gpio(dev->of_node, "adi,pll-mode-gpios", 1); - if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT) - return gpio_pll_mode[1]; + if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT) { + ret = gpio_pll_mode[1]; + goto exit_regulators_disable; + } of_property_read_u32(dev->of_node, "adi,pll-clkdiv", &adau1701->pll_clkdiv); @@ -769,7 +858,7 @@ static int adau1701_i2c_probe(struct i2c_client *client, ret = devm_gpio_request_one(dev, gpio_nreset, GPIOF_OUT_INIT_LOW, "ADAU1701 Reset"); if (ret < 0) - return ret; + goto exit_regulators_disable; } if (gpio_is_valid(gpio_pll_mode[0]) && @@ -778,13 +867,13 @@ static int adau1701_i2c_probe(struct i2c_client *client, GPIOF_OUT_INIT_LOW, "ADAU1701 PLL mode 0"); if (ret < 0) - return ret; + goto exit_regulators_disable; ret = devm_gpio_request_one(dev, gpio_pll_mode[1], GPIOF_OUT_INIT_LOW, "ADAU1701 PLL mode 1"); if (ret < 0) - return ret; + goto exit_regulators_disable; } adau1701->gpio_nreset = gpio_nreset; @@ -795,11 +884,17 @@ static int adau1701_i2c_probe(struct i2c_client *client, adau1701->sigmadsp = devm_sigmadsp_init_i2c(client, &adau1701_sigmadsp_ops, ADAU1701_FIRMWARE); - if (IS_ERR(adau1701->sigmadsp)) - return PTR_ERR(adau1701->sigmadsp); + if (IS_ERR(adau1701->sigmadsp)) { + ret = PTR_ERR(adau1701->sigmadsp); + goto exit_regulators_disable; + } ret = snd_soc_register_codec(&client->dev, &adau1701_codec_drv, &adau1701_dai, 1); + +exit_regulators_disable: + + regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies); return ret; } -- cgit v1.2.3 From 76426aacabc7bb0bafdcad48f5facabe83ebc451 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Fri, 24 Apr 2015 16:19:21 +0200 Subject: spi: spi-ath79: add binding documentation for the AR7100 SPI controller Signed-off-by: Alban Bedel Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-ath79.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-ath79.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-ath79.txt b/Documentation/devicetree/bindings/spi/spi-ath79.txt new file mode 100644 index 000000000000..f1ad9c367532 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-ath79.txt @@ -0,0 +1,24 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- clocks: phandle to the AHB clock. +- clock-names: has to be "ahb". +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1F000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1F000000 0x10>; + + clocks = <&pll 2>; + clock-names = "ahb"; + + #address-cells = <1>; + #size-cells = <0>; + }; -- cgit v1.2.3 From b2dbde542da291adc4ae3bd86686229a23a0b118 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 4 Apr 2015 04:43:37 -0300 Subject: [media] media: i2c/adp1653: Documentation for devicetree support for adp1653 Documentation for adp1653 bindings. Signed-off-by: Pavel Machek Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/adp1653.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/adp1653.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/media/i2c/adp1653.txt b/Documentation/devicetree/bindings/media/i2c/adp1653.txt new file mode 100644 index 000000000000..5ce66f2104e3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/adp1653.txt @@ -0,0 +1,37 @@ +* Analog Devices ADP1653 flash LED driver + +Required Properties: + + - compatible: Must contain "adi,adp1653" + + - reg: I2C slave address + + - enable-gpios: Specifier of the GPIO connected to EN pin + +There are two LED outputs available - flash and indicator. One LED is +represented by one child node, nodes need to be named "flash" and "indicator". + +Required properties of the LED child node: +- max-microamp : see Documentation/devicetree/bindings/leds/common.txt + +Required properties of the flash LED child node: + +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt +- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt + +Example: + + adp1653: led-controller@30 { + compatible = "adi,adp1653"; + reg = <0x30>; + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ + + flash { + flash-timeout-us = <500000>; + flash-max-microamp = <320000>; + max-microamp = <50000>; + }; + indicator { + max-microamp = <17500>; + }; + }; -- cgit v1.2.3 From 12e180a27f3e066a4ed4a446d428fd117f168beb Mon Sep 17 00:00:00 2001 From: Jie Yang Date: Mon, 27 Apr 2015 21:21:02 +0800 Subject: ALSA: Docs: Add documentation for Jack kcontrols Add documentation describing Jack kcontrols and how to use them with HD-Audio and ASoC. Signed-off-by: Jie Yang Signed-off-by: Takashi Iwai --- Documentation/sound/alsa/Jack-Controls.txt | 43 ++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/sound/alsa/Jack-Controls.txt (limited to 'Documentation') diff --git a/Documentation/sound/alsa/Jack-Controls.txt b/Documentation/sound/alsa/Jack-Controls.txt new file mode 100644 index 000000000000..fe1c5e0c8555 --- /dev/null +++ b/Documentation/sound/alsa/Jack-Controls.txt @@ -0,0 +1,43 @@ +Why we need Jack kcontrols +========================== + +ALSA uses kcontrols to export audio controls(switch, volume, Mux, ...) +to user space. This means userspace applications like pulseaudio can +switch off headphones and switch on speakers when no headphones are +pluged in. + +The old ALSA jack code only created input devices for each registered +jack. These jack input devices are not readable by userspace devices +that run as non root. + +The new jack code creates embedded jack kcontrols for each jack that +can be read by any process. + +This can be combined with UCM to allow userspace to route audio more +intelligently based on jack insertion or removal events. + +Jack Kcontrol Internals +======================= + +Each jack will have a kcontrol list, so that we can create a kcontrol +and attach it to the jack, at jack creation stage. We can also add a +kcontrol to an existing jack, at anytime when required. + +Those kcontrols will be freed automatically when the Jack is freed. + +How to use jack kcontrols +========================= + +In order to keep compatibility, snd_jack_new() has been modified by +adding two params :- + + - @initial_kctl: if true, create a kcontrol and add it to the jack + list. + - @phantom_jack: Don't create a input device for phantom jacks. + +HDA jacks can set phantom_jack to true in order to create a phantom +jack and set initial_kctl to true to create an initial kcontrol with +the correct id. + +ASoC jacks should set initial_kctl as false. The pin name will be +assigned as the jack kcontrol name. -- cgit v1.2.3 From 4e39acab03de8db6881dfd981407b6d3ff62c62d Mon Sep 17 00:00:00 2001 From: Peter Chen Date: Fri, 27 Mar 2015 16:32:18 +0800 Subject: usb: Documentation: gadget-testing: fix parameter for capture channel mask Fix the UAC2 parameter capture channel mask Signed-off-by: Peter Chen Signed-off-by: Felipe Balbi --- Documentation/usb/gadget-testing.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/usb/gadget-testing.txt b/Documentation/usb/gadget-testing.txt index f45b2bf4b41d..7769eee3b1b5 100644 --- a/Documentation/usb/gadget-testing.txt +++ b/Documentation/usb/gadget-testing.txt @@ -629,7 +629,7 @@ Function-specific configfs interface The function name to use when creating the function directory is "uac2". The uac2 function provides these attributes in its function directory: - chmask - capture channel mask + c_chmask - capture channel mask c_srate - capture sampling rate c_ssize - capture sample size (bytes) p_chmask - playback channel mask -- cgit v1.2.3 From 73ba51a653e8839b85abc3cca9d57089a8890913 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sat, 25 Apr 2015 05:15:24 -0300 Subject: [media] DocBook/media: attemps -> attempts Fix typo. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/media-func-open.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/media-func-open.xml b/Documentation/DocBook/media/v4l/media-func-open.xml index f7df034dc9ed..122374a3e894 100644 --- a/Documentation/DocBook/media/v4l/media-func-open.xml +++ b/Documentation/DocBook/media/v4l/media-func-open.xml @@ -44,7 +44,7 @@ To open a media device applications call open() with the desired device name. The function has no side effects; the device configuration remain unchanged. - When the device is opened in read-only mode, attemps to modify its + When the device is opened in read-only mode, attempts to modify its configuration will result in an error, and errno will be set to EBADF. -- cgit v1.2.3 From 5a294e5469891d0701183049c4a9678887fa7091 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 8 Apr 2015 19:42:24 +0900 Subject: usb: renesas_usbhs: Revise the binding document about the dma-names Since the DT should describe the hardware (not the driver limitation), This patch revises the binding document about the dma-names to change simple numbering as "ch%d" instead of "tx" and "rx". Also this patch fixes the actual code of renesas_usbhs driver to handle the new dma-names. Signed-off-by: Yoshihiro Shimoda Acked-by: Mark Rutland Acked-by: Geert Uytterhoeven Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/renesas_usbhs.txt | 6 ++---- drivers/usb/renesas_usbhs/fifo.c | 24 ++++++++++++++-------- 2 files changed, 17 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index dc2a18f0b3a1..ddbe304beb21 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -15,10 +15,8 @@ Optional properties: - phys: phandle + phy specifier pair - phy-names: must be "usb" - dmas: Must contain a list of references to DMA specifiers. - - dma-names : Must contain a list of DMA names: - - tx0 ... tx - - rx0 ... rx - - This means DnFIFO in USBHS module. + - dma-names : named "ch%d", where %d is the channel number ranging from zero + to the number of channels (DnFIFOs) minus one. Example: usbhs: usb@e6590000 { diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c index 8597cf9cfceb..bc23b4a2c415 100644 --- a/drivers/usb/renesas_usbhs/fifo.c +++ b/drivers/usb/renesas_usbhs/fifo.c @@ -1227,15 +1227,21 @@ static void usbhsf_dma_init_dt(struct device *dev, struct usbhs_fifo *fifo, { char name[16]; - snprintf(name, sizeof(name), "tx%d", channel); - fifo->tx_chan = dma_request_slave_channel_reason(dev, name); - if (IS_ERR(fifo->tx_chan)) - fifo->tx_chan = NULL; - - snprintf(name, sizeof(name), "rx%d", channel); - fifo->rx_chan = dma_request_slave_channel_reason(dev, name); - if (IS_ERR(fifo->rx_chan)) - fifo->rx_chan = NULL; + /* + * To avoid complex handing for DnFIFOs, the driver uses each + * DnFIFO as TX or RX direction (not bi-direction). + * So, the driver uses odd channels for TX, even channels for RX. + */ + snprintf(name, sizeof(name), "ch%d", channel); + if (channel & 1) { + fifo->tx_chan = dma_request_slave_channel_reason(dev, name); + if (IS_ERR(fifo->tx_chan)) + fifo->tx_chan = NULL; + } else { + fifo->rx_chan = dma_request_slave_channel_reason(dev, name); + if (IS_ERR(fifo->rx_chan)) + fifo->rx_chan = NULL; + } } static void usbhsf_dma_init(struct usbhs_priv *priv, struct usbhs_fifo *fifo, -- cgit v1.2.3 From 591fc116f3302da915bb57d4474a61a5e8884cec Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 9 Apr 2015 11:34:22 +0300 Subject: usb: phy: msm: Use extcon framework for VBUS and ID detection On recent Qualcomm platforms VBUS and ID lines are not routed to USB PHY LINK controller. Use extcon framework to receive connect and disconnect ID and VBUS notification. Signed-off-by: Ivan T. Ivanov Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/msm-hsusb.txt | 7 ++ drivers/usb/phy/Kconfig | 1 + drivers/usb/phy/phy-msm-usb.c | 84 ++++++++++++++++++++++ include/linux/usb/msm_hsusb.h | 17 +++++ 4 files changed, 109 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt index 2826f2af503a..f26bcfac3d8f 100644 --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt @@ -69,6 +69,13 @@ Optional properties: (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner. +- extcon: phandles to external connector devices. First phandle + should point to external connector, which provide "USB" + cable events, the second should point to external connector + device, which provide "USB-HOST" cable events. If one of + the external connector devices is not required empty <0> + phandle should be specified. + Example HSUSB OTG controller device node: usb@f9a55000 { diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 2175678e674e..811f331892d7 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -141,6 +141,7 @@ config USB_MSM_OTG tristate "Qualcomm on-chip USB OTG controller support" depends on (USB || USB_GADGET) && (ARCH_QCOM || COMPILE_TEST) depends on RESET_CONTROLLER + depends on EXTCON select USB_PHY help Enable this to support the USB OTG transceiver on Qualcomm chips. It diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c index c9156beeadef..ad66c67ce9a5 100644 --- a/drivers/usb/phy/phy-msm-usb.c +++ b/drivers/usb/phy/phy-msm-usb.c @@ -1436,9 +1436,42 @@ static const struct of_device_id msm_otg_dt_match[] = { }; MODULE_DEVICE_TABLE(of, msm_otg_dt_match); +static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event, + void *ptr) +{ + struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb); + struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus); + + if (event) + set_bit(B_SESS_VLD, &motg->inputs); + else + clear_bit(B_SESS_VLD, &motg->inputs); + + schedule_work(&motg->sm_work); + + return NOTIFY_DONE; +} + +static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event, + void *ptr) +{ + struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb); + struct msm_otg *motg = container_of(id, struct msm_otg, id); + + if (event) + clear_bit(ID, &motg->inputs); + else + set_bit(ID, &motg->inputs); + + schedule_work(&motg->sm_work); + + return NOTIFY_DONE; +} + static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) { struct msm_otg_platform_data *pdata; + struct extcon_dev *ext_id, *ext_vbus; const struct of_device_id *id; struct device_node *node = pdev->dev.of_node; struct property *prop; @@ -1487,6 +1520,52 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX]; } + ext_id = ERR_PTR(-ENODEV); + ext_vbus = ERR_PTR(-ENODEV); + if (of_property_read_bool(node, "extcon")) { + + /* Each one of them is not mandatory */ + ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0); + if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) + return PTR_ERR(ext_vbus); + + ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1); + if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) + return PTR_ERR(ext_id); + } + + if (!IS_ERR(ext_vbus)) { + motg->vbus.nb.notifier_call = msm_otg_vbus_notifier; + ret = extcon_register_interest(&motg->vbus.conn, ext_vbus->name, + "USB", &motg->vbus.nb); + if (ret < 0) { + dev_err(&pdev->dev, "register VBUS notifier failed\n"); + return ret; + } + + ret = extcon_get_cable_state(ext_vbus, "USB"); + if (ret) + set_bit(B_SESS_VLD, &motg->inputs); + else + clear_bit(B_SESS_VLD, &motg->inputs); + } + + if (!IS_ERR(ext_id)) { + motg->id.nb.notifier_call = msm_otg_id_notifier; + ret = extcon_register_interest(&motg->id.conn, ext_id->name, + "USB-HOST", &motg->id.nb); + if (ret < 0) { + dev_err(&pdev->dev, "register ID notifier failed\n"); + return ret; + } + + ret = extcon_get_cable_state(ext_id, "USB-HOST"); + if (ret) + clear_bit(ID, &motg->inputs); + else + set_bit(ID, &motg->inputs); + } + prop = of_find_property(node, "qcom,phy-init-sequence", &len); if (!prop || !len) return 0; @@ -1700,6 +1779,11 @@ static int msm_otg_remove(struct platform_device *pdev) if (phy->otg->host || phy->otg->gadget) return -EBUSY; + if (motg->id.conn.edev) + extcon_unregister_interest(&motg->id.conn); + if (motg->vbus.conn.edev) + extcon_unregister_interest(&motg->vbus.conn); + msm_otg_debugfs_cleanup(); cancel_delayed_work_sync(&motg->chg_work); cancel_work_sync(&motg->sm_work); diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h index 7dbecf9a4656..c4d956e50d09 100644 --- a/include/linux/usb/msm_hsusb.h +++ b/include/linux/usb/msm_hsusb.h @@ -18,6 +18,7 @@ #ifndef __ASM_ARCH_MSM_HSUSB_H #define __ASM_ARCH_MSM_HSUSB_H +#include #include #include #include @@ -119,6 +120,17 @@ struct msm_otg_platform_data { void (*setup_gpio)(enum usb_otg_state state); }; +/** + * struct msm_usb_cable - structure for exteternal connector cable + * state tracking + * @nb: hold event notification callback + * @conn: used for notification registration + */ +struct msm_usb_cable { + struct notifier_block nb; + struct extcon_specific_cable_nb conn; +}; + /** * struct msm_otg: OTG driver data. Shared by HCD and DCD. * @otg: USB OTG Transceiver structure. @@ -138,6 +150,8 @@ struct msm_otg_platform_data { * @chg_type: The type of charger attached. * @dcd_retires: The retry count used to track Data contact * detection process. + * @vbus: VBUS signal state trakining, using extcon framework + * @id: ID signal state trakining, using extcon framework */ struct msm_otg { struct usb_phy phy; @@ -166,6 +180,9 @@ struct msm_otg { struct reset_control *phy_rst; struct reset_control *link_rst; int vdd_levels[3]; + + struct msm_usb_cable vbus; + struct msm_usb_cable id; }; #endif -- cgit v1.2.3 From 44e42ae3a398b559c768b9b3c324d72b0b0b4479 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 9 Apr 2015 11:34:33 +0300 Subject: usb: phy: msm: Manual PHY and LINK controller VBUS change notification VBUS is not routed to USB PHY on recent Qualcomm platforms. USB controller must see VBUS in order to pull-up DP when setting RS bit. Henc configure USB PHY and LINK registers sense VBUS and enable manual pullup on D+ line. Cc: Vamsi Krishna Cc: Mayank Rana Signed-off-by: Ivan T. Ivanov Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/msm-hsusb.txt | 4 ++++ drivers/usb/phy/phy-msm-usb.c | 26 ++++++++++++++++++++++ include/linux/usb/msm_hsusb.h | 5 +++++ include/linux/usb/msm_hsusb_hw.h | 9 ++++++++ 4 files changed, 44 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt index f26bcfac3d8f..bd8d9e753029 100644 --- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt +++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt @@ -69,6 +69,10 @@ Optional properties: (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner. +- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy + and controller driver therefore enables pull-up explicitly + before starting controller using usbcmd run/stop bit. + - extcon: phandles to external connector devices. First phandle should point to external connector, which provide "USB" cable events, the second should point to external connector diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c index ad66c67ce9a5..00c49bb1bd29 100644 --- a/drivers/usb/phy/phy-msm-usb.c +++ b/drivers/usb/phy/phy-msm-usb.c @@ -240,8 +240,14 @@ static void ulpi_init(struct msm_otg *motg) static int msm_phy_notify_disconnect(struct usb_phy *phy, enum usb_device_speed speed) { + struct msm_otg *motg = container_of(phy, struct msm_otg, phy); int val; + if (motg->manual_pullup) { + val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL; + usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A)); + } + /* * Put the transceiver in non-driving mode. Otherwise host * may not detect soft-disconnection. @@ -422,6 +428,24 @@ static int msm_phy_init(struct usb_phy *phy) ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); } + if (motg->manual_pullup) { + val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT; + ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A)); + + val = readl(USB_GENCONFIG_2); + val |= GENCONFIG_2_SESS_VLD_CTRL_EN; + writel(val, USB_GENCONFIG_2); + + val = readl(USB_USBCMD); + val |= USBCMD_SESS_VLD_CTRL; + writel(val, USB_USBCMD); + + val = ulpi_read(phy, ULPI_FUNC_CTRL); + val &= ~ULPI_FUNC_CTRL_OPMODE_MASK; + val |= ULPI_FUNC_CTRL_OPMODE_NORMAL; + ulpi_write(phy, val, ULPI_FUNC_CTRL); + } + if (motg->phy_number) writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); @@ -1520,6 +1544,8 @@ static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX]; } + motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup"); + ext_id = ERR_PTR(-ENODEV); ext_vbus = ERR_PTR(-ENODEV); if (of_property_read_bool(node, "extcon")) { diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h index c4d956e50d09..e55a1504266e 100644 --- a/include/linux/usb/msm_hsusb.h +++ b/include/linux/usb/msm_hsusb.h @@ -150,6 +150,9 @@ struct msm_usb_cable { * @chg_type: The type of charger attached. * @dcd_retires: The retry count used to track Data contact * detection process. + * @manual_pullup: true if VBUS is not routed to USB controller/phy + * and controller driver therefore enables pull-up explicitly before + * starting controller using usbcmd run/stop bit. * @vbus: VBUS signal state trakining, using extcon framework * @id: ID signal state trakining, using extcon framework */ @@ -181,6 +184,8 @@ struct msm_otg { struct reset_control *link_rst; int vdd_levels[3]; + bool manual_pullup; + struct msm_usb_cable vbus; struct msm_usb_cable id; }; diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h index a29f6030afb1..e159b39f67a2 100644 --- a/include/linux/usb/msm_hsusb_hw.h +++ b/include/linux/usb/msm_hsusb_hw.h @@ -21,6 +21,8 @@ #define USB_AHBBURST (MSM_USB_BASE + 0x0090) #define USB_AHBMODE (MSM_USB_BASE + 0x0098) +#define USB_GENCONFIG_2 (MSM_USB_BASE + 0x00a0) + #define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ #define USB_USBCMD (MSM_USB_BASE + 0x0140) @@ -30,6 +32,9 @@ #define USB_PHY_CTRL (MSM_USB_BASE + 0x0240) #define USB_PHY_CTRL2 (MSM_USB_BASE + 0x0278) +#define GENCONFIG_2_SESS_VLD_CTRL_EN BIT(7) +#define USBCMD_SESS_VLD_CTRL BIT(25) + #define USBCMD_RESET 2 #define USB_USBINTR (MSM_USB_BASE + 0x0148) @@ -50,6 +55,10 @@ #define ULPI_PWR_CLK_MNG_REG 0x88 #define OTG_COMP_DISABLE BIT(0) +#define ULPI_MISC_A 0x96 +#define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1) +#define ULPI_MISC_A_VBUSVLDEXT BIT(0) + #define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */ #define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */ #define PHY_RETEN (1 << 1) /* PHY retention enable/disable */ -- cgit v1.2.3 From b0e6867411ea656124390653570718a90d7167f7 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 9 Apr 2015 15:47:30 +0100 Subject: watchdog: bindings: Provide ST bindings for ST's LPC Watchdog device On current ST platforms the LPC controls a number of functions including Watchdog and Real Time Clock. This patch provides the bindings used to configure LPC in Watchdog mode. Acked-by: Guenter Roeck Signed-off-by: Lee Jones --- .../devicetree/bindings/watchdog/st_lpc_wdt.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt b/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt new file mode 100644 index 000000000000..388c88a01222 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt @@ -0,0 +1,38 @@ +STMicroelectronics Low Power Controller (LPC) - Watchdog +======================================================== + +LPC currently supports Watchdog OR Real Time Clock functionality. + +[See: ../rtc/rtc-st-lpc.txt for RTC options] + +Required properties + +- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc" + "st,stih415-lpc" "st,stid127-lpc" +- reg : LPC registers base address + size +- interrupts : LPC interrupt line number and associated flags +- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) +- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or + ST_LPC_MODE_WDT [1]. One (and only one) mode must be + selected. + +Required properties [watchdog mode] + +- st,syscfg : Phandle to syscfg node used to enable watchdog and configure + CPU reset type. +- timeout-sec : Watchdog timeout in seconds + +Optional properties [watchdog mode] + +- st,warm-reset : If present reset type will be 'warm' - if not it will be cold + +Example: + lpc@fde05000 { + compatible = "st,stih407-lpc"; + reg = <0xfde05000 0x1000>; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + st,syscfg = <&syscfg_core>; + timeout-sec = <120>; + st,lpc-mode = ; + st,warm-reset; + }; -- cgit v1.2.3 From 5cb69745da35c372b3db001efbd3967b633ba0d1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 9 Apr 2015 15:47:32 +0100 Subject: rtc: bindings: Provide ST bindings for ST's LPC RTC device On current ST platforms the LPC controls a number of functions including Watchdog and Real Time Clock. This patch provides the bindings used to configure LPC in RTC mode. Cc: Alessandro Zummo Signed-off-by: Lee Jones --- .../devicetree/bindings/rtc/rtc-st-lpc.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt b/Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt new file mode 100644 index 000000000000..73407f502e4e --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-st-lpc.txt @@ -0,0 +1,25 @@ +STMicroelectronics Low Power Controller (LPC) - RTC +=================================================== + +LPC currently supports Watchdog OR Real Time Clock functionality. + +[See: ../watchdog/st_lpc_wdt.txt for Watchdog options] + +Required properties + +- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc" + "st,stih415-lpc" "st,stid127-lpc" +- reg : LPC registers base address + size +- interrupts : LPC interrupt line number and associated flags +- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) +- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or + ST_LPC_MODE_WDT [1]. One (and only one) mode must be + selected. + +Example: + lpc@fde05000 { + compatible = "st,stih407-lpc"; + reg = <0xfde05000 0x1000>; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + st,lpc-mode = ; + }; -- cgit v1.2.3 From 126187dafd221d672abc2c9839453023b884b5c9 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 30 Apr 2015 15:38:59 +0530 Subject: regulator: Fix spelling error in bindings Minor spell fix, s/intialised/initialised. Signed-off-by: Viresh Kumar Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index abb26b58c83e..606391bea89b 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -13,7 +13,7 @@ Optional properties: - -supply: phandle to the parent supply/regulator node - regulator-ramp-delay: ramp delay for regulator(in uV/uS) For hardware which supports disabling ramp rate, it should be explicitly - intialised to zero (regulator-ramp-delay = <0>) for disabling ramp delay. + initialised to zero (regulator-ramp-delay = <0>) for disabling ramp delay. - regulator-enable-ramp-delay: The time taken, in microseconds, for the supply rail to reach the target voltage, plus/minus whatever tolerance the board design requires. This property describes the total system ramp time -- cgit v1.2.3 From 0bb549052d33f8992544764a6cf1299d06ba7e2f Mon Sep 17 00:00:00 2001 From: Peter Jones Date: Tue, 28 Apr 2015 18:44:31 -0400 Subject: efi: Add esrt support Add sysfs files for the EFI System Resource Table (ESRT) under /sys/firmware/efi/esrt and for each EFI System Resource Entry under entries/ as a subdir. The EFI System Resource Table (ESRT) provides a read-only catalog of system components for which the system accepts firmware upgrades via UEFI's "Capsule Update" feature. This module allows userland utilities to evaluate what firmware updates can be applied to this system, and potentially arrange for those updates to occur. The ESRT is described as part of the UEFI specification, in version 2.5 which should be available from http://uefi.org/specifications in early 2015. If you're a member of the UEFI Forum, information about its addition to the standard is available as UEFI Mantis 1090. For some hardware platforms, additional restrictions may be found at http://msdn.microsoft.com/en-us/library/windows/hardware/jj128256.aspx , and additional documentation may be found at http://download.microsoft.com/download/5/F/5/5F5D16CD-2530-4289-8019-94C6A20BED3C/windows-uefi-firmware-update-platform.docx . Signed-off-by: Peter Jones Signed-off-by: Matt Fleming --- Documentation/ABI/testing/sysfs-firmware-efi-esrt | 81 ++++ arch/x86/platform/efi/efi.c | 2 + drivers/firmware/efi/Makefile | 2 +- drivers/firmware/efi/efi.c | 82 +++- drivers/firmware/efi/esrt.c | 464 ++++++++++++++++++++++ include/linux/efi.h | 8 + 6 files changed, 637 insertions(+), 2 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-firmware-efi-esrt create mode 100644 drivers/firmware/efi/esrt.c (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-firmware-efi-esrt b/Documentation/ABI/testing/sysfs-firmware-efi-esrt new file mode 100644 index 000000000000..6e431d1a4e79 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-firmware-efi-esrt @@ -0,0 +1,81 @@ +What: /sys/firmware/efi/esrt/ +Date: February 2015 +Contact: Peter Jones +Description: Provides userland access to read the EFI System Resource Table + (ESRT), a catalog of firmware for which can be updated with + the UEFI UpdateCapsule mechanism described in section 7.5 of + the UEFI Standard. +Users: fwupdate - https://github.com/rhinstaller/fwupdate + +What: /sys/firmware/efi/esrt/fw_resource_count +Date: February 2015 +Contact: Peter Jones +Description: The number of entries in the ESRT + +What: /sys/firmware/efi/esrt/fw_resource_count_max +Date: February 2015 +Contact: Peter Jones +Description: The maximum number of entries that /could/ be registered + in the allocation the table is currently in. This is + really only useful to the system firmware itself. + +What: /sys/firmware/efi/esrt/fw_resource_version +Date: February 2015 +Contact: Peter Jones +Description: The version of the ESRT structure provided by the firmware. + +What: /sys/firmware/efi/esrt/entries/entry$N/ +Date: February 2015 +Contact: Peter Jones +Description: Each ESRT entry is identified by a GUID, and each gets a + subdirectory under entries/ . + example: /sys/firmware/efi/esrt/entries/entry0/ + +What: /sys/firmware/efi/esrt/entries/entry$N/fw_type +Date: February 2015 +Contact: Peter Jones +Description: What kind of firmware entry this is: + 0 - Unknown + 1 - System Firmware + 2 - Device Firmware + 3 - UEFI Driver + +What: /sys/firmware/efi/esrt/entries/entry$N/fw_class +Date: February 2015 +Contact: Peter Jones +Description: This is the entry's guid, and will match the directory name. + +What: /sys/firmware/efi/esrt/entries/entry$N/fw_version +Date: February 2015 +Contact: Peter Jones +Description: The version of the firmware currently installed. This is a + 32-bit unsigned integer. + +What: /sys/firmware/efi/esrt/entries/entry$N/lowest_supported_fw_version +Date: February 2015 +Contact: Peter Jones +Description: The lowest version of the firmware that can be installed. + +What: /sys/firmware/efi/esrt/entries/entry$N/capsule_flags +Date: February 2015 +Contact: Peter Jones +Description: Flags that must be passed to UpdateCapsule() + +What: /sys/firmware/efi/esrt/entries/entry$N/last_attempt_version +Date: February 2015 +Contact: Peter Jones +Description: The last firmware version for which an update was attempted. + +What: /sys/firmware/efi/esrt/entries/entry$N/last_attempt_status +Date: February 2015 +Contact: Peter Jones +Description: The result of the last firmware update attempt for the + firmware resource entry. + 0 - Success + 1 - Insufficient resources + 2 - Incorrect version + 3 - Invalid format + 4 - Authentication error + 5 - AC power event + 6 - Battery power event + diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 02744df576d5..3b984c3aa1b0 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -501,6 +501,8 @@ void __init efi_init(void) if (efi_enabled(EFI_DBG)) print_efi_memmap(); + + efi_esrt_init(); } void __init efi_late_init(void) diff --git a/drivers/firmware/efi/Makefile b/drivers/firmware/efi/Makefile index d8be608a9f3b..26eabbc55341 100644 --- a/drivers/firmware/efi/Makefile +++ b/drivers/firmware/efi/Makefile @@ -1,7 +1,7 @@ # # Makefile for linux kernel # -obj-$(CONFIG_EFI) += efi.o vars.o reboot.o +obj-$(CONFIG_EFI) += efi.o esrt.o vars.o reboot.o obj-$(CONFIG_EFI_VARS) += efivars.o obj-$(CONFIG_EFI_VARS_PSTORE) += efi-pstore.o obj-$(CONFIG_UEFI_CPER) += cper.o diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c index 3061bb8629dc..48b4c356740f 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -39,6 +39,7 @@ struct efi __read_mostly efi = { .fw_vendor = EFI_INVALID_TABLE_ADDR, .runtime = EFI_INVALID_TABLE_ADDR, .config_table = EFI_INVALID_TABLE_ADDR, + .esrt = EFI_INVALID_TABLE_ADDR, }; EXPORT_SYMBOL(efi); @@ -64,7 +65,7 @@ static int __init parse_efi_cmdline(char *str) } early_param("efi", parse_efi_cmdline); -static struct kobject *efi_kobj; +struct kobject *efi_kobj; static struct kobject *efivars_kobj; /* @@ -232,6 +233,84 @@ err_put: subsys_initcall(efisubsys_init); +/* + * Find the efi memory descriptor for a given physical address. Given a + * physicall address, determine if it exists within an EFI Memory Map entry, + * and if so, populate the supplied memory descriptor with the appropriate + * data. + */ +int __init efi_mem_desc_lookup(u64 phys_addr, efi_memory_desc_t *out_md) +{ + struct efi_memory_map *map = efi.memmap; + void *p, *e; + + if (!efi_enabled(EFI_MEMMAP)) { + pr_err_once("EFI_MEMMAP is not enabled.\n"); + return -EINVAL; + } + + if (!map) { + pr_err_once("efi.memmap is not set.\n"); + return -EINVAL; + } + if (!out_md) { + pr_err_once("out_md is null.\n"); + return -EINVAL; + } + if (WARN_ON_ONCE(!map->phys_map)) + return -EINVAL; + if (WARN_ON_ONCE(map->nr_map == 0) || WARN_ON_ONCE(map->desc_size == 0)) + return -EINVAL; + + e = map->phys_map + map->nr_map * map->desc_size; + for (p = map->phys_map; p < e; p += map->desc_size) { + efi_memory_desc_t *md; + u64 size; + u64 end; + + /* + * If a driver calls this after efi_free_boot_services, + * ->map will be NULL, and the target may also not be mapped. + * So just always get our own virtual map on the CPU. + * + */ + md = early_memremap((phys_addr_t)p, sizeof (*md)); + if (!md) { + pr_err_once("early_memremap(%p, %zu) failed.\n", + p, sizeof (*md)); + return -ENOMEM; + } + + if (!(md->attribute & EFI_MEMORY_RUNTIME) && + md->type != EFI_BOOT_SERVICES_DATA && + md->type != EFI_RUNTIME_SERVICES_DATA) { + early_memunmap(md, sizeof (*md)); + continue; + } + + size = md->num_pages << EFI_PAGE_SHIFT; + end = md->phys_addr + size; + if (phys_addr >= md->phys_addr && phys_addr < end) { + memcpy(out_md, md, sizeof(*out_md)); + early_memunmap(md, sizeof (*md)); + return 0; + } + + early_memunmap(md, sizeof (*md)); + } + pr_err_once("requested map not found.\n"); + return -ENOENT; +} + +/* + * Calculate the highest address of an efi memory descriptor. + */ +u64 __init efi_mem_desc_end(efi_memory_desc_t *md) +{ + u64 size = md->num_pages << EFI_PAGE_SHIFT; + u64 end = md->phys_addr + size; + return end; +} /* * We can't ioremap data in EFI boot services RAM, because we've already mapped @@ -274,6 +353,7 @@ static __initdata efi_config_table_type_t common_tables[] = { {SMBIOS_TABLE_GUID, "SMBIOS", &efi.smbios}, {SMBIOS3_TABLE_GUID, "SMBIOS 3.0", &efi.smbios3}, {UGA_IO_PROTOCOL_GUID, "UGA", &efi.uga}, + {EFI_SYSTEM_RESOURCE_TABLE_GUID, "ESRT", &efi.esrt}, {NULL_GUID, NULL, NULL}, }; diff --git a/drivers/firmware/efi/esrt.c b/drivers/firmware/efi/esrt.c new file mode 100644 index 000000000000..20c0cbdb1c60 --- /dev/null +++ b/drivers/firmware/efi/esrt.c @@ -0,0 +1,464 @@ +/* + * esrt.c + * + * This module exports EFI System Resource Table (ESRT) entries into userspace + * through the sysfs file system. The ESRT provides a read-only catalog of + * system components for which the system accepts firmware upgrades via UEFI's + * "Capsule Update" feature. This module allows userland utilities to evaluate + * what firmware updates can be applied to this system, and potentially arrange + * for those updates to occur. + * + * Data is currently found below /sys/firmware/efi/esrt/... + */ +#define pr_fmt(fmt) "esrt: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct efi_system_resource_entry_v1 { + efi_guid_t fw_class; + u32 fw_type; + u32 fw_version; + u32 lowest_supported_fw_version; + u32 capsule_flags; + u32 last_attempt_version; + u32 last_attempt_status; +}; + +/* + * _count and _version are what they seem like. _max is actually just + * accounting info for the firmware when creating the table; it should never + * have been exposed to us. To wit, the spec says: + * The maximum number of resource array entries that can be within the + * table without reallocating the table, must not be zero. + * Since there's no guidance about what that means in terms of memory layout, + * it means nothing to us. + */ +struct efi_system_resource_table { + u32 fw_resource_count; + u32 fw_resource_count_max; + u64 fw_resource_version; + u8 entries[]; +}; + +static phys_addr_t esrt_data; +static size_t esrt_data_size; + +static struct efi_system_resource_table *esrt; + +struct esre_entry { + union { + struct efi_system_resource_entry_v1 *esre1; + } esre; + + struct kobject kobj; + struct list_head list; +}; + +/* global list of esre_entry. */ +static LIST_HEAD(entry_list); + +/* entry attribute */ +struct esre_attribute { + struct attribute attr; + ssize_t (*show)(struct esre_entry *entry, char *buf); + ssize_t (*store)(struct esre_entry *entry, + const char *buf, size_t count); +}; + +static struct esre_entry *to_entry(struct kobject *kobj) +{ + return container_of(kobj, struct esre_entry, kobj); +} + +static struct esre_attribute *to_attr(struct attribute *attr) +{ + return container_of(attr, struct esre_attribute, attr); +} + +static ssize_t esre_attr_show(struct kobject *kobj, + struct attribute *_attr, char *buf) +{ + struct esre_entry *entry = to_entry(kobj); + struct esre_attribute *attr = to_attr(_attr); + + /* Don't tell normal users what firmware versions we've got... */ + if (!capable(CAP_SYS_ADMIN)) + return -EACCES; + + return attr->show(entry, buf); +} + +static const struct sysfs_ops esre_attr_ops = { + .show = esre_attr_show, +}; + +/* Generic ESRT Entry ("ESRE") support. */ +static ssize_t esre_fw_class_show(struct esre_entry *entry, char *buf) +{ + char *str = buf; + + efi_guid_to_str(&entry->esre.esre1->fw_class, str); + str += strlen(str); + str += sprintf(str, "\n"); + + return str - buf; +} + +static struct esre_attribute esre_fw_class = __ATTR(fw_class, 0400, + esre_fw_class_show, NULL); + +#define esre_attr_decl(name, size, fmt) \ +static ssize_t esre_##name##_show(struct esre_entry *entry, char *buf) \ +{ \ + return sprintf(buf, fmt "\n", \ + le##size##_to_cpu(entry->esre.esre1->name)); \ +} \ +\ +static struct esre_attribute esre_##name = __ATTR(name, 0400, \ + esre_##name##_show, NULL) + +esre_attr_decl(fw_type, 32, "%u"); +esre_attr_decl(fw_version, 32, "%u"); +esre_attr_decl(lowest_supported_fw_version, 32, "%u"); +esre_attr_decl(capsule_flags, 32, "0x%x"); +esre_attr_decl(last_attempt_version, 32, "%u"); +esre_attr_decl(last_attempt_status, 32, "%u"); + +static struct attribute *esre1_attrs[] = { + &esre_fw_class.attr, + &esre_fw_type.attr, + &esre_fw_version.attr, + &esre_lowest_supported_fw_version.attr, + &esre_capsule_flags.attr, + &esre_last_attempt_version.attr, + &esre_last_attempt_status.attr, + NULL +}; +static void esre_release(struct kobject *kobj) +{ + struct esre_entry *entry = to_entry(kobj); + + list_del(&entry->list); + kfree(entry); +} + +static struct kobj_type esre1_ktype = { + .release = esre_release, + .sysfs_ops = &esre_attr_ops, + .default_attrs = esre1_attrs, +}; + + +static struct kobject *esrt_kobj; +static struct kset *esrt_kset; + +static int esre_create_sysfs_entry(void *esre, int entry_num) +{ + int rc = 0; + struct esre_entry *entry; + char name[20]; + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + sprintf(name, "entry%d", entry_num); + + entry->kobj.kset = esrt_kset; + + if (esrt->fw_resource_version == 1) { + entry->esre.esre1 = esre; + rc = kobject_init_and_add(&entry->kobj, &esre1_ktype, NULL, + "%s", name); + } + if (rc) { + kfree(entry); + return rc; + } + + list_add_tail(&entry->list, &entry_list); + return 0; +} + +/* support for displaying ESRT fields at the top level */ +#define esrt_attr_decl(name, size, fmt) \ +static ssize_t esrt_##name##_show(struct kobject *kobj, \ + struct kobj_attribute *attr, char *buf)\ +{ \ + return sprintf(buf, fmt "\n", le##size##_to_cpu(esrt->name)); \ +} \ +\ +static struct kobj_attribute esrt_##name = __ATTR(name, 0400, \ + esrt_##name##_show, NULL) + +esrt_attr_decl(fw_resource_count, 32, "%u"); +esrt_attr_decl(fw_resource_count_max, 32, "%u"); +esrt_attr_decl(fw_resource_version, 64, "%llu"); + +static struct attribute *esrt_attrs[] = { + &esrt_fw_resource_count.attr, + &esrt_fw_resource_count_max.attr, + &esrt_fw_resource_version.attr, + NULL, +}; + +static inline int esrt_table_exists(void) +{ + if (!efi_enabled(EFI_CONFIG_TABLES)) + return 0; + if (efi.esrt == EFI_INVALID_TABLE_ADDR) + return 0; + return 1; +} + +static umode_t esrt_attr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + if (!esrt_table_exists()) + return 0; + return attr->mode; +} + +static struct attribute_group esrt_attr_group = { + .attrs = esrt_attrs, + .is_visible = esrt_attr_is_visible, +}; + +/* + * remap the table, copy it to kmalloced pages, and unmap it. + */ +void __init efi_esrt_init(void) +{ + void *va; + struct efi_system_resource_table tmpesrt; + struct efi_system_resource_entry_v1 *v1_entries; + size_t size, max, entry_size, entries_size; + efi_memory_desc_t md; + int rc; + + pr_debug("esrt-init: loading.\n"); + if (!esrt_table_exists()) + return; + + rc = efi_mem_desc_lookup(efi.esrt, &md); + if (rc < 0) { + pr_err("ESRT header is not in the memory map.\n"); + return; + } + + max = efi_mem_desc_end(&md); + if (max < efi.esrt) { + pr_err("EFI memory descriptor is invalid. (esrt: %p max: %p)\n", + (void *)efi.esrt, (void *)max); + return; + } + + size = sizeof(*esrt); + max -= efi.esrt; + + if (max < size) { + pr_err("ESRT header doen't fit on single memory map entry. (size: %zu max: %zu)\n", + size, max); + return; + } + + va = early_memremap(efi.esrt, size); + if (!va) { + pr_err("early_memremap(%p, %zu) failed.\n", (void *)efi.esrt, + size); + return; + } + + memcpy(&tmpesrt, va, sizeof(tmpesrt)); + + if (tmpesrt.fw_resource_version == 1) { + entry_size = sizeof (*v1_entries); + } else { + pr_err("Unsupported ESRT version %lld.\n", + tmpesrt.fw_resource_version); + return; + } + + if (tmpesrt.fw_resource_count > 0 && max - size < entry_size) { + pr_err("ESRT memory map entry can only hold the header. (max: %zu size: %zu)\n", + max - size, entry_size); + goto err_memunmap; + } + + /* + * The format doesn't really give us any boundary to test here, + * so I'm making up 128 as the max number of individually updatable + * components we support. + * 128 should be pretty excessive, but there's still some chance + * somebody will do that someday and we'll need to raise this. + */ + if (tmpesrt.fw_resource_count > 128) { + pr_err("ESRT says fw_resource_count has very large value %d.\n", + tmpesrt.fw_resource_count); + goto err_memunmap; + } + + /* + * We know it can't be larger than N * sizeof() here, and N is limited + * by the previous test to a small number, so there's no overflow. + */ + entries_size = tmpesrt.fw_resource_count * entry_size; + if (max < size + entries_size) { + pr_err("ESRT does not fit on single memory map entry (size: %zu max: %zu)\n", + size, max); + goto err_memunmap; + } + + /* remap it with our (plausible) new pages */ + early_memunmap(va, size); + size += entries_size; + va = early_memremap(efi.esrt, size); + if (!va) { + pr_err("early_memremap(%p, %zu) failed.\n", (void *)efi.esrt, + size); + return; + } + + esrt_data = (phys_addr_t)efi.esrt; + esrt_data_size = size; + + pr_info("Reserving ESRT space from %p to %p.\n", (void *)esrt_data, + (char *)esrt_data + size); + memblock_reserve(esrt_data, esrt_data_size); + + pr_debug("esrt-init: loaded.\n"); +err_memunmap: + early_memunmap(va, size); +} + +static int __init register_entries(void) +{ + struct efi_system_resource_entry_v1 *v1_entries = (void *)esrt->entries; + int i, rc; + + if (!esrt_table_exists()) + return 0; + + for (i = 0; i < le32_to_cpu(esrt->fw_resource_count); i++) { + void *entry; + if (esrt->fw_resource_version == 1) { + entry = &v1_entries[i]; + } + rc = esre_create_sysfs_entry(entry, i); + if (rc < 0) { + pr_err("ESRT entry creation failed with error %d.\n", + rc); + return rc; + } + } + return 0; +} + +static void cleanup_entry_list(void) +{ + struct esre_entry *entry, *next; + + list_for_each_entry_safe(entry, next, &entry_list, list) { + kobject_put(&entry->kobj); + } +} + +static int __init esrt_sysfs_init(void) +{ + int error; + struct efi_system_resource_table __iomem *ioesrt; + + pr_debug("esrt-sysfs: loading.\n"); + if (!esrt_data || !esrt_data_size) + return -ENOSYS; + + ioesrt = ioremap(esrt_data, esrt_data_size); + if (!ioesrt) { + pr_err("ioremap(%p, %zu) failed.\n", (void *)esrt_data, + esrt_data_size); + return -ENOMEM; + } + + esrt = kmalloc(esrt_data_size, GFP_KERNEL); + if (!esrt) { + pr_err("kmalloc failed. (wanted %zu bytes)\n", esrt_data_size); + iounmap(ioesrt); + return -ENOMEM; + } + + memcpy_fromio(esrt, ioesrt, esrt_data_size); + + esrt_kobj = kobject_create_and_add("esrt", efi_kobj); + if (!esrt_kobj) { + pr_err("Firmware table registration failed.\n"); + error = -ENOMEM; + goto err; + } + + error = sysfs_create_group(esrt_kobj, &esrt_attr_group); + if (error) { + pr_err("Sysfs attribute export failed with error %d.\n", + error); + goto err_remove_esrt; + } + + esrt_kset = kset_create_and_add("entries", NULL, esrt_kobj); + if (!esrt_kset) { + pr_err("kset creation failed.\n"); + error = -ENOMEM; + goto err_remove_group; + } + + error = register_entries(); + if (error) + goto err_cleanup_list; + + memblock_remove(esrt_data, esrt_data_size); + + pr_debug("esrt-sysfs: loaded.\n"); + + return 0; +err_cleanup_list: + cleanup_entry_list(); + kset_unregister(esrt_kset); +err_remove_group: + sysfs_remove_group(esrt_kobj, &esrt_attr_group); +err_remove_esrt: + kobject_put(esrt_kobj); +err: + kfree(esrt); + esrt = NULL; + return error; +} + +static void __exit esrt_sysfs_exit(void) +{ + pr_debug("esrt-sysfs: unloading.\n"); + cleanup_entry_list(); + kset_unregister(esrt_kset); + sysfs_remove_group(esrt_kobj, &esrt_attr_group); + kfree(esrt); + esrt = NULL; + kobject_del(esrt_kobj); + kobject_put(esrt_kobj); +} + +module_init(esrt_sysfs_init); +module_exit(esrt_sysfs_exit); + +MODULE_AUTHOR("Peter Jones "); +MODULE_DESCRIPTION("EFI System Resource Table support"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/efi.h b/include/linux/efi.h index af5be0368dec..024c27e7c0fa 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -583,6 +583,9 @@ void efi_native_runtime_setup(void); #define EFI_FILE_INFO_ID \ EFI_GUID( 0x9576e92, 0x6d3f, 0x11d2, 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b ) +#define EFI_SYSTEM_RESOURCE_TABLE_GUID \ + EFI_GUID( 0xb122a263, 0x3661, 0x4f68, 0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 ) + #define EFI_FILE_SYSTEM_GUID \ EFI_GUID( 0x964e5b22, 0x6459, 0x11d2, 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b ) @@ -823,6 +826,7 @@ extern struct efi { unsigned long fw_vendor; /* fw_vendor */ unsigned long runtime; /* runtime table */ unsigned long config_table; /* config tables */ + unsigned long esrt; /* ESRT table */ efi_get_time_t *get_time; efi_set_time_t *set_time; efi_get_wakeup_time_t *get_wakeup_time; @@ -875,6 +879,7 @@ static inline efi_status_t efi_query_variable_store(u32 attributes, unsigned lon #endif extern void __iomem *efi_lookup_mapped_addr(u64 phys_addr); extern int efi_config_init(efi_config_table_type_t *arch_tables); +extern void __init efi_esrt_init(void); extern int efi_config_parse_tables(void *config_tables, int count, int sz, efi_config_table_type_t *arch_tables); extern u64 efi_get_iobase (void); @@ -882,12 +887,15 @@ extern u32 efi_mem_type (unsigned long phys_addr); extern u64 efi_mem_attributes (unsigned long phys_addr); extern u64 efi_mem_attribute (unsigned long phys_addr, unsigned long size); extern int __init efi_uart_console_only (void); +extern u64 efi_mem_desc_end(efi_memory_desc_t *md); +extern int efi_mem_desc_lookup(u64 phys_addr, efi_memory_desc_t *out_md); extern void efi_initialize_iomem_resources(struct resource *code_resource, struct resource *data_resource, struct resource *bss_resource); extern void efi_get_time(struct timespec *now); extern void efi_reserve_boot_services(void); extern int efi_get_fdt_params(struct efi_fdt_params *params, int verbose); extern struct efi_memory_map memmap; +extern struct kobject *efi_kobj; extern int efi_reboot_quirk_mode; extern bool efi_poweroff_required(void); -- cgit v1.2.3 From a93e178838b85409601c9b909af5addbbfd90264 Mon Sep 17 00:00:00 2001 From: Alex Smith Date: Sat, 28 Mar 2015 12:14:09 +0000 Subject: x86, doc: Remove cmdline_size from list of fields to be filled in for EFI handover The cmdline_size field in setup_header is listed as read-only, and is never read by the kernel. Therefore, there is no need for it to be set by a boot loader implementing the EFI handover protocol, so remove it from the list of fields required to be set by a boot loader. Signed-off-by: Alex Smith Cc: H. Peter Anvin Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Matt Fleming --- Documentation/x86/boot.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/x86/boot.txt b/Documentation/x86/boot.txt index 88b85899d309..7c1f9fad6674 100644 --- a/Documentation/x86/boot.txt +++ b/Documentation/x86/boot.txt @@ -1124,7 +1124,6 @@ The boot loader *must* fill out the following fields in bp, o hdr.code32_start o hdr.cmd_line_ptr - o hdr.cmdline_size o hdr.ramdisk_image (if applicable) o hdr.ramdisk_size (if applicable) -- cgit v1.2.3 From ebb09a96242156660ba585de4b783fd93cdcfb61 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 21 Apr 2015 10:38:32 -0300 Subject: [media] v4l2-pci-skeleton: drop format description The format description is now filled in by the core, so we can drop this in this skeleton driver. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/v4l2-pci-skeleton.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/video4linux/v4l2-pci-skeleton.c b/Documentation/video4linux/v4l2-pci-skeleton.c index 7bd1b975bfd2..9c80c090e92d 100644 --- a/Documentation/video4linux/v4l2-pci-skeleton.c +++ b/Documentation/video4linux/v4l2-pci-skeleton.c @@ -406,9 +406,7 @@ static int skeleton_enum_fmt_vid_cap(struct file *file, void *priv, if (f->index != 0) return -EINVAL; - strlcpy(f->description, "4:2:2, packed, YUYV", sizeof(f->description)); f->pixelformat = V4L2_PIX_FMT_YUYV; - f->flags = 0; return 0; } -- cgit v1.2.3 From e56f8ef05cf6e759a6094fabc537d984137dfd86 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 17 Apr 2015 05:29:08 -0300 Subject: [media] DocBook/media: fix typo Fix copy-and-paste errors: Source -> Process Signed-off-by: Hans Verkuil Acked-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/controls.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/controls.xml b/Documentation/DocBook/media/v4l/controls.xml index 4e9462f1ab4c..6e1667b5f3eb 100644 --- a/Documentation/DocBook/media/v4l/controls.xml +++ b/Documentation/DocBook/media/v4l/controls.xml @@ -4863,7 +4863,7 @@ interface and may change in the future. - The Image Source control class is intended for low-level control of + The Image Process control class is intended for low-level control of image processing functions. Unlike V4L2_CID_IMAGE_SOURCE_CLASS, the controls in this class affect processing the image, and do not control capturing @@ -4871,7 +4871,7 @@ interface and may change in the future. - Image Source Control IDs + Image Process Control IDs -- cgit v1.2.3 From 45339d5ba86acb3aaf18745a4b30be113a4c7429 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 23 Apr 2015 03:38:57 -0300 Subject: [media] DocBook/media: Improve G_EDID specification When using VIDIOC_G_EDID there is a special case where start_blocks and blocks are both set to 0. In that case the driver just has to set blocks to the total number of available blocks and return 0. Even though the drivers do this right and v4l2-compliance tests for it, it turned out not to be documented in the spec. Fix this. Signed-off-by: Hans Verkuil Reported-by: Mats Randgaard Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/vidioc-g-edid.xml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/vidioc-g-edid.xml b/Documentation/DocBook/media/v4l/vidioc-g-edid.xml index 6df40db4c8ba..e44340c1f9f7 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-edid.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-edid.xml @@ -82,6 +82,13 @@ If blocks have to be retrieved from the sink, then this call will block until they have been read. + If start_block and blocks are + both set to 0 when VIDIOC_G_EDID is called, then the driver will + set blocks to the total number of available EDID blocks + and it will return 0 without copying any data. This is an easy way to discover how many + EDID blocks there are. Note that if there are no EDID blocks available at all, then + the driver will set blocks to 0 and it returns 0. + To set the EDID blocks of a receiver the application has to fill in the pad, blocks and edid fields and set start_block to 0. It is not possible to set part of an EDID, -- cgit v1.2.3 From ffa415245b8666c44ddfb5ba1bca5b940828ecdd Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Thu, 16 Apr 2015 12:14:35 +0100 Subject: bus: arm-ccn: cpumask attribute This patch adds a "cpumask" attribute to CCN's event_source class sysfs directory. Perf user tool uses it to restrict events to the processor(s) enumerated in this mask. This patch provides a single CPU mask, making it possible to run "-a" perf session (previously it would request the same CCN event, for example cycle counter, on each available core and most likely fail). Initially the mask is set to the CPU that happened to probe the driver, but it will be changed when it is hot-un-plugged (active events are migrated to another CPU then). Example: Performance counter stats for 'system wide': CPU0 2968148 cycles CPU1 2236736 cycles CPU2 1797968 cycles CPU3 1831715 cycles CPU1 1201850868 ccn/cycles/ 1.001241383 seconds time elapsed Signed-off-by: Pawel Moll --- Documentation/arm/CCN.txt | 15 +++--- drivers/bus/arm-ccn.c | 128 ++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 126 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/arm/CCN.txt b/Documentation/arm/CCN.txt index 0632b3aad83e..3a7604874762 100644 --- a/Documentation/arm/CCN.txt +++ b/Documentation/arm/CCN.txt @@ -33,6 +33,13 @@ directory, with first 8 configurable by user and additional Cycle counter is described by a "type" value 0xff and does not require any other settings. +The driver also provides a "cpumask" sysfs attribute, which contains +a single CPU ID, of the processor which will be used to handle all +the CCN PMU events. It is recommended that the user space tools +request the events on this processor (if not, the perf_event->cpu value +will be overwritten anyway). In case of this processor being offlined, +the events are migrated to another one and the attribute is updated. + Example of perf tool use: / # perf list | grep ccn @@ -41,12 +48,8 @@ Example of perf tool use: ccn/xp_valid_flit/ [Kernel PMU event] <...> -/ # perf stat -C 0 -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ +/ # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ sleep 1 The driver does not support sampling, therefore "perf record" will -not work. Also notice that only single cpu is being selected -("-C 0") - this is because perf framework does not support -"non-CPU related" counters (yet?) so system-wide session ("-a") -would try (and in most cases fail) to set up the same event -per each CPU. +not work. Per-task (without "-a") perf sessions are not supported. diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index 60397ec77ff7..3374dcb12f1e 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -166,13 +166,17 @@ struct arm_ccn_dt { struct hrtimer hrtimer; + cpumask_t cpu; + struct notifier_block cpu_nb; + struct pmu pmu; }; struct arm_ccn { struct device *dev; void __iomem *base; - unsigned irq_used:1; + unsigned int irq; + unsigned sbas_present:1; unsigned sbsx_present:1; @@ -521,6 +525,25 @@ static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { .attrs = arm_ccn_pmu_cmp_mask_attrs, }; +static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu); +} + +static struct device_attribute arm_ccn_pmu_cpumask_attr = + __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL); + +static struct attribute *arm_ccn_pmu_cpumask_attrs[] = { + &arm_ccn_pmu_cpumask_attr.attr, + NULL, +}; + +static struct attribute_group arm_ccn_pmu_cpumask_attr_group = { + .attrs = arm_ccn_pmu_cpumask_attrs, +}; /* * Default poll period is 10ms, which is way over the top anyway, @@ -542,6 +565,7 @@ static const struct attribute_group *arm_ccn_pmu_attr_groups[] = { &arm_ccn_pmu_events_attr_group, &arm_ccn_pmu_format_attr_group, &arm_ccn_pmu_cmp_mask_attr_group, + &arm_ccn_pmu_cpumask_attr_group, NULL }; @@ -642,6 +666,16 @@ static int arm_ccn_pmu_event_init(struct perf_event *event) dev_warn(ccn->dev, "Can't provide per-task data!\n"); return -EOPNOTSUPP; } + /* + * Many perf core operations (eg. events rotation) operate on a + * single CPU context. This is obvious for CPU PMUs, where one + * expects the same sets of events being observed on all CPUs, + * but can lead to issues for off-core PMUs, like CCN, where each + * event could be theoretically assigned to a different CPU. To + * mitigate this, we enforce CPU assignment to one, selected + * processor (the one described in the "cpumask" attribute). + */ + event->cpu = cpumask_first(&ccn->dt.cpu); node_xp = CCN_CONFIG_NODE(event->attr.config); type = CCN_CONFIG_TYPE(event->attr.config); @@ -835,9 +869,15 @@ static void arm_ccn_pmu_event_start(struct perf_event *event, int flags) arm_ccn_pmu_read_counter(ccn, hw->idx)); hw->state = 0; - if (!ccn->irq_used) - hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), - HRTIMER_MODE_REL); + /* + * Pin the timer, so that the overflows are handled by the chosen + * event->cpu (this is the same one as presented in "cpumask" + * attribute). + */ + if (!ccn->irq) + __hrtimer_start_range_ns(&ccn->dt.hrtimer, + arm_ccn_pmu_timer_period(), 0, + HRTIMER_MODE_REL_PINNED, 0); /* Set the DT bus input, engaging the counter */ arm_ccn_pmu_xp_dt_config(event, 1); @@ -852,7 +892,7 @@ static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags) /* Disable counting, setting the DT bus to pass-through mode */ arm_ccn_pmu_xp_dt_config(event, 0); - if (!ccn->irq_used) + if (!ccn->irq) hrtimer_cancel(&ccn->dt.hrtimer); /* Let the DT bus drain */ @@ -1079,12 +1119,39 @@ static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer) } +static int arm_ccn_pmu_cpu_notifier(struct notifier_block *nb, + unsigned long action, void *hcpu) +{ + struct arm_ccn_dt *dt = container_of(nb, struct arm_ccn_dt, cpu_nb); + struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); + unsigned int cpu = (long)hcpu; /* for (long) see kernel/cpu.c */ + unsigned int target; + + switch (action & ~CPU_TASKS_FROZEN) { + case CPU_DOWN_PREPARE: + if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) + break; + target = cpumask_any_but(cpu_online_mask, cpu); + if (target < 0) + break; + perf_pmu_migrate_context(&dt->pmu, cpu, target); + cpumask_set_cpu(target, &dt->cpu); + WARN_ON(irq_set_affinity(ccn->irq, &dt->cpu) != 0); + default: + break; + } + + return NOTIFY_OK; +} + + static DEFINE_IDA(arm_ccn_pmu_ida); static int arm_ccn_pmu_init(struct arm_ccn *ccn) { int i; char *name; + int err; /* Initialize DT subsystem */ ccn->dt.base = ccn->base + CCN_REGION_SIZE; @@ -1136,20 +1203,58 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn) }; /* No overflow interrupt? Have to use a timer instead. */ - if (!ccn->irq_used) { + if (!ccn->irq) { dev_info(ccn->dev, "No access to interrupts, using timer.\n"); hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; } - return perf_pmu_register(&ccn->dt.pmu, name, -1); + /* Pick one CPU which we will use to collect data from CCN... */ + cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu); + + /* + * ... and change the selection when it goes offline. Priority is + * picked to have a chance to migrate events before perf is notified. + */ + ccn->dt.cpu_nb.notifier_call = arm_ccn_pmu_cpu_notifier; + ccn->dt.cpu_nb.priority = CPU_PRI_PERF + 1, + err = register_cpu_notifier(&ccn->dt.cpu_nb); + if (err) + goto error_cpu_notifier; + + /* Also make sure that the overflow interrupt is handled by this CPU */ + if (ccn->irq) { + err = irq_set_affinity(ccn->irq, &ccn->dt.cpu); + if (err) { + dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); + goto error_set_affinity; + } + } + + err = perf_pmu_register(&ccn->dt.pmu, name, -1); + if (err) + goto error_pmu_register; + + return 0; + +error_pmu_register: +error_set_affinity: + unregister_cpu_notifier(&ccn->dt.cpu_nb); +error_cpu_notifier: + ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); + for (i = 0; i < ccn->num_xps; i++) + writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); + writel(0, ccn->dt.base + CCN_DT_PMCR); + return err; } static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn) { int i; + irq_set_affinity(ccn->irq, cpu_possible_mask); + unregister_cpu_notifier(&ccn->dt.cpu_nb); for (i = 0; i < ccn->num_xps; i++) writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); writel(0, ccn->dt.base + CCN_DT_PMCR); @@ -1285,6 +1390,7 @@ static int arm_ccn_probe(struct platform_device *pdev) { struct arm_ccn *ccn; struct resource *res; + unsigned int irq; int err; ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); @@ -1309,6 +1415,7 @@ static int arm_ccn_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res) return -EINVAL; + irq = res->start; /* Check if we can use the interrupt */ writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE, @@ -1318,13 +1425,12 @@ static int arm_ccn_probe(struct platform_device *pdev) /* Can set 'disable' bits, so can acknowledge interrupts */ writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE, ccn->base + CCN_MN_ERRINT_STATUS); - err = devm_request_irq(ccn->dev, res->start, - arm_ccn_irq_handler, 0, dev_name(ccn->dev), - ccn); + err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0, + dev_name(ccn->dev), ccn); if (err) return err; - ccn->irq_used = 1; + ccn->irq = irq; } -- cgit v1.2.3 From 8f06c51fac1ca4104b8b64872f310e28186aea42 Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Thu, 2 Apr 2015 14:01:06 +0100 Subject: bus: arm-ccn: Provide required event arguments Since 688d4dfcdd624192cbf03c08402e444d1d11f294 "perf tools: Support parsing parameterized events" the perf userspace tools understands "argument=?" syntax in the events file, making sure that required arguments are provided by the user and not defaulting to 0, causing confusion. This patch adds the required arguments lists for CCN events. Signed-off-by: Pawel Moll --- Documentation/arm/CCN.txt | 2 +- drivers/bus/arm-ccn.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/arm/CCN.txt b/Documentation/arm/CCN.txt index 3a7604874762..ffca443a19b4 100644 --- a/Documentation/arm/CCN.txt +++ b/Documentation/arm/CCN.txt @@ -45,7 +45,7 @@ Example of perf tool use: / # perf list | grep ccn ccn/cycles/ [Kernel PMU event] <...> - ccn/xp_valid_flit/ [Kernel PMU event] + ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event] <...> / # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c index 3374dcb12f1e..572360f1f493 100644 --- a/drivers/bus/arm-ccn.c +++ b/drivers/bus/arm-ccn.c @@ -340,6 +340,23 @@ static ssize_t arm_ccn_pmu_event_show(struct device *dev, if (event->mask) res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x", event->mask); + + /* Arguments required by an event */ + switch (event->type) { + case CCN_TYPE_CYCLES: + break; + case CCN_TYPE_XP: + res += snprintf(buf + res, PAGE_SIZE - res, + ",xp=?,port=?,vc=?,dir=?"); + if (event->event == CCN_EVENT_WATCHPOINT) + res += snprintf(buf + res, PAGE_SIZE - res, + ",cmp_l=?,cmp_h=?,mask=?"); + break; + default: + res += snprintf(buf + res, PAGE_SIZE - res, ",node=?"); + break; + } + res += snprintf(buf + res, PAGE_SIZE - res, "\n"); return res; -- cgit v1.2.3 From 0ce8cf2f31d661a27b7656e791acacb86eb58739 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 4 Mar 2015 20:01:13 -0600 Subject: Documentation: dt: add common bindings for hwspinlock This patch adds the generic common bindings used to represent a hwlock device and use/request locks in a device-tree build. Each hwspinlock provider should have the '#hwlock-cells' property, which represents the number of cells to be used for representing a specific hwspinlock. Client users shall use the property 'hwlocks' for requesting specific lock(s). Note that the document is named hwlock.txt deliberately to keep it a bit more generic. Cc: Rob Herring Signed-off-by: Suman Anna Reviewed-by: Bjorn Andersson Acked-by: Mark Rutland Signed-off-by: Ohad Ben-Cohen --- .../devicetree/bindings/hwlock/hwlock.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/hwlock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/hwlock/hwlock.txt b/Documentation/devicetree/bindings/hwlock/hwlock.txt new file mode 100644 index 000000000000..085d1f5c916a --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/hwlock.txt @@ -0,0 +1,59 @@ +Generic hwlock bindings +======================= + +Generic bindings that are common to all the hwlock platform specific driver +implementations. + +Please also look through the individual platform specific hwlock binding +documentations for identifying any additional properties specific to that +platform. + +hwlock providers: +================= + +Required properties: +- #hwlock-cells: Specifies the number of cells needed to represent a + specific lock. + +hwlock users: +============= + +Consumers that require specific hwlock(s) should specify them using the +property "hwlocks", and an optional "hwlock-names" property. + +Required properties: +- hwlocks: List of phandle to a hwlock provider node and an + associated hwlock args specifier as indicated by + #hwlock-cells. The list can have just a single hwlock + or multiple hwlocks, with each hwlock represented by + a phandle and a corresponding args specifier. + +Optional properties: +- hwlock-names: List of hwlock name strings defined in the same order + as the hwlocks, with one name per hwlock. Consumers can + use the hwlock-names to match and get a specific hwlock. + + +1. Example of a node using a single specific hwlock: + +The following example has a node requesting a hwlock in the bank defined by +the node hwlock1. hwlock1 is a hwlock provider with an argument specifier +of length 1. + + node { + ... + hwlocks = <&hwlock1 2>; + ... + }; + +2. Example of a node using multiple specific hwlocks: + +The following example has a node requesting two hwlocks, a hwlock within +the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another +hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2. + + node { + ... + hwlocks = <&hwlock1 2>, <&hwlock2 0 3>; + ... + }; -- cgit v1.2.3 From fb7737e949e31d8a71acee6bbb670f32dbd2a2c0 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 4 Mar 2015 20:01:14 -0600 Subject: hwspinlock/core: add device tree support This patch adds a new OF-friendly API of_hwspin_lock_get_id() for hwspinlock clients to use/request locks from a hwspinlock device instantiated through a device-tree blob. This new API can be used by hwspinlock clients to get the id for a specific lock using the phandle + args specifier, so that it can be requested using the available hwspin_lock_request_specific() API. Signed-off-by: Suman Anna Reviewed-by: Bjorn Andersson [small comment clarification] Signed-off-by: Ohad Ben-Cohen --- Documentation/hwspinlock.txt | 10 +++++ drivers/hwspinlock/hwspinlock_core.c | 79 ++++++++++++++++++++++++++++++++++++ include/linux/hwspinlock.h | 7 ++++ 3 files changed, 96 insertions(+) (limited to 'Documentation') diff --git a/Documentation/hwspinlock.txt b/Documentation/hwspinlock.txt index 62f7d4ea6e26..61c1ee98e59f 100644 --- a/Documentation/hwspinlock.txt +++ b/Documentation/hwspinlock.txt @@ -48,6 +48,16 @@ independent, drivers. ids for predefined purposes. Should be called from a process context (might sleep). + int of_hwspin_lock_get_id(struct device_node *np, int index); + - retrieve the global lock id for an OF phandle-based specific lock. + This function provides a means for DT users of a hwspinlock module + to get the global lock id of a specific hwspinlock, so that it can + be requested using the normal hwspin_lock_request_specific() API. + The function returns a lock id number on success, -EPROBE_DEFER if + the hwspinlock device is not yet registered with the core, or other + error values. + Should be called from a process context (might sleep). + int hwspin_lock_free(struct hwspinlock *hwlock); - free a previously-assigned hwspinlock; returns 0 on success, or an appropriate error code on failure (e.g. -EINVAL if the hwspinlock diff --git a/drivers/hwspinlock/hwspinlock_core.c b/drivers/hwspinlock/hwspinlock_core.c index 461a0d739d75..52f708bcf77f 100644 --- a/drivers/hwspinlock/hwspinlock_core.c +++ b/drivers/hwspinlock/hwspinlock_core.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "hwspinlock_internal.h" @@ -257,6 +258,84 @@ void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags) } EXPORT_SYMBOL_GPL(__hwspin_unlock); +/** + * of_hwspin_lock_simple_xlate - translate hwlock_spec to return a lock id + * @bank: the hwspinlock device bank + * @hwlock_spec: hwlock specifier as found in the device tree + * + * This is a simple translation function, suitable for hwspinlock platform + * drivers that only has a lock specifier length of 1. + * + * Returns a relative index of the lock within a specified bank on success, + * or -EINVAL on invalid specifier cell count. + */ +static inline int +of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) +{ + if (WARN_ON(hwlock_spec->args_count != 1)) + return -EINVAL; + + return hwlock_spec->args[0]; +} + +/** + * of_hwspin_lock_get_id() - get lock id for an OF phandle-based specific lock + * @np: device node from which to request the specific hwlock + * @index: index of the hwlock in the list of values + * + * This function provides a means for DT users of the hwspinlock module to + * get the global lock id of a specific hwspinlock using the phandle of the + * hwspinlock device, so that it can be requested using the normal + * hwspin_lock_request_specific() API. + * + * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock + * device is not yet registered, -EINVAL on invalid args specifier value or an + * appropriate error as returned from the OF parsing of the DT client node. + */ +int of_hwspin_lock_get_id(struct device_node *np, int index) +{ + struct of_phandle_args args; + struct hwspinlock *hwlock; + struct radix_tree_iter iter; + void **slot; + int id; + int ret; + + ret = of_parse_phandle_with_args(np, "hwlocks", "#hwlock-cells", index, + &args); + if (ret) + return ret; + + /* Find the hwspinlock device: we need its base_id */ + ret = -EPROBE_DEFER; + rcu_read_lock(); + radix_tree_for_each_slot(slot, &hwspinlock_tree, &iter, 0) { + hwlock = radix_tree_deref_slot(slot); + if (unlikely(!hwlock)) + continue; + + if (hwlock->bank->dev->of_node == args.np) { + ret = 0; + break; + } + } + rcu_read_unlock(); + if (ret < 0) + goto out; + + id = of_hwspin_lock_simple_xlate(&args); + if (id < 0 || id >= hwlock->bank->num_locks) { + ret = -EINVAL; + goto out; + } + id += hwlock->bank->base_id; + +out: + of_node_put(args.np); + return ret ? ret : id; +} +EXPORT_SYMBOL_GPL(of_hwspin_lock_get_id); + static int hwspin_lock_register_single(struct hwspinlock *hwlock, int id) { struct hwspinlock *tmp; diff --git a/include/linux/hwspinlock.h b/include/linux/hwspinlock.h index 3343298e40e8..859d673d98c8 100644 --- a/include/linux/hwspinlock.h +++ b/include/linux/hwspinlock.h @@ -26,6 +26,7 @@ #define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ struct device; +struct device_node; struct hwspinlock; struct hwspinlock_device; struct hwspinlock_ops; @@ -66,6 +67,7 @@ int hwspin_lock_unregister(struct hwspinlock_device *bank); struct hwspinlock *hwspin_lock_request(void); struct hwspinlock *hwspin_lock_request_specific(unsigned int id); int hwspin_lock_free(struct hwspinlock *hwlock); +int of_hwspin_lock_get_id(struct device_node *np, int index); int hwspin_lock_get_id(struct hwspinlock *hwlock); int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, unsigned long *); @@ -120,6 +122,11 @@ void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags) { } +static inline int of_hwspin_lock_get_id(struct device_node *np, int index) +{ + return 0; +} + static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) { return 0; -- cgit v1.2.3 From 67140ed1c9d518565e6e2b86ba761652eb9bf3c4 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 4 Mar 2015 20:01:15 -0600 Subject: Documentation: dt: add the omap hwspinlock bindings document HwSpinlock IP is present only on OMAP4 and other newer SoCs, which are all device-tree boot only. This patch adds the DT bindings information for OMAP hwspinlock module. Cc: Rob Herring Signed-off-by: Suman Anna Acked-by: Mark Rutland Signed-off-by: Ohad Ben-Cohen --- .../devicetree/bindings/hwlock/omap-hwspinlock.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt new file mode 100644 index 000000000000..2c9804f4f4ac --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/omap-hwspinlock.txt @@ -0,0 +1,26 @@ +OMAP4+ HwSpinlock Driver +======================== + +Required properties: +- compatible: Should be "ti,omap4-hwspinlock" for + OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs +- reg: Contains the hwspinlock module register address space + (base address and length) +- ti,hwmods: Name of the hwmod associated with the hwspinlock device +- #hwlock-cells: Should be 1. The OMAP hwspinlock users will use a + 0-indexed relative hwlock number as the argument + specifier value for requesting a specific hwspinlock + within a hwspinlock bank. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example: + +/* OMAP4 */ +hwspinlock: spinlock@4a0f6000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x4a0f6000 0x1000>; + ti,hwmods = "spinlock"; + #hwlock-cells = <1>; +}; -- cgit v1.2.3 From 5b5711f0f1aff1b25ee48da279de4f0c202f7a68 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 24 Mar 2015 10:11:04 -0700 Subject: DT: hwspinlock: Add binding documentation for Qualcomm hwmutex Add binding documentation for the Qualcomm Hardware Mutex. Signed-off-by: Bjorn Andersson Acked-by: Kumar Gala Reviewed-by: Andy Gross Reviewed-by: Jeffrey Hugo Signed-off-by: Ohad Ben-Cohen --- .../devicetree/bindings/hwlock/qcom-hwspinlock.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt new file mode 100644 index 000000000000..4563f524556b --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt @@ -0,0 +1,39 @@ +Qualcomm Hardware Mutex Block: + +The hardware block provides mutexes utilized between different processors on +the SoC as part of the communication protocol used by these processors. + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,sfpb-mutex", + "qcom,tcsr-mutex" + +- syscon: + Usage: required + Value type: + Definition: one cell containing: + syscon phandle + offset of the hwmutex block within the syscon + stride of the hwmutex registers + +- #hwlock-cells: + Usage: required + Value type: + Definition: must be 1, the specified cell represent the lock id + (hwlock standard property, see hwlock.txt) + +Example: + + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + hwlock@fd484000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; + + #hwlock-cells = <1>; + }; -- cgit v1.2.3 From 4749c3ef854e3a5d3dd3cc0ccd2dcb7e05d583bd Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Thu, 30 Apr 2015 12:12:00 +0200 Subject: net: sched: remove TC_MUNGED bits Not used. pedit sets TC_MUNGED when packet content was altered, but all the core does is unset MUNGED again and then set OK2MUNGE. And the latter isn't tested anywhere. So lets remove both TC_MUNGED and TC_OK2MUNGE. Signed-off-by: Florian Westphal Acked-by: Alexei Starovoitov Acked-by: Daniel Borkmann Acked-by: Jamal Hadi Salim Signed-off-by: David S. Miller --- Documentation/networking/tc-actions-env-rules.txt | 2 -- include/net/sch_generic.h | 2 -- include/uapi/linux/pkt_cls.h | 3 +++ net/sched/act_api.c | 5 ----- net/sched/act_pedit.c | 5 +---- 5 files changed, 4 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/tc-actions-env-rules.txt b/Documentation/networking/tc-actions-env-rules.txt index 70d6cf608251..95c71716b2e2 100644 --- a/Documentation/networking/tc-actions-env-rules.txt +++ b/Documentation/networking/tc-actions-env-rules.txt @@ -14,8 +14,6 @@ resets them for you, so invoke skb_act_clone() rather than skb_clone(). 2) If you munge any packet thou shalt call pskb_expand_head in the case someone else is referencing the skb. After that you "own" the skb. -You must also tell us if it is ok to munge the packet (TC_OK2MUNGE), -this way any action downstream can stomp on the packet. 3) Dropping packets you don't own is a no-no. You simply return TC_ACT_SHOT to the caller and they will drop it. diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 6d778efcfdfd..994b5a092f33 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -755,8 +755,6 @@ static inline struct sk_buff *skb_act_clone(struct sk_buff *skb, gfp_t gfp_mask, if (n) { n->tc_verd = SET_TC_VERD(n->tc_verd, 0); - n->tc_verd = CLR_TC_OK2MUNGE(n->tc_verd); - n->tc_verd = CLR_TC_MUNGED(n->tc_verd); } return n; } diff --git a/include/uapi/linux/pkt_cls.h b/include/uapi/linux/pkt_cls.h index bf08e76bf505..6810ca43a80a 100644 --- a/include/uapi/linux/pkt_cls.h +++ b/include/uapi/linux/pkt_cls.h @@ -35,6 +35,8 @@ bits 9,10,11: redirect counter - redirect TTL. Loop avoidance * * */ +#ifndef __KERNEL__ +/* backwards compat for userspace only */ #define TC_MUNGED _TC_MAKEMASK1(0) #define SET_TC_MUNGED(v) ( TC_MUNGED | (v & ~TC_MUNGED)) #define CLR_TC_MUNGED(v) ( v & ~TC_MUNGED) @@ -42,6 +44,7 @@ bits 9,10,11: redirect counter - redirect TTL. Loop avoidance #define TC_OK2MUNGE _TC_MAKEMASK1(1) #define SET_TC_OK2MUNGE(v) ( TC_OK2MUNGE | (v & ~TC_OK2MUNGE)) #define CLR_TC_OK2MUNGE(v) ( v & ~TC_OK2MUNGE) +#endif #define S_TC_VERD _TC_MAKE32(2) #define M_TC_VERD _TC_MAKEMASK(4,S_TC_VERD) diff --git a/net/sched/act_api.c b/net/sched/act_api.c index 3d43e4979f27..af427a3dbcba 100644 --- a/net/sched/act_api.c +++ b/net/sched/act_api.c @@ -392,11 +392,6 @@ int tcf_action_exec(struct sk_buff *skb, const struct list_head *actions, list_for_each_entry(a, actions, list) { repeat: ret = a->ops->act(skb, a, res); - if (TC_MUNGED & skb->tc_verd) { - /* copied already, allow trampling */ - skb->tc_verd = SET_TC_OK2MUNGE(skb->tc_verd); - skb->tc_verd = CLR_TC_MUNGED(skb->tc_verd); - } if (ret == TC_ACT_REPEAT) goto repeat; /* we need a ttl - JHS */ if (ret != TC_ACT_PIPE) diff --git a/net/sched/act_pedit.c b/net/sched/act_pedit.c index 59649d588d79..17e6d6669c7f 100644 --- a/net/sched/act_pedit.c +++ b/net/sched/act_pedit.c @@ -108,7 +108,7 @@ static int tcf_pedit(struct sk_buff *skb, const struct tc_action *a, struct tcf_result *res) { struct tcf_pedit *p = a->priv; - int i, munged = 0; + int i; unsigned int off; if (skb_unclone(skb, GFP_ATOMIC)) @@ -156,11 +156,8 @@ static int tcf_pedit(struct sk_buff *skb, const struct tc_action *a, *ptr = ((*ptr & tkey->mask) ^ tkey->val); if (ptr == &_data) skb_store_bits(skb, off + offset, ptr, 4); - munged++; } - if (munged) - skb->tc_verd = SET_TC_MUNGED(skb->tc_verd); goto done; } else WARN(1, "pedit BUG: index %d\n", p->tcf_index); -- cgit v1.2.3 From 82a584b7cd366511a22e37675b029cf2fb58e291 Mon Sep 17 00:00:00 2001 From: Tom Herbert Date: Wed, 29 Apr 2015 15:33:21 -0700 Subject: ipv6: Flow label state ranges This patch divides the IPv6 flow label space into two ranges: 0-7ffff is reserved for flow label manager, 80000-fffff will be used for creating auto flow labels (per RFC6438). This only affects how labels are set on transmit, it does not affect receive. This range split can be disbaled by systcl. Background: IPv6 flow labels have been an unmitigated disappointment thus far in the lifetime of IPv6. Support in HW devices to use them for ECMP is lacking, and OSes don't turn them on by default. If we had these we could get much better hashing in IPv6 networks without resorting to DPI, possibly eliminating some of the motivations to to define new encaps in UDP just for getting ECMP. Unfortunately, the initial specfications of IPv6 did not clarify how they are to be used. There has always been a vague concept that these can be used for ECMP, flow hashing, etc. and we do now have a good standard how to this in RFC6438. The problem is that flow labels can be either stateful or stateless (as in RFC6438), and we are presented with the possibility that a stateless label may collide with a stateful one. Attempts to split the flow label space were rejected in IETF. When we added support in Linux for RFC6438, we could not turn on flow labels by default due to this conflict. This patch splits the flow label space and should give us a path to enabling auto flow labels by default for all IPv6 packets. This is an API change so we need to consider compatibility with existing deployment. The stateful range is chosen to be the lower values in hopes that most uses would have chosen small numbers. Once we resolve the stateless/stateful issue, we can proceed to look at enabling RFC6438 flow labels by default (starting with scaled testing). Signed-off-by: Tom Herbert Signed-off-by: David S. Miller --- Documentation/networking/ip-sysctl.txt | 8 ++++++++ include/net/ipv6.h | 9 +++++++-- include/net/netns/ipv6.h | 1 + net/ipv6/af_inet6.c | 1 + net/ipv6/ip6_flowlabel.c | 4 ++++ net/ipv6/sysctl_net_ipv6.c | 8 ++++++++ 6 files changed, 29 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 071fb18dc57c..5095c63e50ed 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -1213,6 +1213,14 @@ auto_flowlabels - BOOLEAN FALSE: disabled Default: false +flowlabel_state_ranges - BOOLEAN + Split the flow label number space into two ranges. 0-0x7FFFF is + reserved for the IPv6 flow manager facility, 0x80000-0xFFFFF + is reserved for stateless flow labels as described in RFC6437. + TRUE: enabled + FALSE: disabled + Default: true + anycast_src_echo_reply - BOOLEAN Controls the use of anycast addresses as source addresses for ICMPv6 echo reply diff --git a/include/net/ipv6.h b/include/net/ipv6.h index eec8ad3c9843..53d25ef1699a 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -239,8 +239,10 @@ struct ip6_flowlabel { struct net *fl_net; }; -#define IPV6_FLOWINFO_MASK cpu_to_be32(0x0FFFFFFF) -#define IPV6_FLOWLABEL_MASK cpu_to_be32(0x000FFFFF) +#define IPV6_FLOWINFO_MASK cpu_to_be32(0x0FFFFFFF) +#define IPV6_FLOWLABEL_MASK cpu_to_be32(0x000FFFFF) +#define IPV6_FLOWLABEL_STATELESS_FLAG cpu_to_be32(0x00080000) + #define IPV6_TCLASS_MASK (IPV6_FLOWINFO_MASK & ~IPV6_FLOWLABEL_MASK) #define IPV6_TCLASS_SHIFT 20 @@ -719,6 +721,9 @@ static inline __be32 ip6_make_flowlabel(struct net *net, struct sk_buff *skb, hash ^= hash >> 12; flowlabel = (__force __be32)hash & IPV6_FLOWLABEL_MASK; + + if (net->ipv6.sysctl.flowlabel_state_ranges) + flowlabel |= IPV6_FLOWLABEL_STATELESS_FLAG; } return flowlabel; diff --git a/include/net/netns/ipv6.h b/include/net/netns/ipv6.h index d2527bf81142..8d93544a2d2b 100644 --- a/include/net/netns/ipv6.h +++ b/include/net/netns/ipv6.h @@ -34,6 +34,7 @@ struct netns_sysctl_ipv6 { int fwmark_reflect; int idgen_retries; int idgen_delay; + int flowlabel_state_ranges; }; struct netns_ipv6 { diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index eef63b394c5a..4632afa57e05 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -768,6 +768,7 @@ static int __net_init inet6_net_init(struct net *net) net->ipv6.sysctl.auto_flowlabels = 0; net->ipv6.sysctl.idgen_retries = 3; net->ipv6.sysctl.idgen_delay = 1 * HZ; + net->ipv6.sysctl.flowlabel_state_ranges = 1; atomic_set(&net->ipv6.fib6_sernum, 1); err = ipv6_init_mibs(net); diff --git a/net/ipv6/ip6_flowlabel.c b/net/ipv6/ip6_flowlabel.c index d491125011c4..1f9ebe3cbb4a 100644 --- a/net/ipv6/ip6_flowlabel.c +++ b/net/ipv6/ip6_flowlabel.c @@ -595,6 +595,10 @@ int ipv6_flowlabel_opt(struct sock *sk, char __user *optval, int optlen) if (freq.flr_label & ~IPV6_FLOWLABEL_MASK) return -EINVAL; + if (net->ipv6.sysctl.flowlabel_state_ranges && + (freq.flr_label & IPV6_FLOWLABEL_STATELESS_FLAG)) + return -ERANGE; + fl = fl_create(net, sk, &freq, optval, optlen, &err); if (!fl) return err; diff --git a/net/ipv6/sysctl_net_ipv6.c b/net/ipv6/sysctl_net_ipv6.c index abcc79f649b3..4e705add4f18 100644 --- a/net/ipv6/sysctl_net_ipv6.c +++ b/net/ipv6/sysctl_net_ipv6.c @@ -68,6 +68,13 @@ static struct ctl_table ipv6_table_template[] = { .mode = 0644, .proc_handler = proc_dointvec_jiffies, }, + { + .procname = "flowlabel_state_ranges", + .data = &init_net.ipv6.sysctl.flowlabel_state_ranges, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec + }, { } }; @@ -109,6 +116,7 @@ static int __net_init ipv6_sysctl_net_init(struct net *net) ipv6_table[4].data = &net->ipv6.sysctl.fwmark_reflect; ipv6_table[5].data = &net->ipv6.sysctl.idgen_retries; ipv6_table[6].data = &net->ipv6.sysctl.idgen_delay; + ipv6_table[7].data = &net->ipv6.sysctl.flowlabel_state_ranges; ipv6_route_table = ipv6_route_sysctl_init(net); if (!ipv6_route_table) -- cgit v1.2.3 From 5431b0fdadfec7aa61c916d6978544727a00b5fe Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 29 Apr 2015 13:53:21 +0200 Subject: ARM: tegra: Use lower-case hexadecimal digits For consistency with other device tree content, use lower-case hexadecimal digits in register region specifications. Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt | 2 +- arch/arm/boot/dts/tegra124.dtsi | 2 +- arch/arm/boot/dts/tegra20.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt index 23e1d3194174..41372d441131 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt @@ -29,7 +29,7 @@ Example: fuse@7000f800 { compatible = "nvidia,tegra20-efuse"; - reg = <0x7000F800 0x400>, + reg = <0x7000f800 0x400>, <0x70000000 0x400>; clocks = <&tegra_car TEGRA20_CLK_FUSE>; clock-names = "fuse"; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index cf01c818b8ea..0d9f9ae73149 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -300,7 +300,7 @@ apbmisc@0,70000800 { compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ + <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ }; pinmux: pinmux@0,70000868 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index adf6b048d0bb..f444b67f55c6 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -563,7 +563,7 @@ fuse@7000f800 { compatible = "nvidia,tegra20-efuse"; - reg = <0x7000F800 0x400>; + reg = <0x7000f800 0x400>; clocks = <&tegra_car TEGRA20_CLK_FUSE>; clock-names = "fuse"; resets = <&tegra_car 39>; -- cgit v1.2.3 From ee5d4df7298336a4c40140a1ce179e11ed179b03 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Sun, 3 May 2015 17:00:17 -0700 Subject: ASoC: tas571x: Add DT binding document Document the bindings for the soon-to-be-added tas571x driver. Signed-off-by: Kevin Cernekee Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/tas571x.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/tas571x.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/tas571x.txt b/Documentation/devicetree/bindings/sound/tas571x.txt new file mode 100644 index 000000000000..0ac31d8d5ac4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tas571x.txt @@ -0,0 +1,41 @@ +Texas Instruments TAS5711/TAS5717/TAS5719 stereo power amplifiers + +The codec is controlled through an I2C interface. It also has two other +signals that can be wired up to GPIOs: reset (strongly recommended), and +powerdown (optional). + +Required properties: + +- compatible: "ti,tas5711", "ti,tas5717", or "ti,tas5719" +- reg: The I2C address of the device +- #sound-dai-cells: must be equal to 0 + +Optional properties: + +- reset-gpios: GPIO specifier for the TAS571x's active low reset line +- pdn-gpios: GPIO specifier for the TAS571x's active low powerdown line +- clocks: clock phandle for the MCLK input +- clock-names: should be "mclk" +- AVDD-supply: regulator phandle for the AVDD supply (all chips) +- DVDD-supply: regulator phandle for the DVDD supply (all chips) +- HPVDD-supply: regulator phandle for the HPVDD supply (5717/5719) +- PVDD_AB-supply: regulator phandle for the PVDD_AB supply (5717/5719) +- PVDD_CD-supply: regulator phandle for the PVDD_CD supply (5717/5719) +- PVDD_A-supply: regulator phandle for the PVDD_A supply (5711) +- PVDD_B-supply: regulator phandle for the PVDD_B supply (5711) +- PVDD_C-supply: regulator phandle for the PVDD_C supply (5711) +- PVDD_D-supply: regulator phandle for the PVDD_D supply (5711) + +Example: + + tas5717: audio-codec@2a { + compatible = "ti,tas5717"; + reg = <0x2a>; + #sound-dai-cells = <0>; + + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + pdn-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + + clocks = <&clk_core CLK_I2S>; + clock-names = "mclk"; + }; -- cgit v1.2.3 From 405990c7e834913554482538321f16f457dda50e Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Thu, 12 Mar 2015 15:47:54 +0100 Subject: of: Document long-ram-code property in nvidia,tegra20-apbmisc Needed to properly decode the RAM code register. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index 47b205cc9cc7..4556359c5876 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -10,3 +10,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). -- cgit v1.2.3 From 596f74ec275b0ec608e9450c937c6a29ba91b352 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 27 Apr 2015 14:49:09 +0200 Subject: ASoC: rsnd: Use generic names for device nodes rcar_sound -> sound Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index f316ce1f214a..62ece4c59da7 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -47,7 +47,7 @@ DAI subnode properties: Example: -rcar_sound: rcar_sound@ec500000 { +rcar_sound: sound@ec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; reg = <0 0xec500000 0 0x1000>, /* SCU */ -- cgit v1.2.3 From 72faedae8bc3504ee4252cebf14737a23677cb8f Mon Sep 17 00:00:00 2001 From: Scott Mayhew Date: Wed, 29 Apr 2015 10:38:26 -0400 Subject: Documentation: remove overloads-avoided counter from knfsd-stats.txt The 'overloads-avoided' counter itself was removed several years ago by commit 78c210e (Revert "knfsd: avoid overloading the CPU scheduler with enormous load averages"). Signed-off-by: Scott Mayhew Signed-off-by: J. Bruce Fields --- Documentation/filesystems/nfs/knfsd-stats.txt | 44 +++------------------------ 1 file changed, 4 insertions(+), 40 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/nfs/knfsd-stats.txt b/Documentation/filesystems/nfs/knfsd-stats.txt index 64ced5149d37..1a5d82180b84 100644 --- a/Documentation/filesystems/nfs/knfsd-stats.txt +++ b/Documentation/filesystems/nfs/knfsd-stats.txt @@ -68,16 +68,10 @@ sockets-enqueued rate of change for this counter is zero; significantly non-zero values may indicate a performance limitation. - This can happen either because there are too few nfsd threads in the - thread pool for the NFS workload (the workload is thread-limited), - or because the NFS workload needs more CPU time than is available in - the thread pool (the workload is CPU-limited). In the former case, - configuring more nfsd threads will probably improve the performance - of the NFS workload. In the latter case, the sunrpc server layer is - already choosing not to wake idle nfsd threads because there are too - many nfsd threads which want to run but cannot, so configuring more - nfsd threads will make no difference whatsoever. The overloads-avoided - statistic (see below) can be used to distinguish these cases. + This can happen because there are too few nfsd threads in the thread + pool for the NFS workload (the workload is thread-limited), in which + case configuring more nfsd threads will probably improve the + performance of the NFS workload. threads-woken Counts how many times an idle nfsd thread is woken to try to @@ -88,36 +82,6 @@ threads-woken thing. The ideal rate of change for this counter will be close to but less than the rate of change of the packets-arrived counter. -overloads-avoided - Counts how many times the sunrpc server layer chose not to wake an - nfsd thread, despite the presence of idle nfsd threads, because - too many nfsd threads had been recently woken but could not get - enough CPU time to actually run. - - This statistic counts a circumstance where the sunrpc layer - heuristically avoids overloading the CPU scheduler with too many - runnable nfsd threads. The ideal rate of change for this counter - is zero. Significant non-zero values indicate that the workload - is CPU limited. Usually this is associated with heavy CPU usage - on all the CPUs in the nfsd thread pool. - - If a sustained large overloads-avoided rate is detected on a pool, - the top(1) utility should be used to check for the following - pattern of CPU usage on all the CPUs associated with the given - nfsd thread pool. - - - %us ~= 0 (as you're *NOT* running applications on your NFS server) - - - %wa ~= 0 - - - %id ~= 0 - - - %sy + %hi + %si ~= 100 - - If this pattern is seen, configuring more nfsd threads will *not* - improve the performance of the workload. If this patten is not - seen, then something more subtle is wrong. - threads-timedout Counts how many times an nfsd thread triggered an idle timeout, i.e. was not woken to handle any incoming network packets for -- cgit v1.2.3 From e0d4ffc367b443205c83220078728a5c49b3ad6e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 17 Mar 2015 15:08:26 -0700 Subject: leds: tlc591xx: Document binding for the TI 8/16 Channel i2c LED driver Document the binding for the TLC591xx LED driver. Signed-off-by: Andrew Lunn Tested-by: Imre Kaloz Cc: Matthew.Fatheree@belkin.com Acked-by: Jacek Anaszewski Signed-off-by: Bryan Wu --- .../devicetree/bindings/leds/leds-tlc591xx.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc591xx.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt b/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt new file mode 100644 index 000000000000..3bbbf7024411 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-tlc591xx.txt @@ -0,0 +1,40 @@ +LEDs connected to tlc59116 or tlc59108 + +Required properties +- compatible: should be "ti,tlc59116" or "ti,tlc59108" +- #address-cells: must be 1 +- #size-cells: must be 0 +- reg: typically 0x68 + +Each led is represented as a sub-node of the ti,tlc59116. +See Documentation/devicetree/bindings/leds/common.txt + +LED sub-node properties: +- reg: number of LED line, 0 to 15 or 0 to 7 +- label: (optional) name of LED +- linux,default-trigger : (optional) + +Examples: + +tlc59116@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59116"; + reg = <0x68>; + + wan@0 { + label = "wrt1900ac:amber:wan"; + reg = <0x0>; + }; + + 2g@2 { + label = "wrt1900ac:white:2g"; + reg = <0x2>; + }; + + alive@9 { + label = "wrt1900ac:green:alive"; + reg = <0x9>; + linux,default_trigger = "heartbeat"; + }; +}; -- cgit v1.2.3 From 2269fe093197ade0202128cbd08d8e1c253f1fcb Mon Sep 17 00:00:00 2001 From: Jacek Anaszewski Date: Tue, 28 Apr 2015 00:18:44 -0700 Subject: DT: Add documentation for the Skyworks AAT1290 This patch adds device tree binding documentation for 1.5A Step-Up Current Regulator for Flash LEDs. Signed-off-by: Jacek Anaszewski Acked-by: Kyungmin Park Acked-by: Sakari Ailus Cc: Richard Purdie Cc: devicetree@vger.kernel.org Signed-off-by: Bryan Wu --- .../devicetree/bindings/leds/leds-aat1290.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-aat1290.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-aat1290.txt b/Documentation/devicetree/bindings/leds/leds-aat1290.txt new file mode 100644 index 000000000000..ef88b9c53e37 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-aat1290.txt @@ -0,0 +1,41 @@ +* Skyworks Solutions, Inc. AAT1290 Current Regulator for Flash LEDs + +The device is controlled through two pins: FL_EN and EN_SET. The pins when, +asserted high, enable flash strobe and movie mode (max 1/2 of flash current) +respectively. + +Required properties: + +- compatible : Must be "skyworks,aat1290". +- flen-gpios : Must be device tree identifier of the flash device FL_EN pin. +- enset-gpios : Must be device tree identifier of the flash device EN_SET pin. + +A discrete LED element connected to the device must be represented by a child +node - see Documentation/devicetree/bindings/leds/common.txt. + +Required properties of the LED child node: +- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + Maximum flash LED supply current can be calculated using + following formula: I = 1A * 162kohm / Rset. +- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt + Maximum flash timeout can be calculated using following + formula: T = 8.82 * 10^9 * Ct. + +Optional properties of the LED child node: +- label : see Documentation/devicetree/bindings/leds/common.txt + +Example (by Ct = 220nF, Rset = 160kohm): + +aat1290 { + compatible = "skyworks,aat1290"; + flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; + enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; + + camera_flash: flash-led { + label = "aat1290-flash"; + led-max-microamp = <520833>; + flash-max-microamp = <1012500>; + flash-timeout-us = <1940000>; + }; +}; -- cgit v1.2.3 From 6e4b55e842a6cf3c5048b864c7a02f5a7a95ea3d Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Tue, 28 Apr 2015 09:50:49 -0700 Subject: leds: add DT binding for BCM6328 LED controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds device tree binding documentation for the Broadcom BCM6328 LED controller. Signed-off-by: Álvaro Fernández Rojas Signed-off-by: Jonas Gorski Acked-by: Jacek Anaszewski Signed-off-by: Bryan Wu --- .../devicetree/bindings/leds/leds-bcm6328.txt | 309 +++++++++++++++++++++ 1 file changed, 309 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-bcm6328.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-bcm6328.txt b/Documentation/devicetree/bindings/leds/leds-bcm6328.txt new file mode 100644 index 000000000000..f9e36adc0ebf --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-bcm6328.txt @@ -0,0 +1,309 @@ +LEDs connected to Broadcom BCM6328 controller + +This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. +In these SoCs it's possible to control LEDs both as GPIOs or by hardware. +However, on some devices there are Serial LEDs (LEDs connected to a 74x164 +controller), which can either be controlled by software (exporting the 74x164 +as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +by hardware using this driver. +Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and +exporting the 74x164 as spi-gpio prevents those LEDs to be hardware +controlled, so the only chance to keep them working is by using this driver. + +BCM6328 LED controller has a HWDIS register, which controls whether a LED +should be controlled by a hardware signal instead of the MODE register value, +with 0 meaning hardware control enabled and 1 hardware control disabled. This +is usually 1:1 for hardware to LED signals, but through the activity/link +registers you have some limited control over rerouting the LEDs (as +explained later in brcm,link-signal-sources). Even if a LED is hardware +controlled you are still able to make it blink or light it up if it isn't, +but you can't turn it off if the hardware decides to light it up. For this +reason, hardware controlled LEDs aren't registered as LED class devices. + +Required properties: + - compatible : should be "brcm,bcm6328-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6328 LED controller address and size. + +Optional properties: + - brcm,serial-leds : Boolean, enables Serial LEDs. + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6328-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 23 are valid). + +LED sub-node optional properties: + a) Optional properties for sub-nodes related to software controlled LEDs: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + - default-state : see + Documentation/devicetree/bindings/leds/leds-gpio.txt + - linux,default-trigger : see + Documentation/devicetree/bindings/leds/common.txt + + b) Optional properties for sub-nodes related to hardware controlled LEDs: + - brcm,hardware-controlled : Boolean, makes this LED hardware controlled. + Default : false + - brcm,link-signal-sources : An array of hardware link + signal sources. Up to four link hardware signals can get muxed into + these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may + be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs + 4 to 7. A signal can be muxed to more than one LED, and one LED can + have more than one source signal. + - brcm,activity-signal-sources : An array of hardware activity + signal sources. Up to four activity hardware signals can get muxed into + these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may + be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs + 4 to 7. A signal can be muxed to more than one LED, and one LED can + have more than one source signal. + +Examples: +Scenario 1 : BCM6328 with 4 EPHY LEDs + leds0: led-controller@10000800 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10000800 0x24>; + + alarm_red@2 { + reg = <2>; + active-low; + label = "red:alarm"; + }; + inet_green@3 { + reg = <3>; + active-low; + label = "green:inet"; + }; + power_green@4 { + reg = <4>; + active-low; + label = "green:power"; + default-state = "on"; + }; + ephy0_spd@17 { + reg = <17>; + brcm,hardware-controlled; + }; + ephy1_spd@18 { + reg = <18>; + brcm,hardware-controlled; + }; + ephy2_spd@19 { + reg = <19>; + brcm,hardware-controlled; + }; + ephy3_spd@20 { + reg = <20>; + brcm,hardware-controlled; + }; + }; + +Scenario 2 : BCM63268 with Serial/GPHY0 LEDs + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + brcm,serial-leds; + + gphy0_spd0@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + }; + gphy0_spd1@1 { + reg = <1>; + brcm,hardware-controlled; + brcm,link-signal-sources = <1>; + }; + inet_red@2 { + reg = <2>; + active-low; + label = "red:inet"; + }; + dsl_green@3 { + reg = <3>; + active-low; + label = "green:dsl"; + }; + usb_green@4 { + reg = <4>; + active-low; + label = "green:usb"; + }; + wps_green@7 { + reg = <7>; + active-low; + label = "green:wps"; + }; + inet_green@8 { + reg = <8>; + active-low; + label = "green:inet"; + }; + ephy0_act@9 { + reg = <9>; + brcm,hardware-controlled; + }; + ephy1_act@10 { + reg = <10>; + brcm,hardware-controlled; + }; + ephy2_act@11 { + reg = <11>; + brcm,hardware-controlled; + }; + gphy0_act@12 { + reg = <12>; + brcm,hardware-controlled; + }; + ephy0_spd@13 { + reg = <13>; + brcm,hardware-controlled; + }; + ephy1_spd@14 { + reg = <14>; + brcm,hardware-controlled; + }; + ephy2_spd@15 { + reg = <15>; + brcm,hardware-controlled; + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; + +Scenario 3 : BCM6362 with 1 LED for each EPHY + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + + usb@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + brcm,activity-signal-sources = <0>; + /* USB link/activity routed to USB LED */ + }; + inet@1 { + reg = <1>; + brcm,hardware-controlled; + brcm,activity-signal-sources = <1>; + /* INET activity routed to INET LED */ + }; + ephy0@4 { + reg = <4>; + brcm,hardware-controlled; + brcm,link-signal-sources = <4>; + /* EPHY0 link routed to EPHY0 LED */ + }; + ephy1@5 { + reg = <5>; + brcm,hardware-controlled; + brcm,link-signal-sources = <5>; + /* EPHY1 link routed to EPHY1 LED */ + }; + ephy2@6 { + reg = <6>; + brcm,hardware-controlled; + brcm,link-signal-sources = <6>; + /* EPHY2 link routed to EPHY2 LED */ + }; + ephy3@7 { + reg = <7>; + brcm,hardware-controlled; + brcm,link-signal-sources = <7>; + /* EPHY3 link routed to EPHY3 LED */ + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; + +Scenario 4 : BCM6362 with 1 LED for all EPHYs + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + + usb@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0 1>; + brcm,activity-signal-sources = <0 1>; + /* USB/INET link/activity routed to USB LED */ + }; + ephy@4 { + reg = <4>; + brcm,hardware-controlled; + brcm,link-signal-sources = <4 5 6 7>; + /* EPHY0/1/2/3 link routed to EPHY0 LED */ + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; + +Scenario 5 : BCM6362 with EPHY LEDs swapped + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + + usb@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + brcm,activity-signal-sources = <0 1>; + /* USB link/act and INET act routed to USB LED */ + }; + ephy0@4 { + reg = <4>; + brcm,hardware-controlled; + brcm,link-signal-sources = <7>; + /* EPHY3 link routed to EPHY0 LED */ + }; + ephy1@5 { + reg = <5>; + brcm,hardware-controlled; + brcm,link-signal-sources = <6>; + /* EPHY2 link routed to EPHY1 LED */ + }; + ephy2@6 { + reg = <6>; + brcm,hardware-controlled; + brcm,link-signal-sources = <5>; + /* EPHY1 link routed to EPHY2 LED */ + }; + ephy3@7 { + reg = <7>; + brcm,hardware-controlled; + brcm,link-signal-sources = <4>; + /* EPHY0 link routed to EPHY3 LED */ + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; -- cgit v1.2.3 From 6cd9e9f629f11b9412d4e9aa294c029dbb36b3cf Mon Sep 17 00:00:00 2001 From: Kapileshwar Singh Date: Wed, 18 Feb 2015 16:04:21 +0000 Subject: thermal: of: fix cooling device weights in device tree Currently you can specify the weight of the cooling device in the device tree but that information is not populated to the thermal_bind_params where the fair share governor expects it to be. The of thermal zone device doesn't have a thermal_bind_params structure and arguably it's better to pass the weight inside the thermal_instance as it is specific to the bind of a cooling device to a thermal zone parameter. Core thermal code is fixed to populate the weight in the instance from the thermal_bind_params, so platform code that was passing the weight inside the thermal_bind_params continue to work seamlessly. While we are at it, create a default value for the weight parameter for those thermal zones that currently don't define it and remove the hardcoded default in of-thermal. Cc: Zhang Rui Cc: "Rafael J. Wysocki" Cc: Len Brown Cc: Peter Feuerer Cc: Darren Hart Cc: Eduardo Valentin Cc: Kukjin Kim Cc: Durgadoss R Signed-off-by: Kapileshwar Singh Signed-off-by: Eduardo Valentin --- Documentation/thermal/sysfs-api.txt | 4 +++- drivers/acpi/thermal.c | 9 ++++++--- drivers/platform/x86/acerhdf.c | 3 ++- drivers/thermal/db8500_thermal.c | 2 +- drivers/thermal/fair_share.c | 2 +- drivers/thermal/imx_thermal.c | 3 ++- drivers/thermal/of-thermal.c | 5 +++-- drivers/thermal/thermal_core.c | 22 ++++++++++++++++------ drivers/thermal/thermal_core.h | 1 + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 3 ++- include/linux/thermal.h | 6 +++++- 11 files changed, 42 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index 87519cb379ee..7ec632ed9769 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -95,7 +95,7 @@ temperature) and throttle appropriate devices. 1.3 interface for binding a thermal zone device with a thermal cooling device 1.3.1 int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, int trip, struct thermal_cooling_device *cdev, - unsigned long upper, unsigned long lower); + unsigned long upper, unsigned long lower, unsigned int weight); This interface function bind a thermal cooling device to the certain trip point of a thermal zone device. @@ -110,6 +110,8 @@ temperature) and throttle appropriate devices. lower:the Minimum cooling state can be used for this trip point. THERMAL_NO_LIMIT means no lower limit, and the cooling device can be in cooling state 0. + weight: the influence of this cooling device in this thermal + zone. See 1.4.1 below for more information. 1.3.2 int thermal_zone_unbind_cooling_device(struct thermal_zone_device *tz, int trip, struct thermal_cooling_device *cdev); diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index d24fa1964eb8..6d4e44ea74ac 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -800,7 +800,8 @@ static int acpi_thermal_cooling_device_cb(struct thermal_zone_device *thermal, result = thermal_zone_bind_cooling_device (thermal, trip, cdev, - THERMAL_NO_LIMIT, THERMAL_NO_LIMIT); + THERMAL_NO_LIMIT, THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT); else result = thermal_zone_unbind_cooling_device @@ -824,7 +825,8 @@ static int acpi_thermal_cooling_device_cb(struct thermal_zone_device *thermal, if (bind) result = thermal_zone_bind_cooling_device (thermal, trip, cdev, - THERMAL_NO_LIMIT, THERMAL_NO_LIMIT); + THERMAL_NO_LIMIT, THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT); else result = thermal_zone_unbind_cooling_device (thermal, trip, cdev); @@ -841,7 +843,8 @@ static int acpi_thermal_cooling_device_cb(struct thermal_zone_device *thermal, result = thermal_zone_bind_cooling_device (thermal, THERMAL_TRIPS_NONE, cdev, THERMAL_NO_LIMIT, - THERMAL_NO_LIMIT); + THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT); else result = thermal_zone_unbind_cooling_device (thermal, THERMAL_TRIPS_NONE, diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c index 594c918b553d..1ef02daddb60 100644 --- a/drivers/platform/x86/acerhdf.c +++ b/drivers/platform/x86/acerhdf.c @@ -372,7 +372,8 @@ static int acerhdf_bind(struct thermal_zone_device *thermal, return 0; if (thermal_zone_bind_cooling_device(thermal, 0, cdev, - THERMAL_NO_LIMIT, THERMAL_NO_LIMIT)) { + THERMAL_NO_LIMIT, THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT)) { pr_err("error binding cooling dev\n"); return -EINVAL; } diff --git a/drivers/thermal/db8500_thermal.c b/drivers/thermal/db8500_thermal.c index 20adfbe27df1..2fb273c4baa9 100644 --- a/drivers/thermal/db8500_thermal.c +++ b/drivers/thermal/db8500_thermal.c @@ -76,7 +76,7 @@ static int db8500_cdev_bind(struct thermal_zone_device *thermal, upper = lower = i > max_state ? max_state : i; ret = thermal_zone_bind_cooling_device(thermal, i, cdev, - upper, lower); + upper, lower, THERMAL_WEIGHT_DEFAULT); dev_info(&cdev->device, "%s bind to %d: %d-%s\n", cdev->type, i, ret, ret ? "fail" : "succeed"); diff --git a/drivers/thermal/fair_share.c b/drivers/thermal/fair_share.c index 6e0a3fbfae86..c3b25187b467 100644 --- a/drivers/thermal/fair_share.c +++ b/drivers/thermal/fair_share.c @@ -109,7 +109,7 @@ static int fair_share_throttle(struct thermal_zone_device *tz, int trip) continue; instance->target = get_target_state(tz, cdev, - tzp->tbp[i].weight, cur_trip_level); + instance->weight, cur_trip_level); instance->cdev->updated = false; thermal_cdev_update(cdev); diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 2ccbc0788353..fde4c2876d14 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -306,7 +306,8 @@ static int imx_bind(struct thermal_zone_device *tz, ret = thermal_zone_bind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev, THERMAL_NO_LIMIT, - THERMAL_NO_LIMIT); + THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT); if (ret) { dev_err(&tz->device, "binding zone %s with cdev %s failed:%d\n", diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c index 668fb1bdea9e..c606b85ea9f4 100644 --- a/drivers/thermal/of-thermal.c +++ b/drivers/thermal/of-thermal.c @@ -227,7 +227,8 @@ static int of_thermal_bind(struct thermal_zone_device *thermal, ret = thermal_zone_bind_cooling_device(thermal, tbp->trip_id, cdev, tbp->max, - tbp->min); + tbp->min, + tbp->usage); if (ret) return ret; } @@ -581,7 +582,7 @@ static int thermal_of_populate_bind_params(struct device_node *np, u32 prop; /* Default weight. Usage is optional */ - __tbp->usage = 0; + __tbp->usage = THERMAL_WEIGHT_DEFAULT; ret = of_property_read_u32(np, "contribution", &prop); if (ret == 0) __tbp->usage = prop; diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index 4108db7e10c1..a6cb9b78b629 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -218,7 +218,8 @@ static void print_bind_err_msg(struct thermal_zone_device *tz, static void __bind(struct thermal_zone_device *tz, int mask, struct thermal_cooling_device *cdev, - unsigned long *limits) + unsigned long *limits, + unsigned int weight) { int i, ret; @@ -233,7 +234,8 @@ static void __bind(struct thermal_zone_device *tz, int mask, upper = limits[i * 2 + 1]; } ret = thermal_zone_bind_cooling_device(tz, i, cdev, - upper, lower); + upper, lower, + weight); if (ret) print_bind_err_msg(tz, cdev, ret); } @@ -280,7 +282,8 @@ static void bind_cdev(struct thermal_cooling_device *cdev) continue; tzp->tbp[i].cdev = cdev; __bind(pos, tzp->tbp[i].trip_mask, cdev, - tzp->tbp[i].binding_limits); + tzp->tbp[i].binding_limits, + tzp->tbp[i].weight); } } @@ -319,7 +322,8 @@ static void bind_tz(struct thermal_zone_device *tz) continue; tzp->tbp[i].cdev = pos; __bind(tz, tzp->tbp[i].trip_mask, pos, - tzp->tbp[i].binding_limits); + tzp->tbp[i].binding_limits, + tzp->tbp[i].weight); } } exit: @@ -713,7 +717,8 @@ passive_store(struct device *dev, struct device_attribute *attr, thermal_zone_bind_cooling_device(tz, THERMAL_TRIPS_NONE, cdev, THERMAL_NO_LIMIT, - THERMAL_NO_LIMIT); + THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT); } mutex_unlock(&thermal_list_lock); if (!tz->passive_delay) @@ -931,6 +936,9 @@ static const struct attribute_group *cooling_device_attr_groups[] = { * @lower: the Minimum cooling state can be used for this trip point. * THERMAL_NO_LIMIT means no lower limit, * and the cooling device can be in cooling state 0. + * @weight: The weight of the cooling device to be bound to the + * thermal zone. Use THERMAL_WEIGHT_DEFAULT for the + * default value * * This interface function bind a thermal cooling device to the certain trip * point of a thermal zone device. @@ -941,7 +949,8 @@ static const struct attribute_group *cooling_device_attr_groups[] = { int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, int trip, struct thermal_cooling_device *cdev, - unsigned long upper, unsigned long lower) + unsigned long upper, unsigned long lower, + unsigned int weight) { struct thermal_instance *dev; struct thermal_instance *pos; @@ -986,6 +995,7 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, dev->upper = upper; dev->lower = lower; dev->target = THERMAL_NO_TARGET; + dev->weight = weight; result = get_idr(&tz->idr, &tz->lock, &dev->id); if (result) diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h index 0531c752fbbb..7a465e9d456c 100644 --- a/drivers/thermal/thermal_core.h +++ b/drivers/thermal/thermal_core.h @@ -48,6 +48,7 @@ struct thermal_instance { struct device_attribute attr; struct list_head tz_node; /* node in tz->thermal_instances */ struct list_head cdev_node; /* node in cdev->thermal_instances */ + unsigned int weight; /* The weight of the cooling device */ }; int thermal_register_governor(struct thermal_governor *); diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c index a38c1756442a..cb45e729adb5 100644 --- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c @@ -146,7 +146,8 @@ static int ti_thermal_bind(struct thermal_zone_device *thermal, return thermal_zone_bind_cooling_device(thermal, 0, cdev, /* bind with min and max states defined by cpu_cooling */ THERMAL_NO_LIMIT, - THERMAL_NO_LIMIT); + THERMAL_NO_LIMIT, + THERMAL_WEIGHT_DEFAULT); } /* Unbind callback functions for thermal zone */ diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 5eac316490ea..00dacd4dfdce 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -40,6 +40,9 @@ /* No upper/lower limit requirement */ #define THERMAL_NO_LIMIT ((u32)~0) +/* Default weight of a bound cooling device */ +#define THERMAL_WEIGHT_DEFAULT 0 + /* Unit conversion macros */ #define KELVIN_TO_CELSIUS(t) (long)(((long)t-2732 >= 0) ? \ ((long)t-2732+5)/10 : ((long)t-2732-5)/10) @@ -323,7 +326,8 @@ void thermal_zone_device_unregister(struct thermal_zone_device *); int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int, struct thermal_cooling_device *, - unsigned long, unsigned long); + unsigned long, unsigned long, + unsigned int); int thermal_zone_unbind_cooling_device(struct thermal_zone_device *, int, struct thermal_cooling_device *); void thermal_zone_device_update(struct thermal_zone_device *); -- cgit v1.2.3 From db91651311c8b89978b17d27634582c28c33363e Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Wed, 18 Feb 2015 16:04:24 +0000 Subject: thermal: export weight to sysfs It's useful to have access to the weights for the cooling devices for thermal zones and change them if needed. Export them to sysfs. Cc: Zhang Rui Cc: Eduardo Valentin Signed-off-by: Javi Merino Signed-off-by: Eduardo Valentin --- Documentation/thermal/sysfs-api.txt | 15 +++++++++++++- drivers/thermal/thermal_core.c | 40 +++++++++++++++++++++++++++++++++++++ drivers/thermal/thermal_core.h | 2 ++ 3 files changed, 56 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index 7ec632ed9769..3625453ceef6 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -194,6 +194,8 @@ thermal_zone_bind_cooling_device/thermal_zone_unbind_cooling_device. /sys/class/thermal/thermal_zone[0-*]: |---cdev[0-*]: [0-*]th cooling device in current thermal zone |---cdev[0-*]_trip_point: Trip point that cdev[0-*] is associated with + |---cdev[0-*]_weight: Influence of the cooling device in + this thermal zone Besides the thermal zone device sysfs I/F and cooling device sysfs I/F, the generic thermal driver also creates a hwmon sysfs I/F for each _type_ @@ -267,6 +269,14 @@ cdev[0-*]_trip_point point. RO, Optional +cdev[0-*]_weight + The influence of cdev[0-*] in this thermal zone. This value + is relative to the rest of cooling devices in the thermal + zone. For example, if a cooling device has a weight double + than that of other, it's twice as effective in cooling the + thermal zone. + RW, Optional + passive Attribute is only present for zones in which the passive cooling policy is not supported by native thermal driver. Default is zero @@ -320,7 +330,8 @@ passive, active. If an ACPI thermal zone supports critical, passive, active[0] and active[1] at the same time, it may register itself as a thermal_zone_device (thermal_zone1) with 4 trip points in all. It has one processor and one fan, which are both registered as -thermal_cooling_device. +thermal_cooling_device. Both are considered to have the same +effectiveness in cooling the thermal zone. If the processor is listed in _PSL method, and the fan is listed in _AL0 method, the sys I/F structure will be built like this: @@ -342,8 +353,10 @@ method, the sys I/F structure will be built like this: |---trip_point_3_type: active1 |---cdev0: --->/sys/class/thermal/cooling_device0 |---cdev0_trip_point: 1 /* cdev0 can be used for passive */ + |---cdev0_weight: 1024 |---cdev1: --->/sys/class/thermal/cooling_device3 |---cdev1_trip_point: 2 /* cdev1 can be used for active[0]*/ + |---cdev1_weight: 1024 |cooling_device0: |---type: Processor diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index a6cb9b78b629..605d6919c1b6 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -922,6 +922,34 @@ static const struct attribute_group *cooling_device_attr_groups[] = { NULL, }; +static ssize_t +thermal_cooling_device_weight_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct thermal_instance *instance; + + instance = container_of(attr, struct thermal_instance, weight_attr); + + return sprintf(buf, "%d\n", instance->weight); +} + +static ssize_t +thermal_cooling_device_weight_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct thermal_instance *instance; + int ret, weight; + + ret = kstrtoint(buf, 0, &weight); + if (ret) + return ret; + + instance = container_of(attr, struct thermal_instance, weight_attr); + instance->weight = weight; + + return count; +} /* Device management */ /** @@ -1016,6 +1044,16 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, if (result) goto remove_symbol_link; + sprintf(dev->weight_attr_name, "cdev%d_weight", dev->id); + sysfs_attr_init(&dev->weight_attr.attr); + dev->weight_attr.attr.name = dev->weight_attr_name; + dev->weight_attr.attr.mode = S_IWUSR | S_IRUGO; + dev->weight_attr.show = thermal_cooling_device_weight_show; + dev->weight_attr.store = thermal_cooling_device_weight_store; + result = device_create_file(&tz->device, &dev->weight_attr); + if (result) + goto remove_trip_file; + mutex_lock(&tz->lock); mutex_lock(&cdev->lock); list_for_each_entry(pos, &tz->thermal_instances, tz_node) @@ -1033,6 +1071,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, if (!result) return 0; + device_remove_file(&tz->device, &dev->weight_attr); +remove_trip_file: device_remove_file(&tz->device, &dev->attr); remove_symbol_link: sysfs_remove_link(&tz->device.kobj, dev->name); diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h index 7a465e9d456c..faebe881f062 100644 --- a/drivers/thermal/thermal_core.h +++ b/drivers/thermal/thermal_core.h @@ -46,6 +46,8 @@ struct thermal_instance { unsigned long target; /* expected cooling state */ char attr_name[THERMAL_NAME_LENGTH]; struct device_attribute attr; + char weight_attr_name[THERMAL_NAME_LENGTH]; + struct device_attribute weight_attr; struct list_head tz_node; /* node in tz->thermal_instances */ struct list_head cdev_node; /* node in cdev->thermal_instances */ unsigned int weight; /* The weight of the cooling device */ -- cgit v1.2.3 From bcdcbbc71125c37195f97314f453ca9a3a4eb758 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Wed, 18 Feb 2015 16:04:25 +0000 Subject: thermal: fair_share: generalize the weight concept The fair share governor has the concept of weights, which is the influence of each cooling device in a thermal zone. The current implementation forces the weights of all cooling devices in a thermal zone to add up to a 100. This complicates setups, as you need to know in advance how many cooling devices you are going to have. If you bind a new cooling device, you have to modify all the other cooling devices weights, which is error prone. Furthermore, you can't specify a "default" weight for platforms since that default value depends on the number of cooling devices in the platform. This patch generalizes the concept of weight by allowing any number to be a "weight". Weights are now relative to each other. Platforms that don't specify weights get the same default value for all their cooling devices, so all their cdevs are considered to be equally influential. It's important to note that previous users of the weights don't need to alter the code: percentages continue to work as they used to. This patch just removes the constraint of all the weights in a thermal zone having to add up to a 100. If they do, you get the same behavior as before. If they don't, fair share now works for that platform. Cc: Zhang Rui Cc: Eduardo Valentin Cc: Durgadoss R Acked-by: Durgadoss R Signed-off-by: Javi Merino Signed-off-by: Eduardo Valentin --- Documentation/thermal/sysfs-api.txt | 12 +++++++++--- drivers/thermal/fair_share.c | 26 +++++++++++++++++++++----- include/linux/thermal.h | 9 ++++++--- 3 files changed, 36 insertions(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index 3625453ceef6..fc7dfe10778b 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -129,9 +129,15 @@ temperature) and throttle appropriate devices. This structure defines the following parameters that are used to bind a zone with a cooling device for a particular trip point. .cdev: The cooling device pointer - .weight: The 'influence' of a particular cooling device on this zone. - This is on a percentage scale. The sum of all these weights - (for a particular zone) cannot exceed 100. + .weight: The 'influence' of a particular cooling device on this + zone. This is relative to the rest of the cooling + devices. For example, if all cooling devices have a + weight of 1, then they all contribute the same. You can + use percentages if you want, but it's not mandatory. A + weight of 0 means that this cooling device doesn't + contribute to the cooling of this zone unless all cooling + devices have a weight of 0. If all weights are 0, then + they all contribute the same. .trip_mask:This is a bit mask that gives the binding relation between this thermal zone and cdev, for a particular trip point. If nth bit is set, then the cdev and thermal zone are bound diff --git a/drivers/thermal/fair_share.c b/drivers/thermal/fair_share.c index 692f4053f08b..c2c10bbe24d6 100644 --- a/drivers/thermal/fair_share.c +++ b/drivers/thermal/fair_share.c @@ -59,13 +59,13 @@ static int get_trip_level(struct thermal_zone_device *tz) } static long get_target_state(struct thermal_zone_device *tz, - struct thermal_cooling_device *cdev, int weight, int level) + struct thermal_cooling_device *cdev, int percentage, int level) { unsigned long max_state; cdev->ops->get_max_state(cdev, &max_state); - return (long)(weight * level * max_state) / (100 * tz->trips); + return (long)(percentage * level * max_state) / (100 * tz->trips); } /** @@ -77,7 +77,7 @@ static long get_target_state(struct thermal_zone_device *tz, * * Parameters used for Throttling: * P1. max_state: Maximum throttle state exposed by the cooling device. - * P2. weight[i]/100: + * P2. percentage[i]/100: * How 'effective' the 'i'th device is, in cooling the given zone. * P3. cur_trip_level/max_no_of_trips: * This describes the extent to which the devices should be throttled. @@ -89,16 +89,32 @@ static long get_target_state(struct thermal_zone_device *tz, static int fair_share_throttle(struct thermal_zone_device *tz, int trip) { struct thermal_instance *instance; + int total_weight = 0; + int total_instance = 0; int cur_trip_level = get_trip_level(tz); list_for_each_entry(instance, &tz->thermal_instances, tz_node) { + if (instance->trip != trip) + continue; + + total_weight += instance->weight; + total_instance++; + } + + list_for_each_entry(instance, &tz->thermal_instances, tz_node) { + int percentage; struct thermal_cooling_device *cdev = instance->cdev; if (instance->trip != trip) continue; - instance->target = get_target_state(tz, cdev, - instance->weight, cur_trip_level); + if (!total_weight) + percentage = 100 / total_instance; + else + percentage = (instance->weight * 100) / total_weight; + + instance->target = get_target_state(tz, cdev, percentage, + cur_trip_level); instance->cdev->updated = false; thermal_cdev_update(cdev); diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 00dacd4dfdce..bac0f52c7a1e 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -217,9 +217,12 @@ struct thermal_bind_params { /* * This is a measure of 'how effectively these devices can - * cool 'this' thermal zone. The shall be determined by platform - * characterization. This is on a 'percentage' scale. - * See Documentation/thermal/sysfs-api.txt for more information. + * cool 'this' thermal zone. It shall be determined by + * platform characterization. This value is relative to the + * rest of the weights so a cooling device whose weight is + * double that of another cooling device is twice as + * effective. See Documentation/thermal/sysfs-api.txt for more + * information. */ int weight; -- cgit v1.2.3 From c610afaa21d3c6e7b02040c8563ffc01c7fc0570 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 5 Feb 2015 19:12:56 +0200 Subject: thermal: Add QPNP PMIC temperature alarm driver Add support for the temperature alarm peripheral found inside Qualcomm plug-and-play (QPNP) PMIC chips. The temperature alarm peripheral outputs a pulse on an interrupt line whenever the thermal over temperature stage value changes. Register a thermal sensor. The temperature reported by this thermal sensor device should reflect the actual PMIC die temperature if an ADC is present on the given PMIC. If no ADC is present, then the reported temperature should be estimated from the over temperature stage value. Cc: David Collins Signed-off-by: Ivan T. Ivanov Signed-off-by: Eduardo Valentin --- .../bindings/thermal/qcom-spmi-temp-alarm.txt | 57 ++++ drivers/thermal/Kconfig | 11 + drivers/thermal/Makefile | 1 + drivers/thermal/qcom-spmi-temp-alarm.c | 309 +++++++++++++++++++++ 4 files changed, 378 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt create mode 100644 drivers/thermal/qcom-spmi-temp-alarm.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt b/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt new file mode 100644 index 000000000000..290ec06fa33a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt @@ -0,0 +1,57 @@ +Qualcomm QPNP PMIC Temperature Alarm + +QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips +that utilize the Qualcomm SPMI implementation. These peripherals provide an +interrupt signal and status register to identify high PMIC die temperature. + +Required properties: +- compatible: Should contain "qcom,spmi-temp-alarm". +- reg: Specifies the SPMI address and length of the controller's + registers. +- interrupts: PMIC temperature alarm interrupt. +- #thermal-sensor-cells: Should be 0. See thermal.txt for a description. + +Optional properties: +- io-channels: Should contain IIO channel specifier for the ADC channel, + which report chip die temperature. +- io-channel-names: Should contain "thermal". + +Example: + + pm8941_temp: thermal-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + + io-channels = <&pm8941_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + }; + + thermal-zones { + pm8941 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm8941_temp>; + + trips { + passive { + temperature = <1050000>; + hysteresis = <2000>; + type = "passive"; + }; + alert { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index af40db0df58e..30aee81e9f5b 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -299,4 +299,15 @@ depends on ARCH_STI && OF source "drivers/thermal/st/Kconfig" endmenu +config QCOM_SPMI_TEMP_ALARM + tristate "Qualcomm SPMI PMIC Temperature Alarm" + depends on OF && SPMI && IIO + select REGMAP_SPMI + help + This enables a thermal sysfs driver for Qualcomm plug-and-play (QPNP) + PMIC devices. It shows up in sysfs as a thermal sensor with multiple + trip points. The temperature reported by the thermal sensor reflects the + real time die temperature if an ADC is present or an estimate of the + temperature based upon the over temperature stage value. + endif diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index fa0dc486790f..1fe86652cfb6 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -22,6 +22,7 @@ thermal_sys-$(CONFIG_CPU_THERMAL) += cpu_cooling.o thermal_sys-$(CONFIG_CLOCK_THERMAL) += clock_cooling.o # platform thermal drivers +obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o obj-$(CONFIG_ROCKCHIP_THERMAL) += rockchip_thermal.o obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o diff --git a/drivers/thermal/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom-spmi-temp-alarm.c new file mode 100644 index 000000000000..c8d27b8fb9ec --- /dev/null +++ b/drivers/thermal/qcom-spmi-temp-alarm.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QPNP_TM_REG_TYPE 0x04 +#define QPNP_TM_REG_SUBTYPE 0x05 +#define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 +#define QPNP_TM_REG_ALARM_CTRL 0x46 + +#define QPNP_TM_TYPE 0x09 +#define QPNP_TM_SUBTYPE 0x08 + +#define STATUS_STAGE_MASK 0x03 + +#define SHUTDOWN_CTRL1_THRESHOLD_MASK 0x03 + +#define ALARM_CTRL_FORCE_ENABLE 0x80 + +/* + * Trip point values based on threshold control + * 0 = {105 C, 125 C, 145 C} + * 1 = {110 C, 130 C, 150 C} + * 2 = {115 C, 135 C, 155 C} + * 3 = {120 C, 140 C, 160 C} +*/ +#define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */ +#define TEMP_STAGE_HYSTERESIS 2000 + +#define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */ +#define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */ + +#define THRESH_MIN 0 + +/* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ +#define DEFAULT_TEMP 37000 + +struct qpnp_tm_chip { + struct regmap *map; + struct thermal_zone_device *tz_dev; + long temp; + unsigned int thresh; + unsigned int stage; + unsigned int prev_stage; + unsigned int base; + struct iio_channel *adc; +}; + +static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data) +{ + unsigned int val; + int ret; + + ret = regmap_read(chip->map, chip->base + addr, &val); + if (ret < 0) + return ret; + + *data = val; + return 0; +} + +static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) +{ + return regmap_write(chip->map, chip->base + addr, data); +} + +/* + * This function updates the internal temp value based on the + * current thermal stage and threshold as well as the previous stage + */ +static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) +{ + unsigned int stage; + int ret; + u8 reg = 0; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + stage = reg & STATUS_STAGE_MASK; + + if (stage > chip->stage) { + /* increasing stage, use lower bound */ + chip->temp = (stage - 1) * TEMP_STAGE_STEP + + chip->thresh * TEMP_THRESH_STEP + + TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN; + } else if (stage < chip->stage) { + /* decreasing stage, use upper bound */ + chip->temp = stage * TEMP_STAGE_STEP + + chip->thresh * TEMP_THRESH_STEP - + TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN; + } + + chip->stage = stage; + + return 0; +} + +static int qpnp_tm_get_temp(void *data, long *temp) +{ + struct qpnp_tm_chip *chip = data; + int ret, mili_celsius; + + if (!temp) + return -EINVAL; + + if (IS_ERR(chip->adc)) { + ret = qpnp_tm_update_temp_no_adc(chip); + if (ret < 0) + return ret; + } else { + ret = iio_read_channel_processed(chip->adc, &mili_celsius); + if (ret < 0) + return ret; + + chip->temp = mili_celsius; + } + + *temp = chip->temp < 0 ? 0 : chip->temp; + + return 0; +} + +static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = { + .get_temp = qpnp_tm_get_temp, +}; + +static irqreturn_t qpnp_tm_isr(int irq, void *data) +{ + struct qpnp_tm_chip *chip = data; + + thermal_zone_device_update(chip->tz_dev); + + return IRQ_HANDLED; +} + +/* + * This function initializes the internal temp value based on only the + * current thermal stage and threshold. Setup threshold control and + * disable shutdown override. + */ +static int qpnp_tm_init(struct qpnp_tm_chip *chip) +{ + int ret; + u8 reg; + + chip->thresh = THRESH_MIN; + chip->temp = DEFAULT_TEMP; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + chip->stage = reg & STATUS_STAGE_MASK; + + if (chip->stage) + chip->temp = chip->thresh * TEMP_THRESH_STEP + + (chip->stage - 1) * TEMP_STAGE_STEP + + TEMP_THRESH_MIN; + + /* + * Set threshold and disable software override of stage 2 and 3 + * shutdowns. + */ + reg = chip->thresh & SHUTDOWN_CTRL1_THRESHOLD_MASK; + ret = qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); + if (ret < 0) + return ret; + + /* Enable the thermal alarm PMIC module in always-on mode. */ + reg = ALARM_CTRL_FORCE_ENABLE; + ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg); + + return ret; +} + +static int qpnp_tm_probe(struct platform_device *pdev) +{ + struct qpnp_tm_chip *chip; + struct device_node *node; + u8 type, subtype; + u32 res[2]; + int ret, irq; + + node = pdev->dev.of_node; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, chip); + + chip->map = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->map) + return -ENXIO; + + ret = of_property_read_u32_array(node, "reg", res, 2); + if (ret < 0) + return ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + /* ADC based measurements are optional */ + chip->adc = iio_channel_get(&pdev->dev, "thermal"); + if (PTR_ERR(chip->adc) == -EPROBE_DEFER) + return PTR_ERR(chip->adc); + + chip->base = res[0]; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type); + if (ret < 0) { + dev_err(&pdev->dev, "could not read type\n"); + goto fail; + } + + ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype); + if (ret < 0) { + dev_err(&pdev->dev, "could not read subtype\n"); + goto fail; + } + + if (type != QPNP_TM_TYPE || subtype != QPNP_TM_SUBTYPE) { + dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", + type, subtype); + ret = -ENODEV; + goto fail; + } + + ret = qpnp_tm_init(chip); + if (ret < 0) { + dev_err(&pdev->dev, "init failed\n"); + goto fail; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr, + IRQF_ONESHOT, node->name, chip); + if (ret < 0) + goto fail; + + chip->tz_dev = thermal_zone_of_sensor_register(&pdev->dev, 0, chip, + &qpnp_tm_sensor_ops); + if (IS_ERR(chip->tz_dev)) { + dev_err(&pdev->dev, "failed to register sensor\n"); + ret = PTR_ERR(chip->tz_dev); + goto fail; + } + + return 0; + +fail: + if (!IS_ERR(chip->adc)) + iio_channel_release(chip->adc); + + return ret; +} + +static int qpnp_tm_remove(struct platform_device *pdev) +{ + struct qpnp_tm_chip *chip = dev_get_drvdata(&pdev->dev); + + thermal_zone_of_sensor_unregister(&pdev->dev, chip->tz_dev); + if (!IS_ERR(chip->adc)) + iio_channel_release(chip->adc); + + return 0; +} + +static const struct of_device_id qpnp_tm_match_table[] = { + { .compatible = "qcom,spmi-temp-alarm" }, + { } +}; +MODULE_DEVICE_TABLE(of, qpnp_tm_match_table); + +static struct platform_driver qpnp_tm_driver = { + .driver = { + .name = "spmi-temp-alarm", + .of_match_table = qpnp_tm_match_table, + }, + .probe = qpnp_tm_probe, + .remove = qpnp_tm_remove, +}; +module_platform_driver(qpnp_tm_driver); + +MODULE_ALIAS("platform:spmi-temp-alarm"); +MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From c36cf07176316fbe6a4bdbc23afcb0cbf7822bf2 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Thu, 26 Feb 2015 19:00:29 +0000 Subject: thermal: cpu_cooling: implement the power cooling device API Add a basic power model to the cpu cooling device to implement the power cooling device API. The power model uses the current frequency, current load and OPPs for the power calculations. The cpus must have registered their OPPs using the OPP library. Cc: Zhang Rui Cc: Eduardo Valentin Signed-off-by: Kapileshwar Singh Signed-off-by: Punit Agrawal Signed-off-by: Javi Merino Signed-off-by: Eduardo Valentin --- Documentation/thermal/cpu-cooling-api.txt | 156 +++++++- drivers/thermal/cpu_cooling.c | 583 +++++++++++++++++++++++++++++- include/linux/cpu_cooling.h | 39 ++ 3 files changed, 760 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/thermal/cpu-cooling-api.txt b/Documentation/thermal/cpu-cooling-api.txt index 753e47cc2e20..71653584cd03 100644 --- a/Documentation/thermal/cpu-cooling-api.txt +++ b/Documentation/thermal/cpu-cooling-api.txt @@ -36,8 +36,162 @@ the user. The registration APIs returns the cooling device pointer. np: pointer to the cooling device device tree node clip_cpus: cpumask of cpus where the frequency constraints will happen. -1.1.3 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) +1.1.3 struct thermal_cooling_device *cpufreq_power_cooling_register( + const struct cpumask *clip_cpus, u32 capacitance, + get_static_t plat_static_func) + +Similar to cpufreq_cooling_register, this function registers a cpufreq +cooling device. Using this function, the cooling device will +implement the power extensions by using a simple cpu power model. The +cpus must have registered their OPPs using the OPP library. + +The additional parameters are needed for the power model (See 2. Power +models). "capacitance" is the dynamic power coefficient (See 2.1 +Dynamic power). "plat_static_func" is a function to calculate the +static power consumed by these cpus (See 2.2 Static power). + +1.1.4 struct thermal_cooling_device *of_cpufreq_power_cooling_register( + struct device_node *np, const struct cpumask *clip_cpus, u32 capacitance, + get_static_t plat_static_func) + +Similar to cpufreq_power_cooling_register, this function register a +cpufreq cooling device with power extensions using the device tree +information supplied by the np parameter. + +1.1.5 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) This interface function unregisters the "thermal-cpufreq-%x" cooling device. cdev: Cooling device pointer which has to be unregistered. + +2. Power models + +The power API registration functions provide a simple power model for +CPUs. The current power is calculated as dynamic + (optionally) +static power. This power model requires that the operating-points of +the CPUs are registered using the kernel's opp library and the +`cpufreq_frequency_table` is assigned to the `struct device` of the +cpu. If you are using CONFIG_CPUFREQ_DT then the +`cpufreq_frequency_table` should already be assigned to the cpu +device. + +The `plat_static_func` parameter of `cpufreq_power_cooling_register()` +and `of_cpufreq_power_cooling_register()` is optional. If you don't +provide it, only dynamic power will be considered. + +2.1 Dynamic power + +The dynamic power consumption of a processor depends on many factors. +For a given processor implementation the primary factors are: + +- The time the processor spends running, consuming dynamic power, as + compared to the time in idle states where dynamic consumption is + negligible. Herein we refer to this as 'utilisation'. +- The voltage and frequency levels as a result of DVFS. The DVFS + level is a dominant factor governing power consumption. +- In running time the 'execution' behaviour (instruction types, memory + access patterns and so forth) causes, in most cases, a second order + variation. In pathological cases this variation can be significant, + but typically it is of a much lesser impact than the factors above. + +A high level dynamic power consumption model may then be represented as: + +Pdyn = f(run) * Voltage^2 * Frequency * Utilisation + +f(run) here represents the described execution behaviour and its +result has a units of Watts/Hz/Volt^2 (this often expressed in +mW/MHz/uVolt^2) + +The detailed behaviour for f(run) could be modelled on-line. However, +in practice, such an on-line model has dependencies on a number of +implementation specific processor support and characterisation +factors. Therefore, in initial implementation that contribution is +represented as a constant coefficient. This is a simplification +consistent with the relative contribution to overall power variation. + +In this simplified representation our model becomes: + +Pdyn = Capacitance * Voltage^2 * Frequency * Utilisation + +Where `capacitance` is a constant that represents an indicative +running time dynamic power coefficient in fundamental units of +mW/MHz/uVolt^2. Typical values for mobile CPUs might lie in range +from 100 to 500. For reference, the approximate values for the SoC in +ARM's Juno Development Platform are 530 for the Cortex-A57 cluster and +140 for the Cortex-A53 cluster. + + +2.2 Static power + +Static leakage power consumption depends on a number of factors. For a +given circuit implementation the primary factors are: + +- Time the circuit spends in each 'power state' +- Temperature +- Operating voltage +- Process grade + +The time the circuit spends in each 'power state' for a given +evaluation period at first order means OFF or ON. However, +'retention' states can also be supported that reduce power during +inactive periods without loss of context. + +Note: The visibility of state entries to the OS can vary, according to +platform specifics, and this can then impact the accuracy of a model +based on OS state information alone. It might be possible in some +cases to extract more accurate information from system resources. + +The temperature, operating voltage and process 'grade' (slow to fast) +of the circuit are all significant factors in static leakage power +consumption. All of these have complex relationships to static power. + +Circuit implementation specific factors include the chosen silicon +process as well as the type, number and size of transistors in both +the logic gates and any RAM elements included. + +The static power consumption modelling must take into account the +power managed regions that are implemented. Taking the example of an +ARM processor cluster, the modelling would take into account whether +each CPU can be powered OFF separately or if only a single power +region is implemented for the complete cluster. + +In one view, there are others, a static power consumption model can +then start from a set of reference values for each power managed +region (e.g. CPU, Cluster/L2) in each state (e.g. ON, OFF) at an +arbitrary process grade, voltage and temperature point. These values +are then scaled for all of the following: the time in each state, the +process grade, the current temperature and the operating voltage. +However, since both implementation specific and complex relationships +dominate the estimate, the appropriate interface to the model from the +cpu cooling device is to provide a function callback that calculates +the static power in this platform. When registering the cpu cooling +device pass a function pointer that follows the `get_static_t` +prototype: + + int plat_get_static(cpumask_t *cpumask, int interval, + unsigned long voltage, u32 &power); + +`cpumask` is the cpumask of the cpus involved in the calculation. +`voltage` is the voltage at which they are operating. The function +should calculate the average static power for the last `interval` +milliseconds. It returns 0 on success, -E* on error. If it +succeeds, it should store the static power in `power`. Reading the +temperature of the cpus described by `cpumask` is left for +plat_get_static() to do as the platform knows best which thermal +sensor is closest to the cpu. + +If `plat_static_func` is NULL, static power is considered to be +negligible for this platform and only dynamic power is considered. + +The platform specific callback can then use any combination of tables +and/or equations to permute the estimated value. Process grade +information is not passed to the model since access to such data, from +on-chip measurement capability or manufacture time data, is platform +specific. + +Note: the significance of static power for CPUs in comparison to +dynamic power is highly dependent on implementation. Given the +potential complexity in implementation, the importance and accuracy of +its inclusion when using cpu cooling devices should be assessed on a +case by case basis. + diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c index f65f0d109fc8..ba23150c7bde 100644 --- a/drivers/thermal/cpu_cooling.c +++ b/drivers/thermal/cpu_cooling.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,19 @@ * ... */ +/** + * struct power_table - frequency to power conversion + * @frequency: frequency in KHz + * @power: power in mW + * + * This structure is built when the cooling device registers and helps + * in translating frequency to power and viceversa. + */ +struct power_table { + u32 frequency; + u32 power; +}; + /** * struct cpufreq_cooling_device - data for cooling device with cpufreq * @id: unique integer value corresponding to each cpufreq_cooling_device @@ -58,6 +72,15 @@ * cpufreq frequencies. * @allowed_cpus: all the cpus involved for this cpufreq_cooling_device. * @node: list_head to link all cpufreq_cooling_device together. + * @last_load: load measured by the latest call to cpufreq_get_actual_power() + * @time_in_idle: previous reading of the absolute time that this cpu was idle + * @time_in_idle_timestamp: wall time of the last invocation of + * get_cpu_idle_time_us() + * @dyn_power_table: array of struct power_table for frequency to power + * conversion, sorted in ascending order. + * @dyn_power_table_entries: number of entries in the @dyn_power_table array + * @cpu_dev: the first cpu_device from @allowed_cpus that has OPPs registered + * @plat_get_static_power: callback to calculate the static power * * This structure is required for keeping information of each registered * cpufreq_cooling_device. @@ -71,6 +94,13 @@ struct cpufreq_cooling_device { unsigned int *freq_table; /* In descending order */ struct cpumask allowed_cpus; struct list_head node; + u32 last_load; + u64 *time_in_idle; + u64 *time_in_idle_timestamp; + struct power_table *dyn_power_table; + int dyn_power_table_entries; + struct device *cpu_dev; + get_static_t plat_get_static_power; }; static DEFINE_IDR(cpufreq_idr); static DEFINE_MUTEX(cooling_cpufreq_lock); @@ -167,6 +197,39 @@ unsigned long cpufreq_cooling_get_level(unsigned int cpu, unsigned int freq) } EXPORT_SYMBOL_GPL(cpufreq_cooling_get_level); +static void update_cpu_device(int cpu) +{ + struct cpufreq_cooling_device *cpufreq_dev; + + mutex_lock(&cooling_cpufreq_lock); + list_for_each_entry(cpufreq_dev, &cpufreq_dev_list, node) { + if (cpumask_test_cpu(cpu, &cpufreq_dev->allowed_cpus)) { + cpufreq_dev->cpu_dev = get_cpu_device(cpu); + if (!cpufreq_dev->cpu_dev) { + dev_warn(&cpufreq_dev->cool_dev->device, + "No cpu device for new policy cpu %d\n", + cpu); + } + break; + } + } + mutex_unlock(&cooling_cpufreq_lock); +} + +static void remove_cpu_device(int cpu) +{ + struct cpufreq_cooling_device *cpufreq_dev; + + mutex_lock(&cooling_cpufreq_lock); + list_for_each_entry(cpufreq_dev, &cpufreq_dev_list, node) { + if (cpumask_test_cpu(cpu, &cpufreq_dev->allowed_cpus)) { + cpufreq_dev->cpu_dev = NULL; + break; + } + } + mutex_unlock(&cooling_cpufreq_lock); +} + /** * cpufreq_thermal_notifier - notifier callback for cpufreq policy change. * @nb: struct notifier_block * with callback info. @@ -186,23 +249,240 @@ static int cpufreq_thermal_notifier(struct notifier_block *nb, unsigned long max_freq = 0; struct cpufreq_cooling_device *cpufreq_dev; - if (event != CPUFREQ_ADJUST) - return 0; + switch (event) { - mutex_lock(&cooling_cpufreq_lock); - list_for_each_entry(cpufreq_dev, &cpufreq_dev_list, node) { - if (!cpumask_test_cpu(policy->cpu, - &cpufreq_dev->allowed_cpus)) + case CPUFREQ_ADJUST: + mutex_lock(&cooling_cpufreq_lock); + list_for_each_entry(cpufreq_dev, &cpufreq_dev_list, node) { + if (!cpumask_test_cpu(policy->cpu, + &cpufreq_dev->allowed_cpus)) + continue; + + max_freq = cpufreq_dev->cpufreq_val; + + if (policy->max != max_freq) + cpufreq_verify_within_limits(policy, 0, + max_freq); + } + mutex_unlock(&cooling_cpufreq_lock); + break; + + case CPUFREQ_CREATE_POLICY: + update_cpu_device(policy->cpu); + break; + case CPUFREQ_REMOVE_POLICY: + remove_cpu_device(policy->cpu); + break; + default: + return NOTIFY_DONE; + } + + return NOTIFY_OK; +} + +/** + * build_dyn_power_table() - create a dynamic power to frequency table + * @cpufreq_device: the cpufreq cooling device in which to store the table + * @capacitance: dynamic power coefficient for these cpus + * + * Build a dynamic power to frequency table for this cpu and store it + * in @cpufreq_device. This table will be used in cpu_power_to_freq() and + * cpu_freq_to_power() to convert between power and frequency + * efficiently. Power is stored in mW, frequency in KHz. The + * resulting table is in ascending order. + * + * Return: 0 on success, -E* on error. + */ +static int build_dyn_power_table(struct cpufreq_cooling_device *cpufreq_device, + u32 capacitance) +{ + struct power_table *power_table; + struct dev_pm_opp *opp; + struct device *dev = NULL; + int num_opps = 0, cpu, i, ret = 0; + unsigned long freq; + + rcu_read_lock(); + + for_each_cpu(cpu, &cpufreq_device->allowed_cpus) { + dev = get_cpu_device(cpu); + if (!dev) { + dev_warn(&cpufreq_device->cool_dev->device, + "No cpu device for cpu %d\n", cpu); continue; + } - max_freq = cpufreq_dev->cpufreq_val; + num_opps = dev_pm_opp_get_opp_count(dev); + if (num_opps > 0) { + break; + } else if (num_opps < 0) { + ret = num_opps; + goto unlock; + } + } - if (policy->max != max_freq) - cpufreq_verify_within_limits(policy, 0, max_freq); + if (num_opps == 0) { + ret = -EINVAL; + goto unlock; } - mutex_unlock(&cooling_cpufreq_lock); - return 0; + power_table = kcalloc(num_opps, sizeof(*power_table), GFP_KERNEL); + + for (freq = 0, i = 0; + opp = dev_pm_opp_find_freq_ceil(dev, &freq), !IS_ERR(opp); + freq++, i++) { + u32 freq_mhz, voltage_mv; + u64 power; + + freq_mhz = freq / 1000000; + voltage_mv = dev_pm_opp_get_voltage(opp) / 1000; + + /* + * Do the multiplication with MHz and millivolt so as + * to not overflow. + */ + power = (u64)capacitance * freq_mhz * voltage_mv * voltage_mv; + do_div(power, 1000000000); + + /* frequency is stored in power_table in KHz */ + power_table[i].frequency = freq / 1000; + + /* power is stored in mW */ + power_table[i].power = power; + } + + if (i == 0) { + ret = PTR_ERR(opp); + goto unlock; + } + + cpufreq_device->cpu_dev = dev; + cpufreq_device->dyn_power_table = power_table; + cpufreq_device->dyn_power_table_entries = i; + +unlock: + rcu_read_unlock(); + return ret; +} + +static u32 cpu_freq_to_power(struct cpufreq_cooling_device *cpufreq_device, + u32 freq) +{ + int i; + struct power_table *pt = cpufreq_device->dyn_power_table; + + for (i = 1; i < cpufreq_device->dyn_power_table_entries; i++) + if (freq < pt[i].frequency) + break; + + return pt[i - 1].power; +} + +static u32 cpu_power_to_freq(struct cpufreq_cooling_device *cpufreq_device, + u32 power) +{ + int i; + struct power_table *pt = cpufreq_device->dyn_power_table; + + for (i = 1; i < cpufreq_device->dyn_power_table_entries; i++) + if (power < pt[i].power) + break; + + return pt[i - 1].frequency; +} + +/** + * get_load() - get load for a cpu since last updated + * @cpufreq_device: &struct cpufreq_cooling_device for this cpu + * @cpu: cpu number + * + * Return: The average load of cpu @cpu in percentage since this + * function was last called. + */ +static u32 get_load(struct cpufreq_cooling_device *cpufreq_device, int cpu) +{ + u32 load; + u64 now, now_idle, delta_time, delta_idle; + + now_idle = get_cpu_idle_time(cpu, &now, 0); + delta_idle = now_idle - cpufreq_device->time_in_idle[cpu]; + delta_time = now - cpufreq_device->time_in_idle_timestamp[cpu]; + + if (delta_time <= delta_idle) + load = 0; + else + load = div64_u64(100 * (delta_time - delta_idle), delta_time); + + cpufreq_device->time_in_idle[cpu] = now_idle; + cpufreq_device->time_in_idle_timestamp[cpu] = now; + + return load; +} + +/** + * get_static_power() - calculate the static power consumed by the cpus + * @cpufreq_device: struct &cpufreq_cooling_device for this cpu cdev + * @tz: thermal zone device in which we're operating + * @freq: frequency in KHz + * @power: pointer in which to store the calculated static power + * + * Calculate the static power consumed by the cpus described by + * @cpu_actor running at frequency @freq. This function relies on a + * platform specific function that should have been provided when the + * actor was registered. If it wasn't, the static power is assumed to + * be negligible. The calculated static power is stored in @power. + * + * Return: 0 on success, -E* on failure. + */ +static int get_static_power(struct cpufreq_cooling_device *cpufreq_device, + struct thermal_zone_device *tz, unsigned long freq, + u32 *power) +{ + struct dev_pm_opp *opp; + unsigned long voltage; + struct cpumask *cpumask = &cpufreq_device->allowed_cpus; + unsigned long freq_hz = freq * 1000; + + if (!cpufreq_device->plat_get_static_power || + !cpufreq_device->cpu_dev) { + *power = 0; + return 0; + } + + rcu_read_lock(); + + opp = dev_pm_opp_find_freq_exact(cpufreq_device->cpu_dev, freq_hz, + true); + voltage = dev_pm_opp_get_voltage(opp); + + rcu_read_unlock(); + + if (voltage == 0) { + dev_warn_ratelimited(cpufreq_device->cpu_dev, + "Failed to get voltage for frequency %lu: %ld\n", + freq_hz, IS_ERR(opp) ? PTR_ERR(opp) : 0); + return -EINVAL; + } + + return cpufreq_device->plat_get_static_power(cpumask, tz->passive_delay, + voltage, power); +} + +/** + * get_dynamic_power() - calculate the dynamic power + * @cpufreq_device: &cpufreq_cooling_device for this cdev + * @freq: current frequency + * + * Return: the dynamic power consumed by the cpus described by + * @cpufreq_device. + */ +static u32 get_dynamic_power(struct cpufreq_cooling_device *cpufreq_device, + unsigned long freq) +{ + u32 raw_cpu_power; + + raw_cpu_power = cpu_freq_to_power(cpufreq_device, freq); + return (raw_cpu_power * cpufreq_device->last_load) / 100; } /* cpufreq cooling device callback functions are defined below */ @@ -280,8 +560,169 @@ static int cpufreq_set_cur_state(struct thermal_cooling_device *cdev, return 0; } +/** + * cpufreq_get_requested_power() - get the current power + * @cdev: &thermal_cooling_device pointer + * @tz: a valid thermal zone device pointer + * @power: pointer in which to store the resulting power + * + * Calculate the current power consumption of the cpus in milliwatts + * and store it in @power. This function should actually calculate + * the requested power, but it's hard to get the frequency that + * cpufreq would have assigned if there were no thermal limits. + * Instead, we calculate the current power on the assumption that the + * immediate future will look like the immediate past. + * + * We use the current frequency and the average load since this + * function was last called. In reality, there could have been + * multiple opps since this function was last called and that affects + * the load calculation. While it's not perfectly accurate, this + * simplification is good enough and works. REVISIT this, as more + * complex code may be needed if experiments show that it's not + * accurate enough. + * + * Return: 0 on success, -E* if getting the static power failed. + */ +static int cpufreq_get_requested_power(struct thermal_cooling_device *cdev, + struct thermal_zone_device *tz, + u32 *power) +{ + unsigned long freq; + int cpu, ret; + u32 static_power, dynamic_power, total_load = 0; + struct cpufreq_cooling_device *cpufreq_device = cdev->devdata; + + freq = cpufreq_quick_get(cpumask_any(&cpufreq_device->allowed_cpus)); + + for_each_cpu(cpu, &cpufreq_device->allowed_cpus) { + u32 load; + + if (cpu_online(cpu)) + load = get_load(cpufreq_device, cpu); + else + load = 0; + + total_load += load; + } + + cpufreq_device->last_load = total_load; + + dynamic_power = get_dynamic_power(cpufreq_device, freq); + ret = get_static_power(cpufreq_device, tz, freq, &static_power); + if (ret) + return ret; + + *power = static_power + dynamic_power; + return 0; +} + +/** + * cpufreq_state2power() - convert a cpu cdev state to power consumed + * @cdev: &thermal_cooling_device pointer + * @tz: a valid thermal zone device pointer + * @state: cooling device state to be converted + * @power: pointer in which to store the resulting power + * + * Convert cooling device state @state into power consumption in + * milliwatts assuming 100% load. Store the calculated power in + * @power. + * + * Return: 0 on success, -EINVAL if the cooling device state could not + * be converted into a frequency or other -E* if there was an error + * when calculating the static power. + */ +static int cpufreq_state2power(struct thermal_cooling_device *cdev, + struct thermal_zone_device *tz, + unsigned long state, u32 *power) +{ + unsigned int freq, num_cpus; + cpumask_t cpumask; + u32 static_power, dynamic_power; + int ret; + struct cpufreq_cooling_device *cpufreq_device = cdev->devdata; + + cpumask_and(&cpumask, &cpufreq_device->allowed_cpus, cpu_online_mask); + num_cpus = cpumask_weight(&cpumask); + + /* None of our cpus are online, so no power */ + if (num_cpus == 0) { + *power = 0; + return 0; + } + + freq = cpufreq_device->freq_table[state]; + if (!freq) + return -EINVAL; + + dynamic_power = cpu_freq_to_power(cpufreq_device, freq) * num_cpus; + ret = get_static_power(cpufreq_device, tz, freq, &static_power); + if (ret) + return ret; + + *power = static_power + dynamic_power; + return 0; +} + +/** + * cpufreq_power2state() - convert power to a cooling device state + * @cdev: &thermal_cooling_device pointer + * @tz: a valid thermal zone device pointer + * @power: power in milliwatts to be converted + * @state: pointer in which to store the resulting state + * + * Calculate a cooling device state for the cpus described by @cdev + * that would allow them to consume at most @power mW and store it in + * @state. Note that this calculation depends on external factors + * such as the cpu load or the current static power. Calling this + * function with the same power as input can yield different cooling + * device states depending on those external factors. + * + * Return: 0 on success, -ENODEV if no cpus are online or -EINVAL if + * the calculated frequency could not be converted to a valid state. + * The latter should not happen unless the frequencies available to + * cpufreq have changed since the initialization of the cpu cooling + * device. + */ +static int cpufreq_power2state(struct thermal_cooling_device *cdev, + struct thermal_zone_device *tz, u32 power, + unsigned long *state) +{ + unsigned int cpu, cur_freq, target_freq; + int ret; + s32 dyn_power; + u32 last_load, normalised_power, static_power; + struct cpufreq_cooling_device *cpufreq_device = cdev->devdata; + + cpu = cpumask_any_and(&cpufreq_device->allowed_cpus, cpu_online_mask); + + /* None of our cpus are online */ + if (cpu >= nr_cpu_ids) + return -ENODEV; + + cur_freq = cpufreq_quick_get(cpu); + ret = get_static_power(cpufreq_device, tz, cur_freq, &static_power); + if (ret) + return ret; + + dyn_power = power - static_power; + dyn_power = dyn_power > 0 ? dyn_power : 0; + last_load = cpufreq_device->last_load ?: 1; + normalised_power = (dyn_power * 100) / last_load; + target_freq = cpu_power_to_freq(cpufreq_device, normalised_power); + + *state = cpufreq_cooling_get_level(cpu, target_freq); + if (*state == THERMAL_CSTATE_INVALID) { + dev_warn_ratelimited(&cdev->device, + "Failed to convert %dKHz for cpu %d into a cdev state\n", + target_freq, cpu); + return -EINVAL; + } + + return 0; +} + /* Bind cpufreq callbacks to thermal cooling device ops */ -static struct thermal_cooling_device_ops const cpufreq_cooling_ops = { +static struct thermal_cooling_device_ops cpufreq_cooling_ops = { .get_max_state = cpufreq_get_max_state, .get_cur_state = cpufreq_get_cur_state, .set_cur_state = cpufreq_set_cur_state, @@ -311,6 +752,9 @@ static unsigned int find_next_max(struct cpufreq_frequency_table *table, * @np: a valid struct device_node to the cooling device device tree node * @clip_cpus: cpumask of cpus where the frequency constraints will happen. * Normally this should be same as cpufreq policy->related_cpus. + * @capacitance: dynamic power coefficient for these cpus + * @plat_static_func: function to calculate the static power consumed by these + * cpus (optional) * * This interface function registers the cpufreq cooling device with the name * "thermal-cpufreq-%x". This api can support multiple instances of cpufreq @@ -322,13 +766,14 @@ static unsigned int find_next_max(struct cpufreq_frequency_table *table, */ static struct thermal_cooling_device * __cpufreq_cooling_register(struct device_node *np, - const struct cpumask *clip_cpus) + const struct cpumask *clip_cpus, u32 capacitance, + get_static_t plat_static_func) { struct thermal_cooling_device *cool_dev; struct cpufreq_cooling_device *cpufreq_dev; char dev_name[THERMAL_NAME_LENGTH]; struct cpufreq_frequency_table *pos, *table; - unsigned int freq, i; + unsigned int freq, i, num_cpus; int ret; table = cpufreq_frequency_get_table(cpumask_first(clip_cpus)); @@ -341,6 +786,23 @@ __cpufreq_cooling_register(struct device_node *np, if (!cpufreq_dev) return ERR_PTR(-ENOMEM); + num_cpus = cpumask_weight(clip_cpus); + cpufreq_dev->time_in_idle = kcalloc(num_cpus, + sizeof(*cpufreq_dev->time_in_idle), + GFP_KERNEL); + if (!cpufreq_dev->time_in_idle) { + cool_dev = ERR_PTR(-ENOMEM); + goto free_cdev; + } + + cpufreq_dev->time_in_idle_timestamp = + kcalloc(num_cpus, sizeof(*cpufreq_dev->time_in_idle_timestamp), + GFP_KERNEL); + if (!cpufreq_dev->time_in_idle_timestamp) { + cool_dev = ERR_PTR(-ENOMEM); + goto free_time_in_idle; + } + /* Find max levels */ cpufreq_for_each_valid_entry(pos, table) cpufreq_dev->max_level++; @@ -349,7 +811,7 @@ __cpufreq_cooling_register(struct device_node *np, cpufreq_dev->max_level, GFP_KERNEL); if (!cpufreq_dev->freq_table) { cool_dev = ERR_PTR(-ENOMEM); - goto free_cdev; + goto free_time_in_idle_timestamp; } /* max_level is an index, not a counter */ @@ -357,6 +819,20 @@ __cpufreq_cooling_register(struct device_node *np, cpumask_copy(&cpufreq_dev->allowed_cpus, clip_cpus); + if (capacitance) { + cpufreq_cooling_ops.get_requested_power = + cpufreq_get_requested_power; + cpufreq_cooling_ops.state2power = cpufreq_state2power; + cpufreq_cooling_ops.power2state = cpufreq_power2state; + cpufreq_dev->plat_get_static_power = plat_static_func; + + ret = build_dyn_power_table(cpufreq_dev, capacitance); + if (ret) { + cool_dev = ERR_PTR(ret); + goto free_table; + } + } + ret = get_idr(&cpufreq_idr, &cpufreq_dev->id); if (ret) { cool_dev = ERR_PTR(ret); @@ -402,6 +878,10 @@ remove_idr: release_idr(&cpufreq_idr, cpufreq_dev->id); free_table: kfree(cpufreq_dev->freq_table); +free_time_in_idle_timestamp: + kfree(cpufreq_dev->time_in_idle_timestamp); +free_time_in_idle: + kfree(cpufreq_dev->time_in_idle); free_cdev: kfree(cpufreq_dev); @@ -422,7 +902,7 @@ free_cdev: struct thermal_cooling_device * cpufreq_cooling_register(const struct cpumask *clip_cpus) { - return __cpufreq_cooling_register(NULL, clip_cpus); + return __cpufreq_cooling_register(NULL, clip_cpus, 0, NULL); } EXPORT_SYMBOL_GPL(cpufreq_cooling_register); @@ -446,10 +926,77 @@ of_cpufreq_cooling_register(struct device_node *np, if (!np) return ERR_PTR(-EINVAL); - return __cpufreq_cooling_register(np, clip_cpus); + return __cpufreq_cooling_register(np, clip_cpus, 0, NULL); } EXPORT_SYMBOL_GPL(of_cpufreq_cooling_register); +/** + * cpufreq_power_cooling_register() - create cpufreq cooling device with power extensions + * @clip_cpus: cpumask of cpus where the frequency constraints will happen + * @capacitance: dynamic power coefficient for these cpus + * @plat_static_func: function to calculate the static power consumed by these + * cpus (optional) + * + * This interface function registers the cpufreq cooling device with + * the name "thermal-cpufreq-%x". This api can support multiple + * instances of cpufreq cooling devices. Using this function, the + * cooling device will implement the power extensions by using a + * simple cpu power model. The cpus must have registered their OPPs + * using the OPP library. + * + * An optional @plat_static_func may be provided to calculate the + * static power consumed by these cpus. If the platform's static + * power consumption is unknown or negligible, make it NULL. + * + * Return: a valid struct thermal_cooling_device pointer on success, + * on failure, it returns a corresponding ERR_PTR(). + */ +struct thermal_cooling_device * +cpufreq_power_cooling_register(const struct cpumask *clip_cpus, u32 capacitance, + get_static_t plat_static_func) +{ + return __cpufreq_cooling_register(NULL, clip_cpus, capacitance, + plat_static_func); +} +EXPORT_SYMBOL(cpufreq_power_cooling_register); + +/** + * of_cpufreq_power_cooling_register() - create cpufreq cooling device with power extensions + * @np: a valid struct device_node to the cooling device device tree node + * @clip_cpus: cpumask of cpus where the frequency constraints will happen + * @capacitance: dynamic power coefficient for these cpus + * @plat_static_func: function to calculate the static power consumed by these + * cpus (optional) + * + * This interface function registers the cpufreq cooling device with + * the name "thermal-cpufreq-%x". This api can support multiple + * instances of cpufreq cooling devices. Using this API, the cpufreq + * cooling device will be linked to the device tree node provided. + * Using this function, the cooling device will implement the power + * extensions by using a simple cpu power model. The cpus must have + * registered their OPPs using the OPP library. + * + * An optional @plat_static_func may be provided to calculate the + * static power consumed by these cpus. If the platform's static + * power consumption is unknown or negligible, make it NULL. + * + * Return: a valid struct thermal_cooling_device pointer on success, + * on failure, it returns a corresponding ERR_PTR(). + */ +struct thermal_cooling_device * +of_cpufreq_power_cooling_register(struct device_node *np, + const struct cpumask *clip_cpus, + u32 capacitance, + get_static_t plat_static_func) +{ + if (!np) + return ERR_PTR(-EINVAL); + + return __cpufreq_cooling_register(np, clip_cpus, capacitance, + plat_static_func); +} +EXPORT_SYMBOL(of_cpufreq_power_cooling_register); + /** * cpufreq_cooling_unregister - function to remove cpufreq cooling device. * @cdev: thermal cooling device pointer. @@ -475,6 +1022,8 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) thermal_cooling_device_unregister(cpufreq_dev->cool_dev); release_idr(&cpufreq_idr, cpufreq_dev->id); + kfree(cpufreq_dev->time_in_idle_timestamp); + kfree(cpufreq_dev->time_in_idle); kfree(cpufreq_dev->freq_table); kfree(cpufreq_dev); } diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h index bd955270d5aa..c156f5082758 100644 --- a/include/linux/cpu_cooling.h +++ b/include/linux/cpu_cooling.h @@ -28,6 +28,9 @@ #include #include +typedef int (*get_static_t)(cpumask_t *cpumask, int interval, + unsigned long voltage, u32 *power); + #ifdef CONFIG_CPU_THERMAL /** * cpufreq_cooling_register - function to create cpufreq cooling device. @@ -36,6 +39,10 @@ struct thermal_cooling_device * cpufreq_cooling_register(const struct cpumask *clip_cpus); +struct thermal_cooling_device * +cpufreq_power_cooling_register(const struct cpumask *clip_cpus, + u32 capacitance, get_static_t plat_static_func); + /** * of_cpufreq_cooling_register - create cpufreq cooling device based on DT. * @np: a valid struct device_node to the cooling device device tree node. @@ -45,6 +52,12 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus); struct thermal_cooling_device * of_cpufreq_cooling_register(struct device_node *np, const struct cpumask *clip_cpus); + +struct thermal_cooling_device * +of_cpufreq_power_cooling_register(struct device_node *np, + const struct cpumask *clip_cpus, + u32 capacitance, + get_static_t plat_static_func); #else static inline struct thermal_cooling_device * of_cpufreq_cooling_register(struct device_node *np, @@ -52,6 +65,15 @@ of_cpufreq_cooling_register(struct device_node *np, { return ERR_PTR(-ENOSYS); } + +static inline struct thermal_cooling_device * +of_cpufreq_power_cooling_register(struct device_node *np, + const struct cpumask *clip_cpus, + u32 capacitance, + get_static_t plat_static_func) +{ + return NULL; +} #endif /** @@ -67,12 +89,29 @@ cpufreq_cooling_register(const struct cpumask *clip_cpus) { return ERR_PTR(-ENOSYS); } +static inline struct thermal_cooling_device * +cpufreq_power_cooling_register(const struct cpumask *clip_cpus, + u32 capacitance, get_static_t plat_static_func) +{ + return NULL; +} + static inline struct thermal_cooling_device * of_cpufreq_cooling_register(struct device_node *np, const struct cpumask *clip_cpus) { return ERR_PTR(-ENOSYS); } + +static inline struct thermal_cooling_device * +of_cpufreq_power_cooling_register(struct device_node *np, + const struct cpumask *clip_cpus, + u32 capacitance, + get_static_t plat_static_func) +{ + return NULL; +} + static inline void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) { -- cgit v1.2.3 From 6b775e870c56c59c3e16531ea2307b797395f9f7 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Mon, 2 Mar 2015 17:17:19 +0000 Subject: thermal: introduce the Power Allocator governor The power allocator governor is a thermal governor that controls system and device power allocation to control temperature. Conceptually, the implementation divides the sustainable power of a thermal zone among all the heat sources in that zone. This governor relies on "power actors", entities that represent heat sources. They can report current and maximum power consumption and can set a given maximum power consumption, usually via a cooling device. The governor uses a Proportional Integral Derivative (PID) controller driven by the temperature of the thermal zone. The output of the controller is a power budget that is then allocated to each power actor that can have bearing on the temperature we are trying to control. It decides how much power to give each cooling device based on the performance they are requesting. The PID controller ensures that the total power budget does not exceed the control temperature. Cc: Zhang Rui Cc: Eduardo Valentin Signed-off-by: Punit Agrawal Signed-off-by: Javi Merino Signed-off-by: Eduardo Valentin --- Documentation/thermal/power_allocator.txt | 247 ++++++++++++++ drivers/thermal/Kconfig | 15 + drivers/thermal/Makefile | 1 + drivers/thermal/power_allocator.c | 520 ++++++++++++++++++++++++++++++ drivers/thermal/thermal_core.c | 9 +- drivers/thermal/thermal_core.h | 8 + include/linux/thermal.h | 37 ++- 7 files changed, 830 insertions(+), 7 deletions(-) create mode 100644 Documentation/thermal/power_allocator.txt create mode 100644 drivers/thermal/power_allocator.c (limited to 'Documentation') diff --git a/Documentation/thermal/power_allocator.txt b/Documentation/thermal/power_allocator.txt new file mode 100644 index 000000000000..c3797b529991 --- /dev/null +++ b/Documentation/thermal/power_allocator.txt @@ -0,0 +1,247 @@ +Power allocator governor tunables +================================= + +Trip points +----------- + +The governor requires the following two passive trip points: + +1. "switch on" trip point: temperature above which the governor + control loop starts operating. This is the first passive trip + point of the thermal zone. + +2. "desired temperature" trip point: it should be higher than the + "switch on" trip point. This the target temperature the governor + is controlling for. This is the last passive trip point of the + thermal zone. + +PID Controller +-------------- + +The power allocator governor implements a +Proportional-Integral-Derivative controller (PID controller) with +temperature as the control input and power as the controlled output: + + P_max = k_p * e + k_i * err_integral + k_d * diff_err + sustainable_power + +where + e = desired_temperature - current_temperature + err_integral is the sum of previous errors + diff_err = e - previous_error + +It is similar to the one depicted below: + + k_d + | +current_temp | + | v + | +----------+ +---+ + | +----->| diff_err |-->| X |------+ + | | +----------+ +---+ | + | | | tdp actor + | | k_i | | get_requested_power() + | | | | | | | + | | | | | | | ... + v | v v v v v + +---+ | +-------+ +---+ +---+ +---+ +----------+ + | S |-------+----->| sum e |----->| X |--->| S |-->| S |-->|power | + +---+ | +-------+ +---+ +---+ +---+ |allocation| + ^ | ^ +----------+ + | | | | | + | | +---+ | | | + | +------->| X |-------------------+ v v + | +---+ granted performance +desired_temperature ^ + | + | + k_po/k_pu + +Sustainable power +----------------- + +An estimate of the sustainable dissipatable power (in mW) should be +provided while registering the thermal zone. This estimates the +sustained power that can be dissipated at the desired control +temperature. This is the maximum sustained power for allocation at +the desired maximum temperature. The actual sustained power can vary +for a number of reasons. The closed loop controller will take care of +variations such as environmental conditions, and some factors related +to the speed-grade of the silicon. `sustainable_power` is therefore +simply an estimate, and may be tuned to affect the aggressiveness of +the thermal ramp. For reference, the sustainable power of a 4" phone +is typically 2000mW, while on a 10" tablet is around 4500mW (may vary +depending on screen size). + +If you are using device tree, do add it as a property of the +thermal-zone. For example: + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2500>; + ... + +Instead, if the thermal zone is registered from the platform code, pass a +`thermal_zone_params` that has a `sustainable_power`. If no +`thermal_zone_params` were being passed, then something like below +will suffice: + + static const struct thermal_zone_params tz_params = { + .sustainable_power = 3500, + }; + +and then pass `tz_params` as the 5th parameter to +`thermal_zone_device_register()` + +k_po and k_pu +------------- + +The implementation of the PID controller in the power allocator +thermal governor allows the configuration of two proportional term +constants: `k_po` and `k_pu`. `k_po` is the proportional term +constant during temperature overshoot periods (current temperature is +above "desired temperature" trip point). Conversely, `k_pu` is the +proportional term constant during temperature undershoot periods +(current temperature below "desired temperature" trip point). + +These controls are intended as the primary mechanism for configuring +the permitted thermal "ramp" of the system. For instance, a lower +`k_pu` value will provide a slower ramp, at the cost of capping +available capacity at a low temperature. On the other hand, a high +value of `k_pu` will result in the governor granting very high power +whilst temperature is low, and may lead to temperature overshooting. + +The default value for `k_pu` is: + + 2 * sustainable_power / (desired_temperature - switch_on_temp) + +This means that at `switch_on_temp` the output of the controller's +proportional term will be 2 * `sustainable_power`. The default value +for `k_po` is: + + sustainable_power / (desired_temperature - switch_on_temp) + +Focusing on the proportional and feed forward values of the PID +controller equation we have: + + P_max = k_p * e + sustainable_power + +The proportional term is proportional to the difference between the +desired temperature and the current one. When the current temperature +is the desired one, then the proportional component is zero and +`P_max` = `sustainable_power`. That is, the system should operate in +thermal equilibrium under constant load. `sustainable_power` is only +an estimate, which is the reason for closed-loop control such as this. + +Expanding `k_pu` we get: + P_max = 2 * sustainable_power * (T_set - T) / (T_set - T_on) + + sustainable_power + +where + T_set is the desired temperature + T is the current temperature + T_on is the switch on temperature + +When the current temperature is the switch_on temperature, the above +formula becomes: + + P_max = 2 * sustainable_power * (T_set - T_on) / (T_set - T_on) + + sustainable_power = 2 * sustainable_power + sustainable_power = + 3 * sustainable_power + +Therefore, the proportional term alone linearly decreases power from +3 * `sustainable_power` to `sustainable_power` as the temperature +rises from the switch on temperature to the desired temperature. + +k_i and integral_cutoff +----------------------- + +`k_i` configures the PID loop's integral term constant. This term +allows the PID controller to compensate for long term drift and for +the quantized nature of the output control: cooling devices can't set +the exact power that the governor requests. When the temperature +error is below `integral_cutoff`, errors are accumulated in the +integral term. This term is then multiplied by `k_i` and the result +added to the output of the controller. Typically `k_i` is set low (1 +or 2) and `integral_cutoff` is 0. + +k_d +--- + +`k_d` configures the PID loop's derivative term constant. It's +recommended to leave it as the default: 0. + +Cooling device power API +======================== + +Cooling devices controlled by this governor must supply the additional +"power" API in their `cooling_device_ops`. It consists on three ops: + +1. int get_requested_power(struct thermal_cooling_device *cdev, + struct thermal_zone_device *tz, u32 *power); +@cdev: The `struct thermal_cooling_device` pointer +@tz: thermal zone in which we are currently operating +@power: pointer in which to store the calculated power + +`get_requested_power()` calculates the power requested by the device +in milliwatts and stores it in @power . It should return 0 on +success, -E* on failure. This is currently used by the power +allocator governor to calculate how much power to give to each cooling +device. + +2. int state2power(struct thermal_cooling_device *cdev, struct + thermal_zone_device *tz, unsigned long state, u32 *power); +@cdev: The `struct thermal_cooling_device` pointer +@tz: thermal zone in which we are currently operating +@state: A cooling device state +@power: pointer in which to store the equivalent power + +Convert cooling device state @state into power consumption in +milliwatts and store it in @power. It should return 0 on success, -E* +on failure. This is currently used by thermal core to calculate the +maximum power that an actor can consume. + +3. int power2state(struct thermal_cooling_device *cdev, u32 power, + unsigned long *state); +@cdev: The `struct thermal_cooling_device` pointer +@power: power in milliwatts +@state: pointer in which to store the resulting state + +Calculate a cooling device state that would make the device consume at +most @power mW and store it in @state. It should return 0 on success, +-E* on failure. This is currently used by the thermal core to convert +a given power set by the power allocator governor to a state that the +cooling device can set. It is a function because this conversion may +depend on external factors that may change so this function should the +best conversion given "current circumstances". + +Cooling device weights +---------------------- + +Weights are a mechanism to bias the allocation among cooling +devices. They express the relative power efficiency of different +cooling devices. Higher weight can be used to express higher power +efficiency. Weighting is relative such that if each cooling device +has a weight of one they are considered equal. This is particularly +useful in heterogeneous systems where two cooling devices may perform +the same kind of compute, but with different efficiency. For example, +a system with two different types of processors. + +If the thermal zone is registered using +`thermal_zone_device_register()` (i.e., platform code), then weights +are passed as part of the thermal zone's `thermal_bind_parameters`. +If the platform is registered using device tree, then they are passed +as the `contribution` property of each map in the `cooling-maps` node. + +Limitations of the power allocator governor +=========================================== + +The power allocator governor's PID controller works best if there is a +periodic tick. If you have a driver that calls +`thermal_zone_device_update()` (or anything that ends up calling the +governor's `throttle()` function) repetitively, the governor response +won't be very good. Note that this is not particular to this +governor, step-wise will also misbehave if you call its throttle() +faster than the normal thermal framework tick (due to interrupts for +example) as it will overreact. diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 30aee81e9f5b..a1b43eab0a70 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -71,6 +71,14 @@ config THERMAL_DEFAULT_GOV_USER_SPACE Select this if you want to let the user space manage the platform thermals. +config THERMAL_DEFAULT_GOV_POWER_ALLOCATOR + bool "power_allocator" + select THERMAL_GOV_POWER_ALLOCATOR + help + Select this if you want to control temperature based on + system and device power allocation. This governor can only + operate on cooling devices that implement the power API. + endchoice config THERMAL_GOV_FAIR_SHARE @@ -99,6 +107,13 @@ config THERMAL_GOV_USER_SPACE help Enable this to let the user space manage the platform thermals. +config THERMAL_GOV_POWER_ALLOCATOR + bool "Power allocator thermal governor" + select THERMAL_POWER_ACTOR + help + Enable this to manage platform thermals by dynamically + allocating and limiting power to devices. + config CPU_THERMAL bool "generic cpu cooling support" depends on CPU_FREQ diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 1fe86652cfb6..b1783cf37ed2 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -14,6 +14,7 @@ thermal_sys-$(CONFIG_THERMAL_GOV_FAIR_SHARE) += fair_share.o thermal_sys-$(CONFIG_THERMAL_GOV_BANG_BANG) += gov_bang_bang.o thermal_sys-$(CONFIG_THERMAL_GOV_STEP_WISE) += step_wise.o thermal_sys-$(CONFIG_THERMAL_GOV_USER_SPACE) += user_space.o +thermal_sys-$(CONFIG_THERMAL_GOV_POWER_ALLOCATOR) += power_allocator.o # cpufreq cooling thermal_sys-$(CONFIG_CPU_THERMAL) += cpu_cooling.o diff --git a/drivers/thermal/power_allocator.c b/drivers/thermal/power_allocator.c new file mode 100644 index 000000000000..67982d79b76c --- /dev/null +++ b/drivers/thermal/power_allocator.c @@ -0,0 +1,520 @@ +/* + * A power allocator to manage temperature + * + * Copyright (C) 2014 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "Power allocator: " fmt + +#include +#include +#include + +#include "thermal_core.h" + +#define FRAC_BITS 10 +#define int_to_frac(x) ((x) << FRAC_BITS) +#define frac_to_int(x) ((x) >> FRAC_BITS) + +/** + * mul_frac() - multiply two fixed-point numbers + * @x: first multiplicand + * @y: second multiplicand + * + * Return: the result of multiplying two fixed-point numbers. The + * result is also a fixed-point number. + */ +static inline s64 mul_frac(s64 x, s64 y) +{ + return (x * y) >> FRAC_BITS; +} + +/** + * div_frac() - divide two fixed-point numbers + * @x: the dividend + * @y: the divisor + * + * Return: the result of dividing two fixed-point numbers. The + * result is also a fixed-point number. + */ +static inline s64 div_frac(s64 x, s64 y) +{ + return div_s64(x << FRAC_BITS, y); +} + +/** + * struct power_allocator_params - parameters for the power allocator governor + * @err_integral: accumulated error in the PID controller. + * @prev_err: error in the previous iteration of the PID controller. + * Used to calculate the derivative term. + * @trip_switch_on: first passive trip point of the thermal zone. The + * governor switches on when this trip point is crossed. + * @trip_max_desired_temperature: last passive trip point of the thermal + * zone. The temperature we are + * controlling for. + */ +struct power_allocator_params { + s64 err_integral; + s32 prev_err; + int trip_switch_on; + int trip_max_desired_temperature; +}; + +/** + * pid_controller() - PID controller + * @tz: thermal zone we are operating in + * @current_temp: the current temperature in millicelsius + * @control_temp: the target temperature in millicelsius + * @max_allocatable_power: maximum allocatable power for this thermal zone + * + * This PID controller increases the available power budget so that the + * temperature of the thermal zone gets as close as possible to + * @control_temp and limits the power if it exceeds it. k_po is the + * proportional term when we are overshooting, k_pu is the + * proportional term when we are undershooting. integral_cutoff is a + * threshold below which we stop accumulating the error. The + * accumulated error is only valid if the requested power will make + * the system warmer. If the system is mostly idle, there's no point + * in accumulating positive error. + * + * Return: The power budget for the next period. + */ +static u32 pid_controller(struct thermal_zone_device *tz, + unsigned long current_temp, + unsigned long control_temp, + u32 max_allocatable_power) +{ + s64 p, i, d, power_range; + s32 err, max_power_frac; + struct power_allocator_params *params = tz->governor_data; + + max_power_frac = int_to_frac(max_allocatable_power); + + err = ((s32)control_temp - (s32)current_temp); + err = int_to_frac(err); + + /* Calculate the proportional term */ + p = mul_frac(err < 0 ? tz->tzp->k_po : tz->tzp->k_pu, err); + + /* + * Calculate the integral term + * + * if the error is less than cut off allow integration (but + * the integral is limited to max power) + */ + i = mul_frac(tz->tzp->k_i, params->err_integral); + + if (err < int_to_frac(tz->tzp->integral_cutoff)) { + s64 i_next = i + mul_frac(tz->tzp->k_i, err); + + if (abs64(i_next) < max_power_frac) { + i = i_next; + params->err_integral += err; + } + } + + /* + * Calculate the derivative term + * + * We do err - prev_err, so with a positive k_d, a decreasing + * error (i.e. driving closer to the line) results in less + * power being applied, slowing down the controller) + */ + d = mul_frac(tz->tzp->k_d, err - params->prev_err); + d = div_frac(d, tz->passive_delay); + params->prev_err = err; + + power_range = p + i + d; + + /* feed-forward the known sustainable dissipatable power */ + power_range = tz->tzp->sustainable_power + frac_to_int(power_range); + + return clamp(power_range, (s64)0, (s64)max_allocatable_power); +} + +/** + * divvy_up_power() - divvy the allocated power between the actors + * @req_power: each actor's requested power + * @max_power: each actor's maximum available power + * @num_actors: size of the @req_power, @max_power and @granted_power's array + * @total_req_power: sum of @req_power + * @power_range: total allocated power + * @granted_power: output array: each actor's granted power + * @extra_actor_power: an appropriately sized array to be used in the + * function as temporary storage of the extra power given + * to the actors + * + * This function divides the total allocated power (@power_range) + * fairly between the actors. It first tries to give each actor a + * share of the @power_range according to how much power it requested + * compared to the rest of the actors. For example, if only one actor + * requests power, then it receives all the @power_range. If + * three actors each requests 1mW, each receives a third of the + * @power_range. + * + * If any actor received more than their maximum power, then that + * surplus is re-divvied among the actors based on how far they are + * from their respective maximums. + * + * Granted power for each actor is written to @granted_power, which + * should've been allocated by the calling function. + */ +static void divvy_up_power(u32 *req_power, u32 *max_power, int num_actors, + u32 total_req_power, u32 power_range, + u32 *granted_power, u32 *extra_actor_power) +{ + u32 extra_power, capped_extra_power; + int i; + + /* + * Prevent division by 0 if none of the actors request power. + */ + if (!total_req_power) + total_req_power = 1; + + capped_extra_power = 0; + extra_power = 0; + for (i = 0; i < num_actors; i++) { + u64 req_range = req_power[i] * power_range; + + granted_power[i] = div_u64(req_range, total_req_power); + + if (granted_power[i] > max_power[i]) { + extra_power += granted_power[i] - max_power[i]; + granted_power[i] = max_power[i]; + } + + extra_actor_power[i] = max_power[i] - granted_power[i]; + capped_extra_power += extra_actor_power[i]; + } + + if (!extra_power) + return; + + /* + * Re-divvy the reclaimed extra among actors based on + * how far they are from the max + */ + extra_power = min(extra_power, capped_extra_power); + if (capped_extra_power > 0) + for (i = 0; i < num_actors; i++) + granted_power[i] += (extra_actor_power[i] * + extra_power) / capped_extra_power; +} + +static int allocate_power(struct thermal_zone_device *tz, + unsigned long current_temp, + unsigned long control_temp) +{ + struct thermal_instance *instance; + struct power_allocator_params *params = tz->governor_data; + u32 *req_power, *max_power, *granted_power, *extra_actor_power; + u32 total_req_power, max_allocatable_power; + u32 power_range; + int i, num_actors, total_weight, ret = 0; + int trip_max_desired_temperature = params->trip_max_desired_temperature; + + mutex_lock(&tz->lock); + + num_actors = 0; + total_weight = 0; + list_for_each_entry(instance, &tz->thermal_instances, tz_node) { + if ((instance->trip == trip_max_desired_temperature) && + cdev_is_power_actor(instance->cdev)) { + num_actors++; + total_weight += instance->weight; + } + } + + /* + * We need to allocate three arrays of the same size: + * req_power, max_power and granted_power. They are going to + * be needed until this function returns. Allocate them all + * in one go to simplify the allocation and deallocation + * logic. + */ + BUILD_BUG_ON(sizeof(*req_power) != sizeof(*max_power)); + BUILD_BUG_ON(sizeof(*req_power) != sizeof(*granted_power)); + BUILD_BUG_ON(sizeof(*req_power) != sizeof(*extra_actor_power)); + req_power = devm_kcalloc(&tz->device, num_actors * 4, + sizeof(*req_power), GFP_KERNEL); + if (!req_power) { + ret = -ENOMEM; + goto unlock; + } + + max_power = &req_power[num_actors]; + granted_power = &req_power[2 * num_actors]; + extra_actor_power = &req_power[3 * num_actors]; + + i = 0; + total_req_power = 0; + max_allocatable_power = 0; + + list_for_each_entry(instance, &tz->thermal_instances, tz_node) { + int weight; + struct thermal_cooling_device *cdev = instance->cdev; + + if (instance->trip != trip_max_desired_temperature) + continue; + + if (!cdev_is_power_actor(cdev)) + continue; + + if (cdev->ops->get_requested_power(cdev, tz, &req_power[i])) + continue; + + if (!total_weight) + weight = 1 << FRAC_BITS; + else + weight = instance->weight; + + req_power[i] = frac_to_int(weight * req_power[i]); + + if (power_actor_get_max_power(cdev, tz, &max_power[i])) + continue; + + total_req_power += req_power[i]; + max_allocatable_power += max_power[i]; + + i++; + } + + power_range = pid_controller(tz, current_temp, control_temp, + max_allocatable_power); + + divvy_up_power(req_power, max_power, num_actors, total_req_power, + power_range, granted_power, extra_actor_power); + + i = 0; + list_for_each_entry(instance, &tz->thermal_instances, tz_node) { + if (instance->trip != trip_max_desired_temperature) + continue; + + if (!cdev_is_power_actor(instance->cdev)) + continue; + + power_actor_set_power(instance->cdev, instance, + granted_power[i]); + + i++; + } + + devm_kfree(&tz->device, req_power); +unlock: + mutex_unlock(&tz->lock); + + return ret; +} + +static int get_governor_trips(struct thermal_zone_device *tz, + struct power_allocator_params *params) +{ + int i, ret, last_passive; + bool found_first_passive; + + found_first_passive = false; + last_passive = -1; + ret = -EINVAL; + + for (i = 0; i < tz->trips; i++) { + enum thermal_trip_type type; + + ret = tz->ops->get_trip_type(tz, i, &type); + if (ret) + return ret; + + if (!found_first_passive) { + if (type == THERMAL_TRIP_PASSIVE) { + params->trip_switch_on = i; + found_first_passive = true; + } + } else if (type == THERMAL_TRIP_PASSIVE) { + last_passive = i; + } else { + break; + } + } + + if (last_passive != -1) { + params->trip_max_desired_temperature = last_passive; + ret = 0; + } else { + ret = -EINVAL; + } + + return ret; +} + +static void reset_pid_controller(struct power_allocator_params *params) +{ + params->err_integral = 0; + params->prev_err = 0; +} + +static void allow_maximum_power(struct thermal_zone_device *tz) +{ + struct thermal_instance *instance; + struct power_allocator_params *params = tz->governor_data; + + list_for_each_entry(instance, &tz->thermal_instances, tz_node) { + if ((instance->trip != params->trip_max_desired_temperature) || + (!cdev_is_power_actor(instance->cdev))) + continue; + + instance->target = 0; + instance->cdev->updated = false; + thermal_cdev_update(instance->cdev); + } +} + +/** + * power_allocator_bind() - bind the power_allocator governor to a thermal zone + * @tz: thermal zone to bind it to + * + * Check that the thermal zone is valid for this governor, that is, it + * has two thermal trips. If so, initialize the PID controller + * parameters and bind it to the thermal zone. + * + * Return: 0 on success, -EINVAL if the trips were invalid or -ENOMEM + * if we ran out of memory. + */ +static int power_allocator_bind(struct thermal_zone_device *tz) +{ + int ret; + struct power_allocator_params *params; + unsigned long switch_on_temp, control_temp; + u32 temperature_threshold; + + if (!tz->tzp || !tz->tzp->sustainable_power) { + dev_err(&tz->device, + "power_allocator: missing sustainable_power\n"); + return -EINVAL; + } + + params = devm_kzalloc(&tz->device, sizeof(*params), GFP_KERNEL); + if (!params) + return -ENOMEM; + + ret = get_governor_trips(tz, params); + if (ret) { + dev_err(&tz->device, + "thermal zone %s has wrong trip setup for power allocator\n", + tz->type); + goto free; + } + + ret = tz->ops->get_trip_temp(tz, params->trip_switch_on, + &switch_on_temp); + if (ret) + goto free; + + ret = tz->ops->get_trip_temp(tz, params->trip_max_desired_temperature, + &control_temp); + if (ret) + goto free; + + temperature_threshold = control_temp - switch_on_temp; + + tz->tzp->k_po = tz->tzp->k_po ?: + int_to_frac(tz->tzp->sustainable_power) / temperature_threshold; + tz->tzp->k_pu = tz->tzp->k_pu ?: + int_to_frac(2 * tz->tzp->sustainable_power) / + temperature_threshold; + tz->tzp->k_i = tz->tzp->k_i ?: int_to_frac(10) / 1000; + /* + * The default for k_d and integral_cutoff is 0, so we can + * leave them as they are. + */ + + reset_pid_controller(params); + + tz->governor_data = params; + + return 0; + +free: + devm_kfree(&tz->device, params); + return ret; +} + +static void power_allocator_unbind(struct thermal_zone_device *tz) +{ + dev_dbg(&tz->device, "Unbinding from thermal zone %d\n", tz->id); + devm_kfree(&tz->device, tz->governor_data); + tz->governor_data = NULL; +} + +static int power_allocator_throttle(struct thermal_zone_device *tz, int trip) +{ + int ret; + unsigned long switch_on_temp, control_temp, current_temp; + struct power_allocator_params *params = tz->governor_data; + + /* + * We get called for every trip point but we only need to do + * our calculations once + */ + if (trip != params->trip_max_desired_temperature) + return 0; + + ret = thermal_zone_get_temp(tz, ¤t_temp); + if (ret) { + dev_warn(&tz->device, "Failed to get temperature: %d\n", ret); + return ret; + } + + ret = tz->ops->get_trip_temp(tz, params->trip_switch_on, + &switch_on_temp); + if (ret) { + dev_warn(&tz->device, + "Failed to get switch on temperature: %d\n", ret); + return ret; + } + + if (current_temp < switch_on_temp) { + tz->passive = 0; + reset_pid_controller(params); + allow_maximum_power(tz); + return 0; + } + + tz->passive = 1; + + ret = tz->ops->get_trip_temp(tz, params->trip_max_desired_temperature, + &control_temp); + if (ret) { + dev_warn(&tz->device, + "Failed to get the maximum desired temperature: %d\n", + ret); + return ret; + } + + return allocate_power(tz, current_temp, control_temp); +} + +static struct thermal_governor thermal_gov_power_allocator = { + .name = "power_allocator", + .bind_to_tz = power_allocator_bind, + .unbind_from_tz = power_allocator_unbind, + .throttle = power_allocator_throttle, +}; + +int thermal_gov_power_allocator_register(void) +{ + return thermal_register_governor(&thermal_gov_power_allocator); +} + +void thermal_gov_power_allocator_unregister(void) +{ + thermal_unregister_governor(&thermal_gov_power_allocator); +} diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index 263628b0e862..b389bc2ec0fa 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -1616,7 +1616,7 @@ static void remove_trip_attrs(struct thermal_zone_device *tz) struct thermal_zone_device *thermal_zone_device_register(const char *type, int trips, int mask, void *devdata, struct thermal_zone_device_ops *ops, - const struct thermal_zone_params *tzp, + struct thermal_zone_params *tzp, int passive_delay, int polling_delay) { struct thermal_zone_device *tz; @@ -1968,7 +1968,11 @@ static int __init thermal_register_governors(void) if (result) return result; - return thermal_gov_user_space_register(); + result = thermal_gov_user_space_register(); + if (result) + return result; + + return thermal_gov_power_allocator_register(); } static void thermal_unregister_governors(void) @@ -1977,6 +1981,7 @@ static void thermal_unregister_governors(void) thermal_gov_fair_share_unregister(); thermal_gov_bang_bang_unregister(); thermal_gov_user_space_unregister(); + thermal_gov_power_allocator_unregister(); } static int __init thermal_init(void) diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h index faebe881f062..8a6624488cc5 100644 --- a/drivers/thermal/thermal_core.h +++ b/drivers/thermal/thermal_core.h @@ -88,6 +88,14 @@ static inline int thermal_gov_user_space_register(void) { return 0; } static inline void thermal_gov_user_space_unregister(void) {} #endif /* CONFIG_THERMAL_GOV_USER_SPACE */ +#ifdef CONFIG_THERMAL_GOV_POWER_ALLOCATOR +int thermal_gov_power_allocator_register(void); +void thermal_gov_power_allocator_unregister(void); +#else +static inline int thermal_gov_power_allocator_register(void) { return 0; } +static inline void thermal_gov_power_allocator_unregister(void) {} +#endif /* CONFIG_THERMAL_GOV_POWER_ALLOCATOR */ + /* device tree support */ #ifdef CONFIG_THERMAL_OF int of_parse_thermal_zones(void); diff --git a/include/linux/thermal.h b/include/linux/thermal.h index bf3c55f405c2..6bbe11c97cea 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -59,6 +59,8 @@ #define DEFAULT_THERMAL_GOVERNOR "fair_share" #elif defined(CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE) #define DEFAULT_THERMAL_GOVERNOR "user_space" +#elif defined(CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR) +#define DEFAULT_THERMAL_GOVERNOR "power_allocator" #endif struct thermal_zone_device; @@ -154,8 +156,7 @@ struct thermal_attr { * @devdata: private pointer for device private data * @trips: number of trip points the thermal zone supports * @passive_delay: number of milliseconds to wait between polls when - * performing passive cooling. Currenty only used by the - * step-wise governor + * performing passive cooling. * @polling_delay: number of milliseconds to wait between polls when * checking whether trip points have been crossed (0 for * interrupt driven systems) @@ -165,7 +166,6 @@ struct thermal_attr { * @last_temperature: previous temperature read * @emul_temperature: emulated temperature when using CONFIG_THERMAL_EMULATION * @passive: 1 if you've crossed a passive trip point, 0 otherwise. - * Currenty only used by the step-wise governor. * @forced_passive: If > 0, temperature at which to switch on all ACPI * processor cooling devices. Currently only used by the * step-wise governor. @@ -197,7 +197,7 @@ struct thermal_zone_device { int passive; unsigned int forced_passive; struct thermal_zone_device_ops *ops; - const struct thermal_zone_params *tzp; + struct thermal_zone_params *tzp; struct thermal_governor *governor; void *governor_data; struct list_head thermal_instances; @@ -275,6 +275,33 @@ struct thermal_zone_params { int num_tbps; /* Number of tbp entries */ struct thermal_bind_params *tbp; + + /* + * Sustainable power (heat) that this thermal zone can dissipate in + * mW + */ + u32 sustainable_power; + + /* + * Proportional parameter of the PID controller when + * overshooting (i.e., when temperature is below the target) + */ + s32 k_po; + + /* + * Proportional parameter of the PID controller when + * undershooting + */ + s32 k_pu; + + /* Integral parameter of the PID controller */ + s32 k_i; + + /* Derivative parameter of the PID controller */ + s32 k_d; + + /* threshold below which the error is no longer accumulated */ + s32 integral_cutoff; }; struct thermal_genl_event { @@ -350,7 +377,7 @@ int power_actor_set_power(struct thermal_cooling_device *, struct thermal_instance *, u32); struct thermal_zone_device *thermal_zone_device_register(const char *, int, int, void *, struct thermal_zone_device_ops *, - const struct thermal_zone_params *, int, int); + struct thermal_zone_params *, int, int); void thermal_zone_device_unregister(struct thermal_zone_device *); int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int, -- cgit v1.2.3 From 647f99255d604aa98f919b89c74567bb4e8fe52c Mon Sep 17 00:00:00 2001 From: Punit Agrawal Date: Thu, 26 Feb 2015 19:00:32 +0000 Subject: of: thermal: Introduce sustainable power for a thermal zone Introduce an optional property called, sustainable-power, which represents the power (in mW) which the thermal zone can safely dissipate. If provided the property is parsed and associated with the thermal zone via the thermal zone parameters. Cc: Zhang Rui Cc: Eduardo Valentin Signed-off-by: Punit Agrawal Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/thermal.txt | 9 +++++++++ drivers/thermal/of-thermal.c | 4 ++++ 2 files changed, 13 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt b/Documentation/devicetree/bindings/thermal/thermal.txt index 29fe0bfae38e..8a49362dea6e 100644 --- a/Documentation/devicetree/bindings/thermal/thermal.txt +++ b/Documentation/devicetree/bindings/thermal/thermal.txt @@ -167,6 +167,13 @@ Optional property: by means of sensor ID. Additional coefficients are interpreted as constant offset. +- sustainable-power: An estimate of the sustainable power (in mW) that the + Type: unsigned thermal zone can dissipate at the desired + Size: one cell control temperature. For reference, the + sustainable power of a 4'' phone is typically + 2000mW, while on a 10'' tablet is around + 4500mW. + Note: The delay properties are bound to the maximum dT/dt (temperature derivative over time) in two situations for a thermal zone: (i) - when passive cooling is activated (polling-delay-passive); and @@ -546,6 +553,8 @@ thermal-zones { */ coefficients = <1200 -345 890>; + sustainable-power = <2500>; + trips { /* Trips are based on resulting linear equation */ cpu_trip: cpu-trip { diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c index c606b85ea9f4..705b21d01f1c 100644 --- a/drivers/thermal/of-thermal.c +++ b/drivers/thermal/of-thermal.c @@ -866,6 +866,7 @@ int __init of_parse_thermal_zones(void) for_each_child_of_node(np, child) { struct thermal_zone_device *zone; struct thermal_zone_params *tzp; + u32 prop; /* Check whether child is enabled or not */ if (!of_device_is_available(child)) @@ -892,6 +893,9 @@ int __init of_parse_thermal_zones(void) /* No hwmon because there might be hwmon drivers registering */ tzp->no_hwmon = true; + if (!of_property_read_u32(child, "sustainable-power", &prop)) + tzp->sustainable_power = prop; + zone = thermal_zone_device_register(child->name, tz->ntrips, 0, tz, ops, tzp, -- cgit v1.2.3 From 9f38271c6f82a577d9fdab27aaf2e1c55ae5cf73 Mon Sep 17 00:00:00 2001 From: Javi Merino Date: Thu, 26 Mar 2015 15:53:02 +0000 Subject: thermal: export thermal_zone_parameters to sysfs It's useful for tuning to be able to edit thermal_zone_parameters from userspace. Export them to the thermal_zone sysfs so that they can be easily changed. Cc: Zhang Rui Cc: Eduardo Valentin Signed-off-by: Javi Merino Signed-off-by: Eduardo Valentin --- Documentation/thermal/sysfs-api.txt | 52 +++++++++++++++++++ drivers/thermal/thermal_core.c | 101 ++++++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+) (limited to 'Documentation') diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index fc7dfe10778b..7d44d7f1a71b 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -184,6 +184,12 @@ Thermal zone device sys I/F, created once it's registered: |---trip_point_[0-*]_type: Trip point type |---trip_point_[0-*]_hyst: Hysteresis value for this trip point |---emul_temp: Emulated temperature set node + |---sustainable_power: Sustainable dissipatable power + |---k_po: Proportional term during temperature overshoot + |---k_pu: Proportional term during temperature undershoot + |---k_i: PID's integral term in the power allocator gov + |---k_d: PID's derivative term in the power allocator + |---integral_cutoff: Offset above which errors are accumulated Thermal cooling device sys I/F, created once it's registered: /sys/class/thermal/cooling_device[0-*]: @@ -307,6 +313,52 @@ emul_temp because userland can easily disable the thermal policy by simply flooding this sysfs node with low temperature values. +sustainable_power + An estimate of the sustained power that can be dissipated by + the thermal zone. Used by the power allocator governor. For + more information see Documentation/thermal/power_allocator.txt + Unit: milliwatts + RW, Optional + +k_po + The proportional term of the power allocator governor's PID + controller during temperature overshoot. Temperature overshoot + is when the current temperature is above the "desired + temperature" trip point. For more information see + Documentation/thermal/power_allocator.txt + RW, Optional + +k_pu + The proportional term of the power allocator governor's PID + controller during temperature undershoot. Temperature undershoot + is when the current temperature is below the "desired + temperature" trip point. For more information see + Documentation/thermal/power_allocator.txt + RW, Optional + +k_i + The integral term of the power allocator governor's PID + controller. This term allows the PID controller to compensate + for long term drift. For more information see + Documentation/thermal/power_allocator.txt + RW, Optional + +k_d + The derivative term of the power allocator governor's PID + controller. For more information see + Documentation/thermal/power_allocator.txt + RW, Optional + +integral_cutoff + Temperature offset from the desired temperature trip point + above which the integral term of the power allocator + governor's PID controller starts accumulating errors. For + example, if integral_cutoff is 0, then the integral term only + accumulates error when temperature is above the desired + temperature trip point. For more information see + Documentation/thermal/power_allocator.txt + RW, Optional + ***************************** * Cooling device attributes * ***************************** diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index 78bb9aa9d4e4..962de1847cc0 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -875,6 +875,102 @@ emul_temp_store(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR(emul_temp, S_IWUSR, NULL, emul_temp_store); #endif/*CONFIG_THERMAL_EMULATION*/ +static ssize_t +sustainable_power_show(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + struct thermal_zone_device *tz = to_thermal_zone(dev); + + if (tz->tzp) + return sprintf(buf, "%u\n", tz->tzp->sustainable_power); + else + return -EIO; +} + +static ssize_t +sustainable_power_store(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) +{ + struct thermal_zone_device *tz = to_thermal_zone(dev); + u32 sustainable_power; + + if (!tz->tzp) + return -EIO; + + if (kstrtou32(buf, 10, &sustainable_power)) + return -EINVAL; + + tz->tzp->sustainable_power = sustainable_power; + + return count; +} +static DEVICE_ATTR(sustainable_power, S_IWUSR | S_IRUGO, sustainable_power_show, + sustainable_power_store); + +#define create_s32_tzp_attr(name) \ + static ssize_t \ + name##_show(struct device *dev, struct device_attribute *devattr, \ + char *buf) \ + { \ + struct thermal_zone_device *tz = to_thermal_zone(dev); \ + \ + if (tz->tzp) \ + return sprintf(buf, "%u\n", tz->tzp->name); \ + else \ + return -EIO; \ + } \ + \ + static ssize_t \ + name##_store(struct device *dev, struct device_attribute *devattr, \ + const char *buf, size_t count) \ + { \ + struct thermal_zone_device *tz = to_thermal_zone(dev); \ + s32 value; \ + \ + if (!tz->tzp) \ + return -EIO; \ + \ + if (kstrtos32(buf, 10, &value)) \ + return -EINVAL; \ + \ + tz->tzp->name = value; \ + \ + return count; \ + } \ + static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, name##_show, name##_store) + +create_s32_tzp_attr(k_po); +create_s32_tzp_attr(k_pu); +create_s32_tzp_attr(k_i); +create_s32_tzp_attr(k_d); +create_s32_tzp_attr(integral_cutoff); +#undef create_s32_tzp_attr + +static struct device_attribute *dev_tzp_attrs[] = { + &dev_attr_sustainable_power, + &dev_attr_k_po, + &dev_attr_k_pu, + &dev_attr_k_i, + &dev_attr_k_d, + &dev_attr_integral_cutoff, +}; + +static int create_tzp_attrs(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dev_tzp_attrs); i++) { + int ret; + struct device_attribute *dev_attr = dev_tzp_attrs[i]; + + ret = device_create_file(dev, dev_attr); + if (ret) + return ret; + } + + return 0; +} + /** * power_actor_get_max_power() - get the maximum power that a cdev can consume * @cdev: pointer to &thermal_cooling_device @@ -1712,6 +1808,11 @@ struct thermal_zone_device *thermal_zone_device_register(const char *type, if (result) goto unregister; + /* Add thermal zone params */ + result = create_tzp_attrs(&tz->device); + if (result) + goto unregister; + /* Update 'this' zone's governor information */ mutex_lock(&thermal_governor_lock); -- cgit v1.2.3 From 101197c39b459b6ab0045089b514f3ce8c0d8250 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Thu, 12 Mar 2015 15:47:57 +0100 Subject: of: Document timings subnode of nvidia,tegra-mc The MC driver needs some timing-specific information to program the EMEM during a rate change of the EMC clock. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra-mc.txt | 84 +++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt index f3db93c85eea..3338a2834ad7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt @@ -1,6 +1,9 @@ NVIDIA Tegra Memory Controller device tree bindings =================================================== +memory-controller node +---------------------- + Required properties: - compatible: Should be "nvidia,tegra-mc" - reg: Physical base address and length of the controller's registers. @@ -15,9 +18,49 @@ Required properties: This device implements an IOMMU that complies with the generic IOMMU binding. See ../iommu/iommu.txt for details. -Example: --------- +emc-timings subnode +------------------- + +The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in +register PMC_STRAPPING_OPT_A). + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for. + +timing subnode +-------------- + +Each "emc-timings" node should contain a subnode for every supported EMC clock rate. + +Required properties for timing nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC +(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be +specified, according to the board documentation: + + MC_EMEM_ARB_CFG + MC_EMEM_ARB_OUTSTANDING_REQ + MC_EMEM_ARB_TIMING_RCD + MC_EMEM_ARB_TIMING_RP + MC_EMEM_ARB_TIMING_RC + MC_EMEM_ARB_TIMING_RAS + MC_EMEM_ARB_TIMING_FAW + MC_EMEM_ARB_TIMING_RRD + MC_EMEM_ARB_TIMING_RAP2PRE + MC_EMEM_ARB_TIMING_WAP2PRE + MC_EMEM_ARB_TIMING_R2R + MC_EMEM_ARB_TIMING_W2W + MC_EMEM_ARB_TIMING_R2W + MC_EMEM_ARB_TIMING_W2R + MC_EMEM_ARB_DA_TURNS + MC_EMEM_ARB_DA_COVERS + MC_EMEM_ARB_MISC0 + MC_EMEM_ARB_MISC1 + MC_EMEM_ARB_RING1_THROTTLE +Example SoC include file: + +/ { mc: memory-controller@0,70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -34,3 +77,40 @@ Example: ... iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; }; +}; + +Example board file: + +/ { + memory-controller@0,70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; +}; -- cgit v1.2.3 From 6b22194d5e34f45b71628b7fd0a61e63df9e7dd7 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 12 Mar 2015 15:47:58 +0100 Subject: of: Add Tegra124 EMC bindings Add binding documentation for the nvidia,tegra124-emc device tree node. Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding --- .../bindings/memory-controllers/tegra-emc.txt | 374 +++++++++++++++++++++ 1 file changed, 374 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt new file mode 100644 index 000000000000..b59c625d6336 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt @@ -0,0 +1,374 @@ +NVIDIA Tegra124 SoC EMC (external memory controller) +==================================================== + +Required properties : +- compatible : Should be "nvidia,tegra124-emc". +- reg : physical base address and length of the controller's registers. +- nvidia,memory-controller : phandle of the MC driver. + +The node should contain a "emc-timings" subnode for each supported RAM type +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address +being its RAM_CODE. + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is +used for. + +Each "emc-timings" node should contain a "timing" subnode for every supported +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as +their unit address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- The following properties contain EMC timing characterization values +(specified in the board documentation) : + - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG + - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2 + - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3 + - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL + - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0 + - nvidia,emc-cfg : EMC_CFG + - nvidia,emc-cfg-2 : EMC_CFG_2 + - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL + - nvidia,emc-mode-1 : Mode Register 1 + - nvidia,emc-mode-2 : Mode Register 2 + - nvidia,emc-mode-4 : Mode Register 4 + - nvidia,emc-mode-reset : Mode Register 0 + - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT + - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL + - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2 + - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change + - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL +- nvidia,emc-configuration : EMC timing characterization data. These are the +registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to +be specified, according to the board documentation: + + EMC_RC + EMC_RFC + EMC_RFC_SLR + EMC_RAS + EMC_RP + EMC_R2W + EMC_W2R + EMC_R2P + EMC_W2P + EMC_RD_RCD + EMC_WR_RCD + EMC_RRD + EMC_REXT + EMC_WEXT + EMC_WDV + EMC_WDV_MASK + EMC_QUSE + EMC_QUSE_WIDTH + EMC_IBDLY + EMC_EINPUT + EMC_EINPUT_DURATION + EMC_PUTERM_EXTRA + EMC_PUTERM_WIDTH + EMC_PUTERM_ADJ + EMC_CDB_CNTL_1 + EMC_CDB_CNTL_2 + EMC_CDB_CNTL_3 + EMC_QRST + EMC_QSAFE + EMC_RDV + EMC_RDV_MASK + EMC_REFRESH + EMC_BURST_REFRESH_NUM + EMC_PRE_REFRESH_REQ_CNT + EMC_PDEX2WR + EMC_PDEX2RD + EMC_PCHG2PDEN + EMC_ACT2PDEN + EMC_AR2PDEN + EMC_RW2PDEN + EMC_TXSR + EMC_TXSRDLL + EMC_TCKE + EMC_TCKESR + EMC_TPD + EMC_TFAW + EMC_TRPAB + EMC_TCLKSTABLE + EMC_TCLKSTOP + EMC_TREFBW + EMC_FBIO_CFG6 + EMC_ODT_WRITE + EMC_ODT_READ + EMC_FBIO_CFG5 + EMC_CFG_DIG_DLL + EMC_CFG_DIG_DLL_PERIOD + EMC_DLL_XFORM_DQS0 + EMC_DLL_XFORM_DQS1 + EMC_DLL_XFORM_DQS2 + EMC_DLL_XFORM_DQS3 + EMC_DLL_XFORM_DQS4 + EMC_DLL_XFORM_DQS5 + EMC_DLL_XFORM_DQS6 + EMC_DLL_XFORM_DQS7 + EMC_DLL_XFORM_DQS8 + EMC_DLL_XFORM_DQS9 + EMC_DLL_XFORM_DQS10 + EMC_DLL_XFORM_DQS11 + EMC_DLL_XFORM_DQS12 + EMC_DLL_XFORM_DQS13 + EMC_DLL_XFORM_DQS14 + EMC_DLL_XFORM_DQS15 + EMC_DLL_XFORM_QUSE0 + EMC_DLL_XFORM_QUSE1 + EMC_DLL_XFORM_QUSE2 + EMC_DLL_XFORM_QUSE3 + EMC_DLL_XFORM_QUSE4 + EMC_DLL_XFORM_QUSE5 + EMC_DLL_XFORM_QUSE6 + EMC_DLL_XFORM_QUSE7 + EMC_DLL_XFORM_ADDR0 + EMC_DLL_XFORM_ADDR1 + EMC_DLL_XFORM_ADDR2 + EMC_DLL_XFORM_ADDR3 + EMC_DLL_XFORM_ADDR4 + EMC_DLL_XFORM_ADDR5 + EMC_DLL_XFORM_QUSE8 + EMC_DLL_XFORM_QUSE9 + EMC_DLL_XFORM_QUSE10 + EMC_DLL_XFORM_QUSE11 + EMC_DLL_XFORM_QUSE12 + EMC_DLL_XFORM_QUSE13 + EMC_DLL_XFORM_QUSE14 + EMC_DLL_XFORM_QUSE15 + EMC_DLI_TRIM_TXDQS0 + EMC_DLI_TRIM_TXDQS1 + EMC_DLI_TRIM_TXDQS2 + EMC_DLI_TRIM_TXDQS3 + EMC_DLI_TRIM_TXDQS4 + EMC_DLI_TRIM_TXDQS5 + EMC_DLI_TRIM_TXDQS6 + EMC_DLI_TRIM_TXDQS7 + EMC_DLI_TRIM_TXDQS8 + EMC_DLI_TRIM_TXDQS9 + EMC_DLI_TRIM_TXDQS10 + EMC_DLI_TRIM_TXDQS11 + EMC_DLI_TRIM_TXDQS12 + EMC_DLI_TRIM_TXDQS13 + EMC_DLI_TRIM_TXDQS14 + EMC_DLI_TRIM_TXDQS15 + EMC_DLL_XFORM_DQ0 + EMC_DLL_XFORM_DQ1 + EMC_DLL_XFORM_DQ2 + EMC_DLL_XFORM_DQ3 + EMC_DLL_XFORM_DQ4 + EMC_DLL_XFORM_DQ5 + EMC_DLL_XFORM_DQ6 + EMC_DLL_XFORM_DQ7 + EMC_XM2CMDPADCTRL + EMC_XM2CMDPADCTRL4 + EMC_XM2CMDPADCTRL5 + EMC_XM2DQPADCTRL2 + EMC_XM2DQPADCTRL3 + EMC_XM2CLKPADCTRL + EMC_XM2CLKPADCTRL2 + EMC_XM2COMPPADCTRL + EMC_XM2VTTGENPADCTRL + EMC_XM2VTTGENPADCTRL2 + EMC_XM2VTTGENPADCTRL3 + EMC_XM2DQSPADCTRL3 + EMC_XM2DQSPADCTRL4 + EMC_XM2DQSPADCTRL5 + EMC_XM2DQSPADCTRL6 + EMC_DSR_VTTGEN_DRV + EMC_TXDSRVTTGEN + EMC_FBIO_SPARE + EMC_ZCAL_WAIT_CNT + EMC_MRS_WAIT_CNT2 + EMC_CTT + EMC_CTT_DURATION + EMC_CFG_PIPE + EMC_DYN_SELF_REF_CONTROL + EMC_QPOP + +Example SoC include file: + +/ { + emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; +}; + +Example board file: + +/ { + emc@0,7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + }; + }; +}; -- cgit v1.2.3 From d7b16e4f6283c6ec52b411aa6deb02ca4d030d20 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Mon, 4 May 2015 21:54:18 -0400 Subject: libata: Allow NCQ TRIM to be enabled or disabled with a module parameter We have started seeing SSD firmware updates introduce support for queued TRIM. Sadly, in most cases this support is completely untested and can lead to either errors or data corruption. Add two libata force flags that can be used to either enable or disable queued TRIM support. Signed-off-by: Martin K. Petersen Reviewed-by: Hannes Reinecke Signed-off-by: Tejun Heo --- Documentation/kernel-parameters.txt | 2 ++ drivers/ata/libata-core.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 01aa47d3b6ab..14a4be114cdc 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1755,6 +1755,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. * [no]ncq: Turn on or off NCQ. + * [no]ncqtrim: Turn off queued DSM TRIM. + * nohrst, nosrst, norst: suppress hard, soft and both resets. diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index f6cb1f1b30b7..8c1f0742cc1a 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -6472,6 +6472,8 @@ static int __init ata_parse_force_one(char **cur, { "3.0Gbps", .spd_limit = 2 }, { "noncq", .horkage_on = ATA_HORKAGE_NONCQ }, { "ncq", .horkage_off = ATA_HORKAGE_NONCQ }, + { "noncqtrim", .horkage_on = ATA_HORKAGE_NO_NCQ_TRIM }, + { "ncqtrim", .horkage_off = ATA_HORKAGE_NO_NCQ_TRIM }, { "dump_id", .horkage_on = ATA_HORKAGE_DUMP_ID }, { "pio0", .xfer_mask = 1 << (ATA_SHIFT_PIO + 0) }, { "pio1", .xfer_mask = 1 << (ATA_SHIFT_PIO + 1) }, -- cgit v1.2.3 From f303074160d3401970ccae082014e1ee5a9a52c5 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Mon, 4 May 2015 21:54:19 -0400 Subject: libata: Expose TRIM capability in sysfs Create a sysfs "trim" attribute for each ata_device that displays whether DSM TRIM is "unsupported", "unqueued", "forced_unqueued" (blacklisted) or "queued". Signed-off-by: Martin K. Petersen Reviewed-by: Hannes Reinecke Signed-off-by: Tejun Heo --- Documentation/ABI/testing/sysfs-ata | 11 +++++++++++ drivers/ata/libata-transport.c | 22 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-ata b/Documentation/ABI/testing/sysfs-ata index 0a932155cbba..9231daef3813 100644 --- a/Documentation/ABI/testing/sysfs-ata +++ b/Documentation/ABI/testing/sysfs-ata @@ -90,6 +90,17 @@ gscr 130: SATA_PMP_GSCR_SII_GPIO Only valid if the device is a PM. +trim + + Shows the DSM TRIM mode currently used by the device. Valid + values are: + unsupported: Drive does not support DSM TRIM + unqueued: Drive supports unqueued DSM TRIM only + queued: Drive supports queued DSM TRIM + forced_unqueued: Drive's unqueued DSM support is known to be + buggy and only unqueued TRIM commands + are sent + spdn_cnt Number of time libata decided to lower the speed of link due to errors. diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c index 3227b7c8a05f..d6c37bcd416d 100644 --- a/drivers/ata/libata-transport.c +++ b/drivers/ata/libata-transport.c @@ -560,6 +560,27 @@ show_ata_dev_gscr(struct device *dev, static DEVICE_ATTR(gscr, S_IRUGO, show_ata_dev_gscr, NULL); +static ssize_t +show_ata_dev_trim(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ata_device *ata_dev = transport_class_to_dev(dev); + unsigned char *mode; + + if (!ata_id_has_trim(ata_dev->id)) + mode = "unsupported"; + else if (ata_dev->horkage & ATA_HORKAGE_NO_NCQ_TRIM) + mode = "forced_unqueued"; + else if (ata_fpdma_dsm_supported(ata_dev)) + mode = "queued"; + else + mode = "unqueued"; + + return snprintf(buf, 20, "%s\n", mode); +} + +static DEVICE_ATTR(trim, S_IRUGO, show_ata_dev_trim, NULL); + static DECLARE_TRANSPORT_CLASS(ata_dev_class, "ata_device", NULL, NULL, NULL); @@ -733,6 +754,7 @@ struct scsi_transport_template *ata_attach_transport(void) SETUP_DEV_ATTRIBUTE(ering); SETUP_DEV_ATTRIBUTE(id); SETUP_DEV_ATTRIBUTE(gscr); + SETUP_DEV_ATTRIBUTE(trim); BUG_ON(count > ATA_DEV_ATTRS); i->dev_attrs[count] = NULL; -- cgit v1.2.3 From 6888c6f279a742a3190e186f44de70951b3491fd Mon Sep 17 00:00:00 2001 From: Chris Bainbridge Date: Tue, 5 May 2015 12:49:00 +0100 Subject: workqueue: fix trivial typo in Documentation/workqueue.txt Signed-off-by: Chris Bainbridge Signed-off-by: Tejun Heo --- Documentation/workqueue.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/workqueue.txt b/Documentation/workqueue.txt index f81a65b54c29..5e0e05c5183e 100644 --- a/Documentation/workqueue.txt +++ b/Documentation/workqueue.txt @@ -365,7 +365,7 @@ root 5674 0.0 0.0 0 0 ? S 12:13 0:00 [kworker/1:0] If kworkers are going crazy (using too much cpu), there are two types of possible problems: - 1. Something beeing scheduled in rapid succession + 1. Something being scheduled in rapid succession 2. A single work item that consumes lots of cpu cycles The first one can be tracked using tracing: -- cgit v1.2.3 From c61f819a45f6f71a295502e4c37d09173e74c380 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Sat, 2 May 2015 23:11:35 +0200 Subject: gpio: add DT bindings for lpc1850-gpio driver Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/nxp,lpc1850-gpio.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt new file mode 100644 index 000000000000..eb7cdd69e10b --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt @@ -0,0 +1,39 @@ +NXP LPC18xx/43xx GPIO controller Device Tree Bindings +----------------------------------------------------- + +Required properties: +- compatible : Should be "nxp,lpc1850-gpio" +- reg : Address and length of the register set for the device +- clocks : Clock specifier (see clock bindings for details) +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Should be two + - First cell is the GPIO line number + - Second cell is used to specify polarity + +Optional properties: +- gpio-ranges : Mapping between GPIO and pinctrl + +Example: +#define LPC_GPIO(port, pin) (port * 32 + pin) +#define LPC_PIN(port, pin) (0x##port * 32 + pin) + +gpio: gpio@400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + ... + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; +}; + +gpio_joystick { + compatible = "gpio-keys-polled"; + ... + + button@0 { + ... + gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; + }; +}; -- cgit v1.2.3 From f133d08a3986efeff24069616ac739fc83c8ec9f Mon Sep 17 00:00:00 2001 From: Wang Long Date: Tue, 5 May 2015 01:22:26 +0000 Subject: Documentation: cpufreq: delete duplicate description of sysfs interface 'scaling_driver' The file 'Documentation/cpu-freq/user-guide.txt' has duplicate description of sysfs interface 'scaling_driver'. [first] scaling_driver : this file shows what cpufreq driver is used to set the frequency on this CPU [second] scaling_driver : Hardware driver for cpufreq. Although this does not affect anything, I think we should only have one. so delete the second one because the first one is described in more detail. Signed-off-by: Wang Long Signed-off-by: Rafael J. Wysocki --- Documentation/cpu-freq/user-guide.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cpu-freq/user-guide.txt b/Documentation/cpu-freq/user-guide.txt index ff2f28332cc4..109e97bbab77 100644 --- a/Documentation/cpu-freq/user-guide.txt +++ b/Documentation/cpu-freq/user-guide.txt @@ -196,8 +196,6 @@ affected_cpus : List of Online CPUs that require software related_cpus : List of Online + Offline CPUs that need software coordination of frequency. -scaling_driver : Hardware driver for cpufreq. - scaling_cur_freq : Current frequency of the CPU as determined by the governor and cpufreq core, in KHz. This is the frequency the kernel thinks the CPU runs -- cgit v1.2.3 From 784b58a327ad16967ab64bbfa558df81980d31e9 Mon Sep 17 00:00:00 2001 From: Bernhard Thaler Date: Mon, 4 May 2015 22:47:13 +0200 Subject: bridge: change BR_GROUPFWD_RESTRICTED to allow forwarding of LLDP frames BR_GROUPFWD_RESTRICTED bitmask restricts users from setting values to /sys/class/net/brX/bridge/group_fwd_mask that allow forwarding of some IEEE 802.1D Table 7-10 Reserved addresses: (MAC Control) 802.3 01-80-C2-00-00-01 (Link Aggregation) 802.3 01-80-C2-00-00-02 802.1AB LLDP 01-80-C2-00-00-0E Change BR_GROUPFWD_RESTRICTED to allow to forward LLDP frames and document group_fwd_mask. e.g. echo 16384 > /sys/class/net/brX/bridge/group_fwd_mask allows to forward LLDP frames. This may be needed for bridge setups used for network troubleshooting or any other scenario where forwarding of LLDP frames is desired (e.g. bridge connecting a virtual machine to real switch transmitting LLDP frames that virtual machine needs to receive). Tested on a simple bridge setup with two interfaces and host transmitting LLDP frames on one side of this bridge (used lldpd). Setting group_fwd_mask as described above lets LLDP frames traverse bridge. Signed-off-by: Bernhard Thaler Signed-off-by: David S. Miller --- Documentation/ABI/testing/sysfs-class-net | 19 +++++++++++++++++++ net/bridge/br_private.h | 4 ++-- 2 files changed, 21 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-net b/Documentation/ABI/testing/sysfs-class-net index 5ecfd72ba684..668604fc8e06 100644 --- a/Documentation/ABI/testing/sysfs-class-net +++ b/Documentation/ABI/testing/sysfs-class-net @@ -39,6 +39,25 @@ Description: Format is a string, e.g: 00:11:22:33:44:55 for an Ethernet MAC address. +What: /sys/class/net//bridge/group_fwd_mask +Date: January 2012 +KernelVersion: 3.2 +Contact: netdev@vger.kernel.org +Description: + Bitmask to allow forwarding of link local frames with address + 01-80-C2-00-00-0X on a bridge device. Only values that set bits + not matching BR_GROUPFWD_RESTRICTED in net/bridge/br_private.h + allowed. + Default value 0 does not forward any link local frames. + + Restricted bits: + 0: 01-80-C2-00-00-00 Bridge Group Address used for STP + 1: 01-80-C2-00-00-01 (MAC Control) 802.3 used for MAC PAUSE + 2: 01-80-C2-00-00-02 (Link Aggregation) 802.3ad + + Any values not setting these bits can be used. Take special + care when forwarding control frames e.g. 802.1X-PAE or LLDP. + What: /sys/class/net//broadcast Date: April 2005 KernelVersion: 2.6.12 diff --git a/net/bridge/br_private.h b/net/bridge/br_private.h index 3362c29400f1..1f36fa70639b 100644 --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h @@ -33,8 +33,8 @@ /* Control of forwarding link local multicast */ #define BR_GROUPFWD_DEFAULT 0 -/* Don't allow forwarding control protocols like STP and LLDP */ -#define BR_GROUPFWD_RESTRICTED 0x4007u +/* Don't allow forwarding of control protocols like STP, MAC PAUSE and LACP */ +#define BR_GROUPFWD_RESTRICTED 0x0007u /* The Nearest Customer Bridge Group Address, 01-80-C2-00-00-[00,0B,0C,0D,0F] */ #define BR_GROUPFWD_8021AD 0xB801u -- cgit v1.2.3 From 9eb67f1093fdaefdffe56861e373f50d117352e9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 23 Apr 2015 10:35:43 +0200 Subject: dt-bindings: ARM: Mediatek: Document devicetree bindings for clock/reset controllers This adds the binding documentation for the apmixedsys, perisys and infracfg controllers found on Mediatek SoCs. Signed-off-by: Sascha Hauer Signed-off-by: Stephen Boyd --- .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 23 +++++++++++++++++ .../bindings/arm/mediatek/mediatek,infracfg.txt | 30 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,pericfg.txt | 30 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,topckgen.txt | 23 +++++++++++++++++ 4 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt new file mode 100644 index 000000000000..5af6d7394608 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -0,0 +1,23 @@ +Mediatek apmixedsys controller +============================== + +The Mediatek apmixedsys controller provides the PLLs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8173-apmixedsys" +- #clock-cells: Must be 1 + +The apmixedsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt new file mode 100644 index 000000000000..684da473b3e8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -0,0 +1,30 @@ +Mediatek infracfg controller +============================ + +The Mediatek infracfg controller provides various clocks and reset +outputs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8173-infracfg", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The infracfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. +Also it uses the common reset controller binding from +Documentation/devicetree/bindings/reset/reset.txt. +The available reset outputs are defined in +dt-bindings/reset-controller/mt*-resets.h + +Example: + +infracfg: infracfg@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt new file mode 100644 index 000000000000..fdb45c6b63de --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -0,0 +1,30 @@ +Mediatek pericfg controller +=========================== + +The Mediatek pericfg controller provides various clocks and reset +outputs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-pericfg", "syscon" + - "mediatek,mt8173-pericfg", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The pericfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. +Also it uses the common reset controller binding from +Documentation/devicetree/bindings/reset/reset.txt. +The available reset outputs are defined in +dt-bindings/reset-controller/mt*-resets.h + +Example: + +pericfg: pericfg@10003000 { + compatible = "mediatek,mt8173-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt new file mode 100644 index 000000000000..a4252489860d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -0,0 +1,23 @@ +Mediatek topckgen controller +============================ + +The Mediatek topckgen controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-topckgen" + - "mediatek,mt8173-topckgen" +- #clock-cells: Must be 1 + +The topckgen controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +topckgen: topckgen@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; +}; -- cgit v1.2.3 From a2f11835994ed5bcd6d66c7205947cc482231b08 Mon Sep 17 00:00:00 2001 From: Shawn Landden Date: Tue, 5 May 2015 09:07:16 -0700 Subject: can.h: make padding given by gcc explicit The current definition of struct can_frame has a 16-byte size, with 8-byte alignment, but the 3 bytes of padding are not explicit like the similar 2 bytes of padding of struct canfd_frame. Make it explicit so it is easier to read. Signed-off-by: Shawn Landden Acked-by: Oliver Hartkopp Signed-off-by: Marc Kleine-Budde --- Documentation/networking/can.txt | 3 +++ include/uapi/linux/can.h | 6 ++++++ 2 files changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/networking/can.txt b/Documentation/networking/can.txt index 5abad1e921ca..b48d4a149411 100644 --- a/Documentation/networking/can.txt +++ b/Documentation/networking/can.txt @@ -268,6 +268,9 @@ solution for a couple of reasons: struct can_frame { canid_t can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */ __u8 can_dlc; /* frame payload length in byte (0 .. 8) */ + __u8 __pad; /* padding */ + __u8 __res0; /* reserved / padding */ + __u8 __res1; /* reserved / padding */ __u8 data[8] __attribute__((aligned(8))); }; diff --git a/include/uapi/linux/can.h b/include/uapi/linux/can.h index 41892f720057..9692cda5f8fc 100644 --- a/include/uapi/linux/can.h +++ b/include/uapi/linux/can.h @@ -95,11 +95,17 @@ typedef __u32 can_err_mask_t; * @can_dlc: frame payload length in byte (0 .. 8) aka data length code * N.B. the DLC field from ISO 11898-1 Chapter 8.4.2.3 has a 1:1 * mapping of the 'data length code' to the real payload length + * @__pad: padding + * @__res0: reserved / padding + * @__res1: reserved / padding * @data: CAN frame payload (up to 8 byte) */ struct can_frame { canid_t can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */ __u8 can_dlc; /* frame payload length in byte (0 .. CAN_MAX_DLEN) */ + __u8 __pad; /* padding */ + __u8 __res0; /* reserved / padding */ + __u8 __res1; /* reserved / padding */ __u8 data[CAN_MAX_DLEN] __attribute__((aligned(8))); }; -- cgit v1.2.3 From 0d1802ef8fea1eee9bec00319db33ab54202bb0a Mon Sep 17 00:00:00 2001 From: Andreas Gröger Date: Tue, 5 May 2015 20:08:34 +0200 Subject: can: janz-ican3: add documentation for existing sysfs entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds documentation for the existing sysfs entries for the janz PCI module. Signed-off-by: Andreas Gröger Signed-off-by: Marc Kleine-Budde --- Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio | 8 ++++++++ Documentation/ABI/testing/sysfs-class-net-janz-ican3 | 10 ++++++++++ 2 files changed, 18 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio create mode 100644 Documentation/ABI/testing/sysfs-class-net-janz-ican3 (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio b/Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio new file mode 100644 index 000000000000..4d08f28dc871 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-pci-drivers-janz-cmodio @@ -0,0 +1,8 @@ +What: /sys/bus/pci/drivers/janz-cmodio/.../modulbus_number +Date: May 2010 +KernelVersion: 2.6.35 +Contact: Ira W. Snyder +Description: + Value representing the HEX switch S2 of the janz carrier board CMOD-IO or CAN-PCI2 + + Read-only: value of the configuration switch (0..15) diff --git a/Documentation/ABI/testing/sysfs-class-net-janz-ican3 b/Documentation/ABI/testing/sysfs-class-net-janz-ican3 new file mode 100644 index 000000000000..af25a580e6d6 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-net-janz-ican3 @@ -0,0 +1,10 @@ +What: /sys/class/net//termination +Date: May 2010 +KernelVersion: 2.6.35 +Contact: Ira W. Snyder +Description: + Value representing the can bus termination + + Default: 1 (termination active) + Reading: get actual termination state + Writing: set actual termination state (0=no termination, 1=termination active) -- cgit v1.2.3 From 844e0edf42d1847b974427b5597009f1de45496c Mon Sep 17 00:00:00 2001 From: Andreas Gröger Date: Tue, 5 May 2015 20:08:34 +0200 Subject: can: janz-ican3: add support for CAL/CANopen firmware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In our department we are using some older Janz ICAN3-modules in our dekstop pcs. There we have slightly different carrier boards than the janz-cmodio supported in the kernel sources, called CAN-PCI2 with two submodules. But the pci configuration regions are identical. So extending the supported pci devices to the corresponding device ids is sufficient to get the drivers working. * The old ICAN3-modules with firmware 1.28 need more then 250ms for the restart after reset. I've increased the timeout to 500ms. * The janz_ican3 module uses the raw can services of the Janz-firmware, this means firmware must be ICANOS/2. Our ICAN3-modules are equipped with CAL/CANopen-firmware, so I must use the appropriate commands for the layer management services. Te driver detects the firmware after module reset and selects the commands matching the firmware. This affects the bus on/off-command (ican3_set_bus_state) and the configuration of the bittiming (ican3_set_bittiming). For better diagnostics the detected firmware string is presented as sysfs attribute (fwinfo). Signed-off-by: Andreas Gröger Signed-off-by: Marc Kleine-Budde --- .../ABI/testing/sysfs-class-net-janz-ican3 | 9 ++ drivers/mfd/janz-cmodio.c | 4 + drivers/net/can/janz-ican3.c | 125 +++++++++++++++------ 3 files changed, 101 insertions(+), 37 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-net-janz-ican3 b/Documentation/ABI/testing/sysfs-class-net-janz-ican3 index af25a580e6d6..fdbc03a2b8f8 100644 --- a/Documentation/ABI/testing/sysfs-class-net-janz-ican3 +++ b/Documentation/ABI/testing/sysfs-class-net-janz-ican3 @@ -8,3 +8,12 @@ Description: Default: 1 (termination active) Reading: get actual termination state Writing: set actual termination state (0=no termination, 1=termination active) + +What: /sys/class/net//fwinfo +Date: May 2015 +KernelVersion: 3.19 +Contact: Andreas Gröger +Description: + Firmware stamp of ican3 module + Read-only: 32 byte string identification of the ICAN3 module + (known values: "JANZ-ICAN3 ICANOS 1.xx", "JANZ-ICAN3 CAL/CANopen 1.xx") diff --git a/drivers/mfd/janz-cmodio.c b/drivers/mfd/janz-cmodio.c index 433f823037dd..ec1f46a6be3a 100644 --- a/drivers/mfd/janz-cmodio.c +++ b/drivers/mfd/janz-cmodio.c @@ -267,6 +267,10 @@ static void cmodio_pci_remove(struct pci_dev *dev) static const struct pci_device_id cmodio_pci_ids[] = { { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0101 }, { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0100 }, + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0201 }, + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0202 }, + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0201 }, + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0202 }, { 0, } }; MODULE_DEVICE_TABLE(pci, cmodio_pci_ids); diff --git a/drivers/net/can/janz-ican3.c b/drivers/net/can/janz-ican3.c index 4dd183a3643a..c1e85368a198 100644 --- a/drivers/net/can/janz-ican3.c +++ b/drivers/net/can/janz-ican3.c @@ -40,6 +40,7 @@ #define MSYNC_PEER 0x00 /* ICAN only */ #define MSYNC_LOCL 0x01 /* host only */ #define TARGET_RUNNING 0x02 +#define FIRMWARE_STAMP 0x60 /* big endian firmware stamp */ #define MSYNC_RB0 0x01 #define MSYNC_RB1 0x02 @@ -83,6 +84,7 @@ #define MSG_COFFREQ 0x42 #define MSG_CONREQ 0x43 #define MSG_CCONFREQ 0x47 +#define MSG_LMTS 0xb4 /* * Janz ICAN3 CAN Inquiry Message Types @@ -165,6 +167,12 @@ /* SJA1000 Clock Input */ #define ICAN3_CAN_CLOCK 8000000 +/* Janz ICAN3 firmware types */ +enum ican3_fwtype { + ICAN3_FWTYPE_ICANOS, + ICAN3_FWTYPE_CAL_CANOPEN, +}; + /* Driver Name */ #define DRV_NAME "janz-ican3" @@ -215,6 +223,10 @@ struct ican3_dev { struct completion buserror_comp; struct can_berr_counter bec; + /* firmware type */ + enum ican3_fwtype fwtype; + char fwinfo[32]; + /* old and new style host interface */ unsigned int iftype; @@ -750,13 +762,61 @@ static int ican3_set_id_filter(struct ican3_dev *mod, bool accept) */ static int ican3_set_bus_state(struct ican3_dev *mod, bool on) { + struct can_bittiming *bt = &mod->can.bittiming; struct ican3_msg msg; + u8 btr0, btr1; + int res; - memset(&msg, 0, sizeof(msg)); - msg.spec = on ? MSG_CONREQ : MSG_COFFREQ; - msg.len = cpu_to_le16(0); + /* This algorithm was stolen from drivers/net/can/sja1000/sja1000.c */ + /* The bittiming register command for the ICAN3 just sets the bit timing */ + /* registers on the SJA1000 chip directly */ + btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6); + btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) | + (((bt->phase_seg2 - 1) & 0x7) << 4); + if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) + btr1 |= 0x80; - return ican3_send_msg(mod, &msg); + if (mod->fwtype == ICAN3_FWTYPE_ICANOS) { + if (on) { + /* set bittiming */ + memset(&msg, 0, sizeof(msg)); + msg.spec = MSG_CBTRREQ; + msg.len = cpu_to_le16(4); + msg.data[0] = 0x00; + msg.data[1] = 0x00; + msg.data[2] = btr0; + msg.data[3] = btr1; + + res = ican3_send_msg(mod, &msg); + if (res) + return res; + } + + /* can-on/off request */ + memset(&msg, 0, sizeof(msg)); + msg.spec = on ? MSG_CONREQ : MSG_COFFREQ; + msg.len = cpu_to_le16(0); + + return ican3_send_msg(mod, &msg); + + } else if (mod->fwtype == ICAN3_FWTYPE_CAL_CANOPEN) { + memset(&msg, 0, sizeof(msg)); + msg.spec = MSG_LMTS; + if (on) { + msg.len = cpu_to_le16(4); + msg.data[0] = 0; + msg.data[1] = 0; + msg.data[2] = btr0; + msg.data[3] = btr1; + } else { + msg.len = cpu_to_le16(2); + msg.data[0] = 1; + msg.data[1] = 0; + } + + return ican3_send_msg(mod, &msg); + } + return -ENOTSUPP; } static int ican3_set_termination(struct ican3_dev *mod, bool on) @@ -1402,7 +1462,7 @@ static int ican3_reset_module(struct ican3_dev *mod) return 0; msleep(10); - } while (time_before(jiffies, start + HZ / 4)); + } while (time_before(jiffies, start + HZ / 2)); netdev_err(mod->ndev, "failed to reset CAN module\n"); return -ETIMEDOUT; @@ -1427,6 +1487,17 @@ static int ican3_startup_module(struct ican3_dev *mod) return ret; } + /* detect firmware */ + memcpy_fromio(mod->fwinfo, mod->dpm + FIRMWARE_STAMP, sizeof(mod->fwinfo) - 1); + if (strncmp(mod->fwinfo, "JANZ-ICAN3", 10)) { + netdev_err(mod->ndev, "ICAN3 not detected (found %s)\n", mod->fwinfo); + return -ENODEV; + } + if (strstr(mod->fwinfo, "CAL/CANopen")) + mod->fwtype = ICAN3_FWTYPE_CAL_CANOPEN; + else + mod->fwtype = ICAN3_FWTYPE_ICANOS; + /* re-enable interrupts so we can send messages */ iowrite8(1 << mod->num, &mod->ctrl->int_enable); @@ -1615,36 +1686,6 @@ static const struct can_bittiming_const ican3_bittiming_const = { .brp_inc = 1, }; -/* - * This routine was stolen from drivers/net/can/sja1000/sja1000.c - * - * The bittiming register command for the ICAN3 just sets the bit timing - * registers on the SJA1000 chip directly - */ -static int ican3_set_bittiming(struct net_device *ndev) -{ - struct ican3_dev *mod = netdev_priv(ndev); - struct can_bittiming *bt = &mod->can.bittiming; - struct ican3_msg msg; - u8 btr0, btr1; - - btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6); - btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) | - (((bt->phase_seg2 - 1) & 0x7) << 4); - if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) - btr1 |= 0x80; - - memset(&msg, 0, sizeof(msg)); - msg.spec = MSG_CBTRREQ; - msg.len = cpu_to_le16(4); - msg.data[0] = 0x00; - msg.data[1] = 0x00; - msg.data[2] = btr0; - msg.data[3] = btr1; - - return ican3_send_msg(mod, &msg); -} - static int ican3_set_mode(struct net_device *ndev, enum can_mode mode) { struct ican3_dev *mod = netdev_priv(ndev); @@ -1730,11 +1771,22 @@ static ssize_t ican3_sysfs_set_term(struct device *dev, return count; } +static ssize_t ican3_sysfs_show_fwinfo(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ican3_dev *mod = netdev_priv(to_net_dev(dev)); + + return scnprintf(buf, PAGE_SIZE, "%s\n", mod->fwinfo); +} + static DEVICE_ATTR(termination, S_IWUSR | S_IRUGO, ican3_sysfs_show_term, ican3_sysfs_set_term); +static DEVICE_ATTR(fwinfo, S_IRUSR | S_IRUGO, ican3_sysfs_show_fwinfo, NULL); static struct attribute *ican3_sysfs_attrs[] = { &dev_attr_termination.attr, + &dev_attr_fwinfo.attr, NULL, }; @@ -1794,7 +1846,6 @@ static int ican3_probe(struct platform_device *pdev) mod->can.clock.freq = ICAN3_CAN_CLOCK; mod->can.bittiming_const = &ican3_bittiming_const; - mod->can.do_set_bittiming = ican3_set_bittiming; mod->can.do_set_mode = ican3_set_mode; mod->can.do_get_berr_counter = ican3_get_berr_counter; mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES @@ -1866,7 +1917,7 @@ static int ican3_probe(struct platform_device *pdev) goto out_free_irq; } - dev_info(dev, "module %d: registered CAN device\n", pdata->modno); + netdev_info(mod->ndev, "module %d: registered CAN device\n", pdata->modno); return 0; out_free_irq: -- cgit v1.2.3 From a9ed9eb6345806917bae87b689a906e97415fd01 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Tue, 28 Apr 2015 00:14:09 +0200 Subject: pinctrl: add DT bindings for lpc1850-scu pinctrl driver Signed-off-by: Joachim Eastwood Signed-off-by: Linus Walleij --- .../bindings/pinctrl/nxp,lpc1850-scu.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt new file mode 100644 index 000000000000..df0309c57505 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt @@ -0,0 +1,57 @@ +NXP LPC18xx/43xx SCU pin controller Device Tree Bindings +-------------------------------------------------------- + +Required properties: +- compatible : Should be "nxp,lpc1850-scu" +- reg : Address and length of the register set for the device +- clocks : Clock specifier (see clock bindings for details) + +The lpc1850-scu driver uses the generic pin multiplexing and generic pin +configuration documented in pinctrl-bindings.txt. + +The following generic nodes are supported: + - function + - pins + - bias-disable + - bias-pull-up + - bias-pull-down + - drive-strength + - input-enable + - input-disable + - input-schmitt-enable + - input-schmitt-disable + - slew-rate + +Not all pins support all properties so either refer to the NXP 1850/4350 +user manual or the pin table in the pinctrl-lpc18xx driver for supported +pin properties. + +Example: +pinctrl: pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-disable; + }; + }; +}; -- cgit v1.2.3 From abbc48e1c2a246d3d10393dec070e02ee150d0ae Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Tue, 28 Apr 2015 18:13:01 -0700 Subject: pinctrl: Add Pistachio SoC pin control binding document Add a device-tree binding document for the pin controller present on the IMG Pistachio SoC. Signed-off-by: Damien Horsley Signed-off-by: Ezequiel Garcia Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Linus Walleij --- .../bindings/pinctrl/img,pistachio-pinctrl.txt | 217 +++++++++++++++++++++ 1 file changed, 217 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt new file mode 100644 index 000000000000..08a4a32c8eb0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt @@ -0,0 +1,217 @@ +Imagination Technologies Pistachio SoC pin controllers +====================================================== + +The pin controllers on Pistachio are a combined GPIO controller, (GPIO) +interrupt controller, and pinmux + pinconf device. The system ("east") pin +controller on Pistachio has 99 pins, 90 of which are MFIOs which can be +configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs +each. The GPIO banks are represented as sub-nodes of the pad controller node. + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +Required properties for pin controller node: +-------------------------------------------- + - compatible: "img,pistachio-system-pinctrl". + - reg: Address range of the pinctrl registers. + +Required properties for GPIO bank sub-nodes: +-------------------------------------------- + - interrupts: Interrupt line for the GPIO bank. + - gpio-controller: Indicates the device is a GPIO controller. + - #gpio-cells: Must be two. The first cell is the GPIO pin number and the + second cell indicates the polarity. See for + a list of possible values. + - interrupt-controller: Indicates the device is an interrupt controller. + - #interrupt-cells: Must be two. The first cell is the GPIO pin number and + the second cell encodes the interrupt flags. See + for a list of valid flags. + +Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1. + +Required properties for pin configuration sub-nodes: +---------------------------------------------------- + - pins: List of pins to which the configuration applies. See below for a + list of possible pins. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. This is not applicable for + non-MFIO pins. See below for a list of valid functions for each pin. + - bias-high-impedance: Enable high-impedance mode. + - bias-pull-up: Enable weak pull-up. + - bias-pull-down: Enable weak pull-down. + - bias-bus-hold: Enable bus-keeper mode. + - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12. + - input-schmitt-enable: Enable Schmitt trigger. + - input-schmitt-disable: Disable Schmitt trigger. + - slew-rate: Slew rate control. 0 for slow, 1 for fast. + +Pin Functions +--- --------- +mfio0 spim1 +mfio1 spim1, spim0, uart1 +mfio2 spim1, spim0, uart1 +mfio3 spim1 +mfio4 spim1 +mfio5 spim1 +mfio6 spim1 +mfio7 spim1 +mfio8 spim0 +mfio9 spim0 +mfio10 spim0 +mfio11 spis +mfio12 spis +mfio13 spis +mfio14 spis +mfio15 sdhost, mips_trace_clk, mips_trace_data +mfio16 sdhost, mips_trace_dint, mips_trace_data +mfio17 sdhost, mips_trace_trigout, mips_trace_data +mfio18 sdhost, mips_trace_trigin, mips_trace_data +mfio19 sdhost, mips_trace_dm, mips_trace_data +mfio20 sdhost, mips_trace_probe_n, mips_trace_data +mfio21 sdhost, mips_trace_data +mfio22 sdhost, mips_trace_data +mfio23 sdhost +mfio24 sdhost +mfio25 sdhost +mfio26 sdhost +mfio27 sdhost +mfio28 i2c0, spim0 +mfio29 i2c0, spim0 +mfio30 i2c1, spim0 +mfio31 i2c1, spim1 +mfio32 i2c2 +mfio33 i2c2 +mfio34 i2c3 +mfio35 i2c3 +mfio36 i2s_out, audio_clk_in +mfio37 i2s_out, debug_raw_cca_ind +mfio38 i2s_out, debug_ed_sec20_cca_ind +mfio39 i2s_out, debug_ed_sec40_cca_ind +mfio40 i2s_out, debug_agc_done_0 +mfio41 i2s_out, debug_agc_done_1 +mfio42 i2s_out, debug_ed_cca_ind +mfio43 i2s_out, debug_s2l_done +mfio44 i2s_out +mfio45 i2s_dac_clk, audio_sync +mfio46 audio_trigger +mfio47 i2s_in +mfio48 i2s_in +mfio49 i2s_in +mfio50 i2s_in +mfio51 i2s_in +mfio52 i2s_in +mfio53 i2s_in +mfio54 i2s_in, spdif_in +mfio55 uart0, spim0, spim1 +mfio56 uart0, spim0, spim1 +mfio57 uart0, spim0, spim1 +mfio58 uart0, spim1 +mfio59 uart1 +mfio60 uart1 +mfio61 spdif_out +mfio62 spdif_in +mfio63 eth, mips_trace_clk, mips_trace_data +mfio64 eth, mips_trace_dint, mips_trace_data +mfio65 eth, mips_trace_trigout, mips_trace_data +mfio66 eth, mips_trace_trigin, mips_trace_data +mfio67 eth, mips_trace_dm, mips_trace_data +mfio68 eth, mips_trace_probe_n, mips_trace_data +mfio69 eth, mips_trace_data +mfio70 eth, mips_trace_data +mfio71 eth +mfio72 ir +mfio73 pwmpdm, mips_trace_clk, sram_debug +mfio74 pwmpdm, mips_trace_dint, sram_debug +mfio75 pwmpdm, mips_trace_trigout, rom_debug +mfio76 pwmpdm, mips_trace_trigin, rom_debug +mfio77 mdc_debug, mips_trace_dm, rpu_debug +mfio78 mdc_debug, mips_trace_probe_n, rpu_debug +mfio79 ddr_debug, mips_trace_data, mips_debug +mfio80 ddr_debug, mips_trace_data, mips_debug +mfio81 dreq0, mips_trace_data, eth_debug +mfio82 dreq1, mips_trace_data, eth_debug +mfio83 mips_pll_lock, mips_trace_data, usb_debug +mfio84 sys_pll_lock, mips_trace_data, usb_debug +mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug +mfio86 bt_pll_lock, mips_trace_data, sdhost_debug +mfio87 rpu_v_pll_lock, dreq2, socif_debug +mfio88 rpu_l_pll_lock, dreq3, socif_debug +mfio89 audio_pll_lock, dreq4, dreq5 +tck +trstn +tdi +tms +tdo +jtag_comply +safe_mode +por_disable +resetn + +Example: +-------- +pinctrl@18101C00 { + compatible = "img,pistachio-system-pinctrl"; + reg = <0x18101C00 0x400>; + + gpio0: gpio0 { + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + gpio5: gpio5 { + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + uart0_xfer: uart0-xfer { + uart0-rxd { + pins = "mfio55"; + function = "uart0"; + }; + uart0-txd { + pins = "mfio56"; + function = "uart0"; + }; + }; + + uart0_rts_cts: uart0-rts-cts { + uart0-rts { + pins = "mfio57"; + function = "uart0"; + }; + uart0-cts { + pins = "mfio58"; + function = "uart0"; + }; + }; +}; + +uart@... { + ... + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>; + ... +}; + +usb_vbus: fixed-regulator { + ... + gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + ... +}; -- cgit v1.2.3 From fa76a3db7093a527333c380df82a0f158d9b8299 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 9 Apr 2015 11:13:07 +0800 Subject: pinctrl: allow exlusive GPIO/mux pin allocation Disallow simultaneous use of the the GPIO and peripheral mux functions by setting a flag "strict" in struct pinctrl_desc. The blackfin pinmux and gpio controller doesn't allow user to set up a pin for both GPIO and peripheral function. So, add flag strict in struct pinctrl_desc to check both gpio_owner and mux_owner before approving the pin request. v2-changes: - if strict flag is set, check gpio_owner and mux_onwer in if and else clause v3-changes: - add kerneldoc for this struct - augment Documentation/pinctrl.txt Signed-off-by: Sonic Zhang Signed-off-by: Linus Walleij --- Documentation/pinctrl.txt | 11 +++++++++++ drivers/pinctrl/pinctrl-adi2.c | 1 + drivers/pinctrl/pinmux.c | 13 +++++++++++++ include/linux/pinctrl/pinctrl.h | 3 +++ 4 files changed, 28 insertions(+) (limited to 'Documentation') diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index a9b47163bb5d..d6b2bed94c43 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -73,6 +73,7 @@ static struct pinctrl_desc foo_desc = { .pins = foo_pins, .npins = ARRAY_SIZE(foo_pins), .owner = THIS_MODULE, + .strict = true, }; int __init foo_probe(void) @@ -830,6 +831,11 @@ separate memory range only intended for GPIO driving, and the register range dealing with pin config and pin multiplexing get placed into a different memory range and a separate section of the data sheet. +A flag "strict" in struct pinctrl_desc is available to check and deny +simultaneous access to the same pin from GPIO and pin multiplexing +consumers on hardware of this type. The pinctrl driver should set this flag +accordingly. + (B) pin config @@ -850,6 +856,11 @@ possible that the GPIO, pin config and pin multiplex registers are placed into the same memory range and the same section of the data sheet, although that need not be the case. +In some pin controllers, although the physical pins are designed in the same +way as (B), the GPIO function still can't be enabled at the same time as the +peripheral functions. So again the "strict" flag should be set, denying +simultaneous activation by GPIO and other muxed in devices. + From a kernel point of view, however, these are different aspects of the hardware and shall be put into different subsystems: diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 8434439c5017..fbd492668da1 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -710,6 +710,7 @@ static struct pinctrl_desc adi_pinmux_desc = { .name = DRIVER_NAME, .pctlops = &adi_pctrl_ops, .pmxops = &adi_pinmux_ops, + .strict = true, .owner = THIS_MODULE, }; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index b874458dcb88..2546fa783464 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -107,6 +107,13 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->gpio_owner, owner); goto out; } + if (pctldev->desc->strict && desc->mux_usecount && + strcmp(desc->mux_owner, owner)) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->mux_owner, owner); + goto out; + } desc->gpio_owner = owner; } else { @@ -116,6 +123,12 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->mux_owner, owner); goto out; } + if (pctldev->desc->strict && desc->gpio_owner) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->gpio_owner, owner); + goto out; + } desc->mux_usecount++; if (desc->mux_usecount > 1) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 66e4697516de..fc6b0348c375 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -114,6 +114,8 @@ struct pinctrl_ops { * of the pins field above * @pctlops: pin control operation vtable, to support global concepts like * grouping of pins, this is optional. + * @strict: check both gpio_owner and mux_owner strictly before approving + the pin request * @pmxops: pinmux operations vtable, if you support pinmuxing in your driver * @confops: pin config operations vtable, if you support pin configuration in * your driver @@ -132,6 +134,7 @@ struct pinctrl_desc { const struct pinctrl_ops *pctlops; const struct pinmux_ops *pmxops; const struct pinconf_ops *confops; + bool strict; struct module *owner; #ifdef CONFIG_GENERIC_PINCONF unsigned int num_custom_params; -- cgit v1.2.3 From 8c4c2016345feefcd289ce2479eb70286d30825a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 6 May 2015 14:19:13 +0200 Subject: pinctrl: move strict option to pinmux_ops While the pinmux_ops are ideally just a vtable for pin mux calls, the "strict" setting belongs so intuitively with the pin multiplexing that we should move it here anyway. Putting it in the top pinctrl_desc makes no sense. Cc: Sonic Zhang Signed-off-by: Linus Walleij --- Documentation/pinctrl.txt | 2 +- drivers/pinctrl/pinctrl-adi2.c | 2 +- drivers/pinctrl/pinmux.c | 4 ++-- include/linux/pinctrl/pinctrl.h | 3 --- include/linux/pinctrl/pinmux.h | 4 ++++ 5 files changed, 8 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index d6b2bed94c43..4976389e432d 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -73,7 +73,6 @@ static struct pinctrl_desc foo_desc = { .pins = foo_pins, .npins = ARRAY_SIZE(foo_pins), .owner = THIS_MODULE, - .strict = true, }; int __init foo_probe(void) @@ -715,6 +714,7 @@ static struct pinmux_ops foo_pmxops = { .get_function_name = foo_get_fname, .get_function_groups = foo_get_groups, .set_mux = foo_set_mux, + .strict = true, }; /* Pinmux operations are handled by some pin controller */ diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index fbd492668da1..49df9037b41e 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -703,6 +703,7 @@ static struct pinmux_ops adi_pinmux_ops = { .get_function_name = adi_pinmux_get_func_name, .get_function_groups = adi_pinmux_get_groups, .gpio_request_enable = adi_pinmux_request_gpio, + .strict = true, }; @@ -710,7 +711,6 @@ static struct pinctrl_desc adi_pinmux_desc = { .name = DRIVER_NAME, .pctlops = &adi_pctrl_ops, .pmxops = &adi_pinmux_ops, - .strict = true, .owner = THIS_MODULE, }; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 2546fa783464..c58c168b06c2 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -107,7 +107,7 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->gpio_owner, owner); goto out; } - if (pctldev->desc->strict && desc->mux_usecount && + if (ops->strict && desc->mux_usecount && strcmp(desc->mux_owner, owner)) { dev_err(pctldev->dev, "pin %s already requested by %s; cannot claim for %s\n", @@ -123,7 +123,7 @@ static int pin_request(struct pinctrl_dev *pctldev, desc->name, desc->mux_owner, owner); goto out; } - if (pctldev->desc->strict && desc->gpio_owner) { + if (ops->strict && desc->gpio_owner) { dev_err(pctldev->dev, "pin %s already requested by %s; cannot claim for %s\n", desc->name, desc->gpio_owner, owner); diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index fc6b0348c375..66e4697516de 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -114,8 +114,6 @@ struct pinctrl_ops { * of the pins field above * @pctlops: pin control operation vtable, to support global concepts like * grouping of pins, this is optional. - * @strict: check both gpio_owner and mux_owner strictly before approving - the pin request * @pmxops: pinmux operations vtable, if you support pinmuxing in your driver * @confops: pin config operations vtable, if you support pin configuration in * your driver @@ -134,7 +132,6 @@ struct pinctrl_desc { const struct pinctrl_ops *pctlops; const struct pinmux_ops *pmxops; const struct pinconf_ops *confops; - bool strict; struct module *owner; #ifdef CONFIG_GENERIC_PINCONF unsigned int num_custom_params; diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index 511bda9ed4bf..d3740fa7073f 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -56,6 +56,9 @@ struct pinctrl_dev; * depending on whether the GPIO is configured as input or output, * a direction selector function may be implemented as a backing * to the GPIO controllers that need pin muxing. + * @strict: do not allow simultaneous use of the same pin for GPIO and another + * function. Check both gpio_owner and mux_owner strictly before approving + * the pin request. */ struct pinmux_ops { int (*request) (struct pinctrl_dev *pctldev, unsigned offset); @@ -79,6 +82,7 @@ struct pinmux_ops { struct pinctrl_gpio_range *range, unsigned offset, bool input); + bool strict; }; #endif /* CONFIG_PINMUX */ -- cgit v1.2.3 From 83a21727c3fb23844de38f85fb4250bd21961c25 Mon Sep 17 00:00:00 2001 From: Helmut Buchsbaum Date: Sun, 26 Apr 2015 11:32:47 +0200 Subject: pinctrl: zynq: configure SPI SSx pins separately MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI interfaces, SS0, SS1 and SS2 have to be configured separately as they may be used as simple GPIO lines. This, of course, has to be considered in the devicetree, so pin controller configuration for e.g. an SPI0 using SS0 and SS1 only might look like the following snippet (derived from the example of chapter "17.5.3 MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used as GPIO instead of being occupied by SPI0 SS2 function. Note the separate pinmux function for the slave select signals: pinctrl_spi0_default: spi0-default { mux_spi { function = "spi0"; groups = "spi0_0_grp"; }; mux_ss { function = "spi0_ss"; groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp"; } conf-output { pins = "MIO16", "MIO21"; slew-rate = <0>; bias-disable; low-power-disable; io-standard = <1>; }; conf-input { pins = "MIO17"; slew-rate = <0>; bias-high-impedance; low-power-disable; io-standard = <1>; }; conf-select { pins = "MIO18", "MIO19"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; pinctrl_gpio0_default { mux { function = "gpio0"; groups = "gpio0_20_grp" }; conf { pins = "MIO20"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; Signed-off-by: Helmut Buchsbaum Acked-by: Sören Brinkmann Signed-off-by: Linus Walleij --- .../bindings/pinctrl/xlnx,zynq-pinctrl.txt | 7 ++- drivers/pinctrl/pinctrl-zynq.c | 70 +++++++++++++++++++--- 2 files changed, 67 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt index b7b55a964f65..f488b0f77406 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt @@ -45,8 +45,9 @@ to specify in a pinconf subnode: Valid values for groups are: ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, - qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp, - spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp, + qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp, + spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, + spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, @@ -59,7 +60,7 @@ to specify in a pinconf subnode: Valid values for function are: ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, - spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, + spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp, smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 22280bddb9e2..af726b906656 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -101,6 +101,8 @@ enum zynq_pinmux_functions { ZYNQ_PMUX_qspi_cs1, ZYNQ_PMUX_spi0, ZYNQ_PMUX_spi1, + ZYNQ_PMUX_spi0_ss, + ZYNQ_PMUX_spi1_ss, ZYNQ_PMUX_sdio0, ZYNQ_PMUX_sdio0_pc, ZYNQ_PMUX_sdio0_cd, @@ -196,13 +198,35 @@ static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; static const unsigned int qspi_cs1_pins[] = {0}; static const unsigned int qspi_fbclk_pins[] = {8}; -static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21}; -static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33}; -static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45}; -static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15}; -static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27}; -static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39}; -static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int spi0_0_pins[] = {16, 17, 21}; +static const unsigned int spi0_0_ss0_pins[] = {18}; +static const unsigned int spi0_0_ss1_pins[] = {19}; +static const unsigned int spi0_0_ss2_pins[] = {20,}; +static const unsigned int spi0_1_pins[] = {28, 29, 33}; +static const unsigned int spi0_1_ss0_pins[] = {30}; +static const unsigned int spi0_1_ss1_pins[] = {31}; +static const unsigned int spi0_1_ss2_pins[] = {32}; +static const unsigned int spi0_2_pins[] = {40, 41, 45}; +static const unsigned int spi0_2_ss0_pins[] = {42}; +static const unsigned int spi0_2_ss1_pins[] = {43}; +static const unsigned int spi0_2_ss2_pins[] = {44}; +static const unsigned int spi1_0_pins[] = {10, 11, 12}; +static const unsigned int spi1_0_ss0_pins[] = {13}; +static const unsigned int spi1_0_ss1_pins[] = {14}; +static const unsigned int spi1_0_ss2_pins[] = {15}; +static const unsigned int spi1_1_pins[] = {22, 23, 24}; +static const unsigned int spi1_1_ss0_pins[] = {25}; +static const unsigned int spi1_1_ss1_pins[] = {26}; +static const unsigned int spi1_1_ss2_pins[] = {27}; +static const unsigned int spi1_2_pins[] = {34, 35, 36}; +static const unsigned int spi1_2_ss0_pins[] = {37}; +static const unsigned int spi1_2_ss1_pins[] = {38}; +static const unsigned int spi1_2_ss2_pins[] = {39}; +static const unsigned int spi1_3_pins[] = {46, 47, 48, 49}; +static const unsigned int spi1_3_ss0_pins[] = {49}; +static const unsigned int spi1_3_ss1_pins[] = {50}; +static const unsigned int spi1_3_ss2_pins[] = {51}; + static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; @@ -379,12 +403,33 @@ struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), @@ -552,6 +597,15 @@ static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", "spi0_2_grp"}; static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", "spi1_2_grp", "spi1_3_grp"}; +static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp", + "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp", + "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp", + "spi0_2_ss1_grp", "spi0_2_ss2_grp"}; +static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp", + "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp", + "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp", + "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp", + "spi1_3_ss1_grp", "spi1_3_ss2_grp"}; static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", "sdio0_2_grp"}; static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", @@ -742,6 +796,8 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = { DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK, -- cgit v1.2.3 From 4b9d64ee04a4033213454b384d5ec2dcd5e25b84 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Tue, 5 May 2015 17:53:48 -0400 Subject: libata: Fix sysfs documentation bug forced_unqueued indicates that a drive's queued DSM support is broken. Update sysfs ABI documentation accordingly. Reported-by: Christoph Hellwig Signed-off-by: Martin K. Petersen Signed-off-by: Tejun Heo --- Documentation/ABI/testing/sysfs-ata | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-ata b/Documentation/ABI/testing/sysfs-ata index 9231daef3813..aa4296498859 100644 --- a/Documentation/ABI/testing/sysfs-ata +++ b/Documentation/ABI/testing/sysfs-ata @@ -97,7 +97,7 @@ trim unsupported: Drive does not support DSM TRIM unqueued: Drive supports unqueued DSM TRIM only queued: Drive supports queued DSM TRIM - forced_unqueued: Drive's unqueued DSM support is known to be + forced_unqueued: Drive's queued DSM support is known to be buggy and only unqueued TRIM commands are sent -- cgit v1.2.3 From a605c668cc0c0ed267c014267f04bef29460367d Mon Sep 17 00:00:00 2001 From: Kamlakant Patel Date: Tue, 28 Apr 2015 20:10:44 +0530 Subject: gpio: Add Netlogic XLP GPIO devicetree bindings documentation Provide documentation for Netlogic XLP SoCs GPIO controller DTS bindings. Signed-off-by: Kamlakant Patel Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-xlp.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-xlp.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-xlp.txt b/Documentation/devicetree/bindings/gpio/gpio-xlp.txt new file mode 100644 index 000000000000..262ee4ddf2cb --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-xlp.txt @@ -0,0 +1,47 @@ +Netlogic XLP Family GPIO +======================== + +This GPIO driver is used for following Netlogic XLP SoCs: + XLP832, XLP316, XLP208, XLP980, XLP532 + +Required properties: +------------------- + +- compatible: Should be one of the following: + - "netlogic,xlp832-gpio": For Netlogic XLP832 + - "netlogic,xlp316-gpio": For Netlogic XLP316 + - "netlogic,xlp208-gpio": For Netlogic XLP208 + - "netlogic,xlp980-gpio": For Netlogic XLP980 + - "netlogic,xlp532-gpio": For Netlogic XLP532 +- reg: Physical base address and length of the controller's registers. +- #gpio-cells: Should be two. The first cell is the pin number and the second + cell is used to specify optional parameters (currently unused). +- gpio-controller: Marks the device node as a GPIO controller. +- nr-gpios: Number of GPIO pins supported by the controller. +- interrupt-cells: Should be two. The first cell is the GPIO Number. The + second cell is used to specify flags. The following subset of flags is + supported: + - trigger type: + 1 = low to high edge triggered. + 2 = high to low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. +- interrupts: Interrupt number for this device. +- interrupt-parent: phandle of the parent interrupt controller. +- interrupt-controller: Identifies the node as an interrupt controller. + +Example: + + gpio: xlp_gpio@34000 { + compatible = "netlogic,xlp316-gpio"; + reg = <0 0x34100 0x1000 + 0 0x35100 0x1000>; + #gpio-cells = <2>; + gpio-controller; + nr-gpios = <57>; + + #interrupt-cells = <2>; + interrupt-parent = <&pic>; + interrupts = <39>; + interrupt-controller; + }; -- cgit v1.2.3 From 4b8038dca0c0ccf5e4689cc4fbbbf4f3728304be Mon Sep 17 00:00:00 2001 From: Qipan Li Date: Mon, 20 Apr 2015 08:10:22 +0000 Subject: Revert "serial: sirf: add a new uart type support" This reverts commit 52bec4ed4e("serial: sirf: add a new uart type support"). we misunderstood the clock dependency in atlas7. Actually involved several clocks are in a tree structure. we still only need to take the leaf clock node for BT uarts. Signed-off-by: Qipan Li Signed-off-by: Barry Song Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/sirf-uart.txt | 15 +--------- drivers/tty/serial/sirfsoc_uart.c | 34 +++++----------------- drivers/tty/serial/sirfsoc_uart.h | 4 --- 3 files changed, 8 insertions(+), 45 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/sirf-uart.txt b/Documentation/devicetree/bindings/serial/sirf-uart.txt index f0c39261c5d4..67e2a0aeb042 100644 --- a/Documentation/devicetree/bindings/serial/sirf-uart.txt +++ b/Documentation/devicetree/bindings/serial/sirf-uart.txt @@ -2,8 +2,7 @@ Required properties: - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", - "sirf,atlas7-uart" or "sirf,atlas7-bt-uart" which means - uart located in BT module and used for BT. + "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". - reg : Offset and length of the register set for the device - interrupts : Should contain uart interrupt - fifosize : Should define hardware rx/tx fifo size @@ -33,15 +32,3 @@ usp@b0090000 { rts-gpios = <&gpio 15 0>; cts-gpios = <&gpio 46 0>; }; - -for uart use in BT module, -uart6: uart@11000000 { - cell-index = <6>; - compatible = "sirf,atlas7-bt-uart", "sirf,atlas7-uart"; - reg = <0x11000000 0x1000>; - interrupts = <0 100 0>; - clocks = <&clks 138>, <&clks 140>, <&clks 141>; - clock-names = "uart", "general", "noc"; - fifosize = <128>; - status = "disabled"; -} diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c index 9de3eabe5737..8081cdba8778 100644 --- a/drivers/tty/serial/sirfsoc_uart.c +++ b/drivers/tty/serial/sirfsoc_uart.c @@ -1032,19 +1032,10 @@ static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) { struct sirfsoc_uart_port *sirfport = to_sirfport(port); - if (!state) { - if (sirfport->is_bt_uart) { - clk_prepare_enable(sirfport->clk_noc); - clk_prepare_enable(sirfport->clk_general); - } + if (!state) clk_prepare_enable(sirfport->clk); - } else { + else clk_disable_unprepare(sirfport->clk); - if (sirfport->is_bt_uart) { - clk_disable_unprepare(sirfport->clk_general); - clk_disable_unprepare(sirfport->clk_noc); - } - } } static int sirfsoc_uart_startup(struct uart_port *port) @@ -1387,26 +1378,12 @@ usp_no_flow_control: } port->irq = res->start; - sirfport->clk = devm_clk_get(&pdev->dev, NULL); + sirfport->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(sirfport->clk)) { ret = PTR_ERR(sirfport->clk); goto err; } port->uartclk = clk_get_rate(sirfport->clk); - if (of_device_is_compatible(pdev->dev.of_node, "sirf,atlas7-bt-uart")) { - sirfport->clk_general = devm_clk_get(&pdev->dev, "general"); - if (IS_ERR(sirfport->clk_general)) { - ret = PTR_ERR(sirfport->clk_general); - goto err; - } - sirfport->clk_noc = devm_clk_get(&pdev->dev, "noc"); - if (IS_ERR(sirfport->clk_noc)) { - ret = PTR_ERR(sirfport->clk_noc); - goto err; - } - sirfport->is_bt_uart = true; - } else - sirfport->is_bt_uart = false; port->ops = &sirfsoc_uart_ops; spin_lock_init(&port->lock); @@ -1415,7 +1392,7 @@ usp_no_flow_control: ret = uart_add_one_port(&sirfsoc_uart_drv, port); if (ret != 0) { dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id); - goto err; + goto port_err; } sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx"); @@ -1444,6 +1421,8 @@ alloc_coherent_err: sirfport->rx_dma_items[j].xmit.buf, sirfport->rx_dma_items[j].dma_addr); dma_release_channel(sirfport->rx_dma_chan); +port_err: + clk_put(sirfport->clk); err: return ret; } @@ -1452,6 +1431,7 @@ static int sirfsoc_uart_remove(struct platform_device *pdev) { struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev); struct uart_port *port = &sirfport->port; + clk_put(sirfport->clk); uart_remove_one_port(&sirfsoc_uart_drv, port); if (sirfport->rx_dma_chan) { int i; diff --git a/drivers/tty/serial/sirfsoc_uart.h b/drivers/tty/serial/sirfsoc_uart.h index 727eb6b88fff..11fd6814f76d 100644 --- a/drivers/tty/serial/sirfsoc_uart.h +++ b/drivers/tty/serial/sirfsoc_uart.h @@ -417,10 +417,6 @@ struct sirfsoc_uart_port { struct uart_port port; struct clk *clk; - /* UART6 for BT usage in A7DA platform need multi-clock source */ - bool is_bt_uart; - struct clk *clk_general; - struct clk *clk_noc; /* for SiRFatlas7, there are SET/CLR for UART_INT_EN */ bool is_atlas7; struct sirfsoc_uart_register *uart_reg; -- cgit v1.2.3 From c1c325d703d347d967242efb8fef6a1c91a31aac Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 27 Apr 2015 08:49:57 +0200 Subject: tty: serial: 8250_mtk: Add support for bus clock The mtk 8250 needs two clocks, one for providing the baudrate and one that needs to be enabled for register accesses. The latter has not been supported, this patch adds support for it. It is optional for now since not all SoCs provide a bus clock. Signed-off-by: Sascha Hauer Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/mtk-uart.txt | 12 ++++++++-- drivers/tty/serial/8250/8250_mtk.c | 28 ++++++++++++++++++---- 2 files changed, 34 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 44152261e5c5..8d63f1da07aa 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -14,7 +14,14 @@ Required properties: - interrupts: A single interrupt specifier. -- clocks: Clock driving the hardware. +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: + - "baud": The clock the baudrate is derived from + - "bus": The bus clock for register accesses (optional) + +For compatibility with older device trees an unnamed clock is used for the +baud clock if the baudclk does not exist. Do not use this for new designs. Example: @@ -22,5 +29,6 @@ Example: compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; reg = <0x11006000 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&uart_clk>, <&bus_clk>; + clock-names = "baud", "bus"; }; diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c index 2f28bd08b69f..8eb3876563f1 100644 --- a/drivers/tty/serial/8250/8250_mtk.c +++ b/drivers/tty/serial/8250/8250_mtk.c @@ -34,6 +34,7 @@ struct mtk8250_data { int line; struct clk *uart_clk; + struct clk *bus_clk; }; static void @@ -120,6 +121,7 @@ static int mtk8250_runtime_suspend(struct device *dev) struct mtk8250_data *data = dev_get_drvdata(dev); clk_disable_unprepare(data->uart_clk); + clk_disable_unprepare(data->bus_clk); return 0; } @@ -135,6 +137,12 @@ static int mtk8250_runtime_resume(struct device *dev) return err; } + err = clk_prepare_enable(data->bus_clk); + if (err) { + dev_warn(dev, "Can't enable bus clock\n"); + return err; + } + return 0; } @@ -153,13 +161,24 @@ mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p, struct mtk8250_data *data) { - data->uart_clk = devm_clk_get(&pdev->dev, NULL); + data->uart_clk = devm_clk_get(&pdev->dev, "baud"); if (IS_ERR(data->uart_clk)) { - dev_warn(&pdev->dev, "Can't get uart clock\n"); - return PTR_ERR(data->uart_clk); + /* + * For compatibility with older device trees try unnamed + * clk when no baud clk can be found. + */ + data->uart_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(data->uart_clk)) { + dev_warn(&pdev->dev, "Can't get uart clock\n"); + return PTR_ERR(data->uart_clk); + } + + return 0; } - p->uartclk = clk_get_rate(data->uart_clk); + data->bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(data->bus_clk)) + return PTR_ERR(data->bus_clk); return 0; } @@ -204,6 +223,7 @@ static int mtk8250_probe(struct platform_device *pdev) uart.port.regshift = 2; uart.port.private_data = data; uart.port.set_termios = mtk8250_set_termios; + uart.port.uartclk = clk_get_rate(data->uart_clk); /* Disable Rate Fix function */ writel(0x0, uart.port.membase + -- cgit v1.2.3 From 90de4a1875180f8347c075319af2cce586c96ab6 Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Mon, 13 Apr 2015 01:53:41 +0300 Subject: KVM: x86: Support for disabling quirks Introducing KVM_CAP_DISABLE_QUIRKS for disabling x86 quirks that were previous created in order to overcome QEMU issues. Those issue were mostly result of invalid VM BIOS. Currently there are two quirks that can be disabled: 1. KVM_QUIRK_LINT0_REENABLED - LINT0 was enabled after boot 2. KVM_QUIRK_CD_NW_CLEARED - CD and NW are cleared after boot These two issues are already resolved in recent releases of QEMU, and would therefore be disabled by QEMU. Signed-off-by: Nadav Amit Message-Id: <1428879221-29996-1-git-send-email-namit@cs.technion.ac.il> [Report capability from KVM_CHECK_EXTENSION too. - Paolo] Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/api.txt | 3 ++- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/include/uapi/asm/kvm.h | 3 +++ arch/x86/kvm/lapic.c | 5 +++-- arch/x86/kvm/svm.c | 3 ++- arch/x86/kvm/x86.c | 30 ++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 1 + 7 files changed, 43 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 9fa2bf8c3f6f..695544420ff2 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -959,7 +959,8 @@ documentation when it pops into existence). 4.37 KVM_ENABLE_CAP Capability: KVM_CAP_ENABLE_CAP, KVM_CAP_ENABLE_CAP_VM -Architectures: ppc, s390 +Architectures: x86 (only KVM_CAP_ENABLE_CAP_VM), + mips (only KVM_CAP_ENABLE_CAP), ppc, s390 Type: vcpu ioctl, vm ioctl (with KVM_CAP_ENABLE_CAP_VM) Parameters: struct kvm_enable_cap (in) Returns: 0 on success; -1 on error diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index dea2e7e962e3..f80ad591aa61 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -635,6 +635,8 @@ struct kvm_arch { #endif bool boot_vcpu_runs_old_kvmclock; + + u64 disabled_quirks; }; struct kvm_vm_stat { diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h index d7dcef58aefa..2fec75e4b1e1 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -345,4 +345,7 @@ struct kvm_xcrs { struct kvm_sync_regs { }; +#define KVM_QUIRK_LINT0_REENABLED (1 << 0) +#define KVM_QUIRK_CD_NW_CLEARED (1 << 1) + #endif /* _ASM_X86_KVM_H */ diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 629af0f1c5c4..4071eb161c8f 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1577,8 +1577,9 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu) for (i = 0; i < APIC_LVT_NUM; i++) apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); apic->lapic_timer.timer_mode = 0; - apic_set_reg(apic, APIC_LVT0, - SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); + if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_LINT0_REENABLED)) + apic_set_reg(apic, APIC_LVT0, + SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); apic_set_reg(apic, APIC_DFR, 0xffffffffU); apic_set_spiv(apic, 0xff); diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index ce741b8650f6..46299dac7c6d 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1575,7 +1575,8 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) * does not do it - this results in some delay at * reboot */ - cr0 &= ~(X86_CR0_CD | X86_CR0_NW); + if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_CD_NW_CLEARED)) + cr0 &= ~(X86_CR0_CD | X86_CR0_NW); svm->vmcb->save.cr0 = cr0; mark_dirty(svm->vmcb, VMCB_CR); update_cr0_intercept(svm); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7a959be0aebc..0435b653f583 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2800,6 +2800,8 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_HYPERV_TIME: case KVM_CAP_IOAPIC_POLARITY_IGNORED: case KVM_CAP_TSC_DEADLINE_TIMER: + case KVM_CAP_ENABLE_CAP_VM: + case KVM_CAP_DISABLE_QUIRKS: #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT case KVM_CAP_ASSIGN_DEV_IRQ: case KVM_CAP_PCI_2_3: @@ -3847,6 +3849,26 @@ int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, return 0; } +static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, + struct kvm_enable_cap *cap) +{ + int r; + + if (cap->flags) + return -EINVAL; + + switch (cap->cap) { + case KVM_CAP_DISABLE_QUIRKS: + kvm->arch.disabled_quirks = cap->args[0]; + r = 0; + break; + default: + r = -EINVAL; + break; + } + return r; +} + long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { @@ -4099,7 +4121,15 @@ long kvm_arch_vm_ioctl(struct file *filp, r = 0; break; } + case KVM_ENABLE_CAP: { + struct kvm_enable_cap cap; + r = -EFAULT; + if (copy_from_user(&cap, argp, sizeof(cap))) + goto out; + r = kvm_vm_ioctl_enable_cap(kvm, &cap); + break; + } default: r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 4b60056776d1..75bd9f7fd846 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -814,6 +814,7 @@ struct kvm_ppc_smmu_info { #define KVM_CAP_S390_INJECT_IRQ 113 #define KVM_CAP_S390_IRQ_STATE 114 #define KVM_CAP_PPC_HWRNG 115 +#define KVM_CAP_DISABLE_QUIRKS 116 #ifdef KVM_CAP_IRQ_ROUTING -- cgit v1.2.3 From 1038a6872802bb4a07f627162ff989bf49e2e5cc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 30 Apr 2015 15:15:50 +0200 Subject: iio: magnetometer: support for lsm303dlh The LSM303DLH accelerometer/magnetometer has a different device identification method than using register 0x0f, instead three registers contain a magic value. We rely on WhoAmI to be zero for this variant. Signed-off-by: Linus Walleij Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/st-sensors.txt | 1 + drivers/iio/magnetometer/st_magn.h | 1 + drivers/iio/magnetometer/st_magn_core.c | 116 +++++++++++++++++++++ drivers/iio/magnetometer/st_magn_i2c.c | 5 + 4 files changed, 123 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index d2aaca974531..fb5e0c2d18b5 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -45,6 +45,7 @@ Gyroscopes: - st,lsm330-gyro Magnetometers: +- st,lsm303dlh-magn - st,lsm303dlhc-magn - st,lsm303dlm-magn - st,lis3mdl-magn diff --git a/drivers/iio/magnetometer/st_magn.h b/drivers/iio/magnetometer/st_magn.h index 7e81d00ef0c3..287691ca56c1 100644 --- a/drivers/iio/magnetometer/st_magn.h +++ b/drivers/iio/magnetometer/st_magn.h @@ -14,6 +14,7 @@ #include #include +#define LSM303DLH_MAGN_DEV_NAME "lsm303dlh_magn" #define LSM303DLHC_MAGN_DEV_NAME "lsm303dlhc_magn" #define LSM303DLM_MAGN_DEV_NAME "lsm303dlm_magn" #define LIS3MDL_MAGN_DEV_NAME "lis3mdl" diff --git a/drivers/iio/magnetometer/st_magn_core.c b/drivers/iio/magnetometer/st_magn_core.c index 8ade473f99fe..73574d912e7c 100644 --- a/drivers/iio/magnetometer/st_magn_core.c +++ b/drivers/iio/magnetometer/st_magn_core.c @@ -45,6 +45,46 @@ #define ST_MAGN_FS_AVL_12000MG 12000 #define ST_MAGN_FS_AVL_16000MG 16000 +/* CUSTOM VALUES FOR SENSOR 0 */ +#define ST_MAGN_0_ODR_ADDR 0x00 +#define ST_MAGN_0_ODR_MASK 0x1c +#define ST_MAGN_0_ODR_AVL_1HZ_VAL 0x00 +#define ST_MAGN_0_ODR_AVL_2HZ_VAL 0x01 +#define ST_MAGN_0_ODR_AVL_3HZ_VAL 0x02 +#define ST_MAGN_0_ODR_AVL_8HZ_VAL 0x03 +#define ST_MAGN_0_ODR_AVL_15HZ_VAL 0x04 +#define ST_MAGN_0_ODR_AVL_30HZ_VAL 0x05 +#define ST_MAGN_0_ODR_AVL_75HZ_VAL 0x06 +#define ST_MAGN_0_ODR_AVL_220HZ_VAL 0x07 +#define ST_MAGN_0_PW_ADDR 0x02 +#define ST_MAGN_0_PW_MASK 0x03 +#define ST_MAGN_0_PW_ON 0x00 +#define ST_MAGN_0_PW_OFF 0x03 +#define ST_MAGN_0_FS_ADDR 0x01 +#define ST_MAGN_0_FS_MASK 0xe0 +#define ST_MAGN_0_FS_AVL_1300_VAL 0x01 +#define ST_MAGN_0_FS_AVL_1900_VAL 0x02 +#define ST_MAGN_0_FS_AVL_2500_VAL 0x03 +#define ST_MAGN_0_FS_AVL_4000_VAL 0x04 +#define ST_MAGN_0_FS_AVL_4700_VAL 0x05 +#define ST_MAGN_0_FS_AVL_5600_VAL 0x06 +#define ST_MAGN_0_FS_AVL_8100_VAL 0x07 +#define ST_MAGN_0_FS_AVL_1300_GAIN_XY 1100 +#define ST_MAGN_0_FS_AVL_1900_GAIN_XY 855 +#define ST_MAGN_0_FS_AVL_2500_GAIN_XY 670 +#define ST_MAGN_0_FS_AVL_4000_GAIN_XY 450 +#define ST_MAGN_0_FS_AVL_4700_GAIN_XY 400 +#define ST_MAGN_0_FS_AVL_5600_GAIN_XY 330 +#define ST_MAGN_0_FS_AVL_8100_GAIN_XY 230 +#define ST_MAGN_0_FS_AVL_1300_GAIN_Z 980 +#define ST_MAGN_0_FS_AVL_1900_GAIN_Z 760 +#define ST_MAGN_0_FS_AVL_2500_GAIN_Z 600 +#define ST_MAGN_0_FS_AVL_4000_GAIN_Z 400 +#define ST_MAGN_0_FS_AVL_4700_GAIN_Z 355 +#define ST_MAGN_0_FS_AVL_5600_GAIN_Z 295 +#define ST_MAGN_0_FS_AVL_8100_GAIN_Z 205 +#define ST_MAGN_0_MULTIREAD_BIT false + /* CUSTOM VALUES FOR SENSOR 1 */ #define ST_MAGN_1_WAI_EXP 0x3c #define ST_MAGN_1_ODR_ADDR 0x00 @@ -150,6 +190,82 @@ static const struct iio_chan_spec st_magn_2_16bit_channels[] = { }; static const struct st_sensor_settings st_magn_sensors_settings[] = { + { + .wai = 0, /* This sensor has no valid WhoAmI report 0 */ + .sensors_supported = { + [0] = LSM303DLH_MAGN_DEV_NAME, + }, + .ch = (struct iio_chan_spec *)st_magn_16bit_channels, + .odr = { + .addr = ST_MAGN_0_ODR_ADDR, + .mask = ST_MAGN_0_ODR_MASK, + .odr_avl = { + { 1, ST_MAGN_0_ODR_AVL_1HZ_VAL, }, + { 2, ST_MAGN_0_ODR_AVL_2HZ_VAL, }, + { 3, ST_MAGN_0_ODR_AVL_3HZ_VAL, }, + { 8, ST_MAGN_0_ODR_AVL_8HZ_VAL, }, + { 15, ST_MAGN_0_ODR_AVL_15HZ_VAL, }, + { 30, ST_MAGN_0_ODR_AVL_30HZ_VAL, }, + { 75, ST_MAGN_0_ODR_AVL_75HZ_VAL, }, + }, + }, + .pw = { + .addr = ST_MAGN_0_PW_ADDR, + .mask = ST_MAGN_0_PW_MASK, + .value_on = ST_MAGN_0_PW_ON, + .value_off = ST_MAGN_0_PW_OFF, + }, + .fs = { + .addr = ST_MAGN_0_FS_ADDR, + .mask = ST_MAGN_0_FS_MASK, + .fs_avl = { + [0] = { + .num = ST_MAGN_FS_AVL_1300MG, + .value = ST_MAGN_0_FS_AVL_1300_VAL, + .gain = ST_MAGN_0_FS_AVL_1300_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_1300_GAIN_Z, + }, + [1] = { + .num = ST_MAGN_FS_AVL_1900MG, + .value = ST_MAGN_0_FS_AVL_1900_VAL, + .gain = ST_MAGN_0_FS_AVL_1900_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_1900_GAIN_Z, + }, + [2] = { + .num = ST_MAGN_FS_AVL_2500MG, + .value = ST_MAGN_0_FS_AVL_2500_VAL, + .gain = ST_MAGN_0_FS_AVL_2500_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_2500_GAIN_Z, + }, + [3] = { + .num = ST_MAGN_FS_AVL_4000MG, + .value = ST_MAGN_0_FS_AVL_4000_VAL, + .gain = ST_MAGN_0_FS_AVL_4000_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_4000_GAIN_Z, + }, + [4] = { + .num = ST_MAGN_FS_AVL_4700MG, + .value = ST_MAGN_0_FS_AVL_4700_VAL, + .gain = ST_MAGN_0_FS_AVL_4700_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_4700_GAIN_Z, + }, + [5] = { + .num = ST_MAGN_FS_AVL_5600MG, + .value = ST_MAGN_0_FS_AVL_5600_VAL, + .gain = ST_MAGN_0_FS_AVL_5600_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_5600_GAIN_Z, + }, + [6] = { + .num = ST_MAGN_FS_AVL_8100MG, + .value = ST_MAGN_0_FS_AVL_8100_VAL, + .gain = ST_MAGN_0_FS_AVL_8100_GAIN_XY, + .gain2 = ST_MAGN_0_FS_AVL_8100_GAIN_Z, + }, + }, + }, + .multi_read_bit = ST_MAGN_0_MULTIREAD_BIT, + .bootime = 2, + }, { .wai = ST_MAGN_1_WAI_EXP, .sensors_supported = { diff --git a/drivers/iio/magnetometer/st_magn_i2c.c b/drivers/iio/magnetometer/st_magn_i2c.c index 92e5c15452a3..5311d8aea8cc 100644 --- a/drivers/iio/magnetometer/st_magn_i2c.c +++ b/drivers/iio/magnetometer/st_magn_i2c.c @@ -20,6 +20,10 @@ #ifdef CONFIG_OF static const struct of_device_id st_magn_of_match[] = { + { + .compatible = "st,lsm303dlh-magn", + .data = LSM303DLH_MAGN_DEV_NAME, + }, { .compatible = "st,lsm303dlhc-magn", .data = LSM303DLHC_MAGN_DEV_NAME, @@ -71,6 +75,7 @@ static int st_magn_i2c_remove(struct i2c_client *client) } static const struct i2c_device_id st_magn_id_table[] = { + { LSM303DLH_MAGN_DEV_NAME }, { LSM303DLHC_MAGN_DEV_NAME }, { LSM303DLM_MAGN_DEV_NAME }, { LIS3MDL_MAGN_DEV_NAME }, -- cgit v1.2.3 From bbfd0ccc598ded2ec9f618f10b5bc54b1130f4d3 Mon Sep 17 00:00:00 2001 From: Michal Malý Date: Wed, 8 Apr 2015 22:56:52 +0200 Subject: HID: hid-lg4ff: Update respective sysfs interface documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update respective sysfs interface documentation - Refer to the sysfs interface for "range" using "/sys/bus/..." - Update contact email address Signed-off-by: Michal Malý Signed-off-by: Jiri Kosina --- Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff b/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff index b3f6a2ac5007..db197a879580 100644 --- a/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff +++ b/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff @@ -1,7 +1,7 @@ -What: /sys/module/hid_logitech/drivers/hid:logitech//range. +What: /sys/bus/hid/drivers/logitech//range Date: July 2011 KernelVersion: 3.2 -Contact: Michal Malý +Contact: Michal Malý Description: Display minimum, maximum and current range of the steering wheel. Writing a value within min and max boundaries sets the range of the wheel. @@ -9,7 +9,7 @@ Description: Display minimum, maximum and current range of the steering What: /sys/bus/hid/drivers/logitech//alternate_modes Date: Feb 2015 KernelVersion: 4.1 -Contact: Michal Malý +Contact: Michal Malý Description: Displays a set of alternate modes supported by a wheel. Each mode is listed as follows: Tag: Mode Name @@ -45,7 +45,7 @@ Description: Displays a set of alternate modes supported by a wheel. Each What: /sys/bus/hid/drivers/logitech//real_id Date: Feb 2015 KernelVersion: 4.1 -Contact: Michal Malý +Contact: Michal Malý Description: Displays the real model of the wheel regardless of any alternate mode the wheel might be switched to. It is a read-only value. -- cgit v1.2.3 From 4ae711f4a37bff6cf501b48d58f9e28b031b02c9 Mon Sep 17 00:00:00 2001 From: Chen Gang Date: Sun, 5 Apr 2015 12:25:44 +0800 Subject: Docs: blackfin: Use new switch macro SAMPLE_IRQ_TIMER instead of IRQ_TIMER5 Not all blackfin machines support IRQ_TIMER5, but all machines support IRQ_TIMER2. So add a switch macro for them. The related error: Documentation/blackfin/gptimers-example.c: In function 'gptimer_example_init': Documentation/blackfin/gptimers-example.c:60:20: error: 'IRQ_TIMER5' undeclared (first use in this function) ret = request_irq(IRQ_TIMER5, gptimer_example_irq, IRQF_SHARED, DRIVER_NAME, &data); ^ Documentation/blackfin/gptimers-example.c:60:20: note: each undeclared identifier is reported only once for each function it appears in Documentation/blackfin/gptimers-example.c: In function 'gptimer_example_exit': Documentation/blackfin/gptimers-example.c:78:11: error: 'IRQ_TIMER5' undeclared (first use in this function) free_irq(IRQ_TIMER5, &data); ^ Also notice about 80 columns limitation. Signed-off-by: Chen Gang Signed-off-by: Jonathan Corbet --- Documentation/blackfin/gptimers-example.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/blackfin/gptimers-example.c b/Documentation/blackfin/gptimers-example.c index b1bd6340e748..283eba993d9d 100644 --- a/Documentation/blackfin/gptimers-example.c +++ b/Documentation/blackfin/gptimers-example.c @@ -17,6 +17,12 @@ #define DRIVER_NAME "gptimer_example" +#ifdef IRQ_TIMER5 +#define SAMPLE_IRQ_TIMER IRQ_TIMER5 +#else +#define SAMPLE_IRQ_TIMER IRQ_TIMER2 +#endif + struct gptimer_data { uint32_t period, width; }; @@ -57,7 +63,8 @@ static int __init gptimer_example_init(void) } /* grab the IRQ for the timer */ - ret = request_irq(IRQ_TIMER5, gptimer_example_irq, IRQF_SHARED, DRIVER_NAME, &data); + ret = request_irq(SAMPLE_IRQ_TIMER, gptimer_example_irq, + IRQF_SHARED, DRIVER_NAME, &data); if (ret) { printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n"); peripheral_free(P_TMR5); @@ -65,7 +72,8 @@ static int __init gptimer_example_init(void) } /* setup the timer and enable it */ - set_gptimer_config(TIMER5_id, WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA); + set_gptimer_config(TIMER5_id, + WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA); enable_gptimers(TIMER5bit); return 0; @@ -75,7 +83,7 @@ module_init(gptimer_example_init); static void __exit gptimer_example_exit(void) { disable_gptimers(TIMER5bit); - free_irq(IRQ_TIMER5, &data); + free_irq(SAMPLE_IRQ_TIMER, &data); peripheral_free(P_TMR5); } module_exit(gptimer_example_exit); -- cgit v1.2.3 From e3aa205aa131d9b6452c51191dae0aac8e6f1fbd Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Mon, 20 Apr 2015 22:15:20 +0200 Subject: Documentation usb serial: fixed how to provide vendor and product id While trying to test a Cinterion GSM/GPS/3G module I had reconfigured the USB interface by mistake and therefore needed to run a different USB driver than CDC-ACM. It turned out that I need the "usbserial" driver. This file is an official description how to use it: Documentation/usb/usb-serial.txt But it is outdated. The parameters vendor= and product= have been superseded by a /sys interface. Here was the solution: https://bbs.archlinux.org/viewtopic.php?id=175499 insmod usbserial vendor=0x#### product=0x#### becomes (first #### is vendor, second is product) modprobe usbserial echo #### #### >/sys/bus/usb-serial/drivers/generic/new_id This patch changes the documentation file to describe the modern variant. Please note that the old one still works (if compiled as module). Signed-off-by: H. Nikolaus Schaller Signed-off-by: Marek Belisko Signed-off-by: Jonathan Corbet --- Documentation/usb/usb-serial.txt | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/usb/usb-serial.txt b/Documentation/usb/usb-serial.txt index 947fa62bccf2..349f3104fa4f 100644 --- a/Documentation/usb/usb-serial.txt +++ b/Documentation/usb/usb-serial.txt @@ -465,12 +465,14 @@ Generic Serial driver device, and does not support any kind of device flow control. All that is required of your device is that it has at least one bulk in endpoint, or one bulk out endpoint. - - To enable the generic driver to recognize your device, build the driver - as a module and load it by the following invocation: + + To enable the generic driver to recognize your device, provide + echo >/sys/bus/usb-serial/drivers/generic/new_id + where the and is replaced with the hex representation of your + device's vendor id and product id. + If the driver is compiled as a module you can also provide one id when + loading the module insmod usbserial vendor=0x#### product=0x#### - where the #### is replaced with the hex representation of your device's - vendor id and product id. This driver has been successfully used to connect to the NetChip USB development board, providing a way to develop USB firmware without -- cgit v1.2.3 From c542a54fcb5591e7637f71fa400065853ce54ee0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 27 Apr 2015 14:51:33 +0200 Subject: clk: emev2: Use generic names for device nodes uart -> serial Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/emev2-clock.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/emev2-clock.txt b/Documentation/devicetree/bindings/clock/emev2-clock.txt index 60bbb1a8c69a..268ca615459e 100644 --- a/Documentation/devicetree/bindings/clock/emev2-clock.txt +++ b/Documentation/devicetree/bindings/clock/emev2-clock.txt @@ -52,7 +52,7 @@ usia_u0_sclk: usia_u0_sclk { Example of consumer: -uart@e1020000 { +serial@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; interrupts = <0 8 0>; -- cgit v1.2.3 From 5665aec631245ff1b6e03fa5efe7383f4ef379cb Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 7 May 2015 19:16:53 +0100 Subject: usb: dwc3: dwc3-st: Update the incorrect DT dwc3 example. There is a subtle typo phys-names should be phy-names. Using the current example means you don't have working usb (as you fail to obtain the phys). Also update the example to use the generic phy type constants which are now used for miphy28. Additionally also remove the unnecessary new line in the example. Signed-off-by: Peter Griffin Acked-by: Rob Herring Acked-by: Maxime Coquelin Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc3-st.txt | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt index f9d70252bbb2..01c71b1258f4 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-st.txt +++ b/Documentation/devicetree/bindings/usb/dwc3-st.txt @@ -49,8 +49,7 @@ st_dwc3: dwc3@8f94000 { st,syscfg = <&syscfg_core>; resets = <&powerdown STIH407_USB3_POWERDOWN>, <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", - "softreset"; + reset-names = "powerdown", "softreset"; #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; @@ -62,7 +61,7 @@ st_dwc3: dwc3@8f94000 { reg = <0x09900000 0x100000>; interrupts = ; dr_mode = "host"; - phys-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>; }; }; -- cgit v1.2.3 From d6d22922d9070b660e3dce0a87a94f0b581e803e Mon Sep 17 00:00:00 2001 From: Andrzej Pietrasiewicz Date: Fri, 6 Feb 2015 13:43:30 +0100 Subject: usb: gadget: rndis: remove the limit of available rndis connections RNDIS function has a limitation on the number of allowed instances. So far it has been RNDIS_MAX_CONFIGS, which happens to be one. In order to eliminate this kind of arbitrary limitation we should not preallocate a predefined (RNDIS_MAX_CONFIGS) array of struct rndis_params instances but instead allow allocating them on demand. This patch allocates struct rndis_params on demand in rndis_register(). Coversly, the structure is free()'d in rndis_deregister(). If CONFIG_USB_GADGET_DEBUG_FILES is set, the proc files are created which is the same behaviour as before, but the moment of creation is delayed until struct rndis_params is actually allocated. rnids_init() and rndis_exit() have nothing to do, so they are eliminated. Signed-off-by: Andrzej Pietrasiewicz Signed-off-by: Felipe Balbi --- Documentation/usb/gadget-testing.txt | 2 - drivers/usb/gadget/function/f_rndis.c | 22 +----- drivers/usb/gadget/function/rndis.c | 140 +++++++++++++++++++--------------- drivers/usb/gadget/function/u_rndis.h | 2 - 4 files changed, 78 insertions(+), 88 deletions(-) (limited to 'Documentation') diff --git a/Documentation/usb/gadget-testing.txt b/Documentation/usb/gadget-testing.txt index 7769eee3b1b5..592678009c15 100644 --- a/Documentation/usb/gadget-testing.txt +++ b/Documentation/usb/gadget-testing.txt @@ -526,8 +526,6 @@ Except for ifname they can be written to until the function is linked to a configuration. The ifname is read-only and contains the name of the interface which was assigned by the net core, e. g. usb0. -By default there can be only 1 RNDIS interface in the system. - Testing the RNDIS function -------------------------- diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c index 2dafe728ca2d..32985dade838 100644 --- a/drivers/usb/gadget/function/f_rndis.c +++ b/drivers/usb/gadget/function/f_rndis.c @@ -1012,26 +1012,6 @@ static struct usb_function *rndis_alloc(struct usb_function_instance *fi) return &rndis->port.func; } -DECLARE_USB_FUNCTION(rndis, rndis_alloc_inst, rndis_alloc); - -static int __init rndis_mod_init(void) -{ - int ret; - - ret = rndis_init(); - if (ret) - return ret; - - return usb_function_register(&rndisusb_func); -} -module_init(rndis_mod_init); - -static void __exit rndis_mod_exit(void) -{ - usb_function_unregister(&rndisusb_func); - rndis_exit(); -} -module_exit(rndis_mod_exit); - +DECLARE_USB_FUNCTION_INIT(rndis, rndis_alloc_inst, rndis_alloc); MODULE_LICENSE("GPL"); MODULE_AUTHOR("David Brownell"); diff --git a/drivers/usb/gadget/function/rndis.c b/drivers/usb/gadget/function/rndis.c index 01a3b5891656..dd6800017ade 100644 --- a/drivers/usb/gadget/function/rndis.c +++ b/drivers/usb/gadget/function/rndis.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -57,10 +58,13 @@ MODULE_PARM_DESC (rndis_debug, "enable debugging"); #define rndis_debug 0 #endif -#define RNDIS_MAX_CONFIGS 1 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES +#define NAME_TEMPLATE "driver/rndis-%03d" -static rndis_params rndis_per_dev_params[RNDIS_MAX_CONFIGS]; +#endif /* CONFIG_USB_GADGET_DEBUG_FILES */ + +static DEFINE_IDA(rndis_ida); /* Driver Version */ static const __le32 rndis_driver_version = cpu_to_le32(1); @@ -69,6 +73,11 @@ static const __le32 rndis_driver_version = cpu_to_le32(1); static rndis_resp_t *rndis_add_response(struct rndis_params *params, u32 length); +#ifdef CONFIG_USB_GADGET_DEBUG_FILES + +static const struct file_operations rndis_proc_fops; + +#endif /* CONFIG_USB_GADGET_DEBUG_FILES */ /* supported OIDs */ static const u32 oid_supported_list[] = @@ -850,38 +859,93 @@ int rndis_msg_parser(struct rndis_params *params, u8 *buf) } EXPORT_SYMBOL_GPL(rndis_msg_parser); +static inline int rndis_get_nr(void) +{ + return ida_simple_get(&rndis_ida, 0, 0, GFP_KERNEL); +} + +static inline void rndis_put_nr(int nr) +{ + ida_simple_remove(&rndis_ida, nr); +} + struct rndis_params *rndis_register(void (*resp_avail)(void *v), void *v) { + struct rndis_params *params; u8 i; if (!resp_avail) return ERR_PTR(-EINVAL); - for (i = 0; i < RNDIS_MAX_CONFIGS; i++) { - if (!rndis_per_dev_params[i].used) { - rndis_per_dev_params[i].used = 1; - rndis_per_dev_params[i].resp_avail = resp_avail; - rndis_per_dev_params[i].v = v; - pr_debug("%s: configNr = %d\n", __func__, i); - return &rndis_per_dev_params[i]; + i = rndis_get_nr(); + if (i < 0) { + pr_debug("failed\n"); + + return ERR_PTR(-ENODEV); + } + + params = kzalloc(sizeof(*params), GFP_KERNEL); + if (!params) { + rndis_put_nr(i); + + return ERR_PTR(-ENOMEM); + } + +#ifdef CONFIG_USB_GADGET_DEBUG_FILES + { + struct proc_dir_entry *proc_entry; + char name[20]; + + sprintf(name, NAME_TEMPLATE, i); + proc_entry = proc_create_data(name, 0660, NULL, + &rndis_proc_fops, params); + if (!proc_entry) { + kfree(params); + rndis_put_nr(i); + + return ERR_PTR(-EIO); } } - pr_debug("failed\n"); +#endif - return ERR_PTR(-ENODEV); + params->confignr = i; + params->used = 1; + params->state = RNDIS_UNINITIALIZED; + params->media_state = RNDIS_MEDIA_STATE_DISCONNECTED; + params->resp_avail = resp_avail; + params->v = v; + INIT_LIST_HEAD(&(params->resp_queue)); + pr_debug("%s: configNr = %d\n", __func__, i); + + return params; } EXPORT_SYMBOL_GPL(rndis_register); void rndis_deregister(struct rndis_params *params) { + u8 i; + pr_debug("%s:\n", __func__); if (!params) return; - params->used = 0; + + i = params->confignr; + +#ifdef CONFIG_USB_GADGET_DEBUG_FILES + { + u8 i; + char name[20]; + + sprintf(name, NAME_TEMPLATE, i); + remove_proc_entry(name, NULL); + } +#endif + + kfree(params); + rndis_put_nr(i); } EXPORT_SYMBOL_GPL(rndis_deregister); - int rndis_set_param_dev(struct rndis_params *params, struct net_device *dev, u16 *cdc_filter) { @@ -1114,54 +1178,4 @@ static const struct file_operations rndis_proc_fops = { #define NAME_TEMPLATE "driver/rndis-%03d" -static struct proc_dir_entry *rndis_connect_state [RNDIS_MAX_CONFIGS]; - #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ - - -int rndis_init(void) -{ - u8 i; - - for (i = 0; i < RNDIS_MAX_CONFIGS; i++) { -#ifdef CONFIG_USB_GADGET_DEBUG_FILES - char name [20]; - - sprintf(name, NAME_TEMPLATE, i); - rndis_connect_state[i] = proc_create_data(name, 0660, NULL, - &rndis_proc_fops, - (void *)(rndis_per_dev_params + i)); - if (!rndis_connect_state[i]) { - pr_debug("%s: remove entries", __func__); - while (i) { - sprintf(name, NAME_TEMPLATE, --i); - remove_proc_entry(name, NULL); - } - pr_debug("\n"); - return -EIO; - } -#endif - rndis_per_dev_params[i].confignr = i; - rndis_per_dev_params[i].used = 0; - rndis_per_dev_params[i].state = RNDIS_UNINITIALIZED; - rndis_per_dev_params[i].media_state - = RNDIS_MEDIA_STATE_DISCONNECTED; - INIT_LIST_HEAD(&(rndis_per_dev_params[i].resp_queue)); - } - - return 0; -} - -void rndis_exit(void) -{ -#ifdef CONFIG_USB_GADGET_DEBUG_FILES - u8 i; - char name[20]; - - for (i = 0; i < RNDIS_MAX_CONFIGS; i++) { - sprintf(name, NAME_TEMPLATE, i); - remove_proc_entry(name, NULL); - } -#endif -} - diff --git a/drivers/usb/gadget/function/u_rndis.h b/drivers/usb/gadget/function/u_rndis.h index e902aa42a297..4eafd5050545 100644 --- a/drivers/usb/gadget/function/u_rndis.h +++ b/drivers/usb/gadget/function/u_rndis.h @@ -39,8 +39,6 @@ struct f_rndis_opts { int refcnt; }; -int rndis_init(void); -void rndis_exit(void); void rndis_borrow_net(struct usb_function_instance *f, struct net_device *net); #endif /* U_RNDIS_H */ -- cgit v1.2.3 From c4b6c26e828f4df30fe3289f35c100088f2ff71d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 7 May 2015 10:14:58 +0200 Subject: dt-bindings: ARM: Mediatek: use more generic node name in examples Use 'clock-controller' and 'power-controller' as node names in the examples rather than the specific names of the units. Signed-off-by: Sascha Hauer Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 2 +- Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 2 +- Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt | 2 +- Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 5af6d7394608..936166fbee09 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -16,7 +16,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: -apmixedsys: apmixedsys@10209000 { +apmixedsys: clock-controller@10209000 { compatible = "mediatek,mt8173-apmixedsys"; reg = <0 0x10209000 0 0x1000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 684da473b3e8..f6cd3e4192ff 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -22,7 +22,7 @@ dt-bindings/reset-controller/mt*-resets.h Example: -infracfg: infracfg@10001000 { +infracfg: power-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index fdb45c6b63de..f25b85499a6f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -22,7 +22,7 @@ dt-bindings/reset-controller/mt*-resets.h Example: -pericfg: pericfg@10003000 { +pericfg: power-controller@10003000 { compatible = "mediatek,mt8173-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index a4252489860d..f9e917994ced 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -16,7 +16,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: -topckgen: topckgen@10000000 { +topckgen: power-controller@10000000 { compatible = "mediatek,mt8173-topckgen"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; -- cgit v1.2.3 From df1027abde561f6e7577bc3278f84707de583c89 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Sun, 19 Apr 2015 06:35:01 +0300 Subject: Documentation/CodingStyle: fix example macro parenthesis imbalance Cc: Bartosz Golaszewski Cc: Andrew Morton Fixes: f2027543b9 ('documentation: update CodingStyle on local variables naming in macros') Signed-off-by: Baruch Siach Signed-off-by: Jonathan Corbet --- Documentation/CodingStyle | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/CodingStyle b/Documentation/CodingStyle index f4b78eafd92a..b713c35f8543 100644 --- a/Documentation/CodingStyle +++ b/Documentation/CodingStyle @@ -670,7 +670,7 @@ functions: typeof(x) ret; \ ret = calc_ret(x); \ (ret); \ -)} +}) ret is a common name for a local variable - __foo_ret is less likely to collide with an existing variable. -- cgit v1.2.3 From 9eb059985a7941d0302c9996de13d258d0355f92 Mon Sep 17 00:00:00 2001 From: Chen Hanxiao Date: Mon, 20 Apr 2015 22:48:23 -0400 Subject: Docs: proc: fix kernel version Change the kernel version in table 1-2 from 3.20 to 4.1 Signed-off-by: Chen Hanxiao Reviewed-by: Nathan Scott Signed-off-by: Jonathan Corbet --- Documentation/filesystems/proc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index c3b6b301d8b0..1cc71558cf97 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -205,7 +205,7 @@ asynchronous manner and the value may not be very precise. To see a precise snapshot of a moment, you can see /proc//smaps file and scan page table. It's slow but very precise. -Table 1-2: Contents of the status files (as of 3.20.0) +Table 1-2: Contents of the status files (as of 4.1) .............................................................................. Field Content Name filename of the executable -- cgit v1.2.3 From f66fa08bf9e59b1231aba9e3c2ec28dcf08f0389 Mon Sep 17 00:00:00 2001 From: Wang Long Date: Thu, 23 Apr 2015 07:47:02 +0800 Subject: Documentation: kasan: fix a typo Fix a couple of typos in the kasan document. Signed-off-by: Wang Long Signed-off-by: Jonathan Corbet --- Documentation/kasan.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/kasan.txt b/Documentation/kasan.txt index 092fc10961fe..063095afa964 100644 --- a/Documentation/kasan.txt +++ b/Documentation/kasan.txt @@ -148,7 +148,7 @@ AddressSanitizer dedicates 1/8 of kernel memory to its shadow memory (e.g. 16TB to cover 128TB on x86_64) and uses direct mapping with a scale and offset to translate a memory address to its corresponding shadow address. -Here is the function witch translate an address to its corresponding shadow +Here is the function which translates an address to its corresponding shadow address: static inline void *kasan_mem_to_shadow(const void *addr) -- cgit v1.2.3 From c0d2143dd139e70abba0b8b4bb0fc51c44cc0ac5 Mon Sep 17 00:00:00 2001 From: Chen Hanxiao Date: Fri, 24 Apr 2015 03:44:17 -0400 Subject: docs: add VmPMD description in proc commit dc6c9a35b66b ("mm: account pmd page tables to the process") add VmPMD in /proc/PID/status. This patch add a description in proc.txt for it. Signed-off-by: Chen Hanxiao Acked-by: Kirill A. Shutemov Signed-off-by: Jonathan Corbet --- Documentation/filesystems/proc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index 1cc71558cf97..6f7fafde0884 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -235,6 +235,7 @@ Table 1-2: Contents of the status files (as of 4.1) VmExe size of text segment VmLib size of shared library code VmPTE size of page table entries + VmPMD size of second level page tables VmSwap size of swap usage (the number of referred swapents) Threads number of threads SigQ number of signals queued/max. number for queue -- cgit v1.2.3 From f008db8c00c18d3125ca551e6961e7bd9aba6503 Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Wed, 6 May 2015 11:31:31 +0200 Subject: dmaengine: sun6i: Add support for Allwinner H3 (sun8i) variant The H3 SoC has the same dma engine as the A31 (sun6i), with a reduced amount of endpoints and physical channels. Add the proper config data and compatible string to support it. Signed-off-by: Jens Kuske Acked-by: Maxime Ripard Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/sun6i-dma.txt | 5 ++++- drivers/dma/sun6i-dma.c | 12 ++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt index 9cdcba24d7c3..d13c136cef8c 100644 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt @@ -4,7 +4,10 @@ This driver follows the generic DMA bindings defined in dma.txt. Required properties: -- compatible: Must be "allwinner,sun6i-a31-dma" or "allwinner,sun8i-a23-dma" +- compatible: Must be one of + "allwinner,sun6i-a31-dma" + "allwinner,sun8i-a23-dma" + "allwinner,sun8i-h3-dma" - reg: Should contain the registers base address and length - interrupts: Should contain a reference to the interrupt used by this device - clocks: Should contain a reference to the parent AHB clock diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 11e536586812..842ff97c2cfb 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -891,9 +891,21 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .nr_max_vchans = 37, }; +/* + * The H3 has 12 physical channels, a maximum DRQ port id of 27, + * and a total of 34 usable source and destination endpoints. + */ + +static struct sun6i_dma_config sun8i_h3_dma_cfg = { + .nr_max_channels = 12, + .nr_max_requests = 27, + .nr_max_vchans = 34, +}; + static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg }, + { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, { /* sentinel */ } }; -- cgit v1.2.3 From 13dd92bb4599b5655cafe1f2c0365396a096b94a Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 6 May 2015 15:22:36 +0100 Subject: ARM: 8354/1: Documentation: devicetree: root node serial-number property documentation Open firmware is already using the serial-number property for passing the device's serial number from the bootloader to the kernel. In addition, lshw already has support for scanning this property. The serial number is a string that somewhat represents the device's serial number. It might come from some form of storage (e.g. an eeprom) and be programmed at factory-time by the manufacturer or come from identification bits available in e.g. the SoC (note that the soc_id property in the SoC bus should hold a full account of those bits). The serial number is taken as-is from the bootloader, so it is up to the bootloader to define where the serial number comes from and what length it should be. Some use cases for the serial number require it to have a maximum length (e.g. for USB serial number) and some other cases imply more restrictions on what the serial number should look like (e.g. in Android, the ro.serialno property is usually a 16-bytes (plus one null byte) representation of a 64 bit number). Signed-off-by: Paul Kocialkowski Acked-by: Rob Herring Signed-off-by: Russell King --- Documentation/devicetree/booting-without-of.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt index e49e423268c0..04d34f6a58f3 100644 --- a/Documentation/devicetree/booting-without-of.txt +++ b/Documentation/devicetree/booting-without-of.txt @@ -856,6 +856,10 @@ address which can extend beyond that limit. name may clash with standard defined ones, you prefix them with your vendor name and a comma. + Additional properties for the root node: + + - serial-number : a string representing the device's serial number + b) The /cpus node This node is the parent of all individual CPU nodes. It doesn't -- cgit v1.2.3 From 40579e0b88580cb8fd53218635ab0afbdb3a4919 Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Thu, 7 May 2015 21:29:31 +0200 Subject: ASoC: gtm601: Document GTM601 bindings Add small documentation for GTM601 UMTS modem audio interface. Signed-off-by: Marek Belisko Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/gtm601.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/gtm601.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/gtm601.txt b/Documentation/devicetree/bindings/sound/gtm601.txt new file mode 100644 index 000000000000..5efc8c068de0 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/gtm601.txt @@ -0,0 +1,13 @@ +GTM601 UMTS modem audio interface CODEC + +This device has no configuration interface. Sample rate is fixed - 8kHz. + +Required properties: + + - compatible : "option,gtm601" + +Example: + +codec: gtm601_codec { + compatible = "option,gtm601"; +}; -- cgit v1.2.3 From 4d10da13467e223441d3b081eb70e91149ea5da9 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Fri, 8 May 2015 16:02:43 -0700 Subject: Input: add TI drv2665 haptics driver Add the TI drv2665 piezo haptic driver. This haptics IC requires the data to be streamed to the FIFO for continuous output. Datasheet can be found at: http://www.ti.com/product/drv2665 Signed-off-by: Dan Murphy Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/ti,drv2665.txt | 17 ++ drivers/input/misc/Kconfig | 11 + drivers/input/misc/Makefile | 1 + drivers/input/misc/drv2665.c | 322 +++++++++++++++++++++ 4 files changed, 351 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/ti,drv2665.txt create mode 100644 drivers/input/misc/drv2665.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/input/ti,drv2665.txt b/Documentation/devicetree/bindings/input/ti,drv2665.txt new file mode 100644 index 000000000000..1ba97ac04305 --- /dev/null +++ b/Documentation/devicetree/bindings/input/ti,drv2665.txt @@ -0,0 +1,17 @@ +* Texas Instruments - drv2665 Haptics driver + +Required properties: + - compatible - "ti,drv2665" - DRV2665 + - reg - I2C slave address + - vbat-supply - Required supply regulator + +Example: + +haptics: haptics@59 { + compatible = "ti,drv2665"; + reg = <0x59>; + vbat-supply = <&vbat>; +}; + +For more product information please see the link below: +http://www.ti.com/product/drv2665 diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 7838f1a06856..e5c4de279001 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -775,6 +775,17 @@ config INPUT_DRV260X_HAPTICS To compile this driver as a module, choose M here: the module will be called drv260x-haptics. +config INPUT_DRV2665_HAPTICS + tristate "TI DRV2665 haptics support" + depends on INPUT && I2C + select INPUT_FF_MEMLESS + select REGMAP_I2C + help + Say Y to enable support for the TI DRV2665 haptics driver. + + To compile this driver as a module, choose M here: the + module will be called drv2665-haptics. + config INPUT_DRV2667_HAPTICS tristate "TI DRV2667 haptics support" depends on INPUT && I2C diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 78ba4c1b8532..d3179472474d 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_INPUT_DA9055_ONKEY) += da9055_onkey.o obj-$(CONFIG_INPUT_DM355EVM) += dm355evm_keys.o obj-$(CONFIG_INPUT_E3X0_BUTTON) += e3x0-button.o obj-$(CONFIG_INPUT_DRV260X_HAPTICS) += drv260x.o +obj-$(CONFIG_INPUT_DRV2665_HAPTICS) += drv2665.o obj-$(CONFIG_INPUT_DRV2667_HAPTICS) += drv2667.o obj-$(CONFIG_INPUT_GP2A) += gp2ap002a00f.o obj-$(CONFIG_INPUT_GPIO_BEEPER) += gpio-beeper.o diff --git a/drivers/input/misc/drv2665.c b/drivers/input/misc/drv2665.c new file mode 100644 index 000000000000..0afaa33de07d --- /dev/null +++ b/drivers/input/misc/drv2665.c @@ -0,0 +1,322 @@ +/* + * DRV2665 haptics driver family + * + * Author: Dan Murphy + * + * Copyright: (C) 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Contol registers */ +#define DRV2665_STATUS 0x00 +#define DRV2665_CTRL_1 0x01 +#define DRV2665_CTRL_2 0x02 +#define DRV2665_FIFO 0x0b + +/* Status Register */ +#define DRV2665_FIFO_FULL BIT(0) +#define DRV2665_FIFO_EMPTY BIT(1) + +/* Control 1 Register */ +#define DRV2665_25_VPP_GAIN 0x00 +#define DRV2665_50_VPP_GAIN 0x01 +#define DRV2665_75_VPP_GAIN 0x02 +#define DRV2665_100_VPP_GAIN 0x03 +#define DRV2665_DIGITAL_IN 0xfc +#define DRV2665_ANALOG_IN BIT(2) + +/* Control 2 Register */ +#define DRV2665_BOOST_EN BIT(1) +#define DRV2665_STANDBY BIT(6) +#define DRV2665_DEV_RST BIT(7) +#define DRV2665_5_MS_IDLE_TOUT 0x00 +#define DRV2665_10_MS_IDLE_TOUT 0x04 +#define DRV2665_15_MS_IDLE_TOUT 0x08 +#define DRV2665_20_MS_IDLE_TOUT 0x0c + +/** + * struct drv2665_data - + * @input_dev - Pointer to the input device + * @client - Pointer to the I2C client + * @regmap - Register map of the device + * @work - Work item used to off load the enable/disable of the vibration + * @regulator - Pointer to the regulator for the IC + */ +struct drv2665_data { + struct input_dev *input_dev; + struct i2c_client *client; + struct regmap *regmap; + struct work_struct work; + struct regulator *regulator; +}; + +/* 8kHz Sine wave to stream to the FIFO */ +static const u8 drv2665_sine_wave_form[] = { + 0x00, 0x10, 0x20, 0x2e, 0x3c, 0x48, 0x53, 0x5b, 0x61, 0x65, 0x66, + 0x65, 0x61, 0x5b, 0x53, 0x48, 0x3c, 0x2e, 0x20, 0x10, + 0x00, 0xf0, 0xe0, 0xd2, 0xc4, 0xb8, 0xad, 0xa5, 0x9f, 0x9b, 0x9a, + 0x9b, 0x9f, 0xa5, 0xad, 0xb8, 0xc4, 0xd2, 0xe0, 0xf0, 0x00, +}; + +static struct reg_default drv2665_reg_defs[] = { + { DRV2665_STATUS, 0x02 }, + { DRV2665_CTRL_1, 0x28 }, + { DRV2665_CTRL_2, 0x40 }, + { DRV2665_FIFO, 0x00 }, +}; + +static void drv2665_worker(struct work_struct *work) +{ + struct drv2665_data *haptics = + container_of(work, struct drv2665_data, work); + unsigned int read_buf; + int error; + + error = regmap_read(haptics->regmap, DRV2665_STATUS, &read_buf); + if (error) { + dev_err(&haptics->client->dev, + "Failed to read status: %d\n", error); + return; + } + + if (read_buf & DRV2665_FIFO_EMPTY) { + error = regmap_bulk_write(haptics->regmap, + DRV2665_FIFO, + drv2665_sine_wave_form, + ARRAY_SIZE(drv2665_sine_wave_form)); + if (error) { + dev_err(&haptics->client->dev, + "Failed to write FIFO: %d\n", error); + return; + } + } +} + +static int drv2665_haptics_play(struct input_dev *input, void *data, + struct ff_effect *effect) +{ + struct drv2665_data *haptics = input_get_drvdata(input); + + schedule_work(&haptics->work); + + return 0; +} + +static void drv2665_close(struct input_dev *input) +{ + struct drv2665_data *haptics = input_get_drvdata(input); + int error; + + cancel_work_sync(&haptics->work); + + error = regmap_update_bits(haptics->regmap, + DRV2665_CTRL_2, DRV2665_STANDBY, 1); + if (error) + dev_err(&haptics->client->dev, + "Failed to enter standby mode: %d\n", error); +} + +static const struct reg_default drv2665_init_regs[] = { + { DRV2665_CTRL_2, 0 | DRV2665_10_MS_IDLE_TOUT }, + { DRV2665_CTRL_1, DRV2665_25_VPP_GAIN }, +}; + +static int drv2665_init(struct drv2665_data *haptics) +{ + int error; + + error = regmap_register_patch(haptics->regmap, + drv2665_init_regs, + ARRAY_SIZE(drv2665_init_regs)); + if (error) { + dev_err(&haptics->client->dev, + "Failed to write init registers: %d\n", + error); + return error; + } + + return 0; +} + +static const struct regmap_config drv2665_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = DRV2665_FIFO, + .reg_defaults = drv2665_reg_defs, + .num_reg_defaults = ARRAY_SIZE(drv2665_reg_defs), + .cache_type = REGCACHE_NONE, +}; + +static int drv2665_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct drv2665_data *haptics; + int error; + + haptics = devm_kzalloc(&client->dev, sizeof(*haptics), GFP_KERNEL); + if (!haptics) + return -ENOMEM; + + haptics->regulator = devm_regulator_get(&client->dev, "vbat"); + if (IS_ERR(haptics->regulator)) { + error = PTR_ERR(haptics->regulator); + dev_err(&client->dev, + "unable to get regulator, error: %d\n", error); + return error; + } + + haptics->input_dev = devm_input_allocate_device(&client->dev); + if (!haptics->input_dev) { + dev_err(&client->dev, "Failed to allocate input device\n"); + return -ENOMEM; + } + + haptics->input_dev->name = "drv2665:haptics"; + haptics->input_dev->dev.parent = client->dev.parent; + haptics->input_dev->close = drv2665_close; + input_set_drvdata(haptics->input_dev, haptics); + input_set_capability(haptics->input_dev, EV_FF, FF_RUMBLE); + + error = input_ff_create_memless(haptics->input_dev, NULL, + drv2665_haptics_play); + if (error) { + dev_err(&client->dev, "input_ff_create() failed: %d\n", + error); + return error; + } + + INIT_WORK(&haptics->work, drv2665_worker); + + haptics->client = client; + i2c_set_clientdata(client, haptics); + + haptics->regmap = devm_regmap_init_i2c(client, &drv2665_regmap_config); + if (IS_ERR(haptics->regmap)) { + error = PTR_ERR(haptics->regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + error); + return error; + } + + error = drv2665_init(haptics); + if (error) { + dev_err(&client->dev, "Device init failed: %d\n", error); + return error; + } + + error = input_register_device(haptics->input_dev); + if (error) { + dev_err(&client->dev, "couldn't register input device: %d\n", + error); + return error; + } + + return 0; +} + +static int __maybe_unused drv2665_suspend(struct device *dev) +{ + struct drv2665_data *haptics = dev_get_drvdata(dev); + int ret = 0; + + mutex_lock(&haptics->input_dev->mutex); + + if (haptics->input_dev->users) { + ret = regmap_update_bits(haptics->regmap, DRV2665_CTRL_2, + DRV2665_STANDBY, 1); + if (ret) { + dev_err(dev, "Failed to set standby mode\n"); + regulator_disable(haptics->regulator); + goto out; + } + + ret = regulator_disable(haptics->regulator); + if (ret) { + dev_err(dev, "Failed to disable regulator\n"); + regmap_update_bits(haptics->regmap, + DRV2665_CTRL_2, + DRV2665_STANDBY, 0); + } + } +out: + mutex_unlock(&haptics->input_dev->mutex); + return ret; +} + +static int __maybe_unused drv2665_resume(struct device *dev) +{ + struct drv2665_data *haptics = dev_get_drvdata(dev); + int ret = 0; + + mutex_lock(&haptics->input_dev->mutex); + + if (haptics->input_dev->users) { + ret = regulator_enable(haptics->regulator); + if (ret) { + dev_err(dev, "Failed to enable regulator\n"); + goto out; + } + + ret = regmap_update_bits(haptics->regmap, DRV2665_CTRL_2, + DRV2665_STANDBY, 0); + if (ret) { + dev_err(dev, "Failed to unset standby mode\n"); + regulator_disable(haptics->regulator); + goto out; + } + + } + +out: + mutex_unlock(&haptics->input_dev->mutex); + return ret; +} + +static SIMPLE_DEV_PM_OPS(drv2665_pm_ops, drv2665_suspend, drv2665_resume); + +static const struct i2c_device_id drv2665_id[] = { + { "drv2665", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, drv2665_id); + +#ifdef CONFIG_OF +static const struct of_device_id drv2665_of_match[] = { + { .compatible = "ti,drv2665", }, + { } +}; +MODULE_DEVICE_TABLE(of, drv2665_of_match); +#endif + +static struct i2c_driver drv2665_driver = { + .probe = drv2665_probe, + .driver = { + .name = "drv2665-haptics", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(drv2665_of_match), + .pm = &drv2665_pm_ops, + }, + .id_table = drv2665_id, +}; +module_i2c_driver(drv2665_driver); + +MODULE_DESCRIPTION("TI DRV2665 haptics driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Dan Murphy "); -- cgit v1.2.3 From 56f13c0d9524c5816f5dc9c91b9d766d6b1064ca Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 9 Apr 2015 12:35:47 +0300 Subject: dmaengine: of_dma: Support for DMA routers DMA routers are transparent devices used to mux DMA requests from peripherals to DMA controllers. They are used when the SoC integrates more devices with DMA requests then their controller can handle. DRA7x is one example of such SoC, where the sDMA can hanlde 128 DMA request lines, but in SoC level it has 205 DMA requests. The of_dma_router will be registered as of_dma_controller with special xlate function and additional parameters. The driver for the router is responsible to craft the dma_spec (in the of_dma_route_allocate callback) which can be used to requests a DMA channel from the real DMA controller. This way the router can be transparent for the system while remaining generic enough to be used in different environments. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/dma.txt | 28 +++++++++ drivers/dma/dmaengine.c | 7 +++ drivers/dma/of-dma.c | 89 +++++++++++++++++++++++++++ include/linux/dmaengine.h | 17 +++++ include/linux/of_dma.h | 21 +++++++ 5 files changed, 162 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt index 82104271e754..6312fb00ce8d 100644 --- a/Documentation/devicetree/bindings/dma/dma.txt +++ b/Documentation/devicetree/bindings/dma/dma.txt @@ -31,6 +31,34 @@ Example: dma-requests = <127>; }; +* DMA router + +DMA routers are transparent IP blocks used to route DMA request lines from +devices to the DMA controller. Some SoCs (like TI DRA7x) have more peripherals +integrated with DMA requests than what the DMA controller can handle directly. + +Required property: +- dma-masters: phandle of the DMA controller or list of phandles for + the DMA controllers the router can direct the signal to. +- #dma-cells: Must be at least 1. Used to provide DMA router specific + information. See DMA client binding below for more + details. + +Optional properties: +- dma-requests: Number of incoming request lines the router can handle. +- In the node pointed by the dma-masters: + - dma-requests: The router driver might need to look for this in order + to configure the routing. + +Example: + sdma_xbar: dma-router@4a002b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0x4a002b78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; * DMA client diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 0e035a8cf401..9e5949696b1b 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -267,6 +267,13 @@ static void dma_chan_put(struct dma_chan *chan) /* This channel is not in use anymore, free it */ if (!chan->client_count && chan->device->device_free_chan_resources) chan->device->device_free_chan_resources(chan); + + /* If the channel is used via a DMA request router, free the mapping */ + if (chan->router && chan->router->route_free) { + chan->router->route_free(chan->router->dev, chan->route_data); + chan->router = NULL; + chan->route_data = NULL; + } } enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c index cbd4a8aff120..1e1f2986eba8 100644 --- a/drivers/dma/of-dma.c +++ b/drivers/dma/of-dma.c @@ -44,6 +44,50 @@ static struct of_dma *of_dma_find_controller(struct of_phandle_args *dma_spec) return NULL; } +/** + * of_dma_router_xlate - translation function for router devices + * @dma_spec: pointer to DMA specifier as found in the device tree + * @of_dma: pointer to DMA controller data (router information) + * + * The function creates new dma_spec to be passed to the router driver's + * of_dma_route_allocate() function to prepare a dma_spec which will be used + * to request channel from the real DMA controller. + */ +static struct dma_chan *of_dma_router_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct dma_chan *chan; + struct of_dma *ofdma_target; + struct of_phandle_args dma_spec_target; + void *route_data; + + /* translate the request for the real DMA controller */ + memcpy(&dma_spec_target, dma_spec, sizeof(dma_spec_target)); + route_data = ofdma->of_dma_route_allocate(&dma_spec_target, ofdma); + if (IS_ERR(route_data)) + return NULL; + + ofdma_target = of_dma_find_controller(&dma_spec_target); + if (!ofdma_target) + return NULL; + + chan = ofdma_target->of_dma_xlate(&dma_spec_target, ofdma_target); + if (chan) { + chan->router = ofdma->dma_router; + chan->route_data = route_data; + } else { + ofdma->dma_router->route_free(ofdma->dma_router->dev, + route_data); + } + + /* + * Need to put the node back since the ofdma->of_dma_route_allocate + * has taken it for generating the new, translated dma_spec + */ + of_node_put(dma_spec_target.np); + return chan; +} + /** * of_dma_controller_register - Register a DMA controller to DT DMA helpers * @np: device node of DMA controller @@ -109,6 +153,51 @@ void of_dma_controller_free(struct device_node *np) } EXPORT_SYMBOL_GPL(of_dma_controller_free); +/** + * of_dma_router_register - Register a DMA router to DT DMA helpers as a + * controller + * @np: device node of DMA router + * @of_dma_route_allocate: setup function for the router which need to + * modify the dma_spec for the DMA controller to + * use and to set up the requested route. + * @dma_router: pointer to dma_router structure to be used when + * the route need to be free up. + * + * Returns 0 on success or appropriate errno value on error. + * + * Allocated memory should be freed with appropriate of_dma_controller_free() + * call. + */ +int of_dma_router_register(struct device_node *np, + void *(*of_dma_route_allocate) + (struct of_phandle_args *, struct of_dma *), + struct dma_router *dma_router) +{ + struct of_dma *ofdma; + + if (!np || !of_dma_route_allocate || !dma_router) { + pr_err("%s: not enough information provided\n", __func__); + return -EINVAL; + } + + ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL); + if (!ofdma) + return -ENOMEM; + + ofdma->of_node = np; + ofdma->of_dma_xlate = of_dma_router_xlate; + ofdma->of_dma_route_allocate = of_dma_route_allocate; + ofdma->dma_router = dma_router; + + /* Now queue of_dma controller structure in list */ + mutex_lock(&of_dma_lock); + list_add_tail(&ofdma->of_dma_controllers, &of_dma_list); + mutex_unlock(&of_dma_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(of_dma_router_register); + /** * of_dma_match_channel - Check if a DMA specifier matches name * @np: device node to look for DMA channels diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index ad419757241f..abf63ceabef9 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -221,6 +221,16 @@ struct dma_chan_percpu { unsigned long bytes_transferred; }; +/** + * struct dma_router - DMA router structure + * @dev: pointer to the DMA router device + * @route_free: function to be called when the route can be disconnected + */ +struct dma_router { + struct device *dev; + void (*route_free)(struct device *dev, void *route_data); +}; + /** * struct dma_chan - devices supply DMA channels, clients use them * @device: ptr to the dma device who supplies this channel, always !%NULL @@ -232,6 +242,8 @@ struct dma_chan_percpu { * @local: per-cpu pointer to a struct dma_chan_percpu * @client_count: how many clients are using this channel * @table_count: number of appearances in the mem-to-mem allocation table + * @router: pointer to the DMA router structure + * @route_data: channel specific data for the router * @private: private data for certain client-channel associations */ struct dma_chan { @@ -247,6 +259,11 @@ struct dma_chan { struct dma_chan_percpu __percpu *local; int client_count; int table_count; + + /* DMA router */ + struct dma_router *router; + void *route_data; + void *private; }; diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h index 56bc026c143f..98ba7525929e 100644 --- a/include/linux/of_dma.h +++ b/include/linux/of_dma.h @@ -23,6 +23,9 @@ struct of_dma { struct device_node *of_node; struct dma_chan *(*of_dma_xlate) (struct of_phandle_args *, struct of_dma *); + void *(*of_dma_route_allocate) + (struct of_phandle_args *, struct of_dma *); + struct dma_router *dma_router; void *of_dma_data; }; @@ -37,12 +40,20 @@ extern int of_dma_controller_register(struct device_node *np, (struct of_phandle_args *, struct of_dma *), void *data); extern void of_dma_controller_free(struct device_node *np); + +extern int of_dma_router_register(struct device_node *np, + void *(*of_dma_route_allocate) + (struct of_phandle_args *, struct of_dma *), + struct dma_router *dma_router); +#define of_dma_router_free of_dma_controller_free + extern struct dma_chan *of_dma_request_slave_channel(struct device_node *np, const char *name); extern struct dma_chan *of_dma_simple_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma); extern struct dma_chan *of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec, struct of_dma *ofdma); + #else static inline int of_dma_controller_register(struct device_node *np, struct dma_chan *(*of_dma_xlate) @@ -56,6 +67,16 @@ static inline void of_dma_controller_free(struct device_node *np) { } +static inline int of_dma_router_register(struct device_node *np, + void *(*of_dma_route_allocate) + (struct of_phandle_args *, struct of_dma *), + struct dma_router *dma_router) +{ + return -ENODEV; +} + +#define of_dma_router_free of_dma_controller_free + static inline struct dma_chan *of_dma_request_slave_channel(struct device_node *np, const char *name) { -- cgit v1.2.3 From 73f67d35b5b96eaf6c5d90fc10527c15b135eda2 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 9 Apr 2015 12:35:48 +0300 Subject: Documentation: devicetree: dma: Binding documentation for TI DMA crossbar The DRA7x has more peripherals with DMA requests than the sDMA can handle: 205 vs 127. All DMA requests are routed through the DMA crossbar, which can be configured to route selected incoming DMA requests to specific request line of the DMA controller. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/ti-dma-crossbar.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt new file mode 100644 index 000000000000..63a48928f3a8 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt @@ -0,0 +1,52 @@ +Texas Instruments DMA Crossbar (DMA request router) + +Required properties: +- compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar +- reg: Memory map for accessing module +- #dma-cells: Should be set to <1>. + Clients should use the crossbar request number (input) +- dma-requests: Number of DMA requests the crossbar can receive +- dma-masters: phandle pointing to the DMA controller + +The DMA controller node need to have the following poroperties: +- dma-requests: Number of DMA requests the controller can handle + +Optional properties: +- ti,dma-safe-map: Safe routing value for unused request lines + +Example: + +/* DMA controller */ +sdma: dma-controller@4a056000 { + compatible = "ti,omap4430-sdma"; + reg = <0x4a056000 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; +}; + +/* DMA crossbar */ +sdma_xbar: dma-router@4a002b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0x4a002b78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; +}; + +/* DMA client */ +uart1: serial@4806a000 { + compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; + dma-names = "tx", "rx"; +}; -- cgit v1.2.3 From 988d6f07fc0a29e392035ba56e3bcfaf7b397d95 Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Wed, 6 May 2015 22:27:15 +0530 Subject: devicetree: Add compatible string for Zynq Ultrascale+ MPSoC Add "cdns,zynqmp-gem" to be used for Zynq Ultrascale+ MPSoC. Signed-off-by: Harini Katakam Reviewed-by: Punnaiah Choudary Kalluri Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index ba19d671e808..8ec5fdf444e9 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -9,6 +9,7 @@ Required properties: the Cadence GEM, or the generic form: "cdns,gem". Use "cdns,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. Use "cdns,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs. + Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. -- cgit v1.2.3 From f1f00d8ff60ca056db3805406507483eeb3794d7 Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Thu, 7 May 2015 16:34:51 +0200 Subject: pktgen: adjust flag NO_TIMESTAMP to be more pktgen compliant Allow flag NO_TIMESTAMP to turn timestamping on again, like other flags, with a negation of the flag like !NO_TIMESTAMP. Also document the option flag NO_TIMESTAMP. Fixes: afb84b626184 ("pktgen: add flag NO_TIMESTAMP to disable timestamping") Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 2 ++ net/core/pktgen.c | 3 +++ 2 files changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index 0344f1d45b37..6199ee6a040b 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -145,6 +145,7 @@ Examples: UDPCSUM, IPSEC # IPsec encapsulation (needs CONFIG_XFRM) NODE_ALLOC # node specific memory allocation + NO_TIMESTAMP # disable timestamping pgset spi SPI_VALUE Set specific SA used to transform packet. @@ -287,6 +288,7 @@ flag UDPCSUM IPSEC NODE_ALLOC + NO_TIMESTAMP dst_min dst_max diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 508155b283dd..43bb21507373 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -1267,6 +1267,9 @@ static ssize_t pktgen_if_write(struct file *file, else if (strcmp(f, "NO_TIMESTAMP") == 0) pkt_dev->flags |= F_NO_TIMESTAMP; + else if (strcmp(f, "!NO_TIMESTAMP") == 0) + pkt_dev->flags &= ~F_NO_TIMESTAMP; + else { sprintf(pg_result, "Flag -:%s:- unknown\nAvailable flags, (prepend ! to un-set flag):\n%s", -- cgit v1.2.3 From 62f64aed622b6055b5fc447e3e421c9351563fc8 Mon Sep 17 00:00:00 2001 From: Alexei Starovoitov Date: Thu, 7 May 2015 16:35:32 +0200 Subject: pktgen: introduce xmit_mode '' Introduce xmit_mode 'netif_receive' for pktgen which generates the packets using familiar pktgen commands, but feeds them into netif_receive_skb() instead of ndo_start_xmit(). Default mode is called 'start_xmit'. It is designed to test netif_receive_skb and ingress qdisc performace only. Make sure to understand how it works before using it for other rx benchmarking. Sample script 'pktgen.sh': \#!/bin/bash function pgset() { local result echo $1 > $PGDEV result=`cat $PGDEV | fgrep "Result: OK:"` if [ "$result" = "" ]; then cat $PGDEV | fgrep Result: fi } [ -z "$1" ] && echo "Usage: $0 DEV" && exit 1 ETH=$1 PGDEV=/proc/net/pktgen/kpktgend_0 pgset "rem_device_all" pgset "add_device $ETH" PGDEV=/proc/net/pktgen/$ETH pgset "xmit_mode netif_receive" pgset "pkt_size 60" pgset "dst 198.18.0.1" pgset "dst_mac 90:e2:ba:ff:ff:ff" pgset "count 10000000" pgset "burst 32" PGDEV=/proc/net/pktgen/pgctrl echo "Running... ctrl^C to stop" pgset "start" echo "Done" cat /proc/net/pktgen/$ETH Usage: $ sudo ./pktgen.sh eth2 ... Result: OK: 232376(c232372+d3) usec, 10000000 (60byte,0frags) 43033682pps 20656Mb/sec (20656167360bps) errors: 10000000 Raw netif_receive_skb speed should be ~43 million packet per second on 3.7Ghz x86 and 'perf report' should look like: 37.69% kpktgend_0 [kernel.vmlinux] [k] __netif_receive_skb_core 25.81% kpktgend_0 [kernel.vmlinux] [k] kfree_skb 7.22% kpktgend_0 [kernel.vmlinux] [k] ip_rcv 5.68% kpktgend_0 [pktgen] [k] pktgen_thread_worker If fib_table_lookup is seen on top, it means skb was processed by the stack. To benchmark netif_receive_skb only make sure that 'dst_mac' of your pktgen script is different from receiving device mac and it will be dropped by ip_rcv Signed-off-by: Alexei Starovoitov Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 7 ++++ net/core/pktgen.c | 82 ++++++++++++++++++++++++++++++++++--- 2 files changed, 84 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index 6199ee6a040b..747faccc4120 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -193,6 +193,10 @@ Examples: pgset "rate 300M" set rate to 300 Mb/s pgset "ratep 1000000" set rate to 1Mpps + pgset "xmit_mode netif_receive" RX inject into stack netif_receive_skb() + Works with "burst" but not with "clone_skb". + Default xmit_mode is "start_xmit". + Sample scripts ============== @@ -310,6 +314,9 @@ flowlen rate ratep +xmit_mode + + References: ftp://robur.slu.se/pub/Linux/net-development/pktgen-testing/ ftp://robur.slu.se/pub/Linux/net-development/pktgen-testing/examples/ diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 43bb21507373..8f2687da058e 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -210,6 +210,10 @@ #define T_REMDEVALL (1<<2) /* Remove all devs */ #define T_REMDEV (1<<3) /* Remove one dev */ +/* Xmit modes */ +#define M_START_XMIT 0 /* Default normal TX */ +#define M_NETIF_RECEIVE 1 /* Inject packets into stack */ + /* If lock -- protects updating of if_list */ #define if_lock(t) spin_lock(&(t->if_lock)); #define if_unlock(t) spin_unlock(&(t->if_lock)); @@ -251,13 +255,14 @@ struct pktgen_dev { * we will do a random selection from within the range. */ __u32 flags; - int removal_mark; /* non-zero => the device is marked for - * removal by worker thread */ - + int xmit_mode; int min_pkt_size; int max_pkt_size; int pkt_overhead; /* overhead for MPLS, VLANs, IPSEC etc */ int nfrags; + int removal_mark; /* non-zero => the device is marked for + * removal by worker thread */ + struct page *page; u64 delay; /* nano-seconds */ @@ -620,6 +625,9 @@ static int pktgen_if_show(struct seq_file *seq, void *v) if (pkt_dev->node >= 0) seq_printf(seq, " node: %d\n", pkt_dev->node); + if (pkt_dev->xmit_mode == M_NETIF_RECEIVE) + seq_puts(seq, " xmit_mode: netif_receive\n"); + seq_puts(seq, " Flags: "); if (pkt_dev->flags & F_IPV6) @@ -1081,7 +1089,8 @@ static ssize_t pktgen_if_write(struct file *file, if (len < 0) return len; if ((value > 0) && - (!(pkt_dev->odev->priv_flags & IFF_TX_SKB_SHARING))) + ((pkt_dev->xmit_mode == M_NETIF_RECEIVE) || + !(pkt_dev->odev->priv_flags & IFF_TX_SKB_SHARING))) return -ENOTSUPP; i += len; pkt_dev->clone_skb = value; @@ -1134,7 +1143,7 @@ static ssize_t pktgen_if_write(struct file *file, return len; i += len; - if ((value > 1) && + if ((value > 1) && (pkt_dev->xmit_mode == M_START_XMIT) && (!(pkt_dev->odev->priv_flags & IFF_TX_SKB_SHARING))) return -ENOTSUPP; pkt_dev->burst = value < 1 ? 1 : value; @@ -1160,6 +1169,35 @@ static ssize_t pktgen_if_write(struct file *file, sprintf(pg_result, "ERROR: node not possible"); return count; } + if (!strcmp(name, "xmit_mode")) { + char f[32]; + + memset(f, 0, 32); + len = strn_len(&user_buffer[i], sizeof(f) - 1); + if (len < 0) + return len; + + if (copy_from_user(f, &user_buffer[i], len)) + return -EFAULT; + i += len; + + if (strcmp(f, "start_xmit") == 0) { + pkt_dev->xmit_mode = M_START_XMIT; + } else if (strcmp(f, "netif_receive") == 0) { + /* clone_skb set earlier, not supported in this mode */ + if (pkt_dev->clone_skb > 0) + return -ENOTSUPP; + + pkt_dev->xmit_mode = M_NETIF_RECEIVE; + } else { + sprintf(pg_result, + "xmit_mode -:%s:- unknown\nAvailable modes: %s", + f, "start_xmit, netif_receive\n"); + return count; + } + sprintf(pg_result, "OK: xmit_mode=%s", f); + return count; + } if (!strcmp(name, "flag")) { char f[32]; memset(f, 0, 32); @@ -3320,6 +3358,7 @@ static void pktgen_xmit(struct pktgen_dev *pkt_dev) unsigned int burst = ACCESS_ONCE(pkt_dev->burst); struct net_device *odev = pkt_dev->odev; struct netdev_queue *txq; + struct sk_buff *skb; int ret; /* If device is offline, then don't send */ @@ -3357,6 +3396,38 @@ static void pktgen_xmit(struct pktgen_dev *pkt_dev) if (pkt_dev->delay && pkt_dev->last_ok) spin(pkt_dev, pkt_dev->next_tx); + if (pkt_dev->xmit_mode == M_NETIF_RECEIVE) { + skb = pkt_dev->skb; + skb->protocol = eth_type_trans(skb, skb->dev); + atomic_add(burst, &skb->users); + local_bh_disable(); + do { + ret = netif_receive_skb(skb); + if (ret == NET_RX_DROP) + pkt_dev->errors++; + pkt_dev->sofar++; + pkt_dev->seq_num++; + if (atomic_read(&skb->users) != burst) { + /* skb was queued by rps/rfs or taps, + * so cannot reuse this skb + */ + atomic_sub(burst - 1, &skb->users); + /* get out of the loop and wait + * until skb is consumed + */ + pkt_dev->last_ok = 1; + break; + } + /* skb was 'freed' by stack, so clean few + * bits and reuse it + */ +#ifdef CONFIG_NET_CLS_ACT + skb->tc_verd = 0; /* reset reclass/redir ttl */ +#endif + } while (--burst > 0); + goto out; /* Skips xmit_mode M_START_XMIT */ + } + txq = skb_get_tx_queue(odev, pkt_dev->skb); local_bh_disable(); @@ -3404,6 +3475,7 @@ xmit_more: unlock: HARD_TX_UNLOCK(odev, txq); +out: local_bh_enable(); /* If pkt_dev->count is zero, then run forever */ -- cgit v1.2.3 From 42a95584f31c5f11a669f0db72f6b6e9ff00b8d9 Mon Sep 17 00:00:00 2001 From: Irina Tirdea Date: Wed, 29 Apr 2015 21:16:38 +0300 Subject: iio: magn: bmc150_magn: Add devicetree binding documentation Add binding documentation for Bosch BMC150 magnetometer. Signed-off-by: Irina Tirdea Signed-off-by: Jonathan Cameron --- .../bindings/iio/magnetometer/bmc150_magn.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt b/Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt new file mode 100644 index 000000000000..9f263b7df162 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/bmc150_magn.txt @@ -0,0 +1,22 @@ +* Bosch BMC150 magnetometer sensor + +http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS000-04.pdf + +Required properties: + + - compatible : should be "bosch,bmc150_magn" + - reg : the I2C address of the magnetometer + +Optional properties: + + - interrupt-parent : phandle to the parent interrupt controller + - interrupts : interrupt mapping for GPIO IRQ + +Example: + +bmc150_magn@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + interrupt-parent = <&gpio1>; + interrupts = <0 1>; +}; -- cgit v1.2.3 From faaa44955dedc661f083636d816af90975a359ee Mon Sep 17 00:00:00 2001 From: Irina Tirdea Date: Wed, 29 Apr 2015 21:16:39 +0300 Subject: iio: core: Introduce IIO_CHAN_INFO_OVERSAMPLING_RATIO Some magnetometers can perform a number of repetitions in HW for each measurement to increase accuracy. One example is Bosch BMC150: http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS000-04.pdf. Introduce an interface to set the oversampling ratio for these devices. Signed-off-by: Irina Tirdea Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 12 ++++++++++++ drivers/iio/industrialio-core.c | 1 + include/linux/iio/iio.h | 1 + 3 files changed, 14 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 866b4ec4aab6..e46c71fbd047 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -1375,3 +1375,15 @@ Description: The emissivity ratio of the surface in the field of view of the contactless temperature sensor. Emissivity varies from 0 to 1, with 1 being the emissivity of a black body. + +What: /sys/bus/iio/devices/iio:deviceX/in_magn_x_oversampling_ratio +What: /sys/bus/iio/devices/iio:deviceX/in_magn_y_oversampling_ratio +What: /sys/bus/iio/devices/iio:deviceX/in_magn_z_oversampling_ratio +KernelVersion: 4.2 +Contact: linux-iio@vger.kernel.org +Description: + Hardware applied number of measurements for acquiring one + data point. The HW will do [_name]_oversampling_ratio + measurements and return the average value as output data. Each + value resulted from [_name]_oversampling_ratio measurements + is considered as one sample for [_name]_sampling_frequency. diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 7c98bc1504e6..dfa81db3b910 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -129,6 +129,7 @@ static const char * const iio_chan_info_postfix[] = { [IIO_CHAN_INFO_DEBOUNCE_COUNT] = "debounce_count", [IIO_CHAN_INFO_DEBOUNCE_TIME] = "debounce_time", [IIO_CHAN_INFO_CALIBEMISSIVITY] = "calibemissivity", + [IIO_CHAN_INFO_OVERSAMPLING_RATIO] = "oversampling_ratio", }; /** diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index b1e46ae89aa7..058441da4984 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -44,6 +44,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_DEBOUNCE_COUNT, IIO_CHAN_INFO_DEBOUNCE_TIME, IIO_CHAN_INFO_CALIBEMISSIVITY, + IIO_CHAN_INFO_OVERSAMPLING_RATIO, }; enum iio_shared_by { -- cgit v1.2.3 From ee1a81f90f28a5a2c3339ec62b2a6a6d165075d2 Mon Sep 17 00:00:00 2001 From: Varka Bhadram Date: Fri, 24 Apr 2015 14:53:07 +0530 Subject: imu: inv_mpu6050: adds device tree bindings Signed-off-by: Varka Bhadram Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/imu/inv_mpu6050.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt b/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt new file mode 100644 index 000000000000..e4d8f1c52f4a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt @@ -0,0 +1,17 @@ +InvenSense MPU-6050 Six-Axis (Gyro + Accelerometer) MEMS MotionTracking Device + +http://www.invensense.com/mems/gyro/mpu6050.html + +Required properties: + - compatible : should be "invensense,mpu6050" + - reg : the I2C address of the sensor + - interrupt-parent : should be the phandle for the interrupt controller + - interrupts : interrupt mapping for GPIO IRQ + +Example: + mpu6050@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <18 1>; + }; -- cgit v1.2.3 From 680baacbca69d18a6d7315374ad83d05ac9c0977 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 2 May 2015 13:32:22 -0400 Subject: new ->follow_link() and ->put_link() calling conventions a) instead of storing the symlink body (via nd_set_link()) and returning an opaque pointer later passed to ->put_link(), ->follow_link() _stores_ that opaque pointer (into void * passed by address by caller) and returns the symlink body. Returning ERR_PTR() on error, NULL on jump (procfs magic symlinks) and pointer to symlink body for normal symlinks. Stored pointer is ignored in all cases except the last one. Storing NULL for opaque pointer (or not storing it at all) means no call of ->put_link(). b) the body used to be passed to ->put_link() implicitly (via nameidata). Now only the opaque pointer is. In the cases when we used the symlink body to free stuff, ->follow_link() now should store it as opaque pointer in addition to returning it. Signed-off-by: Al Viro --- Documentation/filesystems/Locking | 4 +- Documentation/filesystems/vfs.txt | 4 +- drivers/staging/lustre/lustre/llite/symlink.c | 11 ++--- fs/9p/vfs_inode.c | 13 +++--- fs/9p/vfs_inode_dotl.c | 7 ++- fs/autofs4/symlink.c | 5 +- fs/befs/linuxvfs.c | 35 +++++++------- fs/cifs/cifsfs.h | 2 +- fs/cifs/link.c | 28 ++++++------ fs/configfs/symlink.c | 28 +++++------- fs/ecryptfs/inode.c | 8 ++-- fs/ext4/symlink.c | 9 ++-- fs/f2fs/namei.c | 18 +++----- fs/fuse/dir.c | 19 ++------ fs/gfs2/inode.c | 10 ++-- fs/hostfs/hostfs_kern.c | 15 +++--- fs/hppfs/hppfs.c | 9 ++-- fs/kernfs/symlink.c | 22 ++++----- fs/libfs.c | 12 ++--- fs/namei.c | 66 +++++++++------------------ fs/nfs/symlink.c | 19 +++----- fs/overlayfs/inode.c | 18 ++++---- fs/proc/base.c | 2 +- fs/proc/inode.c | 9 ++-- fs/proc/namespaces.c | 2 +- fs/proc/self.c | 24 +++++----- fs/proc/thread_self.c | 22 ++++----- fs/xfs/xfs_iops.c | 10 ++-- include/linux/fs.h | 12 ++--- include/linux/namei.h | 2 - mm/shmem.c | 23 +++++----- 31 files changed, 195 insertions(+), 273 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 0a926e2ba3ab..7fa6c4ac858c 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -50,8 +50,8 @@ prototypes: int (*rename2) (struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); - void * (*follow_link) (struct dentry *, struct nameidata *); - void (*put_link) (struct dentry *, struct nameidata *, void *); + const char *(*follow_link) (struct dentry *, void **, struct nameidata *); + void (*put_link) (struct dentry *, void *); void (*truncate) (struct inode *); int (*permission) (struct inode *, int, unsigned int); int (*get_acl)(struct inode *, int); diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index 5d833b32bbcd..1c6b03ac2e5a 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -350,8 +350,8 @@ struct inode_operations { int (*rename2) (struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); - void * (*follow_link) (struct dentry *, struct nameidata *); - void (*put_link) (struct dentry *, struct nameidata *, void *); + const char *(*follow_link) (struct dentry *, void **, struct nameidata *); + void (*put_link) (struct dentry *, void *); int (*permission) (struct inode *, int); int (*get_acl)(struct inode *, int); int (*setattr) (struct dentry *, struct iattr *); diff --git a/drivers/staging/lustre/lustre/llite/symlink.c b/drivers/staging/lustre/lustre/llite/symlink.c index 3711e671a4df..e488cb3bb25d 100644 --- a/drivers/staging/lustre/lustre/llite/symlink.c +++ b/drivers/staging/lustre/lustre/llite/symlink.c @@ -118,7 +118,7 @@ failed: return rc; } -static void *ll_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *ll_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct inode *inode = d_inode(dentry); struct ptlrpc_request *request = NULL; @@ -140,18 +140,17 @@ static void *ll_follow_link(struct dentry *dentry, struct nameidata *nd) } if (rc) { ptlrpc_req_finished(request); - request = NULL; - symname = ERR_PTR(rc); + return ERR_PTR(rc); } - nd_set_link(nd, symname); /* symname may contain a pointer to the request message buffer, * we delay request releasing until ll_put_link then. */ - return request; + *cookie = request; + return symname; } -static void ll_put_link(struct dentry *dentry, struct nameidata *nd, void *cookie) +static void ll_put_link(struct dentry *dentry, void *cookie) { ptlrpc_req_finished(cookie); } diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 0ba11712b388..7cc70a39a1d8 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -1230,11 +1230,12 @@ ino_t v9fs_qid2ino(struct p9_qid *qid) * */ -static void *v9fs_vfs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *v9fs_vfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct v9fs_session_info *v9ses = v9fs_dentry2v9ses(dentry); struct p9_fid *fid = v9fs_fid_lookup(dentry); struct p9_wstat *st; + char *res; p9_debug(P9_DEBUG_VFS, "%pd\n", dentry); @@ -1253,14 +1254,14 @@ static void *v9fs_vfs_follow_link(struct dentry *dentry, struct nameidata *nd) kfree(st); return ERR_PTR(-EINVAL); } - if (strlen(st->extension) >= PATH_MAX) - st->extension[PATH_MAX - 1] = '\0'; - - nd_set_link(nd, st->extension); + res = st->extension; st->extension = NULL; + if (strlen(res) >= PATH_MAX) + res[PATH_MAX - 1] = '\0'; + p9stat_free(st); kfree(st); - return NULL; + return *cookie = res; } /** diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c index bc2a91f2b910..ae062ffa0f1f 100644 --- a/fs/9p/vfs_inode_dotl.c +++ b/fs/9p/vfs_inode_dotl.c @@ -909,8 +909,8 @@ error: * */ -static void * -v9fs_vfs_follow_link_dotl(struct dentry *dentry, struct nameidata *nd) +static const char * +v9fs_vfs_follow_link_dotl(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct p9_fid *fid = v9fs_fid_lookup(dentry); char *target; @@ -923,8 +923,7 @@ v9fs_vfs_follow_link_dotl(struct dentry *dentry, struct nameidata *nd) retval = p9_client_readlink(fid, &target); if (retval) return ERR_PTR(retval); - nd_set_link(nd, target); - return NULL; + return *cookie = target; } int v9fs_refresh_inode_dotl(struct p9_fid *fid, struct inode *inode) diff --git a/fs/autofs4/symlink.c b/fs/autofs4/symlink.c index de58cc7b8076..9c6a07739c9b 100644 --- a/fs/autofs4/symlink.c +++ b/fs/autofs4/symlink.c @@ -12,14 +12,13 @@ #include "autofs_i.h" -static void *autofs4_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *autofs4_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct autofs_sb_info *sbi = autofs4_sbi(dentry->d_sb); struct autofs_info *ino = autofs4_dentry_ino(dentry); if (ino && !autofs4_oz_mode(sbi)) ino->last_used = jiffies; - nd_set_link(nd, d_inode(dentry)->i_private); - return NULL; + return d_inode(dentry)->i_private; } const struct inode_operations autofs4_symlink_inode_operations = { diff --git a/fs/befs/linuxvfs.c b/fs/befs/linuxvfs.c index 172e306d68a7..3a1aefb86a11 100644 --- a/fs/befs/linuxvfs.c +++ b/fs/befs/linuxvfs.c @@ -42,7 +42,7 @@ static struct inode *befs_iget(struct super_block *, unsigned long); static struct inode *befs_alloc_inode(struct super_block *sb); static void befs_destroy_inode(struct inode *inode); static void befs_destroy_inodecache(void); -static void *befs_follow_link(struct dentry *, struct nameidata *); +static const char *befs_follow_link(struct dentry *, void **, struct nameidata *nd); static int befs_utf2nls(struct super_block *sb, const char *in, int in_len, char **out, int *out_len); static int befs_nls2utf(struct super_block *sb, const char *in, int in_len, @@ -463,8 +463,8 @@ befs_destroy_inodecache(void) * The data stream become link name. Unless the LONG_SYMLINK * flag is set. */ -static void * -befs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char * +befs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct super_block *sb = dentry->d_sb; struct befs_inode_info *befs_ino = BEFS_I(d_inode(dentry)); @@ -474,23 +474,20 @@ befs_follow_link(struct dentry *dentry, struct nameidata *nd) if (len == 0) { befs_error(sb, "Long symlink with illegal length"); - link = ERR_PTR(-EIO); - } else { - befs_debug(sb, "Follow long symlink"); - - link = kmalloc(len, GFP_NOFS); - if (!link) { - link = ERR_PTR(-ENOMEM); - } else if (befs_read_lsymlink(sb, data, link, len) != len) { - kfree(link); - befs_error(sb, "Failed to read entire long symlink"); - link = ERR_PTR(-EIO); - } else { - link[len - 1] = '\0'; - } + return ERR_PTR(-EIO); } - nd_set_link(nd, link); - return NULL; + befs_debug(sb, "Follow long symlink"); + + link = kmalloc(len, GFP_NOFS); + if (!link) + return ERR_PTR(-ENOMEM); + if (befs_read_lsymlink(sb, data, link, len) != len) { + kfree(link); + befs_error(sb, "Failed to read entire long symlink"); + return ERR_PTR(-EIO); + } + link[len - 1] = '\0'; + return *cookie = link; } /* diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index 252f5c15806b..61012da7e9d8 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h @@ -120,7 +120,7 @@ extern struct vfsmount *cifs_dfs_d_automount(struct path *path); #endif /* Functions related to symlinks */ -extern void *cifs_follow_link(struct dentry *direntry, struct nameidata *nd); +extern const char *cifs_follow_link(struct dentry *direntry, void **cookie, struct nameidata *nd); extern int cifs_readlink(struct dentry *direntry, char __user *buffer, int buflen); extern int cifs_symlink(struct inode *inode, struct dentry *direntry, diff --git a/fs/cifs/link.c b/fs/cifs/link.c index 252e672d5604..4a439c2c0c7f 100644 --- a/fs/cifs/link.c +++ b/fs/cifs/link.c @@ -626,8 +626,8 @@ cifs_hl_exit: return rc; } -void * -cifs_follow_link(struct dentry *direntry, struct nameidata *nd) +const char * +cifs_follow_link(struct dentry *direntry, void **cookie, struct nameidata *nd) { struct inode *inode = d_inode(direntry); int rc = -ENOMEM; @@ -643,16 +643,18 @@ cifs_follow_link(struct dentry *direntry, struct nameidata *nd) tlink = cifs_sb_tlink(cifs_sb); if (IS_ERR(tlink)) { - rc = PTR_ERR(tlink); - tlink = NULL; - goto out; + free_xid(xid); + return ERR_CAST(tlink); } tcon = tlink_tcon(tlink); server = tcon->ses->server; full_path = build_path_from_dentry(direntry); - if (!full_path) - goto out; + if (!full_path) { + free_xid(xid); + cifs_put_tlink(tlink); + return ERR_PTR(-ENOMEM); + } cifs_dbg(FYI, "Full path: %s inode = 0x%p\n", full_path, inode); @@ -670,17 +672,13 @@ cifs_follow_link(struct dentry *direntry, struct nameidata *nd) &target_path, cifs_sb); kfree(full_path); -out: + free_xid(xid); + cifs_put_tlink(tlink); if (rc != 0) { kfree(target_path); - target_path = ERR_PTR(rc); + return ERR_PTR(rc); } - - free_xid(xid); - if (tlink) - cifs_put_tlink(tlink); - nd_set_link(nd, target_path); - return NULL; + return *cookie = target_path; } int diff --git a/fs/configfs/symlink.c b/fs/configfs/symlink.c index cc9f2546ea4a..fac8e8517f33 100644 --- a/fs/configfs/symlink.c +++ b/fs/configfs/symlink.c @@ -279,30 +279,26 @@ static int configfs_getlink(struct dentry *dentry, char * path) } -static void *configfs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *configfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { - int error = -ENOMEM; unsigned long page = get_zeroed_page(GFP_KERNEL); + int error; - if (page) { - error = configfs_getlink(dentry, (char *)page); - if (!error) { - nd_set_link(nd, (char *)page); - return (void *)page; - } + if (!page) + return ERR_PTR(-ENOMEM); + + error = configfs_getlink(dentry, (char *)page); + if (!error) { + return *cookie = (void *)page; } - nd_set_link(nd, ERR_PTR(error)); - return NULL; + free_page(page); + return ERR_PTR(error); } -static void configfs_put_link(struct dentry *dentry, struct nameidata *nd, - void *cookie) +static void configfs_put_link(struct dentry *dentry, void *cookie) { - if (cookie) { - unsigned long page = (unsigned long)cookie; - free_page(page); - } + free_page((unsigned long)cookie); } const struct inode_operations configfs_symlink_inode_operations = { diff --git a/fs/ecryptfs/inode.c b/fs/ecryptfs/inode.c index fc850b55db67..cdb9d6c4532d 100644 --- a/fs/ecryptfs/inode.c +++ b/fs/ecryptfs/inode.c @@ -675,18 +675,16 @@ out: return rc ? ERR_PTR(rc) : buf; } -static void *ecryptfs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *ecryptfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { size_t len; char *buf = ecryptfs_readlink_lower(dentry, &len); if (IS_ERR(buf)) - goto out; + return buf; fsstack_copy_attr_atime(d_inode(dentry), d_inode(ecryptfs_dentry_to_lower(dentry))); buf[len] = '\0'; -out: - nd_set_link(nd, buf); - return NULL; + return *cookie = buf; } /** diff --git a/fs/ext4/symlink.c b/fs/ext4/symlink.c index 4264fb1e341a..afec475aaf5c 100644 --- a/fs/ext4/symlink.c +++ b/fs/ext4/symlink.c @@ -23,7 +23,7 @@ #include "xattr.h" #ifdef CONFIG_EXT4_FS_ENCRYPTION -static void *ext4_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *ext4_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct page *cpage = NULL; char *caddr, *paddr = NULL; @@ -37,7 +37,7 @@ static void *ext4_follow_link(struct dentry *dentry, struct nameidata *nd) ctx = ext4_get_fname_crypto_ctx(inode, inode->i_sb->s_blocksize); if (IS_ERR(ctx)) - return ctx; + return ERR_CAST(ctx); if (ext4_inode_is_fast_symlink(inode)) { caddr = (char *) EXT4_I(inode)->i_data; @@ -46,7 +46,7 @@ static void *ext4_follow_link(struct dentry *dentry, struct nameidata *nd) cpage = read_mapping_page(inode->i_mapping, 0, NULL); if (IS_ERR(cpage)) { ext4_put_fname_crypto_ctx(&ctx); - return cpage; + return ERR_CAST(cpage); } caddr = kmap(cpage); caddr[size] = 0; @@ -77,13 +77,12 @@ static void *ext4_follow_link(struct dentry *dentry, struct nameidata *nd) /* Null-terminate the name */ if (res <= plen) paddr[res] = '\0'; - nd_set_link(nd, paddr); ext4_put_fname_crypto_ctx(&ctx); if (cpage) { kunmap(cpage); page_cache_release(cpage); } - return NULL; + return *cookie = paddr; errout: ext4_put_fname_crypto_ctx(&ctx); if (cpage) { diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index 658e8079aaf9..d2947937515e 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -296,19 +296,15 @@ fail: return err; } -static void *f2fs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *f2fs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { - struct page *page = page_follow_link_light(dentry, nd); - - if (IS_ERR_OR_NULL(page)) - return page; - - /* this is broken symlink case */ - if (*nd_get_link(nd) == 0) { - page_put_link(dentry, nd, page); - return ERR_PTR(-ENOENT); + const char *link = page_follow_link_light(dentry, cookie, nd); + if (!IS_ERR(link) && !*link) { + /* this is broken symlink case */ + page_put_link(dentry, *cookie); + link = ERR_PTR(-ENOENT); } - return page; + return link; } static int f2fs_symlink(struct inode *dir, struct dentry *dentry, diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index 0572bca49f15..f9cb260375cf 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -1365,7 +1365,7 @@ static int fuse_readdir(struct file *file, struct dir_context *ctx) return err; } -static char *read_link(struct dentry *dentry) +static const char *fuse_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct inode *inode = d_inode(dentry); struct fuse_conn *fc = get_fuse_conn(inode); @@ -1389,26 +1389,15 @@ static char *read_link(struct dentry *dentry) link = ERR_PTR(ret); } else { link[ret] = '\0'; + *cookie = link; } fuse_invalidate_atime(inode); return link; } -static void free_link(char *link) +static void fuse_put_link(struct dentry *dentry, void *cookie) { - if (!IS_ERR(link)) - free_page((unsigned long) link); -} - -static void *fuse_follow_link(struct dentry *dentry, struct nameidata *nd) -{ - nd_set_link(nd, read_link(dentry)); - return NULL; -} - -static void fuse_put_link(struct dentry *dentry, struct nameidata *nd, void *c) -{ - free_link(nd_get_link(nd)); + free_page((unsigned long) cookie); } static int fuse_dir_open(struct inode *inode, struct file *file) diff --git a/fs/gfs2/inode.c b/fs/gfs2/inode.c index 1b3ca7a2e3fc..f59390aebffb 100644 --- a/fs/gfs2/inode.c +++ b/fs/gfs2/inode.c @@ -1548,7 +1548,7 @@ out: * Returns: 0 on success or error code */ -static void *gfs2_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *gfs2_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct gfs2_inode *ip = GFS2_I(d_inode(dentry)); struct gfs2_holder i_gh; @@ -1561,8 +1561,7 @@ static void *gfs2_follow_link(struct dentry *dentry, struct nameidata *nd) error = gfs2_glock_nq(&i_gh); if (error) { gfs2_holder_uninit(&i_gh); - nd_set_link(nd, ERR_PTR(error)); - return NULL; + return ERR_PTR(error); } size = (unsigned int)i_size_read(&ip->i_inode); @@ -1586,8 +1585,9 @@ static void *gfs2_follow_link(struct dentry *dentry, struct nameidata *nd) brelse(dibh); out: gfs2_glock_dq_uninit(&i_gh); - nd_set_link(nd, buf); - return NULL; + if (!IS_ERR(buf)) + *cookie = buf; + return buf; } /** diff --git a/fs/hostfs/hostfs_kern.c b/fs/hostfs/hostfs_kern.c index ef263174acd2..f650ed661fab 100644 --- a/fs/hostfs/hostfs_kern.c +++ b/fs/hostfs/hostfs_kern.c @@ -892,7 +892,7 @@ static const struct inode_operations hostfs_dir_iops = { .setattr = hostfs_setattr, }; -static void *hostfs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *hostfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { char *link = __getname(); if (link) { @@ -906,21 +906,18 @@ static void *hostfs_follow_link(struct dentry *dentry, struct nameidata *nd) } if (err < 0) { __putname(link); - link = ERR_PTR(err); + return ERR_PTR(err); } } else { - link = ERR_PTR(-ENOMEM); + return ERR_PTR(-ENOMEM); } - nd_set_link(nd, link); - return NULL; + return *cookie = link; } -static void hostfs_put_link(struct dentry *dentry, struct nameidata *nd, void *cookie) +static void hostfs_put_link(struct dentry *dentry, void *cookie) { - char *s = nd_get_link(nd); - if (!IS_ERR(s)) - __putname(s); + __putname(cookie); } static const struct inode_operations hostfs_link_iops = { diff --git a/fs/hppfs/hppfs.c b/fs/hppfs/hppfs.c index fa2bd5366ecf..b8f24d3b04ee 100644 --- a/fs/hppfs/hppfs.c +++ b/fs/hppfs/hppfs.c @@ -642,20 +642,19 @@ static int hppfs_readlink(struct dentry *dentry, char __user *buffer, buflen); } -static void *hppfs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *hppfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct dentry *proc_dentry = HPPFS_I(d_inode(dentry))->proc_dentry; - return d_inode(proc_dentry)->i_op->follow_link(proc_dentry, nd); + return d_inode(proc_dentry)->i_op->follow_link(proc_dentry, cookie, nd); } -static void hppfs_put_link(struct dentry *dentry, struct nameidata *nd, - void *cookie) +static void hppfs_put_link(struct dentry *dentry, void *cookie) { struct dentry *proc_dentry = HPPFS_I(d_inode(dentry))->proc_dentry; if (d_inode(proc_dentry)->i_op->put_link) - d_inode(proc_dentry)->i_op->put_link(proc_dentry, nd, cookie); + d_inode(proc_dentry)->i_op->put_link(proc_dentry, cookie); } static const struct inode_operations hppfs_dir_iops = { diff --git a/fs/kernfs/symlink.c b/fs/kernfs/symlink.c index 8a198898e39a..3c7e799974a2 100644 --- a/fs/kernfs/symlink.c +++ b/fs/kernfs/symlink.c @@ -112,25 +112,23 @@ static int kernfs_getlink(struct dentry *dentry, char *path) return error; } -static void *kernfs_iop_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *kernfs_iop_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { int error = -ENOMEM; unsigned long page = get_zeroed_page(GFP_KERNEL); - if (page) { - error = kernfs_getlink(dentry, (char *) page); - if (error < 0) - free_page((unsigned long)page); + if (!page) + return ERR_PTR(-ENOMEM); + error = kernfs_getlink(dentry, (char *)page); + if (unlikely(error < 0)) { + free_page((unsigned long)page); + return ERR_PTR(error); } - nd_set_link(nd, error ? ERR_PTR(error) : (char *)page); - return NULL; + return *cookie = (char *)page; } -static void kernfs_iop_put_link(struct dentry *dentry, struct nameidata *nd, - void *cookie) +static void kernfs_iop_put_link(struct dentry *dentry, void *cookie) { - char *page = nd_get_link(nd); - if (!IS_ERR(page)) - free_page((unsigned long)page); + free_page((unsigned long)cookie); } const struct inode_operations kernfs_symlink_iops = { diff --git a/fs/libfs.c b/fs/libfs.c index 72e4e015455f..0c83fde20dbd 100644 --- a/fs/libfs.c +++ b/fs/libfs.c @@ -1024,12 +1024,9 @@ int noop_fsync(struct file *file, loff_t start, loff_t end, int datasync) } EXPORT_SYMBOL(noop_fsync); -void kfree_put_link(struct dentry *dentry, struct nameidata *nd, - void *cookie) +void kfree_put_link(struct dentry *dentry, void *cookie) { - char *s = nd_get_link(nd); - if (!IS_ERR(s)) - kfree(s); + kfree(cookie); } EXPORT_SYMBOL(kfree_put_link); @@ -1094,10 +1091,9 @@ simple_nosetlease(struct file *filp, long arg, struct file_lock **flp, } EXPORT_SYMBOL(simple_nosetlease); -void *simple_follow_link(struct dentry *dentry, struct nameidata *nd) +const char *simple_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { - nd_set_link(nd, d_inode(dentry)->i_link); - return NULL; + return d_inode(dentry)->i_link; } EXPORT_SYMBOL(simple_follow_link); diff --git a/fs/namei.c b/fs/namei.c index ab2bcbdbd683..aeca44877371 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -502,7 +502,6 @@ struct nameidata { int last_type; unsigned depth; struct file *base; - char *saved_names[MAX_NESTED_LINKS + 1]; }; /* @@ -713,23 +712,11 @@ void nd_jump_link(struct nameidata *nd, struct path *path) nd->flags |= LOOKUP_JUMPED; } -void nd_set_link(struct nameidata *nd, char *path) -{ - nd->saved_names[nd->depth] = path; -} -EXPORT_SYMBOL(nd_set_link); - -char *nd_get_link(struct nameidata *nd) -{ - return nd->saved_names[nd->depth]; -} -EXPORT_SYMBOL(nd_get_link); - static inline void put_link(struct nameidata *nd, struct path *link, void *cookie) { struct inode *inode = link->dentry->d_inode; - if (inode->i_op->put_link) - inode->i_op->put_link(link->dentry, nd, cookie); + if (cookie && inode->i_op->put_link) + inode->i_op->put_link(link->dentry, cookie); path_put(link); } @@ -854,7 +841,7 @@ follow_link(struct path *link, struct nameidata *nd, void **p) { struct dentry *dentry = link->dentry; int error; - char *s; + const char *s; BUG_ON(nd->flags & LOOKUP_RCU); @@ -869,26 +856,20 @@ follow_link(struct path *link, struct nameidata *nd, void **p) current->total_link_count++; touch_atime(link); - nd_set_link(nd, NULL); error = security_inode_follow_link(dentry); if (error) goto out_put_nd_path; nd->last_type = LAST_BIND; - *p = dentry->d_inode->i_op->follow_link(dentry, nd); - error = PTR_ERR(*p); - if (IS_ERR(*p)) + *p = NULL; + s = dentry->d_inode->i_op->follow_link(dentry, p, nd); + error = PTR_ERR(s); + if (IS_ERR(s)) goto out_put_nd_path; error = 0; - s = nd_get_link(nd); if (s) { - if (unlikely(IS_ERR(s))) { - path_put(&nd->path); - put_link(nd, link, *p); - return PTR_ERR(s); - } if (*s == '/') { if (!nd->root.mnt) set_root(nd); @@ -906,7 +887,6 @@ follow_link(struct path *link, struct nameidata *nd, void **p) return error; out_put_nd_path: - *p = NULL; path_put(&nd->path); path_put(link); return error; @@ -4430,18 +4410,15 @@ EXPORT_SYMBOL(readlink_copy); */ int generic_readlink(struct dentry *dentry, char __user *buffer, int buflen) { - struct nameidata nd; void *cookie; + const char *link = dentry->d_inode->i_op->follow_link(dentry, &cookie, NULL); int res; - nd.depth = 0; - cookie = dentry->d_inode->i_op->follow_link(dentry, &nd); - if (IS_ERR(cookie)) - return PTR_ERR(cookie); - - res = readlink_copy(buffer, buflen, nd_get_link(&nd)); - if (dentry->d_inode->i_op->put_link) - dentry->d_inode->i_op->put_link(dentry, &nd, cookie); + if (IS_ERR(link)) + return PTR_ERR(link); + res = readlink_copy(buffer, buflen, link); + if (cookie && dentry->d_inode->i_op->put_link) + dentry->d_inode->i_op->put_link(dentry, cookie); return res; } EXPORT_SYMBOL(generic_readlink); @@ -4473,22 +4450,21 @@ int page_readlink(struct dentry *dentry, char __user *buffer, int buflen) } EXPORT_SYMBOL(page_readlink); -void *page_follow_link_light(struct dentry *dentry, struct nameidata *nd) +const char *page_follow_link_light(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct page *page = NULL; - nd_set_link(nd, page_getlink(dentry, &page)); - return page; + char *res = page_getlink(dentry, &page); + if (!IS_ERR(res)) + *cookie = page; + return res; } EXPORT_SYMBOL(page_follow_link_light); -void page_put_link(struct dentry *dentry, struct nameidata *nd, void *cookie) +void page_put_link(struct dentry *dentry, void *cookie) { struct page *page = cookie; - - if (page) { - kunmap(page); - page_cache_release(page); - } + kunmap(page); + page_cache_release(page); } EXPORT_SYMBOL(page_put_link); diff --git a/fs/nfs/symlink.c b/fs/nfs/symlink.c index 2d56200655fe..c992b200ae7e 100644 --- a/fs/nfs/symlink.c +++ b/fs/nfs/symlink.c @@ -20,7 +20,6 @@ #include #include #include -#include /* Symlink caching in the page cache is even more simplistic * and straight-forward than readdir caching. @@ -43,7 +42,7 @@ error: return -EIO; } -static void *nfs_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *nfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct inode *inode = d_inode(dentry); struct page *page; @@ -51,19 +50,13 @@ static void *nfs_follow_link(struct dentry *dentry, struct nameidata *nd) err = ERR_PTR(nfs_revalidate_mapping(inode, inode->i_mapping)); if (err) - goto read_failed; + return err; page = read_cache_page(&inode->i_data, 0, (filler_t *)nfs_symlink_filler, inode); - if (IS_ERR(page)) { - err = page; - goto read_failed; - } - nd_set_link(nd, kmap(page)); - return page; - -read_failed: - nd_set_link(nd, err); - return NULL; + if (IS_ERR(page)) + return ERR_CAST(page); + *cookie = page; + return kmap(page); } /* diff --git a/fs/overlayfs/inode.c b/fs/overlayfs/inode.c index 1b4b9c5e51b7..235ad42afb57 100644 --- a/fs/overlayfs/inode.c +++ b/fs/overlayfs/inode.c @@ -140,12 +140,12 @@ struct ovl_link_data { void *cookie; }; -static void *ovl_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *ovl_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { - void *ret; struct dentry *realdentry; struct inode *realinode; struct ovl_link_data *data = NULL; + const char *ret; realdentry = ovl_dentry_real(dentry); realinode = realdentry->d_inode; @@ -160,19 +160,21 @@ static void *ovl_follow_link(struct dentry *dentry, struct nameidata *nd) data->realdentry = realdentry; } - ret = realinode->i_op->follow_link(realdentry, nd); - if (IS_ERR(ret)) { + ret = realinode->i_op->follow_link(realdentry, cookie, nd); + if (IS_ERR_OR_NULL(ret)) { kfree(data); return ret; } if (data) - data->cookie = ret; + data->cookie = *cookie; - return data; + *cookie = data; + + return ret; } -static void ovl_put_link(struct dentry *dentry, struct nameidata *nd, void *c) +static void ovl_put_link(struct dentry *dentry, void *c) { struct inode *realinode; struct ovl_link_data *data = c; @@ -181,7 +183,7 @@ static void ovl_put_link(struct dentry *dentry, struct nameidata *nd, void *c) return; realinode = data->realdentry->d_inode; - realinode->i_op->put_link(data->realdentry, nd, data->cookie); + realinode->i_op->put_link(data->realdentry, data->cookie); kfree(data); } diff --git a/fs/proc/base.c b/fs/proc/base.c index 093ca14f5701..52652f86b187 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -1380,7 +1380,7 @@ static int proc_exe_link(struct dentry *dentry, struct path *exe_path) return -ENOENT; } -static void *proc_pid_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *proc_pid_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct inode *inode = d_inode(dentry); struct path path; diff --git a/fs/proc/inode.c b/fs/proc/inode.c index 8272aaba1bb0..acd51d75387d 100644 --- a/fs/proc/inode.c +++ b/fs/proc/inode.c @@ -23,7 +23,6 @@ #include #include #include -#include #include @@ -394,16 +393,16 @@ static const struct file_operations proc_reg_file_ops_no_compat = { }; #endif -static void *proc_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *proc_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct proc_dir_entry *pde = PDE(d_inode(dentry)); if (unlikely(!use_pde(pde))) return ERR_PTR(-EINVAL); - nd_set_link(nd, pde->data); - return pde; + *cookie = pde; + return pde->data; } -static void proc_put_link(struct dentry *dentry, struct nameidata *nd, void *p) +static void proc_put_link(struct dentry *dentry, void *p) { unuse_pde(p); } diff --git a/fs/proc/namespaces.c b/fs/proc/namespaces.c index e512642dbbdc..10d24dd096e8 100644 --- a/fs/proc/namespaces.c +++ b/fs/proc/namespaces.c @@ -30,7 +30,7 @@ static const struct proc_ns_operations *ns_entries[] = { &mntns_operations, }; -static void *proc_ns_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *proc_ns_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct inode *inode = d_inode(dentry); const struct proc_ns_operations *ns_ops = PROC_I(inode)->ns_ops; diff --git a/fs/proc/self.c b/fs/proc/self.c index 6195b4a7c3b1..ad333946b53a 100644 --- a/fs/proc/self.c +++ b/fs/proc/self.c @@ -1,5 +1,4 @@ #include -#include #include #include #include "internal.h" @@ -19,21 +18,20 @@ static int proc_self_readlink(struct dentry *dentry, char __user *buffer, return readlink_copy(buffer, buflen, tmp); } -static void *proc_self_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *proc_self_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct pid_namespace *ns = dentry->d_sb->s_fs_info; pid_t tgid = task_tgid_nr_ns(current, ns); - char *name = ERR_PTR(-ENOENT); - if (tgid) { - /* 11 for max length of signed int in decimal + NULL term */ - name = kmalloc(12, GFP_KERNEL); - if (!name) - name = ERR_PTR(-ENOMEM); - else - sprintf(name, "%d", tgid); - } - nd_set_link(nd, name); - return NULL; + char *name; + + if (!tgid) + return ERR_PTR(-ENOENT); + /* 11 for max length of signed int in decimal + NULL term */ + name = kmalloc(12, GFP_KERNEL); + if (!name) + return ERR_PTR(-ENOMEM); + sprintf(name, "%d", tgid); + return *cookie = name; } static const struct inode_operations proc_self_inode_operations = { diff --git a/fs/proc/thread_self.c b/fs/proc/thread_self.c index a8371993b4fb..85c96e0d7aaa 100644 --- a/fs/proc/thread_self.c +++ b/fs/proc/thread_self.c @@ -1,5 +1,4 @@ #include -#include #include #include #include "internal.h" @@ -20,21 +19,20 @@ static int proc_thread_self_readlink(struct dentry *dentry, char __user *buffer, return readlink_copy(buffer, buflen, tmp); } -static void *proc_thread_self_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *proc_thread_self_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct pid_namespace *ns = dentry->d_sb->s_fs_info; pid_t tgid = task_tgid_nr_ns(current, ns); pid_t pid = task_pid_nr_ns(current, ns); - char *name = ERR_PTR(-ENOENT); - if (pid) { - name = kmalloc(PROC_NUMBUF + 6 + PROC_NUMBUF, GFP_KERNEL); - if (!name) - name = ERR_PTR(-ENOMEM); - else - sprintf(name, "%d/task/%d", tgid, pid); - } - nd_set_link(nd, name); - return NULL; + char *name; + + if (!pid) + return ERR_PTR(-ENOENT); + name = kmalloc(PROC_NUMBUF + 6 + PROC_NUMBUF, GFP_KERNEL); + if (!name) + return ERR_PTR(-ENOMEM); + sprintf(name, "%d/task/%d", tgid, pid); + return *cookie = name; } static const struct inode_operations proc_thread_self_inode_operations = { diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c index f4cd7204e236..26c4dcb1ef56 100644 --- a/fs/xfs/xfs_iops.c +++ b/fs/xfs/xfs_iops.c @@ -41,7 +41,6 @@ #include #include -#include #include #include #include @@ -414,9 +413,10 @@ xfs_vn_rename( * we need to be very careful about how much stack we use. * uio is kmalloced for this reason... */ -STATIC void * +STATIC const char * xfs_vn_follow_link( struct dentry *dentry, + void **cookie, struct nameidata *nd) { char *link; @@ -430,14 +430,12 @@ xfs_vn_follow_link( if (unlikely(error)) goto out_kfree; - nd_set_link(nd, link); - return NULL; + return *cookie = link; out_kfree: kfree(link); out_err: - nd_set_link(nd, ERR_PTR(error)); - return NULL; + return ERR_PTR(error); } STATIC int diff --git a/include/linux/fs.h b/include/linux/fs.h index 0ac758fcff00..9ab934113a28 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1608,12 +1608,12 @@ struct file_operations { struct inode_operations { struct dentry * (*lookup) (struct inode *,struct dentry *, unsigned int); - void * (*follow_link) (struct dentry *, struct nameidata *); + const char * (*follow_link) (struct dentry *, void **, struct nameidata *); int (*permission) (struct inode *, int); struct posix_acl * (*get_acl)(struct inode *, int); int (*readlink) (struct dentry *, char __user *,int); - void (*put_link) (struct dentry *, struct nameidata *, void *); + void (*put_link) (struct dentry *, void *); int (*create) (struct inode *,struct dentry *, umode_t, bool); int (*link) (struct dentry *,struct inode *,struct dentry *); @@ -2705,13 +2705,13 @@ extern const struct file_operations generic_ro_fops; extern int readlink_copy(char __user *, int, const char *); extern int page_readlink(struct dentry *, char __user *, int); -extern void *page_follow_link_light(struct dentry *, struct nameidata *); -extern void page_put_link(struct dentry *, struct nameidata *, void *); +extern const char *page_follow_link_light(struct dentry *, void **, struct nameidata *); +extern void page_put_link(struct dentry *, void *); extern int __page_symlink(struct inode *inode, const char *symname, int len, int nofs); extern int page_symlink(struct inode *inode, const char *symname, int len); extern const struct inode_operations page_symlink_inode_operations; -extern void kfree_put_link(struct dentry *, struct nameidata *, void *); +extern void kfree_put_link(struct dentry *, void *); extern int generic_readlink(struct dentry *, char __user *, int); extern void generic_fillattr(struct inode *, struct kstat *); int vfs_getattr_nosec(struct path *path, struct kstat *stat); @@ -2722,7 +2722,7 @@ void __inode_sub_bytes(struct inode *inode, loff_t bytes); void inode_sub_bytes(struct inode *inode, loff_t bytes); loff_t inode_get_bytes(struct inode *inode); void inode_set_bytes(struct inode *inode, loff_t bytes); -void *simple_follow_link(struct dentry *, struct nameidata *); +const char *simple_follow_link(struct dentry *, void **, struct nameidata *); extern const struct inode_operations simple_symlink_inode_operations; extern int iterate_dir(struct file *, struct dir_context *); diff --git a/include/linux/namei.h b/include/linux/namei.h index c8990779f0c3..a5d5bed2c0e1 100644 --- a/include/linux/namei.h +++ b/include/linux/namei.h @@ -71,8 +71,6 @@ extern struct dentry *lock_rename(struct dentry *, struct dentry *); extern void unlock_rename(struct dentry *, struct dentry *); extern void nd_jump_link(struct nameidata *nd, struct path *path); -extern void nd_set_link(struct nameidata *nd, char *path); -extern char *nd_get_link(struct nameidata *nd); static inline void nd_terminate_link(void *name, size_t len, size_t maxlen) { diff --git a/mm/shmem.c b/mm/shmem.c index 7f6e2f889122..d1693dcb4285 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2475,24 +2475,23 @@ static int shmem_symlink(struct inode *dir, struct dentry *dentry, const char *s return 0; } -static void *shmem_follow_link(struct dentry *dentry, struct nameidata *nd) +static const char *shmem_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) { struct page *page = NULL; int error = shmem_getpage(d_inode(dentry), 0, &page, SGP_READ, NULL); - nd_set_link(nd, error ? ERR_PTR(error) : kmap(page)); - if (page) - unlock_page(page); - return page; + if (error) + return ERR_PTR(error); + unlock_page(page); + *cookie = page; + return kmap(page); } -static void shmem_put_link(struct dentry *dentry, struct nameidata *nd, void *cookie) +static void shmem_put_link(struct dentry *dentry, void *cookie) { - if (!IS_ERR(nd_get_link(nd))) { - struct page *page = cookie; - kunmap(page); - mark_page_accessed(page); - page_cache_release(page); - } + struct page *page = cookie; + kunmap(page); + mark_page_accessed(page); + page_cache_release(page); } #ifdef CONFIG_TMPFS_XATTR -- cgit v1.2.3 From 6e77137b363b8d866ac29c5a0c95e953614fb2d8 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 2 May 2015 13:37:52 -0400 Subject: don't pass nameidata to ->follow_link() its only use is getting passed to nd_jump_link(), which can obtain it from current->nameidata Signed-off-by: Al Viro --- Documentation/filesystems/Locking | 2 +- Documentation/filesystems/vfs.txt | 2 +- drivers/staging/lustre/lustre/llite/symlink.c | 2 +- fs/9p/vfs_inode.c | 2 +- fs/9p/vfs_inode_dotl.c | 2 +- fs/autofs4/symlink.c | 2 +- fs/befs/linuxvfs.c | 4 ++-- fs/cifs/cifsfs.h | 2 +- fs/cifs/link.c | 2 +- fs/configfs/symlink.c | 2 +- fs/ecryptfs/inode.c | 2 +- fs/ext4/symlink.c | 2 +- fs/f2fs/namei.c | 4 ++-- fs/fuse/dir.c | 2 +- fs/gfs2/inode.c | 2 +- fs/hostfs/hostfs_kern.c | 2 +- fs/hppfs/hppfs.c | 4 ++-- fs/kernfs/symlink.c | 2 +- fs/libfs.c | 2 +- fs/namei.c | 11 ++++++----- fs/nfs/symlink.c | 2 +- fs/overlayfs/inode.c | 4 ++-- fs/proc/base.c | 4 ++-- fs/proc/inode.c | 2 +- fs/proc/namespaces.c | 4 ++-- fs/proc/self.c | 2 +- fs/proc/thread_self.c | 2 +- fs/xfs/xfs_iops.c | 3 +-- include/linux/fs.h | 6 +++--- include/linux/namei.h | 2 +- mm/shmem.c | 2 +- 31 files changed, 44 insertions(+), 44 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 7fa6c4ac858c..5b5b4f54c033 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -50,7 +50,7 @@ prototypes: int (*rename2) (struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); - const char *(*follow_link) (struct dentry *, void **, struct nameidata *); + const char *(*follow_link) (struct dentry *, void **); void (*put_link) (struct dentry *, void *); void (*truncate) (struct inode *); int (*permission) (struct inode *, int, unsigned int); diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index 1c6b03ac2e5a..0dec8c880be6 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -350,7 +350,7 @@ struct inode_operations { int (*rename2) (struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); - const char *(*follow_link) (struct dentry *, void **, struct nameidata *); + const char *(*follow_link) (struct dentry *, void **); void (*put_link) (struct dentry *, void *); int (*permission) (struct inode *, int); int (*get_acl)(struct inode *, int); diff --git a/drivers/staging/lustre/lustre/llite/symlink.c b/drivers/staging/lustre/lustre/llite/symlink.c index da6d9d17c50d..f3be3bf0f66f 100644 --- a/drivers/staging/lustre/lustre/llite/symlink.c +++ b/drivers/staging/lustre/lustre/llite/symlink.c @@ -118,7 +118,7 @@ failed: return rc; } -static const char *ll_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *ll_follow_link(struct dentry *dentry, void **cookie) { struct inode *inode = d_inode(dentry); struct ptlrpc_request *request = NULL; diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 7cc70a39a1d8..271f51af2f75 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -1230,7 +1230,7 @@ ino_t v9fs_qid2ino(struct p9_qid *qid) * */ -static const char *v9fs_vfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *v9fs_vfs_follow_link(struct dentry *dentry, void **cookie) { struct v9fs_session_info *v9ses = v9fs_dentry2v9ses(dentry); struct p9_fid *fid = v9fs_fid_lookup(dentry); diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c index ae062ffa0f1f..16658ed677c9 100644 --- a/fs/9p/vfs_inode_dotl.c +++ b/fs/9p/vfs_inode_dotl.c @@ -910,7 +910,7 @@ error: */ static const char * -v9fs_vfs_follow_link_dotl(struct dentry *dentry, void **cookie, struct nameidata *nd) +v9fs_vfs_follow_link_dotl(struct dentry *dentry, void **cookie) { struct p9_fid *fid = v9fs_fid_lookup(dentry); char *target; diff --git a/fs/autofs4/symlink.c b/fs/autofs4/symlink.c index 9c6a07739c9b..da0c33481bc0 100644 --- a/fs/autofs4/symlink.c +++ b/fs/autofs4/symlink.c @@ -12,7 +12,7 @@ #include "autofs_i.h" -static const char *autofs4_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *autofs4_follow_link(struct dentry *dentry, void **cookie) { struct autofs_sb_info *sbi = autofs4_sbi(dentry->d_sb); struct autofs_info *ino = autofs4_dentry_ino(dentry); diff --git a/fs/befs/linuxvfs.c b/fs/befs/linuxvfs.c index 3a1aefb86a11..46aedacfa6a8 100644 --- a/fs/befs/linuxvfs.c +++ b/fs/befs/linuxvfs.c @@ -42,7 +42,7 @@ static struct inode *befs_iget(struct super_block *, unsigned long); static struct inode *befs_alloc_inode(struct super_block *sb); static void befs_destroy_inode(struct inode *inode); static void befs_destroy_inodecache(void); -static const char *befs_follow_link(struct dentry *, void **, struct nameidata *nd); +static const char *befs_follow_link(struct dentry *, void **); static int befs_utf2nls(struct super_block *sb, const char *in, int in_len, char **out, int *out_len); static int befs_nls2utf(struct super_block *sb, const char *in, int in_len, @@ -464,7 +464,7 @@ befs_destroy_inodecache(void) * flag is set. */ static const char * -befs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +befs_follow_link(struct dentry *dentry, void **cookie) { struct super_block *sb = dentry->d_sb; struct befs_inode_info *befs_ino = BEFS_I(d_inode(dentry)); diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index 61012da7e9d8..a782b22904e4 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h @@ -120,7 +120,7 @@ extern struct vfsmount *cifs_dfs_d_automount(struct path *path); #endif /* Functions related to symlinks */ -extern const char *cifs_follow_link(struct dentry *direntry, void **cookie, struct nameidata *nd); +extern const char *cifs_follow_link(struct dentry *direntry, void **cookie); extern int cifs_readlink(struct dentry *direntry, char __user *buffer, int buflen); extern int cifs_symlink(struct inode *inode, struct dentry *direntry, diff --git a/fs/cifs/link.c b/fs/cifs/link.c index 4a439c2c0c7f..546f86ab09aa 100644 --- a/fs/cifs/link.c +++ b/fs/cifs/link.c @@ -627,7 +627,7 @@ cifs_hl_exit: } const char * -cifs_follow_link(struct dentry *direntry, void **cookie, struct nameidata *nd) +cifs_follow_link(struct dentry *direntry, void **cookie) { struct inode *inode = d_inode(direntry); int rc = -ENOMEM; diff --git a/fs/configfs/symlink.c b/fs/configfs/symlink.c index fac8e8517f33..0ace75649009 100644 --- a/fs/configfs/symlink.c +++ b/fs/configfs/symlink.c @@ -279,7 +279,7 @@ static int configfs_getlink(struct dentry *dentry, char * path) } -static const char *configfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *configfs_follow_link(struct dentry *dentry, void **cookie) { unsigned long page = get_zeroed_page(GFP_KERNEL); int error; diff --git a/fs/ecryptfs/inode.c b/fs/ecryptfs/inode.c index cdb9d6c4532d..73d20ae92478 100644 --- a/fs/ecryptfs/inode.c +++ b/fs/ecryptfs/inode.c @@ -675,7 +675,7 @@ out: return rc ? ERR_PTR(rc) : buf; } -static const char *ecryptfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *ecryptfs_follow_link(struct dentry *dentry, void **cookie) { size_t len; char *buf = ecryptfs_readlink_lower(dentry, &len); diff --git a/fs/ext4/symlink.c b/fs/ext4/symlink.c index afec475aaf5c..ba5bd18a9825 100644 --- a/fs/ext4/symlink.c +++ b/fs/ext4/symlink.c @@ -23,7 +23,7 @@ #include "xattr.h" #ifdef CONFIG_EXT4_FS_ENCRYPTION -static const char *ext4_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *ext4_follow_link(struct dentry *dentry, void **cookie) { struct page *cpage = NULL; char *caddr, *paddr = NULL; diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index d2947937515e..cd05a7c91533 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -296,9 +296,9 @@ fail: return err; } -static const char *f2fs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *f2fs_follow_link(struct dentry *dentry, void **cookie) { - const char *link = page_follow_link_light(dentry, cookie, nd); + const char *link = page_follow_link_light(dentry, cookie); if (!IS_ERR(link) && !*link) { /* this is broken symlink case */ page_put_link(dentry, *cookie); diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index f9cb260375cf..d5cdef8b7f3a 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -1365,7 +1365,7 @@ static int fuse_readdir(struct file *file, struct dir_context *ctx) return err; } -static const char *fuse_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *fuse_follow_link(struct dentry *dentry, void **cookie) { struct inode *inode = d_inode(dentry); struct fuse_conn *fc = get_fuse_conn(inode); diff --git a/fs/gfs2/inode.c b/fs/gfs2/inode.c index f59390aebffb..3a1461de1551 100644 --- a/fs/gfs2/inode.c +++ b/fs/gfs2/inode.c @@ -1548,7 +1548,7 @@ out: * Returns: 0 on success or error code */ -static const char *gfs2_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *gfs2_follow_link(struct dentry *dentry, void **cookie) { struct gfs2_inode *ip = GFS2_I(d_inode(dentry)); struct gfs2_holder i_gh; diff --git a/fs/hostfs/hostfs_kern.c b/fs/hostfs/hostfs_kern.c index f650ed661fab..7b6ed7a908f6 100644 --- a/fs/hostfs/hostfs_kern.c +++ b/fs/hostfs/hostfs_kern.c @@ -892,7 +892,7 @@ static const struct inode_operations hostfs_dir_iops = { .setattr = hostfs_setattr, }; -static const char *hostfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *hostfs_follow_link(struct dentry *dentry, void **cookie) { char *link = __getname(); if (link) { diff --git a/fs/hppfs/hppfs.c b/fs/hppfs/hppfs.c index b8f24d3b04ee..15a774eb5bbf 100644 --- a/fs/hppfs/hppfs.c +++ b/fs/hppfs/hppfs.c @@ -642,11 +642,11 @@ static int hppfs_readlink(struct dentry *dentry, char __user *buffer, buflen); } -static const char *hppfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *hppfs_follow_link(struct dentry *dentry, void **cookie) { struct dentry *proc_dentry = HPPFS_I(d_inode(dentry))->proc_dentry; - return d_inode(proc_dentry)->i_op->follow_link(proc_dentry, cookie, nd); + return d_inode(proc_dentry)->i_op->follow_link(proc_dentry, cookie); } static void hppfs_put_link(struct dentry *dentry, void *cookie) diff --git a/fs/kernfs/symlink.c b/fs/kernfs/symlink.c index 3c7e799974a2..366c5a17475e 100644 --- a/fs/kernfs/symlink.c +++ b/fs/kernfs/symlink.c @@ -112,7 +112,7 @@ static int kernfs_getlink(struct dentry *dentry, char *path) return error; } -static const char *kernfs_iop_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *kernfs_iop_follow_link(struct dentry *dentry, void **cookie) { int error = -ENOMEM; unsigned long page = get_zeroed_page(GFP_KERNEL); diff --git a/fs/libfs.c b/fs/libfs.c index 0c83fde20dbd..c5f3373e326b 100644 --- a/fs/libfs.c +++ b/fs/libfs.c @@ -1091,7 +1091,7 @@ simple_nosetlease(struct file *filp, long arg, struct file_lock **flp, } EXPORT_SYMBOL(simple_nosetlease); -const char *simple_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +const char *simple_follow_link(struct dentry *dentry, void **cookie) { return d_inode(dentry)->i_link; } diff --git a/fs/namei.c b/fs/namei.c index b57400ca6a0f..f311f0369e3c 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -753,8 +753,9 @@ static inline void path_to_nameidata(const struct path *path, * Helper to directly jump to a known parsed path from ->follow_link, * caller must have taken a reference to path beforehand. */ -void nd_jump_link(struct nameidata *nd, struct path *path) +void nd_jump_link(struct path *path) { + struct nameidata *nd = current->nameidata; path_put(&nd->path); nd->path = *path; @@ -916,7 +917,7 @@ const char *get_link(struct nameidata *nd) nd->last_type = LAST_BIND; res = inode->i_link; if (!res) { - res = inode->i_op->follow_link(dentry, &last->cookie, nd); + res = inode->i_op->follow_link(dentry, &last->cookie); if (IS_ERR(res)) { out: path_put(&last->link); @@ -4485,12 +4486,12 @@ int generic_readlink(struct dentry *dentry, char __user *buffer, int buflen) int res; if (!link) { - link = dentry->d_inode->i_op->follow_link(dentry, &cookie, NULL); + link = dentry->d_inode->i_op->follow_link(dentry, &cookie); if (IS_ERR(link)) return PTR_ERR(link); } res = readlink_copy(buffer, buflen, link); - if (cookie && dentry->d_inode->i_op->put_link) + if (dentry->d_inode->i_op->put_link) dentry->d_inode->i_op->put_link(dentry, cookie); return res; } @@ -4523,7 +4524,7 @@ int page_readlink(struct dentry *dentry, char __user *buffer, int buflen) } EXPORT_SYMBOL(page_readlink); -const char *page_follow_link_light(struct dentry *dentry, void **cookie, struct nameidata *nd) +const char *page_follow_link_light(struct dentry *dentry, void **cookie) { struct page *page = NULL; char *res = page_getlink(dentry, &page); diff --git a/fs/nfs/symlink.c b/fs/nfs/symlink.c index c992b200ae7e..b6de433da5db 100644 --- a/fs/nfs/symlink.c +++ b/fs/nfs/symlink.c @@ -42,7 +42,7 @@ error: return -EIO; } -static const char *nfs_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *nfs_follow_link(struct dentry *dentry, void **cookie) { struct inode *inode = d_inode(dentry); struct page *page; diff --git a/fs/overlayfs/inode.c b/fs/overlayfs/inode.c index 235ad42afb57..9986833c9fcc 100644 --- a/fs/overlayfs/inode.c +++ b/fs/overlayfs/inode.c @@ -140,7 +140,7 @@ struct ovl_link_data { void *cookie; }; -static const char *ovl_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *ovl_follow_link(struct dentry *dentry, void **cookie) { struct dentry *realdentry; struct inode *realinode; @@ -160,7 +160,7 @@ static const char *ovl_follow_link(struct dentry *dentry, void **cookie, struct data->realdentry = realdentry; } - ret = realinode->i_op->follow_link(realdentry, cookie, nd); + ret = realinode->i_op->follow_link(realdentry, cookie); if (IS_ERR_OR_NULL(ret)) { kfree(data); return ret; diff --git a/fs/proc/base.c b/fs/proc/base.c index 52652f86b187..286a422f440e 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -1380,7 +1380,7 @@ static int proc_exe_link(struct dentry *dentry, struct path *exe_path) return -ENOENT; } -static const char *proc_pid_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *proc_pid_follow_link(struct dentry *dentry, void **cookie) { struct inode *inode = d_inode(dentry); struct path path; @@ -1394,7 +1394,7 @@ static const char *proc_pid_follow_link(struct dentry *dentry, void **cookie, st if (error) goto out; - nd_jump_link(nd, &path); + nd_jump_link(&path); return NULL; out: return ERR_PTR(error); diff --git a/fs/proc/inode.c b/fs/proc/inode.c index acd51d75387d..eb35874fe09c 100644 --- a/fs/proc/inode.c +++ b/fs/proc/inode.c @@ -393,7 +393,7 @@ static const struct file_operations proc_reg_file_ops_no_compat = { }; #endif -static const char *proc_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *proc_follow_link(struct dentry *dentry, void **cookie) { struct proc_dir_entry *pde = PDE(d_inode(dentry)); if (unlikely(!use_pde(pde))) diff --git a/fs/proc/namespaces.c b/fs/proc/namespaces.c index 10d24dd096e8..f6e8354b8cea 100644 --- a/fs/proc/namespaces.c +++ b/fs/proc/namespaces.c @@ -30,7 +30,7 @@ static const struct proc_ns_operations *ns_entries[] = { &mntns_operations, }; -static const char *proc_ns_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *proc_ns_follow_link(struct dentry *dentry, void **cookie) { struct inode *inode = d_inode(dentry); const struct proc_ns_operations *ns_ops = PROC_I(inode)->ns_ops; @@ -45,7 +45,7 @@ static const char *proc_ns_follow_link(struct dentry *dentry, void **cookie, str if (ptrace_may_access(task, PTRACE_MODE_READ)) { error = ns_get_path(&ns_path, task, ns_ops); if (!error) - nd_jump_link(nd, &ns_path); + nd_jump_link(&ns_path); } put_task_struct(task); return error; diff --git a/fs/proc/self.c b/fs/proc/self.c index ad333946b53a..113b8d061fc0 100644 --- a/fs/proc/self.c +++ b/fs/proc/self.c @@ -18,7 +18,7 @@ static int proc_self_readlink(struct dentry *dentry, char __user *buffer, return readlink_copy(buffer, buflen, tmp); } -static const char *proc_self_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *proc_self_follow_link(struct dentry *dentry, void **cookie) { struct pid_namespace *ns = dentry->d_sb->s_fs_info; pid_t tgid = task_tgid_nr_ns(current, ns); diff --git a/fs/proc/thread_self.c b/fs/proc/thread_self.c index 85c96e0d7aaa..947b0f4fd0a1 100644 --- a/fs/proc/thread_self.c +++ b/fs/proc/thread_self.c @@ -19,7 +19,7 @@ static int proc_thread_self_readlink(struct dentry *dentry, char __user *buffer, return readlink_copy(buffer, buflen, tmp); } -static const char *proc_thread_self_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *proc_thread_self_follow_link(struct dentry *dentry, void **cookie) { struct pid_namespace *ns = dentry->d_sb->s_fs_info; pid_t tgid = task_tgid_nr_ns(current, ns); diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c index 26c4dcb1ef56..7f51f39f8acc 100644 --- a/fs/xfs/xfs_iops.c +++ b/fs/xfs/xfs_iops.c @@ -416,8 +416,7 @@ xfs_vn_rename( STATIC const char * xfs_vn_follow_link( struct dentry *dentry, - void **cookie, - struct nameidata *nd) + void **cookie) { char *link; int error = -ENOMEM; diff --git a/include/linux/fs.h b/include/linux/fs.h index 9ab934113a28..ed7c9f298759 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1608,7 +1608,7 @@ struct file_operations { struct inode_operations { struct dentry * (*lookup) (struct inode *,struct dentry *, unsigned int); - const char * (*follow_link) (struct dentry *, void **, struct nameidata *); + const char * (*follow_link) (struct dentry *, void **); int (*permission) (struct inode *, int); struct posix_acl * (*get_acl)(struct inode *, int); @@ -2705,7 +2705,7 @@ extern const struct file_operations generic_ro_fops; extern int readlink_copy(char __user *, int, const char *); extern int page_readlink(struct dentry *, char __user *, int); -extern const char *page_follow_link_light(struct dentry *, void **, struct nameidata *); +extern const char *page_follow_link_light(struct dentry *, void **); extern void page_put_link(struct dentry *, void *); extern int __page_symlink(struct inode *inode, const char *symname, int len, int nofs); @@ -2722,7 +2722,7 @@ void __inode_sub_bytes(struct inode *inode, loff_t bytes); void inode_sub_bytes(struct inode *inode, loff_t bytes); loff_t inode_get_bytes(struct inode *inode); void inode_set_bytes(struct inode *inode, loff_t bytes); -const char *simple_follow_link(struct dentry *, void **, struct nameidata *); +const char *simple_follow_link(struct dentry *, void **); extern const struct inode_operations simple_symlink_inode_operations; extern int iterate_dir(struct file *, struct dir_context *); diff --git a/include/linux/namei.h b/include/linux/namei.h index 3a6cc9651712..d756304aa09b 100644 --- a/include/linux/namei.h +++ b/include/linux/namei.h @@ -72,7 +72,7 @@ extern int follow_up(struct path *); extern struct dentry *lock_rename(struct dentry *, struct dentry *); extern void unlock_rename(struct dentry *, struct dentry *); -extern void nd_jump_link(struct nameidata *nd, struct path *path); +extern void nd_jump_link(struct path *path); static inline void nd_terminate_link(void *name, size_t len, size_t maxlen) { diff --git a/mm/shmem.c b/mm/shmem.c index d1693dcb4285..e02682267046 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2475,7 +2475,7 @@ static int shmem_symlink(struct inode *dir, struct dentry *dentry, const char *s return 0; } -static const char *shmem_follow_link(struct dentry *dentry, void **cookie, struct nameidata *nd) +static const char *shmem_follow_link(struct dentry *dentry, void **cookie) { struct page *page = NULL; int error = shmem_getpage(d_inode(dentry), 0, &page, SGP_READ, NULL); -- cgit v1.2.3 From 22869a9eca4ea5b534538d160b68c7aef44e378a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 3 Mar 2015 09:52:20 +0100 Subject: MFD/OF: document MFD devices and handle simple-mfd This defines a new compatible option for MFD devices "simple-mfd" that will make the OF core spawn child devices for all subnodes of that MFD device. It is optional but handy for things like syscon and possibly other simpler MFD devices. Since there was no file to put the documentation in, I took this opportunity to make a small writeup on MFD devices and add the compatible definition there. Suggested-by: Lee Jones Acked-by: Lee Jones Acked-by: Antoine Tenart Acked-by: Alexandre Belloni Cc: Arnd Bergmann Cc: Devicetree Cc: Rob Herring Cc: Benjamin Herrenschmidt Cc: Grant Likely Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/mfd/mfd.txt | 41 +++++++++++++++++++++++++++ drivers/of/platform.c | 1 + 2 files changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mfd.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/mfd.txt b/Documentation/devicetree/bindings/mfd/mfd.txt new file mode 100644 index 000000000000..af9d6931a1a2 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mfd.txt @@ -0,0 +1,41 @@ +Multi-Function Devices (MFD) + +These devices comprise a nexus for heterogeneous hardware blocks containing +more than one non-unique yet varying hardware functionality. + +A typical MFD can be: + +- A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management + Integrated Circuit) that is manufactured in a lower technology node (rough + silicon) that handles analog drivers for things like audio amplifiers, LED + drivers, level shifters, PHY (physical interfaces to things like USB or + ethernet), regulators etc. + +- A range of memory registers containing "miscellaneous system registers" also + known as a system controller "syscon" or any other memory range containing a + mix of unrelated hardware devices. + +Optional properties: + +- compatible : "simple-mfd" - this signifies that the operating system should + consider all subnodes of the MFD device as separate devices akin to how + "simple-bus" inidicates when to see subnodes as children for a simple + memory-mapped bus. For more complex devices, when the nexus driver has to + probe registers to figure out what child devices exist etc, this should not + be used. In the latter case the child devices will be determined by the + operating system. + +Example: + +foo@1000 { + compatible = "syscon", "simple-mfd"; + reg = <0x01000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "myled"; + default-state = "on"; + }; +}; diff --git a/drivers/of/platform.c b/drivers/of/platform.c index a01f57c9e34e..ddf8e42c9367 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -25,6 +25,7 @@ const struct of_device_id of_default_bus_match_table[] = { { .compatible = "simple-bus", }, + { .compatible = "simple-mfd", }, #ifdef CONFIG_ARM_AMBA { .compatible = "arm,amba-bus", }, #endif /* CONFIG_ARM_AMBA */ -- cgit v1.2.3 From d4bd441532b81fe2be1706e7f9dbbe8b5a364bcf Mon Sep 17 00:00:00 2001 From: Miroslav Benes Date: Mon, 11 May 2015 10:15:48 +0200 Subject: x86/kaslr: Fix typo in the KASLR_FLAG documentation Documentation/x86/boot.txt labels the bit in boot_params.hdr.loadflags as ALSR_FLAG while it should be KASLR_FLAG. Signed-off-by: Miroslav Benes Signed-off-by: Borislav Petkov Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Jiri Kosina Cc: Jonathan Corbet Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1429011324-7170-1-git-send-email-mbenes@suse.cz Link: http://lkml.kernel.org/r/1431332153-18566-4-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/boot.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/x86/boot.txt b/Documentation/x86/boot.txt index 88b85899d309..69e139791868 100644 --- a/Documentation/x86/boot.txt +++ b/Documentation/x86/boot.txt @@ -406,7 +406,7 @@ Protocol: 2.00+ - If 0, the protected-mode code is loaded at 0x10000. - If 1, the protected-mode code is loaded at 0x100000. - Bit 1 (kernel internal): ALSR_FLAG + Bit 1 (kernel internal): KASLR_FLAG - Used internally by the compressed kernel to communicate KASLR status to kernel proper. If 1, KASLR enabled. -- cgit v1.2.3 From 5f2c4179e129bdc47870a81a65d0aff85aa18293 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Thu, 7 May 2015 11:14:26 -0400 Subject: switch ->put_link() from dentry to inode only one instance looks at that argument at all; that sole exception wants inode rather than dentry. Signed-off-by: Al Viro --- Documentation/filesystems/Locking | 2 +- Documentation/filesystems/vfs.txt | 2 +- drivers/staging/lustre/lustre/llite/symlink.c | 2 +- fs/configfs/symlink.c | 2 +- fs/f2fs/namei.c | 2 +- fs/fuse/dir.c | 2 +- fs/hostfs/hostfs_kern.c | 2 +- fs/hppfs/hppfs.c | 8 ++++---- fs/kernfs/symlink.c | 2 +- fs/libfs.c | 2 +- fs/namei.c | 13 +++++++------ fs/overlayfs/inode.c | 4 ++-- fs/proc/inode.c | 2 +- include/linux/fs.h | 6 +++--- mm/shmem.c | 2 +- 15 files changed, 27 insertions(+), 26 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 5b5b4f54c033..6a34a0f4d37c 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -51,7 +51,7 @@ prototypes: struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); const char *(*follow_link) (struct dentry *, void **); - void (*put_link) (struct dentry *, void *); + void (*put_link) (struct inode *, void *); void (*truncate) (struct inode *); int (*permission) (struct inode *, int, unsigned int); int (*get_acl)(struct inode *, int); diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index 0dec8c880be6..542d9352d0f2 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -351,7 +351,7 @@ struct inode_operations { struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); const char *(*follow_link) (struct dentry *, void **); - void (*put_link) (struct dentry *, void *); + void (*put_link) (struct inode *, void *); int (*permission) (struct inode *, int); int (*get_acl)(struct inode *, int); int (*setattr) (struct dentry *, struct iattr *); diff --git a/drivers/staging/lustre/lustre/llite/symlink.c b/drivers/staging/lustre/lustre/llite/symlink.c index f3be3bf0f66f..69b203651905 100644 --- a/drivers/staging/lustre/lustre/llite/symlink.c +++ b/drivers/staging/lustre/lustre/llite/symlink.c @@ -141,7 +141,7 @@ static const char *ll_follow_link(struct dentry *dentry, void **cookie) return symname; } -static void ll_put_link(struct dentry *dentry, void *cookie) +static void ll_put_link(struct inode *unused, void *cookie) { ptlrpc_req_finished(cookie); } diff --git a/fs/configfs/symlink.c b/fs/configfs/symlink.c index 0ace75649009..bc464c26e00e 100644 --- a/fs/configfs/symlink.c +++ b/fs/configfs/symlink.c @@ -296,7 +296,7 @@ static const char *configfs_follow_link(struct dentry *dentry, void **cookie) return ERR_PTR(error); } -static void configfs_put_link(struct dentry *dentry, void *cookie) +static void configfs_put_link(struct inode *unused, void *cookie) { free_page((unsigned long)cookie); } diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index cd05a7c91533..71765d062914 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -301,7 +301,7 @@ static const char *f2fs_follow_link(struct dentry *dentry, void **cookie) const char *link = page_follow_link_light(dentry, cookie); if (!IS_ERR(link) && !*link) { /* this is broken symlink case */ - page_put_link(dentry, *cookie); + page_put_link(NULL, *cookie); link = ERR_PTR(-ENOENT); } return link; diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index d5cdef8b7f3a..9e704c124392 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -1395,7 +1395,7 @@ static const char *fuse_follow_link(struct dentry *dentry, void **cookie) return link; } -static void fuse_put_link(struct dentry *dentry, void *cookie) +static void fuse_put_link(struct inode *unused, void *cookie) { free_page((unsigned long) cookie); } diff --git a/fs/hostfs/hostfs_kern.c b/fs/hostfs/hostfs_kern.c index 7b6ed7a908f6..4a437ab5f296 100644 --- a/fs/hostfs/hostfs_kern.c +++ b/fs/hostfs/hostfs_kern.c @@ -915,7 +915,7 @@ static const char *hostfs_follow_link(struct dentry *dentry, void **cookie) return *cookie = link; } -static void hostfs_put_link(struct dentry *dentry, void *cookie) +static void hostfs_put_link(struct inode *unused, void *cookie) { __putname(cookie); } diff --git a/fs/hppfs/hppfs.c b/fs/hppfs/hppfs.c index 15a774eb5bbf..2867837909a9 100644 --- a/fs/hppfs/hppfs.c +++ b/fs/hppfs/hppfs.c @@ -649,12 +649,12 @@ static const char *hppfs_follow_link(struct dentry *dentry, void **cookie) return d_inode(proc_dentry)->i_op->follow_link(proc_dentry, cookie); } -static void hppfs_put_link(struct dentry *dentry, void *cookie) +static void hppfs_put_link(struct inode *inode, void *cookie) { - struct dentry *proc_dentry = HPPFS_I(d_inode(dentry))->proc_dentry; + struct inode *proc_inode = d_inode(HPPFS_I(inode)->proc_dentry); - if (d_inode(proc_dentry)->i_op->put_link) - d_inode(proc_dentry)->i_op->put_link(proc_dentry, cookie); + if (proc_inode->i_op->put_link) + proc_inode->i_op->put_link(proc_inode, cookie); } static const struct inode_operations hppfs_dir_iops = { diff --git a/fs/kernfs/symlink.c b/fs/kernfs/symlink.c index 366c5a17475e..f6aa2e5a76b4 100644 --- a/fs/kernfs/symlink.c +++ b/fs/kernfs/symlink.c @@ -126,7 +126,7 @@ static const char *kernfs_iop_follow_link(struct dentry *dentry, void **cookie) return *cookie = (char *)page; } -static void kernfs_iop_put_link(struct dentry *dentry, void *cookie) +static void kernfs_iop_put_link(struct inode *unused, void *cookie) { free_page((unsigned long)cookie); } diff --git a/fs/libfs.c b/fs/libfs.c index c5f3373e326b..01c337b0fec8 100644 --- a/fs/libfs.c +++ b/fs/libfs.c @@ -1024,7 +1024,7 @@ int noop_fsync(struct file *file, loff_t start, loff_t end, int datasync) } EXPORT_SYMBOL(noop_fsync); -void kfree_put_link(struct dentry *dentry, void *cookie) +void kfree_put_link(struct inode *unused, void *cookie) { kfree(cookie); } diff --git a/fs/namei.c b/fs/namei.c index 0fa7af23cff6..43034046a0e1 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -749,7 +749,7 @@ static inline void put_link(struct nameidata *nd) struct saved *last = nd->stack + --nd->depth; struct inode *inode = last->inode; if (last->cookie && inode->i_op->put_link) - inode->i_op->put_link(last->link.dentry, last->cookie); + inode->i_op->put_link(inode, last->cookie); path_put(&last->link); } @@ -4444,17 +4444,18 @@ EXPORT_SYMBOL(readlink_copy); int generic_readlink(struct dentry *dentry, char __user *buffer, int buflen) { void *cookie; - const char *link = dentry->d_inode->i_link; + struct inode *inode = d_inode(dentry); + const char *link = inode->i_link; int res; if (!link) { - link = dentry->d_inode->i_op->follow_link(dentry, &cookie); + link = inode->i_op->follow_link(dentry, &cookie); if (IS_ERR(link)) return PTR_ERR(link); } res = readlink_copy(buffer, buflen, link); - if (dentry->d_inode->i_op->put_link) - dentry->d_inode->i_op->put_link(dentry, cookie); + if (inode->i_op->put_link) + inode->i_op->put_link(inode, cookie); return res; } EXPORT_SYMBOL(generic_readlink); @@ -4496,7 +4497,7 @@ const char *page_follow_link_light(struct dentry *dentry, void **cookie) } EXPORT_SYMBOL(page_follow_link_light); -void page_put_link(struct dentry *dentry, void *cookie) +void page_put_link(struct inode *unused, void *cookie) { struct page *page = cookie; kunmap(page); diff --git a/fs/overlayfs/inode.c b/fs/overlayfs/inode.c index 9986833c9fcc..308379b2d0b2 100644 --- a/fs/overlayfs/inode.c +++ b/fs/overlayfs/inode.c @@ -174,7 +174,7 @@ static const char *ovl_follow_link(struct dentry *dentry, void **cookie) return ret; } -static void ovl_put_link(struct dentry *dentry, void *c) +static void ovl_put_link(struct inode *unused, void *c) { struct inode *realinode; struct ovl_link_data *data = c; @@ -183,7 +183,7 @@ static void ovl_put_link(struct dentry *dentry, void *c) return; realinode = data->realdentry->d_inode; - realinode->i_op->put_link(data->realdentry, data->cookie); + realinode->i_op->put_link(realinode, data->cookie); kfree(data); } diff --git a/fs/proc/inode.c b/fs/proc/inode.c index eb35874fe09c..afe232b9df6e 100644 --- a/fs/proc/inode.c +++ b/fs/proc/inode.c @@ -402,7 +402,7 @@ static const char *proc_follow_link(struct dentry *dentry, void **cookie) return pde->data; } -static void proc_put_link(struct dentry *dentry, void *p) +static void proc_put_link(struct inode *unused, void *p) { unuse_pde(p); } diff --git a/include/linux/fs.h b/include/linux/fs.h index ed7c9f298759..f21e3328f991 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1613,7 +1613,7 @@ struct inode_operations { struct posix_acl * (*get_acl)(struct inode *, int); int (*readlink) (struct dentry *, char __user *,int); - void (*put_link) (struct dentry *, void *); + void (*put_link) (struct inode *, void *); int (*create) (struct inode *,struct dentry *, umode_t, bool); int (*link) (struct dentry *,struct inode *,struct dentry *); @@ -2706,12 +2706,12 @@ extern const struct file_operations generic_ro_fops; extern int readlink_copy(char __user *, int, const char *); extern int page_readlink(struct dentry *, char __user *, int); extern const char *page_follow_link_light(struct dentry *, void **); -extern void page_put_link(struct dentry *, void *); +extern void page_put_link(struct inode *, void *); extern int __page_symlink(struct inode *inode, const char *symname, int len, int nofs); extern int page_symlink(struct inode *inode, const char *symname, int len); extern const struct inode_operations page_symlink_inode_operations; -extern void kfree_put_link(struct dentry *, void *); +extern void kfree_put_link(struct inode *, void *); extern int generic_readlink(struct dentry *, char __user *, int); extern void generic_fillattr(struct inode *, struct kstat *); int vfs_getattr_nosec(struct path *path, struct kstat *stat); diff --git a/mm/shmem.c b/mm/shmem.c index e02682267046..a59087edf728 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2486,7 +2486,7 @@ static const char *shmem_follow_link(struct dentry *dentry, void **cookie) return kmap(page); } -static void shmem_put_link(struct dentry *dentry, void *cookie) +static void shmem_put_link(struct inode *unused, void *cookie) { struct page *page = cookie; kunmap(page); -- cgit v1.2.3 From 6791e4661c4bd3e9f193a84247f2c389578a4336 Mon Sep 17 00:00:00 2001 From: Mahesh Bandewar Date: Sat, 9 May 2015 00:01:55 -0700 Subject: bonding: Allow userspace to set actors' system_priority in AD system This patch allows user to randomize the system-priority in an ad-system. The allowed range is 1 - 0xFFFF while default value is 0xFFFF. If user does not specify this value, the system defaults to 0xFFFF, which is what it was before this patch. Following example code could set the value - # modprobe bonding mode=4 # sys_prio=$(( 1 + RANDOM + RANDOM )) # echo $sys_prio > /sys/class/net/bond0/bonding/ad_actor_sys_prio # echo +eth1 > /sys/class/net/bond0/bonding/slaves ... # ip link set bond0 up Signed-off-by: Mahesh Bandewar Reviewed-by: Nikolay Aleksandrov [jt: * fixed up style issues reported by checkpatch * changed how the default value is set in bond_check_params(), this makes the default consistent between what gets set for a new bond and what the default is claimed to be in the bonding options.] Signed-off-by: Jonathan Toppins Signed-off-by: David S. Miller --- Documentation/networking/bonding.txt | 9 +++++++++ drivers/net/bonding/bond_3ad.c | 5 ++++- drivers/net/bonding/bond_main.c | 12 ++++++++++++ drivers/net/bonding/bond_options.c | 28 +++++++++++++++++++++++++++- drivers/net/bonding/bond_procfs.c | 2 ++ drivers/net/bonding/bond_sysfs.c | 15 +++++++++++++++ include/net/bond_options.h | 1 + include/net/bonding.h | 1 + 8 files changed, 71 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt index 83bf4986baea..34946115acec 100644 --- a/Documentation/networking/bonding.txt +++ b/Documentation/networking/bonding.txt @@ -178,6 +178,15 @@ active_slave active slave, or the empty string if there is no active slave or the current mode does not use an active slave. +ad_actor_sys_prio + + In an AD system, this specifies the system priority. The allowed range + is 1 - 65535. If the value is not specified, it takes 65535 as the + default value. + + This parameter has effect only in 802.3ad mode and is available through + SysFs interface. + ad_select Specifies the 802.3ad aggregation selection logic to use. The diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c index fbd54f0e32e8..4c003bc87d4b 100644 --- a/drivers/net/bonding/bond_3ad.c +++ b/drivers/net/bonding/bond_3ad.c @@ -1908,7 +1908,8 @@ void bond_3ad_initialize(struct bonding *bond, u16 tick_resolution) BOND_AD_INFO(bond).aggregator_identifier = 0; - BOND_AD_INFO(bond).system.sys_priority = 0xFFFF; + BOND_AD_INFO(bond).system.sys_priority = + bond->params.ad_actor_sys_prio; BOND_AD_INFO(bond).system.sys_mac_addr = *((struct mac_addr *)bond->dev->dev_addr); /* initialize how many times this module is called in one @@ -1959,6 +1960,8 @@ void bond_3ad_bind_slave(struct slave *slave) port->sm_vars &= ~AD_PORT_LACP_ENABLED; /* actor system is the bond's system */ port->actor_system = BOND_AD_INFO(bond).system.sys_mac_addr; + port->actor_system_priority = + BOND_AD_INFO(bond).system.sys_priority; /* tx timer(to verify that no more than MAX_TX_IN_SECOND * lacpdu's are sent in one second) */ diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index d5fe5d5f490f..5f2f28f0e927 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -4140,6 +4140,7 @@ static int bond_check_params(struct bond_params *params) struct bond_opt_value newval; const struct bond_opt_value *valptr; int arp_all_targets_value; + u16 ad_actor_sys_prio = 0; /* Convert string parameters. */ if (mode) { @@ -4434,6 +4435,16 @@ static int bond_check_params(struct bond_params *params) fail_over_mac_value = BOND_FOM_NONE; } + bond_opt_initstr(&newval, "default"); + valptr = bond_opt_parse( + bond_opt_get(BOND_OPT_AD_ACTOR_SYS_PRIO), + &newval); + if (!valptr) { + pr_err("Error: No ad_actor_sys_prio default value"); + return -EINVAL; + } + ad_actor_sys_prio = valptr->value; + if (lp_interval == 0) { pr_warn("Warning: ip_interval must be between 1 and %d, so it was reset to %d\n", INT_MAX, BOND_ALB_DEFAULT_LP_INTERVAL); @@ -4462,6 +4473,7 @@ static int bond_check_params(struct bond_params *params) params->lp_interval = lp_interval; params->packets_per_slave = packets_per_slave; params->tlb_dynamic_lb = 1; /* Default value */ + params->ad_actor_sys_prio = ad_actor_sys_prio; if (packets_per_slave > 0) { params->reciprocal_packets_per_slave = reciprocal_value(packets_per_slave); diff --git a/drivers/net/bonding/bond_options.c b/drivers/net/bonding/bond_options.c index 4df28943d222..d2b47e5e99f7 100644 --- a/drivers/net/bonding/bond_options.c +++ b/drivers/net/bonding/bond_options.c @@ -70,6 +70,8 @@ static int bond_option_slaves_set(struct bonding *bond, const struct bond_opt_value *newval); static int bond_option_tlb_dynamic_lb_set(struct bonding *bond, const struct bond_opt_value *newval); +static int bond_option_ad_actor_sys_prio_set(struct bonding *bond, + const struct bond_opt_value *newval); static const struct bond_opt_value bond_mode_tbl[] = { @@ -186,6 +188,12 @@ static const struct bond_opt_value bond_tlb_dynamic_lb_tbl[] = { { NULL, -1, 0} }; +static const struct bond_opt_value bond_ad_actor_sys_prio_tbl[] = { + { "minval", 1, BOND_VALFLAG_MIN}, + { "maxval", 65535, BOND_VALFLAG_MAX | BOND_VALFLAG_DEFAULT}, + { NULL, -1, 0}, +}; + static const struct bond_option bond_opts[BOND_OPT_LAST] = { [BOND_OPT_MODE] = { .id = BOND_OPT_MODE, @@ -379,7 +387,15 @@ static const struct bond_option bond_opts[BOND_OPT_LAST] = { .values = bond_tlb_dynamic_lb_tbl, .flags = BOND_OPTFLAG_IFDOWN, .set = bond_option_tlb_dynamic_lb_set, - } + }, + [BOND_OPT_AD_ACTOR_SYS_PRIO] = { + .id = BOND_OPT_AD_ACTOR_SYS_PRIO, + .name = "ad_actor_sys_prio", + .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), + .flags = BOND_OPTFLAG_IFDOWN, + .values = bond_ad_actor_sys_prio_tbl, + .set = bond_option_ad_actor_sys_prio_set, + }, }; /* Searches for an option by name */ @@ -1349,3 +1365,13 @@ static int bond_option_tlb_dynamic_lb_set(struct bonding *bond, return 0; } + +static int bond_option_ad_actor_sys_prio_set(struct bonding *bond, + const struct bond_opt_value *newval) +{ + netdev_info(bond->dev, "Setting ad_actor_sys_prio to (%llu)\n", + newval->value); + + bond->params.ad_actor_sys_prio = newval->value; + return 0; +} diff --git a/drivers/net/bonding/bond_procfs.c b/drivers/net/bonding/bond_procfs.c index b20b35acb47d..11369299e7e5 100644 --- a/drivers/net/bonding/bond_procfs.c +++ b/drivers/net/bonding/bond_procfs.c @@ -135,6 +135,8 @@ static void bond_info_show_master(struct seq_file *seq) bond->params.ad_select); seq_printf(seq, "Aggregator selection policy (ad_select): %s\n", optval->string); + seq_printf(seq, "System priority: %d\n", + BOND_AD_INFO(bond).system.sys_priority); if (__bond_3ad_get_active_agg_info(bond, &ad_info)) { seq_printf(seq, "bond %s has no active aggregator\n", diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index 7e9e151d4d61..4a7626611ca6 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c @@ -692,6 +692,20 @@ static ssize_t bonding_show_packets_per_slave(struct device *d, static DEVICE_ATTR(packets_per_slave, S_IRUGO | S_IWUSR, bonding_show_packets_per_slave, bonding_sysfs_store_option); +static ssize_t bonding_show_ad_actor_sys_prio(struct device *d, + struct device_attribute *attr, + char *buf) +{ + struct bonding *bond = to_bond(d); + + if (BOND_MODE(bond) == BOND_MODE_8023AD) + return sprintf(buf, "%hu\n", bond->params.ad_actor_sys_prio); + + return 0; +} +static DEVICE_ATTR(ad_actor_sys_prio, S_IRUGO | S_IWUSR, + bonding_show_ad_actor_sys_prio, bonding_sysfs_store_option); + static struct attribute *per_bond_attrs[] = { &dev_attr_slaves.attr, &dev_attr_mode.attr, @@ -725,6 +739,7 @@ static struct attribute *per_bond_attrs[] = { &dev_attr_lp_interval.attr, &dev_attr_packets_per_slave.attr, &dev_attr_tlb_dynamic_lb.attr, + &dev_attr_ad_actor_sys_prio.attr, NULL, }; diff --git a/include/net/bond_options.h b/include/net/bond_options.h index ea6546d2c946..894002a2620f 100644 --- a/include/net/bond_options.h +++ b/include/net/bond_options.h @@ -63,6 +63,7 @@ enum { BOND_OPT_LP_INTERVAL, BOND_OPT_SLAVES, BOND_OPT_TLB_DYNAMIC_LB, + BOND_OPT_AD_ACTOR_SYS_PRIO, BOND_OPT_LAST }; diff --git a/include/net/bonding.h b/include/net/bonding.h index 78ed135e9dea..405cf87a450a 100644 --- a/include/net/bonding.h +++ b/include/net/bonding.h @@ -136,6 +136,7 @@ struct bond_params { int packets_per_slave; int tlb_dynamic_lb; struct reciprocal_value reciprocal_packets_per_slave; + u16 ad_actor_sys_prio; }; struct bond_parm_tbl { -- cgit v1.2.3 From 74514957552edd4661a4608618121f3c71d4e891 Mon Sep 17 00:00:00 2001 From: Mahesh Bandewar Date: Sat, 9 May 2015 00:01:56 -0700 Subject: bonding: Allow userspace to set actors' macaddr in an AD-system. In an AD system, the communication between actor and partner is the business between these two entities. In the current setup anyone on the same L2 can "guess" the LACPDU contents and then possibly send the spoofed LACPDUs and trick the partner causing connectivity issues for the AD system. This patch allows to use a random mac-address obscuring it's identity making it harder for someone in the L2 is do the same thing. This patch allows user-space to choose the mac-address for the AD-system. This mac-address can not be NULL or a Multicast. If the mac-address is set from user-space; kernel will honor it and will not overwrite it. In the absence (value from user space); the logic will default to using the masters' mac as the mac-address for the AD-system. It can be set using example code below - # modprobe bonding mode=4 # sys_mac_addr=$(printf '%02x:%02x:%02x:%02x:%02x:%02x' \ $(( (RANDOM & 0xFE) | 0x02 )) \ $(( RANDOM & 0xFF )) \ $(( RANDOM & 0xFF )) \ $(( RANDOM & 0xFF )) \ $(( RANDOM & 0xFF )) \ $(( RANDOM & 0xFF ))) # echo $sys_mac_addr > /sys/class/net/bond0/bonding/ad_actor_system # echo +eth1 > /sys/class/net/bond0/bonding/slaves ... # ip link set bond0 up Signed-off-by: Mahesh Bandewar Reviewed-by: Nikolay Aleksandrov [jt: fixed up style issues reported by checkpatch] Signed-off-by: Jonathan Toppins Signed-off-by: David S. Miller --- Documentation/networking/bonding.txt | 12 ++++++++++++ drivers/net/bonding/bond_3ad.c | 7 ++++++- drivers/net/bonding/bond_main.c | 1 + drivers/net/bonding/bond_options.c | 27 +++++++++++++++++++++++++++ drivers/net/bonding/bond_procfs.c | 6 ++++++ drivers/net/bonding/bond_sysfs.c | 16 ++++++++++++++++ include/net/bond_options.h | 1 + include/net/bonding.h | 1 + 8 files changed, 70 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt index 34946115acec..2c197b68baf0 100644 --- a/Documentation/networking/bonding.txt +++ b/Documentation/networking/bonding.txt @@ -187,6 +187,18 @@ ad_actor_sys_prio This parameter has effect only in 802.3ad mode and is available through SysFs interface. +ad_actor_system + + In an AD system, this specifies the mac-address for the actor in + protocol packet exchanges (LACPDUs). The value cannot be NULL or + multicast. It is preferred to have the local-admin bit set for this + mac but driver does not enforce it. If the value is not given then + system defaults to using the masters' mac address as actors' system + address. + + This parameter has effect only in 802.3ad mode and is available through + SysFs interface. + ad_select Specifies the 802.3ad aggregation selection logic to use. The diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c index 4c003bc87d4b..012f7bc22d91 100644 --- a/drivers/net/bonding/bond_3ad.c +++ b/drivers/net/bonding/bond_3ad.c @@ -1910,7 +1910,12 @@ void bond_3ad_initialize(struct bonding *bond, u16 tick_resolution) BOND_AD_INFO(bond).system.sys_priority = bond->params.ad_actor_sys_prio; - BOND_AD_INFO(bond).system.sys_mac_addr = *((struct mac_addr *)bond->dev->dev_addr); + if (is_zero_ether_addr(bond->params.ad_actor_system)) + BOND_AD_INFO(bond).system.sys_mac_addr = + *((struct mac_addr *)bond->dev->dev_addr); + else + BOND_AD_INFO(bond).system.sys_mac_addr = + *((struct mac_addr *)bond->params.ad_actor_system); /* initialize how many times this module is called in one * second (should be about every 100ms) diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 5f2f28f0e927..a4e2f27ef683 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -4474,6 +4474,7 @@ static int bond_check_params(struct bond_params *params) params->packets_per_slave = packets_per_slave; params->tlb_dynamic_lb = 1; /* Default value */ params->ad_actor_sys_prio = ad_actor_sys_prio; + eth_zero_addr(params->ad_actor_system); if (packets_per_slave > 0) { params->reciprocal_packets_per_slave = reciprocal_value(packets_per_slave); diff --git a/drivers/net/bonding/bond_options.c b/drivers/net/bonding/bond_options.c index d2b47e5e99f7..cdcef217ac84 100644 --- a/drivers/net/bonding/bond_options.c +++ b/drivers/net/bonding/bond_options.c @@ -72,6 +72,8 @@ static int bond_option_tlb_dynamic_lb_set(struct bonding *bond, const struct bond_opt_value *newval); static int bond_option_ad_actor_sys_prio_set(struct bonding *bond, const struct bond_opt_value *newval); +static int bond_option_ad_actor_system_set(struct bonding *bond, + const struct bond_opt_value *newval); static const struct bond_opt_value bond_mode_tbl[] = { @@ -396,6 +398,13 @@ static const struct bond_option bond_opts[BOND_OPT_LAST] = { .values = bond_ad_actor_sys_prio_tbl, .set = bond_option_ad_actor_sys_prio_set, }, + [BOND_OPT_AD_ACTOR_SYSTEM] = { + .id = BOND_OPT_AD_ACTOR_SYSTEM, + .name = "ad_actor_system", + .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), + .flags = BOND_OPTFLAG_RAWVAL | BOND_OPTFLAG_IFDOWN, + .set = bond_option_ad_actor_system_set, + }, }; /* Searches for an option by name */ @@ -1375,3 +1384,21 @@ static int bond_option_ad_actor_sys_prio_set(struct bonding *bond, bond->params.ad_actor_sys_prio = newval->value; return 0; } + +static int bond_option_ad_actor_system_set(struct bonding *bond, + const struct bond_opt_value *newval) +{ + u8 macaddr[ETH_ALEN]; + int i; + + i = sscanf(newval->string, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &macaddr[0], &macaddr[1], &macaddr[2], + &macaddr[3], &macaddr[4], &macaddr[5]); + if (i != ETH_ALEN || !is_valid_ether_addr(macaddr)) { + netdev_err(bond->dev, "Invalid MAC address.\n"); + return -EINVAL; + } + + ether_addr_copy(bond->params.ad_actor_system, macaddr); + return 0; +} diff --git a/drivers/net/bonding/bond_procfs.c b/drivers/net/bonding/bond_procfs.c index 11369299e7e5..e7f3047a26df 100644 --- a/drivers/net/bonding/bond_procfs.c +++ b/drivers/net/bonding/bond_procfs.c @@ -137,6 +137,8 @@ static void bond_info_show_master(struct seq_file *seq) optval->string); seq_printf(seq, "System priority: %d\n", BOND_AD_INFO(bond).system.sys_priority); + seq_printf(seq, "System MAC address: %pM\n", + &BOND_AD_INFO(bond).system.sys_mac_addr); if (__bond_3ad_get_active_agg_info(bond, &ad_info)) { seq_printf(seq, "bond %s has no active aggregator\n", @@ -200,6 +202,8 @@ static void bond_info_show_slave(struct seq_file *seq, seq_puts(seq, "details actor lacp pdu:\n"); seq_printf(seq, " system priority: %d\n", port->actor_system_priority); + seq_printf(seq, " system mac address: %pM\n", + &port->actor_system); seq_printf(seq, " port key: %d\n", port->actor_oper_port_key); seq_printf(seq, " port priority: %d\n", @@ -212,6 +216,8 @@ static void bond_info_show_slave(struct seq_file *seq, seq_puts(seq, "details partner lacp pdu:\n"); seq_printf(seq, " system priority: %d\n", port->partner_oper.system_priority); + seq_printf(seq, " system mac address: %pM\n", + &port->partner_oper.system); seq_printf(seq, " oper key: %d\n", port->partner_oper.key); seq_printf(seq, " port priority: %d\n", diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index 4a7626611ca6..09fefa50d055 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c @@ -706,6 +706,21 @@ static ssize_t bonding_show_ad_actor_sys_prio(struct device *d, static DEVICE_ATTR(ad_actor_sys_prio, S_IRUGO | S_IWUSR, bonding_show_ad_actor_sys_prio, bonding_sysfs_store_option); +static ssize_t bonding_show_ad_actor_system(struct device *d, + struct device_attribute *attr, + char *buf) +{ + struct bonding *bond = to_bond(d); + + if (BOND_MODE(bond) == BOND_MODE_8023AD) + return sprintf(buf, "%pM\n", bond->params.ad_actor_system); + + return 0; +} + +static DEVICE_ATTR(ad_actor_system, S_IRUGO | S_IWUSR, + bonding_show_ad_actor_system, bonding_sysfs_store_option); + static struct attribute *per_bond_attrs[] = { &dev_attr_slaves.attr, &dev_attr_mode.attr, @@ -740,6 +755,7 @@ static struct attribute *per_bond_attrs[] = { &dev_attr_packets_per_slave.attr, &dev_attr_tlb_dynamic_lb.attr, &dev_attr_ad_actor_sys_prio.attr, + &dev_attr_ad_actor_system.attr, NULL, }; diff --git a/include/net/bond_options.h b/include/net/bond_options.h index 894002a2620f..eeeefa1d3cd8 100644 --- a/include/net/bond_options.h +++ b/include/net/bond_options.h @@ -64,6 +64,7 @@ enum { BOND_OPT_SLAVES, BOND_OPT_TLB_DYNAMIC_LB, BOND_OPT_AD_ACTOR_SYS_PRIO, + BOND_OPT_AD_ACTOR_SYSTEM, BOND_OPT_LAST }; diff --git a/include/net/bonding.h b/include/net/bonding.h index 405cf87a450a..650f38693956 100644 --- a/include/net/bonding.h +++ b/include/net/bonding.h @@ -137,6 +137,7 @@ struct bond_params { int tlb_dynamic_lb; struct reciprocal_value reciprocal_packets_per_slave; u16 ad_actor_sys_prio; + u8 ad_actor_system[ETH_ALEN]; }; struct bond_parm_tbl { -- cgit v1.2.3 From d22a5fc0c32edcf5c3bb973ee8c9a2606ba500a8 Mon Sep 17 00:00:00 2001 From: Mahesh Bandewar Date: Sat, 9 May 2015 00:01:57 -0700 Subject: bonding: Implement user key part of port_key in an AD system. The port key has three components - user-key, speed-part, and duplex-part. The LSBit is for the duplex-part, next 5 bits are for the speed while the remaining 10 bits are the user defined key bits. Get these 10 bits from the user-space (through the SysFs interface) and use it to form the admin port-key. Allowed range for the user-key is 0 - 1023 (10 bits). If it is not provided then use zero for the user-key-bits (default). It can set using following example code - # modprobe bonding mode=4 # usr_port_key=$(( RANDOM & 0x3FF )) # echo $usr_port_key > /sys/class/net/bond0/bonding/ad_user_port_key # echo +eth1 > /sys/class/net/bond0/bonding/slaves ... # ip link set bond0 up Signed-off-by: Mahesh Bandewar Reviewed-by: Nikolay Aleksandrov [jt: * fixed up style issues reported by checkpatch * fixed up context from change in ad_actor_sys_prio patch] Signed-off-by: Jonathan Toppins Signed-off-by: David S. Miller --- Documentation/networking/bonding.txt | 63 ++++++++++++++++++++++++++++++++++++ drivers/net/bonding/bond_3ad.c | 14 ++++---- drivers/net/bonding/bond_main.c | 10 ++++++ drivers/net/bonding/bond_options.c | 26 +++++++++++++++ drivers/net/bonding/bond_sysfs.c | 15 +++++++++ include/net/bond_options.h | 1 + include/net/bonding.h | 1 + 7 files changed, 123 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt index 2c197b68baf0..334b49ef02d1 100644 --- a/Documentation/networking/bonding.txt +++ b/Documentation/networking/bonding.txt @@ -51,6 +51,7 @@ Table of Contents 3.4 Configuring Bonding Manually via Sysfs 3.5 Configuration with Interfaces Support 3.6 Overriding Configuration for Special Cases +3.7 Configuring LACP for 802.3ad mode in a more secure way 4. Querying Bonding Configuration 4.1 Bonding Configuration @@ -241,6 +242,21 @@ ad_select This option was added in bonding version 3.4.0. +ad_user_port_key + + In an AD system, the port-key has three parts as shown below - + + Bits Use + 00 Duplex + 01-05 Speed + 06-15 User-defined + + This defines the upper 10 bits of the port key. The values can be + from 0 - 1023. If not given, the system defaults to 0. + + This parameter has effect only in 802.3ad mode and is available through + SysFs interface. + all_slaves_active Specifies that duplicate frames (received on inactive ports) should be @@ -1643,6 +1659,53 @@ output port selection. This feature first appeared in bonding driver version 3.7.0 and support for output slave selection was limited to round-robin and active-backup modes. +3.7 Configuring LACP for 802.3ad mode in a more secure way +---------------------------------------------------------- + +When using 802.3ad bonding mode, the Actor (host) and Partner (switch) +exchange LACPDUs. These LACPDUs cannot be sniffed, because they are +destined to link local mac addresses (which switches/bridges are not +supposed to forward). However, most of the values are easily predictable +or are simply the machine's MAC address (which is trivially known to all +other hosts in the same L2). This implies that other machines in the L2 +domain can spoof LACPDU packets from other hosts to the switch and potentially +cause mayhem by joining (from the point of view of the switch) another +machine's aggregate, thus receiving a portion of that hosts incoming +traffic and / or spoofing traffic from that machine themselves (potentially +even successfully terminating some portion of flows). Though this is not +a likely scenario, one could avoid this possibility by simply configuring +few bonding parameters: + + (a) ad_actor_system : You can set a random mac-address that can be used for + these LACPDU exchanges. The value can not be either NULL or Multicast. + Also it's preferable to set the local-admin bit. Following shell code + generates a random mac-address as described above. + + # sys_mac_addr=$(printf '%02x:%02x:%02x:%02x:%02x:%02x' \ + $(( (RANDOM & 0xFE) | 0x02 )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF )) \ + $(( RANDOM & 0xFF ))) + # echo $sys_mac_addr > /sys/class/net/bond0/bonding/ad_actor_system + + (b) ad_actor_sys_prio : Randomize the system priority. The default value + is 65535, but system can take the value from 1 - 65535. Following shell + code generates random priority and sets it. + + # sys_prio=$(( 1 + RANDOM + RANDOM )) + # echo $sys_prio > /sys/class/net/bond0/bonding/ad_actor_sys_prio + + (c) ad_user_port_key : Use the user portion of the port-key. The default + keeps this empty. These are the upper 10 bits of the port-key and value + ranges from 0 - 1023. Following shell code generates these 10 bits and + sets it. + + # usr_port_key=$(( RANDOM & 0x3FF )) + # echo $usr_port_key > /sys/class/net/bond0/bonding/ad_user_port_key + + 4 Querying Bonding Configuration ================================= diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c index 012f7bc22d91..7fde4d5c2b28 100644 --- a/drivers/net/bonding/bond_3ad.c +++ b/drivers/net/bonding/bond_3ad.c @@ -75,10 +75,10 @@ /* Port Key definitions * key is determined according to the link speed, duplex and * user key (which is yet not supported) - * -------------------------------------------------------------- - * Port key : | User key | Speed | Duplex | - * -------------------------------------------------------------- - * 16 6 1 0 + * -------------------------------------------------------------- + * Port key | User key (10 bits) | Speed (5 bits) | Duplex| + * -------------------------------------------------------------- + * |15 6|5 1|0 */ #define AD_DUPLEX_KEY_MASKS 0x1 #define AD_SPEED_KEY_MASKS 0x3E @@ -1951,10 +1951,10 @@ void bond_3ad_bind_slave(struct slave *slave) port->slave = slave; port->actor_port_number = SLAVE_AD_INFO(slave)->id; - /* key is determined according to the link speed, duplex and user key(which - * is yet not supported) + /* key is determined according to the link speed, duplex and + * user key */ - port->actor_admin_port_key = 0; + port->actor_admin_port_key = bond->params.ad_user_port_key << 6; port->actor_admin_port_key |= __get_duplex(port); port->actor_admin_port_key |= (__get_link_speed(port) << 1); port->actor_oper_port_key = port->actor_admin_port_key; diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index a4e2f27ef683..2ee13be7551b 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -4141,6 +4141,7 @@ static int bond_check_params(struct bond_params *params) const struct bond_opt_value *valptr; int arp_all_targets_value; u16 ad_actor_sys_prio = 0; + u16 ad_user_port_key = 0; /* Convert string parameters. */ if (mode) { @@ -4445,6 +4446,14 @@ static int bond_check_params(struct bond_params *params) } ad_actor_sys_prio = valptr->value; + valptr = bond_opt_parse(bond_opt_get(BOND_OPT_AD_USER_PORT_KEY), + &newval); + if (!valptr) { + pr_err("Error: No ad_user_port_key default value"); + return -EINVAL; + } + ad_user_port_key = valptr->value; + if (lp_interval == 0) { pr_warn("Warning: ip_interval must be between 1 and %d, so it was reset to %d\n", INT_MAX, BOND_ALB_DEFAULT_LP_INTERVAL); @@ -4475,6 +4484,7 @@ static int bond_check_params(struct bond_params *params) params->tlb_dynamic_lb = 1; /* Default value */ params->ad_actor_sys_prio = ad_actor_sys_prio; eth_zero_addr(params->ad_actor_system); + params->ad_user_port_key = ad_user_port_key; if (packets_per_slave > 0) { params->reciprocal_packets_per_slave = reciprocal_value(packets_per_slave); diff --git a/drivers/net/bonding/bond_options.c b/drivers/net/bonding/bond_options.c index cdcef217ac84..c85da05721e6 100644 --- a/drivers/net/bonding/bond_options.c +++ b/drivers/net/bonding/bond_options.c @@ -74,6 +74,8 @@ static int bond_option_ad_actor_sys_prio_set(struct bonding *bond, const struct bond_opt_value *newval); static int bond_option_ad_actor_system_set(struct bonding *bond, const struct bond_opt_value *newval); +static int bond_option_ad_user_port_key_set(struct bonding *bond, + const struct bond_opt_value *newval); static const struct bond_opt_value bond_mode_tbl[] = { @@ -196,6 +198,12 @@ static const struct bond_opt_value bond_ad_actor_sys_prio_tbl[] = { { NULL, -1, 0}, }; +static const struct bond_opt_value bond_ad_user_port_key_tbl[] = { + { "minval", 0, BOND_VALFLAG_MIN | BOND_VALFLAG_DEFAULT}, + { "maxval", 1023, BOND_VALFLAG_MAX}, + { NULL, -1, 0}, +}; + static const struct bond_option bond_opts[BOND_OPT_LAST] = { [BOND_OPT_MODE] = { .id = BOND_OPT_MODE, @@ -405,6 +413,14 @@ static const struct bond_option bond_opts[BOND_OPT_LAST] = { .flags = BOND_OPTFLAG_RAWVAL | BOND_OPTFLAG_IFDOWN, .set = bond_option_ad_actor_system_set, }, + [BOND_OPT_AD_USER_PORT_KEY] = { + .id = BOND_OPT_AD_USER_PORT_KEY, + .name = "ad_user_port_key", + .unsuppmodes = BOND_MODE_ALL_EX(BIT(BOND_MODE_8023AD)), + .flags = BOND_OPTFLAG_IFDOWN, + .values = bond_ad_user_port_key_tbl, + .set = bond_option_ad_user_port_key_set, + } }; /* Searches for an option by name */ @@ -1402,3 +1418,13 @@ static int bond_option_ad_actor_system_set(struct bonding *bond, ether_addr_copy(bond->params.ad_actor_system, macaddr); return 0; } + +static int bond_option_ad_user_port_key_set(struct bonding *bond, + const struct bond_opt_value *newval) +{ + netdev_info(bond->dev, "Setting ad_user_port_key to (%llu)\n", + newval->value); + + bond->params.ad_user_port_key = newval->value; + return 0; +} diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index 09fefa50d055..143a2abd1c1c 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c @@ -721,6 +721,20 @@ static ssize_t bonding_show_ad_actor_system(struct device *d, static DEVICE_ATTR(ad_actor_system, S_IRUGO | S_IWUSR, bonding_show_ad_actor_system, bonding_sysfs_store_option); +static ssize_t bonding_show_ad_user_port_key(struct device *d, + struct device_attribute *attr, + char *buf) +{ + struct bonding *bond = to_bond(d); + + if (BOND_MODE(bond) == BOND_MODE_8023AD) + return sprintf(buf, "%hu\n", bond->params.ad_user_port_key); + + return 0; +} +static DEVICE_ATTR(ad_user_port_key, S_IRUGO | S_IWUSR, + bonding_show_ad_user_port_key, bonding_sysfs_store_option); + static struct attribute *per_bond_attrs[] = { &dev_attr_slaves.attr, &dev_attr_mode.attr, @@ -756,6 +770,7 @@ static struct attribute *per_bond_attrs[] = { &dev_attr_tlb_dynamic_lb.attr, &dev_attr_ad_actor_sys_prio.attr, &dev_attr_ad_actor_system.attr, + &dev_attr_ad_user_port_key.attr, NULL, }; diff --git a/include/net/bond_options.h b/include/net/bond_options.h index eeeefa1d3cd8..c28aca25320e 100644 --- a/include/net/bond_options.h +++ b/include/net/bond_options.h @@ -65,6 +65,7 @@ enum { BOND_OPT_TLB_DYNAMIC_LB, BOND_OPT_AD_ACTOR_SYS_PRIO, BOND_OPT_AD_ACTOR_SYSTEM, + BOND_OPT_AD_USER_PORT_KEY, BOND_OPT_LAST }; diff --git a/include/net/bonding.h b/include/net/bonding.h index 650f38693956..20defc0353d1 100644 --- a/include/net/bonding.h +++ b/include/net/bonding.h @@ -137,6 +137,7 @@ struct bond_params { int tlb_dynamic_lb; struct reciprocal_value reciprocal_packets_per_slave; u16 ad_actor_sys_prio; + u16 ad_user_port_key; u8 ad_actor_system[ETH_ALEN]; }; -- cgit v1.2.3 From 6be109b31ccdb9c98e7be12687171f6602527a5d Mon Sep 17 00:00:00 2001 From: Arun Ramamurthy Date: Wed, 22 Apr 2015 16:04:11 -0700 Subject: phy: core: Add devm_of_phy_get_by_index to phy-core Some generic drivers, such as ehci, may use multiple phys and for such drivers referencing phy(s) by name(s) does not make sense. Instead of inventing new naming schemes and using custom code to iterate through them, such drivers are better of using nameless phy bindings and using this newly introduced API to iterate through them. Signed-off-by: Arun Ramamurthy Reviewed-by: Ray Jui Reviewed-by: Scott Branden [kishon@ti.com: fix compilation errors] Signed-off-by: Kishon Vijay Abraham I --- Documentation/phy.txt | 7 ++++++- drivers/phy/phy-core.c | 32 ++++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 9 +++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/phy.txt b/Documentation/phy.txt index 371361c69a4b..b388c5af9e72 100644 --- a/Documentation/phy.txt +++ b/Documentation/phy.txt @@ -76,6 +76,8 @@ struct phy *phy_get(struct device *dev, const char *string); struct phy *phy_optional_get(struct device *dev, const char *string); struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); +struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, + int index); phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY. In the case of dt boot, the string arguments @@ -86,7 +88,10 @@ successful PHY get. On driver detach, release function is invoked on the the devres data and devres data is freed. phy_optional_get and devm_phy_optional_get should be used when the phy is optional. These two functions will never return -ENODEV, but instead returns NULL when -the phy cannot be found. +the phy cannot be found.Some generic drivers, such as ehci, may use multiple +phys and for such drivers referencing phy(s) by name(s) does not make sense. In +this case, devm_of_phy_get_by_index can be used to get a phy reference based on +the index. It should be noted that NULL is a valid phy reference. All phy consumer calls on the NULL phy become NOPs. That is the release calls, diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 3791838f4bd4..964a84d5a580 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -622,6 +622,38 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, } EXPORT_SYMBOL_GPL(devm_of_phy_get); +/** + * devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index. + * @dev: device that requests this phy + * @np: node containing the phy + * @index: index of the phy + * + * Gets the phy using _of_phy_get(), and associates a device with it using + * devres. On driver detach, release function is invoked on the devres data, + * then, devres data is freed. + * + */ +struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, + int index) +{ + struct phy **ptr, *phy; + + ptr = devres_alloc(devm_phy_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + phy = _of_phy_get(np, index); + if (!IS_ERR(phy)) { + *ptr = phy; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return phy; +} +EXPORT_SYMBOL_GPL(devm_of_phy_get_by_index); + /** * phy_create() - create a new phy * @dev: device that is creating the new phy diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index a0197fa1b116..8cf05e341cff 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -133,6 +133,8 @@ struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, const char *con_id); +struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, + int index); void phy_put(struct phy *phy); void devm_phy_put(struct device *dev, struct phy *phy); struct phy *of_phy_get(struct device_node *np, const char *con_id); @@ -261,6 +263,13 @@ static inline struct phy *devm_of_phy_get(struct device *dev, return ERR_PTR(-ENOSYS); } +static inline struct phy *devm_of_phy_get_by_index(struct device *dev, + struct device_node *np, + int index) +{ + return ERR_PTR(-ENOSYS); +} + static inline void phy_put(struct phy *phy) { } -- cgit v1.2.3 From ea6055c46eda1e19e02209814955e13f334bbe1b Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 11 May 2015 12:20:18 -0300 Subject: spi: pl022: Specify 'num-cs' property as required in devicetree binding Since commit 39a6ac11df65 ("spi/pl022: Devicetree support w/o platform data") the 'num-cs' parameter cannot be passed through platform data when probing with devicetree. Instead, it's a required devicetree property. Fix the binding documentation so the property is properly specified. Fixes: 39a6ac11df65 ("spi/pl022: Devicetree support w/o platform data") Signed-off-by: Ezequiel Garcia Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi_pl022.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt index 22ed6797216d..4d1673ca8cf8 100644 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -4,9 +4,9 @@ Required properties: - compatible : "arm,pl022", "arm,primecell" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt +- num-cs : total number of chipselects Optional properties: -- num-cs : total number of chipselects - cs-gpios : should specify GPIOs used for chipselects. The gpios will be referred to as reg = in the SPI child nodes. If unspecified, a single SPI device without a chip select can be used. -- cgit v1.2.3 From fe88e379e89baf9cb0486caececc744fccbe9cb6 Mon Sep 17 00:00:00 2001 From: Azael Avalos Date: Thu, 26 Feb 2015 10:59:33 -0700 Subject: Documentation/ABI: Add file describing the sysfs entries for toshiba_haps This patch adds a new file describing the sysfs entries for the toshiba_haps driver. Signed-off-by: Azael Avalos Signed-off-by: Darren Hart --- Documentation/ABI/testing/sysfs-driver-toshiba_haps | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-toshiba_haps (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-driver-toshiba_haps b/Documentation/ABI/testing/sysfs-driver-toshiba_haps new file mode 100644 index 000000000000..a662370b4dbf --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-toshiba_haps @@ -0,0 +1,20 @@ +What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS620A:00/protection_level +Date: August 16, 2014 +KernelVersion: 3.17 +Contact: Azael Avalos +Description: This file controls the built-in accelerometer protection level, + valid values are: + * 0 -> Disabled + * 1 -> Low + * 2 -> Medium + * 3 -> High + The default potection value is set to 2 (Medium). +Users: KToshiba + +What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS620A:00/reset_protection +Date: August 16, 2014 +KernelVersion: 3.17 +Contact: Azael Avalos +Description: This file turns off the built-in accelerometer for a few + seconds and then restore normal operation. Accepting 1 as the + only parameter. -- cgit v1.2.3 From 9d0be7f4810257a9b0fc78fff641f14409f14ab3 Mon Sep 17 00:00:00 2001 From: Eduardo Valentin Date: Mon, 11 May 2015 19:34:23 -0700 Subject: thermal: support slope and offset coefficients It is common to have a linear extrapolation from the current sensor readings and the actual temperature value. This is specially the case when the sensor is in use to extrapolate hotspots. This patch adds slope and offset constants for single sensor linear extrapolation equation. Because the same sensor can be use in different locations, from board to board, these constants are added as part of thermal_zone_params. The constants are available through sysfs. It is up to the device driver to determine the usage of these values. Signed-off-by: Eduardo Valentin --- Documentation/thermal/sysfs-api.txt | 16 ++++++++++++++++ drivers/thermal/thermal_core.c | 4 ++++ include/linux/thermal.h | 11 +++++++++++ 3 files changed, 31 insertions(+) (limited to 'Documentation') diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt index 7d44d7f1a71b..c1f6864a8c5d 100644 --- a/Documentation/thermal/sysfs-api.txt +++ b/Documentation/thermal/sysfs-api.txt @@ -190,6 +190,8 @@ Thermal zone device sys I/F, created once it's registered: |---k_i: PID's integral term in the power allocator gov |---k_d: PID's derivative term in the power allocator |---integral_cutoff: Offset above which errors are accumulated + |---slope: Slope constant applied as linear extrapolation + |---offset: Offset constant applied as linear extrapolation Thermal cooling device sys I/F, created once it's registered: /sys/class/thermal/cooling_device[0-*]: @@ -359,6 +361,20 @@ integral_cutoff Documentation/thermal/power_allocator.txt RW, Optional +slope + The slope constant used in a linear extrapolation model + to determine a hotspot temperature based off the sensor's + raw readings. It is up to the device driver to determine + the usage of these values. + RW, Optional + +offset + The offset constant used in a linear extrapolation model + to determine a hotspot temperature based off the sensor's + raw readings. It is up to the device driver to determine + the usage of these values. + RW, Optional + ***************************** * Cooling device attributes * ***************************** diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index 962de1847cc0..04659bfb888b 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -944,6 +944,8 @@ create_s32_tzp_attr(k_pu); create_s32_tzp_attr(k_i); create_s32_tzp_attr(k_d); create_s32_tzp_attr(integral_cutoff); +create_s32_tzp_attr(slope); +create_s32_tzp_attr(offset); #undef create_s32_tzp_attr static struct device_attribute *dev_tzp_attrs[] = { @@ -953,6 +955,8 @@ static struct device_attribute *dev_tzp_attrs[] = { &dev_attr_k_i, &dev_attr_k_d, &dev_attr_integral_cutoff, + &dev_attr_slope, + &dev_attr_offset, }; static int create_tzp_attrs(struct device *dev) diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 6bbe11c97cea..037e9df2f610 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -302,6 +302,17 @@ struct thermal_zone_params { /* threshold below which the error is no longer accumulated */ s32 integral_cutoff; + + /* + * @slope: slope of a linear temperature adjustment curve. + * Used by thermal zone drivers. + */ + int slope; + /* + * @offset: offset of a linear temperature adjustment curve. + * Used by thermal zone drivers (default 0). + */ + int offset; }; struct thermal_genl_event { -- cgit v1.2.3 From 8cee396bfa77ce3a2e5fe48f597206c1cd547f9c Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 4 May 2015 07:51:04 -0300 Subject: [media] DocBook media: document codec draining flow Document the interaction between VIDIOC_DECODER_CMD V4L2_DEC_CMD_STOP and VIDIOC_ENCODER_CMD V4L2_ENC_CMD_STOP to start the draining, the V4L2_EVENT_EOS event signalling all capture buffers are finished and ready to be dequeud, the new V4L2_BUF_FLAG_LAST buffer flag indicating the last buffer being dequeued from the capture queue, and the poll and VIDIOC_DQBUF ioctl return values once the queue is drained. Signed-off-by: Philipp Zabel Acked-by: Hans Verkuil Signed-off-by: Kamil Debski Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 12 ++++++++++++ Documentation/DocBook/media/v4l/vidioc-decoder-cmd.xml | 12 +++++++++++- Documentation/DocBook/media/v4l/vidioc-encoder-cmd.xml | 10 +++++++++- Documentation/DocBook/media/v4l/vidioc-qbuf.xml | 8 ++++++++ 4 files changed, 40 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index 1c17f802b471..cff2ffd3c8a6 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -1127,6 +1127,18 @@ passed on to a DMA-capable hardware unit for further processing or output. Typically applications shall use this flag for output buffers if the data in this buffer has not been created by the CPU but by some DMA-capable unit, in which case caches have not been used. + + + V4L2_BUF_FLAG_LAST + 0x00100000 + Last buffer produced by the hardware. mem2mem codec drivers +set this flag on the capture queue for the last buffer when the +VIDIOC_QUERYBUF or +VIDIOC_DQBUF ioctl is called. Due to hardware +limitations, the last buffer may be empty. In this case the driver will set the +bytesused field to 0, regardless of the format. Any +Any subsequent call to the VIDIOC_DQBUF ioctl +will not block anymore, but return an &EPIPE;. V4L2_BUF_FLAG_TIMESTAMP_MASK diff --git a/Documentation/DocBook/media/v4l/vidioc-decoder-cmd.xml b/Documentation/DocBook/media/v4l/vidioc-decoder-cmd.xml index 9215627b04c7..73eb5cfe698a 100644 --- a/Documentation/DocBook/media/v4l/vidioc-decoder-cmd.xml +++ b/Documentation/DocBook/media/v4l/vidioc-decoder-cmd.xml @@ -197,7 +197,17 @@ be muted when playing back at a non-standard speed. this command does nothing. This command has two flags: if V4L2_DEC_CMD_STOP_TO_BLACK is set, then the decoder will set the picture to black after it stopped decoding. Otherwise the last image will -repeat. If V4L2_DEC_CMD_STOP_IMMEDIATELY is set, then the decoder +repeat. mem2mem decoders will stop producing new frames altogether. They will send +a V4L2_EVENT_EOS event when the last frame has been decoded +and all frames are ready to be dequeued and will set the +V4L2_BUF_FLAG_LAST buffer flag on the last buffer of the +capture queue to indicate there will be no new buffers produced to dequeue. This +buffer may be empty, indicated by the driver setting the +bytesused field to 0. Once the +V4L2_BUF_FLAG_LAST flag was set, the +VIDIOC_DQBUF ioctl will not block anymore, +but return an &EPIPE;. +If V4L2_DEC_CMD_STOP_IMMEDIATELY is set, then the decoder stops immediately (ignoring the pts value), otherwise it will keep decoding until timestamp >= pts or until the last of the pending data from its internal buffers was decoded. diff --git a/Documentation/DocBook/media/v4l/vidioc-encoder-cmd.xml b/Documentation/DocBook/media/v4l/vidioc-encoder-cmd.xml index 0619ca5d2d36..fc1d4625a78c 100644 --- a/Documentation/DocBook/media/v4l/vidioc-encoder-cmd.xml +++ b/Documentation/DocBook/media/v4l/vidioc-encoder-cmd.xml @@ -129,7 +129,15 @@ this command. encoding will continue until the end of the current Group Of Pictures, otherwise encoding will stop immediately. When the encoder is already stopped, this command does -nothing. +nothing. mem2mem encoders will send a V4L2_EVENT_EOS event +when the last frame has been decoded and all frames are ready to be dequeued and +will set the V4L2_BUF_FLAG_LAST buffer flag on the last +buffer of the capture queue to indicate there will be no new buffers produced to +dequeue. This buffer may be empty, indicated by the driver setting the +bytesused field to 0. Once the +V4L2_BUF_FLAG_LAST flag was set, the +VIDIOC_DQBUF ioctl will not block anymore, +but return an &EPIPE;. V4L2_ENC_CMD_PAUSE diff --git a/Documentation/DocBook/media/v4l/vidioc-qbuf.xml b/Documentation/DocBook/media/v4l/vidioc-qbuf.xml index 3504a7f2f382..6cfc53b83a20 100644 --- a/Documentation/DocBook/media/v4l/vidioc-qbuf.xml +++ b/Documentation/DocBook/media/v4l/vidioc-qbuf.xml @@ -186,6 +186,14 @@ In that case the application should be able to safely reuse the buffer and continue streaming. + EPIPE + + VIDIOC_DQBUF returns this on an empty +capture queue for mem2mem codecs if a buffer with the +V4L2_BUF_FLAG_LAST was already dequeued and no new buffers +are expected to become available. + + -- cgit v1.2.3 From d68921f9bd148359e6d01c84aaa2e32bfbd82970 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Mon, 11 May 2015 17:27:09 -0400 Subject: x86/smp/boot: Add cmdline "cpu_init_udelay=N" to specify cpu_up() delay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No change to default behavior. Replace the hard-coded mdelay(10) in cpu_up() with a variable udelay, that is set to a defined default -- rather than a magic number. Add a boot-time override, "cpu_init_udelay=N" Signed-off-by: Len Brown Cc: Alan Cox Cc: Arjan van de Ven Cc: Borislav Petkov Cc: H. Peter Anvin Cc: Jan H. Schönherr Cc: Linus Torvalds Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/2fe8e6c798e8def271122f62df9bbf58dc283e2a.1431379433.git.len.brown@intel.com Signed-off-by: Ingo Molnar --- Documentation/kernel-parameters.txt | 6 ++++++ arch/x86/kernel/smpboot.c | 23 ++++++++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..a320a41e7412 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -746,6 +746,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. cpuidle.off=1 [CPU_IDLE] disable the cpuidle sub-system + cpu_init_udelay=N + [X86] Delay for N microsec between assert and de-assert + of APIC INIT to start processors. This delay occurs + on every CPU online, such as boot, and resume from suspend. + Default: 10000 + cpcihp_generic= [HW,PCI] Generic port I/O CompactPCI driver Format: ,,,[,] diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 51203f60587f..0629a8e513af 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -513,6 +513,27 @@ void __inquire_remote_apic(int apicid) } } +/* + * The Multiprocessor Specification 1.4 (1997) example code suggests + * that there should be a 10ms delay between the BSP asserting INIT + * and de-asserting INIT, when starting a remote processor. + * But that slows boot and resume on modern processors, which include + * many cores and don't require that delay. + * + * Cmdline "init_cpu_udelay=" is available to over-ride this delay. + */ +#define UDELAY_10MS_DEFAULT 10000 + +static unsigned int init_udelay = UDELAY_10MS_DEFAULT; + +static int __init cpu_init_udelay(char *str) +{ + get_option(&str, &init_udelay); + + return 0; +} +early_param("cpu_init_udelay", cpu_init_udelay); + /* * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this @@ -584,7 +605,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) pr_debug("Waiting for send to finish...\n"); send_status = safe_apic_wait_icr_idle(); - mdelay(10); + mdelay(init_udelay); pr_debug("Deasserting INIT\n"); -- cgit v1.2.3 From 166a85e44245d771bd7042f3ad72aa0e12bb53bd Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 4 May 2015 17:10:33 +0200 Subject: gpio: remove gpiod_sysfs_set_active_low Remove gpiod_sysfs_set_active_low (and gpio_sysfs_set_active_low) which allowed code to change the polarity of a gpio line even after it had been exported through sysfs. Drivers should not care, and generally does not know, about gpio-line polarity which is a hardware feature that needs to be described by firmware. It is currently possible to define gpio-line polarity in device-tree and acpi firmware or using platform data. Userspace can also change the polarity through sysfs. Note that drivers using the legacy gpio interface could still use GPIOF_ACTIVE_LOW to change the polarity before exporting the gpio. There are no in-kernel users of this interface. Cc: Jonathan Corbet Cc: Harry Wei Cc: Arnd Bergmann Cc: linux-doc@vger.kernel.org Cc: linux-kernel@zh-kernel.org Cc: linux-arch@vger.kernel.org Signed-off-by: Johan Hovold Reviewed-by: Alexandre Courbot Signed-off-by: Linus Walleij --- Documentation/gpio/gpio-legacy.txt | 9 ------- Documentation/gpio/sysfs.txt | 8 ------- Documentation/zh_CN/gpio.txt | 8 ------- drivers/gpio/gpiolib-sysfs.c | 48 ++------------------------------------ include/asm-generic/gpio.h | 5 ---- include/linux/gpio.h | 7 ------ include/linux/gpio/consumer.h | 6 ----- 7 files changed, 2 insertions(+), 89 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpio/gpio-legacy.txt b/Documentation/gpio/gpio-legacy.txt index 6f83fa965b4b..79ab5648d69b 100644 --- a/Documentation/gpio/gpio-legacy.txt +++ b/Documentation/gpio/gpio-legacy.txt @@ -751,9 +751,6 @@ requested using gpio_request(): int gpio_export_link(struct device *dev, const char *name, unsigned gpio) - /* change the polarity of a GPIO node in sysfs */ - int gpio_sysfs_set_active_low(unsigned gpio, int value); - After a kernel driver requests a GPIO, it may only be made available in the sysfs interface by gpio_export(). The driver can control whether the signal direction may change. This helps drivers prevent userspace code @@ -767,9 +764,3 @@ After the GPIO has been exported, gpio_export_link() allows creating symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can use this to provide the interface under their own device in sysfs with a descriptive name. - -Drivers can use gpio_sysfs_set_active_low() to hide GPIO line polarity -differences between boards from user space. This only affects the -sysfs interface. Polarity change can be done both before and after -gpio_export(), and previously enabled poll(2) support for either -rising or falling edge will be reconfigured to follow this setting. diff --git a/Documentation/gpio/sysfs.txt b/Documentation/gpio/sysfs.txt index c2c3a97f8ff7..535b6a8a7a7c 100644 --- a/Documentation/gpio/sysfs.txt +++ b/Documentation/gpio/sysfs.txt @@ -132,9 +132,6 @@ requested using gpio_request(): int gpiod_export_link(struct device *dev, const char *name, struct gpio_desc *desc); - /* change the polarity of a GPIO node in sysfs */ - int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value); - After a kernel driver requests a GPIO, it may only be made available in the sysfs interface by gpiod_export(). The driver can control whether the signal direction may change. This helps drivers prevent userspace code @@ -148,8 +145,3 @@ After the GPIO has been exported, gpiod_export_link() allows creating symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can use this to provide the interface under their own device in sysfs with a descriptive name. - -Drivers can use gpiod_sysfs_set_active_low() to hide GPIO line polarity -differences between boards from user space. Polarity change can be done both -before and after gpiod_export(), and previously enabled poll(2) support for -either rising or falling edge will be reconfigured to follow this setting. diff --git a/Documentation/zh_CN/gpio.txt b/Documentation/zh_CN/gpio.txt index d5b8f01833f4..bce972521065 100644 --- a/Documentation/zh_CN/gpio.txt +++ b/Documentation/zh_CN/gpio.txt @@ -638,9 +638,6 @@ GPIO 控制器的路径类似 /sys/class/gpio/gpiochip42/ (对于从#42 GPIO int gpio_export_link(struct device *dev, const char *name, unsigned gpio) - /* 改变 sysfs 中的一个 GPIO 节点的极性 */ - int gpio_sysfs_set_active_low(unsigned gpio, int value); - 在一个内核驱动申请一个 GPIO 之后，它可以通过 gpio_export()使其在 sysfs 接口中可见。该驱动可以控制信号方向是否可修改。这有助于防止用户空间代码无意间 破坏重要的系统状态。 @@ -651,8 +648,3 @@ GPIO 控制器的路径类似 /sys/class/gpio/gpiochip42/ (对于从#42 GPIO 在 GPIO 被导出之后，gpio_export_link()允许在 sysfs 文件系统的任何地方 创建一个到这个 GPIO sysfs 节点的符号链接。这样驱动就可以通过一个描述性的 名字，在 sysfs 中他们所拥有的设备下提供一个(到这个 GPIO sysfs 节点的)接口。 - -驱动可以使用 gpio_sysfs_set_active_low() 来在用户空间隐藏电路板之间 -GPIO 线的极性差异。这个仅对 sysfs 接口起作用。极性的改变可以在 gpio_export() -前后进行,且之前使能的轮询操作(poll(2))支持(上升或下降沿)将会被重新配置来遵循 -这个设置。 diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c index aeb73ef2955e..9dcd346a20fb 100644 --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c @@ -308,8 +308,8 @@ static int sysfs_set_active_low(struct gpio_desc *desc, struct device *dev, clear_bit(FLAG_ACTIVE_LOW, &desc->flags); /* reconfigure poll(2) support if enabled on one edge only */ - if (dev != NULL && (!!test_bit(FLAG_TRIG_RISE, &desc->flags) ^ - !!test_bit(FLAG_TRIG_FALL, &desc->flags))) { + if (!!test_bit(FLAG_TRIG_RISE, &desc->flags) ^ + !!test_bit(FLAG_TRIG_FALL, &desc->flags)) { unsigned long trigger_flags = desc->flags & GPIO_TRIGGER_MASK; gpio_setup_irq(desc, dev, 0); @@ -680,50 +680,6 @@ int gpiod_export_link(struct device *dev, const char *name, } EXPORT_SYMBOL_GPL(gpiod_export_link); -/** - * gpiod_sysfs_set_active_low - set the polarity of gpio sysfs value - * @gpio: gpio to change - * @value: non-zero to use active low, i.e. inverted values - * - * Set the polarity of /sys/class/gpio/gpioN/value sysfs attribute. - * The GPIO does not have to be exported yet. If poll(2) support has - * been enabled for either rising or falling edge, it will be - * reconfigured to follow the new polarity. - * - * Returns zero on success, else an error. - */ -int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value) -{ - struct device *dev = NULL; - int status = -EINVAL; - - if (!desc) { - pr_warn("%s: invalid GPIO\n", __func__); - return -EINVAL; - } - - mutex_lock(&sysfs_lock); - - if (test_bit(FLAG_EXPORT, &desc->flags)) { - dev = class_find_device(&gpio_class, NULL, desc, match_export); - if (dev == NULL) { - status = -ENODEV; - goto unlock; - } - } - - status = sysfs_set_active_low(desc, dev, value); - put_device(dev); -unlock: - mutex_unlock(&sysfs_lock); - - if (status) - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - - return status; -} -EXPORT_SYMBOL_GPL(gpiod_sysfs_set_active_low); - /** * gpiod_unexport - reverse effect of gpio_export() * @gpio: gpio to make unavailable diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 9bb0d11729c9..40ec1433f05d 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -128,11 +128,6 @@ static inline int gpio_export_link(struct device *dev, const char *name, return gpiod_export_link(dev, name, gpio_to_desc(gpio)); } -static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) -{ - return gpiod_sysfs_set_active_low(gpio_to_desc(gpio), value); -} - static inline void gpio_unexport(unsigned gpio) { gpiod_unexport(gpio_to_desc(gpio)); diff --git a/include/linux/gpio.h b/include/linux/gpio.h index ab81339a8590..d12b5d566e4b 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -196,13 +196,6 @@ static inline int gpio_export_link(struct device *dev, const char *name, return -EINVAL; } -static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) -{ - /* GPIO can never have been requested */ - WARN_ON(1); - return -EINVAL; -} - static inline void gpio_unexport(unsigned gpio) { /* GPIO can never have been exported */ diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h index 3a7c9ffd5ab9..09a7fb0062a6 100644 --- a/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h @@ -449,7 +449,6 @@ static inline int desc_to_gpio(const struct gpio_desc *desc) int gpiod_export(struct gpio_desc *desc, bool direction_may_change); int gpiod_export_link(struct device *dev, const char *name, struct gpio_desc *desc); -int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value); void gpiod_unexport(struct gpio_desc *desc); #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ @@ -466,11 +465,6 @@ static inline int gpiod_export_link(struct device *dev, const char *name, return -ENOSYS; } -static inline int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value) -{ - return -ENOSYS; -} - static inline void gpiod_unexport(struct gpio_desc *desc) { } -- cgit v1.2.3 From 68cbbc3a9d1fc231810b2490bca73b3b444ef542 Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Thu, 26 Mar 2015 16:42:09 +1100 Subject: drivers/vfio: Support EEH error injection The patch adds one more EEH sub-command (VFIO_EEH_PE_INJECT_ERR) to inject the specified EEH error, which is represented by (struct vfio_eeh_pe_err), to the indicated PE for testing purpose. Signed-off-by: Gavin Shan Reviewed-by: David Gibson Acked-by: Alex Williamson Signed-off-by: Michael Ellerman --- Documentation/vfio.txt | 12 ++++++++++++ drivers/vfio/vfio_spapr_eeh.c | 10 ++++++++++ include/uapi/linux/vfio.h | 14 +++++++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/vfio.txt b/Documentation/vfio.txt index 96978eced341..4c746a7e717a 100644 --- a/Documentation/vfio.txt +++ b/Documentation/vfio.txt @@ -385,6 +385,18 @@ The code flow from the example above should be slightly changed: .... + /* Inject EEH error, which is expected to be caused by 32-bits + * config load. + */ + pe_op.op = VFIO_EEH_PE_INJECT_ERR; + pe_op.err.type = EEH_ERR_TYPE_32; + pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR; + pe_op.err.addr = 0ul; + pe_op.err.mask = 0ul; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + .... + /* When 0xFF's returned from reading PCI config space or IO BARs * of the PCI device. Check the PE's state to see if that has been * frozen. diff --git a/drivers/vfio/vfio_spapr_eeh.c b/drivers/vfio/vfio_spapr_eeh.c index 5fa42db769ee..38edeb4729a9 100644 --- a/drivers/vfio/vfio_spapr_eeh.c +++ b/drivers/vfio/vfio_spapr_eeh.c @@ -85,6 +85,16 @@ long vfio_spapr_iommu_eeh_ioctl(struct iommu_group *group, case VFIO_EEH_PE_CONFIGURE: ret = eeh_pe_configure(pe); break; + case VFIO_EEH_PE_INJECT_ERR: + minsz = offsetofend(struct vfio_eeh_pe_op, err.mask); + if (op.argsz < minsz) + return -EINVAL; + if (copy_from_user(&op, (void __user *)arg, minsz)) + return -EFAULT; + + ret = eeh_pe_inject_err(pe, op.err.type, op.err.func, + op.err.addr, op.err.mask); + break; default: ret = -EINVAL; } diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index b57b750c222f..e4fa1995f613 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -470,12 +470,23 @@ struct vfio_iommu_spapr_tce_info { * - unfreeze IO/DMA for frozen PE; * - read PE state; * - reset PE; - * - configure PE. + * - configure PE; + * - inject EEH error. */ +struct vfio_eeh_pe_err { + __u32 type; + __u32 func; + __u64 addr; + __u64 mask; +}; + struct vfio_eeh_pe_op { __u32 argsz; __u32 flags; __u32 op; + union { + struct vfio_eeh_pe_err err; + }; }; #define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */ @@ -492,6 +503,7 @@ struct vfio_eeh_pe_op { #define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */ #define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */ #define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */ +#define VFIO_EEH_PE_INJECT_ERR 9 /* Inject EEH error */ #define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) -- cgit v1.2.3 From 5b7d414ad025654516c59efd16b4a7f0d8017c1b Mon Sep 17 00:00:00 2001 From: Gregory Fong Date: Wed, 6 May 2015 01:37:55 -0700 Subject: dt-bindings: add brcmstb-gpio GPIO binding Add binding for Broadcom STB "UPG GIO" GPIO controller. Signed-off-by: Gregory Fong Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/brcm,brcmstb-gpio.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt new file mode 100644 index 000000000000..435f1bcca341 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt @@ -0,0 +1,65 @@ +Broadcom STB "UPG GIO" GPIO controller + +The controller's registers are organized as sets of eight 32-bit +registers with each set controlling a bank of up to 32 pins. A single +interrupt is shared for all of the banks handled by the controller. + +Required properties: + +- compatible: + Must be "brcm,brcmstb-gpio" + +- reg: + Define the base and range of the I/O address space containing + the brcmstb GPIO controller registers + +- #gpio-cells: + Should be <2>. The first cell is the pin number (within the controller's + pin space), and the second is used for the following: + bit[0]: polarity (0 for active-high, 1 for active-low) + +- gpio-controller: + Specifies that the node is a GPIO controller. + +- brcm,gpio-bank-widths: + Number of GPIO lines for each bank. Number of elements must + correspond to number of banks suggested by the 'reg' property. + +Optional properties: + +- interrupts: + The interrupt shared by all GPIO lines for this controller. + +- interrupt-parent: + phandle of the parent interrupt controller + +- #interrupt-cells: + Should be <2>. The first cell is the GPIO number, the second should specify + flags. The following subset of flags is supported: + - bits[3:0] trigger type and level flags + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. + See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + +- interrupt-controller: + Marks the device node as an interrupt controller + +- interrupt-names: + The name of the IRQ resource used by this controller + +Example: + upg_gio: gpio@f040a700 { + #gpio-cells = <0x2>; + #interrupt-cells = <0x2>; + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + gpio-controller; + interrupt-controller; + reg = <0xf040a700 0x80>; + interrupt-parent = <0xf>; + interrupts = <0x6>; + interrupt-names = "upg_gio"; + brcm,gpio-bank-widths = <0x20 0x20 0x20 0x18>; + }; -- cgit v1.2.3 From 7e15a967a2d686bc959a268fd12c50e39d705416 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 12 May 2015 11:13:21 +0200 Subject: pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion. Signed-off-by: Ulrich Hecht Acked-by: Simon Horman Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index bfe72ec055e3..6bcf851b6779 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -16,7 +16,8 @@ Required Properties: - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller. + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. + - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin -- cgit v1.2.3 From c778b4726a13ed38f8d36c926b7b0d5144c562de Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Fri, 8 May 2015 21:02:34 +0200 Subject: ASoC: bt-sco: Add devicetree support for bt-sco codec Add devicetree support for bluetooth SCO link codec. Signed-off-by: Marek Belisko Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/bt-sco.txt | 13 +++++++++++++ Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + sound/soc/codecs/bt-sco.c | 9 +++++++++ 3 files changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/bt-sco.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/bt-sco.txt b/Documentation/devicetree/bindings/sound/bt-sco.txt new file mode 100644 index 000000000000..29b8e5d40203 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/bt-sco.txt @@ -0,0 +1,13 @@ +Bluetooth-SCO audio CODEC + +This device support generic Bluetooth SCO link. + +Required properties: + + - compatible : "delta,dfbmcs320" + +Example: + +codec: bt_sco { + compatible = "delta,dfbmcs320"; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..b6969e477bf3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -54,6 +54,7 @@ cosmic Cosmic Circuits crystalfontz Crystalfontz America, Inc. dallas Maxim Integrated Products (formerly Dallas Semiconductor) davicom DAVICOM Semiconductor, Inc. +delta Delta Electronics, Inc. denx Denx Software Engineering digi Digi International Inc. digilent Diglent, Inc. diff --git a/sound/soc/codecs/bt-sco.c b/sound/soc/codecs/bt-sco.c index 9d0b794d3005..b084ad113e96 100644 --- a/sound/soc/codecs/bt-sco.c +++ b/sound/soc/codecs/bt-sco.c @@ -74,9 +74,18 @@ static const struct platform_device_id bt_sco_driver_ids[] = { }; MODULE_DEVICE_TABLE(platform, bt_sco_driver_ids); +#if defined(CONFIG_OF) +static const struct of_device_id bt_sco_codec_of_match[] = { + { .compatible = "delta,dfbmcs320", }, + {}, +}; +MODULE_DEVICE_TABLE(of, bt_sco_codec_of_match); +#endif + static struct platform_driver bt_sco_driver = { .driver = { .name = "bt-sco", + .of_match_table = of_match_ptr(bt_sco_codec_of_match), }, .probe = bt_sco_probe, .remove = bt_sco_remove, -- cgit v1.2.3 From f6505fbabc426b9e293da5bb702ace2eb1ccf87d Mon Sep 17 00:00:00 2001 From: Feng Kan Date: Fri, 24 Apr 2015 15:17:50 -0700 Subject: i2c: add SLIMpro I2C device driver on APM X-Gene platform Add SLIMpro I2C device driver on APM X-Gene platform. This I2C device driver use the SLIMpro Mailbox driver to tunnel message to the SLIMpro coprocessor to do the work of accessing I2C components. Signed-off-by: Feng Kan Signed-off-by: Hieu Le Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-xgene-slimpro.txt | 15 + drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-xgene-slimpro.c | 469 +++++++++++++++++++++ 4 files changed, 494 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt create mode 100644 drivers/i2c/busses/i2c-xgene-slimpro.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt b/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt new file mode 100644 index 000000000000..f6b2c20cfbf6 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt @@ -0,0 +1,15 @@ +APM X-Gene SLIMpro Mailbox I2C Driver + +An I2C controller accessed over the "SLIMpro" mailbox. + +Required properties : + + - compatible : should be "apm,xgene-slimpro-i2c" + - mboxes : use the label reference for the mailbox as the first parameter. + The second parameter is the channel number. + +Example : + i2cslimpro { + compatible = "apm,xgene-slimpro-i2c"; + mboxes = <&mailbox 0>; + }; diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 5c9750ac486c..1d759c3767e7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1110,6 +1110,15 @@ config I2C_CROS_EC_TUNNEL connected there. This will work whatever the interface used to talk to the EC (SPI, I2C or LPC). +config I2C_XGENE_SLIMPRO + tristate "APM X-Gene SoC I2C SLIMpro devices support" + depends on ARCH_XGENE && MAILBOX + help + Enable I2C bus access using the APM X-Gene SoC SLIMpro + co-processor. The I2C device access the I2C bus via the X-Gene + to SLIMpro (On chip coprocessor) mailbox mechanism. + If unsure, say N. + config SCx200_ACB tristate "Geode ACCESS.bus support" depends on X86_32 && PCI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index cdf941da91c6..d8093022ee4c 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -110,6 +110,7 @@ obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o obj-$(CONFIG_I2C_OPAL) += i2c-opal.o obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o +obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o obj-$(CONFIG_SCx200_ACB) += scx200_acb.o ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG diff --git a/drivers/i2c/busses/i2c-xgene-slimpro.c b/drivers/i2c/busses/i2c-xgene-slimpro.c new file mode 100644 index 000000000000..0b33aa2e6730 --- /dev/null +++ b/drivers/i2c/busses/i2c-xgene-slimpro.c @@ -0,0 +1,469 @@ +/* + * X-Gene SLIMpro I2C Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Author: Feng Kan + * Author: Hieu Le + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * This driver provides support for X-Gene SLIMpro I2C device access + * using the APM X-Gene SLIMpro mailbox driver. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAILBOX_OP_TIMEOUT 1000 /* Operation time out in ms */ +#define MAILBOX_I2C_INDEX 0 +#define SLIMPRO_IIC_BUS 1 /* Use I2C bus 1 only */ + +#define SMBUS_CMD_LEN 1 +#define BYTE_DATA 1 +#define WORD_DATA 2 +#define BLOCK_DATA 3 + +#define SLIMPRO_IIC_I2C_PROTOCOL 0 +#define SLIMPRO_IIC_SMB_PROTOCOL 1 + +#define SLIMPRO_IIC_READ 0 +#define SLIMPRO_IIC_WRITE 1 + +#define IIC_SMB_WITHOUT_DATA_LEN 0 +#define IIC_SMB_WITH_DATA_LEN 1 + +#define SLIMPRO_DEBUG_MSG 0 +#define SLIMPRO_MSG_TYPE_SHIFT 28 +#define SLIMPRO_DBG_SUBTYPE_I2C1READ 4 +#define SLIMPRO_DBGMSG_TYPE_SHIFT 24 +#define SLIMPRO_DBGMSG_TYPE_MASK 0x0F000000U +#define SLIMPRO_IIC_DEV_SHIFT 23 +#define SLIMPRO_IIC_DEV_MASK 0x00800000U +#define SLIMPRO_IIC_DEVID_SHIFT 13 +#define SLIMPRO_IIC_DEVID_MASK 0x007FE000U +#define SLIMPRO_IIC_RW_SHIFT 12 +#define SLIMPRO_IIC_RW_MASK 0x00001000U +#define SLIMPRO_IIC_PROTO_SHIFT 11 +#define SLIMPRO_IIC_PROTO_MASK 0x00000800U +#define SLIMPRO_IIC_ADDRLEN_SHIFT 8 +#define SLIMPRO_IIC_ADDRLEN_MASK 0x00000700U +#define SLIMPRO_IIC_DATALEN_SHIFT 0 +#define SLIMPRO_IIC_DATALEN_MASK 0x000000FFU + +/* + * SLIMpro I2C message encode + * + * dev - Controller number (0-based) + * chip - I2C chip address + * op - SLIMPRO_IIC_READ or SLIMPRO_IIC_WRITE + * proto - SLIMPRO_IIC_SMB_PROTOCOL or SLIMPRO_IIC_I2C_PROTOCOL + * addrlen - Length of the address field + * datalen - Length of the data field + */ +#define SLIMPRO_IIC_ENCODE_MSG(dev, chip, op, proto, addrlen, datalen) \ + ((SLIMPRO_DEBUG_MSG << SLIMPRO_MSG_TYPE_SHIFT) | \ + ((SLIMPRO_DBG_SUBTYPE_I2C1READ << SLIMPRO_DBGMSG_TYPE_SHIFT) & \ + SLIMPRO_DBGMSG_TYPE_MASK) | \ + ((dev << SLIMPRO_IIC_DEV_SHIFT) & SLIMPRO_IIC_DEV_MASK) | \ + ((chip << SLIMPRO_IIC_DEVID_SHIFT) & SLIMPRO_IIC_DEVID_MASK) | \ + ((op << SLIMPRO_IIC_RW_SHIFT) & SLIMPRO_IIC_RW_MASK) | \ + ((proto << SLIMPRO_IIC_PROTO_SHIFT) & SLIMPRO_IIC_PROTO_MASK) | \ + ((addrlen << SLIMPRO_IIC_ADDRLEN_SHIFT) & SLIMPRO_IIC_ADDRLEN_MASK) | \ + ((datalen << SLIMPRO_IIC_DATALEN_SHIFT) & SLIMPRO_IIC_DATALEN_MASK)) + +/* + * Encode for upper address for block data + */ +#define SLIMPRO_IIC_ENCODE_FLAG_BUFADDR 0x80000000 +#define SLIMPRO_IIC_ENCODE_FLAG_WITH_DATA_LEN(a) ((u32) (((a) << 30) \ + & 0x40000000)) +#define SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(a) ((u32) (((a) >> 12) \ + & 0x3FF00000)) +#define SLIMPRO_IIC_ENCODE_ADDR(a) ((a) & 0x000FFFFF) + +struct slimpro_i2c_dev { + struct i2c_adapter adapter; + struct device *dev; + struct mbox_chan *mbox_chan; + struct mbox_client mbox_client; + struct completion rd_complete; + u8 dma_buffer[I2C_SMBUS_BLOCK_MAX]; + u32 *resp_msg; +}; + +#define to_slimpro_i2c_dev(cl) \ + container_of(cl, struct slimpro_i2c_dev, mbox_client) + +static void slimpro_i2c_rx_cb(struct mbox_client *cl, void *mssg) +{ + struct slimpro_i2c_dev *ctx = to_slimpro_i2c_dev(cl); + + /* + * Response message format: + * mssg[0] is the return code of the operation + * mssg[1] is the first data word + * mssg[2] is NOT used + */ + if (ctx->resp_msg) + *ctx->resp_msg = ((u32 *)mssg)[1]; + + if (ctx->mbox_client.tx_block) + complete(&ctx->rd_complete); +} + +static int start_i2c_msg_xfer(struct slimpro_i2c_dev *ctx) +{ + if (ctx->mbox_client.tx_block) { + if (!wait_for_completion_timeout(&ctx->rd_complete, + msecs_to_jiffies(MAILBOX_OP_TIMEOUT))) + return -ETIMEDOUT; + } + + /* Check of invalid data or no device */ + if (*ctx->resp_msg == 0xffffffff) + return -ENODEV; + + return 0; +} + +static int slimpro_i2c_rd(struct slimpro_i2c_dev *ctx, u32 chip, + u32 addr, u32 addrlen, u32 protocol, + u32 readlen, u32 *data) +{ + u32 msg[3]; + int rc; + + msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, + SLIMPRO_IIC_READ, protocol, addrlen, readlen); + msg[1] = SLIMPRO_IIC_ENCODE_ADDR(addr); + msg[2] = 0; + ctx->resp_msg = data; + rc = mbox_send_message(ctx->mbox_chan, &msg); + if (rc < 0) + goto err; + + rc = start_i2c_msg_xfer(ctx); +err: + ctx->resp_msg = NULL; + return rc; +} + +static int slimpro_i2c_wr(struct slimpro_i2c_dev *ctx, u32 chip, + u32 addr, u32 addrlen, u32 protocol, u32 writelen, + u32 data) +{ + u32 msg[3]; + int rc; + + msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, + SLIMPRO_IIC_WRITE, protocol, addrlen, writelen); + msg[1] = SLIMPRO_IIC_ENCODE_ADDR(addr); + msg[2] = data; + ctx->resp_msg = msg; + + rc = mbox_send_message(ctx->mbox_chan, &msg); + if (rc < 0) + goto err; + + rc = start_i2c_msg_xfer(ctx); +err: + ctx->resp_msg = NULL; + return rc; +} + +static int slimpro_i2c_blkrd(struct slimpro_i2c_dev *ctx, u32 chip, u32 addr, + u32 addrlen, u32 protocol, u32 readlen, + u32 with_data_len, void *data) +{ + dma_addr_t paddr; + u32 msg[3]; + int rc; + + paddr = dma_map_single(ctx->dev, ctx->dma_buffer, readlen, DMA_FROM_DEVICE); + rc = dma_mapping_error(ctx->dev, paddr); + if (rc) { + dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n", + ctx->dma_buffer); + goto err; + } + + msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, SLIMPRO_IIC_READ, + protocol, addrlen, readlen); + msg[1] = SLIMPRO_IIC_ENCODE_FLAG_BUFADDR | + SLIMPRO_IIC_ENCODE_FLAG_WITH_DATA_LEN(with_data_len) | + SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(paddr) | + SLIMPRO_IIC_ENCODE_ADDR(addr); + msg[2] = (u32)paddr; + ctx->resp_msg = msg; + + rc = mbox_send_message(ctx->mbox_chan, &msg); + if (rc < 0) + goto err_unmap; + + rc = start_i2c_msg_xfer(ctx); + + /* Copy to destination */ + memcpy(data, ctx->dma_buffer, readlen); + +err_unmap: + dma_unmap_single(ctx->dev, paddr, readlen, DMA_FROM_DEVICE); +err: + ctx->resp_msg = NULL; + return rc; +} + +static int slimpro_i2c_blkwr(struct slimpro_i2c_dev *ctx, u32 chip, + u32 addr, u32 addrlen, u32 protocol, u32 writelen, + void *data) +{ + dma_addr_t paddr; + u32 msg[3]; + int rc; + + memcpy(ctx->dma_buffer, data, writelen); + paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen, + DMA_TO_DEVICE); + rc = dma_mapping_error(ctx->dev, paddr); + if (rc) { + dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n", + ctx->dma_buffer); + goto err; + } + + msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, SLIMPRO_IIC_WRITE, + protocol, addrlen, writelen); + msg[1] = SLIMPRO_IIC_ENCODE_FLAG_BUFADDR | + SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(paddr) | + SLIMPRO_IIC_ENCODE_ADDR(addr); + msg[2] = (u32)paddr; + ctx->resp_msg = msg; + + if (ctx->mbox_client.tx_block) + reinit_completion(&ctx->rd_complete); + + rc = mbox_send_message(ctx->mbox_chan, &msg); + if (rc < 0) + goto err_unmap; + + rc = start_i2c_msg_xfer(ctx); + +err_unmap: + dma_unmap_single(ctx->dev, paddr, writelen, DMA_TO_DEVICE); +err: + ctx->resp_msg = NULL; + return rc; +} + +static int xgene_slimpro_i2c_xfer(struct i2c_adapter *adap, u16 addr, + unsigned short flags, char read_write, + u8 command, int size, + union i2c_smbus_data *data) +{ + struct slimpro_i2c_dev *ctx = i2c_get_adapdata(adap); + int ret = -EOPNOTSUPP; + u32 val; + + switch (size) { + case I2C_SMBUS_BYTE: + if (read_write == I2C_SMBUS_READ) { + ret = slimpro_i2c_rd(ctx, addr, 0, 0, + SLIMPRO_IIC_SMB_PROTOCOL, + BYTE_DATA, &val); + data->byte = val; + } else { + ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + 0, 0); + } + break; + case I2C_SMBUS_BYTE_DATA: + if (read_write == I2C_SMBUS_READ) { + ret = slimpro_i2c_rd(ctx, addr, command, SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + BYTE_DATA, &val); + data->byte = val; + } else { + val = data->byte; + ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + BYTE_DATA, val); + } + break; + case I2C_SMBUS_WORD_DATA: + if (read_write == I2C_SMBUS_READ) { + ret = slimpro_i2c_rd(ctx, addr, command, SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + WORD_DATA, &val); + data->word = val; + } else { + val = data->word; + ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + WORD_DATA, val); + } + break; + case I2C_SMBUS_BLOCK_DATA: + if (read_write == I2C_SMBUS_READ) { + ret = slimpro_i2c_blkrd(ctx, addr, command, + SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + I2C_SMBUS_BLOCK_MAX + 1, + IIC_SMB_WITH_DATA_LEN, + &data->block[0]); + + } else { + ret = slimpro_i2c_blkwr(ctx, addr, command, + SMBUS_CMD_LEN, + SLIMPRO_IIC_SMB_PROTOCOL, + data->block[0] + 1, + &data->block[0]); + } + break; + case I2C_SMBUS_I2C_BLOCK_DATA: + if (read_write == I2C_SMBUS_READ) { + ret = slimpro_i2c_blkrd(ctx, addr, + command, + SMBUS_CMD_LEN, + SLIMPRO_IIC_I2C_PROTOCOL, + I2C_SMBUS_BLOCK_MAX, + IIC_SMB_WITHOUT_DATA_LEN, + &data->block[1]); + } else { + ret = slimpro_i2c_blkwr(ctx, addr, command, + SMBUS_CMD_LEN, + SLIMPRO_IIC_I2C_PROTOCOL, + data->block[0], + &data->block[1]); + } + break; + default: + break; + } + return ret; +} + +/* +* Return list of supported functionality. +*/ +static u32 xgene_slimpro_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_BLOCK_DATA | + I2C_FUNC_SMBUS_I2C_BLOCK; +} + +static struct i2c_algorithm xgene_slimpro_i2c_algorithm = { + .smbus_xfer = xgene_slimpro_i2c_xfer, + .functionality = xgene_slimpro_i2c_func, +}; + +static int __init xgene_slimpro_i2c_probe(struct platform_device *pdev) +{ + struct slimpro_i2c_dev *ctx; + struct i2c_adapter *adapter; + struct mbox_client *cl; + int rc; + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->dev = &pdev->dev; + platform_set_drvdata(pdev, ctx); + cl = &ctx->mbox_client; + + /* Request mailbox channel */ + cl->dev = &pdev->dev; + cl->rx_callback = slimpro_i2c_rx_cb; + cl->tx_block = true; + init_completion(&ctx->rd_complete); + cl->tx_tout = MAILBOX_OP_TIMEOUT; + cl->knows_txdone = false; + ctx->mbox_chan = mbox_request_channel(cl, MAILBOX_I2C_INDEX); + if (IS_ERR(ctx->mbox_chan)) { + dev_err(&pdev->dev, "i2c mailbox channel request failed\n"); + return PTR_ERR(ctx->mbox_chan); + } + + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (rc) + dev_warn(&pdev->dev, "Unable to set dma mask\n"); + + /* Setup I2C adapter */ + adapter = &ctx->adapter; + snprintf(adapter->name, sizeof(adapter->name), "MAILBOX I2C"); + adapter->algo = &xgene_slimpro_i2c_algorithm; + adapter->class = I2C_CLASS_HWMON; + adapter->dev.parent = &pdev->dev; + i2c_set_adapdata(adapter, ctx); + rc = i2c_add_adapter(adapter); + if (rc) { + dev_err(&pdev->dev, "Adapter registeration failed\n"); + return rc; + } + + dev_info(&pdev->dev, "Mailbox I2C Adapter registered\n"); + return 0; +} + +static int xgene_slimpro_i2c_remove(struct platform_device *pdev) +{ + struct slimpro_i2c_dev *ctx = platform_get_drvdata(pdev); + + i2c_del_adapter(&ctx->adapter); + + mbox_free_channel(ctx->mbox_chan); + + return 0; +} + +static const struct of_device_id xgene_slimpro_i2c_dt_ids[] = { + {.compatible = "apm,xgene-slimpro-i2c" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xgene_slimpro_i2c_dt_ids); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id xgene_slimpro_i2c_acpi_ids[] = { + {"APMC0D40", 0}, + {} +}; +MODULE_DEVICE_TABLE(acpi, xgene_slimpro_i2c_acpi_ids); +#endif + +static struct platform_driver xgene_slimpro_i2c_driver = { + .probe = xgene_slimpro_i2c_probe, + .remove = xgene_slimpro_i2c_remove, + .driver = { + .name = "xgene-slimpro-i2c", + .of_match_table = of_match_ptr(xgene_slimpro_i2c_dt_ids), + .acpi_match_table = ACPI_PTR(xgene_slimpro_i2c_acpi_ids) + }, +}; + +module_platform_driver(xgene_slimpro_i2c_driver); + +MODULE_DESCRIPTION("APM X-Gene SLIMpro I2C driver"); +MODULE_AUTHOR("Feng Kan "); +MODULE_AUTHOR("Hieu Le "); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From f6a2fbb903d51b1e328d6e358048426ca97932ad Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 17 Apr 2015 01:14:15 +0100 Subject: PM / runtime: add note about re-calling in during device probe() The sh_eth driver has come up with an issue where the runtime_pm code suspends it during the probe() method due to the network device registration re-calling into the driver. Add a note about this into the documentation. Signed-off-by: Ben Dooks Signed-off-by: Ben Hutchings Signed-off-by: Rafael J. Wysocki --- Documentation/power/runtime_pm.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/power/runtime_pm.txt b/Documentation/power/runtime_pm.txt index 44fe1d28a163..e76dc0ad4d2b 100644 --- a/Documentation/power/runtime_pm.txt +++ b/Documentation/power/runtime_pm.txt @@ -556,6 +556,12 @@ helper functions described in Section 4. In that case, pm_runtime_resume() should be used. Of course, for this purpose the device's runtime PM has to be enabled earlier by calling pm_runtime_enable(). +Note, if the device may execute pm_runtime calls during the probe (such as +if it is registers with a subsystem that may call back in) then the +pm_runtime_get_sync() call paired with a pm_runtime_put() call will be +appropriate to ensure that the device is not put back to sleep during the +probe. This can happen with systems such as the network device layer. + It may be desirable to suspend the device once ->probe() has finished. Therefore the driver core uses the asyncronous pm_request_idle() to submit a request to execute the subsystem-level idle callback for the device at that -- cgit v1.2.3 From 4ceec22d6d89360ff7ebbf53dd3ab4e29e3d8a09 Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Sun, 10 May 2015 09:48:09 -0700 Subject: switchdev: bring documentation up-to-date Much need updated of switchdev documentation to cover what's been implmented to-date. There are some XXX comments in the text for unimplemented or broken items. I'd like to keep these in there (poor-man's TODO list) and update the document once each issue is resolved. Signed-off-by: Scott Feldman Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 414 ++++++++++++++++++++++++++++----- 1 file changed, 355 insertions(+), 59 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index f981a9295a39..b3e18c8fd040 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -1,59 +1,355 @@ -Switch (and switch-ish) device drivers HOWTO -=========================== - -Please note that the word "switch" is here used in very generic meaning. -This include devices supporting L2/L3 but also various flow offloading chips, -including switches embedded into SR-IOV NICs. - -Lets describe a topology a bit. Imagine the following example: - - +----------------------------+ +---------------+ - | SOME switch chip | | CPU | - +----------------------------+ +---------------+ - port1 port2 port3 port4 MNGMNT | PCI-E | - | | | | | +---------------+ - PHY PHY | | | | NIC0 NIC1 - | | | | | | - | | +- PCI-E -+ | | - | +------- MII -------+ | - +------------- MII ------------+ - -In this example, there are two independent lines between the switch silicon -and CPU. NIC0 and NIC1 drivers are not aware of a switch presence. They are -separate from the switch driver. SOME switch chip is by managed by a driver -via PCI-E device MNGMNT. Note that MNGMNT device, NIC0 and NIC1 may be -connected to some other type of bus. - -Now, for the previous example show the representation in kernel: - - +----------------------------+ +---------------+ - | SOME switch chip | | CPU | - +----------------------------+ +---------------+ - sw0p0 sw0p1 sw0p2 sw0p3 MNGMNT | PCI-E | - | | | | | +---------------+ - PHY PHY | | | | eth0 eth1 - | | | | | | - | | +- PCI-E -+ | | - | +------- MII -------+ | - +------------- MII ------------+ - -Lets call the example switch driver for SOME switch chip "SOMEswitch". This -driver takes care of PCI-E device MNGMNT. There is a netdevice instance sw0pX -created for each port of a switch. These netdevices are instances -of "SOMEswitch" driver. sw0pX netdevices serve as a "representation" -of the switch chip. eth0 and eth1 are instances of some other existing driver. - -The only difference of the switch-port netdevice from the ordinary netdevice -is that is implements couple more NDOs: - - ndo_switch_parent_id_get - This returns the same ID for two port netdevices - of the same physical switch chip. This is - mandatory to be implemented by all switch drivers - and serves the caller for recognition of a port - netdevice. - ndo_switch_parent_* - Functions that serve for a manipulation of the switch - chip itself (it can be though of as a "parent" of the - port, therefore the name). They are not port-specific. - Caller might use arbitrary port netdevice of the same - switch and it will make no difference. - ndo_switch_port_* - Functions that serve for a port-specific manipulation. +Ethernet switch device driver model (switchdev) +=============================================== +Copyright (c) 2014 Jiri Pirko +Copyright (c) 2014-2015 Scott Feldman + + +The Ethernet switch device driver model (switchdev) is an in-kernel driver +model for switch devices which offload the forwarding (data) plane from the +kernel. + +Figure 1 is a block diagram showing the components of the switchdev model for +an example setup using a data-center-class switch ASIC chip. Other setups +with SR-IOV or soft switches, such as OVS, are possible. + + +                             User-space tools                                  +                                                                               +       user space                   |                                          +      +-------------------------------------------------------------------+    +       kernel                       | Netlink                                  +                                    |                                          +                     +--------------+-------------------------------+          +                     |         Network stack                        |          +                     |           (Linux)                            |          +                     |                                              |          +                     +----------------------------------------------+          +                                                                               + sw1p2 sw1p4 sw1p6 +                      sw1p1  + sw1p3 +  sw1p5 +         eth1              +                        +    |    +    |    +    |            +                +                        |    |    |    |    |    |            |                +                     +--+----+----+----+-+--+----+---+  +-----+-----+          +                     |         Switch driver         |  |    mgmt   |          +                     |        (this document)        |  |   driver  |          +                     |                               |  |           |          +                     +--------------+----------------+  +-----------+          +                                    |                                          +       kernel                       | HW bus (eg PCI)                          +      +-------------------------------------------------------------------+    +       hardware                     |                                          +                     +--------------+---+------------+                         +                     |         Switch device (sw1)   |                         +                     |  +----+                       +--------+                +                     |  |    v offloaded data path   | mgmt port               +                     |  |    |                       |                         +                     +--|----|----+----+----+----+---+                         +                        |    |    |    |    |    |                             +                        +    +    +    +    +    +                             +                       p1   p2   p3   p4   p5   p6 +                                        +                             front-panel ports                                 +                                                                               + + Fig 1. + + +Include Files +------------- + +#include +#include + + +Configuration +------------- + +Use "depends NET_SWITCHDEV" in driver's Kconfig to ensure switchdev model +support is built for driver. + + +Switch Ports +------------ + +On switchdev driver initialization, the driver will allocate and register a +struct net_device (using register_netdev()) for each enumerated physical switch +port, called the port netdev. A port netdev is the software representation of +the physical port and provides a conduit for control traffic to/from the +controller (the kernel) and the network, as well as an anchor point for higher +level constructs such as bridges, bonds, VLANs, tunnels, and L3 routers. Using +standard netdev tools (iproute2, ethtool, etc), the port netdev can also +provide to the user access to the physical properties of the switch port such +as PHY link state and I/O statistics. + +There is (currently) no higher-level kernel object for the switch beyond the +port netdevs. All of the switchdev driver ops are netdev ops or switchdev ops. + +A switch management port is outside the scope of the switchdev driver model. +Typically, the management port is not participating in offloaded data plane and +is loaded with a different driver, such as a NIC driver, on the management port +device. + +Port Netdev Naming +^^^^^^^^^^^^^^^^^^ + +Udev rules should be used for port netdev naming, using some unique attribute +of the port as a key, for example the port MAC address or the port PHYS name. +Hard-coding of kernel netdev names within the driver is discouraged; let the +kernel pick the default netdev name, and let udev set the final name based on a +port attribute. + +Using port PHYS name (ndo_get_phys_port_name) for the key is particularly +useful for dynically-named ports where the device names it's ports based on +external configuration. For example, if a physical 40G port is split logically +into 4 10G ports, resulting in 4 port netdevs, the device can give a unique +name for each port using port PHYS name. The udev rule would be: + +SUBSYSTEM=="net", ACTION=="add", DRIVER="", ATTR{phys_port_name}!="", \ + NAME="$attr{phys_port_name}" + +Suggested naming convention is "swXpYsZ", where X is the switch name or ID, Y +is the port name or ID, and Z is the sub-port name or ID. For example, sw1p1s0 +would be sub-port 0 on port 1 on switch 1. + +Switch ID +^^^^^^^^^ + +The switchdev driver must implement the switchdev op switchdev_port_attr_get for +SWITCHDEV_ATTR_PORT_PARENT_ID for each port netdev, returning the same physical ID +for each port of a switch. The ID must be unique between switches on the same +system. The ID does not need to be unique between switches on different +systems. + +The switch ID is used to locate ports on a switch and to know if aggregated +ports belong to the same switch. + +Port Features +^^^^^^^^^^^^^ + +NETIF_F_NETNS_LOCAL + +If the switchdev driver (and device) only supports offloading of the default +network namespace (netns), the driver should set this feature flag to prevent +the port netdev from being moved out of the default netns. A netns-aware +driver/device would not set this flag and be resposible for partitioning +hardware to preserve netns containment. This means hardware cannot forward +traffic from a port in one namespace to another port in another namespace. + +Port Topology +^^^^^^^^^^^^^ + +The port netdevs representing the physical switch ports can be organized into +higher-level switching constructs. The default construct is a standalone +router port, used to offload L3 forwarding. Two or more ports can be bonded +together to form a LAG. Two or more ports (or LAGs) can be bridged to bridge +to L2 networks. VLANs can be applied to sub-divide L2 networks. L2-over-L3 +tunnels can be built on ports. These constructs are built using standard Linux +tools such as the bridge driver, the bonding/team drivers, and netlink-based +tools such as iproute2. + +The switchdev driver can know a particular port's position in the topology by +monitoring NETDEV_CHANGEUPPER notifications. For example, a port moved into a +bond will see it's upper master change. If that bond is moved into a bridge, +the bond's upper master will change. And so on. The driver will track such +movements to know what position a port is in in the overall topology by +registering for netdevice events and acting on NETDEV_CHANGEUPPER. + +L2 Forwarding Offload +--------------------- + +The idea is to offload the L2 data forwarding (switching) path from the kernel +to the switchdev device by mirroring bridge FDB entries down to the device. An +FDB entry is the {port, MAC, VLAN} tuple forwarding destination. + +To offloading L2 bridging, the switchdev driver/device should support: + + - Static FDB entries installed on a bridge port + - Notification of learned/forgotten src mac/vlans from device + - STP state changes on the port + - VLAN flooding of multicast/broadcast and unknown unicast packets + +Static FDB Entries +^^^^^^^^^^^^^^^^^^ + +The switchdev driver should implement ndo_fdb_add, ndo_fdb_del and ndo_fdb_dump +to support static FDB entries installed to the device. Static bridge FDB +entries are installed, for example, using iproute2 bridge cmd: + + bridge fdb add ADDR dev DEV [vlan VID] [self] + +Note: by default, the bridge does not filter on VLAN and only bridges untagged +traffic. To enable VLAN support, turn on VLAN filtering: + + echo 1 >/sys/class/net//bridge/vlan_filtering + +Notification of Learned/Forgotten Source MAC/VLANs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The switch device will learn/forget source MAC address/VLAN on ingress packets +and notify the switch driver of the mac/vlan/port tuples. The switch driver, +in turn, will notify the bridge driver using the switchdev notifier call: + + err = call_switchdev_notifiers(val, dev, info); + +Where val is SWITCHDEV_FDB_ADD when learning and SWITCHDEV_FDB_DEL when forgetting, and +info points to a struct switchdev_notifier_fdb_info. On SWITCHDEV_FDB_ADD, the bridge +driver will install the FDB entry into the bridge's FDB and mark the entry as +NTF_EXT_LEARNED. The iproute2 bridge command will label these entries +"offload": + + $ bridge fdb + 52:54:00:12:35:01 dev sw1p1 master br0 permanent + 00:02:00:00:02:00 dev sw1p1 master br0 offload + 00:02:00:00:02:00 dev sw1p1 self + 52:54:00:12:35:02 dev sw1p2 master br0 permanent + 00:02:00:00:03:00 dev sw1p2 master br0 offload + 00:02:00:00:03:00 dev sw1p2 self + 33:33:00:00:00:01 dev eth0 self permanent + 01:00:5e:00:00:01 dev eth0 self permanent + 33:33:ff:00:00:00 dev eth0 self permanent + 01:80:c2:00:00:0e dev eth0 self permanent + 33:33:00:00:00:01 dev br0 self permanent + 01:00:5e:00:00:01 dev br0 self permanent + 33:33:ff:12:35:01 dev br0 self permanent + +Learning on the port should be disabled on the bridge using the bridge command: + + bridge link set dev DEV learning off + +Learning on the device port should be enabled, as well as learning_sync: + + bridge link set dev DEV learning on self + bridge link set dev DEV learning_sync on self + +Learning_sync attribute enables syncing of the learned/forgotton FDB entry to +the bridge's FDB. It's possible, but not optimal, to enable learning on the +device port and on the bridge port, and disable learning_sync. + +To support learning and learning_sync port attributes, the driver implements +switchdev op switchdev_port_attr_get/set for SWITCHDEV_ATTR_PORT_BRIDGE_FLAGS. The driver +should initialize the attributes to the hardware defaults. + +FDB Ageing +^^^^^^^^^^ + +There are two FDB ageing models supported: 1) ageing by the device, and 2) +ageing by the kernel. Ageing by the device is preferred if many FDB entries +are supported. The driver calls call_switchdev_notifiers(SWITCHDEV_FDB_DEL, ...) to +age out the FDB entry. In this model, ageing by the kernel should be turned +off. XXX: how to turn off ageing in kernel on a per-port basis or otherwise +prevent the kernel from ageing out the FDB entry? + +In the kernel ageing model, the standard bridge ageing mechanism is used to age +out stale FDB entries. To keep an FDB entry "alive", the driver should refresh +the FDB entry by calling call_switchdev_notifiers(SWITCHDEV_FDB_ADD, ...). The +notification will reset the FDB entry's last-used time to now. The driver +should rate limit refresh notifications, for example, no more than once a +second. If the FDB entry expires, ndo_fdb_del is called to remove entry from +the device. XXX: this last part isn't currently correct: ndo_fdb_del isn't +called, so the stale entry remains in device...this need to get fixed. + +FDB Flush +^^^^^^^^^ + +XXX: Unimplemented. Need to support FDB flush by bridge driver for port and +remove both static and learned FDB entries. + +STP State Change on Port +^^^^^^^^^^^^^^^^^^^^^^^^ + +Internally or with a third-party STP protocol implementation (e.g. mstpd), the +bridge driver maintains the STP state for ports, and will notify the switch +driver of STP state change on a port using the switchdev op switchdev_attr_port_set for +SWITCHDEV_ATTR_PORT_STP_UPDATE. + +State is one of BR_STATE_*. The switch driver can use STP state updates to +update ingress packet filter list for the port. For example, if port is +DISABLED, no packets should pass, but if port moves to BLOCKED, then STP BPDUs +and other IEEE 01:80:c2:xx:xx:xx link-local multicast packets can pass. + +Note that STP BDPUs are untagged and STP state applies to all VLANs on the port +so packet filters should be applied consistently across untagged and tagged +VLANs on the port. + +Flooding L2 domain +^^^^^^^^^^^^^^^^^^ + +For a given L2 VLAN domain, the switch device should flood multicast/broadcast +and unknown unicast packets to all ports in domain, if allowed by port's +current STP state. The switch driver, knowing which ports are within which +vlan L2 domain, can program the switch device for flooding. The packet should +also be sent to the port netdev for processing by the bridge driver. The +bridge should not reflood the packet to the same ports the device flooded. +XXX: the mechanism to avoid duplicate flood packets is being discuseed. + +It is possible for the switch device to not handle flooding and push the +packets up to the bridge driver for flooding. This is not ideal as the number +of ports scale in the L2 domain as the device is much more efficient at +flooding packets that software. + +IGMP Snooping +^^^^^^^^^^^^^ + +XXX: complete this section + + +L3 routing +---------- + +Offloading L3 routing requires that device be programmed with FIB entries from +the kernel, with the device doing the FIB lookup and forwarding. The device +does a longest prefix match (LPM) on FIB entries matching route prefix and +forwards the packet to the matching FIB entry's nexthop(s) egress ports. To +program the device, the switchdev driver is called with add/delete ops for IPv4 +and IPv6 FIB entries. For IPv4, the driver implements switchdev ops: + + int (*switchdev_fib_ipv4_add)(struct net_device *dev, + __be32 dst, int dst_len, + struct fib_info *fi, + u8 tos, u8 type, + u32 nlflags, u32 tb_id); + + int (*switchdev_fib_ipv4_del)(struct net_device *dev, + __be32 dst, int dst_len, + struct fib_info *fi, + u8 tos, u8 type, + u32 tb_id); + +to add/delete IPv4 dst/dest_len prefix on table tb_id. The *fi structure holds +details on the route and route's nexthops. *dev is one of the port netdevs +mentioned in the routes next hop list. If the output port netdevs referenced +in the route's nexthop list don't all have the same switch ID, the driver is +not called to add/delete the FIB entry. + +Routes offloaded to the device are labeled with "offload" in the ip route +listing: + + $ ip route show + default via 192.168.0.2 dev eth0 + 11.0.0.0/30 dev sw1p1 proto kernel scope link src 11.0.0.2 offload + 11.0.0.4/30 via 11.0.0.1 dev sw1p1 proto zebra metric 20 offload + 11.0.0.8/30 dev sw1p2 proto kernel scope link src 11.0.0.10 offload + 11.0.0.12/30 via 11.0.0.9 dev sw1p2 proto zebra metric 20 offload + 12.0.0.2 proto zebra metric 30 offload + nexthop via 11.0.0.1 dev sw1p1 weight 1 + nexthop via 11.0.0.9 dev sw1p2 weight 1 + 12.0.0.3 via 11.0.0.1 dev sw1p1 proto zebra metric 20 offload + 12.0.0.4 via 11.0.0.9 dev sw1p2 proto zebra metric 20 offload + 192.168.0.0/24 dev eth0 proto kernel scope link src 192.168.0.15 + +XXX: add/del IPv6 FIB API + +Nexthop Resolution +^^^^^^^^^^^^^^^^^^ + +The FIB entry's nexthop list contains the nexthop tuple (gateway, dev), but for +the switch device to forward the packet with the correct dst mac address, the +nexthop gateways must be resolved to the neighbor's mac address. Neighbor mac +address discovery comes via the ARP (or ND) process and is available via the +arp_tbl neighbor table. To resolve the routes nexthop gateways, the driver +should trigger the kernel's neighbor resolution process. See the rocker +driver's rocker_port_ipv4_resolve() for an example. + +The driver can monitor for updates to arp_tbl using the netevent notifier +NETEVENT_NEIGH_UPDATE. The device can be programmed with resolved nexthops +for the routes as arp_tbl updates. -- cgit v1.2.3 From bd1b40fe584e64f40fbb57e98dcfaf3b6e583642 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 6 Mar 2015 11:36:21 -0800 Subject: Documentation: devicetree: add binding doc for Broadcom NAND controller Signed-off-by: Brian Norris Reviewed-by: Florian Fainelli --- .../devicetree/bindings/mtd/brcm,brcmnand.txt | 110 +++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt new file mode 100644 index 000000000000..662c857e74fe --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt @@ -0,0 +1,110 @@ +* Broadcom STB NAND Controller + +The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND +flash chips. It has a memory-mapped register interface for both control +registers and for its data input/output buffer. On some SoCs, this controller is +paired with a custom DMA engine (inventively named "Flash DMA") which supports +basic PROGRAM and READ functions, among other features. + +This controller was originally designed for STB SoCs (BCM7xxx) but is now +available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and +iProc/Cygnus. Its history includes several similar (but not fully register +compatible) versions. + +Required properties: +- compatible : should contain "brcm,brcmnand" and an appropriate version + compatibility string, like "brcm,brcmnand-v7.0" + Possible values: + brcm,brcmnand-v4.0 + brcm,brcmnand-v5.0 + brcm,brcmnand-v6.0 + brcm,brcmnand-v6.1 + brcm,brcmnand-v7.0 + brcm,brcmnand-v7.1 + brcm,brcmnand +- reg : the register start and length for NAND register region. + (optional) Flash DMA register range (if present) + (optional) NAND flash cache range (if at non-standard offset) +- reg-names : a list of the names corresponding to the previous register + ranges. Should contain "nand" and (optionally) + "flash-dma" and/or "nand-cache". +- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) + FLASH_DMA_DONE +- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" +- interrupt-parent : See standard interrupt bindings +- #address-cells : <1> - subnodes give the chip-select number +- #size-cells : <0> + +Optional properties: +- brcm,nand-has-wp : Some versions of this IP include a write-protect + (WP) control bit. It is always available on >= + v7.0. Use this property to describe the rare + earlier versions of this core that include WP + +* NAND chip-select + +Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes +to represent enabled chip-selects which (may) contain NAND flash chips. Their +properties are as follows. + +Required properties: +- compatible : should contain "brcm,nandcs" +- reg : a single integer representing the chip-select + number (e.g., 0, 1, 2, etc.) +- #address-cells : see partition.txt +- #size-cells : see partition.txt +- nand-ecc-strength : see nand.txt +- nand-ecc-step-size : must be 512 or 1024. See nand.txt + +Optional properties: +- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this + chip-select. See nand.txt +- brcm,nand-oob-sector-size : integer, to denote the spare area sector size + expected for the ECC layout in use. This size, in + addition to the strength and step-size, + determines how the hardware BCH engine will lay + out the parity bytes it stores on the flash. + This property can be automatically determined by + the flash geometry (particularly the NAND page + and OOB size) in many cases, but when booting + from NAND, the boot controller has only a limited + number of available options for its default ECC + layout. + +Each nandcs device node may optionally contain sub-nodes describing the flash +partition mapping. See partition.txt for more detail. + +Example: + +nand@f0442800 { + compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; + reg = <0xF0442800 0x600>, + <0xF0443000 0x100>; + reg-names = "nand", "flash-dma"; + interrupt-parent = <&hif_intr2_intc>; + interrupts = <24>, <4>; + + #address-cells = <1>; + #size-cells = <0>; + + nandcs@1 { + compatible = "brcm,nandcs"; + reg = <1>; // Chip select 1 + nand-on-flash-bbt; + nand-ecc-strength = <12>; + nand-ecc-step-size = <512>; + + // Partitions + #address-cells = <1>; // <2>, for 64-bit offset + #size-cells = <1>; // <2>, for 64-bit length + flash0.rootfs@0 { + reg = <0 0x10000000>; + }; + flash0@0 { + reg = <0 0>; // MTDPART_SIZ_FULL + }; + flash0.kernel@10000000 { + reg = <0x10000000 0x400000>; + }; + }; +}; -- cgit v1.2.3 From 8265a2f89c8ecf526931951fa240982d1f438736 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Sat, 11 Apr 2015 17:07:03 +0200 Subject: ima: added ima-sig template among choices in kernel-parameters.txt This patch adds the template 'ima-sig' among choices for the kernel parameter 'ima_template'. Signed-off-by: Roberto Sassu Signed-off-by: Mimi Zohar --- Documentation/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index f6befa9855c1..abc496f95220 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1406,7 +1406,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. ima_template= [IMA] Select one of defined IMA measurements template formats. - Formats: { "ima" | "ima-ng" } + Formats: { "ima" | "ima-ng" | "ima-sig" } Default: "ima-ng" ima_template_fmt= -- cgit v1.2.3 From e34812c5bac8de641a2551b5ccb601627c10e772 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Thu, 12 Mar 2015 15:47:56 +0100 Subject: of: document new emc-timings subnode in nvidia,tegra124-car The EMC clock needs some extra information for changing its rate. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra124-car.txt | 42 +++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt index c6620bc96703..c3891cece73f 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt @@ -21,10 +21,31 @@ Required properties : In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +The node should contain a "emc-timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A). + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set + is used for. + +Each "emc-timings" node should contain a "timing" subnode for every supported +EMC clock rate. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate to which this timing +relates. +- nvidia,parent-clock-frequency : Should contain the rate at which the current +parent of the EMC clock should be running at this timing. +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + - emc-parent : the clock that should be the parent of the EMC clock at this +timing. + Example SoC include file: / { - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra124-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; @@ -62,4 +83,23 @@ Example board file: &tegra_car { clocks = <&clk_32k> <&osc>; }; + + clock@60006000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + }; + }; }; -- cgit v1.2.3 From ef03b35a9a2cadd6b3abc758dab4c580a454760c Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Thu, 12 Mar 2015 15:47:59 +0100 Subject: of: document external-memory-controller property in tegra124-car This property contains a phandle to the EMC driver that is needed by the EMC clock to request the EMC driver to do its part of the clock change sequence. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt index c3891cece73f..7f02fb4ca4ad 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt @@ -20,6 +20,7 @@ Required properties : - #reset-cells : Should be 1. In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +- nvidia,external-memory-controller : phandle of the EMC driver. The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in register PMC_STRAPPING_OPT_A). @@ -50,6 +51,7 @@ Example SoC include file: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; usb@c5004000 { -- cgit v1.2.3 From c354b54cfdf63587154da4fa0731c1fbda44c589 Mon Sep 17 00:00:00 2001 From: Sergej Sawazki Date: Wed, 13 May 2015 11:39:01 +0200 Subject: ASoC: wm8741: Add differential mono mode support The WM8741 DAC supports several differential output modes (stereo, stereo reversed, mono left, mono right). Add platform data and DT bindings to configure it. Signed-off-by: Sergej Sawazki Acked-by: Charles Keepax Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/wm8741.txt | 11 ++ sound/soc/codecs/wm8741.c | 129 ++++++++++++++++++--- sound/soc/codecs/wm8741.h | 10 ++ 3 files changed, 137 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/wm8741.txt b/Documentation/devicetree/bindings/sound/wm8741.txt index 74bda58c1bcf..a13315408719 100644 --- a/Documentation/devicetree/bindings/sound/wm8741.txt +++ b/Documentation/devicetree/bindings/sound/wm8741.txt @@ -10,9 +10,20 @@ Required properties: - reg : the I2C address of the device for I2C, the chip select number for SPI. +Optional properties: + + - diff-mode: Differential output mode configuration. Default value for field + DIFF in register R8 (MODE_CONTROL_2). If absent, the default is 0, shall be: + 0 = stereo + 1 = mono left + 2 = stereo reversed + 3 = mono right + Example: codec: wm8741@1a { compatible = "wlf,wm8741"; reg = <0x1a>; + + diff-mode = <3>; }; diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c index 9e71c768966f..c065ea166875 100644 --- a/sound/soc/codecs/wm8741.c +++ b/sound/soc/codecs/wm8741.c @@ -41,6 +41,7 @@ static const char *wm8741_supply_names[WM8741_NUM_SUPPLIES] = { /* codec private data */ struct wm8741_priv { + struct wm8741_platform_data pdata; struct regmap *regmap; struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES]; unsigned int sysclk; @@ -87,13 +88,27 @@ static int wm8741_reset(struct snd_soc_codec *codec) static const DECLARE_TLV_DB_SCALE(dac_tlv_fine, -12700, 13, 0); static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 400, 0); -static const struct snd_kcontrol_new wm8741_snd_controls[] = { +static const struct snd_kcontrol_new wm8741_snd_controls_stereo[] = { SOC_DOUBLE_R_TLV("Fine Playback Volume", WM8741_DACLLSB_ATTENUATION, WM8741_DACRLSB_ATTENUATION, 1, 255, 1, dac_tlv_fine), SOC_DOUBLE_R_TLV("Playback Volume", WM8741_DACLMSB_ATTENUATION, WM8741_DACRMSB_ATTENUATION, 0, 511, 1, dac_tlv), }; +static const struct snd_kcontrol_new wm8741_snd_controls_mono_left[] = { +SOC_SINGLE_TLV("Fine Playback Volume", WM8741_DACLLSB_ATTENUATION, + 1, 255, 1, dac_tlv_fine), +SOC_SINGLE_TLV("Playback Volume", WM8741_DACLMSB_ATTENUATION, + 0, 511, 1, dac_tlv), +}; + +static const struct snd_kcontrol_new wm8741_snd_controls_mono_right[] = { +SOC_SINGLE_TLV("Fine Playback Volume", WM8741_DACRLSB_ATTENUATION, + 1, 255, 1, dac_tlv_fine), +SOC_SINGLE_TLV("Playback Volume", WM8741_DACRMSB_ATTENUATION, + 0, 511, 1, dac_tlv), +}; + static const struct snd_soc_dapm_widget wm8741_dapm_widgets[] = { SND_SOC_DAPM_DAC("DACL", "Playback", SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_DAC("DACR", "Playback", SND_SOC_NOPM, 0, 0), @@ -398,7 +413,7 @@ static struct snd_soc_dai_driver wm8741_dai = { .name = "wm8741", .playback = { .stream_name = "Playback", - .channels_min = 2, /* Mono modes not yet supported */ + .channels_min = 2, .channels_max = 2, .rates = WM8741_RATES, .formats = WM8741_FORMATS, @@ -416,6 +431,65 @@ static int wm8741_resume(struct snd_soc_codec *codec) #define wm8741_resume NULL #endif +static int wm8741_configure(struct snd_soc_codec *codec) +{ + struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec); + + /* Configure differential mode */ + switch (wm8741->pdata.diff_mode) { + case WM8741_DIFF_MODE_STEREO: + case WM8741_DIFF_MODE_STEREO_REVERSED: + case WM8741_DIFF_MODE_MONO_LEFT: + case WM8741_DIFF_MODE_MONO_RIGHT: + snd_soc_update_bits(codec, WM8741_MODE_CONTROL_2, + WM8741_DIFF_MASK, + wm8741->pdata.diff_mode << WM8741_DIFF_SHIFT); + break; + default: + return -EINVAL; + } + + /* Change some default settings - latch VU */ + snd_soc_update_bits(codec, WM8741_DACLLSB_ATTENUATION, + WM8741_UPDATELL, WM8741_UPDATELL); + snd_soc_update_bits(codec, WM8741_DACLMSB_ATTENUATION, + WM8741_UPDATELM, WM8741_UPDATELM); + snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION, + WM8741_UPDATERL, WM8741_UPDATERL); + snd_soc_update_bits(codec, WM8741_DACRMSB_ATTENUATION, + WM8741_UPDATERM, WM8741_UPDATERM); + + return 0; +} + +static int wm8741_add_controls(struct snd_soc_codec *codec) +{ + struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec); + + switch (wm8741->pdata.diff_mode) { + case WM8741_DIFF_MODE_STEREO: + case WM8741_DIFF_MODE_STEREO_REVERSED: + snd_soc_add_codec_controls(codec, + wm8741_snd_controls_stereo, + ARRAY_SIZE(wm8741_snd_controls_stereo)); + break; + case WM8741_DIFF_MODE_MONO_LEFT: + snd_soc_add_codec_controls(codec, + wm8741_snd_controls_mono_left, + ARRAY_SIZE(wm8741_snd_controls_mono_left)); + break; + case WM8741_DIFF_MODE_MONO_RIGHT: + snd_soc_add_codec_controls(codec, + wm8741_snd_controls_mono_right, + ARRAY_SIZE(wm8741_snd_controls_mono_right)); + break; + default: + return -EINVAL; + } + + return 0; +} + static int wm8741_probe(struct snd_soc_codec *codec) { struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec); @@ -434,15 +508,17 @@ static int wm8741_probe(struct snd_soc_codec *codec) goto err_enable; } - /* Change some default settings - latch VU */ - snd_soc_update_bits(codec, WM8741_DACLLSB_ATTENUATION, - WM8741_UPDATELL, WM8741_UPDATELL); - snd_soc_update_bits(codec, WM8741_DACLMSB_ATTENUATION, - WM8741_UPDATELM, WM8741_UPDATELM); - snd_soc_update_bits(codec, WM8741_DACRLSB_ATTENUATION, - WM8741_UPDATERL, WM8741_UPDATERL); - snd_soc_update_bits(codec, WM8741_DACRMSB_ATTENUATION, - WM8741_UPDATERM, WM8741_UPDATERM); + ret = wm8741_configure(codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to change default settings\n"); + goto err_enable; + } + + ret = wm8741_add_controls(codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to add controls\n"); + goto err_enable; + } dev_dbg(codec->dev, "Successful registration\n"); return ret; @@ -467,8 +543,6 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8741 = { .remove = wm8741_remove, .resume = wm8741_resume, - .controls = wm8741_snd_controls, - .num_controls = ARRAY_SIZE(wm8741_snd_controls), .dapm_widgets = wm8741_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(wm8741_dapm_widgets), .dapm_routes = wm8741_dapm_routes, @@ -493,6 +567,23 @@ static const struct regmap_config wm8741_regmap = { .readable_reg = wm8741_readable, }; +static int wm8741_set_pdata(struct device *dev, struct wm8741_priv *wm8741) +{ + const struct wm8741_platform_data *pdata = dev_get_platdata(dev); + u32 diff_mode; + + if (dev->of_node) { + if (of_property_read_u32(dev->of_node, "diff-mode", &diff_mode) + >= 0) + wm8741->pdata.diff_mode = diff_mode; + } else { + if (pdata != NULL) + memcpy(&wm8741->pdata, pdata, sizeof(wm8741->pdata)); + } + + return 0; +} + #if IS_ENABLED(CONFIG_I2C) static int wm8741_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) @@ -522,6 +613,12 @@ static int wm8741_i2c_probe(struct i2c_client *i2c, return ret; } + wm8741_set_pdata(&i2c->dev, wm8741); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to set pdata: %d\n", ret); + return ret; + } + i2c_set_clientdata(i2c, wm8741); ret = snd_soc_register_codec(&i2c->dev, @@ -582,6 +679,12 @@ static int wm8741_spi_probe(struct spi_device *spi) return ret; } + wm8741_set_pdata(&spi->dev, wm8741); + if (ret != 0) { + dev_err(&spi->dev, "Failed to set pdata: %d\n", ret); + return ret; + } + spi_set_drvdata(spi, wm8741); ret = snd_soc_register_codec(&spi->dev, diff --git a/sound/soc/codecs/wm8741.h b/sound/soc/codecs/wm8741.h index 56c1b1d4a681..c8835f65f342 100644 --- a/sound/soc/codecs/wm8741.h +++ b/sound/soc/codecs/wm8741.h @@ -194,6 +194,12 @@ #define WM8741_DITHER_SHIFT 0 /* DITHER - [1:0] */ #define WM8741_DITHER_WIDTH 2 /* DITHER - [1:0] */ +/* DIFF field values */ +#define WM8741_DIFF_MODE_STEREO 0 /* stereo normal */ +#define WM8741_DIFF_MODE_STEREO_REVERSED 2 /* stereo reversed */ +#define WM8741_DIFF_MODE_MONO_LEFT 1 /* mono left */ +#define WM8741_DIFF_MODE_MONO_RIGHT 3 /* mono right */ + /* * R32 (0x20) - ADDITONAL_CONTROL_1 */ @@ -208,4 +214,8 @@ #define WM8741_SYSCLK 0 +struct wm8741_platform_data { + u32 diff_mode; /* Differential Output Mode */ +}; + #endif -- cgit v1.2.3 From 768a87c8e12e17b44ab2163be70739ec5889f06f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 10 Apr 2015 12:09:02 +0800 Subject: mfd: axp20x: Update DT bindings with AXP22x compatibles Add AXP221 to the list of supported devices. Also replace any mention of AXP20x in the document with a generic "PMIC". Signed-off-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 98685f291a72..3914a3f91ff6 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -1,15 +1,16 @@ -AXP202/AXP209 device tree bindings +AXP family PMIC device tree bindings The axp20x family current members : axp202 (X-Powers) axp209 (X-Powers) +axp221 (X-Powers) Required properties: -- compatible: "x-powers,axp202" or "x-powers,axp209" +- compatible: "x-powers,axp202", "x-powers,axp209", "x-powers,axp221" - reg: The I2C slave address for the AXP chip - interrupt-parent: The parent interrupt controller - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin -- interrupt-controller: axp20x has its own internal IRQs +- interrupt-controller: The PMIC has its own internal IRQs - #interrupt-cells: Should be set to 1 Optional properties: -- cgit v1.2.3 From 97ba5ac1f2a5e3e07b67133215b2958bd4f1b41a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 10 Apr 2015 12:09:05 +0800 Subject: mfd: axp20x: Add AXP22x regulator information to DT bindings Add the list of regulators for AXP22x to the DT bindings. This includes the names and supply names. Signed-off-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/axp20x.txt | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 3914a3f91ff6..753f14f46e85 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -49,6 +49,31 @@ LDO3 : LDO : ldo3in-supply LDO4 : LDO : ldo24in-supply : shared supply LDO5 : LDO : ldo5in-supply +AXP221 regulators, type, and corresponding input supply names: + +Regulator Type Supply Name Notes +--------- ---- ----------- ----- +DCDC1 : DC-DC buck : vin1-supply +DCDC2 : DC-DC buck : vin2-supply +DCDC3 : DC-DC buck : vin3-supply +DCDC4 : DC-DC buck : vin4-supply +DCDC5 : DC-DC buck : vin5-supply +DC1SW : On/Off Switch : dcdc1-supply : DCDC1 secondary output +DC5LDO : LDO : dcdc5-supply : input from DCDC5 +ALDO1 : LDO : aldoin-supply : shared supply +ALDO2 : LDO : aldoin-supply : shared supply +ALDO3 : LDO : aldoin-supply : shared supply +DLDO1 : LDO : dldoin-supply : shared supply +DLDO2 : LDO : dldoin-supply : shared supply +DLDO3 : LDO : dldoin-supply : shared supply +DLDO4 : LDO : dldoin-supply : shared supply +ELDO1 : LDO : eldoin-supply : shared supply +ELDO2 : LDO : eldoin-supply : shared supply +ELDO3 : LDO : eldoin-supply : shared supply +LDO_IO0 : LDO : ips-supply : GPIO 0 +LDO_IO1 : LDO : ips-supply : GPIO 1 +RTC_LDO : LDO : ips-supply : always on + Example: axp209: pmic@34 { -- cgit v1.2.3 From 1f5dc44c881281c6573b73366bcfde575074d1b0 Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Tue, 12 May 2015 23:03:54 -0700 Subject: switchdev: apply review comments on documentation There were a few review comments on the switchdev.txt documentation that didn't get included with the Spring Cleanup series, so include them now. Signed-off-by: Scott Feldman Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index b3e18c8fd040..616f89267d23 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -99,7 +99,7 @@ kernel pick the default netdev name, and let udev set the final name based on a port attribute. Using port PHYS name (ndo_get_phys_port_name) for the key is particularly -useful for dynically-named ports where the device names it's ports based on +useful for dynamically-named ports where the device names its ports based on external configuration. For example, if a physical 40G port is split logically into 4 10G ports, resulting in 4 port netdevs, the device can give a unique name for each port using port PHYS name. The udev rule would be: @@ -131,7 +131,7 @@ NETIF_F_NETNS_LOCAL If the switchdev driver (and device) only supports offloading of the default network namespace (netns), the driver should set this feature flag to prevent the port netdev from being moved out of the default netns. A netns-aware -driver/device would not set this flag and be resposible for partitioning +driver/device would not set this flag and be responsible for partitioning hardware to preserve netns containment. This means hardware cannot forward traffic from a port in one namespace to another port in another namespace. @@ -177,6 +177,9 @@ entries are installed, for example, using iproute2 bridge cmd: bridge fdb add ADDR dev DEV [vlan VID] [self] +XXX: what should be done if offloading this rule to hardware fails (for +example, due to full capacity in hardware tables) ? + Note: by default, the bridge does not filter on VLAN and only bridges untagged traffic. To enable VLAN support, turn on VLAN filtering: -- cgit v1.2.3 From b3e913bed6ac8ea0cd01233252699fb43de754a5 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 17 Apr 2015 10:48:46 -0700 Subject: Documentation: DT: Add Broadcom BCM63138 PMB binding Add a Device Tree binding for the Broadcom BCM63138 Processor Monitor Bus, which is an internal bus used to access different power and reset signals within a BCM63138 System-on-a-Chip. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/reset/brcm,bcm63138-pmb.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt b/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt new file mode 100644 index 000000000000..a98872d27872 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt @@ -0,0 +1,19 @@ +Broadcom BCM63138 Processor Monitor Bus binding +=============================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Require properties: + +- compatible: must be "brcm,bcm63138-pmb" +- reg: base register address and size for this bus controller +- #reset-cells: must be 2 first cell is the address within the bus instance designated + by the phandle, and the second is the number of zones for this peripheral + +Example: + pmb0: reset-controller@4800c0 { + compatible = "brcm,bcm63138-pmb"; + reg = <0x4800c0 0x10>; + #reset-cells = <2>; + }; -- cgit v1.2.3 From a4cdbb96edd975a88688c2464dbb0de8dfe25e3d Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 17 Apr 2015 11:21:39 -0700 Subject: Documentation: DT: Document SMP DT nodes and properties for BCM63138 Add binding documentation for the additional nodes and properties required to get the secondary CPU online on the BCM63138 SoC. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/brcm,bcm63138.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt index bd49987a8812..999e074b8ac3 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt @@ -7,3 +7,45 @@ following properties: Required root node property: compatible: should be "brcm,bcm63138" + +An optional Boot lookup table Device Tree node is required for secondary CPU +initialization as well as a 'resets' phandle to the correct PMB controller as +defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an +'enable-method' property. + +Required properties for the Boot lookup table node: +- compatible: should be "brcm,bcm63138-bootlut" +- reg: register base address and length for the Boot Lookup table + +Optional properties for the primary CPU node: +- enable-method: should be "brcm,bcm63138" + +Optional properties for the secondary CPU node: +- enable-method: should be "brcm,bcm63138" +- resets: phandle to the relevant PMB controller, one integer indicating the internal + bus number, and a second integer indicating the address of the CPU in the PMB + internal bus number. + +Example: + + cpus { + cpu@0 { + compatible = "arm,cotex-a9"; + reg = <0>; + ... + enable-method = "brcm,bcm63138"; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + ... + enable-method = "brcm,bcm63138"; + resets = <&pmb0 4 1>; + }; + }; + + bootlut: bootlut@8000 { + compatible = "brcm,bcm63138-bootlut"; + reg = <0x8000 0x50>; + }; -- cgit v1.2.3 From 3e10a2ce98d1a57992a44ed40325af60ab7b0f5d Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Wed, 13 May 2015 15:26:49 +0300 Subject: usb: dwc3: add hsphy_interface property Platforms that have configured DWC_USB3_HSPHY_INTERFACE with value 3, i.e. UTMI+ and ULPI, need to inform the driver of the actual HSPHY interface type with the property. "utmi" if the interface is UTMI+ or "ulpi" if the interface is ULPI. Signed-off-by: Heikki Krogerus Acked-by: David Cohen Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++ drivers/usb/dwc3/core.h | 3 +++ drivers/usb/dwc3/platform_data.h | 2 ++ 4 files changed, 27 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 5cc364309edb..0815eac5b185 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -38,6 +38,8 @@ Optional properties: - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold + - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for + UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. This is usually a subnode to DWC3 glue to which it is connected. diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 6b02e12aad73..0de8968a2e97 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -438,6 +438,22 @@ static void dwc3_phy_setup(struct dwc3 *dwc) reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + /* Select the HS PHY interface */ + switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { + case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: + if (!strncmp(dwc->hsphy_interface, "utmi", 4)) { + reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; + } else if (!strncmp(dwc->hsphy_interface, "ulpi", 4)) { + reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; + } else { + dev_warn(dwc->dev, "HSPHY Interface not defined\n"); + break; + } + /* FALLTHROUGH */ + default: + break; + } + /* * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to * '0' during coreConsultant configuration. So default value will @@ -844,6 +860,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,tx_de_emphasis_quirk"); of_property_read_u8(node, "snps,tx_de_emphasis", &tx_de_emphasis); + of_property_read_string(node, "snps,hsphy_interface", + &dwc->hsphy_interface); } else if (pdata) { dwc->maximum_speed = pdata->maximum_speed; dwc->has_lpm_erratum = pdata->has_lpm_erratum; @@ -871,6 +889,8 @@ static int dwc3_probe(struct platform_device *pdev) dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; if (pdata->tx_de_emphasis) tx_de_emphasis = pdata->tx_de_emphasis; + + dwc->hsphy_interface = pdata->hsphy_interface; } /* default to superspeed if no maximum_speed passed */ diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index c6eafaab8b27..7b3ab64a387e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -682,6 +682,7 @@ struct dwc3_scratchpad_array { * @test_mode_nr: test feature selector * @lpm_nyet_threshold: LPM NYET response threshold * @hird_threshold: HIRD threshold + * @hsphy_interface: "utmi" or "ulpi" * @delayed_status: true when gadget driver asks for delayed status * @ep0_bounced: true when we used bounce buffer * @ep0_expect_in: true when we expect a DATA IN transfer @@ -809,6 +810,8 @@ struct dwc3 { u8 lpm_nyet_threshold; u8 hird_threshold; + const char *hsphy_interface; + unsigned delayed_status:1; unsigned ep0_bounced:1; unsigned ep0_expect_in:1; diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index a2bd464be828..d3614ecbb9ca 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -45,4 +45,6 @@ struct dwc3_platform_data { unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; + + const char *hsphy_interface; }; -- cgit v1.2.3 From 5dc11e810676ec4a5acb4423ccd33314bf74f4e5 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 31 Mar 2015 16:42:37 +0530 Subject: iio: adc: ti_am335x_adc: make sample delay, open delay, averaging DT parameters Add optional DT properties to set open delay, sample delay and number of averages per sample for each adc step. Open delay, sample delay and averaging are some of the parameters that affect the sampling rate and accuracy of the sample. Making these parameters configurable via DT will help in balancing speed vs accuracy. Signed-off-by: Vignesh R Signed-off-by: Jonathan Cameron --- .../bindings/input/touchscreen/ti-tsc-adc.txt | 24 ++++++++++ drivers/iio/adc/ti_am335x_adc.c | 54 +++++++++++++++++++--- 2 files changed, 72 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt index 6c4fb34823d3..b1163bf97146 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt @@ -42,6 +42,27 @@ Optional properties: hardware knob for adjusting the amount of "settling time". +- child "adc" + ti,chan-step-opendelay: List of open delays for each channel of + ADC in the order of ti,adc-channels. The + value corresponds to the number of ADC + clock cycles to wait after applying the + step configuration registers and before + sending the start of ADC conversion. + Maximum value is 0x3FFFF. + ti,chan-step-sampledelay: List of sample delays for each channel + of ADC in the order of ti,adc-channels. + The value corresponds to the number of + ADC clock cycles to sample (to hold + start of conversion high). + Maximum value is 0xFF. + ti,chan-step-avg: Number of averages to be performed for each + channel of ADC. If average is 16 then input + is sampled 16 times and averaged to get more + accurate value. This increases the time taken + by ADC to generate a sample. Valid range is 0 + average to 16 averages. Maximum value is 16. + Example: tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; @@ -55,5 +76,8 @@ Example: adc { ti,adc-channels = <4 5 6 7>; + ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>; + ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>; + ti,chan-step-avg = <16 2 4 8>; }; } diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c index 42e444044ea5..942320e32753 100644 --- a/drivers/iio/adc/ti_am335x_adc.c +++ b/drivers/iio/adc/ti_am335x_adc.c @@ -37,6 +37,7 @@ struct tiadc_device { u8 channel_step[8]; int buffer_en_ch_steps; u16 data[8]; + u32 open_delay[8], sample_delay[8], step_avg[8]; }; static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) @@ -85,6 +86,7 @@ static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) static void tiadc_step_config(struct iio_dev *indio_dev) { struct tiadc_device *adc_dev = iio_priv(indio_dev); + struct device *dev = adc_dev->mfd_tscadc->dev; unsigned int stepconfig; int i, steps = 0; @@ -98,20 +100,47 @@ static void tiadc_step_config(struct iio_dev *indio_dev) * needs to be given to ADC to digitalize data. */ - if (iio_buffer_enabled(indio_dev)) - stepconfig = STEPCONFIG_AVG_16 | STEPCONFIG_FIFO1 - | STEPCONFIG_MODE_SWCNT; - else - stepconfig = STEPCONFIG_AVG_16 | STEPCONFIG_FIFO1; for (i = 0; i < adc_dev->channels; i++) { int chan; chan = adc_dev->channel_line[i]; + + if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { + dev_warn(dev, "chan %d step_avg truncating to %d\n", + chan, STEPCONFIG_AVG_16); + adc_dev->step_avg[i] = STEPCONFIG_AVG_16; + } + + if (adc_dev->step_avg[i]) + stepconfig = + STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | + STEPCONFIG_FIFO1; + else + stepconfig = STEPCONFIG_FIFO1; + + if (iio_buffer_enabled(indio_dev)) + stepconfig |= STEPCONFIG_MODE_SWCNT; + tiadc_writel(adc_dev, REG_STEPCONFIG(steps), stepconfig | STEPCONFIG_INP(chan)); + + if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) { + dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n", + chan); + adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK; + } + + if (adc_dev->sample_delay[i] > 0xFF) { + dev_warn(dev, "chan %d sample delay truncating to 0xFF\n", + chan); + adc_dev->sample_delay[i] = 0xFF; + } + tiadc_writel(adc_dev, REG_STEPDELAY(steps), - STEPCONFIG_OPENDLY); + STEPDELAY_OPEN(adc_dev->open_delay[i]) | + STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); + adc_dev->channel_step[i] = steps; steps++; } @@ -406,9 +435,22 @@ static int tiadc_parse_dt(struct platform_device *pdev, of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { adc_dev->channel_line[channels] = val; + + /* Set Default values for optional DT parameters */ + adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; + adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; + adc_dev->step_avg[channels] = 16; + channels++; } + of_property_read_u32_array(node, "ti,chan-step-avg", + adc_dev->step_avg, channels); + of_property_read_u32_array(node, "ti,chan-step-opendelay", + adc_dev->open_delay, channels); + of_property_read_u32_array(node, "ti,chan-step-sampledelay", + adc_dev->sample_delay, channels); + adc_dev->channels = channels; return 0; } -- cgit v1.2.3 From ac61cf8a01924b0794d0eda80688714368e27d0b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 23 Apr 2015 15:55:00 -0700 Subject: dt-bindings: Add documentation for the BCM63138 timer and syscon-reboot A timer node and a syscon-reboot node are required for software reboot to work on BCM63138, document these two nodes in the platform binding. Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/brcm,bcm63138.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt index 999e074b8ac3..b82b6a0ae6f7 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt @@ -49,3 +49,37 @@ Example: compatible = "brcm,bcm63138-bootlut"; reg = <0x8000 0x50>; }; + +======= +reboot +------ +Two nodes are required for software reboot: a timer node and a syscon-reboot node. + +Timer node: + +- compatible: Must be "brcm,bcm6328-timer", "syscon" +- reg: Register base address and length + +Syscon reboot node: + +See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the +detailed list of properties, the two values defined below are specific to the +BCM6328-style timer: + +- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register + from the beginning of the TIMER block +- mask: Should be 1 for the SoftRst bit. + +Example: + + timer: timer@80 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x80 0x3c>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <0x1>; + }; -- cgit v1.2.3 From e578d9c02587d57bfa7b560767c698a668a468c6 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Mon, 11 May 2015 19:50:41 +0200 Subject: net: sched: use counter to break reclassify loops Seems all we want here is to avoid endless 'goto reclassify' loop. tc_classify_compat even resets this counter when something other than TC_ACT_RECLASSIFY is returned, so this skb-counter doesn't break hypothetical loops induced by something other than perpetual TC_ACT_RECLASSIFY return values. skb_act_clone is now identical to skb_clone, so just use that. Tested with following (bogus) filter: tc filter add dev eth0 parent ffff: \ protocol ip u32 match u32 0 0 police rate 10Kbit burst \ 64000 mtu 1500 action reclassify Acked-by: Daniel Borkmann Signed-off-by: Florian Westphal Acked-by: Alexei Starovoitov Acked-by: Jamal Hadi Salim Signed-off-by: David S. Miller --- Documentation/networking/tc-actions-env-rules.txt | 4 ---- include/net/sch_generic.h | 15 --------------- include/uapi/linux/pkt_cls.h | 2 +- net/sched/act_mirred.c | 2 +- net/sched/sch_api.c | 12 +++--------- 5 files changed, 5 insertions(+), 30 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/tc-actions-env-rules.txt b/Documentation/networking/tc-actions-env-rules.txt index 95c71716b2e2..f37814693ad3 100644 --- a/Documentation/networking/tc-actions-env-rules.txt +++ b/Documentation/networking/tc-actions-env-rules.txt @@ -8,10 +8,6 @@ For example if your action queues a packet to be processed later, or intentionally branches by redirecting a packet, then you need to clone the packet. -There are certain fields in the skb tc_verd that need to be reset so we -avoid loops, etc. A few are generic enough that skb_act_clone() -resets them for you, so invoke skb_act_clone() rather than skb_clone(). - 2) If you munge any packet thou shalt call pskb_expand_head in the case someone else is referencing the skb. After that you "own" the skb. diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 1b0a2e88ed2b..2738f6f87908 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -739,21 +739,6 @@ static inline u32 qdisc_l2t(struct qdisc_rate_table* rtab, unsigned int pktlen) return rtab->data[slot]; } -#ifdef CONFIG_NET_CLS_ACT -static inline struct sk_buff *skb_act_clone(struct sk_buff *skb, gfp_t gfp_mask, - int action) -{ - struct sk_buff *n; - - n = skb_clone(skb, gfp_mask); - - if (n) { - n->tc_verd = SET_TC_VERD(n->tc_verd, 0); - } - return n; -} -#endif - struct psched_ratecfg { u64 rate_bytes_ps; /* bytes per second */ u32 mult; diff --git a/include/uapi/linux/pkt_cls.h b/include/uapi/linux/pkt_cls.h index 596ffa0c7084..ffc112c8e1c2 100644 --- a/include/uapi/linux/pkt_cls.h +++ b/include/uapi/linux/pkt_cls.h @@ -44,13 +44,13 @@ bits 9,10,11: redirect counter - redirect TTL. Loop avoidance #define TC_OK2MUNGE _TC_MAKEMASK1(1) #define SET_TC_OK2MUNGE(v) ( TC_OK2MUNGE | (v & ~TC_OK2MUNGE)) #define CLR_TC_OK2MUNGE(v) ( v & ~TC_OK2MUNGE) -#endif #define S_TC_VERD _TC_MAKE32(2) #define M_TC_VERD _TC_MAKEMASK(4,S_TC_VERD) #define G_TC_VERD(x) _TC_GETVALUE(x,S_TC_VERD,M_TC_VERD) #define V_TC_VERD(x) _TC_MAKEVALUE(x,S_TC_VERD) #define SET_TC_VERD(v,n) ((V_TC_VERD(n)) | (v & ~M_TC_VERD)) +#endif #define S_TC_FROM _TC_MAKE32(6) #define M_TC_FROM _TC_MAKEMASK(2,S_TC_FROM) diff --git a/net/sched/act_mirred.c b/net/sched/act_mirred.c index 3f63ceac8e01..a42a3b257226 100644 --- a/net/sched/act_mirred.c +++ b/net/sched/act_mirred.c @@ -151,7 +151,7 @@ static int tcf_mirred(struct sk_buff *skb, const struct tc_action *a, } at = G_TC_AT(skb->tc_verd); - skb2 = skb_act_clone(skb, GFP_ATOMIC, m->tcf_action); + skb2 = skb_clone(skb, GFP_ATOMIC); if (skb2 == NULL) goto out; diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index ad9eed70bc8f..0b74dc0ede9c 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1816,13 +1816,8 @@ int tc_classify_compat(struct sk_buff *skb, const struct tcf_proto *tp, continue; err = tp->classify(skb, tp, res); - if (err >= 0) { -#ifdef CONFIG_NET_CLS_ACT - if (err != TC_ACT_RECLASSIFY && skb->tc_verd) - skb->tc_verd = SET_TC_VERD(skb->tc_verd, 0); -#endif + if (err >= 0) return err; - } } return -1; } @@ -1834,23 +1829,22 @@ int tc_classify(struct sk_buff *skb, const struct tcf_proto *tp, int err = 0; #ifdef CONFIG_NET_CLS_ACT const struct tcf_proto *otp = tp; + int limit = 0; reclassify: #endif err = tc_classify_compat(skb, tp, res); #ifdef CONFIG_NET_CLS_ACT if (err == TC_ACT_RECLASSIFY) { - u32 verd = G_TC_VERD(skb->tc_verd); tp = otp; - if (verd++ >= MAX_REC_LOOP) { + if (unlikely(limit++ >= MAX_REC_LOOP)) { net_notice_ratelimited("%s: packet reclassify loop rule prio %u protocol %02x\n", tp->q->ops->id, tp->prio & 0xffff, ntohs(tp->protocol)); return TC_ACT_SHOT; } - skb->tc_verd = SET_TC_VERD(skb->tc_verd, verd); goto reclassify; } #endif -- cgit v1.2.3 From dbc3976d9123a00925e3c9893b3f40f58f82636c Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 7 May 2015 23:43:26 -0700 Subject: clk: bindings: Fix assigned-clock-rates description The binding uses assigned-clock-parents when it should use assigned-clock-rates. Furthermore, the part that describes how they relate to the assigned-clocks property is not clear about what is related. Correct and clarify this part of the binding. Reported-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt index 06fc6d541c89..2ec489eebe72 100644 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -138,9 +138,10 @@ Some platforms may require initial configuration of default parent clocks and clock frequencies. Such a configuration can be specified in a device tree node through assigned-clocks, assigned-clock-parents and assigned-clock-rates properties. The assigned-clock-parents property should contain a list of parent -clocks in form of phandle and clock specifier pairs, the assigned-clock-parents -property the list of assigned clock frequency values - corresponding to clocks -listed in the assigned-clocks property. +clocks in the form of a phandle and clock specifier pair and the +assigned-clock-rates property should contain a list of frequencies in Hz. Both +these properties should correspond to the clocks listed in the assigned-clocks +property. To skip setting parent or rate of a clock its corresponding entry should be set to 0, or can be omitted if it is not followed by any non-zero entry. -- cgit v1.2.3 From 42801ca46719b189d4090b76268e6db90fc01e3c Mon Sep 17 00:00:00 2001 From: Daniel Thompson Date: Mon, 11 May 2015 11:20:06 +0100 Subject: clk: Update docs after removal of clk-private.h Currently Documentation/clk.txt describes an obsolete techinique to statically define struct clk objects. This capability was removed by b09d6d991025("clk: remove clk-private.h") and is no longer supported. The documentation describing the feature should be removed. Signed-off-by: Daniel Thompson Cc: Jonathan Corbet Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Stephen Boyd --- Documentation/clk.txt | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) (limited to 'Documentation') diff --git a/Documentation/clk.txt b/Documentation/clk.txt index 0e4f90aa1c13..f463bdc37f88 100644 --- a/Documentation/clk.txt +++ b/Documentation/clk.txt @@ -230,30 +230,7 @@ clk_register(...) See the basic clock types in drivers/clk/clk-*.c for examples. - Part 5 - static initialization of clock data - -For platforms with many clocks (often numbering into the hundreds) it -may be desirable to statically initialize some clock data. This -presents a problem since the definition of struct clk should be hidden -from everyone except for the clock core in drivers/clk/clk.c. - -To get around this problem struct clk's definition is exposed in -include/linux/clk-private.h along with some macros for more easily -initializing instances of the basic clock types. These clocks must -still be initialized with the common clock framework via a call to -__clk_init. - -clk-private.h must NEVER be included by code which implements struct -clk_ops callbacks, nor must it be included by any logic which pokes -around inside of struct clk at run-time. To do so is a layering -violation. - -To better enforce this policy, always follow this simple rule: any -statically initialized clock data MUST be defined in a separate file -from the logic that implements its ops. Basically separate the logic -from the data and all is well. - - Part 6 - Disabling clock gating of unused clocks + Part 5 - Disabling clock gating of unused clocks Sometimes during development it can be useful to be able to bypass the default disabling of unused clocks. For example, if drivers aren't enabling @@ -264,7 +241,7 @@ are sorted out. To bypass this disabling, include "clk_ignore_unused" in the bootargs to the kernel. - Part 7 - Locking + Part 6 - Locking The common clock framework uses two global locks, the prepare lock and the enable lock. -- cgit v1.2.3 From 9b88798c8e2db5d146508fe3b299e352388b9a25 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 4 May 2015 19:39:50 +0200 Subject: Documentation/magic-number: Remove SCI_MAGIC The SCI_MAGIC define was removed in commit f8e53553f452dcbf ("serial: sh-sci: Kill off more unused defines."). Its last user was the old drivers/char sh-sci driver, which was removed in 2004. Signed-off-by: Geert Uytterhoeven Signed-off-by: Jonathan Corbet --- Documentation/magic-number.txt | 1 - Documentation/zh_CN/magic-number.txt | 1 - 2 files changed, 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/magic-number.txt b/Documentation/magic-number.txt index 4c8e142db2ef..d9af851a6f20 100644 --- a/Documentation/magic-number.txt +++ b/Documentation/magic-number.txt @@ -138,7 +138,6 @@ KMALLOC_MAGIC 0x87654321 snd_alloc_track sound/core/memory.c PWC_MAGIC 0x89DC10AB pwc_device drivers/usb/media/pwc.h NBD_REPLY_MAGIC 0x96744668 nbd_reply include/linux/nbd.h ENI155_MAGIC 0xa54b872d midway_eprom drivers/atm/eni.h -SCI_MAGIC 0xbabeface gs_port drivers/char/sh-sci.h CODA_MAGIC 0xC0DAC0DA coda_file_info fs/coda/coda_fs_i.h DPMEM_MAGIC 0xc0ffee11 gdt_pci_sram drivers/scsi/gdth.h YAM_MAGIC 0xF10A7654 yam_port drivers/net/hamradio/yam.c diff --git a/Documentation/zh_CN/magic-number.txt b/Documentation/zh_CN/magic-number.txt index dfb72a5c63e9..c2607a69a727 100644 --- a/Documentation/zh_CN/magic-number.txt +++ b/Documentation/zh_CN/magic-number.txt @@ -138,7 +138,6 @@ KMALLOC_MAGIC 0x87654321 snd_alloc_track sound/core/memory.c PWC_MAGIC 0x89DC10AB pwc_device drivers/usb/media/pwc.h NBD_REPLY_MAGIC 0x96744668 nbd_reply include/linux/nbd.h ENI155_MAGIC 0xa54b872d midway_eprom drivers/atm/eni.h -SCI_MAGIC 0xbabeface gs_port drivers/char/sh-sci.h CODA_MAGIC 0xC0DAC0DA coda_file_info include/linux/coda_fs_i.h DPMEM_MAGIC 0xc0ffee11 gdt_pci_sram drivers/scsi/gdth.h YAM_MAGIC 0xF10A7654 yam_port drivers/net/hamradio/yam.c -- cgit v1.2.3 From dd7e283308a162f2fe50dec25bb864b2dc3cde3f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 4 May 2015 19:39:51 +0200 Subject: Documentation/magic-number: Remove SCC_MAGIC The SCC_MAGIC define was removed in commit 1ec3ba93c5fad9dc ("Staging: remove drivers/char/scc.h as it should have gone a while ago"), while its actual last user was removed before in commit bb2a97e9ccd525dd ("Staging: delete generic_serial drivers"). Signed-off-by: Geert Uytterhoeven Signed-off-by: Jonathan Corbet --- Documentation/magic-number.txt | 1 - Documentation/zh_CN/magic-number.txt | 1 - 2 files changed, 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/magic-number.txt b/Documentation/magic-number.txt index d9af851a6f20..28befed9f610 100644 --- a/Documentation/magic-number.txt +++ b/Documentation/magic-number.txt @@ -116,7 +116,6 @@ COW_MAGIC 0x4f4f4f4d cow_header_v1 arch/um/drivers/ubd_user.c I810_CARD_MAGIC 0x5072696E i810_card sound/oss/i810_audio.c TRIDENT_CARD_MAGIC 0x5072696E trident_card sound/oss/trident.c ROUTER_MAGIC 0x524d4157 wan_device [in wanrouter.h pre 3.9] -SCC_MAGIC 0x52696368 gs_port drivers/char/scc.h SAVEKMSG_MAGIC1 0x53415645 savekmsg arch/*/amiga/config.c GDA_MAGIC 0x58464552 gda arch/mips/include/asm/sn/gda.h RED_MAGIC1 0x5a2cf071 (any) mm/slab.c diff --git a/Documentation/zh_CN/magic-number.txt b/Documentation/zh_CN/magic-number.txt index c2607a69a727..e9db693c0a23 100644 --- a/Documentation/zh_CN/magic-number.txt +++ b/Documentation/zh_CN/magic-number.txt @@ -116,7 +116,6 @@ COW_MAGIC 0x4f4f4f4d cow_header_v1 arch/um/drivers/ubd_user.c I810_CARD_MAGIC 0x5072696E i810_card sound/oss/i810_audio.c TRIDENT_CARD_MAGIC 0x5072696E trident_card sound/oss/trident.c ROUTER_MAGIC 0x524d4157 wan_device [in wanrouter.h pre 3.9] -SCC_MAGIC 0x52696368 gs_port drivers/char/scc.h SAVEKMSG_MAGIC1 0x53415645 savekmsg arch/*/amiga/config.c GDA_MAGIC 0x58464552 gda arch/mips/include/asm/sn/gda.h RED_MAGIC1 0x5a2cf071 (any) mm/slab.c -- cgit v1.2.3 From 8547aa131495b081ef3e5ada8bc726251e23d2e0 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Mon, 4 May 2015 19:48:54 +0200 Subject: Documentation: tracing: fix grammar 4a88d44ab17da ("tracing: Remove mentioning of legacy latency_trace file from documentation") changed a sentence to refer to only one file instead of two, but the sentence still uses "they". Fix it. Signed-off-by: Rabin Vincent Acked-by: Steven Rostedt Signed-off-by: Jonathan Corbet --- Documentation/trace/ftrace.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/trace/ftrace.txt b/Documentation/trace/ftrace.txt index 572ca923631a..7ddb1e319f84 100644 --- a/Documentation/trace/ftrace.txt +++ b/Documentation/trace/ftrace.txt @@ -108,8 +108,8 @@ of ftrace. Here is a list of some of the key files: data is read from this file, it is consumed, and will not be read again with a sequential read. The "trace" file is static, and if the tracer is not - adding more data,they will display the same - information every time they are read. + adding more data, it will display the same + information every time it is read. trace_options: -- cgit v1.2.3 From 6f1b5605f3d0b6325c69c2be288a93c5d5c294dc Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Thu, 29 Jan 2015 18:10:47 +0000 Subject: ARM: bcm2835: dt: Add vendor prefix for Raspberry Pi Since the prefix is already in use, we need to add it in the vendor list. Reviewed-by: Stephen Warren Acked-by: Rob Herring Signed-off-by: Stefan Wahren Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..3fc90ac4f801 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -159,6 +159,7 @@ radxa Radxa raidsonic RaidSonic Technology GmbH ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International +raspberrypi Raspberry Pi Foundation realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation ricoh Ricoh Co. Ltd. -- cgit v1.2.3 From 4c059b0b2b59b16c1d053b781056b7e934a36121 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Thu, 29 Jan 2015 18:10:48 +0000 Subject: ARM: bcm2835: dt: Add root properties for Raspberry Pi This patch adds root compatible properties for the following boards: - Raspberry Pi Model A - Raspberry Pi Model A+ - Raspberry Pi Model B - Raspberry Pi Model B (no P5) - Raspberry Pi Model B rev2 - Raspberry Pi Model B+ - Raspberry Pi Compute Module Reviewed-by: Stephen Warren Acked-by: Rob Herring Signed-off-by: Stefan Wahren Signed-off-by: Lee Jones --- .../devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 31 ++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index ac683480c486..c78576bb7729 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -1,8 +1,35 @@ Broadcom BCM2835 device tree bindings ------------------------------------------- -Boards with the BCM2835 SoC shall have the following properties: +Raspberry Pi Model A +Required root node properties: +compatible = "raspberrypi,model-a", "brcm,bcm2835"; -Required root node property: +Raspberry Pi Model A+ +Required root node properties: +compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; +Raspberry Pi Model B +Required root node properties: +compatible = "raspberrypi,model-b", "brcm,bcm2835"; + +Raspberry Pi Model B (no P5) +early model B with I2C0 rather than I2C1 routed to the expansion header +Required root node properties: +compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835"; + +Raspberry Pi Model B rev2 +Required root node properties: +compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; + +Raspberry Pi Model B+ +Required root node properties: +compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + +Raspberry Pi Compute Module +Required root node properties: +compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + +Generic BCM2835 board +Required root node properties: compatible = "brcm,bcm2835"; -- cgit v1.2.3 From ab6016e0c134c3a564e6750f5b246ba17ada4686 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 12 May 2015 10:33:25 -0700 Subject: of: mdio: Add a "broken-turn-around" property Some Ethernet PHY devices/switches may not properly release the MDIO bus during turn-around time, and fail to drive it low, which can be seen by some controllers as a read failure, while the data clocked in is still correct. Add a boolean property "broken-turn-around" which is parsed by the generic MDIO bus probing code and will set the corresponding bit in the MDIO bus phy_ignore_ta_mask bitmask for MDIO bus drivers to utilize that information. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/phy.txt | 3 +++ drivers/of/of_mdio.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 40831fbaff72..525e1658f2da 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt @@ -30,6 +30,9 @@ Optional Properties: - max-speed: Maximum PHY supported speed (10, 100, 1000...) +- broken-turn-around: If set, indicates the PHY device does not correctly + release the turn around line low at the end of a MDIO transaction. + Example: ethernet-phy@0 { diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c index 0c064485d1c2..fdc60db60829 100644 --- a/drivers/of/of_mdio.c +++ b/drivers/of/of_mdio.c @@ -68,6 +68,9 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *chi phy->irq = mdio->irq[addr]; } + if (of_property_read_bool(child, "broken-turn-around")) + mdio->phy_ignore_ta_mask |= 1 << addr; + /* Associate the OF node with the device structure so it * can be looked up later */ of_node_get(child); -- cgit v1.2.3 From 8cda4c3ad480a974324532b6dacc67b9c1deb207 Mon Sep 17 00:00:00 2001 From: Luke Dashjr Date: Thu, 14 May 2015 18:58:01 +0000 Subject: SubmittingPatches: Clarify requirements for patches directed toward stable I misunderstood this section as simply asking me to add an email Cc, and was unaware of the existence of Documentation/stable_kernel_rules.txt. Hopefully this clarification will help save maintainers and new/rare submitters time in the future. Signed-off-by: Luke Dashjr Signed-off-by: Jonathan Corbet --- Documentation/SubmittingPatches | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/SubmittingPatches b/Documentation/SubmittingPatches index b03a832a08e2..27e7e5edeca8 100644 --- a/Documentation/SubmittingPatches +++ b/Documentation/SubmittingPatches @@ -299,7 +299,9 @@ toward the stable maintainers by putting a line like this: Cc: stable@vger.kernel.org -into your patch. +into the sign-off area of your patch (note, NOT an email recipient). You +should also read Documentation/stable_kernel_rules.txt in addition to this +file. Note, however, that some subsystem maintainers want to come to their own conclusions on which patches should go to the stable trees. The networking -- cgit v1.2.3 From ef69449b1c06668c3f08ae6d147833cf52c6381c Mon Sep 17 00:00:00 2001 From: Dominik Brodowski Date: Thu, 14 May 2015 15:31:28 +0200 Subject: ACPI: fix kernel-parameters ordering in Documentation Signed-off-by: Dominik Brodowski Signed-off-by: Rafael J. Wysocki --- Documentation/kernel-parameters.txt | 62 ++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..7e0fe6f336ab 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -179,11 +179,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. See also Documentation/power/runtime_pm.txt, pci=noacpi - acpi_rsdp= [ACPI,EFI,KEXEC] - Pass the RSDP address to the kernel, mostly used - on machines running EFI runtime service to boot the - second kernel for kdump. - acpi_apic_instance= [ACPI, IOAPIC] Format: 2: use 2nd APIC table, if available @@ -197,6 +192,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted. (e.g. thinkpad_acpi, sony_acpi, etc.) instead of the ACPI video.ko driver. + acpica_no_return_repair [HW, ACPI] + Disable AML predefined validation mechanism + This mechanism can repair the evaluation result to make + the return objects more ACPI specification compliant. + This option is useful for developers to identify the + root cause of an AML interpreter issue when the issue + has something to do with the repair mechanism. + acpi.debug_layer= [HW,ACPI,ACPI_DEBUG] acpi.debug_level= [HW,ACPI,ACPI_DEBUG] Format: @@ -225,6 +228,22 @@ bytes respectively. Such letter suffixes can also be entirely omitted. unusable. The "log_buf_len" parameter may be useful if you need to capture more output. + acpi_enforce_resources= [ACPI] + { strict | lax | no } + Check for resource conflicts between native drivers + and ACPI OperationRegions (SystemIO and SystemMemory + only). IO ports and memory declared in ACPI might be + used by the ACPI subsystem in arbitrary AML code and + can interfere with legacy drivers. + strict (default): access to resources claimed by ACPI + is denied; legacy drivers trying to access reserved + resources will fail to bind to device using them. + lax: access to resources claimed by ACPI is allowed; + legacy drivers trying to access reserved resources + will bind successfully but a warning message is logged. + no: ACPI OperationRegions are not marked as reserved, + no further checks are performed. + acpi_force_table_verification [HW,ACPI] Enable table checksum verification during early stage. By default, this is disabled due to x86 early mapping @@ -253,6 +272,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. This feature is enabled by default. This option allows to turn off the feature. + acpi_no_memhotplug [ACPI] Disable memory hotplug. Useful for kdump + kernels. + acpi_no_static_ssdt [HW,ACPI] Disable installation of static SSDTs at early boot time By default, SSDTs contained in the RSDT/XSDT will be @@ -263,13 +285,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. dynamic table installation which will install SSDT tables to /sys/firmware/acpi/tables/dynamic. - acpica_no_return_repair [HW, ACPI] - Disable AML predefined validation mechanism - This mechanism can repair the evaluation result to make - the return objects more ACPI specification compliant. - This option is useful for developers to identify the - root cause of an AML interpreter issue when the issue - has something to do with the repair mechanism. + acpi_rsdp= [ACPI,EFI,KEXEC] + Pass the RSDP address to the kernel, mostly used + on machines running EFI runtime service to boot the + second kernel for kdump. acpi_os_name= [HW,ACPI] Tell ACPI BIOS the name of the OS Format: To spoof as Windows 98: ="Microsoft Windows" @@ -365,25 +384,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Use timer override. For some broken Nvidia NF5 boards that require a timer override, but don't have HPET - acpi_enforce_resources= [ACPI] - { strict | lax | no } - Check for resource conflicts between native drivers - and ACPI OperationRegions (SystemIO and SystemMemory - only). IO ports and memory declared in ACPI might be - used by the ACPI subsystem in arbitrary AML code and - can interfere with legacy drivers. - strict (default): access to resources claimed by ACPI - is denied; legacy drivers trying to access reserved - resources will fail to bind to device using them. - lax: access to resources claimed by ACPI is allowed; - legacy drivers trying to access reserved resources - will bind successfully but a warning message is logged. - no: ACPI OperationRegions are not marked as reserved, - no further checks are performed. - - acpi_no_memhotplug [ACPI] Disable memory hotplug. Useful for kdump - kernels. - add_efi_memmap [EFI; X86] Include EFI memory map in kernel's map of available physical RAM. -- cgit v1.2.3 From 4c12adad26f059fa207d6b07aa61f39bc459211b Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 9 Apr 2015 16:36:49 -0300 Subject: [media] dvb: Document FE_SCALE_DECIBEL units consistently In comments and in the documentation, the units of properties marked with the FE_SCALE_DECIBEL scale are specified in terms of 1/1000 dB or 0.0001 dB. This is inconsistent, however, as 1/1000 is 0.001, not 0.0001. Note that the v4l-utils divide the value by 1000 for the signal strength suggesting that the 1/1000 is correct. Settle on millidecibels, ie. 1/1000dB or 0.001dB. Signed-off-by: David Howells Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 4 ++-- include/uapi/linux/dvb/frontend.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 3018564ddfd9..7ddab2ba9b40 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -953,7 +953,7 @@ enum fe_interleaving { Possible scales for this metric are: FE_SCALE_NOT_AVAILABLE - it failed to measure it, or the measurement was not complete yet. - FE_SCALE_DECIBEL - signal strength is in 0.0001 dBm units, power measured in miliwatts. This value is generally negative. + FE_SCALE_DECIBEL - signal strength is in 0.001 dBm units, power measured in miliwatts. This value is generally negative. FE_SCALE_RELATIVE - The frontend provides a 0% to 100% measurement for power (actually, 0 to 65535). @@ -963,7 +963,7 @@ enum fe_interleaving { Possible scales for this metric are: FE_SCALE_NOT_AVAILABLE - it failed to measure it, or the measurement was not complete yet. - FE_SCALE_DECIBEL - Signal/Noise ratio is in 0.0001 dB units. + FE_SCALE_DECIBEL - Signal/Noise ratio is in 0.001 dB units. FE_SCALE_RELATIVE - The frontend provides a 0% to 100% measurement for Signal/Noise (actually, 0 to 65535). diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index c56d77c496a5..466f56997272 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -467,7 +467,7 @@ struct dtv_cmds_h { * @FE_SCALE_NOT_AVAILABLE: That QoS measure is not available. That * could indicate a temporary or a permanent * condition. - * @FE_SCALE_DECIBEL: The scale is measured in 0.0001 dB steps, typically + * @FE_SCALE_DECIBEL: The scale is measured in 0.001 dB steps, typically * used on signal measures. * @FE_SCALE_RELATIVE: The scale is a relative percentual measure, * ranging from 0 (0%) to 0xffff (100%). @@ -516,7 +516,7 @@ struct dtv_stats { __u8 scale; /* enum fecap_scale_params type */ union { __u64 uvalue; /* for counters and relative scales */ - __s64 svalue; /* for 0.0001 dB measures */ + __s64 svalue; /* for 0.001 dB measures */ }; } __attribute__ ((packed)); -- cgit v1.2.3 From 203bc643db59e2538e9a3f19be1636cdfd2bb2db Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 11 May 2015 08:29:30 -0400 Subject: update Documentation/filesystems/ regarding the follow_link/put_link changes Signed-off-by: Al Viro --- Documentation/filesystems/porting | 17 +++++++++++++++++ Documentation/filesystems/vfs.txt | 18 ++++++++++-------- 2 files changed, 27 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/porting b/Documentation/filesystems/porting index e69274de8d0c..3eae250254d5 100644 --- a/Documentation/filesystems/porting +++ b/Documentation/filesystems/porting @@ -483,3 +483,20 @@ in your dentry operations instead. -- [mandatory] ->aio_read/->aio_write are gone. Use ->read_iter/->write_iter. +--- +[recommended] + for embedded ("fast") symlinks just set inode->i_link to wherever the + symlink body is and use simple_follow_link() as ->follow_link(). +-- +[mandatory] + calling conventions for ->follow_link() have changed. Instead of returning + cookie and using nd_set_link() to store the body to traverse, we return + the body to traverse and store the cookie using explicit void ** argument. + nameidata isn't passed at all - nd_jump_link() doesn't need it and + nd_[gs]et_link() is gone. +-- +[mandatory] + calling conventions for ->put_link() have changed. It gets inode instead of + dentry, it does not get nameidata at all and it gets called only when cookie + is non-NULL. Note that link body isn't available anymore, so if you need it, + store it as cookie. diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index 542d9352d0f2..b403b29ef710 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -436,16 +436,18 @@ otherwise noted. follow_link: called by the VFS to follow a symbolic link to the inode it points to. Only required if you want to support - symbolic links. This method returns a void pointer cookie - that is passed to put_link(). + symbolic links. This method returns the symlink body + to traverse (and possibly resets the current position with + nd_jump_link()). If the body won't go away until the inode + is gone, nothing else is needed; if it needs to be otherwise + pinned, the data needed to release whatever we'd grabbed + is to be stored in void * variable passed by address to + follow_link() instance. put_link: called by the VFS to release resources allocated by - follow_link(). The cookie returned by follow_link() is passed - to this method as the last parameter. It is used by - filesystems such as NFS where page cache is not stable - (i.e. page that was installed when the symbolic link walk - started might not be in the page cache at the end of the - walk). + follow_link(). The cookie stored by follow_link() is passed + to this method as the last parameter; only called when + cookie isn't NULL. permission: called by the VFS to check for access rights on a POSIX-like filesystem. -- cgit v1.2.3 From 99ff6cf0e67ada025ba8054a055862383355ec0e Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Mon, 23 Mar 2015 13:37:38 +1100 Subject: Documentation: remove outdated information from automount-support.txt The guidelines for adding automount support to a filesystem in filesystems/automount-support.txt is out or date. filesystems/autofs4.txt contains more current text, so replace the out-of-date content with a reference to that. Signed-off-by: NeilBrown Signed-off-by: Al Viro --- Documentation/filesystems/automount-support.txt | 51 +++++++------------------ 1 file changed, 13 insertions(+), 38 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/automount-support.txt b/Documentation/filesystems/automount-support.txt index 7cac200e2a85..7eb762eb3136 100644 --- a/Documentation/filesystems/automount-support.txt +++ b/Documentation/filesystems/automount-support.txt @@ -1,41 +1,15 @@ -Support is available for filesystems that wish to do automounting support (such -as kAFS which can be found in fs/afs/). This facility includes allowing -in-kernel mounts to be performed and mountpoint degradation to be -requested. The latter can also be requested by userspace. +Support is available for filesystems that wish to do automounting +support (such as kAFS which can be found in fs/afs/ and NFS in +fs/nfs/). This facility includes allowing in-kernel mounts to be +performed and mountpoint degradation to be requested. The latter can +also be requested by userspace. ====================== IN-KERNEL AUTOMOUNTING ====================== -A filesystem can now mount another filesystem on one of its directories by the -following procedure: - - (1) Give the directory a follow_link() operation. - - When the directory is accessed, the follow_link op will be called, and - it will be provided with the location of the mountpoint in the nameidata - structure (vfsmount and dentry). - - (2) Have the follow_link() op do the following steps: - - (a) Call vfs_kern_mount() to call the appropriate filesystem to set up a - superblock and gain a vfsmount structure representing it. - - (b) Copy the nameidata provided as an argument and substitute the dentry - argument into it the copy. - - (c) Call do_add_mount() to install the new vfsmount into the namespace's - mountpoint tree, thus making it accessible to userspace. Use the - nameidata set up in (b) as the destination. - - If the mountpoint will be automatically expired, then do_add_mount() - should also be given the location of an expiration list (see further - down). - - (d) Release the path in the nameidata argument and substitute in the new - vfsmount and its root dentry. The ref counts on these will need - incrementing. +See section "Mount Traps" of Documentation/filesystems/autofs4.txt Then from userspace, you can just do something like: @@ -61,17 +35,18 @@ AUTOMATIC MOUNTPOINT EXPIRY =========================== Automatic expiration of mountpoints is easy, provided you've mounted the -mountpoint to be expired in the automounting procedure outlined above. +mountpoint to be expired in the automounting procedure outlined separately. To do expiration, you need to follow these steps: - (3) Create at least one list off which the vfsmounts to be expired can be - hung. Access to this list will be governed by the vfsmount_lock. + (1) Create at least one list off which the vfsmounts to be expired can be + hung. - (4) In step (2c) above, the call to do_add_mount() should be provided with a - pointer to this list. It will hang the vfsmount off of it if it succeeds. + (2) When a new mountpoint is created in the ->d_automount method, add + the mnt to the list using mnt_set_expiry() + mnt_set_expiry(newmnt, &afs_vfsmounts); - (5) When you want mountpoints to be expired, call mark_mounts_for_expiry() + (3) When you want mountpoints to be expired, call mark_mounts_for_expiry() with a pointer to this list. This will process the list, marking every vfsmount thereon for potential expiry on the next call. -- cgit v1.2.3 From f8cff12b6fb62ef124bc1e06502d987c6da71731 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 14 May 2015 12:10:57 +0200 Subject: doc: dt: add documentation for nxp,lpc1850-dwmac Add device tree binding documentation for nxp,lpc1850-dwmac. Signed-off-by: Joachim Eastwood Signed-off-by: David S. Miller --- .../devicetree/bindings/net/nxp,lpc1850-dwmac.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt new file mode 100644 index 000000000000..7edba1264f6f --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.txt @@ -0,0 +1,20 @@ +* NXP LPC1850 GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: + - compatible: Should contain "nxp,lpc1850-dwmac" + +Examples: + +mac: ethernet@40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + resets = <&rgu 22>; + reset-names = "stmmaceth"; +} -- cgit v1.2.3 From 13696e0a735d0ae2d1fc16ff7e607aafdc5896a6 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Sat, 16 May 2015 02:16:43 +0900 Subject: Doc: Fix description of nomce in kernel-parameters.txt Description of nomce tells opposite. Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/kernel-parameters.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..e9159eb986ec 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2437,7 +2437,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. nomca [IA-64] Disable machine check abort handling - nomce [X86-32] Machine Check Exception + nomce [X86-32] Disable Machine Check Exception nomfgpt [X86-32] Disable Multi-Function General Purpose Timer usage (for AMD Geode machines). -- cgit v1.2.3 From 7c12aa08779cfa8e0a64943bd6d823c5c110766b Mon Sep 17 00:00:00 2001 From: "Lendacky, Thomas" Date: Thu, 14 May 2015 11:44:15 -0500 Subject: amd-xgbe: Move the PHY support into amd-xgbe The AMD XGBE device is intended to work with a specific integrated PHY and that PHY is not meant to be a standalone PHY for use by other devices. As such this patch removes the phylib driver and implements the PHY support in the amd-xgbe driver (the majority of the logic from the phylib driver is moved into the amd-xgbe driver). Update the driver version to 1.0.1. Signed-off-by: Tom Lendacky Signed-off-by: David S. Miller --- .../devicetree/bindings/net/amd-xgbe-phy.txt | 48 - Documentation/devicetree/bindings/net/amd-xgbe.txt | 51 +- MAINTAINERS | 1 - drivers/net/ethernet/amd/Kconfig | 4 +- drivers/net/ethernet/amd/xgbe/xgbe-common.h | 155 ++ drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 17 - drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 176 +- drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c | 50 +- drivers/net/ethernet/amd/xgbe/xgbe-main.c | 360 +++- drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 1165 ++++++++++-- drivers/net/ethernet/amd/xgbe/xgbe.h | 205 ++- drivers/net/phy/Kconfig | 7 - drivers/net/phy/Makefile | 1 - drivers/net/phy/amd-xgbe-phy.c | 1862 -------------------- 14 files changed, 1828 insertions(+), 2274 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/amd-xgbe-phy.txt delete mode 100644 drivers/net/phy/amd-xgbe-phy.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt b/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt deleted file mode 100644 index 8db32384a486..000000000000 --- a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt +++ /dev/null @@ -1,48 +0,0 @@ -* AMD 10GbE PHY driver (amd-xgbe-phy) - -Required properties: -- compatible: Should be "amd,xgbe-phy-seattle-v1a" and - "ethernet-phy-ieee802.3-c45" -- reg: Address and length of the register sets for the device - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device -- interrupts: Should contain the amd-xgbe-phy interrupt. - -Optional properties: -- amd,speed-set: Speed capabilities of the device - 0 - 1GbE and 10GbE (default) - 1 - 2.5GbE and 10GbE - -The following optional properties are represented by an array with each -value corresponding to a particular speed. The first array value represents -the setting for the 1GbE speed, the second value for the 2.5GbE speed and -the third value for the 10GbE speed. All three values are required if the -property is used. -- amd,serdes-blwc: Baseline wandering correction enablement - 0 - Off - 1 - On -- amd,serdes-cdr-rate: CDR rate speed selection -- amd,serdes-pq-skew: PQ (data sampling) skew -- amd,serdes-tx-amp: TX amplitude boost -- amd,serdes-dfe-tap-config: DFE taps available to run -- amd,serdes-dfe-tap-enable: DFE taps to enable - -Example: - xgbe_phy@e1240800 { - compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45"; - reg = <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 323 4>; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <30>; - amd,serdes-tx-amp = <15>, <15>, <10>; - amd,serdes-dfe-tap-config = <3>, <3>, <1>; - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; - }; diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt index 26efd526d16c..5dbc55a2db90 100644 --- a/Documentation/devicetree/bindings/net/amd-xgbe.txt +++ b/Documentation/devicetree/bindings/net/amd-xgbe.txt @@ -1,6 +1,6 @@ * AMD 10GbE driver (amd-xgbe) -Required properties: +Required properties (ethernet device): - compatible: Should be "amd,xgbe-seattle-v1a" - reg: Address and length of the register sets for the device - MAC registers @@ -22,7 +22,7 @@ Required properties: - phy-handle: See ethernet.txt file in the same directory - phy-mode: See ethernet.txt file in the same directory -Optional properties: +Optional properties (ethernet device): - mac-address: mac address to be assigned to the device. Can be overridden by UEFI. - dma-coherent: Present if dma operations are coherent @@ -30,6 +30,35 @@ Optional properties: a unique interrupt for each DMA channel - this requires an additional interrupt be configured for each DMA channel +Required properties (phy device): +- compatible: Should be "amd,xgbe-phy-seattle-v1a" +- reg: Address and length of the register sets for the device + - SerDes Rx/Tx registers + - SerDes integration registers (1/2) + - SerDes integration registers (2/2) +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupts: Should contain the amd-xgbe-phy interrupt. + +Optional properties (phy device): +- amd,speed-set: Speed capabilities of the device + 0 - 1GbE and 10GbE (default) + 1 - 2.5GbE and 10GbE + +The following optional properties are represented by an array with each +value corresponding to a particular speed. The first array value represents +the setting for the 1GbE speed, the second value for the 2.5GbE speed and +the third value for the 10GbE speed. All three values are required if the +property is used. +- amd,serdes-blwc: Baseline wandering correction enablement + 0 - Off + 1 - On +- amd,serdes-cdr-rate: CDR rate speed selection +- amd,serdes-pq-skew: PQ (data sampling) skew +- amd,serdes-tx-amp: TX amplitude boost +- amd,serdes-dfe-tap-config: DFE taps available to run +- amd,serdes-dfe-tap-enable: DFE taps to enable + Example: xgbe@e0700000 { compatible = "amd,xgbe-seattle-v1a"; @@ -41,7 +70,23 @@ Example: amd,per-channel-interrupt; clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; clock-names = "dma_clk", "ptp_clk"; - phy-handle = <&phy>; + phy-handle = <&xgbe_phy>; phy-mode = "xgmii"; mac-address = [ 02 a1 a2 a3 a4 a5 ]; }; + + xgbe_phy@e1240800 { + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0 0xe1240800 0 0x00400>, + <0 0xe1250000 0 0x00060>, + <0 0xe1250080 0 0x00004>; + interrupt-parent = <&gic>; + interrupts = <0 323 4>; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <30>; + amd,serdes-tx-amp = <15>, <15>, <10>; + amd,serdes-dfe-tap-config = <3>, <3>, <1>; + amd,serdes-dfe-tap-enable = <0>, <0>, <127>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5d87ccbee19b..38abdb270111 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -652,7 +652,6 @@ M: Tom Lendacky L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/amd/xgbe/ -F: drivers/net/phy/amd-xgbe-phy.c AMS (Apple Motion Sensor) DRIVER M: Michael Hanselmann diff --git a/drivers/net/ethernet/amd/Kconfig b/drivers/net/ethernet/amd/Kconfig index 426916036151..acd53173fcc0 100644 --- a/drivers/net/ethernet/amd/Kconfig +++ b/drivers/net/ethernet/amd/Kconfig @@ -179,10 +179,8 @@ config SUNLANCE config AMD_XGBE tristate "AMD 10GbE Ethernet driver" - depends on (OF_NET || ACPI) && HAS_IOMEM && HAS_DMA + depends on ((OF_NET && OF_ADDRESS) || ACPI) && HAS_IOMEM && HAS_DMA depends on ARM64 || COMPILE_TEST - select PHYLIB - select AMD_XGBE_PHY select BITREVERSE select CRC32 select PTP_1588_CLOCK diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h index 34c28aac767f..b6fa89102526 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h @@ -857,6 +857,48 @@ */ #define PCS_MMD_SELECT 0xff +/* SerDes integration register offsets */ +#define SIR0_KR_RT_1 0x002c +#define SIR0_STATUS 0x0040 +#define SIR1_SPEED 0x0000 + +/* SerDes integration register entry bit positions and sizes */ +#define SIR0_KR_RT_1_RESET_INDEX 11 +#define SIR0_KR_RT_1_RESET_WIDTH 1 +#define SIR0_STATUS_RX_READY_INDEX 0 +#define SIR0_STATUS_RX_READY_WIDTH 1 +#define SIR0_STATUS_TX_READY_INDEX 8 +#define SIR0_STATUS_TX_READY_WIDTH 1 +#define SIR1_SPEED_CDR_RATE_INDEX 12 +#define SIR1_SPEED_CDR_RATE_WIDTH 4 +#define SIR1_SPEED_DATARATE_INDEX 4 +#define SIR1_SPEED_DATARATE_WIDTH 2 +#define SIR1_SPEED_PLLSEL_INDEX 3 +#define SIR1_SPEED_PLLSEL_WIDTH 1 +#define SIR1_SPEED_RATECHANGE_INDEX 6 +#define SIR1_SPEED_RATECHANGE_WIDTH 1 +#define SIR1_SPEED_TXAMP_INDEX 8 +#define SIR1_SPEED_TXAMP_WIDTH 4 +#define SIR1_SPEED_WORDMODE_INDEX 0 +#define SIR1_SPEED_WORDMODE_WIDTH 3 + +/* SerDes RxTx register offsets */ +#define RXTX_REG6 0x0018 +#define RXTX_REG20 0x0050 +#define RXTX_REG22 0x0058 +#define RXTX_REG114 0x01c8 +#define RXTX_REG129 0x0204 + +/* SerDes RxTx register entry bit positions and sizes */ +#define RXTX_REG6_RESETB_RXD_INDEX 8 +#define RXTX_REG6_RESETB_RXD_WIDTH 1 +#define RXTX_REG20_BLWC_ENA_INDEX 2 +#define RXTX_REG20_BLWC_ENA_WIDTH 1 +#define RXTX_REG114_PQ_REG_INDEX 9 +#define RXTX_REG114_PQ_REG_WIDTH 7 +#define RXTX_REG129_RXDFE_CONFIG_INDEX 14 +#define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 + /* Descriptor/Packet entry bit positions and sizes */ #define RX_PACKET_ERRORS_CRC_INDEX 2 #define RX_PACKET_ERRORS_CRC_WIDTH 1 @@ -973,10 +1015,47 @@ #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 /* MDIO undefined or vendor specific registers */ +#ifndef MDIO_PMA_10GBR_PMD_CTRL +#define MDIO_PMA_10GBR_PMD_CTRL 0x0096 +#endif + +#ifndef MDIO_PMA_10GBR_FECCTRL +#define MDIO_PMA_10GBR_FECCTRL 0x00ab +#endif + +#ifndef MDIO_AN_XNP +#define MDIO_AN_XNP 0x0016 +#endif + +#ifndef MDIO_AN_LPX +#define MDIO_AN_LPX 0x0019 +#endif + #ifndef MDIO_AN_COMP_STAT #define MDIO_AN_COMP_STAT 0x0030 #endif +#ifndef MDIO_AN_INTMASK +#define MDIO_AN_INTMASK 0x8001 +#endif + +#ifndef MDIO_AN_INT +#define MDIO_AN_INT 0x8002 +#endif + +#ifndef MDIO_CTRL1_SPEED1G +#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) +#endif + +/* MDIO mask values */ +#define XGBE_XNP_MCF_NULL_MESSAGE 0x001 +#define XGBE_XNP_ACK_PROCESSED BIT(12) +#define XGBE_XNP_MP_FORMATTED BIT(13) +#define XGBE_XNP_NP_EXCHANGE BIT(15) + +#define XGBE_KR_TRAINING_START BIT(0) +#define XGBE_KR_TRAINING_ENABLE BIT(1) + /* Bit setting and getting macros * The get macro will extract the current bit field value from within * the variable @@ -1118,6 +1197,82 @@ do { \ #define XPCS_IOREAD(_pdata, _off) \ ioread32((_pdata)->xpcs_regs + (_off)) +/* Macros for building, reading or writing register values or bits + * within the register values of SerDes integration registers. + */ +#define XSIR_GET_BITS(_var, _prefix, _field) \ + GET_BITS((_var), \ + _prefix##_##_field##_INDEX, \ + _prefix##_##_field##_WIDTH) + +#define XSIR_SET_BITS(_var, _prefix, _field, _val) \ + SET_BITS((_var), \ + _prefix##_##_field##_INDEX, \ + _prefix##_##_field##_WIDTH, (_val)) + +#define XSIR0_IOREAD(_pdata, _reg) \ + ioread16((_pdata)->sir0_regs + _reg) + +#define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ + GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ + _reg##_##_field##_INDEX, \ + _reg##_##_field##_WIDTH) + +#define XSIR0_IOWRITE(_pdata, _reg, _val) \ + iowrite16((_val), (_pdata)->sir0_regs + _reg) + +#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ +do { \ + u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ + SET_BITS(reg_val, \ + _reg##_##_field##_INDEX, \ + _reg##_##_field##_WIDTH, (_val)); \ + XSIR0_IOWRITE((_pdata), _reg, reg_val); \ +} while (0) + +#define XSIR1_IOREAD(_pdata, _reg) \ + ioread16((_pdata)->sir1_regs + _reg) + +#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ + GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ + _reg##_##_field##_INDEX, \ + _reg##_##_field##_WIDTH) + +#define XSIR1_IOWRITE(_pdata, _reg, _val) \ + iowrite16((_val), (_pdata)->sir1_regs + _reg) + +#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ +do { \ + u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ + SET_BITS(reg_val, \ + _reg##_##_field##_INDEX, \ + _reg##_##_field##_WIDTH, (_val)); \ + XSIR1_IOWRITE((_pdata), _reg, reg_val); \ +} while (0) + +/* Macros for building, reading or writing register values or bits + * within the register values of SerDes RxTx registers. + */ +#define XRXTX_IOREAD(_pdata, _reg) \ + ioread16((_pdata)->rxtx_regs + _reg) + +#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ + GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ + _reg##_##_field##_INDEX, \ + _reg##_##_field##_WIDTH) + +#define XRXTX_IOWRITE(_pdata, _reg, _val) \ + iowrite16((_val), (_pdata)->rxtx_regs + _reg) + +#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ +do { \ + u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ + SET_BITS(reg_val, \ + _reg##_##_field##_INDEX, \ + _reg##_##_field##_WIDTH, (_val)); \ + XRXTX_IOWRITE((_pdata), _reg, reg_val); \ +} while (0) + /* Macros for building, reading or writing register values or bits * using MDIO. Different from above because of the use of standardized * Linux include values. No shifting is performed with the bit diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c index dab3a1ed566b..506e832c9e9a 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c @@ -910,23 +910,6 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, else mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); - /* If the PCS is changing modes, match the MAC speed to it */ - if (((mmd_address >> 16) == MDIO_MMD_PCS) && - ((mmd_address & 0xffff) == MDIO_CTRL2)) { - struct phy_device *phydev = pdata->phydev; - - if (mmd_data & MDIO_PCS_CTRL2_TYPE) { - /* KX mode */ - if (phydev->supported & SUPPORTED_1000baseKX_Full) - xgbe_set_gmii_speed(pdata); - else - xgbe_set_gmii_2500_speed(pdata); - } else { - /* KR mode */ - xgbe_set_xgmii_speed(pdata); - } - } - /* The PCS registers are accessed using mmio. The underlying APB3 * management interface uses indirect addressing to access the MMD * register sets. This requires accessing of the PCS register in two diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c index f0fbe3386951..401703fc7b4f 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c @@ -437,12 +437,31 @@ static void xgbe_tx_timer(unsigned long data) DBGPR("<--xgbe_tx_timer\n"); } -static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata) +static void xgbe_service(struct work_struct *work) +{ + struct xgbe_prv_data *pdata = container_of(work, + struct xgbe_prv_data, + service_work); + + pdata->phy_if.phy_status(pdata); +} + +static void xgbe_service_timer(unsigned long data) +{ + struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; + + schedule_work(&pdata->service_work); + + mod_timer(&pdata->service_timer, jiffies + HZ); +} + +static void xgbe_init_timers(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; - DBGPR("-->xgbe_init_tx_timers\n"); + setup_timer(&pdata->service_timer, xgbe_service_timer, + (unsigned long)pdata); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { @@ -452,16 +471,19 @@ static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata) setup_timer(&channel->tx_timer, xgbe_tx_timer, (unsigned long)channel); } +} - DBGPR("<--xgbe_init_tx_timers\n"); +static void xgbe_start_timers(struct xgbe_prv_data *pdata) +{ + mod_timer(&pdata->service_timer, jiffies + HZ); } -static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata) +static void xgbe_stop_timers(struct xgbe_prv_data *pdata) { struct xgbe_channel *channel; unsigned int i; - DBGPR("-->xgbe_stop_tx_timers\n"); + del_timer_sync(&pdata->service_timer); channel = pdata->channel; for (i = 0; i < pdata->channel_count; i++, channel++) { @@ -470,8 +492,6 @@ static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata) del_timer_sync(&channel->tx_timer); } - - DBGPR("<--xgbe_stop_tx_timers\n"); } void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) @@ -758,113 +778,14 @@ static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) DBGPR("<--xgbe_free_rx_data\n"); } -static void xgbe_adjust_link(struct net_device *netdev) -{ - struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct xgbe_hw_if *hw_if = &pdata->hw_if; - struct phy_device *phydev = pdata->phydev; - int new_state = 0; - - if (!phydev) - return; - - if (phydev->link) { - /* Flow control support */ - if (pdata->pause_autoneg) { - if (phydev->pause || phydev->asym_pause) { - pdata->tx_pause = 1; - pdata->rx_pause = 1; - } else { - pdata->tx_pause = 0; - pdata->rx_pause = 0; - } - } - - if (pdata->tx_pause != pdata->phy_tx_pause) { - hw_if->config_tx_flow_control(pdata); - pdata->phy_tx_pause = pdata->tx_pause; - } - - if (pdata->rx_pause != pdata->phy_rx_pause) { - hw_if->config_rx_flow_control(pdata); - pdata->phy_rx_pause = pdata->rx_pause; - } - - /* Speed support */ - if (phydev->speed != pdata->phy_speed) { - new_state = 1; - - switch (phydev->speed) { - case SPEED_10000: - hw_if->set_xgmii_speed(pdata); - break; - - case SPEED_2500: - hw_if->set_gmii_2500_speed(pdata); - break; - - case SPEED_1000: - hw_if->set_gmii_speed(pdata); - break; - } - pdata->phy_speed = phydev->speed; - } - - if (phydev->link != pdata->phy_link) { - new_state = 1; - pdata->phy_link = 1; - } - } else if (pdata->phy_link) { - new_state = 1; - pdata->phy_link = 0; - pdata->phy_speed = SPEED_UNKNOWN; - } - - if (new_state) - phy_print_status(phydev); -} - static int xgbe_phy_init(struct xgbe_prv_data *pdata) { - struct net_device *netdev = pdata->netdev; - struct phy_device *phydev = pdata->phydev; - int ret; - pdata->phy_link = -1; pdata->phy_speed = SPEED_UNKNOWN; pdata->phy_tx_pause = pdata->tx_pause; pdata->phy_rx_pause = pdata->rx_pause; - ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link, - pdata->phy_mode); - if (ret) { - netdev_err(netdev, "phy_connect_direct failed\n"); - return ret; - } - - if (!phydev->drv || (phydev->drv->phy_id == 0)) { - netdev_err(netdev, "phy_id not valid\n"); - ret = -ENODEV; - goto err_phy_connect; - } - netif_dbg(pdata, ifup, pdata->netdev, - "phy_connect_direct succeeded for PHY %s\n", - dev_name(&phydev->dev)); - - return 0; - -err_phy_connect: - phy_disconnect(phydev); - - return ret; -} - -static void xgbe_phy_exit(struct xgbe_prv_data *pdata) -{ - if (!pdata->phydev) - return; - - phy_disconnect(pdata->phydev); + return pdata->phy_if.phy_reset(pdata); } int xgbe_powerdown(struct net_device *netdev, unsigned int caller) @@ -889,13 +810,14 @@ int xgbe_powerdown(struct net_device *netdev, unsigned int caller) netif_tx_stop_all_queues(netdev); + xgbe_stop_timers(pdata); + flush_workqueue(pdata->dev_workqueue); + hw_if->powerdown_tx(pdata); hw_if->powerdown_rx(pdata); xgbe_napi_disable(pdata, 0); - phy_stop(pdata->phydev); - pdata->power_down = 1; spin_unlock_irqrestore(&pdata->lock, flags); @@ -924,8 +846,6 @@ int xgbe_powerup(struct net_device *netdev, unsigned int caller) pdata->power_down = 0; - phy_start(pdata->phydev); - xgbe_napi_enable(pdata, 0); hw_if->powerup_tx(pdata); @@ -936,6 +856,8 @@ int xgbe_powerup(struct net_device *netdev, unsigned int caller) netif_tx_start_all_queues(netdev); + xgbe_start_timers(pdata); + spin_unlock_irqrestore(&pdata->lock, flags); DBGPR("<--xgbe_powerup\n"); @@ -946,6 +868,7 @@ int xgbe_powerup(struct net_device *netdev, unsigned int caller) static int xgbe_start(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; + struct xgbe_phy_if *phy_if = &pdata->phy_if; struct net_device *netdev = pdata->netdev; int ret; @@ -953,7 +876,9 @@ static int xgbe_start(struct xgbe_prv_data *pdata) hw_if->init(pdata); - phy_start(pdata->phydev); + ret = phy_if->phy_start(pdata); + if (ret) + goto err_phy; xgbe_napi_enable(pdata, 1); @@ -964,10 +889,11 @@ static int xgbe_start(struct xgbe_prv_data *pdata) hw_if->enable_tx(pdata); hw_if->enable_rx(pdata); - xgbe_init_tx_timers(pdata); - netif_tx_start_all_queues(netdev); + xgbe_start_timers(pdata); + schedule_work(&pdata->service_work); + DBGPR("<--xgbe_start\n"); return 0; @@ -975,8 +901,9 @@ static int xgbe_start(struct xgbe_prv_data *pdata) err_napi: xgbe_napi_disable(pdata, 1); - phy_stop(pdata->phydev); + phy_if->phy_stop(pdata); +err_phy: hw_if->exit(pdata); return ret; @@ -985,6 +912,7 @@ err_napi: static void xgbe_stop(struct xgbe_prv_data *pdata) { struct xgbe_hw_if *hw_if = &pdata->hw_if; + struct xgbe_phy_if *phy_if = &pdata->phy_if; struct xgbe_channel *channel; struct net_device *netdev = pdata->netdev; struct netdev_queue *txq; @@ -994,7 +922,8 @@ static void xgbe_stop(struct xgbe_prv_data *pdata) netif_tx_stop_all_queues(netdev); - xgbe_stop_tx_timers(pdata); + xgbe_stop_timers(pdata); + flush_workqueue(pdata->dev_workqueue); hw_if->disable_tx(pdata); hw_if->disable_rx(pdata); @@ -1003,7 +932,7 @@ static void xgbe_stop(struct xgbe_prv_data *pdata) xgbe_napi_disable(pdata, 1); - phy_stop(pdata->phydev); + phy_if->phy_stop(pdata); hw_if->exit(pdata); @@ -1374,7 +1303,7 @@ static int xgbe_open(struct net_device *netdev) ret = clk_prepare_enable(pdata->sysclk); if (ret) { netdev_alert(netdev, "dma clk_prepare_enable failed\n"); - goto err_phy_init; + return ret; } ret = clk_prepare_enable(pdata->ptpclk); @@ -1399,14 +1328,17 @@ static int xgbe_open(struct net_device *netdev) if (ret) goto err_channels; - /* Initialize the device restart and Tx timestamp work struct */ + INIT_WORK(&pdata->service_work, xgbe_service); INIT_WORK(&pdata->restart_work, xgbe_restart); INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); + xgbe_init_timers(pdata); ret = xgbe_start(pdata); if (ret) goto err_rings; + clear_bit(XGBE_DOWN, &pdata->dev_state); + DBGPR("<--xgbe_open\n"); return 0; @@ -1423,9 +1355,6 @@ err_ptpclk: err_sysclk: clk_disable_unprepare(pdata->sysclk); -err_phy_init: - xgbe_phy_exit(pdata); - return ret; } @@ -1449,8 +1378,7 @@ static int xgbe_close(struct net_device *netdev) clk_disable_unprepare(pdata->ptpclk); clk_disable_unprepare(pdata->sysclk); - /* Release the phy */ - xgbe_phy_exit(pdata); + set_bit(XGBE_DOWN, &pdata->dev_state); DBGPR("<--xgbe_close\n"); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c index 95baa866c841..b24a78c39800 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c @@ -258,7 +258,6 @@ static int xgbe_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct phy_device *phydev = pdata->phydev; int ret = 0; DBGPR("-->xgbe_set_pauseparam\n"); @@ -268,19 +267,19 @@ static int xgbe_set_pauseparam(struct net_device *netdev, pdata->pause_autoneg = pause->autoneg; if (pause->autoneg) { - phydev->advertising |= ADVERTISED_Pause; - phydev->advertising |= ADVERTISED_Asym_Pause; + pdata->phy.advertising |= ADVERTISED_Pause; + pdata->phy.advertising |= ADVERTISED_Asym_Pause; } else { - phydev->advertising &= ~ADVERTISED_Pause; - phydev->advertising &= ~ADVERTISED_Asym_Pause; + pdata->phy.advertising &= ~ADVERTISED_Pause; + pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; pdata->tx_pause = pause->tx_pause; pdata->rx_pause = pause->rx_pause; } if (netif_running(netdev)) - ret = phy_start_aneg(phydev); + ret = pdata->phy_if.phy_config_aneg(pdata); DBGPR("<--xgbe_set_pauseparam\n"); @@ -291,36 +290,39 @@ static int xgbe_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) { struct xgbe_prv_data *pdata = netdev_priv(netdev); - int ret; DBGPR("-->xgbe_get_settings\n"); - if (!pdata->phydev) - return -ENODEV; + cmd->phy_address = pdata->phy.address; + + cmd->supported = pdata->phy.supported; + cmd->advertising = pdata->phy.advertising; + cmd->lp_advertising = pdata->phy.lp_advertising; + + cmd->autoneg = pdata->phy.autoneg; + ethtool_cmd_speed_set(cmd, pdata->phy.speed); + cmd->duplex = pdata->phy.duplex; - ret = phy_ethtool_gset(pdata->phydev, cmd); + cmd->port = PORT_NONE; + cmd->transceiver = XCVR_INTERNAL; DBGPR("<--xgbe_get_settings\n"); - return ret; + return 0; } static int xgbe_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd) { struct xgbe_prv_data *pdata = netdev_priv(netdev); - struct phy_device *phydev = pdata->phydev; u32 speed; int ret; DBGPR("-->xgbe_set_settings\n"); - if (!pdata->phydev) - return -ENODEV; - speed = ethtool_cmd_speed(cmd); - if (cmd->phy_address != phydev->addr) + if (cmd->phy_address != pdata->phy.address) return -EINVAL; if ((cmd->autoneg != AUTONEG_ENABLE) && @@ -341,23 +343,23 @@ static int xgbe_set_settings(struct net_device *netdev, return -EINVAL; } - cmd->advertising &= phydev->supported; + cmd->advertising &= pdata->phy.supported; if ((cmd->autoneg == AUTONEG_ENABLE) && !cmd->advertising) return -EINVAL; ret = 0; - phydev->autoneg = cmd->autoneg; - phydev->speed = speed; - phydev->duplex = cmd->duplex; - phydev->advertising = cmd->advertising; + pdata->phy.autoneg = cmd->autoneg; + pdata->phy.speed = speed; + pdata->phy.duplex = cmd->duplex; + pdata->phy.advertising = cmd->advertising; if (cmd->autoneg == AUTONEG_ENABLE) - phydev->advertising |= ADVERTISED_Autoneg; + pdata->phy.advertising |= ADVERTISED_Autoneg; else - phydev->advertising &= ~ADVERTISED_Autoneg; + pdata->phy.advertising &= ~ADVERTISED_Autoneg; if (netif_running(netdev)) - ret = phy_start_aneg(phydev); + ret = pdata->phy_if.phy_config_aneg(pdata); DBGPR("<--xgbe_set_settings\n"); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c index ae869d41cec8..0c219b30c129 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c @@ -124,9 +124,11 @@ #include #include #include +#include #include #include #include +#include #include "xgbe.h" #include "xgbe-common.h" @@ -143,6 +145,42 @@ MODULE_PARM_DESC(debug, " Network interface message level setting"); static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP); +static const u32 xgbe_serdes_blwc[] = { + XGBE_SPEED_1000_BLWC, + XGBE_SPEED_2500_BLWC, + XGBE_SPEED_10000_BLWC, +}; + +static const u32 xgbe_serdes_cdr_rate[] = { + XGBE_SPEED_1000_CDR, + XGBE_SPEED_2500_CDR, + XGBE_SPEED_10000_CDR, +}; + +static const u32 xgbe_serdes_pq_skew[] = { + XGBE_SPEED_1000_PQ, + XGBE_SPEED_2500_PQ, + XGBE_SPEED_10000_PQ, +}; + +static const u32 xgbe_serdes_tx_amp[] = { + XGBE_SPEED_1000_TXAMP, + XGBE_SPEED_2500_TXAMP, + XGBE_SPEED_10000_TXAMP, +}; + +static const u32 xgbe_serdes_dfe_tap_cfg[] = { + XGBE_SPEED_1000_DFE_TAP_CONFIG, + XGBE_SPEED_2500_DFE_TAP_CONFIG, + XGBE_SPEED_10000_DFE_TAP_CONFIG, +}; + +static const u32 xgbe_serdes_dfe_tap_ena[] = { + XGBE_SPEED_1000_DFE_TAP_ENABLE, + XGBE_SPEED_2500_DFE_TAP_ENABLE, + XGBE_SPEED_10000_DFE_TAP_ENABLE, +}; + static void xgbe_default_config(struct xgbe_prv_data *pdata) { DBGPR("-->xgbe_default_config\n"); @@ -160,8 +198,6 @@ static void xgbe_default_config(struct xgbe_prv_data *pdata) pdata->rx_pause = 1; pdata->phy_speed = SPEED_UNKNOWN; pdata->power_down = 0; - pdata->default_autoneg = AUTONEG_ENABLE; - pdata->default_speed = SPEED_10000; DBGPR("<--xgbe_default_config\n"); } @@ -169,6 +205,7 @@ static void xgbe_default_config(struct xgbe_prv_data *pdata) static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata) { xgbe_init_function_ptrs_dev(&pdata->hw_if); + xgbe_init_function_ptrs_phy(&pdata->phy_if); xgbe_init_function_ptrs_desc(&pdata->desc_if); } @@ -255,23 +292,75 @@ static int xgbe_of_support(struct xgbe_prv_data *pdata) return 0; } + +static struct platform_device *xgbe_of_get_phy_pdev(struct xgbe_prv_data *pdata) +{ + struct device *dev = pdata->dev; + struct device_node *phy_node; + struct platform_device *phy_pdev; + + phy_node = of_parse_phandle(dev->of_node, "phy-handle", 0); + if (!phy_node) { + dev_err(dev, "unable to locate phy device\n"); + return NULL; + } + + phy_pdev = of_find_device_by_node(phy_node); + of_node_put(phy_node); + + return phy_pdev; +} #else /* CONFIG_OF */ static int xgbe_of_support(struct xgbe_prv_data *pdata) { return -EINVAL; } -#endif /*CONFIG_OF */ + +static struct platform_device *xgbe_of_get_phy_pdev(struct xgbe_prv_data *pdata) +{ + return NULL; +} +#endif /* CONFIG_OF */ + +static unsigned int xgbe_resource_count(struct platform_device *pdev, + unsigned int type) +{ + unsigned int count; + int i; + + for (i = 0, count = 0; i < pdev->num_resources; i++) { + struct resource *res = &pdev->resource[i]; + + if (type == resource_type(res)) + count++; + } + + return count; +} + +static struct platform_device *xgbe_get_phy_pdev(struct xgbe_prv_data *pdata) +{ + struct platform_device *phy_pdev; + + if (pdata->use_acpi) { + get_device(pdata->dev); + phy_pdev = pdata->pdev; + } else { + phy_pdev = xgbe_of_get_phy_pdev(pdata); + } + + return phy_pdev; +} static int xgbe_probe(struct platform_device *pdev) { struct xgbe_prv_data *pdata; - struct xgbe_hw_if *hw_if; - struct xgbe_desc_if *desc_if; struct net_device *netdev; - struct device *dev = &pdev->dev; + struct device *dev = &pdev->dev, *phy_dev; + struct platform_device *phy_pdev; struct resource *res; const char *phy_mode; - unsigned int i; + unsigned int i, phy_memnum, phy_irqnum; int ret; DBGPR("--> xgbe_probe\n"); @@ -298,9 +387,34 @@ static int xgbe_probe(struct platform_device *pdev) pdata->msg_enable = netif_msg_init(debug, default_msg_level); + set_bit(XGBE_DOWN, &pdata->dev_state); + /* Check if we should use ACPI or DT */ pdata->use_acpi = (!pdata->adev || acpi_disabled) ? 0 : 1; + phy_pdev = xgbe_get_phy_pdev(pdata); + if (!phy_pdev) { + dev_err(dev, "unable to obtain phy device\n"); + ret = -EINVAL; + goto err_phydev; + } + phy_dev = &phy_pdev->dev; + + if (pdev == phy_pdev) { + /* ACPI: + * The XGBE and PHY resources are grouped together with + * the PHY resources listed last + */ + phy_memnum = xgbe_resource_count(pdev, IORESOURCE_MEM) - 3; + phy_irqnum = xgbe_resource_count(pdev, IORESOURCE_IRQ) - 1; + } else { + /* Device tree: + * The XGBE and PHY resources are separate + */ + phy_memnum = 0; + phy_irqnum = 0; + } + /* Set and validate the number of descriptors for a ring */ BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT); pdata->tx_desc_count = XGBE_TX_DESC_CNT; @@ -340,6 +454,36 @@ static int xgbe_probe(struct platform_device *pdev) if (netif_msg_probe(pdata)) dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs); + res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_memnum++); + pdata->rxtx_regs = devm_ioremap_resource(dev, res); + if (IS_ERR(pdata->rxtx_regs)) { + dev_err(dev, "rxtx ioremap failed\n"); + ret = PTR_ERR(pdata->rxtx_regs); + goto err_io; + } + if (netif_msg_probe(pdata)) + dev_dbg(dev, "rxtx_regs = %p\n", pdata->rxtx_regs); + + res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_memnum++); + pdata->sir0_regs = devm_ioremap_resource(dev, res); + if (IS_ERR(pdata->sir0_regs)) { + dev_err(dev, "sir0 ioremap failed\n"); + ret = PTR_ERR(pdata->sir0_regs); + goto err_io; + } + if (netif_msg_probe(pdata)) + dev_dbg(dev, "sir0_regs = %p\n", pdata->sir0_regs); + + res = platform_get_resource(phy_pdev, IORESOURCE_MEM, phy_memnum++); + pdata->sir1_regs = devm_ioremap_resource(dev, res); + if (IS_ERR(pdata->sir1_regs)) { + dev_err(dev, "sir1 ioremap failed\n"); + ret = PTR_ERR(pdata->sir1_regs); + goto err_io; + } + if (netif_msg_probe(pdata)) + dev_dbg(dev, "sir1_regs = %p\n", pdata->sir1_regs); + /* Retrieve the MAC address */ ret = device_property_read_u8_array(dev, XGBE_MAC_ADDR_PROPERTY, pdata->mac_addr, @@ -366,6 +510,115 @@ static int xgbe_probe(struct platform_device *pdev) if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY)) pdata->per_channel_irq = 1; + /* Retrieve the PHY speedset */ + ret = device_property_read_u32(phy_dev, XGBE_SPEEDSET_PROPERTY, + &pdata->speed_set); + if (ret) { + dev_err(dev, "invalid %s property\n", XGBE_SPEEDSET_PROPERTY); + goto err_io; + } + + switch (pdata->speed_set) { + case XGBE_SPEEDSET_1000_10000: + case XGBE_SPEEDSET_2500_10000: + break; + default: + dev_err(dev, "invalid %s property\n", XGBE_SPEEDSET_PROPERTY); + ret = -EINVAL; + goto err_io; + } + + /* Retrieve the PHY configuration properties */ + if (device_property_present(phy_dev, XGBE_BLWC_PROPERTY)) { + ret = device_property_read_u32_array(phy_dev, + XGBE_BLWC_PROPERTY, + pdata->serdes_blwc, + XGBE_SPEEDS); + if (ret) { + dev_err(dev, "invalid %s property\n", + XGBE_BLWC_PROPERTY); + goto err_io; + } + } else { + memcpy(pdata->serdes_blwc, xgbe_serdes_blwc, + sizeof(pdata->serdes_blwc)); + } + + if (device_property_present(phy_dev, XGBE_CDR_RATE_PROPERTY)) { + ret = device_property_read_u32_array(phy_dev, + XGBE_CDR_RATE_PROPERTY, + pdata->serdes_cdr_rate, + XGBE_SPEEDS); + if (ret) { + dev_err(dev, "invalid %s property\n", + XGBE_CDR_RATE_PROPERTY); + goto err_io; + } + } else { + memcpy(pdata->serdes_cdr_rate, xgbe_serdes_cdr_rate, + sizeof(pdata->serdes_cdr_rate)); + } + + if (device_property_present(phy_dev, XGBE_PQ_SKEW_PROPERTY)) { + ret = device_property_read_u32_array(phy_dev, + XGBE_PQ_SKEW_PROPERTY, + pdata->serdes_pq_skew, + XGBE_SPEEDS); + if (ret) { + dev_err(dev, "invalid %s property\n", + XGBE_PQ_SKEW_PROPERTY); + goto err_io; + } + } else { + memcpy(pdata->serdes_pq_skew, xgbe_serdes_pq_skew, + sizeof(pdata->serdes_pq_skew)); + } + + if (device_property_present(phy_dev, XGBE_TX_AMP_PROPERTY)) { + ret = device_property_read_u32_array(phy_dev, + XGBE_TX_AMP_PROPERTY, + pdata->serdes_tx_amp, + XGBE_SPEEDS); + if (ret) { + dev_err(dev, "invalid %s property\n", + XGBE_TX_AMP_PROPERTY); + goto err_io; + } + } else { + memcpy(pdata->serdes_tx_amp, xgbe_serdes_tx_amp, + sizeof(pdata->serdes_tx_amp)); + } + + if (device_property_present(phy_dev, XGBE_DFE_CFG_PROPERTY)) { + ret = device_property_read_u32_array(phy_dev, + XGBE_DFE_CFG_PROPERTY, + pdata->serdes_dfe_tap_cfg, + XGBE_SPEEDS); + if (ret) { + dev_err(dev, "invalid %s property\n", + XGBE_DFE_CFG_PROPERTY); + goto err_io; + } + } else { + memcpy(pdata->serdes_dfe_tap_cfg, xgbe_serdes_dfe_tap_cfg, + sizeof(pdata->serdes_dfe_tap_cfg)); + } + + if (device_property_present(phy_dev, XGBE_DFE_ENA_PROPERTY)) { + ret = device_property_read_u32_array(phy_dev, + XGBE_DFE_ENA_PROPERTY, + pdata->serdes_dfe_tap_ena, + XGBE_SPEEDS); + if (ret) { + dev_err(dev, "invalid %s property\n", + XGBE_DFE_ENA_PROPERTY); + goto err_io; + } + } else { + memcpy(pdata->serdes_dfe_tap_ena, xgbe_serdes_dfe_tap_ena, + sizeof(pdata->serdes_dfe_tap_ena)); + } + /* Obtain device settings unique to ACPI/OF */ if (pdata->use_acpi) ret = xgbe_acpi_support(pdata); @@ -393,17 +646,23 @@ static int xgbe_probe(struct platform_device *pdev) } pdata->dev_irq = ret; + /* Get the auto-negotiation interrupt */ + ret = platform_get_irq(phy_pdev, phy_irqnum++); + if (ret < 0) { + dev_err(dev, "platform_get_irq phy 0 failed\n"); + goto err_io; + } + pdata->an_irq = ret; + netdev->irq = pdata->dev_irq; netdev->base_addr = (unsigned long)pdata->xgmac_regs; memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len); /* Set all the function pointers */ xgbe_init_all_fptrs(pdata); - hw_if = &pdata->hw_if; - desc_if = &pdata->desc_if; /* Issue software reset to device */ - hw_if->exit(pdata); + pdata->hw_if.exit(pdata); /* Populate the hardware features */ xgbe_get_all_hw_features(pdata); @@ -458,16 +717,8 @@ static int xgbe_probe(struct platform_device *pdev) XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); - /* Prepare to regsiter with MDIO */ - pdata->mii_bus_id = kasprintf(GFP_KERNEL, "%s", pdev->name); - if (!pdata->mii_bus_id) { - dev_err(dev, "failed to allocate mii bus id\n"); - ret = -ENOMEM; - goto err_io; - } - ret = xgbe_mdio_register(pdata); - if (ret) - goto err_bus_id; + /* Call MDIO/PHY initialization routine */ + pdata->phy_if.phy_init(pdata); /* Set device operations */ netdev->netdev_ops = xgbe_get_netdev_ops(); @@ -512,26 +763,52 @@ static int xgbe_probe(struct platform_device *pdev) ret = register_netdev(netdev); if (ret) { dev_err(dev, "net device registration failed\n"); - goto err_reg_netdev; + goto err_io; + } + + /* Create the PHY/ANEG name based on netdev name */ + snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs", + netdev_name(netdev)); + + /* Create workqueues */ + pdata->dev_workqueue = + create_singlethread_workqueue(netdev_name(netdev)); + if (!pdata->dev_workqueue) { + netdev_err(netdev, "device workqueue creation failed\n"); + ret = -ENOMEM; + goto err_netdev; + } + + pdata->an_workqueue = + create_singlethread_workqueue(pdata->an_name); + if (!pdata->an_workqueue) { + netdev_err(netdev, "phy workqueue creation failed\n"); + ret = -ENOMEM; + goto err_wq; } xgbe_ptp_register(pdata); xgbe_debugfs_init(pdata); + platform_device_put(phy_pdev); + netdev_notice(netdev, "net device enabled\n"); DBGPR("<-- xgbe_probe\n"); return 0; -err_reg_netdev: - xgbe_mdio_unregister(pdata); +err_wq: + destroy_workqueue(pdata->dev_workqueue); -err_bus_id: - kfree(pdata->mii_bus_id); +err_netdev: + unregister_netdev(netdev); err_io: + platform_device_put(phy_pdev); + +err_phydev: free_netdev(netdev); err_alloc: @@ -551,11 +828,13 @@ static int xgbe_remove(struct platform_device *pdev) xgbe_ptp_unregister(pdata); - unregister_netdev(netdev); + flush_workqueue(pdata->an_workqueue); + destroy_workqueue(pdata->an_workqueue); - xgbe_mdio_unregister(pdata); + flush_workqueue(pdata->dev_workqueue); + destroy_workqueue(pdata->dev_workqueue); - kfree(pdata->mii_bus_id); + unregister_netdev(netdev); free_netdev(netdev); @@ -568,16 +847,17 @@ static int xgbe_remove(struct platform_device *pdev) static int xgbe_suspend(struct device *dev) { struct net_device *netdev = dev_get_drvdata(dev); - int ret; + struct xgbe_prv_data *pdata = netdev_priv(netdev); + int ret = 0; DBGPR("-->xgbe_suspend\n"); - if (!netif_running(netdev)) { - DBGPR("<--xgbe_dev_suspend\n"); - return -EINVAL; - } + if (netif_running(netdev)) + ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT); - ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT); + pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); DBGPR("<--xgbe_suspend\n"); @@ -587,16 +867,16 @@ static int xgbe_suspend(struct device *dev) static int xgbe_resume(struct device *dev) { struct net_device *netdev = dev_get_drvdata(dev); - int ret; + struct xgbe_prv_data *pdata = netdev_priv(netdev); + int ret = 0; DBGPR("-->xgbe_resume\n"); - if (!netif_running(netdev)) { - DBGPR("<--xgbe_dev_resume\n"); - return -EINVAL; - } + pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); - ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT); + if (netif_running(netdev)) + ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT); DBGPR("<--xgbe_resume\n"); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c index 532a67f728e0..1ae4bfbd13d3 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c @@ -119,48 +119,1036 @@ #include #include #include +#include +#include #include "xgbe.h" #include "xgbe-common.h" -static int xgbe_mdio_read(struct mii_bus *mii, int prtad, int mmd_reg) +static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata) { - struct xgbe_prv_data *pdata = mii->priv; - struct xgbe_hw_if *hw_if = &pdata->hw_if; - int mmd_data; + unsigned int reg; - DBGPR_MDIO("-->xgbe_mdio_read: prtad=%#x mmd_reg=%#x\n", - prtad, mmd_reg); + reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); - mmd_data = hw_if->read_mmd_regs(pdata, prtad, mmd_reg); + reg |= XGBE_KR_TRAINING_ENABLE; + XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); +} + +static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata) +{ + unsigned int reg; + + reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); + + reg &= ~XGBE_KR_TRAINING_ENABLE; + XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); +} + +static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata) +{ + unsigned int reg; + + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + + reg |= MDIO_CTRL1_LPOWER; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); + + usleep_range(75, 100); + + reg &= ~MDIO_CTRL1_LPOWER; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); +} + +static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata) +{ + /* Assert Rx and Tx ratechange */ + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1); +} + +static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata) +{ + unsigned int wait; + u16 status; + + /* Release Rx and Tx ratechange */ + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0); + + /* Wait for Rx and Tx ready */ + wait = XGBE_RATECHANGE_COUNT; + while (wait--) { + usleep_range(50, 75); + + status = XSIR0_IOREAD(pdata, SIR0_STATUS); + if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) && + XSIR_GET_BITS(status, SIR0_STATUS, TX_READY)) + goto rx_reset; + } + + netdev_dbg(pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", + status); + +rx_reset: + /* Perform Rx reset for the DFE changes */ + XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1); +} + +static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata) +{ + unsigned int reg; + + /* Enable KR training */ + xgbe_an_enable_kr_training(pdata); + + /* Set MAC to 10G speed */ + pdata->hw_if.set_xgmii_speed(pdata); + + /* Set PCS to KR/10G speed */ + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); + reg &= ~MDIO_PCS_CTRL2_TYPE; + reg |= MDIO_PCS_CTRL2_10GBR; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); + + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + reg &= ~MDIO_CTRL1_SPEEDSEL; + reg |= MDIO_CTRL1_SPEED10G; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); + + xgbe_pcs_power_cycle(pdata); + + /* Set SerDes to 10G speed */ + xgbe_serdes_start_ratechange(pdata); + + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL); + + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, + pdata->serdes_cdr_rate[XGBE_SPEED_10000]); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, + pdata->serdes_tx_amp[XGBE_SPEED_10000]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, + pdata->serdes_blwc[XGBE_SPEED_10000]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, + pdata->serdes_pq_skew[XGBE_SPEED_10000]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, + pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]); + XRXTX_IOWRITE(pdata, RXTX_REG22, + pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]); + + xgbe_serdes_complete_ratechange(pdata); +} + +static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata) +{ + unsigned int reg; + + /* Disable KR training */ + xgbe_an_disable_kr_training(pdata); + + /* Set MAC to 2.5G speed */ + pdata->hw_if.set_gmii_2500_speed(pdata); + + /* Set PCS to KX/1G speed */ + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); + reg &= ~MDIO_PCS_CTRL2_TYPE; + reg |= MDIO_PCS_CTRL2_10GBX; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); + + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + reg &= ~MDIO_CTRL1_SPEEDSEL; + reg |= MDIO_CTRL1_SPEED1G; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); + + xgbe_pcs_power_cycle(pdata); + + /* Set SerDes to 2.5G speed */ + xgbe_serdes_start_ratechange(pdata); + + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL); + + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, + pdata->serdes_cdr_rate[XGBE_SPEED_2500]); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, + pdata->serdes_tx_amp[XGBE_SPEED_2500]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, + pdata->serdes_blwc[XGBE_SPEED_2500]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, + pdata->serdes_pq_skew[XGBE_SPEED_2500]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, + pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]); + XRXTX_IOWRITE(pdata, RXTX_REG22, + pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]); + + xgbe_serdes_complete_ratechange(pdata); +} + +static void xgbe_gmii_mode(struct xgbe_prv_data *pdata) +{ + unsigned int reg; + + /* Disable KR training */ + xgbe_an_disable_kr_training(pdata); + + /* Set MAC to 1G speed */ + pdata->hw_if.set_gmii_speed(pdata); + + /* Set PCS to KX/1G speed */ + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); + reg &= ~MDIO_PCS_CTRL2_TYPE; + reg |= MDIO_PCS_CTRL2_10GBX; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); + + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + reg &= ~MDIO_CTRL1_SPEEDSEL; + reg |= MDIO_CTRL1_SPEED1G; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); + + xgbe_pcs_power_cycle(pdata); + + /* Set SerDes to 1G speed */ + xgbe_serdes_start_ratechange(pdata); + + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL); + + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, + pdata->serdes_cdr_rate[XGBE_SPEED_1000]); + XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, + pdata->serdes_tx_amp[XGBE_SPEED_1000]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, + pdata->serdes_blwc[XGBE_SPEED_1000]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, + pdata->serdes_pq_skew[XGBE_SPEED_1000]); + XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, + pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]); + XRXTX_IOWRITE(pdata, RXTX_REG22, + pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]); + + xgbe_serdes_complete_ratechange(pdata); +} + +static void xgbe_cur_mode(struct xgbe_prv_data *pdata, + enum xgbe_mode *mode) +{ + unsigned int reg; + + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); + if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR) + *mode = XGBE_MODE_KR; + else + *mode = XGBE_MODE_KX; +} + +static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) +{ + enum xgbe_mode mode; + + xgbe_cur_mode(pdata, &mode); + + return (mode == XGBE_MODE_KR); +} + +static void xgbe_switch_mode(struct xgbe_prv_data *pdata) +{ + /* If we are in KR switch to KX, and vice-versa */ + if (xgbe_in_kr_mode(pdata)) { + if (pdata->speed_set == XGBE_SPEEDSET_1000_10000) + xgbe_gmii_mode(pdata); + else + xgbe_gmii_2500_mode(pdata); + } else { + xgbe_xgmii_mode(pdata); + } +} + +static void xgbe_set_mode(struct xgbe_prv_data *pdata, + enum xgbe_mode mode) +{ + enum xgbe_mode cur_mode; + + xgbe_cur_mode(pdata, &cur_mode); + if (mode != cur_mode) + xgbe_switch_mode(pdata); +} + +static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart) +{ + unsigned int reg; + + reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); + reg &= ~MDIO_AN_CTRL1_ENABLE; + + if (enable) + reg |= MDIO_AN_CTRL1_ENABLE; + + if (restart) + reg |= MDIO_AN_CTRL1_RESTART; + + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); +} + +static void xgbe_restart_an(struct xgbe_prv_data *pdata) +{ + xgbe_set_an(pdata, true, true); +} + +static void xgbe_disable_an(struct xgbe_prv_data *pdata) +{ + xgbe_set_an(pdata, false, false); +} + +static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata, + enum xgbe_rx *state) +{ + unsigned int ad_reg, lp_reg, reg; + + *state = XGBE_RX_COMPLETE; + + /* If we're not in KR mode then we're done */ + if (!xgbe_in_kr_mode(pdata)) + return XGBE_AN_PAGE_RECEIVED; + + /* Enable/Disable FEC */ + ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); + lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); + + reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); + reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); + if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) + reg |= pdata->fec_ability; + + XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); + + /* Start KR training */ + reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); + if (reg & XGBE_KR_TRAINING_ENABLE) { + XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1); + + reg |= XGBE_KR_TRAINING_START; + XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, + reg); + + XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0); + } + + return XGBE_AN_PAGE_RECEIVED; +} + +static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata, + enum xgbe_rx *state) +{ + u16 msg; + + *state = XGBE_RX_XNP; + + msg = XGBE_XNP_MCF_NULL_MESSAGE; + msg |= XGBE_XNP_MP_FORMATTED; + + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); + + return XGBE_AN_PAGE_RECEIVED; +} + +static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata, + enum xgbe_rx *state) +{ + unsigned int link_support; + unsigned int reg, ad_reg, lp_reg; + + /* Read Base Ability register 2 first */ + reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); + + /* Check for a supported mode, otherwise restart in a different one */ + link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; + if (!(reg & link_support)) + return XGBE_AN_INCOMPAT_LINK; + + /* Check Extended Next Page support */ + ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); + lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); + + return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || + (lp_reg & XGBE_XNP_NP_EXCHANGE)) + ? xgbe_an_tx_xnp(pdata, state) + : xgbe_an_tx_training(pdata, state); +} + +static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata, + enum xgbe_rx *state) +{ + unsigned int ad_reg, lp_reg; + + /* Check Extended Next Page support */ + ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); + lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); + + return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || + (lp_reg & XGBE_XNP_NP_EXCHANGE)) + ? xgbe_an_tx_xnp(pdata, state) + : xgbe_an_tx_training(pdata, state); +} + +static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata) +{ + enum xgbe_rx *state; + unsigned long an_timeout; + enum xgbe_an ret; + + if (!pdata->an_start) { + pdata->an_start = jiffies; + } else { + an_timeout = pdata->an_start + + msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); + if (time_after(jiffies, an_timeout)) { + /* Auto-negotiation timed out, reset state */ + pdata->kr_state = XGBE_RX_BPA; + pdata->kx_state = XGBE_RX_BPA; + + pdata->an_start = jiffies; + } + } + + state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state + : &pdata->kx_state; + + switch (*state) { + case XGBE_RX_BPA: + ret = xgbe_an_rx_bpa(pdata, state); + break; + + case XGBE_RX_XNP: + ret = xgbe_an_rx_xnp(pdata, state); + break; + + default: + ret = XGBE_AN_ERROR; + } + + return ret; +} + +static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata) +{ + /* Be sure we aren't looping trying to negotiate */ + if (xgbe_in_kr_mode(pdata)) { + pdata->kr_state = XGBE_RX_ERROR; + + if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && + !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) + return XGBE_AN_NO_LINK; + + if (pdata->kx_state != XGBE_RX_BPA) + return XGBE_AN_NO_LINK; + } else { + pdata->kx_state = XGBE_RX_ERROR; + + if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) + return XGBE_AN_NO_LINK; + + if (pdata->kr_state != XGBE_RX_BPA) + return XGBE_AN_NO_LINK; + } + + xgbe_disable_an(pdata); + + xgbe_switch_mode(pdata); + + xgbe_restart_an(pdata); + + return XGBE_AN_INCOMPAT_LINK; +} + +static irqreturn_t xgbe_an_isr(int irq, void *data) +{ + struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; + + /* Interrupt reason must be read and cleared outside of IRQ context */ + disable_irq_nosync(pdata->an_irq); + + queue_work(pdata->an_workqueue, &pdata->an_irq_work); + + return IRQ_HANDLED; +} + +static void xgbe_an_irq_work(struct work_struct *work) +{ + struct xgbe_prv_data *pdata = container_of(work, + struct xgbe_prv_data, + an_irq_work); + + /* Avoid a race between enabling the IRQ and exiting the work by + * waiting for the work to finish and then queueing it + */ + flush_work(&pdata->an_work); + queue_work(pdata->an_workqueue, &pdata->an_work); +} + +static void xgbe_an_state_machine(struct work_struct *work) +{ + struct xgbe_prv_data *pdata = container_of(work, + struct xgbe_prv_data, + an_work); + enum xgbe_an cur_state = pdata->an_state; + unsigned int int_reg, int_mask; + + mutex_lock(&pdata->an_mutex); + + /* Read the interrupt */ + int_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); + if (!int_reg) + goto out; + +next_int: + if (int_reg & XGBE_AN_PG_RCV) { + pdata->an_state = XGBE_AN_PAGE_RECEIVED; + int_mask = XGBE_AN_PG_RCV; + } else if (int_reg & XGBE_AN_INC_LINK) { + pdata->an_state = XGBE_AN_INCOMPAT_LINK; + int_mask = XGBE_AN_INC_LINK; + } else if (int_reg & XGBE_AN_INT_CMPLT) { + pdata->an_state = XGBE_AN_COMPLETE; + int_mask = XGBE_AN_INT_CMPLT; + } else { + pdata->an_state = XGBE_AN_ERROR; + int_mask = 0; + } + + /* Clear the interrupt to be processed */ + int_reg &= ~int_mask; + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, int_reg); + + pdata->an_result = pdata->an_state; + +again: + cur_state = pdata->an_state; + + switch (pdata->an_state) { + case XGBE_AN_READY: + pdata->an_supported = 0; + break; + + case XGBE_AN_PAGE_RECEIVED: + pdata->an_state = xgbe_an_page_received(pdata); + pdata->an_supported++; + break; - DBGPR_MDIO("<--xgbe_mdio_read: mmd_data=%#x\n", mmd_data); + case XGBE_AN_INCOMPAT_LINK: + pdata->an_supported = 0; + pdata->parallel_detect = 0; + pdata->an_state = xgbe_an_incompat_link(pdata); + break; - return mmd_data; + case XGBE_AN_COMPLETE: + pdata->parallel_detect = pdata->an_supported ? 0 : 1; + netdev_dbg(pdata->netdev, "%s successful\n", + pdata->an_supported ? "Auto negotiation" + : "Parallel detection"); + break; + + case XGBE_AN_NO_LINK: + break; + + default: + pdata->an_state = XGBE_AN_ERROR; + } + + if (pdata->an_state == XGBE_AN_NO_LINK) { + int_reg = 0; + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); + } else if (pdata->an_state == XGBE_AN_ERROR) { + netdev_err(pdata->netdev, + "error during auto-negotiation, state=%u\n", + cur_state); + + int_reg = 0; + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); + } + + if (pdata->an_state >= XGBE_AN_COMPLETE) { + pdata->an_result = pdata->an_state; + pdata->an_state = XGBE_AN_READY; + pdata->kr_state = XGBE_RX_BPA; + pdata->kx_state = XGBE_RX_BPA; + pdata->an_start = 0; + } + + if (cur_state != pdata->an_state) + goto again; + + if (int_reg) + goto next_int; + +out: + enable_irq(pdata->an_irq); + + mutex_unlock(&pdata->an_mutex); } -static int xgbe_mdio_write(struct mii_bus *mii, int prtad, int mmd_reg, - u16 mmd_val) +static void xgbe_an_init(struct xgbe_prv_data *pdata) { - struct xgbe_prv_data *pdata = mii->priv; - struct xgbe_hw_if *hw_if = &pdata->hw_if; - int mmd_data = mmd_val; + unsigned int reg; + + /* Set up Advertisement register 3 first */ + reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); + if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC) + reg |= 0xc000; + else + reg &= ~0xc000; + + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); + + /* Set up Advertisement register 2 next */ + reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); + if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) + reg |= 0x80; + else + reg &= ~0x80; + + if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || + (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) + reg |= 0x20; + else + reg &= ~0x20; + + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); - DBGPR_MDIO("-->xgbe_mdio_write: prtad=%#x mmd_reg=%#x mmd_data=%#x\n", - prtad, mmd_reg, mmd_data); + /* Set up Advertisement register 1 last */ + reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); + if (pdata->phy.advertising & ADVERTISED_Pause) + reg |= 0x400; + else + reg &= ~0x400; - hw_if->write_mmd_regs(pdata, prtad, mmd_reg, mmd_data); + if (pdata->phy.advertising & ADVERTISED_Asym_Pause) + reg |= 0x800; + else + reg &= ~0x800; + + /* We don't intend to perform XNP */ + reg &= ~XGBE_XNP_NP_EXCHANGE; + + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); +} + +static const char *xgbe_phy_speed_string(int speed) +{ + switch (speed) { + case SPEED_1000: + return "1Gbps"; + case SPEED_2500: + return "2.5Gbps"; + case SPEED_10000: + return "10Gbps"; + case SPEED_UNKNOWN: + return "Unknown"; + default: + return "Unsupported"; + } +} + +static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) +{ + if (pdata->phy.link) + netdev_info(pdata->netdev, + "Link is Up - %s/%s - flow control %s\n", + xgbe_phy_speed_string(pdata->phy.speed), + pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", + pdata->phy.pause ? "rx/tx" : "off"); + else + netdev_info(pdata->netdev, "Link is Down\n"); +} + +static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) +{ + int new_state = 0; + + if (pdata->phy.link) { + /* Flow control support */ + if (pdata->pause_autoneg) { + if (pdata->phy.pause || pdata->phy.asym_pause) { + pdata->tx_pause = 1; + pdata->rx_pause = 1; + } else { + pdata->tx_pause = 0; + pdata->rx_pause = 0; + } + } + + if (pdata->tx_pause != pdata->phy_tx_pause) { + pdata->hw_if.config_tx_flow_control(pdata); + pdata->phy_tx_pause = pdata->tx_pause; + } + + if (pdata->rx_pause != pdata->phy_rx_pause) { + pdata->hw_if.config_rx_flow_control(pdata); + pdata->phy_rx_pause = pdata->rx_pause; + } + + /* Speed support */ + if (pdata->phy_speed != pdata->phy.speed) { + new_state = 1; + pdata->phy_speed = pdata->phy.speed; + } + + if (pdata->phy_link != pdata->phy.link) { + new_state = 1; + pdata->phy_link = pdata->phy.link; + } + } else if (pdata->phy_link) { + new_state = 1; + pdata->phy_link = 0; + pdata->phy_speed = SPEED_UNKNOWN; + } + + if (new_state && netif_msg_link(pdata)) + xgbe_phy_print_status(pdata); +} + +static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) +{ + /* Disable auto-negotiation */ + xgbe_disable_an(pdata); + + /* Validate/Set specified speed */ + switch (pdata->phy.speed) { + case SPEED_10000: + xgbe_set_mode(pdata, XGBE_MODE_KR); + break; + + case SPEED_2500: + case SPEED_1000: + xgbe_set_mode(pdata, XGBE_MODE_KX); + break; + + default: + return -EINVAL; + } - DBGPR_MDIO("<--xgbe_mdio_write\n"); + /* Validate duplex mode */ + if (pdata->phy.duplex != DUPLEX_FULL) + return -EINVAL; + + pdata->phy.pause = 0; + pdata->phy.asym_pause = 0; return 0; } -void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) +static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) +{ + set_bit(XGBE_LINK_INIT, &pdata->dev_state); + pdata->link_check = jiffies; + + if (pdata->phy.autoneg != AUTONEG_ENABLE) + return xgbe_phy_config_fixed(pdata); + + /* Disable auto-negotiation interrupt */ + disable_irq(pdata->an_irq); + + /* Start auto-negotiation in a supported mode */ + if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) { + xgbe_set_mode(pdata, XGBE_MODE_KR); + } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || + (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) { + xgbe_set_mode(pdata, XGBE_MODE_KX); + } else { + enable_irq(pdata->an_irq); + return -EINVAL; + } + + /* Disable and stop any in progress auto-negotiation */ + xgbe_disable_an(pdata); + + /* Clear any auto-negotitation interrupts */ + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); + + pdata->an_result = XGBE_AN_READY; + pdata->an_state = XGBE_AN_READY; + pdata->kr_state = XGBE_RX_BPA; + pdata->kx_state = XGBE_RX_BPA; + + /* Re-enable auto-negotiation interrupt */ + enable_irq(pdata->an_irq); + + /* Set up advertisement registers based on current settings */ + xgbe_an_init(pdata); + + /* Enable and start auto-negotiation */ + xgbe_restart_an(pdata); + + return 0; +} + +static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) +{ + int ret; + + mutex_lock(&pdata->an_mutex); + + ret = __xgbe_phy_config_aneg(pdata); + if (ret) + set_bit(XGBE_LINK_ERR, &pdata->dev_state); + else + clear_bit(XGBE_LINK_ERR, &pdata->dev_state); + + mutex_unlock(&pdata->an_mutex); + + return ret; +} + +static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) +{ + return (pdata->an_result == XGBE_AN_COMPLETE); +} + +static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) +{ + unsigned long link_timeout; + + link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); + if (time_after(jiffies, link_timeout)) + xgbe_phy_config_aneg(pdata); +} + +static void xgbe_phy_status_force(struct xgbe_prv_data *pdata) +{ + if (xgbe_in_kr_mode(pdata)) { + pdata->phy.speed = SPEED_10000; + } else { + switch (pdata->speed_set) { + case XGBE_SPEEDSET_1000_10000: + pdata->phy.speed = SPEED_1000; + break; + + case XGBE_SPEEDSET_2500_10000: + pdata->phy.speed = SPEED_2500; + break; + } + } + pdata->phy.duplex = DUPLEX_FULL; + pdata->phy.pause = 0; + pdata->phy.asym_pause = 0; +} + +static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) +{ + unsigned int ad_reg, lp_reg; + + pdata->phy.lp_advertising = 0; + + if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) + return xgbe_phy_status_force(pdata); + + pdata->phy.lp_advertising |= ADVERTISED_Autoneg; + pdata->phy.lp_advertising |= ADVERTISED_Backplane; + + /* Compare Advertisement and Link Partner register 1 */ + ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); + lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); + if (lp_reg & 0x400) + pdata->phy.lp_advertising |= ADVERTISED_Pause; + if (lp_reg & 0x800) + pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; + + ad_reg &= lp_reg; + pdata->phy.pause = (ad_reg & 0x400) ? 1 : 0; + pdata->phy.asym_pause = (ad_reg & 0x800) ? 1 : 0; + + /* Compare Advertisement and Link Partner register 2 */ + ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); + lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); + if (lp_reg & 0x80) + pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; + if (lp_reg & 0x20) { + switch (pdata->speed_set) { + case XGBE_SPEEDSET_1000_10000: + pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; + break; + case XGBE_SPEEDSET_2500_10000: + pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full; + break; + } + } + + ad_reg &= lp_reg; + if (ad_reg & 0x80) { + pdata->phy.speed = SPEED_10000; + xgbe_set_mode(pdata, XGBE_MODE_KR); + } else if (ad_reg & 0x20) { + switch (pdata->speed_set) { + case XGBE_SPEEDSET_1000_10000: + pdata->phy.speed = SPEED_1000; + break; + + case XGBE_SPEEDSET_2500_10000: + pdata->phy.speed = SPEED_2500; + break; + } + + xgbe_set_mode(pdata, XGBE_MODE_KX); + } else { + pdata->phy.speed = SPEED_UNKNOWN; + } + + /* Compare Advertisement and Link Partner register 3 */ + ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); + lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); + if (lp_reg & 0xc000) + pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; + + pdata->phy.duplex = DUPLEX_FULL; +} + +static void xgbe_phy_status(struct xgbe_prv_data *pdata) +{ + unsigned int reg, link_aneg; + + if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { + if (test_and_clear_bit(XGBE_LINK, &pdata->dev_state)) + netif_carrier_off(pdata->netdev); + + pdata->phy.link = 0; + goto adjust_link; + } + + link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); + + /* Get the link status. Link status is latched low, so read + * once to clear and then read again to get current state + */ + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); + pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0; + + if (pdata->phy.link) { + if (link_aneg && !xgbe_phy_aneg_done(pdata)) { + xgbe_check_link_timeout(pdata); + return; + } + + xgbe_phy_status_aneg(pdata); + + if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) + clear_bit(XGBE_LINK_INIT, &pdata->dev_state); + + if (!test_bit(XGBE_LINK, &pdata->dev_state)) { + set_bit(XGBE_LINK, &pdata->dev_state); + netif_carrier_on(pdata->netdev); + } + } else { + if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { + xgbe_check_link_timeout(pdata); + + if (link_aneg) + return; + } + + xgbe_phy_status_aneg(pdata); + + if (test_bit(XGBE_LINK, &pdata->dev_state)) { + clear_bit(XGBE_LINK, &pdata->dev_state); + netif_carrier_off(pdata->netdev); + } + } + +adjust_link: + xgbe_phy_adjust_link(pdata); +} + +static void xgbe_phy_stop(struct xgbe_prv_data *pdata) +{ + /* Disable auto-negotiation */ + xgbe_disable_an(pdata); + + /* Disable auto-negotiation interrupts */ + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); + + devm_free_irq(pdata->dev, pdata->an_irq, pdata); + + pdata->phy.link = 0; + if (test_and_clear_bit(XGBE_LINK, &pdata->dev_state)) + netif_carrier_off(pdata->netdev); + + xgbe_phy_adjust_link(pdata); +} + +static int xgbe_phy_start(struct xgbe_prv_data *pdata) +{ + struct net_device *netdev = pdata->netdev; + int ret; + + ret = devm_request_irq(pdata->dev, pdata->an_irq, + xgbe_an_isr, 0, pdata->an_name, + pdata); + if (ret) { + netdev_err(netdev, "phy irq request failed\n"); + return ret; + } + + /* Set initial mode - call the mode setting routines + * directly to insure we are properly configured + */ + if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) { + xgbe_xgmii_mode(pdata); + } else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) { + xgbe_gmii_mode(pdata); + } else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) { + xgbe_gmii_2500_mode(pdata); + } else { + ret = -EINVAL; + goto err_irq; + } + + /* Set up advertisement registers based on current settings */ + xgbe_an_init(pdata); + + /* Enable auto-negotiation interrupts */ + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); + + return xgbe_phy_config_aneg(pdata); + +err_irq: + devm_free_irq(pdata->dev, pdata->an_irq, pdata); + + return ret; +} + +static int xgbe_phy_reset(struct xgbe_prv_data *pdata) +{ + unsigned int count, reg; + + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + reg |= MDIO_CTRL1_RESET; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); + + count = 50; + do { + msleep(20); + reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); + } while ((reg & MDIO_CTRL1_RESET) && --count); + + if (reg & MDIO_CTRL1_RESET) + return -ETIMEDOUT; + + /* Disable auto-negotiation for now */ + xgbe_disable_an(pdata); + + /* Clear auto-negotiation interrupts */ + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); + + return 0; +} + +static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) { struct device *dev = pdata->dev; - struct phy_device *phydev = pdata->phydev; - int i; dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); @@ -194,122 +1182,59 @@ void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) MDIO_AN_COMP_STAT, XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); - dev_dbg(dev, "MMD Device Mask = %#x\n", - phydev->c45_ids.devices_in_package); - for (i = 0; i < ARRAY_SIZE(phydev->c45_ids.device_ids); i++) - dev_dbg(dev, " MMD %d: ID = %#08x\n", i, - phydev->c45_ids.device_ids[i]); - dev_dbg(dev, "\n*************************************************\n"); } -int xgbe_mdio_register(struct xgbe_prv_data *pdata) +static void xgbe_phy_init(struct xgbe_prv_data *pdata) { - struct mii_bus *mii; - struct phy_device *phydev; - int ret = 0; - - DBGPR("-->xgbe_mdio_register\n"); - - mii = mdiobus_alloc(); - if (!mii) { - dev_err(pdata->dev, "mdiobus_alloc failed\n"); - return -ENOMEM; - } - - /* Register on the MDIO bus (don't probe any PHYs) */ - mii->name = XGBE_PHY_NAME; - mii->read = xgbe_mdio_read; - mii->write = xgbe_mdio_write; - snprintf(mii->id, sizeof(mii->id), "%s", pdata->mii_bus_id); - mii->priv = pdata; - mii->phy_mask = ~0; - mii->parent = pdata->dev; - ret = mdiobus_register(mii); - if (ret) { - dev_err(pdata->dev, "mdiobus_register failed\n"); - goto err_mdiobus_alloc; - } - if (netif_msg_drv(pdata)) - dev_dbg(pdata->dev, "mdiobus_register succeeded for %s\n", - pdata->mii_bus_id); - - /* Probe the PCS using Clause 45 */ - phydev = get_phy_device(mii, XGBE_PRTAD, true); - if (IS_ERR(phydev) || !phydev || - !phydev->c45_ids.device_ids[MDIO_MMD_PCS]) { - dev_err(pdata->dev, "get_phy_device failed\n"); - ret = phydev ? PTR_ERR(phydev) : -ENOLINK; - goto err_mdiobus_register; - } - request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, - MDIO_ID_ARGS(phydev->c45_ids.device_ids[MDIO_MMD_PCS])); + mutex_init(&pdata->an_mutex); + INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); + INIT_WORK(&pdata->an_work, xgbe_an_state_machine); + pdata->mdio_mmd = MDIO_MMD_PCS; - ret = phy_device_register(phydev); - if (ret) { - dev_err(pdata->dev, "phy_device_register failed\n"); - goto err_phy_device; - } - if (!phydev->dev.driver) { - dev_err(pdata->dev, "phy driver probe failed\n"); - ret = -EIO; - goto err_phy_device; + /* Initialize supported features */ + pdata->phy.supported = SUPPORTED_Autoneg; + pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; + pdata->phy.supported |= SUPPORTED_Backplane; + pdata->phy.supported |= SUPPORTED_10000baseKR_Full; + switch (pdata->speed_set) { + case XGBE_SPEEDSET_1000_10000: + pdata->phy.supported |= SUPPORTED_1000baseKX_Full; + break; + case XGBE_SPEEDSET_2500_10000: + pdata->phy.supported |= SUPPORTED_2500baseX_Full; + break; } - /* Add a reference to the PHY driver so it can't be unloaded */ - pdata->phy_module = phydev->dev.driver->owner; - if (!try_module_get(pdata->phy_module)) { - dev_err(pdata->dev, "try_module_get failed\n"); - ret = -EIO; - goto err_phy_device; - } + pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, + MDIO_PMA_10GBR_FECABLE); + pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | + MDIO_PMA_10GBR_FECABLE_ERRABLE); + if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) + pdata->phy.supported |= SUPPORTED_10000baseR_FEC; - pdata->mii = mii; - pdata->mdio_mmd = MDIO_MMD_PCS; + pdata->phy.advertising = pdata->phy.supported; - phydev->autoneg = pdata->default_autoneg; - if (phydev->autoneg == AUTONEG_DISABLE) { - phydev->speed = pdata->default_speed; - phydev->duplex = DUPLEX_FULL; + pdata->phy.address = 0; - phydev->advertising &= ~ADVERTISED_Autoneg; - } + pdata->phy.autoneg = AUTONEG_ENABLE; + pdata->phy.speed = SPEED_UNKNOWN; + pdata->phy.duplex = DUPLEX_UNKNOWN; - pdata->phydev = phydev; + pdata->phy.link = 0; if (netif_msg_drv(pdata)) xgbe_dump_phy_registers(pdata); - - DBGPR("<--xgbe_mdio_register\n"); - - return 0; - -err_phy_device: - phy_device_free(phydev); - -err_mdiobus_register: - mdiobus_unregister(mii); - -err_mdiobus_alloc: - mdiobus_free(mii); - - return ret; } -void xgbe_mdio_unregister(struct xgbe_prv_data *pdata) +void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) { - DBGPR("-->xgbe_mdio_unregister\n"); - - pdata->phydev = NULL; - - module_put(pdata->phy_module); - pdata->phy_module = NULL; - - mdiobus_unregister(pdata->mii); - pdata->mii->priv = NULL; + phy_if->phy_init = xgbe_phy_init; - mdiobus_free(pdata->mii); - pdata->mii = NULL; + phy_if->phy_reset = xgbe_phy_reset; + phy_if->phy_start = xgbe_phy_start; + phy_if->phy_stop = xgbe_phy_stop; - DBGPR("<--xgbe_mdio_unregister\n"); + phy_if->phy_status = xgbe_phy_status; + phy_if->phy_config_aneg = xgbe_phy_config_aneg; } diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h index e182b2569bde..b6aecc95e63f 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h @@ -129,7 +129,7 @@ #include #define XGBE_DRV_NAME "amd-xgbe" -#define XGBE_DRV_VERSION "1.0.0-a" +#define XGBE_DRV_VERSION "1.0.1" #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" /* Descriptor related defines */ @@ -178,14 +178,17 @@ #define XGMAC_JUMBO_PACKET_MTU 9000 #define XGMAC_MAX_JUMBO_PACKET 9018 -/* MDIO bus phy name */ -#define XGBE_PHY_NAME "amd_xgbe_phy" -#define XGBE_PRTAD 0 - /* Common property names */ #define XGBE_MAC_ADDR_PROPERTY "mac-address" #define XGBE_PHY_MODE_PROPERTY "phy-mode" #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" +#define XGBE_SPEEDSET_PROPERTY "amd,speed-set" +#define XGBE_BLWC_PROPERTY "amd,serdes-blwc" +#define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" +#define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" +#define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp" +#define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config" +#define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable" /* Device-tree clock names */ #define XGBE_DMA_CLOCK "dma_clk" @@ -241,6 +244,49 @@ #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 #define XGBE_RSS_HASH_KEY_TYPE 1 +/* Auto-negotiation */ +#define XGBE_AN_MS_TIMEOUT 500 +#define XGBE_LINK_TIMEOUT 10 + +#define XGBE_AN_INT_CMPLT 0x01 +#define XGBE_AN_INC_LINK 0x02 +#define XGBE_AN_PG_RCV 0x04 +#define XGBE_AN_INT_MASK 0x07 + +/* Rate-change complete wait/retry count */ +#define XGBE_RATECHANGE_COUNT 500 + +/* Default SerDes settings */ +#define XGBE_SPEED_10000_BLWC 0 +#define XGBE_SPEED_10000_CDR 0x7 +#define XGBE_SPEED_10000_PLL 0x1 +#define XGBE_SPEED_10000_PQ 0x12 +#define XGBE_SPEED_10000_RATE 0x0 +#define XGBE_SPEED_10000_TXAMP 0xa +#define XGBE_SPEED_10000_WORD 0x7 +#define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1 +#define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f + +#define XGBE_SPEED_2500_BLWC 1 +#define XGBE_SPEED_2500_CDR 0x2 +#define XGBE_SPEED_2500_PLL 0x0 +#define XGBE_SPEED_2500_PQ 0xa +#define XGBE_SPEED_2500_RATE 0x1 +#define XGBE_SPEED_2500_TXAMP 0xf +#define XGBE_SPEED_2500_WORD 0x1 +#define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3 +#define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0 + +#define XGBE_SPEED_1000_BLWC 1 +#define XGBE_SPEED_1000_CDR 0x2 +#define XGBE_SPEED_1000_PLL 0x0 +#define XGBE_SPEED_1000_PQ 0xa +#define XGBE_SPEED_1000_RATE 0x3 +#define XGBE_SPEED_1000_TXAMP 0xf +#define XGBE_SPEED_1000_WORD 0x1 +#define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3 +#define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0 + struct xgbe_prv_data; struct xgbe_packet_data { @@ -412,6 +458,13 @@ struct xgbe_channel { struct xgbe_ring *rx_ring; } ____cacheline_aligned; +enum xgbe_state { + XGBE_DOWN, + XGBE_LINK, + XGBE_LINK_INIT, + XGBE_LINK_ERR, +}; + enum xgbe_int { XGMAC_INT_DMA_CH_SR_TI, XGMAC_INT_DMA_CH_SR_TPS, @@ -443,6 +496,55 @@ enum xgbe_mtl_fifo_size { XGMAC_MTL_FIFO_SIZE_256K = 0x3ff, }; +enum xgbe_speed { + XGBE_SPEED_1000 = 0, + XGBE_SPEED_2500, + XGBE_SPEED_10000, + XGBE_SPEEDS, +}; + +enum xgbe_an { + XGBE_AN_READY = 0, + XGBE_AN_PAGE_RECEIVED, + XGBE_AN_INCOMPAT_LINK, + XGBE_AN_COMPLETE, + XGBE_AN_NO_LINK, + XGBE_AN_ERROR, +}; + +enum xgbe_rx { + XGBE_RX_BPA = 0, + XGBE_RX_XNP, + XGBE_RX_COMPLETE, + XGBE_RX_ERROR, +}; + +enum xgbe_mode { + XGBE_MODE_KR = 0, + XGBE_MODE_KX, +}; + +enum xgbe_speedset { + XGBE_SPEEDSET_1000_10000 = 0, + XGBE_SPEEDSET_2500_10000, +}; + +struct xgbe_phy { + u32 supported; + u32 advertising; + u32 lp_advertising; + + int address; + + int autoneg; + int speed; + int duplex; + int pause; + int asym_pause; + + int link; +}; + struct xgbe_mmc_stats { /* Tx Stats */ u64 txoctetcount_gb; @@ -594,6 +696,20 @@ struct xgbe_hw_if { int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); }; +struct xgbe_phy_if { + /* For initial PHY setup */ + void (*phy_init)(struct xgbe_prv_data *); + + /* For PHY support when setting device up/down */ + int (*phy_reset)(struct xgbe_prv_data *); + int (*phy_start)(struct xgbe_prv_data *); + void (*phy_stop)(struct xgbe_prv_data *); + + /* For PHY support while device is up */ + void (*phy_status)(struct xgbe_prv_data *); + int (*phy_config_aneg)(struct xgbe_prv_data *); +}; + struct xgbe_desc_if { int (*alloc_ring_resources)(struct xgbe_prv_data *); void (*free_ring_resources)(struct xgbe_prv_data *); @@ -663,6 +779,9 @@ struct xgbe_prv_data { /* XGMAC/XPCS related mmio registers */ void __iomem *xgmac_regs; /* XGMAC CSRs */ void __iomem *xpcs_regs; /* XPCS MMD registers */ + void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ + void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ + void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ /* Overall device lock */ spinlock_t lock; @@ -673,10 +792,14 @@ struct xgbe_prv_data { /* RSS addressing mutex */ struct mutex rss_mutex; + /* Flags representing xgbe_state */ + unsigned long dev_state; + int dev_irq; unsigned int per_channel_irq; struct xgbe_hw_if hw_if; + struct xgbe_phy_if phy_if; struct xgbe_desc_if desc_if; /* AXI DMA settings */ @@ -685,6 +808,11 @@ struct xgbe_prv_data { unsigned int arcache; unsigned int awcache; + /* Service routine support */ + struct workqueue_struct *dev_workqueue; + struct work_struct service_work; + struct timer_list service_timer; + /* Rings for Tx/Rx on a DMA channel */ struct xgbe_channel *channel; unsigned int channel_count; @@ -732,22 +860,6 @@ struct xgbe_prv_data { u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; u32 rss_options; - /* MDIO settings */ - struct module *phy_module; - char *mii_bus_id; - struct mii_bus *mii; - int mdio_mmd; - struct phy_device *phydev; - int default_autoneg; - int default_speed; - - /* Current PHY settings */ - phy_interface_t phy_mode; - int phy_link; - int phy_speed; - unsigned int phy_tx_pause; - unsigned int phy_rx_pause; - /* Netdev related settings */ unsigned char mac_addr[ETH_ALEN]; netdev_features_t netdev_features; @@ -794,6 +906,53 @@ struct xgbe_prv_data { /* Network interface message level setting */ u32 msg_enable; + /* Current PHY settings */ + phy_interface_t phy_mode; + int phy_link; + int phy_speed; + unsigned int phy_tx_pause; + unsigned int phy_rx_pause; + + /* MDIO/PHY related settings */ + struct xgbe_phy phy; + int mdio_mmd; + unsigned long link_check; + + char an_name[IFNAMSIZ + 32]; + struct workqueue_struct *an_workqueue; + + int an_irq; + struct work_struct an_irq_work; + + unsigned int speed_set; + + /* SerDes UEFI configurable settings. + * Switching between modes/speeds requires new values for some + * SerDes settings. The values can be supplied as device + * properties in array format. The first array entry is for + * 1GbE, second for 2.5GbE and third for 10GbE + */ + u32 serdes_blwc[XGBE_SPEEDS]; + u32 serdes_cdr_rate[XGBE_SPEEDS]; + u32 serdes_pq_skew[XGBE_SPEEDS]; + u32 serdes_tx_amp[XGBE_SPEEDS]; + u32 serdes_dfe_tap_cfg[XGBE_SPEEDS]; + u32 serdes_dfe_tap_ena[XGBE_SPEEDS]; + + /* Auto-negotiation state machine support */ + struct mutex an_mutex; + enum xgbe_an an_result; + enum xgbe_an an_state; + enum xgbe_rx kr_state; + enum xgbe_rx kx_state; + struct work_struct an_work; + unsigned int an_supported; + unsigned int parallel_detect; + unsigned int fec_ability; + unsigned long an_start; + + unsigned int lpm_ctrl; /* CTRL1 for resume */ + #ifdef CONFIG_DEBUG_FS struct dentry *xgbe_debugfs; @@ -807,6 +966,7 @@ struct xgbe_prv_data { /* Function prototypes*/ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); +void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); struct net_device_ops *xgbe_get_netdev_ops(void); struct ethtool_ops *xgbe_get_ethtool_ops(void); @@ -814,9 +974,6 @@ struct ethtool_ops *xgbe_get_ethtool_ops(void); const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); #endif -int xgbe_mdio_register(struct xgbe_prv_data *); -void xgbe_mdio_unregister(struct xgbe_prv_data *); -void xgbe_dump_phy_registers(struct xgbe_prv_data *); void xgbe_ptp_register(struct xgbe_prv_data *); void xgbe_ptp_unregister(struct xgbe_prv_data *); void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 70641d2c0429..7c0cb87d1f2f 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -24,13 +24,6 @@ config AMD_PHY ---help--- Currently supports the am79c874 -config AMD_XGBE_PHY - tristate "Driver for the AMD 10GbE (amd-xgbe) PHYs" - depends on (OF || ACPI) && HAS_IOMEM - depends on ARM64 || COMPILE_TEST - ---help--- - Currently supports the AMD 10GbE PHY - config MARVELL_PHY tristate "Drivers for Marvell PHYs" ---help--- diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 501ea7699a2d..e97e7f921862 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -33,5 +33,4 @@ obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o -obj-$(CONFIG_AMD_XGBE_PHY) += amd-xgbe-phy.o obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c deleted file mode 100644 index fb276f64cd64..000000000000 --- a/drivers/net/phy/amd-xgbe-phy.c +++ /dev/null @@ -1,1862 +0,0 @@ -/* - * AMD 10Gb Ethernet PHY driver - * - * This file is available to you under your choice of the following two - * licenses: - * - * License 1: GPLv2 - * - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * This file is free software; you may copy, redistribute and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or (at - * your option) any later version. - * - * This file is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * - * License 2: Modified BSD - * - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -MODULE_AUTHOR("Tom Lendacky "); -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_VERSION("1.0.0-a"); -MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver"); - -#define XGBE_PHY_ID 0x000162d0 -#define XGBE_PHY_MASK 0xfffffff0 - -#define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set" -#define XGBE_PHY_BLWC_PROPERTY "amd,serdes-blwc" -#define XGBE_PHY_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" -#define XGBE_PHY_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" -#define XGBE_PHY_TX_AMP_PROPERTY "amd,serdes-tx-amp" -#define XGBE_PHY_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config" -#define XGBE_PHY_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable" - -#define XGBE_PHY_SPEEDS 3 -#define XGBE_PHY_SPEED_1000 0 -#define XGBE_PHY_SPEED_2500 1 -#define XGBE_PHY_SPEED_10000 2 - -#define XGBE_AN_MS_TIMEOUT 500 - -#define XGBE_AN_INT_CMPLT 0x01 -#define XGBE_AN_INC_LINK 0x02 -#define XGBE_AN_PG_RCV 0x04 -#define XGBE_AN_INT_MASK 0x07 - -#define XNP_MCF_NULL_MESSAGE 0x001 -#define XNP_ACK_PROCESSED BIT(12) -#define XNP_MP_FORMATTED BIT(13) -#define XNP_NP_EXCHANGE BIT(15) - -#define XGBE_PHY_RATECHANGE_COUNT 500 - -#define XGBE_PHY_KR_TRAINING_START 0x01 -#define XGBE_PHY_KR_TRAINING_ENABLE 0x02 - -#define XGBE_PHY_FEC_ENABLE 0x01 -#define XGBE_PHY_FEC_FORWARD 0x02 -#define XGBE_PHY_FEC_MASK 0x03 - -#ifndef MDIO_PMA_10GBR_PMD_CTRL -#define MDIO_PMA_10GBR_PMD_CTRL 0x0096 -#endif - -#ifndef MDIO_PMA_10GBR_FEC_ABILITY -#define MDIO_PMA_10GBR_FEC_ABILITY 0x00aa -#endif - -#ifndef MDIO_PMA_10GBR_FEC_CTRL -#define MDIO_PMA_10GBR_FEC_CTRL 0x00ab -#endif - -#ifndef MDIO_AN_XNP -#define MDIO_AN_XNP 0x0016 -#endif - -#ifndef MDIO_AN_LPX -#define MDIO_AN_LPX 0x0019 -#endif - -#ifndef MDIO_AN_INTMASK -#define MDIO_AN_INTMASK 0x8001 -#endif - -#ifndef MDIO_AN_INT -#define MDIO_AN_INT 0x8002 -#endif - -#ifndef MDIO_CTRL1_SPEED1G -#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) -#endif - -/* SerDes integration register offsets */ -#define SIR0_KR_RT_1 0x002c -#define SIR0_STATUS 0x0040 -#define SIR1_SPEED 0x0000 - -/* SerDes integration register entry bit positions and sizes */ -#define SIR0_KR_RT_1_RESET_INDEX 11 -#define SIR0_KR_RT_1_RESET_WIDTH 1 -#define SIR0_STATUS_RX_READY_INDEX 0 -#define SIR0_STATUS_RX_READY_WIDTH 1 -#define SIR0_STATUS_TX_READY_INDEX 8 -#define SIR0_STATUS_TX_READY_WIDTH 1 -#define SIR1_SPEED_CDR_RATE_INDEX 12 -#define SIR1_SPEED_CDR_RATE_WIDTH 4 -#define SIR1_SPEED_DATARATE_INDEX 4 -#define SIR1_SPEED_DATARATE_WIDTH 2 -#define SIR1_SPEED_PLLSEL_INDEX 3 -#define SIR1_SPEED_PLLSEL_WIDTH 1 -#define SIR1_SPEED_RATECHANGE_INDEX 6 -#define SIR1_SPEED_RATECHANGE_WIDTH 1 -#define SIR1_SPEED_TXAMP_INDEX 8 -#define SIR1_SPEED_TXAMP_WIDTH 4 -#define SIR1_SPEED_WORDMODE_INDEX 0 -#define SIR1_SPEED_WORDMODE_WIDTH 3 - -#define SPEED_10000_BLWC 0 -#define SPEED_10000_CDR 0x7 -#define SPEED_10000_PLL 0x1 -#define SPEED_10000_PQ 0x12 -#define SPEED_10000_RATE 0x0 -#define SPEED_10000_TXAMP 0xa -#define SPEED_10000_WORD 0x7 -#define SPEED_10000_DFE_TAP_CONFIG 0x1 -#define SPEED_10000_DFE_TAP_ENABLE 0x7f - -#define SPEED_2500_BLWC 1 -#define SPEED_2500_CDR 0x2 -#define SPEED_2500_PLL 0x0 -#define SPEED_2500_PQ 0xa -#define SPEED_2500_RATE 0x1 -#define SPEED_2500_TXAMP 0xf -#define SPEED_2500_WORD 0x1 -#define SPEED_2500_DFE_TAP_CONFIG 0x3 -#define SPEED_2500_DFE_TAP_ENABLE 0x0 - -#define SPEED_1000_BLWC 1 -#define SPEED_1000_CDR 0x2 -#define SPEED_1000_PLL 0x0 -#define SPEED_1000_PQ 0xa -#define SPEED_1000_RATE 0x3 -#define SPEED_1000_TXAMP 0xf -#define SPEED_1000_WORD 0x1 -#define SPEED_1000_DFE_TAP_CONFIG 0x3 -#define SPEED_1000_DFE_TAP_ENABLE 0x0 - -/* SerDes RxTx register offsets */ -#define RXTX_REG6 0x0018 -#define RXTX_REG20 0x0050 -#define RXTX_REG22 0x0058 -#define RXTX_REG114 0x01c8 -#define RXTX_REG129 0x0204 - -/* SerDes RxTx register entry bit positions and sizes */ -#define RXTX_REG6_RESETB_RXD_INDEX 8 -#define RXTX_REG6_RESETB_RXD_WIDTH 1 -#define RXTX_REG20_BLWC_ENA_INDEX 2 -#define RXTX_REG20_BLWC_ENA_WIDTH 1 -#define RXTX_REG114_PQ_REG_INDEX 9 -#define RXTX_REG114_PQ_REG_WIDTH 7 -#define RXTX_REG129_RXDFE_CONFIG_INDEX 14 -#define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 - -/* Bit setting and getting macros - * The get macro will extract the current bit field value from within - * the variable - * - * The set macro will clear the current bit field value within the - * variable and then set the bit field of the variable to the - * specified value - */ -#define GET_BITS(_var, _index, _width) \ - (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) - -#define SET_BITS(_var, _index, _width, _val) \ -do { \ - (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ - (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ -} while (0) - -#define XSIR_GET_BITS(_var, _prefix, _field) \ - GET_BITS((_var), \ - _prefix##_##_field##_INDEX, \ - _prefix##_##_field##_WIDTH) - -#define XSIR_SET_BITS(_var, _prefix, _field, _val) \ - SET_BITS((_var), \ - _prefix##_##_field##_INDEX, \ - _prefix##_##_field##_WIDTH, (_val)) - -/* Macros for reading or writing SerDes integration registers - * The ioread macros will get bit fields or full values using the - * register definitions formed using the input names - * - * The iowrite macros will set bit fields or full values using the - * register definitions formed using the input names - */ -#define XSIR0_IOREAD(_priv, _reg) \ - ioread16((_priv)->sir0_regs + _reg) - -#define XSIR0_IOREAD_BITS(_priv, _reg, _field) \ - GET_BITS(XSIR0_IOREAD((_priv), _reg), \ - _reg##_##_field##_INDEX, \ - _reg##_##_field##_WIDTH) - -#define XSIR0_IOWRITE(_priv, _reg, _val) \ - iowrite16((_val), (_priv)->sir0_regs + _reg) - -#define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \ -do { \ - u16 reg_val = XSIR0_IOREAD((_priv), _reg); \ - SET_BITS(reg_val, \ - _reg##_##_field##_INDEX, \ - _reg##_##_field##_WIDTH, (_val)); \ - XSIR0_IOWRITE((_priv), _reg, reg_val); \ -} while (0) - -#define XSIR1_IOREAD(_priv, _reg) \ - ioread16((_priv)->sir1_regs + _reg) - -#define XSIR1_IOREAD_BITS(_priv, _reg, _field) \ - GET_BITS(XSIR1_IOREAD((_priv), _reg), \ - _reg##_##_field##_INDEX, \ - _reg##_##_field##_WIDTH) - -#define XSIR1_IOWRITE(_priv, _reg, _val) \ - iowrite16((_val), (_priv)->sir1_regs + _reg) - -#define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \ -do { \ - u16 reg_val = XSIR1_IOREAD((_priv), _reg); \ - SET_BITS(reg_val, \ - _reg##_##_field##_INDEX, \ - _reg##_##_field##_WIDTH, (_val)); \ - XSIR1_IOWRITE((_priv), _reg, reg_val); \ -} while (0) - -/* Macros for reading or writing SerDes RxTx registers - * The ioread macros will get bit fields or full values using the - * register definitions formed using the input names - * - * The iowrite macros will set bit fields or full values using the - * register definitions formed using the input names - */ -#define XRXTX_IOREAD(_priv, _reg) \ - ioread16((_priv)->rxtx_regs + _reg) - -#define XRXTX_IOREAD_BITS(_priv, _reg, _field) \ - GET_BITS(XRXTX_IOREAD((_priv), _reg), \ - _reg##_##_field##_INDEX, \ - _reg##_##_field##_WIDTH) - -#define XRXTX_IOWRITE(_priv, _reg, _val) \ - iowrite16((_val), (_priv)->rxtx_regs + _reg) - -#define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \ -do { \ - u16 reg_val = XRXTX_IOREAD((_priv), _reg); \ - SET_BITS(reg_val, \ - _reg##_##_field##_INDEX, \ - _reg##_##_field##_WIDTH, (_val)); \ - XRXTX_IOWRITE((_priv), _reg, reg_val); \ -} while (0) - -static const u32 amd_xgbe_phy_serdes_blwc[] = { - SPEED_1000_BLWC, - SPEED_2500_BLWC, - SPEED_10000_BLWC, -}; - -static const u32 amd_xgbe_phy_serdes_cdr_rate[] = { - SPEED_1000_CDR, - SPEED_2500_CDR, - SPEED_10000_CDR, -}; - -static const u32 amd_xgbe_phy_serdes_pq_skew[] = { - SPEED_1000_PQ, - SPEED_2500_PQ, - SPEED_10000_PQ, -}; - -static const u32 amd_xgbe_phy_serdes_tx_amp[] = { - SPEED_1000_TXAMP, - SPEED_2500_TXAMP, - SPEED_10000_TXAMP, -}; - -static const u32 amd_xgbe_phy_serdes_dfe_tap_cfg[] = { - SPEED_1000_DFE_TAP_CONFIG, - SPEED_2500_DFE_TAP_CONFIG, - SPEED_10000_DFE_TAP_CONFIG, -}; - -static const u32 amd_xgbe_phy_serdes_dfe_tap_ena[] = { - SPEED_1000_DFE_TAP_ENABLE, - SPEED_2500_DFE_TAP_ENABLE, - SPEED_10000_DFE_TAP_ENABLE, -}; - -enum amd_xgbe_phy_an { - AMD_XGBE_AN_READY = 0, - AMD_XGBE_AN_PAGE_RECEIVED, - AMD_XGBE_AN_INCOMPAT_LINK, - AMD_XGBE_AN_COMPLETE, - AMD_XGBE_AN_NO_LINK, - AMD_XGBE_AN_ERROR, -}; - -enum amd_xgbe_phy_rx { - AMD_XGBE_RX_BPA = 0, - AMD_XGBE_RX_XNP, - AMD_XGBE_RX_COMPLETE, - AMD_XGBE_RX_ERROR, -}; - -enum amd_xgbe_phy_mode { - AMD_XGBE_MODE_KR, - AMD_XGBE_MODE_KX, -}; - -enum amd_xgbe_phy_speedset { - AMD_XGBE_PHY_SPEEDSET_1000_10000 = 0, - AMD_XGBE_PHY_SPEEDSET_2500_10000, -}; - -struct amd_xgbe_phy_priv { - struct platform_device *pdev; - struct acpi_device *adev; - struct device *dev; - - struct phy_device *phydev; - - /* SerDes related mmio resources */ - struct resource *rxtx_res; - struct resource *sir0_res; - struct resource *sir1_res; - - /* SerDes related mmio registers */ - void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ - void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ - void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ - - int an_irq; - char an_irq_name[IFNAMSIZ + 32]; - struct work_struct an_irq_work; - unsigned int an_irq_allocated; - - unsigned int speed_set; - - /* SerDes UEFI configurable settings. - * Switching between modes/speeds requires new values for some - * SerDes settings. The values can be supplied as device - * properties in array format. The first array entry is for - * 1GbE, second for 2.5GbE and third for 10GbE - */ - u32 serdes_blwc[XGBE_PHY_SPEEDS]; - u32 serdes_cdr_rate[XGBE_PHY_SPEEDS]; - u32 serdes_pq_skew[XGBE_PHY_SPEEDS]; - u32 serdes_tx_amp[XGBE_PHY_SPEEDS]; - u32 serdes_dfe_tap_cfg[XGBE_PHY_SPEEDS]; - u32 serdes_dfe_tap_ena[XGBE_PHY_SPEEDS]; - - /* Auto-negotiation state machine support */ - struct mutex an_mutex; - enum amd_xgbe_phy_an an_result; - enum amd_xgbe_phy_an an_state; - enum amd_xgbe_phy_rx kr_state; - enum amd_xgbe_phy_rx kx_state; - struct work_struct an_work; - struct workqueue_struct *an_workqueue; - unsigned int an_supported; - unsigned int parallel_detect; - unsigned int fec_ability; - unsigned long an_start; - - unsigned int lpm_ctrl; /* CTRL1 for resume */ -}; - -static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev) -{ - int ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); - if (ret < 0) - return ret; - - ret |= XGBE_PHY_KR_TRAINING_ENABLE; - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); - - return 0; -} - -static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev) -{ - int ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); - if (ret < 0) - return ret; - - ret &= ~XGBE_PHY_KR_TRAINING_ENABLE; - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); - - return 0; -} - -static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev) -{ - int ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret |= MDIO_CTRL1_LPOWER; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - usleep_range(75, 100); - - ret &= ~MDIO_CTRL1_LPOWER; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - return 0; -} - -static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - - /* Assert Rx and Tx ratechange */ - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1); -} - -static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - unsigned int wait; - u16 status; - - /* Release Rx and Tx ratechange */ - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0); - - /* Wait for Rx and Tx ready */ - wait = XGBE_PHY_RATECHANGE_COUNT; - while (wait--) { - usleep_range(50, 75); - - status = XSIR0_IOREAD(priv, SIR0_STATUS); - if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) && - XSIR_GET_BITS(status, SIR0_STATUS, TX_READY)) - goto rx_reset; - } - - netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n", - status); - -rx_reset: - /* Perform Rx reset for the DFE changes */ - XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RESETB_RXD, 0); - XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RESETB_RXD, 1); -} - -static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - /* Enable KR training */ - ret = amd_xgbe_an_enable_kr_training(phydev); - if (ret < 0) - return ret; - - /* Set PCS to KR/10G speed */ - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); - if (ret < 0) - return ret; - - ret &= ~MDIO_PCS_CTRL2_TYPE; - ret |= MDIO_PCS_CTRL2_10GBR; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret &= ~MDIO_CTRL1_SPEEDSEL; - ret |= MDIO_CTRL1_SPEED10G; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - ret = amd_xgbe_phy_pcs_power_cycle(phydev); - if (ret < 0) - return ret; - - /* Set SerDes to 10G speed */ - amd_xgbe_phy_serdes_start_ratechange(phydev); - - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL); - - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE, - priv->serdes_cdr_rate[XGBE_PHY_SPEED_10000]); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, - priv->serdes_tx_amp[XGBE_PHY_SPEED_10000]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, - priv->serdes_blwc[XGBE_PHY_SPEED_10000]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, - priv->serdes_pq_skew[XGBE_PHY_SPEED_10000]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG129, RXDFE_CONFIG, - priv->serdes_dfe_tap_cfg[XGBE_PHY_SPEED_10000]); - XRXTX_IOWRITE(priv, RXTX_REG22, - priv->serdes_dfe_tap_ena[XGBE_PHY_SPEED_10000]); - - amd_xgbe_phy_serdes_complete_ratechange(phydev); - - return 0; -} - -static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - /* Disable KR training */ - ret = amd_xgbe_an_disable_kr_training(phydev); - if (ret < 0) - return ret; - - /* Set PCS to KX/1G speed */ - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); - if (ret < 0) - return ret; - - ret &= ~MDIO_PCS_CTRL2_TYPE; - ret |= MDIO_PCS_CTRL2_10GBX; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret &= ~MDIO_CTRL1_SPEEDSEL; - ret |= MDIO_CTRL1_SPEED1G; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - ret = amd_xgbe_phy_pcs_power_cycle(phydev); - if (ret < 0) - return ret; - - /* Set SerDes to 2.5G speed */ - amd_xgbe_phy_serdes_start_ratechange(phydev); - - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL); - - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE, - priv->serdes_cdr_rate[XGBE_PHY_SPEED_2500]); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, - priv->serdes_tx_amp[XGBE_PHY_SPEED_2500]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, - priv->serdes_blwc[XGBE_PHY_SPEED_2500]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, - priv->serdes_pq_skew[XGBE_PHY_SPEED_2500]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG129, RXDFE_CONFIG, - priv->serdes_dfe_tap_cfg[XGBE_PHY_SPEED_2500]); - XRXTX_IOWRITE(priv, RXTX_REG22, - priv->serdes_dfe_tap_ena[XGBE_PHY_SPEED_2500]); - - amd_xgbe_phy_serdes_complete_ratechange(phydev); - - return 0; -} - -static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - /* Disable KR training */ - ret = amd_xgbe_an_disable_kr_training(phydev); - if (ret < 0) - return ret; - - /* Set PCS to KX/1G speed */ - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); - if (ret < 0) - return ret; - - ret &= ~MDIO_PCS_CTRL2_TYPE; - ret |= MDIO_PCS_CTRL2_10GBX; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret &= ~MDIO_CTRL1_SPEEDSEL; - ret |= MDIO_CTRL1_SPEED1G; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - ret = amd_xgbe_phy_pcs_power_cycle(phydev); - if (ret < 0) - return ret; - - /* Set SerDes to 1G speed */ - amd_xgbe_phy_serdes_start_ratechange(phydev); - - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL); - - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE, - priv->serdes_cdr_rate[XGBE_PHY_SPEED_1000]); - XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, - priv->serdes_tx_amp[XGBE_PHY_SPEED_1000]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, - priv->serdes_blwc[XGBE_PHY_SPEED_1000]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, - priv->serdes_pq_skew[XGBE_PHY_SPEED_1000]); - XRXTX_IOWRITE_BITS(priv, RXTX_REG129, RXDFE_CONFIG, - priv->serdes_dfe_tap_cfg[XGBE_PHY_SPEED_1000]); - XRXTX_IOWRITE(priv, RXTX_REG22, - priv->serdes_dfe_tap_ena[XGBE_PHY_SPEED_1000]); - - amd_xgbe_phy_serdes_complete_ratechange(phydev); - - return 0; -} - -static int amd_xgbe_phy_cur_mode(struct phy_device *phydev, - enum amd_xgbe_phy_mode *mode) -{ - int ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); - if (ret < 0) - return ret; - - if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR) - *mode = AMD_XGBE_MODE_KR; - else - *mode = AMD_XGBE_MODE_KX; - - return 0; -} - -static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev) -{ - enum amd_xgbe_phy_mode mode; - - if (amd_xgbe_phy_cur_mode(phydev, &mode)) - return false; - - return (mode == AMD_XGBE_MODE_KR); -} - -static int amd_xgbe_phy_switch_mode(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - /* If we are in KR switch to KX, and vice-versa */ - if (amd_xgbe_phy_in_kr_mode(phydev)) { - if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000) - ret = amd_xgbe_phy_gmii_mode(phydev); - else - ret = amd_xgbe_phy_gmii_2500_mode(phydev); - } else { - ret = amd_xgbe_phy_xgmii_mode(phydev); - } - - return ret; -} - -static int amd_xgbe_phy_set_mode(struct phy_device *phydev, - enum amd_xgbe_phy_mode mode) -{ - enum amd_xgbe_phy_mode cur_mode; - int ret; - - ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode); - if (ret) - return ret; - - if (mode != cur_mode) - ret = amd_xgbe_phy_switch_mode(phydev); - - return ret; -} - -static int amd_xgbe_phy_set_an(struct phy_device *phydev, bool enable, - bool restart) -{ - int ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret &= ~MDIO_AN_CTRL1_ENABLE; - - if (enable) - ret |= MDIO_AN_CTRL1_ENABLE; - - if (restart) - ret |= MDIO_AN_CTRL1_RESTART; - - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret); - - return 0; -} - -static int amd_xgbe_phy_restart_an(struct phy_device *phydev) -{ - return amd_xgbe_phy_set_an(phydev, true, true); -} - -static int amd_xgbe_phy_disable_an(struct phy_device *phydev) -{ - return amd_xgbe_phy_set_an(phydev, false, false); -} - -static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev, - enum amd_xgbe_phy_rx *state) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ad_reg, lp_reg, ret; - - *state = AMD_XGBE_RX_COMPLETE; - - /* If we're not in KR mode then we're done */ - if (!amd_xgbe_phy_in_kr_mode(phydev)) - return AMD_XGBE_AN_PAGE_RECEIVED; - - /* Enable/Disable FEC */ - ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); - if (ad_reg < 0) - return AMD_XGBE_AN_ERROR; - - lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2); - if (lp_reg < 0) - return AMD_XGBE_AN_ERROR; - - ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL); - if (ret < 0) - return AMD_XGBE_AN_ERROR; - - ret &= ~XGBE_PHY_FEC_MASK; - if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) - ret |= priv->fec_ability; - - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret); - - /* Start KR training */ - ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); - if (ret < 0) - return AMD_XGBE_AN_ERROR; - - if (ret & XGBE_PHY_KR_TRAINING_ENABLE) { - XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1); - - ret |= XGBE_PHY_KR_TRAINING_START; - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, - ret); - - XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0); - } - - return AMD_XGBE_AN_PAGE_RECEIVED; -} - -static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev, - enum amd_xgbe_phy_rx *state) -{ - u16 msg; - - *state = AMD_XGBE_RX_XNP; - - msg = XNP_MCF_NULL_MESSAGE; - msg |= XNP_MP_FORMATTED; - - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg); - - return AMD_XGBE_AN_PAGE_RECEIVED; -} - -static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev, - enum amd_xgbe_phy_rx *state) -{ - unsigned int link_support; - int ret, ad_reg, lp_reg; - - /* Read Base Ability register 2 first */ - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1); - if (ret < 0) - return AMD_XGBE_AN_ERROR; - - /* Check for a supported mode, otherwise restart in a different one */ - link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20; - if (!(ret & link_support)) - return AMD_XGBE_AN_INCOMPAT_LINK; - - /* Check Extended Next Page support */ - ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); - if (ad_reg < 0) - return AMD_XGBE_AN_ERROR; - - lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); - if (lp_reg < 0) - return AMD_XGBE_AN_ERROR; - - return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ? - amd_xgbe_an_tx_xnp(phydev, state) : - amd_xgbe_an_tx_training(phydev, state); -} - -static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev, - enum amd_xgbe_phy_rx *state) -{ - int ad_reg, lp_reg; - - /* Check Extended Next Page support */ - ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP); - if (ad_reg < 0) - return AMD_XGBE_AN_ERROR; - - lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX); - if (lp_reg < 0) - return AMD_XGBE_AN_ERROR; - - return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ? - amd_xgbe_an_tx_xnp(phydev, state) : - amd_xgbe_an_tx_training(phydev, state); -} - -static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - enum amd_xgbe_phy_rx *state; - unsigned long an_timeout; - int ret; - - if (!priv->an_start) { - priv->an_start = jiffies; - } else { - an_timeout = priv->an_start + - msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); - if (time_after(jiffies, an_timeout)) { - /* Auto-negotiation timed out, reset state */ - priv->kr_state = AMD_XGBE_RX_BPA; - priv->kx_state = AMD_XGBE_RX_BPA; - - priv->an_start = jiffies; - } - } - - state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state - : &priv->kx_state; - - switch (*state) { - case AMD_XGBE_RX_BPA: - ret = amd_xgbe_an_rx_bpa(phydev, state); - break; - - case AMD_XGBE_RX_XNP: - ret = amd_xgbe_an_rx_xnp(phydev, state); - break; - - default: - ret = AMD_XGBE_AN_ERROR; - } - - return ret; -} - -static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - /* Be sure we aren't looping trying to negotiate */ - if (amd_xgbe_phy_in_kr_mode(phydev)) { - priv->kr_state = AMD_XGBE_RX_ERROR; - - if (!(phydev->advertising & SUPPORTED_1000baseKX_Full) && - !(phydev->advertising & SUPPORTED_2500baseX_Full)) - return AMD_XGBE_AN_NO_LINK; - - if (priv->kx_state != AMD_XGBE_RX_BPA) - return AMD_XGBE_AN_NO_LINK; - } else { - priv->kx_state = AMD_XGBE_RX_ERROR; - - if (!(phydev->advertising & SUPPORTED_10000baseKR_Full)) - return AMD_XGBE_AN_NO_LINK; - - if (priv->kr_state != AMD_XGBE_RX_BPA) - return AMD_XGBE_AN_NO_LINK; - } - - ret = amd_xgbe_phy_disable_an(phydev); - if (ret) - return AMD_XGBE_AN_ERROR; - - ret = amd_xgbe_phy_switch_mode(phydev); - if (ret) - return AMD_XGBE_AN_ERROR; - - ret = amd_xgbe_phy_restart_an(phydev); - if (ret) - return AMD_XGBE_AN_ERROR; - - return AMD_XGBE_AN_INCOMPAT_LINK; -} - -static irqreturn_t amd_xgbe_an_isr(int irq, void *data) -{ - struct amd_xgbe_phy_priv *priv = (struct amd_xgbe_phy_priv *)data; - - /* Interrupt reason must be read and cleared outside of IRQ context */ - disable_irq_nosync(priv->an_irq); - - queue_work(priv->an_workqueue, &priv->an_irq_work); - - return IRQ_HANDLED; -} - -static void amd_xgbe_an_irq_work(struct work_struct *work) -{ - struct amd_xgbe_phy_priv *priv = container_of(work, - struct amd_xgbe_phy_priv, - an_irq_work); - - /* Avoid a race between enabling the IRQ and exiting the work by - * waiting for the work to finish and then queueing it - */ - flush_work(&priv->an_work); - queue_work(priv->an_workqueue, &priv->an_work); -} - -static void amd_xgbe_an_state_machine(struct work_struct *work) -{ - struct amd_xgbe_phy_priv *priv = container_of(work, - struct amd_xgbe_phy_priv, - an_work); - struct phy_device *phydev = priv->phydev; - enum amd_xgbe_phy_an cur_state = priv->an_state; - int int_reg, int_mask; - - mutex_lock(&priv->an_mutex); - - /* Read the interrupt */ - int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT); - if (!int_reg) - goto out; - -next_int: - if (int_reg < 0) { - priv->an_state = AMD_XGBE_AN_ERROR; - int_mask = XGBE_AN_INT_MASK; - } else if (int_reg & XGBE_AN_PG_RCV) { - priv->an_state = AMD_XGBE_AN_PAGE_RECEIVED; - int_mask = XGBE_AN_PG_RCV; - } else if (int_reg & XGBE_AN_INC_LINK) { - priv->an_state = AMD_XGBE_AN_INCOMPAT_LINK; - int_mask = XGBE_AN_INC_LINK; - } else if (int_reg & XGBE_AN_INT_CMPLT) { - priv->an_state = AMD_XGBE_AN_COMPLETE; - int_mask = XGBE_AN_INT_CMPLT; - } else { - priv->an_state = AMD_XGBE_AN_ERROR; - int_mask = 0; - } - - /* Clear the interrupt to be processed */ - int_reg &= ~int_mask; - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg); - - priv->an_result = priv->an_state; - -again: - cur_state = priv->an_state; - - switch (priv->an_state) { - case AMD_XGBE_AN_READY: - priv->an_supported = 0; - break; - - case AMD_XGBE_AN_PAGE_RECEIVED: - priv->an_state = amd_xgbe_an_page_received(phydev); - priv->an_supported++; - break; - - case AMD_XGBE_AN_INCOMPAT_LINK: - priv->an_supported = 0; - priv->parallel_detect = 0; - priv->an_state = amd_xgbe_an_incompat_link(phydev); - break; - - case AMD_XGBE_AN_COMPLETE: - priv->parallel_detect = priv->an_supported ? 0 : 1; - netdev_dbg(phydev->attached_dev, "%s successful\n", - priv->an_supported ? "Auto negotiation" - : "Parallel detection"); - break; - - case AMD_XGBE_AN_NO_LINK: - break; - - default: - priv->an_state = AMD_XGBE_AN_ERROR; - } - - if (priv->an_state == AMD_XGBE_AN_NO_LINK) { - int_reg = 0; - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); - } else if (priv->an_state == AMD_XGBE_AN_ERROR) { - netdev_err(phydev->attached_dev, - "error during auto-negotiation, state=%u\n", - cur_state); - - int_reg = 0; - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); - } - - if (priv->an_state >= AMD_XGBE_AN_COMPLETE) { - priv->an_result = priv->an_state; - priv->an_state = AMD_XGBE_AN_READY; - priv->kr_state = AMD_XGBE_RX_BPA; - priv->kx_state = AMD_XGBE_RX_BPA; - priv->an_start = 0; - } - - if (cur_state != priv->an_state) - goto again; - - if (int_reg) - goto next_int; - -out: - enable_irq(priv->an_irq); - - mutex_unlock(&priv->an_mutex); -} - -static int amd_xgbe_an_init(struct phy_device *phydev) -{ - int ret; - - /* Set up Advertisement register 3 first */ - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); - if (ret < 0) - return ret; - - if (phydev->advertising & SUPPORTED_10000baseR_FEC) - ret |= 0xc000; - else - ret &= ~0xc000; - - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret); - - /* Set up Advertisement register 2 next */ - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); - if (ret < 0) - return ret; - - if (phydev->advertising & SUPPORTED_10000baseKR_Full) - ret |= 0x80; - else - ret &= ~0x80; - - if ((phydev->advertising & SUPPORTED_1000baseKX_Full) || - (phydev->advertising & SUPPORTED_2500baseX_Full)) - ret |= 0x20; - else - ret &= ~0x20; - - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret); - - /* Set up Advertisement register 1 last */ - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); - if (ret < 0) - return ret; - - if (phydev->advertising & SUPPORTED_Pause) - ret |= 0x400; - else - ret &= ~0x400; - - if (phydev->advertising & SUPPORTED_Asym_Pause) - ret |= 0x800; - else - ret &= ~0x800; - - /* We don't intend to perform XNP */ - ret &= ~XNP_NP_EXCHANGE; - - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret); - - return 0; -} - -static int amd_xgbe_phy_soft_reset(struct phy_device *phydev) -{ - int count, ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret |= MDIO_CTRL1_RESET; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - count = 50; - do { - msleep(20); - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - return ret; - } while ((ret & MDIO_CTRL1_RESET) && --count); - - if (ret & MDIO_CTRL1_RESET) - return -ETIMEDOUT; - - /* Disable auto-negotiation for now */ - ret = amd_xgbe_phy_disable_an(phydev); - if (ret < 0) - return ret; - - /* Clear auto-negotiation interrupts */ - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); - - return 0; -} - -static int amd_xgbe_phy_config_init(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - struct net_device *netdev = phydev->attached_dev; - int ret; - - if (!priv->an_irq_allocated) { - /* Allocate the auto-negotiation workqueue and interrupt */ - snprintf(priv->an_irq_name, sizeof(priv->an_irq_name) - 1, - "%s-pcs", netdev_name(netdev)); - - priv->an_workqueue = - create_singlethread_workqueue(priv->an_irq_name); - if (!priv->an_workqueue) { - netdev_err(netdev, "phy workqueue creation failed\n"); - return -ENOMEM; - } - - ret = devm_request_irq(priv->dev, priv->an_irq, - amd_xgbe_an_isr, 0, priv->an_irq_name, - priv); - if (ret) { - netdev_err(netdev, "phy irq request failed\n"); - destroy_workqueue(priv->an_workqueue); - return ret; - } - - priv->an_irq_allocated = 1; - } - - /* Set initial mode - call the mode setting routines - * directly to insure we are properly configured - */ - if (phydev->advertising & SUPPORTED_10000baseKR_Full) - ret = amd_xgbe_phy_xgmii_mode(phydev); - else if (phydev->advertising & SUPPORTED_1000baseKX_Full) - ret = amd_xgbe_phy_gmii_mode(phydev); - else if (phydev->advertising & SUPPORTED_2500baseX_Full) - ret = amd_xgbe_phy_gmii_2500_mode(phydev); - else - ret = -EINVAL; - if (ret < 0) - return ret; - - /* Set up advertisement registers based on current settings */ - ret = amd_xgbe_an_init(phydev); - if (ret) - return ret; - - /* Enable auto-negotiation interrupts */ - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); - - return 0; -} - -static int amd_xgbe_phy_setup_forced(struct phy_device *phydev) -{ - int ret; - - /* Disable auto-negotiation */ - ret = amd_xgbe_phy_disable_an(phydev); - if (ret < 0) - return ret; - - /* Validate/Set specified speed */ - switch (phydev->speed) { - case SPEED_10000: - ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); - break; - - case SPEED_2500: - case SPEED_1000: - ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); - break; - - default: - ret = -EINVAL; - } - - if (ret < 0) - return ret; - - /* Validate duplex mode */ - if (phydev->duplex != DUPLEX_FULL) - return -EINVAL; - - phydev->pause = 0; - phydev->asym_pause = 0; - - return 0; -} - -static int __amd_xgbe_phy_config_aneg(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - u32 mmd_mask = phydev->c45_ids.devices_in_package; - int ret; - - if (phydev->autoneg != AUTONEG_ENABLE) - return amd_xgbe_phy_setup_forced(phydev); - - /* Make sure we have the AN MMD present */ - if (!(mmd_mask & MDIO_DEVS_AN)) - return -EINVAL; - - /* Disable auto-negotiation interrupt */ - disable_irq(priv->an_irq); - - /* Start auto-negotiation in a supported mode */ - if (phydev->advertising & SUPPORTED_10000baseKR_Full) - ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); - else if ((phydev->advertising & SUPPORTED_1000baseKX_Full) || - (phydev->advertising & SUPPORTED_2500baseX_Full)) - ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); - else - ret = -EINVAL; - if (ret < 0) { - enable_irq(priv->an_irq); - return ret; - } - - /* Disable and stop any in progress auto-negotiation */ - ret = amd_xgbe_phy_disable_an(phydev); - if (ret < 0) - return ret; - - /* Clear any auto-negotitation interrupts */ - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); - - priv->an_result = AMD_XGBE_AN_READY; - priv->an_state = AMD_XGBE_AN_READY; - priv->kr_state = AMD_XGBE_RX_BPA; - priv->kx_state = AMD_XGBE_RX_BPA; - - /* Re-enable auto-negotiation interrupt */ - enable_irq(priv->an_irq); - - /* Set up advertisement registers based on current settings */ - ret = amd_xgbe_an_init(phydev); - if (ret) - return ret; - - /* Enable and start auto-negotiation */ - return amd_xgbe_phy_restart_an(phydev); -} - -static int amd_xgbe_phy_config_aneg(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - mutex_lock(&priv->an_mutex); - - ret = __amd_xgbe_phy_config_aneg(phydev); - - mutex_unlock(&priv->an_mutex); - - return ret; -} - -static int amd_xgbe_phy_aneg_done(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - - return (priv->an_result == AMD_XGBE_AN_COMPLETE); -} - -static int amd_xgbe_phy_update_link(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - /* If we're doing auto-negotiation don't report link down */ - if (priv->an_state != AMD_XGBE_AN_READY) { - phydev->link = 1; - return 0; - } - - /* Link status is latched low, so read once to clear - * and then read again to get current state - */ - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); - if (ret < 0) - return ret; - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); - if (ret < 0) - return ret; - - phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0; - - return 0; -} - -static int amd_xgbe_phy_read_status(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - u32 mmd_mask = phydev->c45_ids.devices_in_package; - int ret, ad_ret, lp_ret; - - ret = amd_xgbe_phy_update_link(phydev); - if (ret) - return ret; - - if ((phydev->autoneg == AUTONEG_ENABLE) && - !priv->parallel_detect) { - if (!(mmd_mask & MDIO_DEVS_AN)) - return -EINVAL; - - if (!amd_xgbe_phy_aneg_done(phydev)) - return 0; - - /* Compare Advertisement and Link Partner register 1 */ - ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); - if (ad_ret < 0) - return ad_ret; - lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); - if (lp_ret < 0) - return lp_ret; - - ad_ret &= lp_ret; - phydev->pause = (ad_ret & 0x400) ? 1 : 0; - phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0; - - /* Compare Advertisement and Link Partner register 2 */ - ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, - MDIO_AN_ADVERTISE + 1); - if (ad_ret < 0) - return ad_ret; - lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1); - if (lp_ret < 0) - return lp_ret; - - ad_ret &= lp_ret; - if (ad_ret & 0x80) { - phydev->speed = SPEED_10000; - ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); - if (ret) - return ret; - } else { - switch (priv->speed_set) { - case AMD_XGBE_PHY_SPEEDSET_1000_10000: - phydev->speed = SPEED_1000; - break; - - case AMD_XGBE_PHY_SPEEDSET_2500_10000: - phydev->speed = SPEED_2500; - break; - } - - ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); - if (ret) - return ret; - } - - phydev->duplex = DUPLEX_FULL; - } else { - if (amd_xgbe_phy_in_kr_mode(phydev)) { - phydev->speed = SPEED_10000; - } else { - switch (priv->speed_set) { - case AMD_XGBE_PHY_SPEEDSET_1000_10000: - phydev->speed = SPEED_1000; - break; - - case AMD_XGBE_PHY_SPEEDSET_2500_10000: - phydev->speed = SPEED_2500; - break; - } - } - phydev->duplex = DUPLEX_FULL; - phydev->pause = 0; - phydev->asym_pause = 0; - } - - return 0; -} - -static int amd_xgbe_phy_suspend(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - int ret; - - mutex_lock(&phydev->lock); - - ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); - if (ret < 0) - goto unlock; - - priv->lpm_ctrl = ret; - - ret |= MDIO_CTRL1_LPOWER; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); - - ret = 0; - -unlock: - mutex_unlock(&phydev->lock); - - return ret; -} - -static int amd_xgbe_phy_resume(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - - mutex_lock(&phydev->lock); - - priv->lpm_ctrl &= ~MDIO_CTRL1_LPOWER; - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, priv->lpm_ctrl); - - mutex_unlock(&phydev->lock); - - return 0; -} - -static unsigned int amd_xgbe_phy_resource_count(struct platform_device *pdev, - unsigned int type) -{ - unsigned int count; - int i; - - for (i = 0, count = 0; i < pdev->num_resources; i++) { - struct resource *r = &pdev->resource[i]; - - if (type == resource_type(r)) - count++; - } - - return count; -} - -static int amd_xgbe_phy_probe(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv; - struct platform_device *phy_pdev; - struct device *dev, *phy_dev; - unsigned int phy_resnum, phy_irqnum; - int ret; - - if (!phydev->bus || !phydev->bus->parent) - return -EINVAL; - - dev = phydev->bus->parent; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->pdev = to_platform_device(dev); - priv->adev = ACPI_COMPANION(dev); - priv->dev = dev; - priv->phydev = phydev; - mutex_init(&priv->an_mutex); - INIT_WORK(&priv->an_irq_work, amd_xgbe_an_irq_work); - INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine); - - if (!priv->adev || acpi_disabled) { - struct device_node *bus_node; - struct device_node *phy_node; - - bus_node = priv->dev->of_node; - phy_node = of_parse_phandle(bus_node, "phy-handle", 0); - if (!phy_node) { - dev_err(dev, "unable to parse phy-handle\n"); - ret = -EINVAL; - goto err_priv; - } - - phy_pdev = of_find_device_by_node(phy_node); - of_node_put(phy_node); - - if (!phy_pdev) { - dev_err(dev, "unable to obtain phy device\n"); - ret = -EINVAL; - goto err_priv; - } - - phy_resnum = 0; - phy_irqnum = 0; - } else { - /* In ACPI, the XGBE and PHY resources are the grouped - * together with the PHY resources at the end - */ - phy_pdev = priv->pdev; - phy_resnum = amd_xgbe_phy_resource_count(phy_pdev, - IORESOURCE_MEM) - 3; - phy_irqnum = amd_xgbe_phy_resource_count(phy_pdev, - IORESOURCE_IRQ) - 1; - } - phy_dev = &phy_pdev->dev; - - /* Get the device mmio areas */ - priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, - phy_resnum++); - priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res); - if (IS_ERR(priv->rxtx_regs)) { - dev_err(dev, "rxtx ioremap failed\n"); - ret = PTR_ERR(priv->rxtx_regs); - goto err_put; - } - - priv->sir0_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, - phy_resnum++); - priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res); - if (IS_ERR(priv->sir0_regs)) { - dev_err(dev, "sir0 ioremap failed\n"); - ret = PTR_ERR(priv->sir0_regs); - goto err_rxtx; - } - - priv->sir1_res = platform_get_resource(phy_pdev, IORESOURCE_MEM, - phy_resnum++); - priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res); - if (IS_ERR(priv->sir1_regs)) { - dev_err(dev, "sir1 ioremap failed\n"); - ret = PTR_ERR(priv->sir1_regs); - goto err_sir0; - } - - /* Get the auto-negotiation interrupt */ - ret = platform_get_irq(phy_pdev, phy_irqnum); - if (ret < 0) { - dev_err(dev, "platform_get_irq failed\n"); - goto err_sir1; - } - priv->an_irq = ret; - - /* Get the device speed set property */ - ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY, - &priv->speed_set); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_SPEEDSET_PROPERTY); - goto err_sir1; - } - - switch (priv->speed_set) { - case AMD_XGBE_PHY_SPEEDSET_1000_10000: - case AMD_XGBE_PHY_SPEEDSET_2500_10000: - break; - default: - dev_err(dev, "invalid %s property\n", - XGBE_PHY_SPEEDSET_PROPERTY); - ret = -EINVAL; - goto err_sir1; - } - - if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) { - ret = device_property_read_u32_array(phy_dev, - XGBE_PHY_BLWC_PROPERTY, - priv->serdes_blwc, - XGBE_PHY_SPEEDS); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_BLWC_PROPERTY); - goto err_sir1; - } - } else { - memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc, - sizeof(priv->serdes_blwc)); - } - - if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) { - ret = device_property_read_u32_array(phy_dev, - XGBE_PHY_CDR_RATE_PROPERTY, - priv->serdes_cdr_rate, - XGBE_PHY_SPEEDS); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_CDR_RATE_PROPERTY); - goto err_sir1; - } - } else { - memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate, - sizeof(priv->serdes_cdr_rate)); - } - - if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) { - ret = device_property_read_u32_array(phy_dev, - XGBE_PHY_PQ_SKEW_PROPERTY, - priv->serdes_pq_skew, - XGBE_PHY_SPEEDS); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_PQ_SKEW_PROPERTY); - goto err_sir1; - } - } else { - memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew, - sizeof(priv->serdes_pq_skew)); - } - - if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) { - ret = device_property_read_u32_array(phy_dev, - XGBE_PHY_TX_AMP_PROPERTY, - priv->serdes_tx_amp, - XGBE_PHY_SPEEDS); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_TX_AMP_PROPERTY); - goto err_sir1; - } - } else { - memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp, - sizeof(priv->serdes_tx_amp)); - } - - if (device_property_present(phy_dev, XGBE_PHY_DFE_CFG_PROPERTY)) { - ret = device_property_read_u32_array(phy_dev, - XGBE_PHY_DFE_CFG_PROPERTY, - priv->serdes_dfe_tap_cfg, - XGBE_PHY_SPEEDS); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_DFE_CFG_PROPERTY); - goto err_sir1; - } - } else { - memcpy(priv->serdes_dfe_tap_cfg, - amd_xgbe_phy_serdes_dfe_tap_cfg, - sizeof(priv->serdes_dfe_tap_cfg)); - } - - if (device_property_present(phy_dev, XGBE_PHY_DFE_ENA_PROPERTY)) { - ret = device_property_read_u32_array(phy_dev, - XGBE_PHY_DFE_ENA_PROPERTY, - priv->serdes_dfe_tap_ena, - XGBE_PHY_SPEEDS); - if (ret) { - dev_err(dev, "invalid %s property\n", - XGBE_PHY_DFE_ENA_PROPERTY); - goto err_sir1; - } - } else { - memcpy(priv->serdes_dfe_tap_ena, - amd_xgbe_phy_serdes_dfe_tap_ena, - sizeof(priv->serdes_dfe_tap_ena)); - } - - /* Initialize supported features */ - phydev->supported = SUPPORTED_Autoneg; - phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; - phydev->supported |= SUPPORTED_Backplane; - phydev->supported |= SUPPORTED_10000baseKR_Full; - switch (priv->speed_set) { - case AMD_XGBE_PHY_SPEEDSET_1000_10000: - phydev->supported |= SUPPORTED_1000baseKX_Full; - break; - case AMD_XGBE_PHY_SPEEDSET_2500_10000: - phydev->supported |= SUPPORTED_2500baseX_Full; - break; - } - - ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY); - if (ret < 0) - return ret; - priv->fec_ability = ret & XGBE_PHY_FEC_MASK; - if (priv->fec_ability & XGBE_PHY_FEC_ENABLE) - phydev->supported |= SUPPORTED_10000baseR_FEC; - - phydev->advertising = phydev->supported; - - phydev->priv = priv; - - if (!priv->adev || acpi_disabled) - platform_device_put(phy_pdev); - - return 0; - -err_sir1: - devm_iounmap(dev, priv->sir1_regs); - devm_release_mem_region(dev, priv->sir1_res->start, - resource_size(priv->sir1_res)); - -err_sir0: - devm_iounmap(dev, priv->sir0_regs); - devm_release_mem_region(dev, priv->sir0_res->start, - resource_size(priv->sir0_res)); - -err_rxtx: - devm_iounmap(dev, priv->rxtx_regs); - devm_release_mem_region(dev, priv->rxtx_res->start, - resource_size(priv->rxtx_res)); - -err_put: - if (!priv->adev || acpi_disabled) - platform_device_put(phy_pdev); - -err_priv: - devm_kfree(dev, priv); - - return ret; -} - -static void amd_xgbe_phy_remove(struct phy_device *phydev) -{ - struct amd_xgbe_phy_priv *priv = phydev->priv; - struct device *dev = priv->dev; - - if (priv->an_irq_allocated) { - devm_free_irq(dev, priv->an_irq, priv); - - flush_workqueue(priv->an_workqueue); - destroy_workqueue(priv->an_workqueue); - } - - /* Release resources */ - devm_iounmap(dev, priv->sir1_regs); - devm_release_mem_region(dev, priv->sir1_res->start, - resource_size(priv->sir1_res)); - - devm_iounmap(dev, priv->sir0_regs); - devm_release_mem_region(dev, priv->sir0_res->start, - resource_size(priv->sir0_res)); - - devm_iounmap(dev, priv->rxtx_regs); - devm_release_mem_region(dev, priv->rxtx_res->start, - resource_size(priv->rxtx_res)); - - devm_kfree(dev, priv); -} - -static int amd_xgbe_match_phy_device(struct phy_device *phydev) -{ - return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID; -} - -static struct phy_driver amd_xgbe_phy_driver[] = { - { - .phy_id = XGBE_PHY_ID, - .phy_id_mask = XGBE_PHY_MASK, - .name = "AMD XGBE PHY", - .features = 0, - .flags = PHY_IS_INTERNAL, - .probe = amd_xgbe_phy_probe, - .remove = amd_xgbe_phy_remove, - .soft_reset = amd_xgbe_phy_soft_reset, - .config_init = amd_xgbe_phy_config_init, - .suspend = amd_xgbe_phy_suspend, - .resume = amd_xgbe_phy_resume, - .config_aneg = amd_xgbe_phy_config_aneg, - .aneg_done = amd_xgbe_phy_aneg_done, - .read_status = amd_xgbe_phy_read_status, - .match_phy_device = amd_xgbe_match_phy_device, - .driver = { - .owner = THIS_MODULE, - }, - }, -}; - -module_phy_driver(amd_xgbe_phy_driver); - -static struct mdio_device_id __maybe_unused amd_xgbe_phy_ids[] = { - { XGBE_PHY_ID, XGBE_PHY_MASK }, - { } -}; -MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_ids); -- cgit v1.2.3 From 34bfff404ca2eb2f0e60f82f301ad6abcdd22150 Mon Sep 17 00:00:00 2001 From: "Lendacky, Thomas" Date: Thu, 14 May 2015 11:44:21 -0500 Subject: amd-xgbe: Support defining PHY resources in ETH device node Simplify the device tree support of the amd-xgbe driver by defining the PHY-related resources within the ethernet device node. The support provides backwards compatibility with the original way. Update the driver version to 1.0.2. Signed-off-by: Tom Lendacky Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/amd-xgbe.txt | 41 +++++++--------------- drivers/net/ethernet/amd/xgbe/xgbe-main.c | 23 +++++++----- drivers/net/ethernet/amd/xgbe/xgbe.h | 2 +- 3 files changed, 29 insertions(+), 37 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt index 5dbc55a2db90..4bb624a73b54 100644 --- a/Documentation/devicetree/bindings/net/amd-xgbe.txt +++ b/Documentation/devicetree/bindings/net/amd-xgbe.txt @@ -1,16 +1,20 @@ * AMD 10GbE driver (amd-xgbe) -Required properties (ethernet device): +Required properties: - compatible: Should be "amd,xgbe-seattle-v1a" - reg: Address and length of the register sets for the device - MAC registers - PCS registers + - SerDes Rx/Tx registers + - SerDes integration registers (1/2) + - SerDes integration registers (2/2) - interrupt-parent: Should be the phandle for the interrupt controller that services interrupts for this device - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt listed is required and is the general device interrupt. If the optional amd,per-channel-interrupt property is specified, then one additional - interrupt for each DMA channel supported by the device should be specified + interrupt for each DMA channel supported by the device should be specified. + The last interrupt listed should be the PCS auto-negotiation interrupt. - clocks: - DMA clock for the amd-xgbe device (used for calculating the correct Rx interrupt watchdog timer value on a DMA channel @@ -19,28 +23,15 @@ Required properties (ethernet device): - clock-names: Should be the names of the clocks - "dma_clk" for the DMA clock - "ptp_clk" for the PTP clock -- phy-handle: See ethernet.txt file in the same directory - phy-mode: See ethernet.txt file in the same directory -Optional properties (ethernet device): +Optional properties: - mac-address: mac address to be assigned to the device. Can be overridden by UEFI. - dma-coherent: Present if dma operations are coherent - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate a unique interrupt for each DMA channel - this requires an additional interrupt be configured for each DMA channel - -Required properties (phy device): -- compatible: Should be "amd,xgbe-phy-seattle-v1a" -- reg: Address and length of the register sets for the device - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device -- interrupts: Should contain the amd-xgbe-phy interrupt. - -Optional properties (phy device): - amd,speed-set: Speed capabilities of the device 0 - 1GbE and 10GbE (default) 1 - 2.5GbE and 10GbE @@ -63,25 +54,19 @@ Example: xgbe@e0700000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>; + <0 0xe0780000 0 0x80000>, + <0 0xe1240800 0 0x00400>, + <0 0xe1250000 0 0x00060>, + <0 0xe1250080 0 0x00004>; interrupt-parent = <&gic>; interrupts = <0 325 4>, - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>; + <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, + <0 323 4>; amd,per-channel-interrupt; clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; clock-names = "dma_clk", "ptp_clk"; - phy-handle = <&xgbe_phy>; phy-mode = "xgmii"; mac-address = [ 02 a1 a2 a3 a4 a5 ]; - }; - - xgbe_phy@e1240800 { - compatible = "amd,xgbe-phy-seattle-v1a"; - reg = <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 323 4>; amd,speed-set = <0>; amd,serdes-blwc = <1>, <1>, <0>; amd,serdes-cdr-rate = <2>, <2>, <7>; diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c index 0c219b30c129..34c521d8b578 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c @@ -300,14 +300,21 @@ static struct platform_device *xgbe_of_get_phy_pdev(struct xgbe_prv_data *pdata) struct platform_device *phy_pdev; phy_node = of_parse_phandle(dev->of_node, "phy-handle", 0); - if (!phy_node) { - dev_err(dev, "unable to locate phy device\n"); - return NULL; + if (phy_node) { + /* Old style device tree: + * The XGBE and PHY resources are separate + */ + phy_pdev = of_find_device_by_node(phy_node); + of_node_put(phy_node); + } else { + /* New style device tree: + * The XGBE and PHY resources are grouped together with + * the PHY resources listed last + */ + get_device(dev); + phy_pdev = pdata->pdev; } - phy_pdev = of_find_device_by_node(phy_node); - of_node_put(phy_node); - return phy_pdev; } #else /* CONFIG_OF */ @@ -401,14 +408,14 @@ static int xgbe_probe(struct platform_device *pdev) phy_dev = &phy_pdev->dev; if (pdev == phy_pdev) { - /* ACPI: + /* New style device tree or ACPI: * The XGBE and PHY resources are grouped together with * the PHY resources listed last */ phy_memnum = xgbe_resource_count(pdev, IORESOURCE_MEM) - 3; phy_irqnum = xgbe_resource_count(pdev, IORESOURCE_IRQ) - 1; } else { - /* Device tree: + /* Old style device tree: * The XGBE and PHY resources are separate */ phy_memnum = 0; diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h index b6aecc95e63f..f535d19da803 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h @@ -129,7 +129,7 @@ #include #define XGBE_DRV_NAME "amd-xgbe" -#define XGBE_DRV_VERSION "1.0.1" +#define XGBE_DRV_VERSION "1.0.2" #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" /* Descriptor related defines */ -- cgit v1.2.3 From 8a3d9c164152e461e5f80db65aaaa0fbfdb2eed3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 11 May 2015 17:25:19 -0500 Subject: dt-bindings: Add pxa1928 clock binding This adds the clock binding documentation for the Marvell PXA1928 SOC. The PXA1928 has 3 clock control blocks for different subsystems of the chip. Signed-off-by: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/marvell,pxa1928.txt | 21 ++++++++ include/dt-bindings/clock/marvell,pxa1928.h | 57 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1928.txt create mode 100644 include/dt-bindings/clock/marvell,pxa1928.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt b/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt new file mode 100644 index 000000000000..809c5a2d8d9d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1928.txt @@ -0,0 +1,21 @@ +* Marvell PXA1928 Clock Controllers + +The PXA1928 clock subsystem generates and supplies clock to various +controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller +blocks called APMU, MPMU, and APBC roughly corresponding to internal buses. + +Required Properties: + +- compatible: should be one of the following. + - "marvell,pxa1928-apmu" - APMU controller compatible + - "marvell,pxa1928-mpmu" - MPMU controller compatible + - "marvell,pxa1928-apbc" - APBC controller compatible +- reg: physical base address of the clock controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Each clock is assigned an identifier and client nodes use the clock controller +phandle and this identifier to specify the clock which they consume. + +All these identifiers can be found in . diff --git a/include/dt-bindings/clock/marvell,pxa1928.h b/include/dt-bindings/clock/marvell,pxa1928.h new file mode 100644 index 000000000000..d4f2e18919ff --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1928.h @@ -0,0 +1,57 @@ +#ifndef __DTS_MARVELL_PXA1928_CLOCK_H +#define __DTS_MARVELL_PXA1928_CLOCK_H + +/* + * Clock ID values here correspond to the control register offset/4. + */ + +/* apb peripherals */ +#define PXA1928_CLK_RTC 0x00 +#define PXA1928_CLK_TWSI0 0x01 +#define PXA1928_CLK_TWSI1 0x02 +#define PXA1928_CLK_TWSI2 0x03 +#define PXA1928_CLK_TWSI3 0x04 +#define PXA1928_CLK_OWIRE 0x05 +#define PXA1928_CLK_KPC 0x06 +#define PXA1928_CLK_TB_ROTARY 0x07 +#define PXA1928_CLK_SW_JTAG 0x08 +#define PXA1928_CLK_TIMER1 0x09 +#define PXA1928_CLK_UART0 0x0b +#define PXA1928_CLK_UART1 0x0c +#define PXA1928_CLK_UART2 0x0d +#define PXA1928_CLK_GPIO 0x0e +#define PXA1928_CLK_PWM0 0x0f +#define PXA1928_CLK_PWM1 0x10 +#define PXA1928_CLK_PWM2 0x11 +#define PXA1928_CLK_PWM3 0x12 +#define PXA1928_CLK_SSP0 0x13 +#define PXA1928_CLK_SSP1 0x14 +#define PXA1928_CLK_SSP2 0x15 + +#define PXA1928_CLK_TWSI4 0x1f +#define PXA1928_CLK_TWSI5 0x20 +#define PXA1928_CLK_UART3 0x22 +#define PXA1928_CLK_THSENS_GLOB 0x24 +#define PXA1928_CLK_THSENS_CPU 0x26 +#define PXA1928_CLK_THSENS_VPU 0x27 +#define PXA1928_CLK_THSENS_GC 0x28 +#define PXA1928_APBC_NR_CLKS 0x30 + + +/* axi peripherals */ +#define PXA1928_CLK_SDH0 0x15 +#define PXA1928_CLK_SDH1 0x16 +#define PXA1928_CLK_USB 0x17 +#define PXA1928_CLK_NAND 0x18 +#define PXA1928_CLK_DMA 0x19 + +#define PXA1928_CLK_SDH2 0x3a +#define PXA1928_CLK_SDH3 0x3b +#define PXA1928_CLK_HSIC 0x3e +#define PXA1928_CLK_SDH4 0x57 +#define PXA1928_CLK_GC3D 0x5d +#define PXA1928_CLK_GC2D 0x5f + +#define PXA1928_APMU_NR_CLKS 0x60 + +#endif -- cgit v1.2.3 From 9b799b78372c925d3204567741e3ff8fe0cc1c7d Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Sat, 9 May 2015 09:53:54 +0200 Subject: ARM: Add STM32 family machine STMicrolectronics's STM32 series is a family of Cortex-M microcontrollers. It is used in various applications, and proposes a wide range of peripherals. Tested-by: Chanwoo Choi Signed-off-by: Maxime Coquelin Signed-off-by: Arnd Bergmann --- Documentation/arm/stm32/overview.txt | 32 ++++++++++++++++++++++++++ Documentation/arm/stm32/stm32f429-overview.txt | 22 ++++++++++++++++++ arch/arm/Kconfig | 18 +++++++++++++++ arch/arm/Makefile | 1 + arch/arm/mach-stm32/Makefile | 1 + arch/arm/mach-stm32/Makefile.boot | 3 +++ arch/arm/mach-stm32/board-dt.c | 19 +++++++++++++++ 7 files changed, 96 insertions(+) create mode 100644 Documentation/arm/stm32/overview.txt create mode 100644 Documentation/arm/stm32/stm32f429-overview.txt create mode 100644 arch/arm/mach-stm32/Makefile create mode 100644 arch/arm/mach-stm32/Makefile.boot create mode 100644 arch/arm/mach-stm32/board-dt.c (limited to 'Documentation') diff --git a/Documentation/arm/stm32/overview.txt b/Documentation/arm/stm32/overview.txt new file mode 100644 index 000000000000..09aed5588d7c --- /dev/null +++ b/Documentation/arm/stm32/overview.txt @@ -0,0 +1,32 @@ + STM32 ARM Linux Overview + ======================== + +Introduction +------------ + + The STMicroelectronics family of Cortex-M based MCUs are supported by the + 'STM32' platform of ARM Linux. Currently only the STM32F429 is supported. + + +Configuration +------------- + + A generic configuration is provided for STM32 family, and can be used as the + default by + make stm32_defconfig + +Layout +------ + + All the files for multiple machine families are located in the platform code + contained in arch/arm/mach-stm32 + + There is a generic board board-dt.c in the mach folder which support + Flattened Device Tree, which means, it works with any compatible board with + Device Trees. + + +Document Author +--------------- + + Maxime Coquelin diff --git a/Documentation/arm/stm32/stm32f429-overview.txt b/Documentation/arm/stm32/stm32f429-overview.txt new file mode 100644 index 000000000000..5206822bd8ef --- /dev/null +++ b/Documentation/arm/stm32/stm32f429-overview.txt @@ -0,0 +1,22 @@ + STM32F429 Overview + ================== + + Introduction + ------------ + The STM32F429 is a Cortex-M4 MCU aimed at various applications. + It features: + - ARM Cortex-M4 up to 180MHz with FPU + - 2MB internal Flash Memory + - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND) + - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers + - LCD controller & Camera interface + - Cryptographic processor + + Resources + --------- + Datasheet and reference manual are publicly available on ST website: + - http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013 + + Document Author + --------------- + Maxime Coquelin diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7cd23bb03244..99544479ab01 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -758,6 +758,24 @@ config ARCH_OMAP1 help Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) +config ARCH_STM32 + bool "STMicrolectronics STM32" + depends on !MMU + select ARCH_HAS_RESET_CONTROLLER + select ARM_NVIC + select ARMV7M_SYSTICK + select AUTO_ZRELADDR + select CLKSRC_OF + select COMMON_CLK + select CPU_V7M + select GENERIC_CLOCKEVENTS + select NO_IOPORT_MAP + select RESET_CONTROLLER + select SPARSE_IRQ + select USE_OF + help + Support for STMicroelectronics STM32 processors. + endchoice menu "Multiple platform selection" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index fe8f9ef89395..d7af1922f56f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -196,6 +196,7 @@ machine-$(CONFIG_ARCH_SHMOBILE) += shmobile machine-$(CONFIG_ARCH_SIRF) += prima2 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STI) += sti +machine-$(CONFIG_ARCH_STM32) += stm32 machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U300) += u300 diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile new file mode 100644 index 000000000000..bd0b7b5d6e9d --- /dev/null +++ b/arch/arm/mach-stm32/Makefile @@ -0,0 +1 @@ +obj-y += board-dt.o diff --git a/arch/arm/mach-stm32/Makefile.boot b/arch/arm/mach-stm32/Makefile.boot new file mode 100644 index 000000000000..eacfc3f5c33e --- /dev/null +++ b/arch/arm/mach-stm32/Makefile.boot @@ -0,0 +1,3 @@ +# Empty file waiting for deletion once Makefile.boot isn't needed any more. +# Patch waits for application at +# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c new file mode 100644 index 000000000000..f2ad7723d034 --- /dev/null +++ b/arch/arm/mach-stm32/board-dt.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin + * License terms: GNU General Public License (GPL), version 2 + */ + +#include +#include +#include + +static const char *const stm32_compat[] __initconst = { + "st,stm32f429", + NULL +}; + +DT_MACHINE_START(STM32DT, "STM32 (Device Tree Support)") + .dt_compat = stm32_compat, + .restart = armv7m_restart, +MACHINE_END -- cgit v1.2.3 From 3a52be8a79a6777c0595e8655b22077a1bebec81 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 5 May 2015 15:51:12 -0700 Subject: Documentation: devicetree: brcmstb_nand: add BCM63138 and Cygnus/iProc Add notes to describe how some SoCs integrate this NAND core a little differently, and so we define extra compatibility strings and register resources/names. Signed-off-by: Brian Norris Reviewed-by: Florian Fainelli --- .../devicetree/bindings/mtd/brcm,brcmnand.txt | 48 ++++++++++++++++++++-- 1 file changed, 44 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt index 662c857e74fe..4ff7128ee3b2 100644 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt @@ -12,9 +12,14 @@ iProc/Cygnus. Its history includes several similar (but not fully register compatible) versions. Required properties: -- compatible : should contain "brcm,brcmnand" and an appropriate version - compatibility string, like "brcm,brcmnand-v7.0" - Possible values: +- compatible : May contain an SoC-specific compatibility string (see below) + to account for any SoC-specific hardware bits that may be + added on top of the base core controller. + In addition, must contain compatibility information about + the core NAND controller, of the following form: + "brcm,brcmnand" and an appropriate version compatibility + string, like "brcm,brcmnand-v7.0" + Possible values: brcm,brcmnand-v4.0 brcm,brcmnand-v5.0 brcm,brcmnand-v6.0 @@ -30,7 +35,11 @@ Required properties: "flash-dma" and/or "nand-cache". - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) FLASH_DMA_DONE -- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" +- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as + individual interrupts. + May be "nand", if the SoC has the individual NAND + interrupts multiplexed behind another custom piece of + hardware - interrupt-parent : See standard interrupt bindings - #address-cells : <1> - subnodes give the chip-select number - #size-cells : <0> @@ -41,6 +50,36 @@ Optional properties: v7.0. Use this property to describe the rare earlier versions of this core that include WP + -- Additonal SoC-specific NAND controller properties -- + +The NAND controller is integrated differently on the variety of SoCs on which it +is found. Part of this integration involves providing status and enable bits +with which to control the 8 exposed NAND interrupts, as well as hardware for +configuring the endianness of the data bus. On some SoCs, these features are +handled via standard, modular components (e.g., their interrupts look like a +normal IRQ chip), but on others, they are controlled in unique and interesting +ways, sometimes with registers that lump multiple NAND-related functions +together. The former case can be described simply by the standard interrupts +properties in the main controller node. But for the latter exceptional cases, +we define additional 'compatible' properties and associated register resources within the NAND controller node above. + + - compatible: Can be one of several SoC-specific strings. Each SoC may have + different requirements for its additional properties, as described below each + bullet point below. + + * "brcm,nand-bcm63138" + - reg: (required) the 'NAND_INT_BASE' register range, with separate status + and enable registers + - reg-names: (required) "nand-int-base" + + * "brcm,nand-iproc" + - reg: (required) the "IDM" register range, for interrupt enable and APB + bus access endianness configuration, and the "EXT" register range, + for interrupt status/ack. + - reg-names: (required) a list of the names corresponding to the previous + register ranges. Should contain "iproc-idm" and "iproc-ext". + + * NAND chip-select Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes @@ -74,6 +113,7 @@ Optional properties: Each nandcs device node may optionally contain sub-nodes describing the flash partition mapping. See partition.txt for more detail. + Example: nand@f0442800 { -- cgit v1.2.3 From 56bd3771e61bd5059c151ad0138c40e56688eba1 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Tue, 12 May 2015 00:00:51 +0200 Subject: ARM: dts: Add DT for Embedded Artists LPC4357 Developers Kit Adds basic support for Embedded Artists' LPC4357 Developer's Kit. Board features a LPC4357 Soc, 32 MB SDRAM, 128 MB NAND Flash, 16 MB SPI Flash, USB and Ethernet. More information can be found on: http://www.embeddedartists.com/products/kits/lpc4357_kit.php Signed-off-by: Joachim Eastwood Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 41 ++++++++++++++++++++++ arch/arm/boot/dts/lpc4357.dtsi | 39 ++++++++++++++++++++ 4 files changed, 83 insertions(+) create mode 100644 arch/arm/boot/dts/lpc4357-ea4357-devkit.dts create mode 100644 arch/arm/boot/dts/lpc4357.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b6682aba2f41..7822acc76c5d 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -61,6 +61,7 @@ digilent Diglent, Inc. dlg Dialog Semiconductor dlink D-Link Corporation dmo Data Modul AG +ea Embedded Artists AB ebv EBV Elektronik edt Emerging Display Technologies elan Elan Microelectronic Corp. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 69bf811960cb..9feb07a58867 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -207,6 +207,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ts219-6282.dtb \ kirkwood-ts419-6281.dtb \ kirkwood-ts419-6282.dtb +dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ ea3250.dtb phy3250.dtb dtb-$(CONFIG_MACH_MESON6) += \ diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts new file mode 100644 index 000000000000..08a6f757f924 --- /dev/null +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -0,0 +1,41 @@ +/* + * Embedded Artist LPC4357 Developer's Kit + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +/ { + model = "Embedded Artists' LPC4357 Developer's Kit"; + compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x28000000 0x2000000>; /* 32 MB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lpc4357.dtsi b/arch/arm/boot/dts/lpc4357.dtsi new file mode 100644 index 000000000000..fb9ecc754e8d --- /dev/null +++ b/arch/arm/boot/dts/lpc4357.dtsi @@ -0,0 +1,39 @@ +/* + * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4357"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +}; -- cgit v1.2.3 From 7dfc635894d1de84145fb02b210e6dfa5f50b6cc Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Tue, 12 May 2015 00:00:52 +0200 Subject: ARM: dts: Add DT for Hitex LPC4350 Evaluation Board Add basic support for Hitex LPC4350 Evaluation Board. Board features a LPC4350 Soc, 8 MB SDRAM, 8 MB SPI Flash, USB and Ethernet. More information can be found on: http://www.hitex.com/index.php?id=3212 Signed-off-by: Ariel D'Alessandro Signed-off-by: Joachim Eastwood Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/lpc4350-hitex-eval.dts | 45 ++++++++++++++++++++++ arch/arm/boot/dts/lpc4350.dtsi | 39 +++++++++++++++++++ 4 files changed, 86 insertions(+) create mode 100644 arch/arm/boot/dts/lpc4350-hitex-eval.dts create mode 100644 arch/arm/boot/dts/lpc4350.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 7822acc76c5d..826f573a4009 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -95,6 +95,7 @@ haoyu Haoyu Microelectronic Co. Ltd. himax Himax Technologies, Inc. hisilicon Hisilicon Limited. hit Hitachi Ltd. +hitex Hitex Development Tools honeywell Honeywell hp Hewlett Packard i2se I2SE GmbH diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9feb07a58867..07476a0256bb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -208,6 +208,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ts419-6281.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4350-hitex-eval.dtb \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ ea3250.dtb phy3250.dtb diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts new file mode 100644 index 000000000000..d04072f40817 --- /dev/null +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -0,0 +1,45 @@ +/* + * Hitex LPC4350 Evaluation Board + * + * Copyright 2015 Ariel D'Alessandro + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4350.dtsi" + +/ { + model = "Hitex LPC4350 Evaluation Board"; + compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x28000000 0x800000>; /* 8 MB */ + }; +}; + +&pll1 { + clock-mult = <15>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lpc4350.dtsi b/arch/arm/boot/dts/lpc4350.dtsi new file mode 100644 index 000000000000..c4422f587055 --- /dev/null +++ b/arch/arm/boot/dts/lpc4350.dtsi @@ -0,0 +1,39 @@ +/* + * NXP LPC4350 and LPC4330 SoC + * + * Copyright 2015 Ariel D'Alessandro + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4350", "nxp,lpc4330"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +}; -- cgit v1.2.3 From f07b4e49d27e8c085f0021093a612034bc0c75c6 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 27 Apr 2015 21:39:47 +0200 Subject: Documentation: bindings: berlin: consider our dt bindings as unstable Because the support of Marvell Berlin SoCs is still a work in progress, add a statement to explicitly consider our device tree files and bindings as unstable. Signed-off-by: Antoine Tenart Signed-off-by: Sebastian Hesselbarth --- Documentation/devicetree/bindings/arm/marvell,berlin.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index a99eb9eb14c0..060daafc14ff 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -1,6 +1,18 @@ Marvell Berlin SoC Family Device Tree Bindings --------------------------------------------------------------- +Work in progress statement: + +Device tree files and bindings applying to Marvell Berlin SoCs and boards are +considered "unstable". Any Marvell Berlin device tree binding may change at any +time. Be sure to use a device tree binary and a kernel image generated from the +same source tree. + +Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a +stable binding/ABI. + +--------------------------------------------------------------- + Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: -- cgit v1.2.3 From 7c90a5a9af6f02e04980958ef3f8d5f254364cca Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 27 Apr 2015 21:39:48 +0200 Subject: Documentation: bindings: update the Berlin controllers documentation We're moving from a single node for multiple devices to a node with one sub-node per sub-device, registered by simple-mfd. Update the documentation to reflect the changes. Signed-off-by: Antoine Tenart Signed-off-by: Sebastian Hesselbarth --- .../devicetree/bindings/arm/marvell,berlin.txt | 26 +++++++++++++--------- 1 file changed, 16 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 060daafc14ff..1f05794ecf74 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -61,10 +61,13 @@ chip control registers, so there should be a single DT node only providing the different functions which are described below. Required properties: -- compatible: shall be one of - "marvell,berlin2-chip-ctrl" for BG2 - "marvell,berlin2cd-chip-ctrl" for BG2CD - "marvell,berlin2q-chip-ctrl" for BG2Q +- compatible: + * the first value should be one of: + "marvell,berlin2-chip-ctrl" for BG2 + "marvell,berlin2cd-chip-ctrl" for BG2CD + "marvell,berlin2q-chip-ctrl" for BG2Q + * the second and third values must be: + "simple-mfd", "syscon" - reg: address and length of following register sets for BG2/BG2CD: chip control register set BG2Q: chip control register set and cpu pll registers @@ -75,10 +78,13 @@ Marvell Berlin SoCs have a system control register set providing several individual registers dealing with pinmux, padmux, and reset. Required properties: -- compatible: should be one of - "marvell,berlin2-system-ctrl" for BG2 - "marvell,berlin2cd-system-ctrl" for BG2CD - "marvell,berlin2q-system-ctrl" for BG2Q +- compatible: + * the first value should be one of: + "marvell,berlin2-system-ctrl" for BG2 + "marvell,berlin2cd-system-ctrl" for BG2CD + "marvell,berlin2q-system-ctrl" for BG2Q + * the second and third values must be: + "simple-mfd", "syscon" - reg: address and length of the system control register set * Clock provider binding @@ -130,7 +136,7 @@ Required property: Example: chip: chip-control@ea0000 { - compatible = "marvell,berlin2-chip-ctrl"; + compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon"; #clock-cells = <1>; #reset-cells = <2>; reg = <0xea0000 0x400>; @@ -144,7 +150,7 @@ chip: chip-control@ea0000 { }; sysctrl: system-controller@d000 { - compatible = "marvell,berlin2-system-ctrl"; + compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon"; reg = <0xd000 0x100>; uart0_pmux: uart0-pmux { -- cgit v1.2.3 From 185cff3d661ab7ad56a09005c2874a9a0b25c109 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 27 Apr 2015 21:39:48 +0200 Subject: Documentation: bindings: move the Berlin reset documentation The Berlin reset documentation was part of the Marvell Berlin SoC documentation because the Berlin reset configuration was inside the chip controller. With the recent rework of the chip and system controller handling (now an MFD driver registers all sub-devices of the two soc and system controller nodes and each device has its own sub-node), the documentation of the Berlin reset driver can be moved to the generic reset documentation directory. Signed-off-by: Antoine Tenart Acked-by: Philipp Zabel Signed-off-by: Sebastian Hesselbarth --- .../devicetree/bindings/arm/marvell,berlin.txt | 10 ---------- .../devicetree/bindings/reset/berlin,reset.txt | 23 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/berlin,reset.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 1f05794ecf74..6b7c21079bea 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -124,21 +124,11 @@ Required subnode-properties: - groups: a list of strings describing the group names. - function: a string describing the function used to mux the groups. -* Reset controller binding - -A reset controller is part of the chip control registers set. The chip control -node also provides the reset. The register set is not at the same offset between -Berlin SoCs. - -Required property: -- #reset-cells: must be set to 2 - Example: chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon"; #clock-cells = <1>; - #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>, <&externaldev 0>; clock-names = "refclk", "video_ext0"; diff --git a/Documentation/devicetree/bindings/reset/berlin,reset.txt b/Documentation/devicetree/bindings/reset/berlin,reset.txt new file mode 100644 index 000000000000..514fee098b4b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/berlin,reset.txt @@ -0,0 +1,23 @@ +Marvell Berlin reset controller +=============================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller node must be a sub-node of the chip controller +node on Berlin SoCs. + +Required properties: +- compatible: should be "marvell,berlin2-reset" +- #reset-cells: must be set to 2 + +Example: + +chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; +}; + +&usb_phy0 { + resets = <&chip_rst 0x104 12>; +}; -- cgit v1.2.3 From 66fa300e60728ddbf7f9e8291c94c6c6691b00de Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 27 Apr 2015 21:39:48 +0200 Subject: Documentation: bindings: move the Berlin pinctrl documentation The Berlin pinctrl documentation was part of the Marvell Berlin SoC documentation because the Berlin pinctrl configuration was inside the chip and the system controllers. With the recent rework of the chip and system controller handling (now an MFD driver registers all sub-devices of the two soc and system controller nodes and each device has its own sub-node), the documentation of the Berlin pinctrl driver can be moved to the generic pinctrl documentation directory. Signed-off-by: Antoine Tenart Signed-off-by: Sebastian Hesselbarth --- .../devicetree/bindings/arm/marvell,berlin.txt | 37 ------------------- .../devicetree/bindings/pinctrl/berlin,pinctrl.txt | 43 ++++++++++++++++++++++ 2 files changed, 43 insertions(+), 37 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 6b7c21079bea..e8d9111a9852 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -107,23 +107,6 @@ Clocks provided by core clocks shall be referenced by a clock specifier indexing one of the provided clocks. Refer to dt-bindings/clock/berlin.h for the corresponding index mapping. -* Pin controller binding - -Pin control registers are part of both register sets, chip control and system -control. The pins controlled are organized in groups, so no actual pin -information is needed. - -A pin-controller node should contain subnodes representing the pin group -configurations, one per function. Each subnode has the group name and the muxing -function used. - -Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called -a 'function' in the pin-controller subsystem. - -Required subnode-properties: -- groups: a list of strings describing the group names. -- function: a string describing the function used to mux the groups. - Example: chip: chip-control@ea0000 { @@ -132,29 +115,9 @@ chip: chip-control@ea0000 { reg = <0xea0000 0x400>; clocks = <&refclk>, <&externaldev 0>; clock-names = "refclk", "video_ext0"; - - spi1_pmux: spi1-pmux { - groups = "G0"; - function = "spi1"; - }; }; sysctrl: system-controller@d000 { compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon"; reg = <0xd000 0x100>; - - uart0_pmux: uart0-pmux { - groups = "GSM4"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM5"; - function = "uart1"; - }; - - uart2_pmux: uart2-pmux { - groups = "GSM3"; - function = "uart2"; - }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt new file mode 100644 index 000000000000..a8bb5e26019c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt @@ -0,0 +1,43 @@ +* Pin-controller driver for the Marvell Berlin SoCs + +Pin control registers are part of both chip controller and system +controller register sets. Pin controller nodes should be a sub-node of +either the chip controller or system controller node. The pins +controlled are organized in groups, so no actual pin information is +needed. + +A pin-controller node should contain subnodes representing the pin group +configurations, one per function. Each subnode has the group name and +the muxing function used. + +Be aware the Marvell Berlin datasheets use the keyword 'mode' for what +is called a 'function' in the pin-controller subsystem. + +Required properties: +- compatible: should be one of: + "marvell,berlin2-soc-pinctrl", + "marvell,berlin2-system-pinctrl", + "marvell,berlin2cd-soc-pinctrl", + "marvell,berlin2cd-system-pinctrl", + "marvell,berlin2q-soc-pinctrl", + "marvell,berlin2q-system-pinctrl" + +Required subnode-properties: +- groups: a list of strings describing the group names. +- function: a string describing the function used to mux the groups. + +Example: + +sys_pinctrl: pin-controller { + compatible = "marvell,berlin2q-system-pinctrl"; + + uart0_pmux: uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From c1f86f2fded23f337bb9e5dab1b42634784bf883 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 7 Apr 2015 16:45:02 +0200 Subject: Documentation: bindings: move the Berlin clock documentation The Berlin clock documentation was part of the Marvell Berlin SoC documentation because the Berlin clock configuration was inside the chip controller. With the recent rework of the chip and system controller handling (now all sub-devices of the soc and system controller nodes are registred with simple-mfd, and each device has its own sub-node), the documentation of the Berlin clock driver can be moved to the generic clock documentation directory. Signed-off-by: Antoine Tenart Acked-by: Stephen Boyd Signed-off-by: Sebastian Hesselbarth --- .../devicetree/bindings/arm/marvell,berlin.txt | 27 +++---------------- .../devicetree/bindings/clock/marvell,berlin.txt | 31 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index e8d9111a9852..4a61bd802491 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -87,37 +87,18 @@ Required properties: "simple-mfd", "syscon" - reg: address and length of the system control register set -* Clock provider binding - -As clock related registers are spread among the chip control registers, the -chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q) -SoCs share the same IP for PLLs and clocks, with some minor differences in -features and register layout. - -Required properties: -- #clock-cells: shall be set to 1 -- clocks: clock specifiers referencing the core clock input clocks -- clock-names: array of strings describing the input clock specifiers above. - Allowed clock-names for the reference clocks are - "refclk" for the SoCs osciallator input on all SoCs, - and SoC-specific input clocks for - BG2/BG2CD: "video_ext0" for the external video clock input - -Clocks provided by core clocks shall be referenced by a clock specifier -indexing one of the provided clocks. Refer to dt-bindings/clock/berlin.h -for the corresponding index mapping. - Example: chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon"; - #clock-cells = <1>; reg = <0xea0000 0x400>; - clocks = <&refclk>, <&externaldev 0>; - clock-names = "refclk", "video_ext0"; + + /* sub-device nodes */ }; sysctrl: system-controller@d000 { compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon"; reg = <0xd000 0x100>; + + /* sub-device nodes */ }; diff --git a/Documentation/devicetree/bindings/clock/marvell,berlin.txt b/Documentation/devicetree/bindings/clock/marvell,berlin.txt new file mode 100644 index 000000000000..c611c495f3ff --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,berlin.txt @@ -0,0 +1,31 @@ +Device Tree Clock bindings for Marvell Berlin + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Clock related registers are spread among the chip control registers. Berlin +clock node should be a sub-node of the chip controller node. Marvell Berlin2 +(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some +minor differences in features and register layout. + +Required properties: +- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" +- #clock-cells: must be 1 +- clocks: must be the input parent clock phandle +- clock-names: name of the input parent clock + Allowed clock-names for the reference clocks are + "refclk" for the SoCs oscillator input on all SoCs, + and SoC-specific input clocks for + BG2/BG2CD: "video_ext0" for the external video clock input + + +Example: + +chip_clk: clock { + compatible = "marvell,berlin2q-clk"; + + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; +}; -- cgit v1.2.3 From 576efe38000dc81d8140925d9725a4f4e789514a Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 7 Apr 2015 16:45:06 +0200 Subject: Documentation: bindings: update the berlin chip and system ctrl doc Now that the rework to have one sub-node per device in the chip and system controllers is done, their dedicated compatible can be removed. Signed-off-by: Antoine Tenart Signed-off-by: Sebastian Hesselbarth --- Documentation/devicetree/bindings/arm/marvell,berlin.txt | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 4a61bd802491..3bab18409b7a 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -62,11 +62,7 @@ different functions which are described below. Required properties: - compatible: - * the first value should be one of: - "marvell,berlin2-chip-ctrl" for BG2 - "marvell,berlin2cd-chip-ctrl" for BG2CD - "marvell,berlin2q-chip-ctrl" for BG2Q - * the second and third values must be: + * the first and second values must be: "simple-mfd", "syscon" - reg: address and length of following register sets for BG2/BG2CD: chip control register set @@ -79,25 +75,21 @@ individual registers dealing with pinmux, padmux, and reset. Required properties: - compatible: - * the first value should be one of: - "marvell,berlin2-system-ctrl" for BG2 - "marvell,berlin2cd-system-ctrl" for BG2CD - "marvell,berlin2q-system-ctrl" for BG2Q - * the second and third values must be: + * the first and second values must be: "simple-mfd", "syscon" - reg: address and length of the system control register set Example: chip: chip-control@ea0000 { - compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon"; + compatible = "simple-mfd", "syscon"; reg = <0xea0000 0x400>; /* sub-device nodes */ }; sysctrl: system-controller@d000 { - compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon"; + compatible = "simple-mfd", "syscon"; reg = <0xd000 0x100>; /* sub-device nodes */ -- cgit v1.2.3 From b3b10e99b73b5e079fdb9bdaa1dad43b53e330cd Mon Sep 17 00:00:00 2001 From: Anatol Pomozov Date: Wed, 13 May 2015 08:25:15 -0700 Subject: ASoC: rt5677: Add reset-gpio dts option It allows to configure codec's RESET pin gpio Signed-off-by: Anatol Pomozov Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5677.txt | 2 ++ sound/soc/codecs/rt5677.c | 32 ++++++++++++++++++++-- sound/soc/codecs/rt5677.h | 1 + 3 files changed, 33 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/rt5677.txt b/Documentation/devicetree/bindings/sound/rt5677.txt index 740ff771aa8b..f07078997f87 100644 --- a/Documentation/devicetree/bindings/sound/rt5677.txt +++ b/Documentation/devicetree/bindings/sound/rt5677.txt @@ -18,6 +18,7 @@ Required properties: Optional properties: - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin. +- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. - realtek,in1-differential - realtek,in2-differential @@ -70,6 +71,7 @@ rt5677 { realtek,pow-ldo2-gpio = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; realtek,in1-differential = "true"; realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; /* pull up GPIO6 */ realtek,jd2-gpio = <3>; /* Enables Jack detection for GPIO6 */ diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index c73105e75c1a..aba00fd8dfc4 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -4763,6 +4763,8 @@ static int rt5677_remove(struct snd_soc_codec *codec) regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); if (gpio_is_valid(rt5677->pow_ldo2)) gpio_set_value_cansleep(rt5677->pow_ldo2, 0); + if (gpio_is_valid(rt5677->reset_pin)) + gpio_set_value_cansleep(rt5677->reset_pin, 0); return 0; } @@ -4778,6 +4780,8 @@ static int rt5677_suspend(struct snd_soc_codec *codec) if (gpio_is_valid(rt5677->pow_ldo2)) gpio_set_value_cansleep(rt5677->pow_ldo2, 0); + if (gpio_is_valid(rt5677->reset_pin)) + gpio_set_value_cansleep(rt5677->reset_pin, 0); } return 0; @@ -4788,10 +4792,13 @@ static int rt5677_resume(struct snd_soc_codec *codec) struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); if (!rt5677->dsp_vad_en) { - if (gpio_is_valid(rt5677->pow_ldo2)) { + if (gpio_is_valid(rt5677->pow_ldo2)) gpio_set_value_cansleep(rt5677->pow_ldo2, 1); + if (gpio_is_valid(rt5677->reset_pin)) + gpio_set_value_cansleep(rt5677->reset_pin, 1); + if (gpio_is_valid(rt5677->pow_ldo2) || + gpio_is_valid(rt5677->reset_pin)) msleep(10); - } regcache_cache_only(rt5677->regmap, false); regcache_sync(rt5677->regmap); @@ -5029,6 +5036,8 @@ static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np) rt5677->pow_ldo2 = of_get_named_gpio(np, "realtek,pow-ldo2-gpio", 0); + rt5677->reset_pin = of_get_named_gpio(np, + "realtek,reset-gpio", 0); /* * POW_LDO2 is optional (it may be statically tied on the board). @@ -5039,6 +5048,9 @@ static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np) if (!gpio_is_valid(rt5677->pow_ldo2) && (rt5677->pow_ldo2 != -ENOENT)) return rt5677->pow_ldo2; + if (!gpio_is_valid(rt5677->reset_pin) && + (rt5677->reset_pin != -ENOENT)) + return rt5677->reset_pin; of_property_read_u8_array(np, "realtek,gpio-config", rt5677->pdata.gpio_config, RT5677_GPIO_NUM); @@ -5140,6 +5152,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c, } } else { rt5677->pow_ldo2 = -EINVAL; + rt5677->reset_pin = -EINVAL; } if (gpio_is_valid(rt5677->pow_ldo2)) { @@ -5151,6 +5164,21 @@ static int rt5677_i2c_probe(struct i2c_client *i2c, rt5677->pow_ldo2, ret); return ret; } + } + + if (gpio_is_valid(rt5677->reset_pin)) { + ret = devm_gpio_request_one(&i2c->dev, rt5677->reset_pin, + GPIOF_OUT_INIT_HIGH, + "RT5677 RESET"); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to request RESET %d: %d\n", + rt5677->reset_pin, ret); + return ret; + } + } + + if (gpio_is_valid(rt5677->pow_ldo2) || + gpio_is_valid(rt5677->reset_pin)) { /* Wait a while until I2C bus becomes available. The datasheet * does not specify the exact we should wait but startup * sequence mentiones at least a few milliseconds. diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index 62571d071a8d..7eca38a23255 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1776,6 +1776,7 @@ struct rt5677_priv { int pll_in; int pll_out; int pow_ldo2; /* POW_LDO2 pin */ + int reset_pin; /* RESET pin */ enum rt5677_type type; #ifdef CONFIG_GPIOLIB struct gpio_chip gpio_chip; -- cgit v1.2.3 From 062f49c460d7ea585e0279be55daa66d1b375e8c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 2 May 2015 14:33:55 +0900 Subject: ARM: dts: Use s3c6410-rtc instead of exynos3250-rtc for exynos3250/4415 Mark "samsung,exynos3250-rtc" compatible as deprecated because it duplicates the "samsung,s3c6410-rtc". Use "samsung,s3c6410-rtc" on Exynos3250 and Exynos4415 boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Reviewed-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- Documentation/devicetree/bindings/rtc/s3c-rtc.txt | 3 ++- arch/arm/boot/dts/exynos3250.dtsi | 2 +- arch/arm/boot/dts/exynos4415.dtsi | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt index ab757b84daa7..ac2fcd6ff4b8 100644 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt @@ -6,7 +6,8 @@ Required properties: * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc. * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc. * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. - * "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc. + * "samsung,exynos3250-rtc" - (deprecated) for controllers compatible with + exynos3250 rtc (use "samsung,s3c6410-rtc"). - reg: physical base address of the controller and length of memory mapped region. - interrupts: Two interrupt numbers to the cpu should be specified. First diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index e25088cbae9a..4728c77ed6e4 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -189,7 +189,7 @@ }; rtc: rtc@10070000 { - compatible = "samsung,exynos3250-rtc"; + compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 73 0>, <0 74 0>; interrupt-parent = <&pmu_system_controller>; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi index 5caea996e090..186cb8465683 100644 --- a/arch/arm/boot/dts/exynos4415.dtsi +++ b/arch/arm/boot/dts/exynos4415.dtsi @@ -177,7 +177,7 @@ }; rtc: rtc@10070000 { - compatible = "samsung,exynos3250-rtc"; + compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 73 0>, <0 74 0>; status = "disabled"; -- cgit v1.2.3 From 3f7f642b9bc46453e1435e8b67f1c4f7949be7ff Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Wed, 13 May 2015 12:26:42 +0200 Subject: iio: core: add high pass filter attributes Add a high pass filter attribute for measurements (like the existing low pass) Also add both high and low pass attributes for events. Signed-off-by: Martin Fuzzey Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 30 ++++++++++++++++++++++++++++++ drivers/iio/industrialio-core.c | 2 ++ drivers/iio/industrialio-event.c | 2 ++ include/linux/iio/iio.h | 1 + include/linux/iio/types.h | 2 ++ 5 files changed, 37 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index e46c71fbd047..f66262c64e2f 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -420,6 +420,16 @@ Description: to the underlying data channel, then this parameter gives the 3dB frequency of the filter in Hz. +What: /sys/.../in_accel_filter_high_pass_3db_frequency +What: /sys/.../in_anglvel_filter_high_pass_3db_frequency +What: /sys/.../in_magn_filter_high_pass_3db_frequency +KernelVersion: 4.2 +Contact: linux-iio@vger.kernel.org +Description: + If a known or controllable high pass filter is applied + to the underlying data channel, then this parameter + gives the 3dB frequency of the filter in Hz. + What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_raw What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_raw KernelVersion: 2.6.37 @@ -880,6 +890,26 @@ Description: met before an event is generated. If direction is not specified then this period applies to both directions. +What: /sys/.../events/in_accel_thresh_rising_low_pass_filter_3db +What: /sys/.../events/in_anglvel_thresh_rising_low_pass_filter_3db +What: /sys/.../events/in_magn_thresh_rising_low_pass_filter_3db +KernelVersion: 4.2 +Contact: linux-iio@vger.kernel.org +Description: + If a low pass filter can be applied to the event generation + this property gives its 3db frequency in Hz. + A value of zero disables the filter. + +What: /sys/.../events/in_accel_thresh_rising_high_pass_filter_3db +What: /sys/.../events/in_anglvel_thresh_rising_high_pass_filter_3db +What: /sys/.../events/in_magn_thresh_rising_high_pass_filter_3db +KernelVersion: 4.2 +Contact: linux-iio@vger.kernel.org +Description: + If a high pass filter can be applied to the event generation + this property gives its 3db frequency in Hz. + A value of zero disables the filter. + What: /sys/.../events/in_activity_still_thresh_rising_en What: /sys/.../events/in_activity_still_thresh_falling_en What: /sys/.../events/in_activity_walking_thresh_rising_en diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index dfa81db3b910..9688a88b6198 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -117,6 +117,8 @@ static const char * const iio_chan_info_postfix[] = { [IIO_CHAN_INFO_AVERAGE_RAW] = "mean_raw", [IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY] = "filter_low_pass_3db_frequency", + [IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY] + = "filter_high_pass_3db_frequency", [IIO_CHAN_INFO_SAMP_FREQ] = "sampling_frequency", [IIO_CHAN_INFO_FREQUENCY] = "frequency", [IIO_CHAN_INFO_PHASE] = "phase", diff --git a/drivers/iio/industrialio-event.c b/drivers/iio/industrialio-event.c index a99692ba91bc..894d8137c4cf 100644 --- a/drivers/iio/industrialio-event.c +++ b/drivers/iio/industrialio-event.c @@ -211,6 +211,8 @@ static const char * const iio_ev_info_text[] = { [IIO_EV_INFO_VALUE] = "value", [IIO_EV_INFO_HYSTERESIS] = "hysteresis", [IIO_EV_INFO_PERIOD] = "period", + [IIO_EV_INFO_HIGH_PASS_FILTER_3DB] = "high_pass_filter_3db", + [IIO_EV_INFO_LOW_PASS_FILTER_3DB] = "low_pass_filter_3db", }; static enum iio_event_direction iio_ev_attr_dir(struct iio_dev_attr *attr) diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 058441da4984..f79148261d16 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -32,6 +32,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW, IIO_CHAN_INFO_AVERAGE_RAW, IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY, + IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY, IIO_CHAN_INFO_SAMP_FREQ, IIO_CHAN_INFO_FREQUENCY, IIO_CHAN_INFO_PHASE, diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h index 942b6de68e2f..32b579525004 100644 --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h @@ -17,6 +17,8 @@ enum iio_event_info { IIO_EV_INFO_VALUE, IIO_EV_INFO_HYSTERESIS, IIO_EV_INFO_PERIOD, + IIO_EV_INFO_HIGH_PASS_FILTER_3DB, + IIO_EV_INFO_LOW_PASS_FILTER_3DB, }; #define IIO_VAL_INT 1 -- cgit v1.2.3 From 18e25fa40331364759bc2a48cffc5d7772b89c78 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Tue, 14 Apr 2015 10:08:15 +0200 Subject: quota: Update documentation Mention that quota netlink messages are sent only in initial network namespace. Signed-off-by: Jan Kara --- Documentation/filesystems/quota.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/quota.txt b/Documentation/filesystems/quota.txt index 5e8de25bf0f1..29fc01552646 100644 --- a/Documentation/filesystems/quota.txt +++ b/Documentation/filesystems/quota.txt @@ -32,7 +32,10 @@ The interface uses generic netlink framework (see http://lwn.net/Articles/208755/ and http://people.suug.ch/~tgr/libnl/ for more details about this layer). The name of the quota generic netlink interface is "VFS_DQUOT". Definitions of constants below are in . - Currently, the interface supports only one message type QUOTA_NL_C_WARNING. +Since the quota netlink protocol is not namespace aware, quota netlink messages +are sent only in initial network namespace. + +Currently, the interface supports only one message type QUOTA_NL_C_WARNING. This command is used to send a notification about any of the above mentioned events. Each message has six attributes. These are (type of the argument is in parentheses): -- cgit v1.2.3 From 07db781dcaa59e497eb5b8642fee86201d256ecc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 May 2015 17:57:39 +0200 Subject: ARM: scu: document Snoop Control Unit DT bindings This adds device tree bindings for the ARM Cortex-A5 and Cortex-A9 Snoop Control Units. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/scu.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/scu.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt new file mode 100644 index 000000000000..c447680519bb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/scu.txt @@ -0,0 +1,25 @@ +* ARM Snoop Control Unit (SCU) + +As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided +with a Snoop Control Unit. The register range is usually 256 (0x100) +bytes. + +References: + +- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual + Revision r2p0 +- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual + Revision r0p1 + +- compatible : Should be: + "arm,cortex-a9-scu" + "arm,cortex-a5-scu" + +- reg : Specify the base address and the size of the SCU register window. + +Example: + +scu@a04100000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; +}; -- cgit v1.2.3 From a3355a236d7d6363bb10813d5e84d23a3b409dad Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 May 2015 18:01:19 +0200 Subject: ARM: ux500: add board documentation This documents the device tree bindings on the top level of the Ux500 boards. Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- .../devicetree/bindings/arm/ux500/boards.txt | 83 ++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ux500/boards.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt new file mode 100644 index 000000000000..b8737a8de718 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ux500/boards.txt @@ -0,0 +1,83 @@ +ST-Ericsson Ux500 boards +------------------------ + +Required properties (in root node) one of these: + compatible = "st-ericsson,mop500" (legacy) + compatible = "st-ericsson,u8500" + +Required node (under root node): + +soc: represents the system-on-chip and contains the chip +peripherals + +Required property of soc node, one of these: + compatible = "stericsson,db8500" + +Required subnodes under soc node: + +backupram: (used for CPU spin tables and for storing data +during retention, system won't boot without this): + compatible = "ste,dbx500-backupram" + +scu: + see binding for arm/scu.txt + +interrupt-controller: + see binding for arm/gic.txt + +timer: + see binding for arm/twd.txt + +clocks: + see binding for clocks/ux500.txt + +Example: + +/dts-v1/; + +/ { + model = "ST-Ericsson HREF (pre-v60) and ST UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; + ranges; + + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + scu@a04100000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ + clocks = <&smp_twd_clk>; + }; + + clocks { + compatible = "stericsson,u8500-clks"; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + }; + }; +}; -- cgit v1.2.3 From 9c23f4dab1a467f41a27c7d7b87a987c5a3cfc2d Mon Sep 17 00:00:00 2001 From: Eugene Crosser Date: Mon, 18 May 2015 14:27:56 +0200 Subject: qeth: OSA version of SETBRIDGEPORT command OSA Ethernet hardware is introducing BRIDGEPORT functionality similar (but not identical) to HiperSockets BRIDGEPORT. This patch makes HiperSockets BRIDGEPORT related sysfs attributes and udev events work with OSA hardware too. Reviewed-by: Thomas Richter Signed-off-by: Eugene Crosser Signed-off-by: Ursula Braun Signed-off-by: David S. Miller --- Documentation/s390/qeth.txt | 4 +-- drivers/s390/net/qeth_core_main.c | 3 +- drivers/s390/net/qeth_core_mpc.c | 3 +- drivers/s390/net/qeth_core_mpc.h | 3 +- drivers/s390/net/qeth_l2_main.c | 68 +++++++++++++++++++++++++-------------- 5 files changed, 51 insertions(+), 30 deletions(-) (limited to 'Documentation') diff --git a/Documentation/s390/qeth.txt b/Documentation/s390/qeth.txt index 74122ada9949..aa06fcf5f8c2 100644 --- a/Documentation/s390/qeth.txt +++ b/Documentation/s390/qeth.txt @@ -1,6 +1,6 @@ IBM s390 QDIO Ethernet Driver -HiperSockets Bridge Port Support +OSA and HiperSockets Bridge Port Support Uevents @@ -8,7 +8,7 @@ To generate the events the device must be assigned a role of either a primary or a secondary Bridge Port. For more information, see "z/VM Connectivity, SC24-6174". -When run on HiperSockets Bridge Capable Port hardware, and the state +When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state of some configured Bridge Port device on the channel changes, a udev event with ACTION=CHANGE is emitted on behalf of the corresponding ccwgroup device. The event has the following attributes: diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 3466d3cb7647..5e20fba37bff 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -645,7 +645,8 @@ static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card, card->info.hwtrap = 2; qeth_schedule_recovery(card); return NULL; - case IPA_CMD_SETBRIDGEPORT: + case IPA_CMD_SETBRIDGEPORT_IQD: + case IPA_CMD_SETBRIDGEPORT_OSA: case IPA_CMD_ADDRESS_CHANGE_NOTIF: if (card->discipline->control_event_handler (card, cmd)) diff --git a/drivers/s390/net/qeth_core_mpc.c b/drivers/s390/net/qeth_core_mpc.c index 7b55768a9592..beb4bdc26de5 100644 --- a/drivers/s390/net/qeth_core_mpc.c +++ b/drivers/s390/net/qeth_core_mpc.c @@ -237,6 +237,7 @@ static struct ipa_cmd_names qeth_ipa_cmd_names[] = { {IPA_CMD_DELGMAC, "delgmac"}, {IPA_CMD_SETVLAN, "setvlan"}, {IPA_CMD_DELVLAN, "delvlan"}, + {IPA_CMD_SETBRIDGEPORT_OSA, "set_bridge_port(osa)"}, {IPA_CMD_SETCCID, "setccid"}, {IPA_CMD_DELCCID, "delccid"}, {IPA_CMD_MODCCID, "modccid"}, @@ -249,7 +250,7 @@ static struct ipa_cmd_names qeth_ipa_cmd_names[] = { {IPA_CMD_DELIP, "delip"}, {IPA_CMD_SETADAPTERPARMS, "setadapterparms"}, {IPA_CMD_SET_DIAG_ASS, "set_diag_ass"}, - {IPA_CMD_SETBRIDGEPORT, "set_bridge_port"}, + {IPA_CMD_SETBRIDGEPORT_IQD, "set_bridge_port(hs)"}, {IPA_CMD_CREATE_ADDR, "create_addr"}, {IPA_CMD_DESTROY_ADDR, "destroy_addr"}, {IPA_CMD_REGISTER_LOCAL_ADDR, "register_local_addr"}, diff --git a/drivers/s390/net/qeth_core_mpc.h b/drivers/s390/net/qeth_core_mpc.h index 1558be1af72d..6cccc9a49ede 100644 --- a/drivers/s390/net/qeth_core_mpc.h +++ b/drivers/s390/net/qeth_core_mpc.h @@ -92,6 +92,7 @@ enum qeth_ipa_cmds { IPA_CMD_DELGMAC = 0x24, IPA_CMD_SETVLAN = 0x25, IPA_CMD_DELVLAN = 0x26, + IPA_CMD_SETBRIDGEPORT_OSA = 0x2b, IPA_CMD_SETCCID = 0x41, IPA_CMD_DELCCID = 0x42, IPA_CMD_MODCCID = 0x43, @@ -104,7 +105,7 @@ enum qeth_ipa_cmds { IPA_CMD_DELIP = 0xb7, IPA_CMD_SETADAPTERPARMS = 0xb8, IPA_CMD_SET_DIAG_ASS = 0xb9, - IPA_CMD_SETBRIDGEPORT = 0xbe, + IPA_CMD_SETBRIDGEPORT_IQD = 0xbe, IPA_CMD_CREATE_ADDR = 0xc3, IPA_CMD_DESTROY_ADDR = 0xc4, IPA_CMD_REGISTER_LOCAL_ADDR = 0xd1, diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index 0ff926d4d63d..789377c7d5ef 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c @@ -1028,7 +1028,7 @@ static int __qeth_l2_set_online(struct ccwgroup_device *gdev, int recovery_mode) qeth_bridgeport_query_support(card); if (card->options.sbp.supported_funcs) dev_info(&card->gdev->dev, - "The device represents a HiperSockets Bridge Capable Port\n"); + "The device represents a Bridge Capable Port\n"); qeth_trace_features(card); if (!card->dev && qeth_l2_setup_netdev(card)) { @@ -1281,7 +1281,8 @@ static int qeth_l2_control_event(struct qeth_card *card, struct qeth_ipa_cmd *cmd) { switch (cmd->hdr.command) { - case IPA_CMD_SETBRIDGEPORT: + case IPA_CMD_SETBRIDGEPORT_OSA: + case IPA_CMD_SETBRIDGEPORT_IQD: if (cmd->data.sbp.hdr.command_code == IPA_SBP_BRIDGE_PORT_STATE_CHANGE) { qeth_bridge_state_change(card, cmd); @@ -1567,7 +1568,7 @@ static void qeth_bridge_host_event_worker(struct work_struct *work) if (data->hostevs.lost_event_mask) { dev_info(&data->card->gdev->dev, -"Address notification from the HiperSockets Bridge Port stopped %s (%s)\n", +"Address notification from the Bridge Port stopped %s (%s)\n", data->card->dev->name, (data->hostevs.lost_event_mask == 0x01) ? "Overflow" @@ -1651,70 +1652,80 @@ static int qeth_bridgeport_makerc(struct qeth_card *card, struct _qeth_sbp_cbctl *cbctl, enum qeth_ipa_sbp_cmd setcmd) { int rc; + int is_iqd = (card->info.type == QETH_CARD_TYPE_IQD); - switch (cbctl->ipa_rc) { - case IPA_RC_SUCCESS: + if ((is_iqd && (cbctl->ipa_rc == IPA_RC_SUCCESS)) || + (!is_iqd && (cbctl->ipa_rc == cbctl->cmd_rc))) switch (cbctl->cmd_rc) { case 0x0000: rc = 0; break; + case 0x2B04: case 0x0004: rc = -ENOSYS; break; + case 0x2B0C: case 0x000C: /* Not configured as bridge Port */ rc = -ENODEV; /* maybe not the best code here? */ dev_err(&card->gdev->dev, - "The HiperSockets device is not configured as a Bridge Port\n"); + "The device is not configured as a Bridge Port\n"); break; + case 0x2B14: case 0x0014: /* Another device is Primary */ switch (setcmd) { case IPA_SBP_SET_PRIMARY_BRIDGE_PORT: rc = -EEXIST; dev_err(&card->gdev->dev, - "The HiperSockets LAN already has a primary Bridge Port\n"); + "The LAN already has a primary Bridge Port\n"); break; case IPA_SBP_SET_SECONDARY_BRIDGE_PORT: rc = -EBUSY; dev_err(&card->gdev->dev, - "The HiperSockets device is already a primary Bridge Port\n"); + "The device is already a primary Bridge Port\n"); break; default: rc = -EIO; } break; + case 0x2B18: case 0x0018: /* This device is currently Secondary */ rc = -EBUSY; dev_err(&card->gdev->dev, - "The HiperSockets device is already a secondary Bridge Port\n"); + "The device is already a secondary Bridge Port\n"); break; + case 0x2B1C: case 0x001C: /* Limit for Secondary devices reached */ rc = -EEXIST; dev_err(&card->gdev->dev, - "The HiperSockets LAN cannot have more secondary Bridge Ports\n"); + "The LAN cannot have more secondary Bridge Ports\n"); break; + case 0x2B24: case 0x0024: /* This device is currently Primary */ rc = -EBUSY; dev_err(&card->gdev->dev, - "The HiperSockets device is already a primary Bridge Port\n"); + "The device is already a primary Bridge Port\n"); break; + case 0x2B20: case 0x0020: /* Not authorized by zManager */ rc = -EACCES; dev_err(&card->gdev->dev, - "The HiperSockets device is not authorized to be a Bridge Port\n"); + "The device is not authorized to be a Bridge Port\n"); break; default: rc = -EIO; } - break; - case IPA_RC_NOTSUPP: - rc = -ENOSYS; - break; - case IPA_RC_UNSUPPORTED_COMMAND: - rc = -ENOSYS; - break; - default: - rc = -EIO; - } + else + switch (cbctl->ipa_rc) { + case IPA_RC_NOTSUPP: + rc = -ENOSYS; + break; + case IPA_RC_UNSUPPORTED_COMMAND: + rc = -ENOSYS; + break; + default: + rc = -EIO; + } + if (rc) { QETH_CARD_TEXT_(card, 2, "SBPi%04x", cbctl->ipa_rc); QETH_CARD_TEXT_(card, 2, "SBPc%04x", cbctl->cmd_rc); @@ -1722,6 +1733,13 @@ static int qeth_bridgeport_makerc(struct qeth_card *card, return rc; } +static inline int ipa_cmd_sbp(struct qeth_card *card) +{ + return (card->info.type == QETH_CARD_TYPE_IQD) ? + IPA_CMD_SETBRIDGEPORT_IQD : + IPA_CMD_SETBRIDGEPORT_OSA; +} + static int qeth_bridgeport_query_support_cb(struct qeth_card *card, struct qeth_reply *reply, unsigned long data) { @@ -1753,7 +1771,7 @@ static void qeth_bridgeport_query_support(struct qeth_card *card) struct _qeth_sbp_cbctl cbctl; QETH_CARD_TEXT(card, 2, "brqsuppo"); - iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETBRIDGEPORT, 0); + iob = qeth_get_ipacmd_buffer(card, ipa_cmd_sbp(card), 0); if (!iob) return; cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); @@ -1830,7 +1848,7 @@ int qeth_bridgeport_query_ports(struct qeth_card *card, QETH_CARD_TEXT(card, 2, "brqports"); if (!(card->options.sbp.supported_funcs & IPA_SBP_QUERY_BRIDGE_PORTS)) return -EOPNOTSUPP; - iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETBRIDGEPORT, 0); + iob = qeth_get_ipacmd_buffer(card, ipa_cmd_sbp(card), 0); if (!iob) return -ENOMEM; cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); @@ -1897,7 +1915,7 @@ int qeth_bridgeport_setrole(struct qeth_card *card, enum qeth_sbp_roles role) } if (!(card->options.sbp.supported_funcs & setcmd)) return -EOPNOTSUPP; - iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETBRIDGEPORT, 0); + iob = qeth_get_ipacmd_buffer(card, ipa_cmd_sbp(card), 0); if (!iob) return -ENOMEM; cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); -- cgit v1.2.3 From ffe2a8536c556042d7f03edd45c8cc6a5fc32be5 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 8 May 2015 07:54:35 -0300 Subject: [media] DocBook/media: remove spurious space Looks ugly, a space before a period at the end of a sentence. Remove it. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index cff2ffd3c8a6..bfe666204888 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -1167,7 +1167,7 @@ will not block anymore, but return an &EPIPE;. The buffer timestamp has been taken from the CLOCK_MONOTONIC clock. To access the same clock outside V4L2, use - clock_gettime(2) . + clock_gettime(2). V4L2_BUF_FLAG_TIMESTAMP_COPY -- cgit v1.2.3 From 200a28050953d7ba6df434e8315e31f542556680 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 8 May 2015 07:55:01 -0300 Subject: [media] DocBook/media: improve timestamp documentation Explain which clock was used to make the timestamp. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/vidioc-dqevent.xml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/vidioc-dqevent.xml b/Documentation/DocBook/media/v4l/vidioc-dqevent.xml index 50ccd33948c1..c9c3c7713832 100644 --- a/Documentation/DocBook/media/v4l/vidioc-dqevent.xml +++ b/Documentation/DocBook/media/v4l/vidioc-dqevent.xml @@ -133,7 +133,10 @@ struct timespec timestamp - Event timestamp. + Event timestamp. The timestamp has been taken from the + CLOCK_MONOTONIC clock. To access the + same clock outside V4L2, use clock_gettime(2). + u32 -- cgit v1.2.3 From 9cae84b32dd52768cf2fd2fcb214c3f570676c4b Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 15 May 2015 07:28:02 -0300 Subject: [media] DocBook/media: fix syntax error Missing varlistentry tags. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/vidioc-qbuf.xml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/vidioc-qbuf.xml b/Documentation/DocBook/media/v4l/vidioc-qbuf.xml index 6cfc53b83a20..8b98a0e421fc 100644 --- a/Documentation/DocBook/media/v4l/vidioc-qbuf.xml +++ b/Documentation/DocBook/media/v4l/vidioc-qbuf.xml @@ -186,13 +186,15 @@ In that case the application should be able to safely reuse the buffer and continue streaming. + + EPIPE VIDIOC_DQBUF returns this on an empty capture queue for mem2mem codecs if a buffer with the V4L2_BUF_FLAG_LAST was already dequeued and no new buffers are expected to become available. - + -- cgit v1.2.3 From b92b8b35a2e38bde319fd1d68ec84628c1f1b0fb Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Tue, 12 May 2015 10:51:55 +0200 Subject: locking/arch: Rename set_mb() to smp_store_mb() Since set_mb() is really about an smp_mb() -- not a IO/DMA barrier like mb() rename it to match the recent smp_load_acquire() and smp_store_release(). Suggested-by: Linus Torvalds Signed-off-by: Peter Zijlstra (Intel) Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- Documentation/memory-barriers.txt | 6 +++--- arch/arm/include/asm/barrier.h | 2 +- arch/arm64/include/asm/barrier.h | 2 +- arch/ia64/include/asm/barrier.h | 7 +------ arch/metag/include/asm/barrier.h | 2 +- arch/mips/include/asm/barrier.h | 2 +- arch/powerpc/include/asm/barrier.h | 2 +- arch/s390/include/asm/barrier.h | 2 +- arch/sh/include/asm/barrier.h | 2 +- arch/sparc/include/asm/barrier_64.h | 2 +- arch/x86/include/asm/barrier.h | 4 ++-- arch/x86/um/asm/barrier.h | 3 ++- fs/select.c | 6 +++--- include/asm-generic/barrier.h | 4 ++-- include/linux/sched.h | 8 ++++---- kernel/futex.c | 2 +- kernel/locking/qspinlock_paravirt.h | 2 +- kernel/sched/wait.c | 4 ++-- 18 files changed, 29 insertions(+), 33 deletions(-) (limited to 'Documentation') diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index f95746189b5d..fe4020e4b468 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1662,7 +1662,7 @@ CPU from reordering them. There are some more advanced barrier functions: - (*) set_mb(var, value) + (*) smp_store_mb(var, value) This assigns the value to the variable and then inserts a full memory barrier after it, depending on the function. It isn't guaranteed to @@ -1975,7 +1975,7 @@ after it has altered the task state: CPU 1 =============================== set_current_state(); - set_mb(); + smp_store_mb(); STORE current->state LOAD event_indicated @@ -2016,7 +2016,7 @@ between the STORE to indicate the event and the STORE to set TASK_RUNNING: CPU 1 CPU 2 =============================== =============================== set_current_state(); STORE event_indicated - set_mb(); wake_up(); + smp_store_mb(); wake_up(); STORE current->state STORE current->state LOAD event_indicated diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 993150aea681..6c2327e1c732 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -81,7 +81,7 @@ do { \ #define read_barrier_depends() do { } while(0) #define smp_read_barrier_depends() do { } while(0) -#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) #define smp_mb__before_atomic() smp_mb() #define smp_mb__after_atomic() smp_mb() diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index ff7de78d01b8..0fa47c4275cb 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -114,7 +114,7 @@ do { \ #define read_barrier_depends() do { } while(0) #define smp_read_barrier_depends() do { } while(0) -#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) #define nop() asm volatile("nop"); #define smp_mb__before_atomic() smp_mb() diff --git a/arch/ia64/include/asm/barrier.h b/arch/ia64/include/asm/barrier.h index 03117e7b2ab8..843ba435e43b 100644 --- a/arch/ia64/include/asm/barrier.h +++ b/arch/ia64/include/asm/barrier.h @@ -77,12 +77,7 @@ do { \ ___p1; \ }) -/* - * XXX check on this ---I suspect what Linus really wants here is - * acquire vs release semantics but we can't discuss this stuff with - * Linus just yet. Grrr... - */ -#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) /* * The group barrier in front of the rsm & ssm are necessary to ensure diff --git a/arch/metag/include/asm/barrier.h b/arch/metag/include/asm/barrier.h index 97eb018a2933..5a696e507930 100644 --- a/arch/metag/include/asm/barrier.h +++ b/arch/metag/include/asm/barrier.h @@ -84,7 +84,7 @@ static inline void fence(void) #define read_barrier_depends() do { } while (0) #define smp_read_barrier_depends() do { } while (0) -#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) #define smp_store_release(p, v) \ do { \ diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index cff1bbdaa74a..7ecba84656d4 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -112,7 +112,7 @@ #define __WEAK_LLSC_MB " \n" #endif -#define set_mb(var, value) \ +#define smp_store_mb(var, value) \ do { WRITE_ONCE(var, value); smp_mb(); } while (0) #define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index 2a072e48780d..39505d660a70 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -34,7 +34,7 @@ #define rmb() __asm__ __volatile__ ("sync" : : : "memory") #define wmb() __asm__ __volatile__ ("sync" : : : "memory") -#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) #ifdef __SUBARCH_HAS_LWSYNC # define SMPWMB LWSYNC diff --git a/arch/s390/include/asm/barrier.h b/arch/s390/include/asm/barrier.h index b66cd53d35fc..e6f8615a11eb 100644 --- a/arch/s390/include/asm/barrier.h +++ b/arch/s390/include/asm/barrier.h @@ -36,7 +36,7 @@ #define smp_mb__before_atomic() smp_mb() #define smp_mb__after_atomic() smp_mb() -#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) #define smp_store_release(p, v) \ do { \ diff --git a/arch/sh/include/asm/barrier.h b/arch/sh/include/asm/barrier.h index 43715308b068..bf91037db4e0 100644 --- a/arch/sh/include/asm/barrier.h +++ b/arch/sh/include/asm/barrier.h @@ -32,7 +32,7 @@ #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") #endif -#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) +#define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) #include diff --git a/arch/sparc/include/asm/barrier_64.h b/arch/sparc/include/asm/barrier_64.h index 125fec7512f4..809941e33e12 100644 --- a/arch/sparc/include/asm/barrier_64.h +++ b/arch/sparc/include/asm/barrier_64.h @@ -40,7 +40,7 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ #define dma_rmb() rmb() #define dma_wmb() wmb() -#define set_mb(__var, __value) \ +#define smp_store_mb(__var, __value) \ do { WRITE_ONCE(__var, __value); membar_safe("#StoreLoad"); } while(0) #ifdef CONFIG_SMP diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index 9de5cde133a1..e51a8f803f55 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -35,12 +35,12 @@ #define smp_mb() mb() #define smp_rmb() dma_rmb() #define smp_wmb() barrier() -#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) +#define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) #else /* !SMP */ #define smp_mb() barrier() #define smp_rmb() barrier() #define smp_wmb() barrier() -#define set_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0) #endif /* SMP */ #define read_barrier_depends() do { } while (0) diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h index cc0cb01f346d..b9531d343134 100644 --- a/arch/x86/um/asm/barrier.h +++ b/arch/x86/um/asm/barrier.h @@ -39,7 +39,8 @@ #define smp_mb() barrier() #define smp_rmb() barrier() #define smp_wmb() barrier() -#define set_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0) + +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0) #define read_barrier_depends() do { } while (0) #define smp_read_barrier_depends() do { } while (0) diff --git a/fs/select.c b/fs/select.c index f684c750e08a..015547330e88 100644 --- a/fs/select.c +++ b/fs/select.c @@ -189,7 +189,7 @@ static int __pollwake(wait_queue_t *wait, unsigned mode, int sync, void *key) * doesn't imply write barrier and the users expect write * barrier semantics on wakeup functions. The following * smp_wmb() is equivalent to smp_wmb() in try_to_wake_up() - * and is paired with set_mb() in poll_schedule_timeout. + * and is paired with smp_store_mb() in poll_schedule_timeout. */ smp_wmb(); pwq->triggered = 1; @@ -244,7 +244,7 @@ int poll_schedule_timeout(struct poll_wqueues *pwq, int state, /* * Prepare for the next iteration. * - * The following set_mb() serves two purposes. First, it's + * The following smp_store_mb() serves two purposes. First, it's * the counterpart rmb of the wmb in pollwake() such that data * written before wake up is always visible after wake up. * Second, the full barrier guarantees that triggered clearing @@ -252,7 +252,7 @@ int poll_schedule_timeout(struct poll_wqueues *pwq, int state, * this problem doesn't exist for the first iteration as * add_wait_queue() has full barrier semantics. */ - set_mb(pwq->triggered, 0); + smp_store_mb(pwq->triggered, 0); return rc; } diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h index 3938716b44d7..e6a83d712ef6 100644 --- a/include/asm-generic/barrier.h +++ b/include/asm-generic/barrier.h @@ -66,8 +66,8 @@ #define smp_read_barrier_depends() do { } while (0) #endif -#ifndef set_mb -#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) +#ifndef smp_store_mb +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) #endif #ifndef smp_mb__before_atomic diff --git a/include/linux/sched.h b/include/linux/sched.h index 26a2e6122734..18f197223ebd 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -252,7 +252,7 @@ extern char ___assert_task_state[1 - 2*!!( #define set_task_state(tsk, state_value) \ do { \ (tsk)->task_state_change = _THIS_IP_; \ - set_mb((tsk)->state, (state_value)); \ + smp_store_mb((tsk)->state, (state_value)); \ } while (0) /* @@ -274,7 +274,7 @@ extern char ___assert_task_state[1 - 2*!!( #define set_current_state(state_value) \ do { \ current->task_state_change = _THIS_IP_; \ - set_mb(current->state, (state_value)); \ + smp_store_mb(current->state, (state_value)); \ } while (0) #else @@ -282,7 +282,7 @@ extern char ___assert_task_state[1 - 2*!!( #define __set_task_state(tsk, state_value) \ do { (tsk)->state = (state_value); } while (0) #define set_task_state(tsk, state_value) \ - set_mb((tsk)->state, (state_value)) + smp_store_mb((tsk)->state, (state_value)) /* * set_current_state() includes a barrier so that the write of current->state @@ -298,7 +298,7 @@ extern char ___assert_task_state[1 - 2*!!( #define __set_current_state(state_value) \ do { current->state = (state_value); } while (0) #define set_current_state(state_value) \ - set_mb(current->state, (state_value)) + smp_store_mb(current->state, (state_value)) #endif diff --git a/kernel/futex.c b/kernel/futex.c index 2579e407ff67..55ca63ad9622 100644 --- a/kernel/futex.c +++ b/kernel/futex.c @@ -2055,7 +2055,7 @@ static void futex_wait_queue_me(struct futex_hash_bucket *hb, struct futex_q *q, { /* * The task state is guaranteed to be set before another task can - * wake it. set_current_state() is implemented using set_mb() and + * wake it. set_current_state() is implemented using smp_store_mb() and * queue_me() calls spin_unlock() upon completion, both serializing * access to the hash list and forcing another memory barrier. */ diff --git a/kernel/locking/qspinlock_paravirt.h b/kernel/locking/qspinlock_paravirt.h index 27ab96dca68c..04ab18151cc8 100644 --- a/kernel/locking/qspinlock_paravirt.h +++ b/kernel/locking/qspinlock_paravirt.h @@ -175,7 +175,7 @@ static void pv_wait_node(struct mcs_spinlock *node) * * Matches the xchg() from pv_kick_node(). */ - set_mb(pn->state, vcpu_halted); + smp_store_mb(pn->state, vcpu_halted); if (!READ_ONCE(node->locked)) pv_wait(&pn->state, vcpu_halted); diff --git a/kernel/sched/wait.c b/kernel/sched/wait.c index 852143a79f36..9bc82329eaad 100644 --- a/kernel/sched/wait.c +++ b/kernel/sched/wait.c @@ -341,7 +341,7 @@ long wait_woken(wait_queue_t *wait, unsigned mode, long timeout) * condition being true _OR_ WQ_FLAG_WOKEN such that we will not miss * an event. */ - set_mb(wait->flags, wait->flags & ~WQ_FLAG_WOKEN); /* B */ + smp_store_mb(wait->flags, wait->flags & ~WQ_FLAG_WOKEN); /* B */ return timeout; } @@ -354,7 +354,7 @@ int woken_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *key) * doesn't imply write barrier and the users expects write * barrier semantics on wakeup functions. The following * smp_wmb() is equivalent to smp_wmb() in try_to_wake_up() - * and is paired with set_mb() in wait_woken(). + * and is paired with smp_store_mb() in wait_woken(). */ smp_wmb(); /* C */ wait->flags |= WQ_FLAG_WOKEN; -- cgit v1.2.3 From 3aed357ee499c71f589a2537af6ec7785029873f Mon Sep 17 00:00:00 2001 From: Zhiqiang Zhang Date: Mon, 18 May 2015 15:00:24 +0200 Subject: sched/dl/Documentation: Correct the definition of density as C_i/min{D_i,P_i} C_i/min{D_i,T_i}, where T_i is not referred before, should be substituted with C_i/min{D_i,P_i}. Signed-off-by: Zhiqiang Zhang Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-2-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index 21461a0441c1..194664bb8bbf 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -169,8 +169,8 @@ CONTENTS of all the tasks executing on a CPU if and only if the total utilisation of the tasks running on such a CPU is smaller or equal than 1. If D_i != P_i for some task, then it is possible to define the density of - a task as C_i/min{D_i,T_i}, and EDF is able to respect all the deadlines - of all the tasks running on a CPU if the sum sum_i C_i/min{D_i,T_i} of the + a task as C_i/min{D_i,P_i}, and EDF is able to respect all the deadlines + of all the tasks running on a CPU if the sum sum_i C_i/min{D_i,P_i} of the densities of the tasks running on such a CPU is smaller or equal than 1 (notice that this condition is only sufficient, and not necessary). -- cgit v1.2.3 From 3a3a58d4068382cf2e05f5c8fd3a0587836dacec Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:25 +0200 Subject: sched/dl/Documentation: Switch to American English This file previously mixed American and British English; switch to American for consistency. Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-3-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 32 +++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index 194664bb8bbf..af40d6cc776b 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -43,7 +43,7 @@ CONTENTS "deadline", to schedule tasks. A SCHED_DEADLINE task should receive "runtime" microseconds of execution time every "period" microseconds, and these "runtime" microseconds are available within "deadline" microseconds - from the beginning of the period. In order to implement this behaviour, + from the beginning of the period. In order to implement this behavior, every time the task wakes up, the scheduler computes a "scheduling deadline" consistent with the guarantee (using the CBS[2,3] algorithm). Tasks are then scheduled using EDF[1] on these scheduling deadlines (the task with the @@ -63,7 +63,7 @@ CONTENTS In more details, the CBS algorithm assigns scheduling deadlines to tasks in the following way: - - Each SCHED_DEADLINE task is characterised by the "runtime", + - Each SCHED_DEADLINE task is characterized by the "runtime", "deadline", and "period" parameters; - The state of the task is described by a "scheduling deadline", and @@ -78,7 +78,7 @@ CONTENTS then, if the scheduling deadline is smaller than the current time, or this condition is verified, the scheduling deadline and the - remaining runtime are re-initialised as + remaining runtime are re-initialized as scheduling deadline = current time + deadline remaining runtime = runtime @@ -129,7 +129,7 @@ CONTENTS A typical real-time task is composed of a repetition of computation phases (task instances, or jobs) which are activated on a periodic or sporadic fashion. - Each job J_j (where J_j is the j^th job of the task) is characterised by an + Each job J_j (where J_j is the j^th job of the task) is characterized by an arrival time r_j (the time when the job starts), an amount of computation time c_j needed to finish the job, and a job absolute deadline d_j, which is the time within which the job should be finished. The maximum execution @@ -137,20 +137,20 @@ CONTENTS A real-time task can be periodic with period P if r_{j+1} = r_j + P, or sporadic with minimum inter-arrival time P is r_{j+1} >= r_j + P. Finally, d_j = r_j + D, where D is the task's relative deadline. - The utilisation of a real-time task is defined as the ratio between its + The utilization of a real-time task is defined as the ratio between its WCET and its period (or minimum inter-arrival time), and represents the fraction of CPU time needed to execute the task. - If the total utilisation sum_i(WCET_i/P_i) is larger than M (with M equal + If the total utilization sum_i(WCET_i/P_i) is larger than M (with M equal to the number of CPUs), then the scheduler is unable to respect all the deadlines. - Note that total utilisation is defined as the sum of the utilisations + Note that total utilization is defined as the sum of the utilizations WCET_i/P_i over all the real-time tasks in the system. When considering multiple real-time tasks, the parameters of the i-th task are indicated with the "_i" suffix. - Moreover, if the total utilisation is larger than M, then we risk starving + Moreover, if the total utilization is larger than M, then we risk starving non- real-time tasks by real-time tasks. - If, instead, the total utilisation is smaller than M, then non real-time + If, instead, the total utilization is smaller than M, then non real-time tasks will not be starved and the system might be able to respect all the deadlines. As a matter of fact, in this case it is possible to provide an upper bound @@ -160,13 +160,13 @@ CONTENTS maximum tardiness of each task is smaller or equal than ((M − 1) · WCET_max − WCET_min)/(M − (M − 2) · U_max) + WCET_max where WCET_max = max_i{WCET_i} is the maximum WCET, WCET_min=min_i{WCET_i} - is the minimum WCET, and U_max = max_i{WCET_i/P_i} is the maximum utilisation. + is the minimum WCET, and U_max = max_i{WCET_i/P_i} is the maximum utilization. If M=1 (uniprocessor system), or in case of partitioned scheduling (each real-time task is statically assigned to one and only one CPU), it is possible to formally check if all the deadlines are respected. If D_i = P_i for all tasks, then EDF is able to respect all the deadlines - of all the tasks executing on a CPU if and only if the total utilisation + of all the tasks executing on a CPU if and only if the total utilization of the tasks running on such a CPU is smaller or equal than 1. If D_i != P_i for some task, then it is possible to define the density of a task as C_i/min{D_i,P_i}, and EDF is able to respect all the deadlines @@ -176,9 +176,9 @@ CONTENTS On multiprocessor systems with global EDF scheduling (non partitioned systems), a sufficient test for schedulability can not be based on the - utilisations (it can be shown that task sets with utilisations slightly + utilizations (it can be shown that task sets with utilizations slightly larger than 1 can miss deadlines regardless of the number of CPUs M). - However, as previously stated, enforcing that the total utilisation is smaller + However, as previously stated, enforcing that the total utilization is smaller than M is enough to guarantee that non real-time tasks are not starved and that the tardiness of real-time tasks has an upper bound. @@ -218,10 +218,10 @@ CONTENTS no guarantee can be given on the actual scheduling of the -deadline tasks. As already stated in Section 3, a necessary condition to be respected to - correctly schedule a set of real-time tasks is that the total utilisation + correctly schedule a set of real-time tasks is that the total utilization is smaller than M. When talking about -deadline tasks, this requires that the sum of the ratio between runtime and period for all tasks is smaller - than M. Notice that the ratio runtime/period is equivalent to the utilisation + than M. Notice that the ratio runtime/period is equivalent to the utilization of a "traditional" real-time task, and is also often referred to as "bandwidth". The interface used to control the CPU bandwidth that can be allocated @@ -251,7 +251,7 @@ CONTENTS The system wide settings are configured under the /proc virtual file system. For now the -rt knobs are used for -deadline admission control and the - -deadline runtime is accounted against the -rt runtime. We realise that this + -deadline runtime is accounted against the -rt runtime. We realize that this isn't entirely desirable; however, it is better to have a small interface for now, and be able to change it easily later. The ideal situation (see 5.) is to run -rt tasks from a -deadline server; in which case the -rt bandwidth is a -- cgit v1.2.3 From 3aa2dbe27f76528660e18b21f88a2c78ea8996ba Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:26 +0200 Subject: sched/dl/Documentation: Fix typos Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-4-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index af40d6cc776b..0f51a1a2f4b9 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -52,7 +52,7 @@ CONTENTS "admission control" strategy (see Section "4. Bandwidth management") is used (clearly, if the system is overloaded this guarantee cannot be respected). - Summing up, the CBS[2,3] algorithms assigns scheduling deadlines to tasks so + Summing up, the CBS[2,3] algorithm assigns scheduling deadlines to tasks so that each task runs for at most its runtime every period, avoiding any interference between different tasks (bandwidth isolation), while the EDF[1] algorithm selects the task with the earliest scheduling deadline as the one @@ -190,7 +190,7 @@ CONTENTS - deadline = D - period <= P - IOW, if runtime >= WCET and if period is >= P, then the scheduling deadlines + IOW, if runtime >= WCET and if period is <= P, then the scheduling deadlines and the absolute deadlines (d_j) coincide, so a proper admission control allows to respect the jobs' absolute deadlines for this task (this is what is called "hard schedulability property" and is an extension of Lemma 1 of [2]). -- cgit v1.2.3 From 48355c4775741ee15b66bad7d09b263d93ce86f8 Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:27 +0200 Subject: sched/dl/Documentation: Use consistent naming The name "C_i" was used (without previously defining it) instead of "WCET_i". Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-5-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index 0f51a1a2f4b9..73ef489fcecf 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -169,8 +169,8 @@ CONTENTS of all the tasks executing on a CPU if and only if the total utilization of the tasks running on such a CPU is smaller or equal than 1. If D_i != P_i for some task, then it is possible to define the density of - a task as C_i/min{D_i,P_i}, and EDF is able to respect all the deadlines - of all the tasks running on a CPU if the sum sum_i C_i/min{D_i,P_i} of the + a task as WCET_i/min{D_i,P_i}, and EDF is able to respect all the deadlines + of all the tasks running on a CPU if the sum sum_i WCET_i/min{D_i,P_i} of the densities of the tasks running on such a CPU is smaller or equal than 1 (notice that this condition is only sufficient, and not necessary). -- cgit v1.2.3 From c2a684930fce07f19d1a52d7bbe7474fe64fde31 Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:28 +0200 Subject: sched/dl/Documentation: Clarify indexing notation The "_i" index is used in this document to to denote a particular task, so "sum_i", "max_i" and "min_i" might be confusing. Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-6-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index 73ef489fcecf..c794ebfc08a5 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -133,7 +133,7 @@ CONTENTS arrival time r_j (the time when the job starts), an amount of computation time c_j needed to finish the job, and a job absolute deadline d_j, which is the time within which the job should be finished. The maximum execution - time max_j{c_j} is called "Worst Case Execution Time" (WCET) for the task. + time max{c_j} is called "Worst Case Execution Time" (WCET) for the task. A real-time task can be periodic with period P if r_{j+1} = r_j + P, or sporadic with minimum inter-arrival time P is r_{j+1} >= r_j + P. Finally, d_j = r_j + D, where D is the task's relative deadline. @@ -141,7 +141,7 @@ CONTENTS WCET and its period (or minimum inter-arrival time), and represents the fraction of CPU time needed to execute the task. - If the total utilization sum_i(WCET_i/P_i) is larger than M (with M equal + If the total utilization U=sum(WCET_i/P_i) is larger than M (with M equal to the number of CPUs), then the scheduler is unable to respect all the deadlines. Note that total utilization is defined as the sum of the utilizations @@ -159,8 +159,8 @@ CONTENTS More precisely, it can be proven that using a global EDF scheduler the maximum tardiness of each task is smaller or equal than ((M − 1) · WCET_max − WCET_min)/(M − (M − 2) · U_max) + WCET_max - where WCET_max = max_i{WCET_i} is the maximum WCET, WCET_min=min_i{WCET_i} - is the minimum WCET, and U_max = max_i{WCET_i/P_i} is the maximum utilization. + where WCET_max = max{WCET_i} is the maximum WCET, WCET_min=min{WCET_i} + is the minimum WCET, and U_max = max{WCET_i/P_i} is the maximum utilization. If M=1 (uniprocessor system), or in case of partitioned scheduling (each real-time task is statically assigned to one and only one CPU), it is @@ -170,7 +170,7 @@ CONTENTS of the tasks running on such a CPU is smaller or equal than 1. If D_i != P_i for some task, then it is possible to define the density of a task as WCET_i/min{D_i,P_i}, and EDF is able to respect all the deadlines - of all the tasks running on a CPU if the sum sum_i WCET_i/min{D_i,P_i} of the + of all the tasks running on a CPU if the sum sum(WCET_i/min{D_i,P_i}) of the densities of the tasks running on such a CPU is smaller or equal than 1 (notice that this condition is only sufficient, and not necessary). -- cgit v1.2.3 From e0deda8142a60e4a39d5ba2ea47294a851b4309a Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:29 +0200 Subject: sched/dl/Documentation: Add some notes on EDF schedulability Add a short discussion about sufficient and necessary schedulability tests, and add a simple example showing that if D_i != P_i then density based tests are only sufficient. Also add some references to scientific papers on schedulability tests for EDF that are both necessary and sufficient, and on their computational complexity. Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-7-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 45 ++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index c794ebfc08a5..bd4123b761e5 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -137,6 +137,9 @@ CONTENTS A real-time task can be periodic with period P if r_{j+1} = r_j + P, or sporadic with minimum inter-arrival time P is r_{j+1} >= r_j + P. Finally, d_j = r_j + D, where D is the task's relative deadline. + Summing up, a real-time task can be described as + Task = (WCET, D, P) + The utilization of a real-time task is defined as the ratio between its WCET and its period (or minimum inter-arrival time), and represents the fraction of CPU time needed to execute the task. @@ -170,9 +173,35 @@ CONTENTS of the tasks running on such a CPU is smaller or equal than 1. If D_i != P_i for some task, then it is possible to define the density of a task as WCET_i/min{D_i,P_i}, and EDF is able to respect all the deadlines - of all the tasks running on a CPU if the sum sum(WCET_i/min{D_i,P_i}) of the - densities of the tasks running on such a CPU is smaller or equal than 1 - (notice that this condition is only sufficient, and not necessary). + of all the tasks running on a CPU if the sum of the densities of the tasks + running on such a CPU is smaller or equal than 1: + sum(WCET_i / min{D_i, P_i}) <= 1 + It is important to notice that this condition is only sufficient, and not + necessary: there are task sets that are schedulable, but do not respect the + condition. For example, consider the task set {Task_1,Task_2} composed by + Task_1=(50ms,50ms,100ms) and Task_2=(10ms,100ms,100ms). + EDF is clearly able to schedule the two tasks without missing any deadline + (Task_1 is scheduled as soon as it is released, and finishes just in time + to respect its deadline; Task_2 is scheduled immediately after Task_1, hence + its response time cannot be larger than 50ms + 10ms = 60ms) even if + 50 / min{50,100} + 10 / min{100, 100} = 50 / 50 + 10 / 100 = 1.1 + Of course it is possible to test the exact schedulability of tasks with + D_i != P_i (checking a condition that is both sufficient and necessary), + but this cannot be done by comparing the total utilization or density with + a constant. Instead, the so called "processor demand" approach can be used, + computing the total amount of CPU time h(t) needed by all the tasks to + respect all of their deadlines in a time interval of size t, and comparing + such a time with the interval size t. If h(t) is smaller than t (that is, + the amount of time needed by the tasks in a time interval of size t is + smaller than the size of the interval) for all the possible values of t, then + EDF is able to schedule the tasks respecting all of their deadlines. Since + performing this check for all possible values of t is impossible, it has been + proven[4,5,6] that it is sufficient to perform the test for values of t + between 0 and a maximum value L. The cited papers contain all of the + mathematical details and explain how to compute h(t) and L. + In any case, this kind of analysis is too complex as well as too + time-consuming to be performed on-line. Hence, as explained in Section + 4 Linux uses an admission test based on the tasks' utilizations. On multiprocessor systems with global EDF scheduling (non partitioned systems), a sufficient test for schedulability can not be based on the @@ -206,6 +235,16 @@ CONTENTS Symposium, 1998. http://retis.sssup.it/~giorgio/paps/1998/rtss98-cbs.pdf 3 - L. Abeni. Server Mechanisms for Multimedia Applications. ReTiS Lab Technical Report. http://disi.unitn.it/~abeni/tr-98-01.pdf + 4 - J. Y. Leung and M.L. Merril. A Note on Preemptive Scheduling of + Periodic, Real-Time Tasks. Information Processing Letters, vol. 11, + no. 3, pp. 115-118, 1980. + 5 - S. K. Baruah, A. K. Mok and L. E. Rosier. Preemptively Scheduling + Hard-Real-Time Sporadic Tasks on One Processor. Proceedings of the + 11th IEEE Real-time Systems Symposium, 1990. + 6 - S. K. Baruah, L. E. Rosier and R. R. Howell. Algorithms and Complexity + Concerning the Preemptive Scheduling of Periodic Real-Time tasks on + One Processor. Real-Time Systems Journal, vol. 4, no. 2, pp 301-324, + 1990. 4. Bandwidth management ======================= -- cgit v1.2.3 From 134136c4b730c1a4830a8b74e2717d858291361b Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:30 +0200 Subject: sched/dl/Documentation: Add some references Add a description of the Dhall's effect, some discussion about schedulability tests for global EDF, and references to real-time literature. Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-8-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 73 +++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index bd4123b761e5..984a01d3c68f 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -163,7 +163,8 @@ CONTENTS maximum tardiness of each task is smaller or equal than ((M − 1) · WCET_max − WCET_min)/(M − (M − 2) · U_max) + WCET_max where WCET_max = max{WCET_i} is the maximum WCET, WCET_min=min{WCET_i} - is the minimum WCET, and U_max = max{WCET_i/P_i} is the maximum utilization. + is the minimum WCET, and U_max = max{WCET_i/P_i} is the maximum + utilization[12]. If M=1 (uniprocessor system), or in case of partitioned scheduling (each real-time task is statically assigned to one and only one CPU), it is @@ -205,11 +206,48 @@ CONTENTS On multiprocessor systems with global EDF scheduling (non partitioned systems), a sufficient test for schedulability can not be based on the - utilizations (it can be shown that task sets with utilizations slightly - larger than 1 can miss deadlines regardless of the number of CPUs M). - However, as previously stated, enforcing that the total utilization is smaller - than M is enough to guarantee that non real-time tasks are not starved and - that the tardiness of real-time tasks has an upper bound. + utilizations or densities: it can be shown that even if D_i = P_i task + sets with utilizations slightly larger than 1 can miss deadlines regardless + of the number of CPUs. + + Consider a set {Task_1,...Task_{M+1}} of M+1 tasks on a system with M + CPUs, with the first task Task_1=(P,P,P) having period, relative deadline + and WCET equal to P. The remaining M tasks Task_i=(e,P-1,P-1) have an + arbitrarily small worst case execution time (indicated as "e" here) and a + period smaller than the one of the first task. Hence, if all the tasks + activate at the same time t, global EDF schedules these M tasks first + (because their absolute deadlines are equal to t + P - 1, hence they are + smaller than the absolute deadline of Task_1, which is t + P). As a + result, Task_1 can be scheduled only at time t + e, and will finish at + time t + e + P, after its absolute deadline. The total utilization of the + task set is U = M · e / (P - 1) + P / P = M · e / (P - 1) + 1, and for small + values of e this can become very close to 1. This is known as "Dhall's + effect"[7]. Note: the example in the original paper by Dhall has been + slightly simplified here (for example, Dhall more correctly computed + lim_{e->0}U). + + More complex schedulability tests for global EDF have been developed in + real-time literature[8,9], but they are not based on a simple comparison + between total utilization (or density) and a fixed constant. If all tasks + have D_i = P_i, a sufficient schedulability condition can be expressed in + a simple way: + sum(WCET_i / P_i) <= M - (M - 1) · U_max + where U_max = max{WCET_i / P_i}[10]. Notice that for U_max = 1, + M - (M - 1) · U_max becomes M - M + 1 = 1 and this schedulability condition + just confirms the Dhall's effect. A more complete survey of the literature + about schedulability tests for multi-processor real-time scheduling can be + found in [11]. + + As seen, enforcing that the total utilization is smaller than M does not + guarantee that global EDF schedules the tasks without missing any deadline + (in other words, global EDF is not an optimal scheduling algorithm). However, + a total utilization smaller than M is enough to guarantee that non real-time + tasks are not starved and that the tardiness of real-time tasks has an upper + bound[12] (as previously noted). Different bounds on the maximum tardiness + experienced by real-time tasks have been developed in various papers[13,14], + but the theoretical result that is important for SCHED_DEADLINE is that if + the total utilization is smaller or equal than M then the response times of + the tasks are limited. SCHED_DEADLINE can be used to schedule real-time tasks guaranteeing that the jobs' deadlines of a task are respected. In order to do this, a task @@ -245,6 +283,29 @@ CONTENTS Concerning the Preemptive Scheduling of Periodic Real-Time tasks on One Processor. Real-Time Systems Journal, vol. 4, no. 2, pp 301-324, 1990. + 7 - S. J. Dhall and C. L. Liu. On a real-time scheduling problem. Operations + research, vol. 26, no. 1, pp 127-140, 1978. + 8 - T. Baker. Multiprocessor EDF and Deadline Monotonic Schedulability + Analysis. Proceedings of the 24th IEEE Real-Time Systems Symposium, 2003. + 9 - T. Baker. An Analysis of EDF Schedulability on a Multiprocessor. + IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 8, + pp 760-768, 2005. + 10 - J. Goossens, S. Funk and S. Baruah, Priority-Driven Scheduling of + Periodic Task Systems on Multiprocessors. Real-Time Systems Journal, + vol. 25, no. 2–3, pp. 187–205, 2003. + 11 - R. Davis and A. Burns. A Survey of Hard Real-Time Scheduling for + Multiprocessor Systems. ACM Computing Surveys, vol. 43, no. 4, 2011. + http://www-users.cs.york.ac.uk/~robdavis/papers/MPSurveyv5.0.pdf + 12 - U. C. Devi and J. H. Anderson. Tardiness Bounds under Global EDF + Scheduling on a Multiprocessor. Real-Time Systems Journal, vol. 32, + no. 2, pp 133-189, 2008. + 13 - P. Valente and G. Lipari. An Upper Bound to the Lateness of Soft + Real-Time Tasks Scheduled by EDF on Multiprocessors. Proceedings of + the 26th IEEE Real-Time Systems Symposium, 2005. + 14 - J. Erickson, U. Devi and S. Baruah. Improved tardiness bounds for + Global EDF. Proceedings of the 22nd Euromicro Conference on + Real-Time Systems, 2010. + 4. Bandwidth management ======================= -- cgit v1.2.3 From 78740858903460d4b926b9a90c705fcb6103da54 Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:31 +0200 Subject: sched/dl/Documentation: Clarify the relationship between tasks' deadlines and absolute scheduling deadlines Clarify what is the relationship between tasks' parameters and scheduling parameters, explaining how to set the scheduling parameters so that all the absolute deadlines of a task are respected. Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-9-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index 984a01d3c68f..2a924e19912a 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -249,9 +249,17 @@ CONTENTS the total utilization is smaller or equal than M then the response times of the tasks are limited. - SCHED_DEADLINE can be used to schedule real-time tasks guaranteeing that - the jobs' deadlines of a task are respected. In order to do this, a task - must be scheduled by setting: + Finally, it is important to understand the relationship between the + SCHED_DEADLINE scheduling parameters described in Section 2 (runtime, + deadline and period) and the real-time task parameters (WCET, D, P) + described in this section. Note that the tasks' temporal constraints are + represented by its absolute deadlines d_j = r_j + D described above, while + SCHED_DEADLINE schedules the tasks according to scheduling deadlines (see + Section 2). + If an admission test is used to guarantee that the scheduling deadlines + are respected, then SCHED_DEADLINE can be used to schedule real-time tasks + guaranteeing that all the jobs' deadlines of a task are respected. + In order to do this, a task must be scheduled by setting: - runtime >= WCET - deadline = D -- cgit v1.2.3 From 6aaa10254dfe61c8c5e87c26e21be0664782a5b4 Mon Sep 17 00:00:00 2001 From: Luca Abeni Date: Mon, 18 May 2015 15:00:32 +0200 Subject: sched/dl/Documentation: Split Section 3 Introduce 4 subsections to make Section 3 more readable. Signed-off-by: Luca Abeni Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: henrik@austad.us Cc: juri.lelli@gmail.com Cc: raistlin@linux.it Link: http://lkml.kernel.org/r/1431954032-16473-10-git-send-email-luca.abeni@unitn.it Signed-off-by: Ingo Molnar --- Documentation/scheduler/sched-deadline.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation') diff --git a/Documentation/scheduler/sched-deadline.txt b/Documentation/scheduler/sched-deadline.txt index 2a924e19912a..e114513a2731 100644 --- a/Documentation/scheduler/sched-deadline.txt +++ b/Documentation/scheduler/sched-deadline.txt @@ -8,6 +8,10 @@ CONTENTS 1. Overview 2. Scheduling algorithm 3. Scheduling Real-Time Tasks + 3.1 Definitions + 3.2 Schedulability Analysis for Uniprocessor Systems + 3.3 Schedulability Analysis for Multiprocessor Systems + 3.4 Relationship with SCHED_DEADLINE Parameters 4. Bandwidth management 4.1 System-wide settings 4.2 Task interface @@ -126,6 +130,9 @@ CONTENTS suited for periodic or sporadic real-time tasks that need guarantees on their timing behavior, e.g., multimedia, streaming, control applications, etc. +3.1 Definitions +------------------------ + A typical real-time task is composed of a repetition of computation phases (task instances, or jobs) which are activated on a periodic or sporadic fashion. @@ -166,6 +173,9 @@ CONTENTS is the minimum WCET, and U_max = max{WCET_i/P_i} is the maximum utilization[12]. +3.2 Schedulability Analysis for Uniprocessor Systems +------------------------ + If M=1 (uniprocessor system), or in case of partitioned scheduling (each real-time task is statically assigned to one and only one CPU), it is possible to formally check if all the deadlines are respected. @@ -204,6 +214,9 @@ CONTENTS time-consuming to be performed on-line. Hence, as explained in Section 4 Linux uses an admission test based on the tasks' utilizations. +3.3 Schedulability Analysis for Multiprocessor Systems +------------------------ + On multiprocessor systems with global EDF scheduling (non partitioned systems), a sufficient test for schedulability can not be based on the utilizations or densities: it can be shown that even if D_i = P_i task @@ -249,6 +262,9 @@ CONTENTS the total utilization is smaller or equal than M then the response times of the tasks are limited. +3.4 Relationship with SCHED_DEADLINE Parameters +------------------------ + Finally, it is important to understand the relationship between the SCHED_DEADLINE scheduling parameters described in Section 2 (runtime, deadline and period) and the real-time task parameters (WCET, D, P) -- cgit v1.2.3 From 9bf63cf858a5530df4fb48ab170cb7dbcab18d5e Mon Sep 17 00:00:00 2001 From: Inha Song Date: Mon, 4 May 2015 13:42:14 +0900 Subject: mfd: arizona: Update DT binding to support hpdet channel This patch add device tree bindings for the pdata needed to configure the Accessory Detect Mode select when Headphone detection. Signed-off-by: Inha Song Acked-by: Lee Jones Acked-by: Charles Keepax Signed-off-by: Chanwoo Choi --- Documentation/devicetree/bindings/mfd/arizona.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 7665aa95979f..32a71b76794f 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -62,6 +62,12 @@ Optional properties: present, the number of values should be less than or equal to the number of inputs, unspecified inputs will use the chip default. + - wlf,hpdet-channel : Headphone detection channel. + ARIZONA_ACCDET_MODE_HPL or 1 - Headphone detect mode is set to HPDETL + ARIZONA_ACCDET_MODE_HPR or 2 - Headphone detect mode is set to HPDETR + If this node is not mentioned or if the value is unknown, then + headphone detection mode is set to HPDETL. + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt -- cgit v1.2.3 From b016951e897b5bd06abfb732012f67b461fb1e2e Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 19 May 2015 10:20:13 +0200 Subject: ALSA: hda - Add headset-mode* model options for ALC269 & co Modern machines tend to have only one headset jack nowadays, and they often need these quirks. Let's allow them applicable via model option for ease of debugging. Signed-off-by: Takashi Iwai --- Documentation/sound/alsa/HD-Audio-Models.txt | 2 ++ sound/pci/hda/patch_realtek.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/sound/alsa/HD-Audio-Models.txt b/Documentation/sound/alsa/HD-Audio-Models.txt index 5a3163cac6c3..d92b85d38adc 100644 --- a/Documentation/sound/alsa/HD-Audio-Models.txt +++ b/Documentation/sound/alsa/HD-Audio-Models.txt @@ -29,6 +29,8 @@ ALC269/270/275/276/28x/29x alc271-dmic Enable ALC271X digital mic workaround inv-dmic Inverted internal mic workaround headset-mic Indicates a combined headset (headphone+mic) jack + headset-mode More comprehensive headset support for ALC269 & co + headset-mode-no-hp-mic Headset mode support without headphone mic lenovo-dock Enables docking station I/O for some Lenovos dell-headset-multi Headset jack, which can also be used as mic-in dell-headset-dock Headset jack (without mic-in), and also dock I/O diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 6e1c8c34e841..4d11fbfca5e2 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -5242,6 +5242,8 @@ static const struct hda_model_fixup alc269_fixup_models[] = { {.id = ALC271_FIXUP_DMIC, .name = "alc271-dmic"}, {.id = ALC269_FIXUP_INV_DMIC, .name = "inv-dmic"}, {.id = ALC269_FIXUP_HEADSET_MIC, .name = "headset-mic"}, + {.id = ALC269_FIXUP_HEADSET_MODE, .name = "headset-mode"}, + {.id = ALC269_FIXUP_HEADSET_MODE_NO_HP_MIC, .name = "headset-mode-no-hp-mic"}, {.id = ALC269_FIXUP_LENOVO_DOCK, .name = "lenovo-dock"}, {.id = ALC269_FIXUP_HP_GPIO_LED, .name = "hp-gpio-led"}, {.id = ALC269_FIXUP_DELL1_MIC_NO_PRESENCE, .name = "dell-headset-multi"}, -- cgit v1.2.3 From 1882b0577b5b67e7b663be4e8126997423b6cb6f Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 19 May 2015 10:21:57 +0200 Subject: ALSA: hda - Sync HD-Audio-Models.txt for Realtek codecs Added missing model entries and updated the codec names. Signed-off-by: Takashi Iwai --- Documentation/sound/alsa/HD-Audio-Models.txt | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/sound/alsa/HD-Audio-Models.txt b/Documentation/sound/alsa/HD-Audio-Models.txt index d92b85d38adc..ec099d4343f2 100644 --- a/Documentation/sound/alsa/HD-Audio-Models.txt +++ b/Documentation/sound/alsa/HD-Audio-Models.txt @@ -11,7 +11,10 @@ ALC880 ALC260 ====== - N/A + gpio1 Enable GPIO1 + coef Enable EAPD via COEF table + fujitsu Quirk for FSC S7020 + fujitsu-jwse Quirk for FSC S7020 with jack modes and HP mic support ALC262 ====== @@ -20,8 +23,9 @@ ALC262 ALC267/268 ========== inv-dmic Inverted internal mic workaround + hp-eapd Disable HP EAPD on NID 0x15 -ALC269/270/275/276/28x/29x +ALC22x/23x/25x/269/27x/28x/29x (and vendor-specific ALC3xxx models) ====== laptop-amic Laptops with analog-mic input laptop-dmic Laptops with digital-mic input @@ -32,8 +36,12 @@ ALC269/270/275/276/28x/29x headset-mode More comprehensive headset support for ALC269 & co headset-mode-no-hp-mic Headset mode support without headphone mic lenovo-dock Enables docking station I/O for some Lenovos + hp-gpio-led GPIO LED support on HP laptops dell-headset-multi Headset jack, which can also be used as mic-in dell-headset-dock Headset jack (without mic-in), and also dock I/O + alc283-dac-wcaps Fixups for Chromebook with ALC283 + alc283-sense-combo Combo jack sensing on ALC283 + tpt440-dock Pin configs for Lenovo Thinkpad Dock support ALC66x/67x/892 ============== -- cgit v1.2.3 From 8a88375c3866901753adc4f957f25540cbe11521 Mon Sep 17 00:00:00 2001 From: Hongzhou Yang Date: Mon, 18 May 2015 23:11:12 -0700 Subject: pinctrl: mediatek: Modify pinctrl bindings for mt6397. Since 6397 is no need to support interrupt controller, moving interrupt controller relate property to optional list. Also adding mt8173 and mt8127 to bindings. Signed-off-by: Hongzhou Yang Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 5868a0f7255d..0480bc31bfd7 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -3,9 +3,11 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: -- compatible: value should be either of the following. +- compatible: value should be one of the following. (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. -- mediatek,pctl-regmap: Should be a phandle of the syscfg node. + (b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. + (c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. + (d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. - gpio-controller : Marks the device node as a gpio controller. @@ -24,6 +26,9 @@ Required properties: Only the following flags are supported: 0 - GPIO_ACTIVE_HIGH 1 - GPIO_ACTIVE_LOW + +Optional properties: +- mediatek,pctl-regmap: Should be a phandle of the syscfg node. - reg: physicall address base for EINT registers - interrupt-controller: Marks the device node as an interrupt controller - #interrupt-cells: Should be two. -- cgit v1.2.3 From 3a0aee4801d475b64a408539c01ec0d17d52192b Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 22 Apr 2015 13:16:47 +0200 Subject: x86/fpu: Rename math_state_restore() to fpu__restore() Move to the new fpu__*() namespace. Reviewed-by: Borislav Petkov Cc: Andy Lutomirski Cc: Dave Hansen Cc: Fenghua Yu Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Oleg Nesterov Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- Documentation/preempt-locking.txt | 2 +- arch/x86/include/asm/i387.h | 2 +- arch/x86/kernel/fpu/core.c | 6 +++--- arch/x86/kernel/fpu/xsave.c | 2 +- arch/x86/kernel/process_32.c | 2 +- arch/x86/kernel/process_64.c | 2 +- arch/x86/kernel/traps.c | 2 +- drivers/lguest/x86/core.c | 4 ++-- 8 files changed, 11 insertions(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/preempt-locking.txt b/Documentation/preempt-locking.txt index 57883ca2498b..e89ce6624af2 100644 --- a/Documentation/preempt-locking.txt +++ b/Documentation/preempt-locking.txt @@ -48,7 +48,7 @@ preemption must be disabled around such regions. Note, some FPU functions are already explicitly preempt safe. For example, kernel_fpu_begin and kernel_fpu_end will disable and enable preemption. -However, math_state_restore must be called with preemption disabled. +However, fpu__restore() must be called with preemption disabled. RULE #3: Lock acquire and release must be performed by same task diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h index d6fc84440b73..c8ee395dd6c6 100644 --- a/arch/x86/include/asm/i387.h +++ b/arch/x86/include/asm/i387.h @@ -23,7 +23,7 @@ extern void fpstate_init(struct fpu *fpu); extern void fpu__flush_thread(struct task_struct *tsk); extern int dump_fpu(struct pt_regs *, struct user_i387_struct *); -extern void math_state_restore(void); +extern void fpu__restore(void); extern bool irq_fpu_usable(void); diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 7add2fb7369e..15c3cf7bd160 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -228,7 +228,7 @@ static int fpu__unlazy_stopped(struct task_struct *child) } /* - * 'math_state_restore()' saves the current math information in the + * 'fpu__restore()' saves the current math information in the * old math state array, and gets the new ones from the current task * * Careful.. There are problems with IBM-designed IRQ13 behaviour. @@ -237,7 +237,7 @@ static int fpu__unlazy_stopped(struct task_struct *child) * Must be called with kernel preemption disabled (eg with local * local interrupts as in the case of do_device_not_available). */ -void math_state_restore(void) +void fpu__restore(void) { struct task_struct *tsk = current; @@ -267,7 +267,7 @@ void math_state_restore(void) } kernel_fpu_enable(); } -EXPORT_SYMBOL_GPL(math_state_restore); +EXPORT_SYMBOL_GPL(fpu__restore); void fpu__flush_thread(struct task_struct *tsk) { diff --git a/arch/x86/kernel/fpu/xsave.c b/arch/x86/kernel/fpu/xsave.c index 163b5cc582ef..d913d5024901 100644 --- a/arch/x86/kernel/fpu/xsave.c +++ b/arch/x86/kernel/fpu/xsave.c @@ -404,7 +404,7 @@ int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size) set_used_math(); if (use_eager_fpu()) { preempt_disable(); - math_state_restore(); + fpu__restore(); preempt_enable(); } diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 84d647d4b14d..1a0edce626b2 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -295,7 +295,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) * Leave lazy mode, flushing any hypercalls made here. * This must be done before restoring TLS segments so * the GDT and LDT are properly updated, and must be - * done before math_state_restore, so the TS bit is up + * done before fpu__restore(), so the TS bit is up * to date. */ arch_end_context_switch(next_p); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index ae6efeccb46e..99cc4b8589ad 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -298,7 +298,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) * Leave lazy mode, flushing any hypercalls made here. This * must be done after loading TLS entries in the GDT but before * loading segments that might reference them, and and it must - * be done before math_state_restore, so the TS bit is up to + * be done before fpu__restore(), so the TS bit is up to * date. */ arch_end_context_switch(next_p); diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 63c7fc3677b4..22ad90a40dbf 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -846,7 +846,7 @@ do_device_not_available(struct pt_regs *regs, long error_code) return; } #endif - math_state_restore(); /* interrupts still off */ + fpu__restore(); /* interrupts still off */ #ifdef CONFIG_X86_32 conditional_sti(regs); #endif diff --git a/drivers/lguest/x86/core.c b/drivers/lguest/x86/core.c index 30f2aef69d78..bcb534a5512d 100644 --- a/drivers/lguest/x86/core.c +++ b/drivers/lguest/x86/core.c @@ -297,12 +297,12 @@ void lguest_arch_run_guest(struct lg_cpu *cpu) /* * Similarly, if we took a trap because the Guest used the FPU, * we have to restore the FPU it expects to see. - * math_state_restore() may sleep and we may even move off to + * fpu__restore() may sleep and we may even move off to * a different CPU. So all the critical stuff should be done * before this. */ else if (cpu->regs->trapnum == 7 && !user_has_fpu()) - math_state_restore(); + fpu__restore(); } /*H:130 -- cgit v1.2.3 From f9367793293d2262460942b0a4904c21857a1a8b Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 18 May 2015 07:28:32 +0000 Subject: pinctrl: sirf: add sirf atlas7 pinctrl and gpio support The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-atlas7.txt | 50 + .../devicetree/bindings/pinctrl/pinctrl-atlas7.txt | 109 + drivers/pinctrl/Kconfig | 2 + drivers/pinctrl/sirf/Makefile | 1 + drivers/pinctrl/sirf/pinctrl-atlas7.c | 4639 ++++++++++++++++++++ 5 files changed, 4801 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-atlas7.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt create mode 100644 drivers/pinctrl/sirf/pinctrl-atlas7.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt new file mode 100644 index 000000000000..d7e123fc90b5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt @@ -0,0 +1,50 @@ +CSR SiRFatlas7 GPIO controller bindings + +Required properties: +- compatible : "sirf,atlas7-gpio" +- reg : Address range of the pinctrl registers +- interrupts : Interrupts used by every GPIO group +- gpio-banks : How many gpio banks on this controller +- gpio-controller : Indicates this device is a GPIO controller +- interrupt-controller : Marks the device node as an interrupt controller + +The GPIO controller also acts as an interrupt controller. It uses the default +two cells specifier as described in Documentation/devicetree/bindings/ +interrupt-controller/interrupts.txt. + +Example: + + gpio_0: gpio_mediam@17040000 { + compatible = "sirf,atlas7-gpio"; + reg = <0x17040000 0x1000>; + interrupts = <0 13 0>, <0 14 0>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + gpio-controller; + interrupt-controller; + + gpio-banks = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 32 0 0>; + gpio-ranges-group-names = "lvds_gpio_grp", + "uart_nand_gpio_grp"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio_1 15 0>; + ... + }; + + led2 { + gpios = <&gpio_2 34 0>; + ... + }; + }; + +Please refer to gpio.txt in this directory for details of the common +gpio properties used by devices. diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt new file mode 100644 index 000000000000..eecf028ff485 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt @@ -0,0 +1,109 @@ +CSR SiRFatlas7 pinmux controller + +Required properties: +- compatible : "sirf,atlas7-ioc" +- reg : Address range of the pinctrl registers + +For example, pinctrl might have properties like the following: + pinctrl: ioc@18880000 { + compatible = "sirf,atlas7-ioc"; + reg = <0x18880000 0x1000>; + + a_ac97_pmx: ac97@0 { + ac97 { + groups = "audio_ac97_grp"; + function = "audio_ac97"; + }; + }; + + ... + + sd2_pmx: sd2@0 { + sd2 { + groups = "sd2_grp0"; + function = "sd2"; + }; + }; + + ... + + + sample0_cfg: sample0@0 { + sample0 { + pins = "ldd_0", "ldd_1"; + bias-pull-up; + }; + }; + + sample1_cfg: sample1@0 { + sample1 { + pins = "ldd_2", "ldd_3"; + input-schmitt-enable; + }; + }; + + sample2_cfg: sample2@0 { + sample2 { + groups = "uart4_nopause_grp"; + bias-pull-down; + }; + }; + + sample3_cfg: sample3@0 { + sample3 { + pins = "ldd_4", "ldd_5"; + drive-strength = <2>; + }; + }; + }; + +Please refer to pinctrl-bindings.txt in this directory for details of the common +pinctrl bindings used by client devices. + +SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes. +Each of these subnodes represents some desired configuration for a group of pins. + +Required subnode-properties: +- groups : An array of strings. Each string contains the name of a group. +- function: A string containing the name of the function to mux to the + group. + + Valid values for group and function names can be found from looking at the + group and function arrays in driver files: + drivers/pinctrl/pinctrl-sirf.c + +For example, pinctrl might have subnodes like the following: + sd0_pmx: sd0@0 { + sd0 { + groups = "sd0_grp"; + function = "sd0"; + }; + }; + + sd1_pmx0: sd1@0 { + sd1 { + groups = "sd1_grp0"; + function = "sd1_m0"; + }; + }; + + sd1_pmx1: sd1@1 { + sd1 { + groups = "sd1_grp1"; + function = "sd1_m1"; + }; + }; + +For a specific board, if it wants to use sd1, +it can add the following to its board-specific .dts file. +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx0>; +} + +or + +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx1>; +} diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 542a12a17991..100d9ac2ae1f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -132,6 +132,8 @@ config PINCTRL_SIRF bool "CSR SiRFprimaII pin controller driver" depends on ARCH_SIRF select PINMUX + select PINCONF + select GENERIC_PINCONF select GPIOLIB_IRQCHIP config PINCTRL_PISTACHIO diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile index 3ffc475ce40c..fd58e0bacb2a 100644 --- a/drivers/pinctrl/sirf/Makefile +++ b/drivers/pinctrl/sirf/Makefile @@ -3,3 +3,4 @@ obj-y += pinctrl-sirf.o obj-y += pinctrl-prima2.o obj-y += pinctrl-atlas6.o +obj-y += pinctrl-atlas7.o diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c new file mode 100644 index 000000000000..046251aaf156 --- /dev/null +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -0,0 +1,4639 @@ +/* + * pinctrl pads, groups, functions for CSR SiRFatlasVII + * + * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group + * company. + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Definition of Pad&Mux Properties */ +#define N 0 + +/* The Bank contains input-disable regisgers */ +#define BANK_DS 0 + +/* Clear Register offset */ +#define CLR_REG(r) ((r) + 0x04) + +/* Definition of multiple function select register */ +#define FUNC_CLEAR_MASK 0x7 +#define FUNC_GPIO 0 +#define FUNC_ANALOGUE 0x8 +#define ANA_CLEAR_MASK 0x1 + +/* The Atlas7's Pad Type List */ +enum altas7_pad_type { + PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */ + PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */ + PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */ + PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */ + PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */ + PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */ + PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */ + PAD_T_AD, /* PRDWUWHW08SCDG_HZ */ +}; + +/* Raw value of Driver-Strength Bits */ +#define DS3 BIT(3) +#define DS2 BIT(2) +#define DS1 BIT(1) +#define DS0 BIT(0) +#define DSZ 0 + +/* Drive-Strength Intermediate Values */ +#define DS_NULL -1 +#define DS_1BIT_IM_VAL DS0 +#define DS_1BIT_MASK 0x1 +#define DS_2BIT_IM_VAL (DS1 | DS0) +#define DS_2BIT_MASK 0x3 +#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0) +#define DS_4BIT_MASK 0xf + +/* The Drive-Strength of 4WE Pad DS1 0 CO */ +#define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */ +#define DS_4WE_2 (DS1) /* 1 0 2 */ +#define DS_4WE_1 (DS0) /* 0 1 1 */ +#define DS_4WE_0 (DSZ) /* 0 0 0 */ + +/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */ +#define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */ +#define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */ +#define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */ +#define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */ +#define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */ +#define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */ +#define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */ +#define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */ +#define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */ +#define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */ +#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */ +#define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */ +#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */ +#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */ +#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */ +#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */ + +/* The Drive-Strength of M31 Pad DS0 CO */ +#define DS_M31_0 (DSZ) /* 0 0 */ +#define DS_M31_1 (DS0) /* 1 1 */ + +/* Raw values of Pull Option Bits */ +#define PUN BIT(1) +#define PD BIT(0) +#define PE BIT(0) +#define PZ 0 + +/* Definition of Pull Types */ +#define PULL_UP 0 +#define HIGH_HYSTERESIS 1 +#define HIGH_Z 2 +#define PULL_DOWN 3 +#define PULL_DISABLE 4 +#define PULL_ENABLE 5 +#define PULL_UNKNOWN -1 + +/* Pull Options for 4WE Pad PUN PD CO */ +#define P4WE_PULL_MASK 0x3 +#define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define P4WE_HIGH_Z (PUN) /* 1 0 2 */ +#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */ +#define P4WE_PULL_UP (PZ) /* 0 0 0 */ + +/* Pull Options for 16ST Pad PUN PD CO */ +#define P16ST_PULL_MASK 0x3 +#define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define P16ST_HIGH_Z (PUN) /* 1 0 2 */ +#define P16ST_PULL_UP (PZ) /* 0 0 0 */ + +/* Pull Options for M31 Pad PE */ +#define PM31_PULL_MASK 0x1 +#define PM31_PULL_ENABLED (PE) /* 1 */ +#define PM31_PULL_DISABLED (PZ) /* 0 */ + +/* Pull Options for A/D Pad PUN PD CO */ +#define PANGD_PULL_MASK 0x3 +#define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */ +#define PANGD_HIGH_Z (PUN) /* 1 0 2 */ +#define PANGD_PULL_UP (PZ) /* 0 0 0 */ + +/* Definition of Input Disable */ +#define DI_MASK 0x1 +#define DI_DISABLE 0x1 +#define DI_ENABLE 0x0 + +/* Definition of Input Disable Value */ +#define DIV_MASK 0x1 +#define DIV_DISABLE 0x1 +#define DIV_ENABLE 0x0 + +struct dt_params { + const char *property; + int value; +}; + +/** + * struct atlas7_pad_conf - Atlas7 Pad Configuration + * @id The ID of this Pad. + * @type: The type of this Pad. + * @mux_reg: The mux register offset. + * This register contains the mux. + * @pupd_reg: The pull-up/down register offset. + * @drvstr_reg: The drive-strength register offset. + * @ad_ctrl_reg: The Analogue/Digital Control register. + * + * @mux_bit: The start bit of mux register. + * @pupd_bit: The start bit of pull-up/down register. + * @drvstr_bit: The start bit of drive-strength register. + * @ad_ctrl_bit: The start bit of analogue/digital register. + */ +struct atlas7_pad_config { + const u32 id; + u32 type; + u32 mux_reg; + u32 pupd_reg; + u32 drvstr_reg; + u32 ad_ctrl_reg; + /* bits in register */ + u8 mux_bit; + u8 pupd_bit; + u8 drvstr_bit; + u8 ad_ctrl_bit; +}; + +#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \ + { \ + .id = pad, \ + .type = t, \ + .mux_reg = mr, \ + .pupd_reg = pr, \ + .drvstr_reg = dsr, \ + .ad_ctrl_reg = adr, \ + .mux_bit = mb, \ + .pupd_bit = pb, \ + .drvstr_bit = dsb, \ + .ad_ctrl_bit = adb, \ + } + +/** + * struct atlas7_pad_mux - Atlas7 mux + * @bank: The bank of this pad's registers on. + * @pin : The ID of this Pad. + * @func: The mux func on this Pad. + * @dinput_reg: The Input-Disable register offset. + * @dinput_bit: The start bit of Input-Disable register. + * @dinput_val_reg: The Input-Disable-value register offset. + * This register is used to set the value of this pad + * if this pad was disabled. + * @dinput_val_bit: The start bit of Input-Disable Value register. + */ +struct atlas7_pad_mux { + u32 bank; + u32 pin; + u32 func; + u32 dinput_reg; + u32 dinput_bit; + u32 dinput_val_reg; + u32 dinput_val_bit; +}; + +#define MUX(b, pad, f, dr, db, dvr, dvb) \ + { \ + .bank = b, \ + .pin = pad, \ + .func = f, \ + .dinput_reg = dr, \ + .dinput_bit = db, \ + .dinput_val_reg = dvr, \ + .dinput_val_bit = dvb, \ + } + +struct atlas7_grp_mux { + unsigned int group; + unsigned int pad_mux_count; + const struct atlas7_pad_mux *pad_mux_list; +}; + + /** + * struct sirfsoc_pin_group - describes a SiRFprimaII pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + */ +struct atlas7_pin_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +#define GROUP(n, p) \ + { \ + .name = n, \ + .pins = p, \ + .num_pins = ARRAY_SIZE(p), \ + } + +struct atlas7_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; + const struct atlas7_grp_mux *grpmux; +}; + +#define FUNCTION(n, g, m) \ + { \ + .name = n, \ + .groups = g, \ + .num_groups = ARRAY_SIZE(g), \ + .grpmux = m, \ + } + +struct atlas7_pinctrl_data { + struct pinctrl_pin_desc *pads; + int pads_cnt; + struct atlas7_pin_group *grps; + int grps_cnt; + struct atlas7_pmx_func *funcs; + int funcs_cnt; + struct atlas7_pad_config *confs; + int confs_cnt; +}; + +/* Platform info of atlas7 pinctrl */ +#define ATLAS7_PINCTRL_REG_BANKS 2 +#define ATLAS7_PINCTRL_BANK_0_PINS 18 + +/** + * Atlas7 GPIO Chip + */ + +#define NGPIO_OF_BANK 32 +#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK) + +/* Registers of GPIO Controllers */ +#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b)) +#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i)) +#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C) + +/* Definition bits of GPIO Control Registers */ +#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0) +#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1) +#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2) +#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3) +#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4) +#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5) +#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6) +#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7) + +struct atlas7_gpio_bank { + struct pinctrl_dev *pctldev; + int id; + int irq; + void __iomem *base; + unsigned int gpio_offset; + unsigned int ngpio; + const unsigned int *gpio_pins; +}; + +struct atlas7_gpio_chip { + const char *name; + void __iomem *reg; + struct clk *clk; + int nbank; + spinlock_t lock; + struct gpio_chip chip; + struct atlas7_gpio_bank banks[0]; +}; + +static inline struct atlas7_gpio_chip *to_atlas7_gpio(struct gpio_chip *gc) +{ + return container_of(gc, struct atlas7_gpio_chip, chip); +} + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct atlas7_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + struct atlas7_pinctrl_data *pctl_data; + void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS]; +}; + +/* + * Pad list for the pinmux subsystem + * refer to A7DA IO Summary - CS-314158-DD-4E.xls + */ + +/*Pads in IOC RTC & TOP */ +static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { + /* RTC PADs */ + PINCTRL_PIN(0, "rtc_gpio_0"), + PINCTRL_PIN(1, "rtc_gpio_1"), + PINCTRL_PIN(2, "rtc_gpio_2"), + PINCTRL_PIN(3, "rtc_gpio_3"), + PINCTRL_PIN(4, "low_bat_ind_b"), + PINCTRL_PIN(5, "on_key_b"), + PINCTRL_PIN(6, "ext_on"), + PINCTRL_PIN(7, "mem_on"), + PINCTRL_PIN(8, "core_on"), + PINCTRL_PIN(9, "io_on"), + PINCTRL_PIN(10, "can0_tx"), + PINCTRL_PIN(11, "can0_rx"), + PINCTRL_PIN(12, "spi0_clk"), + PINCTRL_PIN(13, "spi0_cs_b"), + PINCTRL_PIN(14, "spi0_io_0"), + PINCTRL_PIN(15, "spi0_io_1"), + PINCTRL_PIN(16, "spi0_io_2"), + PINCTRL_PIN(17, "spi0_io_3"), + + /* TOP PADs */ + PINCTRL_PIN(18, "spi1_en"), + PINCTRL_PIN(19, "spi1_clk"), + PINCTRL_PIN(20, "spi1_din"), + PINCTRL_PIN(21, "spi1_dout"), + PINCTRL_PIN(22, "trg_spi_clk"), + PINCTRL_PIN(23, "trg_spi_di"), + PINCTRL_PIN(24, "trg_spi_do"), + PINCTRL_PIN(25, "trg_spi_cs_b"), + PINCTRL_PIN(26, "trg_acq_d1"), + PINCTRL_PIN(27, "trg_irq_b"), + PINCTRL_PIN(28, "trg_acq_d0"), + PINCTRL_PIN(29, "trg_acq_clk"), + PINCTRL_PIN(30, "trg_shutdown_b_out"), + PINCTRL_PIN(31, "sdio2_clk"), + PINCTRL_PIN(32, "sdio2_cmd"), + PINCTRL_PIN(33, "sdio2_dat_0"), + PINCTRL_PIN(34, "sdio2_dat_1"), + PINCTRL_PIN(35, "sdio2_dat_2"), + PINCTRL_PIN(36, "sdio2_dat_3"), + PINCTRL_PIN(37, "df_ad_7"), + PINCTRL_PIN(38, "df_ad_6"), + PINCTRL_PIN(39, "df_ad_5"), + PINCTRL_PIN(40, "df_ad_4"), + PINCTRL_PIN(41, "df_ad_3"), + PINCTRL_PIN(42, "df_ad_2"), + PINCTRL_PIN(43, "df_ad_1"), + PINCTRL_PIN(44, "df_ad_0"), + PINCTRL_PIN(45, "df_dqs"), + PINCTRL_PIN(46, "df_cle"), + PINCTRL_PIN(47, "df_ale"), + PINCTRL_PIN(48, "df_we_b"), + PINCTRL_PIN(49, "df_re_b"), + PINCTRL_PIN(50, "df_ry_by"), + PINCTRL_PIN(51, "df_cs_b_1"), + PINCTRL_PIN(52, "df_cs_b_0"), + PINCTRL_PIN(53, "l_pclk"), + PINCTRL_PIN(54, "l_lck"), + PINCTRL_PIN(55, "l_fck"), + PINCTRL_PIN(56, "l_de"), + PINCTRL_PIN(57, "ldd_0"), + PINCTRL_PIN(58, "ldd_1"), + PINCTRL_PIN(59, "ldd_2"), + PINCTRL_PIN(60, "ldd_3"), + PINCTRL_PIN(61, "ldd_4"), + PINCTRL_PIN(62, "ldd_5"), + PINCTRL_PIN(63, "ldd_6"), + PINCTRL_PIN(64, "ldd_7"), + PINCTRL_PIN(65, "ldd_8"), + PINCTRL_PIN(66, "ldd_9"), + PINCTRL_PIN(67, "ldd_10"), + PINCTRL_PIN(68, "ldd_11"), + PINCTRL_PIN(69, "ldd_12"), + PINCTRL_PIN(70, "ldd_13"), + PINCTRL_PIN(71, "ldd_14"), + PINCTRL_PIN(72, "ldd_15"), + PINCTRL_PIN(73, "lcd_gpio_20"), + PINCTRL_PIN(74, "vip_0"), + PINCTRL_PIN(75, "vip_1"), + PINCTRL_PIN(76, "vip_2"), + PINCTRL_PIN(77, "vip_3"), + PINCTRL_PIN(78, "vip_4"), + PINCTRL_PIN(79, "vip_5"), + PINCTRL_PIN(80, "vip_6"), + PINCTRL_PIN(81, "vip_7"), + PINCTRL_PIN(82, "vip_pxclk"), + PINCTRL_PIN(83, "vip_hsync"), + PINCTRL_PIN(84, "vip_vsync"), + PINCTRL_PIN(85, "sdio3_clk"), + PINCTRL_PIN(86, "sdio3_cmd"), + PINCTRL_PIN(87, "sdio3_dat_0"), + PINCTRL_PIN(88, "sdio3_dat_1"), + PINCTRL_PIN(89, "sdio3_dat_2"), + PINCTRL_PIN(90, "sdio3_dat_3"), + PINCTRL_PIN(91, "sdio5_clk"), + PINCTRL_PIN(92, "sdio5_cmd"), + PINCTRL_PIN(93, "sdio5_dat_0"), + PINCTRL_PIN(94, "sdio5_dat_1"), + PINCTRL_PIN(95, "sdio5_dat_2"), + PINCTRL_PIN(96, "sdio5_dat_3"), + PINCTRL_PIN(97, "rgmii_txd_0"), + PINCTRL_PIN(98, "rgmii_txd_1"), + PINCTRL_PIN(99, "rgmii_txd_2"), + PINCTRL_PIN(100, "rgmii_txd_3"), + PINCTRL_PIN(101, "rgmii_txclk"), + PINCTRL_PIN(102, "rgmii_tx_ctl"), + PINCTRL_PIN(103, "rgmii_rxd_0"), + PINCTRL_PIN(104, "rgmii_rxd_1"), + PINCTRL_PIN(105, "rgmii_rxd_2"), + PINCTRL_PIN(106, "rgmii_rxd_3"), + PINCTRL_PIN(107, "rgmii_rx_clk"), + PINCTRL_PIN(108, "rgmii_rxc_ctl"), + PINCTRL_PIN(109, "rgmii_mdio"), + PINCTRL_PIN(110, "rgmii_mdc"), + PINCTRL_PIN(111, "rgmii_intr_n"), + PINCTRL_PIN(112, "i2s_mclk"), + PINCTRL_PIN(113, "i2s_bclk"), + PINCTRL_PIN(114, "i2s_ws"), + PINCTRL_PIN(115, "i2s_dout0"), + PINCTRL_PIN(116, "i2s_dout1"), + PINCTRL_PIN(117, "i2s_dout2"), + PINCTRL_PIN(118, "i2s_din"), + PINCTRL_PIN(119, "gpio_0"), + PINCTRL_PIN(120, "gpio_1"), + PINCTRL_PIN(121, "gpio_2"), + PINCTRL_PIN(122, "gpio_3"), + PINCTRL_PIN(123, "gpio_4"), + PINCTRL_PIN(124, "gpio_5"), + PINCTRL_PIN(125, "gpio_6"), + PINCTRL_PIN(126, "gpio_7"), + PINCTRL_PIN(127, "sda_0"), + PINCTRL_PIN(128, "scl_0"), + PINCTRL_PIN(129, "coex_pio_0"), + PINCTRL_PIN(130, "coex_pio_1"), + PINCTRL_PIN(131, "coex_pio_2"), + PINCTRL_PIN(132, "coex_pio_3"), + PINCTRL_PIN(133, "uart0_tx"), + PINCTRL_PIN(134, "uart0_rx"), + PINCTRL_PIN(135, "uart1_tx"), + PINCTRL_PIN(136, "uart1_rx"), + PINCTRL_PIN(137, "uart3_tx"), + PINCTRL_PIN(138, "uart3_rx"), + PINCTRL_PIN(139, "uart4_tx"), + PINCTRL_PIN(140, "uart4_rx"), + PINCTRL_PIN(141, "usp0_clk"), + PINCTRL_PIN(142, "usp0_tx"), + PINCTRL_PIN(143, "usp0_rx"), + PINCTRL_PIN(144, "usp0_fs"), + PINCTRL_PIN(145, "usp1_clk"), + PINCTRL_PIN(146, "usp1_tx"), + PINCTRL_PIN(147, "usp1_rx"), + PINCTRL_PIN(148, "usp1_fs"), + PINCTRL_PIN(149, "lvds_tx0d4p"), + PINCTRL_PIN(150, "lvds_tx0d4n"), + PINCTRL_PIN(151, "lvds_tx0d3p"), + PINCTRL_PIN(152, "lvds_tx0d3n"), + PINCTRL_PIN(153, "lvds_tx0d2p"), + PINCTRL_PIN(154, "lvds_tx0d2n"), + PINCTRL_PIN(155, "lvds_tx0d1p"), + PINCTRL_PIN(156, "lvds_tx0d1n"), + PINCTRL_PIN(157, "lvds_tx0d0p"), + PINCTRL_PIN(158, "lvds_tx0d0n"), +}; + +struct atlas7_pad_config atlas7_ioc_pad_confs[] = { + /* The Configuration of IOC_RTC Pads */ + PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0), + PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0), + PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0), + PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0), + PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0), + PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0), + PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0), + PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0), + PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0), + PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0), + PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0), + PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0), + PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0), + PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0), + PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0), + PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0), + PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0), + PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0), + /* The Configuration of IOC_TOP Pads */ + PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0), + PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0), + PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0), + PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0), + PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0), + PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0), + PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0), + PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0), + PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0), + PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0), + PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0), + PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0), + PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0), + PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0), + PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0), + PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0), + PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0), + PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0), + PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0), + PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0), + PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0), + PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0), + PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0), + PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0), + PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0), + PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0), + PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0), + PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0), + PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0), + PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0), + PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0), + PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0), + PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0), + PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0), + PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0), + PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0), + PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0), + PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0), + PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0), + PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0), + PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0), + PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0), + PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0), + PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0), + PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0), + PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0), + PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0), + PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0), + PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0), + PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0), + PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0), + PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0), + PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0), + PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0), + PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0), + PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0), + PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0), + PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0), + PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0), + PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0), + PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0), + PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0), + PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0), + PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0), + PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0), + PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0), + PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0), + PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0), + PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0), + PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0), + PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0), + PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0), + PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0), + PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0), + PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0), + PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0), + PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0), + PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0), + PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0), + PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0), + PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0), + PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0), + PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0), + PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0), + PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0), + PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0), + PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0), + PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0), + PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0), + PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0), + PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0), + PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0), + PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0), + PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0), + PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0), + PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0), + PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0), + PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0), + PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0), + PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0), + PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0), + PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0), + PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0), + PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0), + PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0), + PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0), + PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0), + PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0), + PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0), + PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0), + PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0), + PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0), + PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0), + PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0), + PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0), + PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0), + PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0), + PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0), + PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0), + PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0), + PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0), + PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0), + PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0), + PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0), + PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0), + PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0), + PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0), + PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0), + PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0), + PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0), + PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0), + PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0), + PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1), + PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2), + PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3), + PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4), + PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5), + PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6), + PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), + PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), + PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), +}; + +/* pin list of each pin group */ +static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124, + 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, }; +static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, }; +static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36, + 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94, + 95, 96, 112, 113, 114, 115, 116, 117, 118, }; +static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102, + 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21, + 141, 142, 143, 144, 145, 146, 147, 148, }; +static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, + 151, 152, 149, 150, }; +static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39, + 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136, + 137, 138, 139, 140, }; +static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, + 14, 15, 16, 17, }; +static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; +static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, + 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, + 115, 49, 50, 142, 143, 80, }; +static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113, + 114, }; +static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; +static const unsigned int audio_i2s_extclk_pins[] = { 112, }; +static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, }; +static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, }; +static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, }; +static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, }; +static const unsigned int c_can_trnsvr_pins[] = { 1, }; +static const unsigned int c0_can_pins0[] = { 11, 10, }; +static const unsigned int c0_can_pins1[] = { 2, 3, }; +static const unsigned int c1_can_pins0[] = { 138, 137, }; +static const unsigned int c1_can_pins1[] = { 147, 146, }; +static const unsigned int c1_can_pins2[] = { 2, 3, }; +static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, }; +static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, }; +static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, }; +static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, }; +static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47, + 49, 50, 54, 55, 56, }; +static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, }; +static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, }; +static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75, + 76, 77, }; +static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, }; +static const unsigned int clkc_pins0[] = { 30, 47, }; +static const unsigned int clkc_pins1[] = { 78, 54, }; +static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, }; +static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, }; +static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, }; +static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, }; +static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, }; +static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78, + 79, 80, 81, 83, 84, 73, 55, 56, }; +static const unsigned int cvbs_dbg_test_pins0[] = { 57, }; +static const unsigned int cvbs_dbg_test_pins1[] = { 58, }; +static const unsigned int cvbs_dbg_test_pins2[] = { 59, }; +static const unsigned int cvbs_dbg_test_pins3[] = { 60, }; +static const unsigned int cvbs_dbg_test_pins4[] = { 61, }; +static const unsigned int cvbs_dbg_test_pins5[] = { 62, }; +static const unsigned int cvbs_dbg_test_pins6[] = { 63, }; +static const unsigned int cvbs_dbg_test_pins7[] = { 64, }; +static const unsigned int cvbs_dbg_test_pins8[] = { 65, }; +static const unsigned int cvbs_dbg_test_pins9[] = { 66, }; +static const unsigned int cvbs_dbg_test_pins10[] = { 67, }; +static const unsigned int cvbs_dbg_test_pins11[] = { 68, }; +static const unsigned int cvbs_dbg_test_pins12[] = { 69, }; +static const unsigned int cvbs_dbg_test_pins13[] = { 70, }; +static const unsigned int cvbs_dbg_test_pins14[] = { 71, }; +static const unsigned int cvbs_dbg_test_pins15[] = { 72, }; +static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125, + 120, }; +static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, }; +static const unsigned int gn_gnss_eclk_pins[] = { 113, }; +static const unsigned int gn_gnss_irq1_pins0[] = { 112, }; +static const unsigned int gn_gnss_irq2_pins0[] = { 118, }; +static const unsigned int gn_gnss_tm_pins[] = { 115, }; +static const unsigned int gn_gnss_tsync_pins[] = { 114, }; +static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40, + 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, }; +static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, }; +static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, }; +static const unsigned int gn_trg_shutdown_pins0[] = { 30, }; +static const unsigned int gn_trg_shutdown_pins1[] = { 83, }; +static const unsigned int gn_trg_shutdown_pins2[] = { 117, }; +static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; +static const unsigned int i2c0_pins[] = { 128, 127, }; +static const unsigned int i2c1_pins[] = { 126, 125, }; +static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, }; +static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; +static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, + 81, 56, 53, }; +static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, }; +static const unsigned int ld_ldd_fck_pins[] = { 55, }; +static const unsigned int ld_ldd_lck_pins[] = { 54, }; +static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, }; +static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154, + 155, 156, 157, 158, }; +static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, + 47, 46, 52, 51, 45, 49, 50, 48, 124, }; +static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, + 37, 47, 46, 52, 51, 45, 49, 50, 48, }; +static const unsigned int ps_pins[] = { 120, 119, }; +static const unsigned int pwc_core_on_pins[] = { 8, }; +static const unsigned int pwc_ext_on_pins[] = { 6, }; +static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; +static const unsigned int pwc_io_on_pins[] = { 9, }; +static const unsigned int pwc_lowbatt_b_pins0[] = { 4, }; +static const unsigned int pwc_mem_on_pins[] = { 7, }; +static const unsigned int pwc_on_key_b_pins0[] = { 5, }; +static const unsigned int pwc_wakeup_src0_pins[] = { 0, }; +static const unsigned int pwc_wakeup_src1_pins[] = { 1, }; +static const unsigned int pwc_wakeup_src2_pins[] = { 2, }; +static const unsigned int pwc_wakeup_src3_pins[] = { 3, }; +static const unsigned int pw_cko0_pins0[] = { 123, }; +static const unsigned int pw_cko0_pins1[] = { 101, }; +static const unsigned int pw_cko0_pins2[] = { 82, }; +static const unsigned int pw_cko1_pins0[] = { 124, }; +static const unsigned int pw_cko1_pins1[] = { 110, }; +static const unsigned int pw_i2s01_clk_pins0[] = { 125, }; +static const unsigned int pw_i2s01_clk_pins1[] = { 117, }; +static const unsigned int pw_pwm0_pins[] = { 119, }; +static const unsigned int pw_pwm1_pins[] = { 120, }; +static const unsigned int pw_pwm2_pins0[] = { 121, }; +static const unsigned int pw_pwm2_pins1[] = { 98, }; +static const unsigned int pw_pwm3_pins0[] = { 122, }; +static const unsigned int pw_pwm3_pins1[] = { 73, }; +static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, }; +static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, }; +static const unsigned int pw_backlight_pins0[] = { 122, }; +static const unsigned int pw_backlight_pins1[] = { 73, }; +static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107, + 102, 97, 98, 99, 100, 101, }; +static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, }; +static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, }; +static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, }; +static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, }; +static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38, + 37, }; +static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, }; +static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38, + 37, }; +static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, }; +static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, }; +static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, }; +static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, }; +static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, }; +static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; +static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; +static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, }; +static const unsigned int sp0_ext_ldo_on_pins[] = { 4, }; +static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, }; +static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, }; +static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, }; +static const unsigned int uart0_pins[] = { 121, 120, 134, 133, }; +static const unsigned int uart0_nopause_pins[] = { 134, 133, }; +static const unsigned int uart1_pins[] = { 136, 135, }; +static const unsigned int uart2_pins[] = { 11, 10, }; +static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, }; +static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, }; +static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, }; +static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, }; +static const unsigned int uart3_nopause_pins0[] = { 138, 137, }; +static const unsigned int uart3_nopause_pins1[] = { 84, 83, }; +static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, }; +static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, }; +static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, }; +static const unsigned int uart4_nopause_pins[] = { 140, 139, }; +static const unsigned int usb0_drvvbus_pins[] = { 51, }; +static const unsigned int usb1_drvvbus_pins[] = { 134, }; +static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86, + 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, }; +static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81, + 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, }; +static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98, + 99, 100, }; +static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79, + 80, 81, }; +static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103, + 104, 105, 106, }; + +/* definition of pin group table */ +struct atlas7_pin_group altas7_pin_groups[] = { + GROUP("gnss_gpio_grp", gnss_gpio_pins), + GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins), + GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), + GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins), + GROUP("lvds_gpio_grp", lvds_gpio_pins), + GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins), + GROUP("rtc_gpio_grp", rtc_gpio_pins), + GROUP("audio_ac97_grp", audio_ac97_pins), + GROUP("audio_func_dbg_grp", audio_func_dbg_pins), + GROUP("audio_i2s_grp", audio_i2s_pins), + GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins), + GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins), + GROUP("audio_uart0_grp", audio_uart0_pins), + GROUP("audio_uart1_grp", audio_uart1_pins), + GROUP("audio_uart2_grp0", audio_uart2_pins0), + GROUP("audio_uart2_grp1", audio_uart2_pins1), + GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins), + GROUP("c0_can_grp0", c0_can_pins0), + GROUP("c0_can_grp1", c0_can_pins1), + GROUP("c1_can_grp0", c1_can_pins0), + GROUP("c1_can_grp1", c1_can_pins1), + GROUP("c1_can_grp2", c1_can_pins2), + GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins), + GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins), + GROUP("ca_coex_grp", ca_coex_pins), + GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins), + GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins), + GROUP("ca_pio_grp", ca_pio_pins), + GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins), + GROUP("ca_spi_grp", ca_spi_pins), + GROUP("ca_trb_grp", ca_trb_pins), + GROUP("ca_uart_debug_grp", ca_uart_debug_pins), + GROUP("clkc_grp0", clkc_pins0), + GROUP("clkc_grp1", clkc_pins1), + GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins), + GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins), + GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins), + GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0), + GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1), + GROUP("cvbs_dbg_grp", cvbs_dbg_pins), + GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0), + GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1), + GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2), + GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3), + GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4), + GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5), + GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6), + GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7), + GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8), + GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9), + GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10), + GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11), + GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12), + GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13), + GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14), + GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15), + GROUP("gn_gnss_power_grp", gn_gnss_power_pins), + GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins), + GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins), + GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0), + GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0), + GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins), + GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins), + GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins), + GROUP("gn_trg_grp0", gn_trg_pins0), + GROUP("gn_trg_grp1", gn_trg_pins1), + GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0), + GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1), + GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2), + GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3), + GROUP("i2c0_grp", i2c0_pins), + GROUP("i2c1_grp", i2c1_pins), + GROUP("jtag_grp0", jtag_pins0), + GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0), + GROUP("ld_ldd_grp", ld_ldd_pins), + GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins), + GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins), + GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins), + GROUP("lr_lcdrom_grp", lr_lcdrom_pins), + GROUP("lvds_analog_grp", lvds_analog_pins), + GROUP("nd_df_grp", nd_df_pins), + GROUP("nd_df_nowp_grp", nd_df_nowp_pins), + GROUP("ps_grp", ps_pins), + GROUP("pwc_core_on_grp", pwc_core_on_pins), + GROUP("pwc_ext_on_grp", pwc_ext_on_pins), + GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins), + GROUP("pwc_io_on_grp", pwc_io_on_pins), + GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0), + GROUP("pwc_mem_on_grp", pwc_mem_on_pins), + GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0), + GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins), + GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins), + GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins), + GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins), + GROUP("pw_cko0_grp0", pw_cko0_pins0), + GROUP("pw_cko0_grp1", pw_cko0_pins1), + GROUP("pw_cko0_grp2", pw_cko0_pins2), + GROUP("pw_cko1_grp0", pw_cko1_pins0), + GROUP("pw_cko1_grp1", pw_cko1_pins1), + GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0), + GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1), + GROUP("pw_pwm0_grp", pw_pwm0_pins), + GROUP("pw_pwm1_grp", pw_pwm1_pins), + GROUP("pw_pwm2_grp0", pw_pwm2_pins0), + GROUP("pw_pwm2_grp1", pw_pwm2_pins1), + GROUP("pw_pwm3_grp0", pw_pwm3_pins0), + GROUP("pw_pwm3_grp1", pw_pwm3_pins1), + GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0), + GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1), + GROUP("pw_backlight_grp0", pw_backlight_pins0), + GROUP("pw_backlight_grp1", pw_backlight_pins1), + GROUP("rg_eth_mac_grp", rg_eth_mac_pins), + GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins), + GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins), + GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0), + GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1), + GROUP("sd0_grp", sd0_pins), + GROUP("sd0_4bit_grp", sd0_4bit_pins), + GROUP("sd1_grp", sd1_pins), + GROUP("sd1_4bit_grp0", sd1_4bit_pins0), + GROUP("sd1_4bit_grp1", sd1_4bit_pins1), + GROUP("sd2_grp0", sd2_pins0), + GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0), + GROUP("sd3_grp", sd3_pins), + GROUP("sd5_grp", sd5_pins), + GROUP("sd6_grp0", sd6_pins0), + GROUP("sd6_grp1", sd6_pins1), + GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins), + GROUP("sp0_qspi_grp", sp0_qspi_pins), + GROUP("sp1_spi_grp", sp1_spi_pins), + GROUP("tpiu_trace_grp", tpiu_trace_pins), + GROUP("uart0_grp", uart0_pins), + GROUP("uart0_nopause_grp", uart0_nopause_pins), + GROUP("uart1_grp", uart1_pins), + GROUP("uart2_grp", uart2_pins), + GROUP("uart3_grp0", uart3_pins0), + GROUP("uart3_grp1", uart3_pins1), + GROUP("uart3_grp2", uart3_pins2), + GROUP("uart3_grp3", uart3_pins3), + GROUP("uart3_nopause_grp0", uart3_nopause_pins0), + GROUP("uart3_nopause_grp1", uart3_nopause_pins1), + GROUP("uart4_grp0", uart4_pins0), + GROUP("uart4_grp1", uart4_pins1), + GROUP("uart4_grp2", uart4_pins2), + GROUP("uart4_nopause_grp", uart4_nopause_pins), + GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins), + GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins), + GROUP("visbus_dout_grp", visbus_dout_pins), + GROUP("vi_vip1_grp", vi_vip1_pins), + GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins), + GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins), + GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins), +}; + +/* How many groups that a function can use */ +static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", }; +static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", }; +static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", }; +static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", }; +static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", }; +static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", }; +static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", }; +static const char * const audio_ac97_grp[] = { "audio_ac97_grp", }; +static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", }; +static const char * const audio_i2s_grp[] = { "audio_i2s_grp", }; +static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", }; +static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", }; +static const char * const audio_uart0_grp[] = { "audio_uart0_grp", }; +static const char * const audio_uart1_grp[] = { "audio_uart1_grp", }; +static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", }; +static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", }; +static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", }; +static const char * const c0_can_grp0[] = { "c0_can_grp0", }; +static const char * const c0_can_grp1[] = { "c0_can_grp1", }; +static const char * const c1_can_grp0[] = { "c1_can_grp0", }; +static const char * const c1_can_grp1[] = { "c1_can_grp1", }; +static const char * const c1_can_grp2[] = { "c1_can_grp2", }; +static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", }; +static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", }; +static const char * const ca_coex_grp[] = { "ca_coex_grp", }; +static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", }; +static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", }; +static const char * const ca_pio_grp[] = { "ca_pio_grp", }; +static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", }; +static const char * const ca_spi_grp[] = { "ca_spi_grp", }; +static const char * const ca_trb_grp[] = { "ca_trb_grp", }; +static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", }; +static const char * const clkc_grp0[] = { "clkc_grp0", }; +static const char * const clkc_grp1[] = { "clkc_grp1", }; +static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", }; +static const char * const gn_gnss_uart_nopause_grp[] = { + "gn_gnss_uart_nopause_grp", }; +static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", }; +static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", }; +static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", }; +static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", }; +static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", }; +static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", }; +static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", }; +static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", }; +static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", }; +static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", }; +static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", }; +static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", }; +static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", }; +static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", }; +static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", }; +static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", }; +static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", }; +static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", }; +static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", }; +static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", }; +static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", }; +static const char * const gn_gnss_sw_status_grp[] = { + "gn_gnss_sw_status_grp", }; +static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", }; +static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", }; +static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", }; +static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", }; +static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", }; +static const char * const gn_io_gnsssys_sw_cfg_grp[] = { + "gn_io_gnsssys_sw_cfg_grp", }; +static const char * const gn_trg_grp0[] = { "gn_trg_grp0", }; +static const char * const gn_trg_grp1[] = { "gn_trg_grp1", }; +static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", }; +static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", }; +static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", }; +static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", }; +static const char * const i2c0_grp[] = { "i2c0_grp", }; +static const char * const i2c1_grp[] = { "i2c1_grp", }; +static const char * const jtag_grp0[] = { "jtag_grp0", }; +static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", }; +static const char * const ld_ldd_grp[] = { "ld_ldd_grp", }; +static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", }; +static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", }; +static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", }; +static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", }; +static const char * const lvds_analog_grp[] = { "lvds_analog_grp", }; +static const char * const nd_df_grp[] = { "nd_df_grp", }; +static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", }; +static const char * const ps_grp[] = { "ps_grp", }; +static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", }; +static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", }; +static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", }; +static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", }; +static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", }; +static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", }; +static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", }; +static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", }; +static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", }; +static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", }; +static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", }; +static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", }; +static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", }; +static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", }; +static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", }; +static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", }; +static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", }; +static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", }; +static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", }; +static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", }; +static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", }; +static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", }; +static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", }; +static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", }; +static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", }; +static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", }; +static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", }; +static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", }; +static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", }; +static const char * const rg_gmac_phy_intr_n_grp[] = { + "rg_gmac_phy_intr_n_grp", }; +static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", }; +static const char * const rg_rgmii_phy_ref_clk_grp0[] = { + "rg_rgmii_phy_ref_clk_grp0", }; +static const char * const rg_rgmii_phy_ref_clk_grp1[] = { + "rg_rgmii_phy_ref_clk_grp1", }; +static const char * const sd0_grp[] = { "sd0_grp", }; +static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", }; +static const char * const sd1_grp[] = { "sd1_grp", }; +static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", }; +static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", }; +static const char * const sd2_grp0[] = { "sd2_grp0", }; +static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", }; +static const char * const sd3_grp[] = { "sd3_grp", }; +static const char * const sd5_grp[] = { "sd5_grp", }; +static const char * const sd6_grp0[] = { "sd6_grp0", }; +static const char * const sd6_grp1[] = { "sd6_grp1", }; +static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", }; +static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", }; +static const char * const sp1_spi_grp[] = { "sp1_spi_grp", }; +static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", }; +static const char * const uart0_grp[] = { "uart0_grp", }; +static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", }; +static const char * const uart1_grp[] = { "uart1_grp", }; +static const char * const uart2_grp[] = { "uart2_grp", }; +static const char * const uart3_grp0[] = { "uart3_grp0", }; +static const char * const uart3_grp1[] = { "uart3_grp1", }; +static const char * const uart3_grp2[] = { "uart3_grp2", }; +static const char * const uart3_grp3[] = { "uart3_grp3", }; +static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", }; +static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", }; +static const char * const uart4_grp0[] = { "uart4_grp0", }; +static const char * const uart4_grp1[] = { "uart4_grp1", }; +static const char * const uart4_grp2[] = { "uart4_grp2", }; +static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", }; +static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", }; +static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", }; +static const char * const visbus_dout_grp[] = { "visbus_dout_grp", }; +static const char * const vi_vip1_grp[] = { "vi_vip1_grp", }; +static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", }; +static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", }; +static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", }; + +static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = { + MUX(1, 119, 0, N, N, N, N), + MUX(1, 120, 0, N, N, N, N), + MUX(1, 121, 0, N, N, N, N), + MUX(1, 122, 0, N, N, N, N), + MUX(1, 123, 0, N, N, N, N), + MUX(1, 124, 0, N, N, N, N), + MUX(1, 125, 0, N, N, N, N), + MUX(1, 126, 0, N, N, N, N), + MUX(1, 127, 0, N, N, N, N), + MUX(1, 128, 0, N, N, N, N), + MUX(1, 22, 0, N, N, N, N), + MUX(1, 23, 0, N, N, N, N), + MUX(1, 24, 0, N, N, N, N), + MUX(1, 25, 0, N, N, N, N), + MUX(1, 26, 0, N, N, N, N), + MUX(1, 27, 0, N, N, N, N), + MUX(1, 28, 0, N, N, N, N), + MUX(1, 29, 0, N, N, N, N), + MUX(1, 30, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux gnss_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux), + .pad_mux_list = gnss_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = { + MUX(1, 74, 0, N, N, N, N), + MUX(1, 75, 0, N, N, N, N), + MUX(1, 76, 0, N, N, N, N), + MUX(1, 77, 0, N, N, N, N), + MUX(1, 78, 0, N, N, N, N), + MUX(1, 79, 0, N, N, N, N), + MUX(1, 80, 0, N, N, N, N), + MUX(1, 81, 0, N, N, N, N), + MUX(1, 82, 0, N, N, N, N), + MUX(1, 83, 0, N, N, N, N), + MUX(1, 84, 0, N, N, N, N), + MUX(1, 53, 0, N, N, N, N), + MUX(1, 54, 0, N, N, N, N), + MUX(1, 55, 0, N, N, N, N), + MUX(1, 56, 0, N, N, N, N), + MUX(1, 57, 0, N, N, N, N), + MUX(1, 58, 0, N, N, N, N), + MUX(1, 59, 0, N, N, N, N), + MUX(1, 60, 0, N, N, N, N), + MUX(1, 61, 0, N, N, N, N), + MUX(1, 62, 0, N, N, N, N), + MUX(1, 63, 0, N, N, N, N), + MUX(1, 64, 0, N, N, N, N), + MUX(1, 65, 0, N, N, N, N), + MUX(1, 66, 0, N, N, N, N), + MUX(1, 67, 0, N, N, N, N), + MUX(1, 68, 0, N, N, N, N), + MUX(1, 69, 0, N, N, N, N), + MUX(1, 70, 0, N, N, N, N), + MUX(1, 71, 0, N, N, N, N), + MUX(1, 72, 0, N, N, N, N), + MUX(1, 73, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux), + .pad_mux_list = lcd_vip_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = { + MUX(1, 31, 0, N, N, N, N), + MUX(1, 32, 0, N, N, N, N), + MUX(1, 33, 0, N, N, N, N), + MUX(1, 34, 0, N, N, N, N), + MUX(1, 35, 0, N, N, N, N), + MUX(1, 36, 0, N, N, N, N), + MUX(1, 85, 0, N, N, N, N), + MUX(1, 86, 0, N, N, N, N), + MUX(1, 87, 0, N, N, N, N), + MUX(1, 88, 0, N, N, N, N), + MUX(1, 89, 0, N, N, N, N), + MUX(1, 90, 0, N, N, N, N), + MUX(1, 129, 0, N, N, N, N), + MUX(1, 130, 0, N, N, N, N), + MUX(1, 131, 0, N, N, N, N), + MUX(1, 132, 0, N, N, N, N), + MUX(1, 91, 0, N, N, N, N), + MUX(1, 92, 0, N, N, N, N), + MUX(1, 93, 0, N, N, N, N), + MUX(1, 94, 0, N, N, N, N), + MUX(1, 95, 0, N, N, N, N), + MUX(1, 96, 0, N, N, N, N), + MUX(1, 112, 0, N, N, N, N), + MUX(1, 113, 0, N, N, N, N), + MUX(1, 114, 0, N, N, N, N), + MUX(1, 115, 0, N, N, N, N), + MUX(1, 116, 0, N, N, N, N), + MUX(1, 117, 0, N, N, N, N), + MUX(1, 118, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux), + .pad_mux_list = sdio_i2s_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = { + MUX(1, 97, 0, N, N, N, N), + MUX(1, 98, 0, N, N, N, N), + MUX(1, 99, 0, N, N, N, N), + MUX(1, 100, 0, N, N, N, N), + MUX(1, 101, 0, N, N, N, N), + MUX(1, 102, 0, N, N, N, N), + MUX(1, 103, 0, N, N, N, N), + MUX(1, 104, 0, N, N, N, N), + MUX(1, 105, 0, N, N, N, N), + MUX(1, 106, 0, N, N, N, N), + MUX(1, 107, 0, N, N, N, N), + MUX(1, 108, 0, N, N, N, N), + MUX(1, 109, 0, N, N, N, N), + MUX(1, 110, 0, N, N, N, N), + MUX(1, 111, 0, N, N, N, N), + MUX(1, 18, 0, N, N, N, N), + MUX(1, 19, 0, N, N, N, N), + MUX(1, 20, 0, N, N, N, N), + MUX(1, 21, 0, N, N, N, N), + MUX(1, 141, 0, N, N, N, N), + MUX(1, 142, 0, N, N, N, N), + MUX(1, 143, 0, N, N, N, N), + MUX(1, 144, 0, N, N, N, N), + MUX(1, 145, 0, N, N, N, N), + MUX(1, 146, 0, N, N, N, N), + MUX(1, 147, 0, N, N, N, N), + MUX(1, 148, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux), + .pad_mux_list = sp_rgmii_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = { + MUX(1, 157, 0, N, N, N, N), + MUX(1, 158, 0, N, N, N, N), + MUX(1, 155, 0, N, N, N, N), + MUX(1, 156, 0, N, N, N, N), + MUX(1, 153, 0, N, N, N, N), + MUX(1, 154, 0, N, N, N, N), + MUX(1, 151, 0, N, N, N, N), + MUX(1, 152, 0, N, N, N, N), + MUX(1, 149, 0, N, N, N, N), + MUX(1, 150, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux lvds_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux), + .pad_mux_list = lvds_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { + MUX(1, 44, 0, N, N, N, N), + MUX(1, 43, 0, N, N, N, N), + MUX(1, 42, 0, N, N, N, N), + MUX(1, 41, 0, N, N, N, N), + MUX(1, 40, 0, N, N, N, N), + MUX(1, 39, 0, N, N, N, N), + MUX(1, 38, 0, N, N, N, N), + MUX(1, 37, 0, N, N, N, N), + MUX(1, 46, 0, N, N, N, N), + MUX(1, 47, 0, N, N, N, N), + MUX(1, 48, 0, N, N, N, N), + MUX(1, 49, 0, N, N, N, N), + MUX(1, 50, 0, N, N, N, N), + MUX(1, 52, 0, N, N, N, N), + MUX(1, 51, 0, N, N, N, N), + MUX(1, 45, 0, N, N, N, N), + MUX(1, 133, 0, N, N, N, N), + MUX(1, 134, 0, N, N, N, N), + MUX(1, 135, 0, N, N, N, N), + MUX(1, 136, 0, N, N, N, N), + MUX(1, 137, 0, N, N, N, N), + MUX(1, 138, 0, N, N, N, N), + MUX(1, 139, 0, N, N, N, N), + MUX(1, 140, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux uart_nand_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux), + .pad_mux_list = uart_nand_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { + MUX(0, 0, 0, N, N, N, N), + MUX(0, 1, 0, N, N, N, N), + MUX(0, 2, 0, N, N, N, N), + MUX(0, 3, 0, N, N, N, N), + MUX(0, 4, 0, N, N, N, N), + MUX(0, 10, 0, N, N, N, N), + MUX(0, 11, 0, N, N, N, N), + MUX(0, 12, 0, N, N, N, N), + MUX(0, 13, 0, N, N, N, N), + MUX(0, 14, 0, N, N, N, N), + MUX(0, 15, 0, N, N, N, N), + MUX(0, 16, 0, N, N, N, N), + MUX(0, 17, 0, N, N, N, N), +}; + +static struct atlas7_grp_mux rtc_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux), + .pad_mux_list = rtc_gpio_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = { + MUX(1, 113, 2, N, N, N, N), + MUX(1, 118, 2, N, N, N, N), + MUX(1, 115, 2, N, N, N, N), + MUX(1, 114, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_ac97_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux), + .pad_mux_list = audio_ac97_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = { + MUX(1, 141, 4, N, N, N, N), + MUX(1, 144, 4, N, N, N, N), + MUX(1, 44, 6, N, N, N, N), + MUX(1, 43, 6, N, N, N, N), + MUX(1, 42, 6, N, N, N, N), + MUX(1, 41, 6, N, N, N, N), + MUX(1, 40, 6, N, N, N, N), + MUX(1, 39, 6, N, N, N, N), + MUX(1, 38, 6, N, N, N, N), + MUX(1, 37, 6, N, N, N, N), + MUX(1, 74, 6, N, N, N, N), + MUX(1, 75, 6, N, N, N, N), + MUX(1, 76, 6, N, N, N, N), + MUX(1, 77, 6, N, N, N, N), + MUX(1, 78, 6, N, N, N, N), + MUX(1, 79, 6, N, N, N, N), + MUX(1, 81, 6, N, N, N, N), + MUX(1, 113, 6, N, N, N, N), + MUX(1, 114, 6, N, N, N, N), + MUX(1, 118, 6, N, N, N, N), + MUX(1, 115, 6, N, N, N, N), + MUX(1, 49, 6, N, N, N, N), + MUX(1, 50, 6, N, N, N, N), + MUX(1, 142, 4, N, N, N, N), + MUX(1, 143, 4, N, N, N, N), + MUX(1, 80, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_func_dbg_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux), + .pad_mux_list = audio_func_dbg_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = { + MUX(1, 118, 1, N, N, N, N), + MUX(1, 115, 1, N, N, N, N), + MUX(1, 116, 1, N, N, N, N), + MUX(1, 117, 1, N, N, N, N), + MUX(1, 112, 1, N, N, N, N), + MUX(1, 113, 1, N, N, N, N), + MUX(1, 114, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_i2s_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux), + .pad_mux_list = audio_i2s_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = { + MUX(1, 118, 1, N, N, N, N), + MUX(1, 115, 1, N, N, N, N), + MUX(1, 112, 1, N, N, N, N), + MUX(1, 113, 1, N, N, N, N), + MUX(1, 114, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux), + .pad_mux_list = audio_i2s_2ch_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = { + MUX(1, 112, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux), + .pad_mux_list = audio_i2s_extclk_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = { + MUX(1, 143, 1, N, N, N, N), + MUX(1, 142, 1, N, N, N, N), + MUX(1, 141, 1, N, N, N, N), + MUX(1, 144, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_uart0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux), + .pad_mux_list = audio_uart0_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = { + MUX(1, 147, 1, N, N, N, N), + MUX(1, 146, 1, N, N, N, N), + MUX(1, 145, 1, N, N, N, N), + MUX(1, 148, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_uart1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux), + .pad_mux_list = audio_uart1_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = { + MUX(1, 20, 2, 0xa00, 24, 0xa80, 24), + MUX(1, 21, 2, 0xa00, 25, 0xa80, 25), + MUX(1, 19, 2, 0xa00, 23, 0xa80, 23), + MUX(1, 18, 2, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux), + .pad_mux_list = audio_uart2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = { + MUX(1, 109, 2, 0xa00, 24, 0xa80, 24), + MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), + MUX(1, 101, 2, 0xa00, 23, 0xa80, 23), + MUX(1, 111, 2, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux), + .pad_mux_list = audio_uart2_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = { + MUX(0, 1, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c_can_trnsvr_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux), + .pad_mux_list = c_can_trnsvr_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = { + MUX(0, 11, 1, 0xa08, 9, 0xa88, 9), + MUX(0, 10, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux c0_can_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux), + .pad_mux_list = c0_can_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = { + MUX(0, 2, 5, 0xa08, 9, 0xa88, 9), + MUX(0, 3, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux c0_can_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux), + .pad_mux_list = c0_can_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = { + MUX(1, 138, 2, 0xa00, 4, 0xa80, 4), + MUX(1, 137, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux), + .pad_mux_list = c1_can_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = { + MUX(1, 147, 2, 0xa00, 4, 0xa80, 4), + MUX(1, 146, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux), + .pad_mux_list = c1_can_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = { + MUX(0, 2, 2, 0xa00, 4, 0xa80, 4), + MUX(0, 3, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux), + .pad_mux_list = c1_can_grp2_pad_mux, +}; + +static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = { + MUX(1, 62, 4, N, N, N, N), + MUX(1, 63, 4, N, N, N, N), + MUX(1, 64, 4, N, N, N, N), + MUX(1, 65, 4, N, N, N, N), + MUX(1, 66, 4, N, N, N, N), + MUX(1, 67, 4, N, N, N, N), + MUX(1, 68, 4, N, N, N, N), + MUX(1, 69, 4, N, N, N, N), + MUX(1, 70, 4, N, N, N, N), + MUX(1, 71, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_audio_lpc_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux), + .pad_mux_list = ca_audio_lpc_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = { + MUX(1, 85, 5, N, N, N, N), + MUX(1, 86, 5, N, N, N, N), + MUX(1, 87, 5, N, N, N, N), + MUX(1, 88, 5, N, N, N, N), + MUX(1, 89, 5, N, N, N, N), + MUX(1, 90, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_bt_lpc_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux), + .pad_mux_list = ca_bt_lpc_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = { + MUX(1, 129, 1, N, N, N, N), + MUX(1, 130, 1, N, N, N, N), + MUX(1, 131, 1, N, N, N, N), + MUX(1, 132, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_coex_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux), + .pad_mux_list = ca_coex_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = { + MUX(1, 57, 4, N, N, N, N), + MUX(1, 58, 4, N, N, N, N), + MUX(1, 59, 4, N, N, N, N), + MUX(1, 60, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_curator_lpc_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux), + .pad_mux_list = ca_curator_lpc_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = { + MUX(1, 91, 5, N, N, N, N), + MUX(1, 93, 5, N, N, N, N), + MUX(1, 94, 5, N, N, N, N), + MUX(1, 92, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_pcm_debug_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux), + .pad_mux_list = ca_pcm_debug_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = { + MUX(1, 121, 2, N, N, N, N), + MUX(1, 122, 2, N, N, N, N), + MUX(1, 125, 6, N, N, N, N), + MUX(1, 126, 6, N, N, N, N), + MUX(1, 38, 5, N, N, N, N), + MUX(1, 37, 5, N, N, N, N), + MUX(1, 47, 5, N, N, N, N), + MUX(1, 49, 5, N, N, N, N), + MUX(1, 50, 5, N, N, N, N), + MUX(1, 54, 4, N, N, N, N), + MUX(1, 55, 4, N, N, N, N), + MUX(1, 56, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_pio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux), + .pad_mux_list = ca_pio_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = { + MUX(1, 40, 5, N, N, N, N), + MUX(1, 39, 5, N, N, N, N), + MUX(1, 44, 5, N, N, N, N), + MUX(1, 43, 5, N, N, N, N), + MUX(1, 42, 5, N, N, N, N), + MUX(1, 41, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_sdio_debug_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux), + .pad_mux_list = ca_sdio_debug_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = { + MUX(1, 82, 5, N, N, N, N), + MUX(1, 79, 5, 0xa08, 6, 0xa88, 6), + MUX(1, 80, 5, N, N, N, N), + MUX(1, 81, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_spi_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux), + .pad_mux_list = ca_spi_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = { + MUX(1, 91, 4, N, N, N, N), + MUX(1, 93, 4, N, N, N, N), + MUX(1, 94, 4, N, N, N, N), + MUX(1, 95, 4, N, N, N, N), + MUX(1, 96, 4, N, N, N, N), + MUX(1, 78, 5, N, N, N, N), + MUX(1, 74, 5, N, N, N, N), + MUX(1, 75, 5, N, N, N, N), + MUX(1, 76, 5, N, N, N, N), + MUX(1, 77, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_trb_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux), + .pad_mux_list = ca_trb_grp_pad_mux, +}; + +static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = { + MUX(1, 136, 3, N, N, N, N), + MUX(1, 135, 3, N, N, N, N), + MUX(1, 134, 3, N, N, N, N), + MUX(1, 133, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux ca_uart_debug_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux), + .pad_mux_list = ca_uart_debug_grp_pad_mux, +}; + +static struct atlas7_pad_mux clkc_grp0_pad_mux[] = { + MUX(1, 30, 2, 0xa08, 14, 0xa88, 14), + MUX(1, 47, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux clkc_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux), + .pad_mux_list = clkc_grp0_pad_mux, +}; + +static struct atlas7_pad_mux clkc_grp1_pad_mux[] = { + MUX(1, 78, 3, 0xa08, 14, 0xa88, 14), + MUX(1, 54, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux clkc_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux), + .pad_mux_list = clkc_grp1_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = { + MUX(1, 128, 2, N, N, N, N), + MUX(1, 127, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux), + .pad_mux_list = gn_gnss_i2c_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = { + MUX(1, 134, 4, N, N, N, N), + MUX(1, 133, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux), + .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = { + MUX(1, 134, 4, N, N, N, N), + MUX(1, 133, 4, N, N, N, N), + MUX(1, 136, 4, N, N, N, N), + MUX(1, 135, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_uart_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux), + .pad_mux_list = gn_gnss_uart_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = { + MUX(1, 22, 1, N, N, N, N), + MUX(1, 25, 1, N, N, N, N), + MUX(1, 23, 1, 0xa00, 10, 0xa80, 10), + MUX(1, 24, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_spi_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux), + .pad_mux_list = gn_trg_spi_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = { + MUX(1, 82, 3, N, N, N, N), + MUX(1, 79, 3, N, N, N, N), + MUX(1, 80, 3, 0xa00, 10, 0xa80, 10), + MUX(1, 81, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_spi_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux), + .pad_mux_list = gn_trg_spi_grp1_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = { + MUX(1, 54, 3, N, N, N, N), + MUX(1, 53, 3, N, N, N, N), + MUX(1, 82, 7, N, N, N, N), + MUX(1, 74, 7, N, N, N, N), + MUX(1, 75, 7, N, N, N, N), + MUX(1, 76, 7, N, N, N, N), + MUX(1, 77, 7, N, N, N, N), + MUX(1, 78, 7, N, N, N, N), + MUX(1, 79, 7, N, N, N, N), + MUX(1, 80, 7, N, N, N, N), + MUX(1, 81, 7, N, N, N, N), + MUX(1, 83, 7, N, N, N, N), + MUX(1, 84, 7, N, N, N, N), + MUX(1, 73, 3, N, N, N, N), + MUX(1, 55, 3, N, N, N, N), + MUX(1, 56, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_grp_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux), + .pad_mux_list = cvbs_dbg_grp_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = { + MUX(1, 57, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp0_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = { + MUX(1, 58, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp1_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = { + MUX(1, 59, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp2_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = { + MUX(1, 60, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp3_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = { + MUX(1, 61, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp4_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = { + MUX(1, 62, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp5_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = { + MUX(1, 63, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp6_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = { + MUX(1, 64, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp7_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = { + MUX(1, 65, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp8_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = { + MUX(1, 66, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp9_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = { + MUX(1, 67, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp10_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = { + MUX(1, 68, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp11_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = { + MUX(1, 69, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp12_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = { + MUX(1, 70, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp13_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = { + MUX(1, 71, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp14_pad_mux, +}; + +static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = { + MUX(1, 72, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = { + .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux), + .pad_mux_list = cvbs_dbg_test_grp15_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = { + MUX(1, 123, 7, N, N, N, N), + MUX(1, 124, 7, N, N, N, N), + MUX(1, 121, 7, N, N, N, N), + MUX(1, 122, 7, N, N, N, N), + MUX(1, 125, 7, N, N, N, N), + MUX(1, 120, 7, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_power_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux), + .pad_mux_list = gn_gnss_power_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = { + MUX(1, 57, 7, N, N, N, N), + MUX(1, 58, 7, N, N, N, N), + MUX(1, 59, 7, N, N, N, N), + MUX(1, 60, 7, N, N, N, N), + MUX(1, 61, 7, N, N, N, N), + MUX(1, 62, 7, N, N, N, N), + MUX(1, 63, 7, N, N, N, N), + MUX(1, 64, 7, N, N, N, N), + MUX(1, 65, 7, N, N, N, N), + MUX(1, 66, 7, N, N, N, N), + MUX(1, 67, 7, N, N, N, N), + MUX(1, 68, 7, N, N, N, N), + MUX(1, 69, 7, N, N, N, N), + MUX(1, 70, 7, N, N, N, N), + MUX(1, 71, 7, N, N, N, N), + MUX(1, 72, 7, N, N, N, N), + MUX(1, 53, 7, N, N, N, N), + MUX(1, 55, 7, N, N, N, N), + MUX(1, 56, 7, 0xa08, 12, 0xa88, 12), + MUX(1, 54, 7, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux), + .pad_mux_list = gn_gnss_sw_status_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = { + MUX(1, 113, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux), + .pad_mux_list = gn_gnss_eclk_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = { + MUX(1, 112, 4, 0xa08, 10, 0xa88, 10), +}; + +static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux), + .pad_mux_list = gn_gnss_irq1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = { + MUX(1, 118, 4, 0xa08, 11, 0xa88, 11), +}; + +static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux), + .pad_mux_list = gn_gnss_irq2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = { + MUX(1, 115, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_tm_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux), + .pad_mux_list = gn_gnss_tm_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = { + MUX(1, 114, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux), + .pad_mux_list = gn_gnss_tsync_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = { + MUX(1, 44, 7, N, N, N, N), + MUX(1, 43, 7, N, N, N, N), + MUX(1, 42, 7, N, N, N, N), + MUX(1, 41, 7, N, N, N, N), + MUX(1, 40, 7, N, N, N, N), + MUX(1, 39, 7, N, N, N, N), + MUX(1, 38, 7, N, N, N, N), + MUX(1, 37, 7, N, N, N, N), + MUX(1, 49, 7, N, N, N, N), + MUX(1, 50, 7, N, N, N, N), + MUX(1, 91, 7, N, N, N, N), + MUX(1, 92, 7, N, N, N, N), + MUX(1, 93, 7, N, N, N, N), + MUX(1, 94, 7, N, N, N, N), + MUX(1, 95, 7, N, N, N, N), + MUX(1, 96, 7, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = { + .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux), + .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = { + MUX(1, 29, 1, 0xa00, 6, 0xa80, 6), + MUX(1, 28, 1, 0xa00, 7, 0xa80, 7), + MUX(1, 26, 1, 0xa00, 8, 0xa80, 8), + MUX(1, 27, 1, 0xa00, 9, 0xa80, 9), +}; + +static struct atlas7_grp_mux gn_trg_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux), + .pad_mux_list = gn_trg_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = { + MUX(1, 77, 3, 0xa00, 6, 0xa80, 6), + MUX(1, 76, 3, 0xa00, 7, 0xa80, 7), + MUX(1, 74, 3, 0xa00, 8, 0xa80, 8), + MUX(1, 75, 3, 0xa00, 9, 0xa80, 9), +}; + +static struct atlas7_grp_mux gn_trg_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux), + .pad_mux_list = gn_trg_grp1_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = { + MUX(1, 30, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp0_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = { + MUX(1, 83, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp1_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = { + MUX(1, 117, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp2_pad_mux, +}; + +static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = { + MUX(1, 123, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux), + .pad_mux_list = gn_trg_shutdown_grp3_pad_mux, +}; + +static struct atlas7_pad_mux i2c0_grp_pad_mux[] = { + MUX(1, 128, 1, N, N, N, N), + MUX(1, 127, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux i2c0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux), + .pad_mux_list = i2c0_grp_pad_mux, +}; + +static struct atlas7_pad_mux i2c1_grp_pad_mux[] = { + MUX(1, 126, 4, N, N, N, N), + MUX(1, 125, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux i2c1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux), + .pad_mux_list = i2c1_grp_pad_mux, +}; + +static struct atlas7_pad_mux jtag_grp0_pad_mux[] = { + MUX(1, 125, 5, 0xa08, 2, 0xa88, 2), + MUX(0, 4, 3, 0xa08, 3, 0xa88, 3), + MUX(0, 2, 3, N, N, N, N), + MUX(0, 0, 3, N, N, N, N), + MUX(0, 1, 3, N, N, N, N), + MUX(0, 3, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux jtag_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux), + .pad_mux_list = jtag_grp0_pad_mux, +}; + +static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = { + MUX(1, 141, 2, N, N, N, N), + MUX(1, 144, 2, 0xa08, 8, 0xa88, 8), + MUX(1, 143, 2, N, N, N, N), + MUX(1, 142, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux ks_kas_spi_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux), + .pad_mux_list = ks_kas_spi_grp0_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = { + MUX(1, 57, 1, N, N, N, N), + MUX(1, 58, 1, N, N, N, N), + MUX(1, 59, 1, N, N, N, N), + MUX(1, 60, 1, N, N, N, N), + MUX(1, 61, 1, N, N, N, N), + MUX(1, 62, 1, N, N, N, N), + MUX(1, 63, 1, N, N, N, N), + MUX(1, 64, 1, N, N, N, N), + MUX(1, 65, 1, N, N, N, N), + MUX(1, 66, 1, N, N, N, N), + MUX(1, 67, 1, N, N, N, N), + MUX(1, 68, 1, N, N, N, N), + MUX(1, 69, 1, N, N, N, N), + MUX(1, 70, 1, N, N, N, N), + MUX(1, 71, 1, N, N, N, N), + MUX(1, 72, 1, N, N, N, N), + MUX(1, 74, 2, N, N, N, N), + MUX(1, 75, 2, N, N, N, N), + MUX(1, 76, 2, N, N, N, N), + MUX(1, 77, 2, N, N, N, N), + MUX(1, 78, 2, N, N, N, N), + MUX(1, 79, 2, N, N, N, N), + MUX(1, 80, 2, N, N, N, N), + MUX(1, 81, 2, N, N, N, N), + MUX(1, 56, 1, N, N, N, N), + MUX(1, 53, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux), + .pad_mux_list = ld_ldd_grp_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = { + MUX(1, 57, 1, N, N, N, N), + MUX(1, 58, 1, N, N, N, N), + MUX(1, 59, 1, N, N, N, N), + MUX(1, 60, 1, N, N, N, N), + MUX(1, 61, 1, N, N, N, N), + MUX(1, 62, 1, N, N, N, N), + MUX(1, 63, 1, N, N, N, N), + MUX(1, 64, 1, N, N, N, N), + MUX(1, 65, 1, N, N, N, N), + MUX(1, 66, 1, N, N, N, N), + MUX(1, 67, 1, N, N, N, N), + MUX(1, 68, 1, N, N, N, N), + MUX(1, 69, 1, N, N, N, N), + MUX(1, 70, 1, N, N, N, N), + MUX(1, 71, 1, N, N, N, N), + MUX(1, 72, 1, N, N, N, N), + MUX(1, 56, 1, N, N, N, N), + MUX(1, 53, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux), + .pad_mux_list = ld_ldd_16bit_grp_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = { + MUX(1, 55, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_fck_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux), + .pad_mux_list = ld_ldd_fck_grp_pad_mux, +}; + +static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = { + MUX(1, 54, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux ld_ldd_lck_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux), + .pad_mux_list = ld_ldd_lck_grp_pad_mux, +}; + +static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = { + MUX(1, 73, 2, N, N, N, N), + MUX(1, 54, 2, N, N, N, N), + MUX(1, 57, 2, N, N, N, N), + MUX(1, 58, 2, N, N, N, N), + MUX(1, 59, 2, N, N, N, N), + MUX(1, 60, 2, N, N, N, N), + MUX(1, 61, 2, N, N, N, N), + MUX(1, 62, 2, N, N, N, N), + MUX(1, 63, 2, N, N, N, N), + MUX(1, 64, 2, N, N, N, N), + MUX(1, 65, 2, N, N, N, N), + MUX(1, 66, 2, N, N, N, N), + MUX(1, 67, 2, N, N, N, N), + MUX(1, 68, 2, N, N, N, N), + MUX(1, 69, 2, N, N, N, N), + MUX(1, 70, 2, N, N, N, N), + MUX(1, 71, 2, N, N, N, N), + MUX(1, 72, 2, N, N, N, N), + MUX(1, 56, 2, N, N, N, N), + MUX(1, 53, 2, N, N, N, N), + MUX(1, 55, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux lr_lcdrom_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux), + .pad_mux_list = lr_lcdrom_grp_pad_mux, +}; + +static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = { + MUX(1, 149, 8, N, N, N, N), + MUX(1, 150, 8, N, N, N, N), + MUX(1, 151, 8, N, N, N, N), + MUX(1, 152, 8, N, N, N, N), + MUX(1, 153, 8, N, N, N, N), + MUX(1, 154, 8, N, N, N, N), + MUX(1, 155, 8, N, N, N, N), + MUX(1, 156, 8, N, N, N, N), + MUX(1, 157, 8, N, N, N, N), + MUX(1, 158, 8, N, N, N, N), +}; + +static struct atlas7_grp_mux lvds_analog_grp_mux = { + .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux), + .pad_mux_list = lvds_analog_grp_pad_mux, +}; + +static struct atlas7_pad_mux nd_df_grp_pad_mux[] = { + MUX(1, 44, 1, N, N, N, N), + MUX(1, 43, 1, N, N, N, N), + MUX(1, 42, 1, N, N, N, N), + MUX(1, 41, 1, N, N, N, N), + MUX(1, 40, 1, N, N, N, N), + MUX(1, 39, 1, N, N, N, N), + MUX(1, 38, 1, N, N, N, N), + MUX(1, 37, 1, N, N, N, N), + MUX(1, 47, 1, N, N, N, N), + MUX(1, 46, 1, N, N, N, N), + MUX(1, 52, 1, N, N, N, N), + MUX(1, 51, 1, N, N, N, N), + MUX(1, 45, 1, N, N, N, N), + MUX(1, 49, 1, N, N, N, N), + MUX(1, 50, 1, N, N, N, N), + MUX(1, 48, 1, N, N, N, N), + MUX(1, 124, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux nd_df_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux), + .pad_mux_list = nd_df_grp_pad_mux, +}; + +static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = { + MUX(1, 44, 1, N, N, N, N), + MUX(1, 43, 1, N, N, N, N), + MUX(1, 42, 1, N, N, N, N), + MUX(1, 41, 1, N, N, N, N), + MUX(1, 40, 1, N, N, N, N), + MUX(1, 39, 1, N, N, N, N), + MUX(1, 38, 1, N, N, N, N), + MUX(1, 37, 1, N, N, N, N), + MUX(1, 47, 1, N, N, N, N), + MUX(1, 46, 1, N, N, N, N), + MUX(1, 52, 1, N, N, N, N), + MUX(1, 51, 1, N, N, N, N), + MUX(1, 45, 1, N, N, N, N), + MUX(1, 49, 1, N, N, N, N), + MUX(1, 50, 1, N, N, N, N), + MUX(1, 48, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux nd_df_nowp_grp_mux = { + .pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux), + .pad_mux_list = nd_df_nowp_grp_pad_mux, +}; + +static struct atlas7_pad_mux ps_grp_pad_mux[] = { + MUX(1, 120, 2, N, N, N, N), + MUX(1, 119, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux ps_grp_mux = { + .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux), + .pad_mux_list = ps_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = { + MUX(0, 8, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_core_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux), + .pad_mux_list = pwc_core_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = { + MUX(0, 6, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_ext_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux), + .pad_mux_list = pwc_ext_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = { + MUX(0, 3, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux), + .pad_mux_list = pwc_gpio3_clk_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = { + MUX(0, 9, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_io_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux), + .pad_mux_list = pwc_io_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = { + MUX(0, 4, 1, 0xa08, 4, 0xa88, 4), +}; + +static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux), + .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = { + MUX(0, 7, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_mem_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux), + .pad_mux_list = pwc_mem_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = { + MUX(0, 5, 1, 0xa08, 5, 0xa88, 5), +}; + +static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux), + .pad_mux_list = pwc_on_key_b_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = { + MUX(0, 0, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src0_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = { + MUX(0, 1, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src1_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = { + MUX(0, 2, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src2_grp_pad_mux, +}; + +static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = { + MUX(0, 3, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux), + .pad_mux_list = pwc_wakeup_src3_grp_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = { + MUX(1, 123, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux), + .pad_mux_list = pw_cko0_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = { + MUX(1, 101, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux), + .pad_mux_list = pw_cko0_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = { + MUX(1, 82, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux), + .pad_mux_list = pw_cko0_grp2_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = { + MUX(1, 124, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux), + .pad_mux_list = pw_cko1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = { + MUX(1, 110, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko1_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux), + .pad_mux_list = pw_cko1_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = { + MUX(1, 125, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux), + .pad_mux_list = pw_i2s01_clk_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = { + MUX(1, 117, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux), + .pad_mux_list = pw_i2s01_clk_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = { + MUX(1, 119, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux), + .pad_mux_list = pw_pwm0_grp_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = { + MUX(1, 120, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux), + .pad_mux_list = pw_pwm1_grp_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = { + MUX(1, 121, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux), + .pad_mux_list = pw_pwm2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = { + MUX(1, 98, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm2_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux), + .pad_mux_list = pw_pwm2_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = { + MUX(1, 122, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm3_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux), + .pad_mux_list = pw_pwm3_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = { + MUX(1, 73, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm3_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux), + .pad_mux_list = pw_pwm3_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = { + MUX(1, 121, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux), + .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = { + MUX(1, 98, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux), + .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = { + MUX(1, 122, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_backlight_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux), + .pad_mux_list = pw_backlight_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = { + MUX(1, 73, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_backlight_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux), + .pad_mux_list = pw_backlight_grp1_pad_mux, +}; + +static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = { + MUX(1, 108, 1, N, N, N, N), + MUX(1, 103, 1, N, N, N, N), + MUX(1, 104, 1, N, N, N, N), + MUX(1, 105, 1, N, N, N, N), + MUX(1, 106, 1, N, N, N, N), + MUX(1, 107, 1, N, N, N, N), + MUX(1, 102, 1, N, N, N, N), + MUX(1, 97, 1, N, N, N, N), + MUX(1, 98, 1, N, N, N, N), + MUX(1, 99, 1, N, N, N, N), + MUX(1, 100, 1, N, N, N, N), + MUX(1, 101, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_eth_mac_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux), + .pad_mux_list = rg_eth_mac_grp_pad_mux, +}; + +static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = { + MUX(1, 111, 1, 0xa08, 13, 0xa88, 13), +}; + +static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux), + .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux, +}; + +static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = { + MUX(1, 109, 1, N, N, N, N), + MUX(1, 110, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = { + .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux), + .pad_mux_list = rg_rgmii_mac_grp_pad_mux, +}; + +static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = { + MUX(1, 111, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux), + .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux, +}; + +static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = { + MUX(1, 53, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux), + .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sd0_grp_pad_mux[] = { + MUX(1, 46, 2, N, N, N, N), + MUX(1, 47, 2, N, N, N, N), + MUX(1, 44, 2, N, N, N, N), + MUX(1, 43, 2, N, N, N, N), + MUX(1, 42, 2, N, N, N, N), + MUX(1, 41, 2, N, N, N, N), + MUX(1, 40, 2, N, N, N, N), + MUX(1, 39, 2, N, N, N, N), + MUX(1, 38, 2, N, N, N, N), + MUX(1, 37, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux), + .pad_mux_list = sd0_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = { + MUX(1, 46, 2, N, N, N, N), + MUX(1, 47, 2, N, N, N, N), + MUX(1, 44, 2, N, N, N, N), + MUX(1, 43, 2, N, N, N, N), + MUX(1, 42, 2, N, N, N, N), + MUX(1, 41, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd0_4bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux), + .pad_mux_list = sd0_4bit_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd1_grp_pad_mux[] = { + MUX(1, 48, 3, N, N, N, N), + MUX(1, 49, 3, N, N, N, N), + MUX(1, 44, 3, 0xa00, 0, 0xa80, 0), + MUX(1, 43, 3, 0xa00, 1, 0xa80, 1), + MUX(1, 42, 3, 0xa00, 2, 0xa80, 2), + MUX(1, 41, 3, 0xa00, 3, 0xa80, 3), + MUX(1, 40, 3, N, N, N, N), + MUX(1, 39, 3, N, N, N, N), + MUX(1, 38, 3, N, N, N, N), + MUX(1, 37, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux sd1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux), + .pad_mux_list = sd1_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = { + MUX(1, 48, 3, N, N, N, N), + MUX(1, 49, 3, N, N, N, N), + MUX(1, 44, 3, 0xa00, 0, 0xa80, 0), + MUX(1, 43, 3, 0xa00, 1, 0xa80, 1), + MUX(1, 42, 3, 0xa00, 2, 0xa80, 2), + MUX(1, 41, 3, 0xa00, 3, 0xa80, 3), +}; + +static struct atlas7_grp_mux sd1_4bit_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux), + .pad_mux_list = sd1_4bit_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = { + MUX(1, 48, 3, N, N, N, N), + MUX(1, 49, 3, N, N, N, N), + MUX(1, 40, 4, 0xa00, 0, 0xa80, 0), + MUX(1, 39, 4, 0xa00, 1, 0xa80, 1), + MUX(1, 38, 4, 0xa00, 2, 0xa80, 2), + MUX(1, 37, 4, 0xa00, 3, 0xa80, 3), +}; + +static struct atlas7_grp_mux sd1_4bit_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux), + .pad_mux_list = sd1_4bit_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sd2_grp0_pad_mux[] = { + MUX(1, 124, 2, 0xa08, 7, 0xa88, 7), + MUX(1, 31, 1, N, N, N, N), + MUX(1, 32, 1, N, N, N, N), + MUX(1, 33, 1, N, N, N, N), + MUX(1, 34, 1, N, N, N, N), + MUX(1, 35, 1, N, N, N, N), + MUX(1, 36, 1, N, N, N, N), + MUX(1, 123, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd2_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux), + .pad_mux_list = sd2_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = { + MUX(1, 31, 1, N, N, N, N), + MUX(1, 32, 1, N, N, N, N), + MUX(1, 33, 1, N, N, N, N), + MUX(1, 34, 1, N, N, N, N), + MUX(1, 35, 1, N, N, N, N), + MUX(1, 36, 1, N, N, N, N), + MUX(1, 123, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux), + .pad_mux_list = sd2_no_cdb_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd3_grp_pad_mux[] = { + MUX(1, 85, 1, N, N, N, N), + MUX(1, 86, 1, N, N, N, N), + MUX(1, 87, 1, N, N, N, N), + MUX(1, 88, 1, N, N, N, N), + MUX(1, 89, 1, N, N, N, N), + MUX(1, 90, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sd3_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux), + .pad_mux_list = sd3_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd5_grp_pad_mux[] = { + MUX(1, 91, 1, N, N, N, N), + MUX(1, 92, 1, N, N, N, N), + MUX(1, 93, 1, N, N, N, N), + MUX(1, 94, 1, N, N, N, N), + MUX(1, 95, 1, N, N, N, N), + MUX(1, 96, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sd5_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux), + .pad_mux_list = sd5_grp_pad_mux, +}; + +static struct atlas7_pad_mux sd6_grp0_pad_mux[] = { + MUX(1, 79, 4, 0xa00, 27, 0xa80, 27), + MUX(1, 78, 4, 0xa00, 26, 0xa80, 26), + MUX(1, 74, 4, 0xa00, 28, 0xa80, 28), + MUX(1, 75, 4, 0xa00, 29, 0xa80, 29), + MUX(1, 76, 4, 0xa00, 30, 0xa80, 30), + MUX(1, 77, 4, 0xa00, 31, 0xa80, 31), +}; + +static struct atlas7_grp_mux sd6_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux), + .pad_mux_list = sd6_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd6_grp1_pad_mux[] = { + MUX(1, 101, 3, 0xa00, 27, 0xa80, 27), + MUX(1, 99, 3, 0xa00, 26, 0xa80, 26), + MUX(1, 100, 3, 0xa00, 28, 0xa80, 28), + MUX(1, 110, 3, 0xa00, 29, 0xa80, 29), + MUX(1, 109, 3, 0xa00, 30, 0xa80, 30), + MUX(1, 111, 3, 0xa00, 31, 0xa80, 31), +}; + +static struct atlas7_grp_mux sd6_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux), + .pad_mux_list = sd6_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = { + MUX(0, 4, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux), + .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux, +}; + +static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = { + MUX(0, 12, 1, N, N, N, N), + MUX(0, 13, 1, N, N, N, N), + MUX(0, 14, 1, N, N, N, N), + MUX(0, 15, 1, N, N, N, N), + MUX(0, 16, 1, N, N, N, N), + MUX(0, 17, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sp0_qspi_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux), + .pad_mux_list = sp0_qspi_grp_pad_mux, +}; + +static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = { + MUX(1, 19, 1, N, N, N, N), + MUX(1, 20, 1, N, N, N, N), + MUX(1, 21, 1, N, N, N, N), + MUX(1, 18, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux sp1_spi_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux), + .pad_mux_list = sp1_spi_grp_pad_mux, +}; + +static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = { + MUX(1, 53, 5, N, N, N, N), + MUX(1, 56, 5, N, N, N, N), + MUX(1, 57, 5, N, N, N, N), + MUX(1, 58, 5, N, N, N, N), + MUX(1, 59, 5, N, N, N, N), + MUX(1, 60, 5, N, N, N, N), + MUX(1, 61, 5, N, N, N, N), + MUX(1, 62, 5, N, N, N, N), + MUX(1, 63, 5, N, N, N, N), + MUX(1, 64, 5, N, N, N, N), + MUX(1, 65, 5, N, N, N, N), + MUX(1, 66, 5, N, N, N, N), + MUX(1, 67, 5, N, N, N, N), + MUX(1, 68, 5, N, N, N, N), + MUX(1, 69, 5, N, N, N, N), + MUX(1, 70, 5, N, N, N, N), + MUX(1, 71, 5, N, N, N, N), + MUX(1, 72, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux tpiu_trace_grp_mux = { + .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux), + .pad_mux_list = tpiu_trace_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart0_grp_pad_mux[] = { + MUX(1, 121, 4, N, N, N, N), + MUX(1, 120, 4, N, N, N, N), + MUX(1, 134, 1, N, N, N, N), + MUX(1, 133, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux), + .pad_mux_list = uart0_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = { + MUX(1, 134, 1, N, N, N, N), + MUX(1, 133, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart0_nopause_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux), + .pad_mux_list = uart0_nopause_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart1_grp_pad_mux[] = { + MUX(1, 136, 1, N, N, N, N), + MUX(1, 135, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux), + .pad_mux_list = uart1_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart2_grp_pad_mux[] = { + MUX(0, 11, 2, N, N, N, N), + MUX(0, 10, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux), + .pad_mux_list = uart2_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp0_pad_mux[] = { + MUX(1, 125, 2, 0xa08, 0, 0xa88, 0), + MUX(1, 126, 2, N, N, N, N), + MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), + MUX(1, 137, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux), + .pad_mux_list = uart3_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp1_pad_mux[] = { + MUX(1, 111, 4, 0xa08, 0, 0xa88, 0), + MUX(1, 109, 4, N, N, N, N), + MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), + MUX(1, 83, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux), + .pad_mux_list = uart3_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp2_pad_mux[] = { + MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), + MUX(1, 139, 2, N, N, N, N), + MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), + MUX(1, 137, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux), + .pad_mux_list = uart3_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_grp3_pad_mux[] = { + MUX(1, 139, 2, N, N, N, N), + MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), + MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), + MUX(1, 83, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux), + .pad_mux_list = uart3_grp3_pad_mux, +}; + +static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = { + MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), + MUX(1, 137, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_nopause_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux), + .pad_mux_list = uart3_nopause_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = { + MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), + MUX(1, 83, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_nopause_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux), + .pad_mux_list = uart3_nopause_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart4_grp0_pad_mux[] = { + MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), + MUX(1, 123, 4, N, N, N, N), + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux), + .pad_mux_list = uart4_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart4_grp1_pad_mux[] = { + MUX(1, 100, 4, 0xa08, 1, 0xa88, 1), + MUX(1, 99, 4, N, N, N, N), + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux), + .pad_mux_list = uart4_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart4_grp2_pad_mux[] = { + MUX(1, 117, 2, 0xa08, 1, 0xa88, 1), + MUX(1, 116, 2, N, N, N, N), + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux), + .pad_mux_list = uart4_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = { + MUX(1, 140, 1, N, N, N, N), + MUX(1, 139, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_nopause_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux), + .pad_mux_list = uart4_nopause_grp_pad_mux, +}; + +static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = { + MUX(1, 51, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux usb0_drvvbus_grp_mux = { + .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux), + .pad_mux_list = usb0_drvvbus_grp_pad_mux, +}; + +static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = { + MUX(1, 134, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux usb1_drvvbus_grp_mux = { + .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux), + .pad_mux_list = usb1_drvvbus_grp_pad_mux, +}; + +static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = { + MUX(1, 57, 6, N, N, N, N), + MUX(1, 58, 6, N, N, N, N), + MUX(1, 59, 6, N, N, N, N), + MUX(1, 60, 6, N, N, N, N), + MUX(1, 61, 6, N, N, N, N), + MUX(1, 62, 6, N, N, N, N), + MUX(1, 63, 6, N, N, N, N), + MUX(1, 64, 6, N, N, N, N), + MUX(1, 65, 6, N, N, N, N), + MUX(1, 66, 6, N, N, N, N), + MUX(1, 67, 6, N, N, N, N), + MUX(1, 68, 6, N, N, N, N), + MUX(1, 69, 6, N, N, N, N), + MUX(1, 70, 6, N, N, N, N), + MUX(1, 71, 6, N, N, N, N), + MUX(1, 72, 6, N, N, N, N), + MUX(1, 53, 6, N, N, N, N), + MUX(1, 54, 6, N, N, N, N), + MUX(1, 55, 6, N, N, N, N), + MUX(1, 56, 6, N, N, N, N), + MUX(1, 85, 6, N, N, N, N), + MUX(1, 86, 6, N, N, N, N), + MUX(1, 87, 6, N, N, N, N), + MUX(1, 88, 6, N, N, N, N), + MUX(1, 89, 6, N, N, N, N), + MUX(1, 90, 6, N, N, N, N), + MUX(1, 91, 6, N, N, N, N), + MUX(1, 92, 6, N, N, N, N), + MUX(1, 93, 6, N, N, N, N), + MUX(1, 94, 6, N, N, N, N), + MUX(1, 95, 6, N, N, N, N), + MUX(1, 96, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux visbus_dout_grp_mux = { + .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux), + .pad_mux_list = visbus_dout_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = { + MUX(1, 74, 1, N, N, N, N), + MUX(1, 75, 1, N, N, N, N), + MUX(1, 76, 1, N, N, N, N), + MUX(1, 77, 1, N, N, N, N), + MUX(1, 78, 1, N, N, N, N), + MUX(1, 79, 1, N, N, N, N), + MUX(1, 80, 1, N, N, N, N), + MUX(1, 81, 1, N, N, N, N), + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), + MUX(1, 103, 2, N, N, N, N), + MUX(1, 104, 2, N, N, N, N), + MUX(1, 105, 2, N, N, N, N), + MUX(1, 106, 2, N, N, N, N), + MUX(1, 107, 2, N, N, N, N), + MUX(1, 102, 2, N, N, N, N), + MUX(1, 97, 2, N, N, N, N), + MUX(1, 98, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux), + .pad_mux_list = vi_vip1_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = { + MUX(1, 74, 1, N, N, N, N), + MUX(1, 75, 1, N, N, N, N), + MUX(1, 76, 1, N, N, N, N), + MUX(1, 77, 1, N, N, N, N), + MUX(1, 78, 1, N, N, N, N), + MUX(1, 79, 1, N, N, N, N), + MUX(1, 80, 1, N, N, N, N), + MUX(1, 81, 1, N, N, N, N), + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), + MUX(1, 108, 2, N, N, N, N), + MUX(1, 103, 2, N, N, N, N), + MUX(1, 104, 2, N, N, N, N), + MUX(1, 105, 2, N, N, N, N), + MUX(1, 106, 2, N, N, N, N), + MUX(1, 107, 2, N, N, N, N), + MUX(1, 102, 2, N, N, N, N), + MUX(1, 97, 2, N, N, N, N), + MUX(1, 98, 2, N, N, N, N), + MUX(1, 99, 2, N, N, N, N), + MUX(1, 100, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_ext_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux), + .pad_mux_list = vi_vip1_ext_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = { + MUX(1, 74, 1, N, N, N, N), + MUX(1, 75, 1, N, N, N, N), + MUX(1, 76, 1, N, N, N, N), + MUX(1, 77, 1, N, N, N, N), + MUX(1, 78, 1, N, N, N, N), + MUX(1, 79, 1, N, N, N, N), + MUX(1, 80, 1, N, N, N, N), + MUX(1, 81, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux), + .pad_mux_list = vi_vip1_low8bit_grp_pad_mux, +}; + +static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = { + MUX(1, 82, 1, N, N, N, N), + MUX(1, 83, 1, N, N, N, N), + MUX(1, 84, 1, N, N, N, N), + MUX(1, 108, 2, N, N, N, N), + MUX(1, 103, 2, N, N, N, N), + MUX(1, 104, 2, N, N, N, N), + MUX(1, 105, 2, N, N, N, N), + MUX(1, 106, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = { + .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux), + .pad_mux_list = vi_vip1_high8bit_grp_pad_mux, +}; + +static struct atlas7_pmx_func atlas7_pmx_functions[] = { + FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux), + FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux), + FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux), + FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux), + FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux), + FUNCTION("uart_nand_gpio", + uart_nand_gpio_grp, + &uart_nand_gpio_grp_mux), + FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux), + FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux), + FUNCTION("audio_func_dbg", + audio_func_dbg_grp, + &audio_func_dbg_grp_mux), + FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux), + FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux), + FUNCTION("audio_i2s_extclk", + audio_i2s_extclk_grp, + &audio_i2s_extclk_grp_mux), + FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux), + FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux), + FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux), + FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux), + FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux), + FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux), + FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux), + FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux), + FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux), + FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux), + FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux), + FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux), + FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux), + FUNCTION("ca_curator_lpc", + ca_curator_lpc_grp, + &ca_curator_lpc_grp_mux), + FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux), + FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux), + FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux), + FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux), + FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux), + FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux), + FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux), + FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux), + FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux), + FUNCTION("gn_gnss_uart_nopause", + gn_gnss_uart_nopause_grp, + &gn_gnss_uart_nopause_grp_mux), + FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux), + FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux), + FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux), + FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux), + FUNCTION("cvbs_dbg_test_m0", + cvbs_dbg_test_grp0, + &cvbs_dbg_test_grp0_mux), + FUNCTION("cvbs_dbg_test_m1", + cvbs_dbg_test_grp1, + &cvbs_dbg_test_grp1_mux), + FUNCTION("cvbs_dbg_test_m2", + cvbs_dbg_test_grp2, + &cvbs_dbg_test_grp2_mux), + FUNCTION("cvbs_dbg_test_m3", + cvbs_dbg_test_grp3, + &cvbs_dbg_test_grp3_mux), + FUNCTION("cvbs_dbg_test_m4", + cvbs_dbg_test_grp4, + &cvbs_dbg_test_grp4_mux), + FUNCTION("cvbs_dbg_test_m5", + cvbs_dbg_test_grp5, + &cvbs_dbg_test_grp5_mux), + FUNCTION("cvbs_dbg_test_m6", + cvbs_dbg_test_grp6, + &cvbs_dbg_test_grp6_mux), + FUNCTION("cvbs_dbg_test_m7", + cvbs_dbg_test_grp7, + &cvbs_dbg_test_grp7_mux), + FUNCTION("cvbs_dbg_test_m8", + cvbs_dbg_test_grp8, + &cvbs_dbg_test_grp8_mux), + FUNCTION("cvbs_dbg_test_m9", + cvbs_dbg_test_grp9, + &cvbs_dbg_test_grp9_mux), + FUNCTION("cvbs_dbg_test_m10", + cvbs_dbg_test_grp10, + &cvbs_dbg_test_grp10_mux), + FUNCTION("cvbs_dbg_test_m11", + cvbs_dbg_test_grp11, + &cvbs_dbg_test_grp11_mux), + FUNCTION("cvbs_dbg_test_m12", + cvbs_dbg_test_grp12, + &cvbs_dbg_test_grp12_mux), + FUNCTION("cvbs_dbg_test_m13", + cvbs_dbg_test_grp13, + &cvbs_dbg_test_grp13_mux), + FUNCTION("cvbs_dbg_test_m14", + cvbs_dbg_test_grp14, + &cvbs_dbg_test_grp14_mux), + FUNCTION("cvbs_dbg_test_m15", + cvbs_dbg_test_grp15, + &cvbs_dbg_test_grp15_mux), + FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux), + FUNCTION("gn_gnss_sw_status", + gn_gnss_sw_status_grp, + &gn_gnss_sw_status_grp_mux), + FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux), + FUNCTION("gn_gnss_irq1_m0", + gn_gnss_irq1_grp0, + &gn_gnss_irq1_grp0_mux), + FUNCTION("gn_gnss_irq2_m0", + gn_gnss_irq2_grp0, + &gn_gnss_irq2_grp0_mux), + FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux), + FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux), + FUNCTION("gn_io_gnsssys_sw_cfg", + gn_io_gnsssys_sw_cfg_grp, + &gn_io_gnsssys_sw_cfg_grp_mux), + FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux), + FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux), + FUNCTION("gn_trg_shutdown_m0", + gn_trg_shutdown_grp0, + &gn_trg_shutdown_grp0_mux), + FUNCTION("gn_trg_shutdown_m1", + gn_trg_shutdown_grp1, + &gn_trg_shutdown_grp1_mux), + FUNCTION("gn_trg_shutdown_m2", + gn_trg_shutdown_grp2, + &gn_trg_shutdown_grp2_mux), + FUNCTION("gn_trg_shutdown_m3", + gn_trg_shutdown_grp3, + &gn_trg_shutdown_grp3_mux), + FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux), + FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux), + FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux), + FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux), + FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux), + FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux), + FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux), + FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux), + FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux), + FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux), + FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux), + FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux), + FUNCTION("ps", ps_grp, &ps_grp_mux), + FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux), + FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux), + FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux), + FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux), + FUNCTION("pwc_lowbatt_b_m0", + pwc_lowbatt_b_grp0, + &pwc_lowbatt_b_grp0_mux), + FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux), + FUNCTION("pwc_on_key_b_m0", + pwc_on_key_b_grp0, + &pwc_on_key_b_grp0_mux), + FUNCTION("pwc_wakeup_src0", + pwc_wakeup_src0_grp, + &pwc_wakeup_src0_grp_mux), + FUNCTION("pwc_wakeup_src1", + pwc_wakeup_src1_grp, + &pwc_wakeup_src1_grp_mux), + FUNCTION("pwc_wakeup_src2", + pwc_wakeup_src2_grp, + &pwc_wakeup_src2_grp_mux), + FUNCTION("pwc_wakeup_src3", + pwc_wakeup_src3_grp, + &pwc_wakeup_src3_grp_mux), + FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux), + FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux), + FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux), + FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux), + FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux), + FUNCTION("pw_i2s01_clk_m0", + pw_i2s01_clk_grp0, + &pw_i2s01_clk_grp0_mux), + FUNCTION("pw_i2s01_clk_m1", + pw_i2s01_clk_grp1, + &pw_i2s01_clk_grp1_mux), + FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux), + FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux), + FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux), + FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux), + FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux), + FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux), + FUNCTION("pw_pwm_cpu_vol_m0", + pw_pwm_cpu_vol_grp0, + &pw_pwm_cpu_vol_grp0_mux), + FUNCTION("pw_pwm_cpu_vol_m1", + pw_pwm_cpu_vol_grp1, + &pw_pwm_cpu_vol_grp1_mux), + FUNCTION("pw_backlight_m0", + pw_backlight_grp0, + &pw_backlight_grp0_mux), + FUNCTION("pw_backlight_m1", + pw_backlight_grp1, + &pw_backlight_grp1_mux), + FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux), + FUNCTION("rg_gmac_phy_intr_n", + rg_gmac_phy_intr_n_grp, + &rg_gmac_phy_intr_n_grp_mux), + FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux), + FUNCTION("rg_rgmii_phy_ref_clk_m0", + rg_rgmii_phy_ref_clk_grp0, + &rg_rgmii_phy_ref_clk_grp0_mux), + FUNCTION("rg_rgmii_phy_ref_clk_m1", + rg_rgmii_phy_ref_clk_grp1, + &rg_rgmii_phy_ref_clk_grp1_mux), + FUNCTION("sd0", sd0_grp, &sd0_grp_mux), + FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux), + FUNCTION("sd1", sd1_grp, &sd1_grp_mux), + FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux), + FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux), + FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux), + FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux), + FUNCTION("sd3", sd3_grp, &sd3_grp_mux), + FUNCTION("sd5", sd5_grp, &sd5_grp_mux), + FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux), + FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux), + FUNCTION("sp0_ext_ldo_on", + sp0_ext_ldo_on_grp, + &sp0_ext_ldo_on_grp_mux), + FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux), + FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux), + FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux), + FUNCTION("uart0", uart0_grp, &uart0_grp_mux), + FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux), + FUNCTION("uart1", uart1_grp, &uart1_grp_mux), + FUNCTION("uart2", uart2_grp, &uart2_grp_mux), + FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux), + FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux), + FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux), + FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux), + FUNCTION("uart3_nopause_m0", + uart3_nopause_grp0, + &uart3_nopause_grp0_mux), + FUNCTION("uart3_nopause_m1", + uart3_nopause_grp1, + &uart3_nopause_grp1_mux), + FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux), + FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux), + FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux), + FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux), + FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux), + FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux), + FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux), + FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux), + FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux), + FUNCTION("vi_vip1_low8bit", + vi_vip1_low8bit_grp, + &vi_vip1_low8bit_grp_mux), + FUNCTION("vi_vip1_high8bit", + vi_vip1_high8bit_grp, + &vi_vip1_high8bit_grp_mux), +}; + +struct atlas7_pinctrl_data atlas7_ioc_data = { + .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads, + .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads), + .grps = (struct atlas7_pin_group *)altas7_pin_groups, + .grps_cnt = ARRAY_SIZE(altas7_pin_groups), + .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions, + .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions), + .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs, + .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs), +}; + +static inline u32 atlas7_pin_to_bank(u32 pin) +{ + return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0; +} + +static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->funcs_cnt; +} + +static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev, + u32 selector) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->funcs[selector].name; +} + +static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev, + u32 selector, const char * const **groups, + u32 * const num_groups) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *groups = pmx->pctl_data->funcs[selector].groups; + *num_groups = pmx->pctl_data->funcs[selector].num_groups; + + return 0; +} + +static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx, + const struct atlas7_pad_mux *mux) +{ + /* Set Input Disable to avoid input glitches + * + * All Input-Disable Control registers are located on IOCRTC. + * So the regs bank is always 0. + * + */ + if (mux->dinput_reg && mux->dinput_val_reg) { + writel(DI_MASK << mux->dinput_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg)); + writel(DI_DISABLE << mux->dinput_bit, + pmx->regs[BANK_DS] + mux->dinput_reg); + + + writel(DIV_MASK << mux->dinput_val_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg)); + writel(DIV_DISABLE << mux->dinput_val_bit, + pmx->regs[BANK_DS] + mux->dinput_val_reg); + } +} + +static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx, + const struct atlas7_pad_mux *mux) +{ + /* Clear Input Disable to avoid input glitches */ + if (mux->dinput_reg && mux->dinput_val_reg) { + writel(DI_MASK << mux->dinput_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg)); + writel(DI_ENABLE << mux->dinput_bit, + pmx->regs[BANK_DS] + mux->dinput_reg); + + writel(DIV_MASK << mux->dinput_val_bit, + pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg)); + writel(DIV_ENABLE << mux->dinput_val_bit, + pmx->regs[BANK_DS] + mux->dinput_val_reg); + } +} + +static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx, + struct atlas7_pad_config *conf, + u32 bank, u32 ad_sel) +{ + unsigned long regv; + + /* Write to clear register to clear A/D selector */ + writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit, + pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg)); + + /* Set target pad A/D selector */ + regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); + regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit); + writel(regv | (ad_sel << conf->ad_ctrl_bit), + pmx->regs[bank] + conf->ad_ctrl_reg); + + regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); + pr_debug("bank:%d reg:0x%04x val:0x%08lx\n", + bank, conf->ad_ctrl_reg, regv); + return 0; +} + +static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx, + struct atlas7_pad_config *conf, u32 bank) +{ + /* Only PAD_T_AD pins can change between Analogue&Digital */ + if (conf->type != PAD_T_AD) + return -EINVAL; + + return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0); +} + +static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx, + struct atlas7_pad_config *conf, u32 bank) +{ + /* Other type pads are always digital */ + if (conf->type != PAD_T_AD) + return 0; + + return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1); +} + +static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx, + u32 pin, u32 func) +{ + struct atlas7_pad_config *conf; + u32 bank; + int ret; + unsigned long regv; + + pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n", + pin, func); + + /* Get this Pad's descriptor from PINCTRL */ + conf = &pmx->pctl_data->confs[pin]; + bank = atlas7_pin_to_bank(pin); + + /* Just enable the analog function of this pad */ + if (FUNC_ANALOGUE == func) { + ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank); + if (ret) + dev_err(pmx->dev, + "Convert pad#%d to analog failed, ret=%d\n", + pin, ret); + return ret; + } + + /* Set Pads from analog to digital */ + ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank); + if (ret) { + dev_err(pmx->dev, + "Convert pad#%d to digital failed, ret=%d\n", + pin, ret); + return ret; + } + + /* Write to clear register to clear current function */ + writel(FUNC_CLEAR_MASK << conf->mux_bit, + pmx->regs[bank] + CLR_REG(conf->mux_reg)); + + /* Set target pad mux function */ + regv = readl(pmx->regs[bank] + conf->mux_reg); + regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit); + writel(regv | (func << conf->mux_bit), + pmx->regs[bank] + conf->mux_reg); + + regv = readl(pmx->regs[bank] + conf->mux_reg); + pr_debug("bank:%d reg:0x%04x val:0x%08lx\n", + bank, conf->mux_reg, regv); + + return 0; +} + +static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev, + u32 func_selector, u32 group_selector) +{ + int idx, ret; + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pmx_func *pmx_func; + struct atlas7_pin_group *pin_grp; + const struct atlas7_grp_mux *grp_mux; + const struct atlas7_pad_mux *mux; + + pmx_func = &pmx->pctl_data->funcs[func_selector]; + pin_grp = &pmx->pctl_data->grps[group_selector]; + + pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n", + pmx_func->name, pin_grp->name); + + grp_mux = pmx_func->grpmux; + + for (idx = 0; idx < grp_mux->pad_mux_count; idx++) { + mux = &grp_mux->pad_mux_list[idx]; + __atlas7_pmx_pin_input_disable_set(pmx, mux); + ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func); + if (ret) { + dev_err(pmx->dev, + "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n", + pmx_func->name, pin_grp->name, + mux->pin, mux->func, ret); + BUG_ON(1); + } + __atlas7_pmx_pin_input_disable_clr(pmx, mux); + } + pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n", + pmx_func->name, pin_grp->name); + + return 0; +} + +struct atlas7_ds_info { + u32 ma; + u32 ds_16st; + u32 ds_4we; + u32 ds_0204m31; + u32 ds_0610m31; +}; + +const struct atlas7_ds_info atlas7_ds_map[] = { + { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL}, + { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL}, + { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0}, + { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL}, + { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1}, + { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL}, + { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL}, + { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL}, + { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL}, + { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL}, + { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL}, + { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL}, + { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL}, + { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL}, + { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL}, + { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL}, +}; + +static u32 convert_current_to_drive_strength(u32 type, u32 ma) +{ + int idx; + + for (idx = 0; idx < ARRAY_SIZE(atlas7_ds_map); idx++) { + if (atlas7_ds_map[idx].ma != ma) + continue; + + if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) + return atlas7_ds_map[idx].ds_4we; + else if (type == PAD_T_16ST) + return atlas7_ds_map[idx].ds_16st; + else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU) + return atlas7_ds_map[idx].ds_0204m31; + else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) + return atlas7_ds_map[idx].ds_0610m31; + } + + return DS_NULL; +} + +static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev, + u32 pin, u32 sel) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; + u32 type = conf->type; + u32 shift = conf->pupd_bit; + u32 bank = atlas7_pin_to_bank(pin); + void __iomem *pull_sel_reg, *pull_clr_reg; + + pull_sel_reg = pmx->regs[bank] + conf->pupd_reg; + pull_clr_reg = CLR_REG(pull_sel_reg); + + if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) { + writel(P4WE_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(P4WE_PULL_UP << shift, pull_sel_reg); + else if (sel == HIGH_HYSTERESIS) + writel(P4WE_HIGH_HYSTERESIS << shift, pull_sel_reg); + else if (sel == HIGH_Z) + writel(P4WE_HIGH_Z << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(P4WE_PULL_DOWN << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for 4WEPAD#%d\n", + pin); + return -ENOTSUPP; + } + } else if (type == PAD_T_16ST) { + writel(P16ST_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(P16ST_PULL_UP << shift, pull_sel_reg); + else if (sel == HIGH_Z) + writel(P16ST_HIGH_Z << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(P16ST_PULL_DOWN << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for 16STPAD#%d\n", + pin); + return -ENOTSUPP; + } + } else if (type == PAD_T_M31_0204_PD || + type == PAD_T_M31_0204_PU || + type == PAD_T_M31_0610_PD || + type == PAD_T_M31_0610_PU) { + writel(PM31_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(PM31_PULL_ENABLED << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(PM31_PULL_DISABLED << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for M31PAD#%d\n", + pin); + return -ENOTSUPP; + } + } else if (type == PAD_T_AD) { + writel(PANGD_PULL_MASK << shift, pull_clr_reg); + + if (sel == PULL_UP) + writel(PANGD_PULL_UP << shift, pull_sel_reg); + else if (sel == HIGH_Z) + writel(PANGD_HIGH_Z << shift, pull_sel_reg); + else if (sel == PULL_DOWN) + writel(PANGD_PULL_DOWN << shift, pull_sel_reg); + else { + pr_err("Unknown Pull select type for A/D PAD#%d\n", + pin); + return -ENOTSUPP; + } + } else { + pr_err("Unknown Pad type[%d] for pull select PAD#%d\n", + type, pin); + return -ENOTSUPP; + } + + pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n", + pin, sel); + return 0; +} + +static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev, + u32 pin, u32 sel) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; + u32 type = conf->type; + u32 shift = conf->drvstr_bit; + u32 bank = atlas7_pin_to_bank(pin); + void __iomem *ds_sel_reg, *ds_clr_reg; + + ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg; + ds_clr_reg = CLR_REG(ds_sel_reg); + if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) { + if (sel & (~DS_2BIT_MASK)) + goto unsupport; + + writel(DS_2BIT_IM_VAL << shift, ds_clr_reg); + writel(sel << shift, ds_sel_reg); + + return 0; + } else if (type == PAD_T_16ST) { + if (sel & (~DS_4BIT_MASK)) + goto unsupport; + + writel(DS_4BIT_IM_VAL << shift, ds_clr_reg); + writel(sel << shift, ds_sel_reg); + + return 0; + } else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU || + type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) { + if (sel & (~DS_1BIT_MASK)) + goto unsupport; + + writel(DS_1BIT_IM_VAL << shift, ds_clr_reg); + writel(sel << shift, ds_sel_reg); + + return 0; + } + +unsupport: + pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n", + pin, type, sel); + return -ENOTSUPP; +} + +static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev, + u32 pin, u32 ma) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; + u32 type = conf->type; + u32 sel; + int ret; + + sel = convert_current_to_drive_strength(conf->type, ma); + if (DS_NULL == sel) { + pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n", + pin, type, ma); + return -ENOTSUPP; + } + + ret = __altas7_pinctrl_set_drive_strength_sel(pctldev, + pin, sel); + pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n", + pin, sel, ma, ret?"FAILED":"OK"); + return ret; +} + +static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, u32 pin) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + u32 idx; + + dev_dbg(pmx->dev, + "atlas7_pmx_gpio_request_enable: pin=%d\n", pin); + for (idx = 0; idx < range->npins; idx++) { + if (pin == range->pins[idx]) + break; + } + + if (idx >= range->npins) { + dev_err(pmx->dev, + "The pin#%d could not be requested as GPIO!!\n", + pin); + return -EPERM; + } + + __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO); + + return 0; +} + +static struct pinmux_ops atlas7_pinmux_ops = { + .get_functions_count = atlas7_pmx_get_funcs_count, + .get_function_name = atlas7_pmx_get_func_name, + .get_function_groups = atlas7_pmx_get_func_groups, + .set_mux = atlas7_pmx_set_mux, + .gpio_request_enable = atlas7_pmx_gpio_request_enable, +}; + +static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->grps_cnt; +} + +static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + u32 group) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pmx->pctl_data->grps[group].name; +} + +static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + u32 group, const u32 **pins, u32 *num_pins) +{ + struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + *num_pins = pmx->pctl_data->grps[group].num_pins; + *pins = pmx->pctl_data->grps[group].pins; + + return 0; +} + +static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, + num_maps, PIN_MAP_TYPE_INVALID); +} + +static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops atlas7_pinctrl_ops = { + .get_groups_count = atlas7_pinctrl_get_groups_count, + .get_group_name = atlas7_pinctrl_get_group_name, + .get_group_pins = atlas7_pinctrl_get_group_pins, + .dt_node_to_map = atlas7_pinctrl_dt_node_to_map, + .dt_free_map = atlas7_pinctrl_dt_free_map, +}; + +static int atlas7_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *configs, + unsigned num_configs) +{ + u16 param, arg; + int idx, err; + + for (idx = 0; idx < num_configs; idx++) { + param = pinconf_to_config_param(configs[idx]); + arg = pinconf_to_config_argument(configs[idx]); + + pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n", + pin, atlas7_ioc_pads[pin].name, param, arg); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, PULL_UP); + if (err) + return err; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, PULL_DOWN); + if (err) + return err; + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, HIGH_HYSTERESIS); + if (err) + return err; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + err = altas7_pinctrl_set_pull_sel(pctldev, + pin, HIGH_Z); + if (err) + return err; + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + err = altas7_pinctrl_set_drive_strength_sel(pctldev, + pin, arg); + if (err) + return err; + break; + default: + return -ENOTSUPP; + } + pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n", + pin, atlas7_ioc_pads[pin].name, param, arg); + } + + return 0; +} + +static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *configs, + unsigned num_configs) +{ + const unsigned *pins; + unsigned npins; + int i, ret; + + ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + for (i = 0; i < npins; i++) { + if (atlas7_pin_config_set(pctldev, pins[i], + configs, num_configs)) + return -ENOTSUPP; + } + return 0; +} + +static const struct pinconf_ops atlas7_pinconf_ops = { + .pin_config_set = atlas7_pin_config_set, + .pin_config_group_set = atlas7_pin_config_group_set, + .is_generic = true, +}; + +static int atlas7_pinmux_probe(struct platform_device *pdev) +{ + int ret, idx; + struct atlas7_pmx *pmx; + struct device_node *np = pdev->dev.of_node; + u32 banks = ATLAS7_PINCTRL_REG_BANKS; + + /* Create state holders etc for this driver */ + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->dev = &pdev->dev; + + pmx->pctl_data = &atlas7_ioc_data; + pmx->pctl_desc.name = "pinctrl-atlas7"; + pmx->pctl_desc.pins = pmx->pctl_data->pads; + pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt; + pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops; + pmx->pctl_desc.pmxops = &atlas7_pinmux_ops; + pmx->pctl_desc.confops = &atlas7_pinconf_ops; + pmx->pctl_desc.owner = THIS_MODULE; + + for (idx = 0; idx < banks; idx++) { + pmx->regs[idx] = of_iomap(np, idx); + if (!pmx->regs[idx]) { + dev_err(&pdev->dev, + "can't map ioc bank#%d registers\n", idx); + ret = -ENOMEM; + goto unmap_io; + } + } + + /* Now register the pin controller and all pins it handles */ + pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx); + if (!pmx->pctl) { + dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n"); + ret = -EINVAL; + goto unmap_io; + } + + platform_set_drvdata(pdev, pmx); + + dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n"); + + return 0; + +unmap_io: + for (idx = 0; idx < banks; idx++) { + if (!pmx->regs[idx]) + break; + iounmap(pmx->regs[idx]); + } + + return ret; +} + +static const struct of_device_id atlas7_pinmux_ids[] = { + { .compatible = "sirf,atlas7-ioc",}, +}; + +static struct platform_driver atlas7_pinmux_driver = { + .driver = { + .name = "atlas7-ioc", + .owner = THIS_MODULE, + .of_match_table = atlas7_pinmux_ids, + }, + .probe = atlas7_pinmux_probe, +}; + +static int __init atlas7_pinmux_init(void) +{ + return platform_driver_register(&atlas7_pinmux_driver); +} +arch_initcall(atlas7_pinmux_init); + + +/** + * The Following is GPIO Code + */ +static inline struct +atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio) +{ + return &a7gc->banks[GPIO_TO_BANK(gpio)]; +} + +static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio) +{ + struct atlas7_gpio_bank *bank; + u32 ofs; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + ofs = gpio - bank->gpio_offset; + if (ofs >= bank->ngpio) + return -ENODEV; + + return bank->gpio_pins[ofs]; +} + +static void atlas7_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, d->hwirq); + pin_in_bank = d->hwirq - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ctrl_reg); + /* clear interrupt status */ + writel(val, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx) +{ + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + + bank = atlas7_gpio_to_bank(a7gc, idx); + pin_in_bank = idx - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + val = readl(ctrl_reg); + val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK | + ATLAS7_GPIO_CTL_INTR_STATUS_MASK); + writel(val, ctrl_reg); +} + +static void atlas7_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_irq_mask(a7gc, d->hwirq); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static void atlas7_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, d->hwirq); + pin_in_bank = d->hwirq - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ctrl_reg); + val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK; + val |= ATLAS7_GPIO_CTL_INTR_EN_MASK; + writel(val, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static int atlas7_gpio_irq_type(struct irq_data *d, + unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, d->hwirq); + pin_in_bank = d->hwirq - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ctrl_reg); + val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK | + ATLAS7_GPIO_CTL_INTR_EN_MASK); + + switch (type) { + case IRQ_TYPE_NONE: + break; + + case IRQ_TYPE_EDGE_RISING: + val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK; + val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK; + break; + + case IRQ_TYPE_EDGE_FALLING: + val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK; + val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK; + break; + + case IRQ_TYPE_EDGE_BOTH: + val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK | + ATLAS7_GPIO_CTL_INTR_LOW_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK; + break; + + case IRQ_TYPE_LEVEL_LOW: + val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK); + val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK; + break; + + case IRQ_TYPE_LEVEL_HIGH: + val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK; + val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK | + ATLAS7_GPIO_CTL_INTR_TYPE_MASK); + break; + } + + writel(val, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static struct irq_chip atlas7_gpio_irq_chip = { + .name = "atlas7-gpio-irq", + .irq_ack = atlas7_gpio_irq_ack, + .irq_mask = atlas7_gpio_irq_mask, + .irq_unmask = atlas7_gpio_irq_unmask, + .irq_set_type = atlas7_gpio_irq_type, +}; + +static void atlas7_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); + struct atlas7_gpio_bank *bank = NULL; + u32 status, ctrl; + int pin_in_bank = 0, idx; + struct irq_chip *chip = irq_get_chip(irq); + + for (idx = 0; idx < a7gc->nbank; idx++) { + bank = &a7gc->banks[idx]; + if (bank->irq == irq) + break; + } + BUG_ON(idx == a7gc->nbank); + + chained_irq_enter(chip, desc); + + status = readl(ATLAS7_GPIO_INT_STATUS(bank)); + if (!status) { + pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n", + __func__, gc->label, status); + handle_bad_irq(irq, desc); + return; + } + + while (status) { + ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); + + /* + * Here we must check whether the corresponding GPIO's + * interrupt has been enabled, otherwise just skip it + */ + if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) { + pr_debug("%s: chip[%s] gpio:%d happens\n", + __func__, gc->label, + bank->gpio_offset + pin_in_bank); + generic_handle_irq( + irq_find_mapping(gc->irqdomain, + bank->gpio_offset + pin_in_bank)); + } + + if (++pin_in_bank >= bank->ngpio) + break; + + status = status >> 1; + } + + chained_irq_exit(chip, desc); +} + +static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc, + unsigned int gpio) +{ + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 val, pin_in_bank; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + val = readl(ctrl_reg); + val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK; + writel(val, ctrl_reg); +} + +static int atlas7_gpio_request(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + int ret; + unsigned long flags; + + ret = __atlas7_gpio_to_pin(a7gc, gpio); + if (ret < 0) + return ret; + + if (pinctrl_request_gpio(chip->base + gpio)) + return -ENODEV; + + spin_lock_irqsave(&a7gc->lock, flags); + + /* + * default status: + * set direction as input and mask irq + */ + __atlas7_gpio_set_input(a7gc, gpio); + __atlas7_gpio_irq_mask(a7gc, gpio); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static void atlas7_gpio_free(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_irq_mask(a7gc, gpio); + __atlas7_gpio_set_input(a7gc, gpio); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + pinctrl_free_gpio(chip->base + gpio); +} + +static int atlas7_gpio_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_set_input(a7gc, gpio); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc, + unsigned int gpio, int value) +{ + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 out_ctrl, pin_in_bank; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + out_ctrl = readl(ctrl_reg); + if (value) + out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK; + else + out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK; + + out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK; + out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK; + writel(out_ctrl, ctrl_reg); +} + +static int atlas7_gpio_direction_output(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + unsigned long flags; + + spin_lock_irqsave(&a7gc->lock, flags); + + __atlas7_gpio_set_output(a7gc, gpio, value); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return 0; +} + +static int atlas7_gpio_get_value(struct gpio_chip *chip, + unsigned int gpio) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + struct atlas7_gpio_bank *bank; + u32 val, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + + spin_lock_irqsave(&a7gc->lock, flags); + + val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); + + spin_unlock_irqrestore(&a7gc->lock, flags); + + return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK); +} + +static void atlas7_gpio_set_value(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip); + struct atlas7_gpio_bank *bank; + void __iomem *ctrl_reg; + u32 ctrl, pin_in_bank; + unsigned long flags; + + bank = atlas7_gpio_to_bank(a7gc, gpio); + pin_in_bank = gpio - bank->gpio_offset; + ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); + + spin_lock_irqsave(&a7gc->lock, flags); + + ctrl = readl(ctrl_reg); + if (value) + ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK; + else + ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK; + writel(ctrl, ctrl_reg); + + spin_unlock_irqrestore(&a7gc->lock, flags); +} + +static const struct of_device_id atlas7_gpio_ids[] = { + { .compatible = "sirf,atlas7-gpio", }, +}; + +static int atlas7_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct atlas7_gpio_chip *a7gc; + struct gpio_chip *chip; + u32 nbank; + int ret, idx; + + ret = of_property_read_u32(np, "gpio-banks", &nbank); + if (ret) { + dev_err(&pdev->dev, + "Could not find GPIO bank info,ret=%d!\n", + ret); + return ret; + } + + /* retrieve gpio descriptor data */ + a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) + + sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL); + if (!a7gc) + return -ENOMEM; + + /* Get Gpio clk */ + a7gc->clk = of_clk_get(np, 0); + if (!IS_ERR(a7gc->clk)) { + ret = clk_prepare_enable(a7gc->clk); + if (ret) { + dev_err(&pdev->dev, + "Could not enable clock!\n"); + return ret; + } + } + + /* Get Gpio Registers */ + a7gc->reg = of_iomap(np, 0); + if (!a7gc->reg) { + dev_err(&pdev->dev, "Could not map GPIO Registers!\n"); + return -ENOMEM; + } + + a7gc->nbank = nbank; + spin_lock_init(&a7gc->lock); + + /* Setup GPIO Chip */ + chip = &a7gc->chip; + chip->request = atlas7_gpio_request; + chip->free = atlas7_gpio_free; + chip->direction_input = atlas7_gpio_direction_input; + chip->get = atlas7_gpio_get_value; + chip->direction_output = atlas7_gpio_direction_output; + chip->set = atlas7_gpio_set_value; + chip->base = -1; + /* Each chip can support 32 pins at one bank */ + chip->ngpio = NGPIO_OF_BANK * nbank; + chip->label = kstrdup(np->name, GFP_KERNEL); + chip->of_node = np; + chip->of_gpio_n_cells = 2; + chip->dev = &pdev->dev; + + /* Add gpio chip to system */ + ret = gpiochip_add(chip); + if (ret) { + dev_err(&pdev->dev, + "%s: error in probe function with status %d\n", + np->name, ret); + goto failed; + } + + /* Add gpio chip to irq subsystem */ + ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip, + 0, handle_level_irq, IRQ_TYPE_NONE); + if (ret) { + dev_err(&pdev->dev, + "could not connect irqchip to gpiochip\n"); + goto failed; + } + + for (idx = 0; idx < nbank; idx++) { + struct gpio_pin_range *pin_range; + struct atlas7_gpio_bank *bank; + + bank = &a7gc->banks[idx]; + /* Set ctrl registers' base of this bank */ + bank->base = ATLAS7_GPIO_BASE(a7gc, idx); + + /* Get interrupt number from DTS */ + ret = of_irq_get(np, idx); + if (ret == -EPROBE_DEFER) { + dev_err(&pdev->dev, + "Unable to find IRQ number. ret=%d\n", ret); + goto failed; + } + bank->irq = ret; + + gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip, + bank->irq, atlas7_gpio_handle_irq); + + /* Records gpio_pin_range to a7gc */ + list_for_each_entry(pin_range, &chip->pin_ranges, node) { + struct pinctrl_gpio_range *range; + + range = &pin_range->range; + if (range->id == NGPIO_OF_BANK * idx) { + bank->gpio_offset = range->id; + bank->ngpio = range->npins; + bank->gpio_pins = range->pins; + bank->pctldev = pin_range->pctldev; + break; + } + } + + BUG_ON(!bank->pctldev); + } + + dev_info(&pdev->dev, "add to system.\n"); + return 0; +failed: + return ret; +} + +static struct platform_driver atlas7_gpio_driver = { + .driver = { + .name = "atlas7-gpio", + .owner = THIS_MODULE, + .of_match_table = atlas7_gpio_ids, + }, + .probe = atlas7_gpio_probe, +}; + +static int __init atlas7_gpio_init(void) +{ + return platform_driver_register(&atlas7_gpio_driver); +} +subsys_initcall(atlas7_gpio_init); + +MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From edc90b7dc4ceef62ef0ad9cc6c3f5dc770e83ad2 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Mon, 11 May 2015 22:55:21 +0800 Subject: KVM: MMU: fix SMAP virtualization KVM may turn a user page to a kernel page when kernel writes a readonly user page if CR0.WP = 1. This shadow page entry will be reused after SMAP is enabled so that kernel is allowed to access this user page Fix it by setting SMAP && !CR0.WP into shadow page's role and reset mmu once CR4.SMAP is updated Signed-off-by: Xiao Guangrong Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/mmu.txt | 18 ++++++++++++++---- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/mmu.c | 16 ++++++++++++---- arch/x86/kvm/mmu.h | 2 -- arch/x86/kvm/x86.c | 8 +++----- 5 files changed, 30 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/virtual/kvm/mmu.txt b/Documentation/virtual/kvm/mmu.txt index 53838d9c6295..c59bd9bc41ef 100644 --- a/Documentation/virtual/kvm/mmu.txt +++ b/Documentation/virtual/kvm/mmu.txt @@ -169,6 +169,10 @@ Shadow pages contain the following information: Contains the value of cr4.smep && !cr0.wp for which the page is valid (pages for which this is true are different from other pages; see the treatment of cr0.wp=0 below). + role.smap_andnot_wp: + Contains the value of cr4.smap && !cr0.wp for which the page is valid + (pages for which this is true are different from other pages; see the + treatment of cr0.wp=0 below). gfn: Either the guest page table containing the translations shadowed by this page, or the base page frame for linear translations. See role.direct. @@ -344,10 +348,16 @@ on fault type: (user write faults generate a #PF) -In the first case there is an additional complication if CR4.SMEP is -enabled: since we've turned the page into a kernel page, the kernel may now -execute it. We handle this by also setting spte.nx. If we get a user -fetch or read fault, we'll change spte.u=1 and spte.nx=gpte.nx back. +In the first case there are two additional complications: +- if CR4.SMEP is enabled: since we've turned the page into a kernel page, + the kernel may now execute it. We handle this by also setting spte.nx. + If we get a user fetch or read fault, we'll change spte.u=1 and + spte.nx=gpte.nx back. +- if CR4.SMAP is disabled: since the page has been changed to a kernel + page, it can not be reused when CR4.SMAP is enabled. We set + CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note, + here we do not care the case that CR4.SMAP is enabled since KVM will + directly inject #PF to guest due to failed permission check. To prevent an spte that was converted into a kernel page with cr0.wp=0 from being written by the kernel after cr0.wp has changed to 1, we make diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 8b661d1946b5..bbb8f4e7738a 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -207,6 +207,7 @@ union kvm_mmu_page_role { unsigned nxe:1; unsigned cr0_wp:1; unsigned smep_andnot_wp:1; + unsigned smap_andnot_wp:1; }; }; diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 209fe1477465..44a7d2515497 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -3736,8 +3736,8 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, } } -void update_permission_bitmask(struct kvm_vcpu *vcpu, - struct kvm_mmu *mmu, bool ept) +static void update_permission_bitmask(struct kvm_vcpu *vcpu, + struct kvm_mmu *mmu, bool ept) { unsigned bit, byte, pfec; u8 map; @@ -3918,6 +3918,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) { bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); + bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); struct kvm_mmu *context = &vcpu->arch.mmu; MMU_WARN_ON(VALID_PAGE(context->root_hpa)); @@ -3936,6 +3937,8 @@ void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) context->base_role.cr0_wp = is_write_protection(vcpu); context->base_role.smep_andnot_wp = smep && !is_write_protection(vcpu); + context->base_role.smap_andnot_wp + = smap && !is_write_protection(vcpu); } EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); @@ -4207,12 +4210,18 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new, int bytes) { gfn_t gfn = gpa >> PAGE_SHIFT; - union kvm_mmu_page_role mask = { .word = 0 }; struct kvm_mmu_page *sp; LIST_HEAD(invalid_list); u64 entry, gentry, *spte; int npte; bool remote_flush, local_flush, zap_page; + union kvm_mmu_page_role mask = (union kvm_mmu_page_role) { + .cr0_wp = 1, + .cr4_pae = 1, + .nxe = 1, + .smep_andnot_wp = 1, + .smap_andnot_wp = 1, + }; /* * If we don't have indirect shadow pages, it means no page is @@ -4238,7 +4247,6 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, ++vcpu->kvm->stat.mmu_pte_write; kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); - mask.cr0_wp = mask.cr4_pae = mask.nxe = mask.smep_andnot_wp = 1; for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { if (detect_write_misaligned(sp, gpa, bytes) || detect_write_flooding(sp)) { diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 06eb2fc1bab8..0ada65ecddcf 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -71,8 +71,6 @@ enum { int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct); void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu); void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly); -void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, - bool ept); static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm) { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cdccbe1749a5..cde5d614ff0a 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -702,8 +702,9 @@ EXPORT_SYMBOL_GPL(kvm_set_xcr); int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) { unsigned long old_cr4 = kvm_read_cr4(vcpu); - unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | - X86_CR4_PAE | X86_CR4_SMEP; + unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | + X86_CR4_SMEP | X86_CR4_SMAP; + if (cr4 & CR4_RESERVED_BITS) return 1; @@ -744,9 +745,6 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) kvm_mmu_reset_context(vcpu); - if ((cr4 ^ old_cr4) & X86_CR4_SMAP) - update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); - if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) kvm_update_cpuid(vcpu); -- cgit v1.2.3 From 492135557dc090a1abb2cfbe1a412757e3ed68ab Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Tue, 19 May 2015 21:04:22 +0200 Subject: tcp: add rfc3168, section 6.1.1.1. fallback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This work as a follow-up of commit f7b3bec6f516 ("net: allow setting ecn via routing table") and adds RFC3168 section 6.1.1.1. fallback for outgoing ECN connections. In other words, this work adds a retry with a non-ECN setup SYN packet, as suggested from the RFC on the first timeout: [...] A host that receives no reply to an ECN-setup SYN within the normal SYN retransmission timeout interval MAY resend the SYN and any subsequent SYN retransmissions with CWR and ECE cleared. [...] Schematic client-side view when assuming the server is in tcp_ecn=2 mode, that is, Linux default since 2009 via commit 255cac91c3c9 ("tcp: extend ECN sysctl to allow server-side only ECN"): 1) Normal ECN-capable path: SYN ECE CWR -----> <----- SYN ACK ECE ACK -----> 2) Path with broken middlebox, when client has fallback: SYN ECE CWR ----X crappy middlebox drops packet (timeout, rtx) SYN -----> <----- SYN ACK ACK -----> In case we would not have the fallback implemented, the middlebox drop point would basically end up as: SYN ECE CWR ----X crappy middlebox drops packet (timeout, rtx) SYN ECE CWR ----X crappy middlebox drops packet (timeout, rtx) SYN ECE CWR ----X crappy middlebox drops packet (timeout, rtx) In any case, it's rather a smaller percentage of sites where there would occur such additional setup latency: it was found in end of 2014 that ~56% of IPv4 and 65% of IPv6 servers of Alexa 1 million list would negotiate ECN (aka tcp_ecn=2 default), 0.42% of these webservers will fail to connect when trying to negotiate with ECN (tcp_ecn=1) due to timeouts, which the fallback would mitigate with a slight latency trade-off. Recent related paper on this topic: Brian Trammell, Mirja Kühlewind, Damiano Boppart, Iain Learmonth, Gorry Fairhurst, and Richard Scheffenegger: "Enabling Internet-Wide Deployment of Explicit Congestion Notification." Proc. PAM 2015, New York. http://ecn.ethz.ch/ecn-pam15.pdf Thus, when net.ipv4.tcp_ecn=1 is being set, the patch will perform RFC3168, section 6.1.1.1. fallback on timeout. For users explicitly not wanting this which can be in DC use case, we add a net.ipv4.tcp_ecn_fallback knob that allows for disabling the fallback. tp->ecn_flags are not being cleared in tcp_ecn_clear_syn() on output, but rather we let tcp_ecn_rcv_synack() take that over on input path in case a SYN ACK ECE was delayed. Thus a spurious SYN retransmission will not prevent ECN being negotiated eventually in that case. Reference: https://www.ietf.org/proceedings/92/slides/slides-92-iccrg-1.pdf Reference: https://www.ietf.org/proceedings/89/slides/slides-89-tsvarea-1.pdf Signed-off-by: Daniel Borkmann Signed-off-by: Florian Westphal Signed-off-by: Mirja Kühlewind Signed-off-by: Brian Trammell Cc: Eric Dumazet Cc: Dave That Acked-by: Eric Dumazet Signed-off-by: David S. Miller --- Documentation/networking/dctcp.txt | 1 + Documentation/networking/ip-sysctl.txt | 9 +++++++++ include/net/netns/ipv4.h | 2 ++ include/net/tcp.h | 2 ++ net/ipv4/sysctl_net_ipv4.c | 7 +++++++ net/ipv4/tcp_ipv4.c | 5 ++++- net/ipv4/tcp_output.c | 13 +++++++++++++ 7 files changed, 38 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/networking/dctcp.txt b/Documentation/networking/dctcp.txt index 0d5dfbc89ec9..13a857753208 100644 --- a/Documentation/networking/dctcp.txt +++ b/Documentation/networking/dctcp.txt @@ -8,6 +8,7 @@ the data center network to provide multi-bit feedback to the end hosts. To enable it on end hosts: sysctl -w net.ipv4.tcp_congestion_control=dctcp + sysctl -w net.ipv4.tcp_ecn_fallback=0 (optional) All switches in the data center network running DCTCP must support ECN marking and be configured for marking when reaching defined switch buffer diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 5095c63e50ed..cb083e0d682c 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -267,6 +267,15 @@ tcp_ecn - INTEGER but do not request ECN on outgoing connections. Default: 2 +tcp_ecn_fallback - BOOLEAN + If the kernel detects that ECN connection misbehaves, enable fall + back to non-ECN. Currently, this knob implements the fallback + from RFC3168, section 6.1.1.1., but we reserve that in future, + additional detection mechanisms could be implemented under this + knob. The value is not used, if tcp_ecn or per route (or congestion + control) ECN settings are disabled. + Default: 1 (fallback enabled) + tcp_fack - BOOLEAN Enable FACK congestion avoidance and fast retransmission. The value is not used, if tcp_sack is not enabled. diff --git a/include/net/netns/ipv4.h b/include/net/netns/ipv4.h index 614a49be68a9..6848b8bb2e63 100644 --- a/include/net/netns/ipv4.h +++ b/include/net/netns/ipv4.h @@ -77,6 +77,8 @@ struct netns_ipv4 { struct local_ports ip_local_ports; int sysctl_tcp_ecn; + int sysctl_tcp_ecn_fallback; + int sysctl_ip_no_pmtu_disc; int sysctl_ip_fwd_use_pmtu; int sysctl_ip_nonlocal_bind; diff --git a/include/net/tcp.h b/include/net/tcp.h index 0d85223efa4c..2bb2bad21d5c 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -712,6 +712,8 @@ static inline u32 tcp_skb_timestamp(const struct sk_buff *skb) #define TCPHDR_ECE 0x40 #define TCPHDR_CWR 0x80 +#define TCPHDR_SYN_ECN (TCPHDR_SYN | TCPHDR_ECE | TCPHDR_CWR) + /* This is what the send packet queuing engine uses to pass * TCP per-packet control information to the transmission code. * We also store the host-order sequence numbers in here too. diff --git a/net/ipv4/sysctl_net_ipv4.c b/net/ipv4/sysctl_net_ipv4.c index c3852a7ff3c7..841de32f1fee 100644 --- a/net/ipv4/sysctl_net_ipv4.c +++ b/net/ipv4/sysctl_net_ipv4.c @@ -820,6 +820,13 @@ static struct ctl_table ipv4_net_table[] = { .mode = 0644, .proc_handler = proc_dointvec }, + { + .procname = "tcp_ecn_fallback", + .data = &init_net.ipv4.sysctl_tcp_ecn_fallback, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec + }, { .procname = "ip_local_port_range", .maxlen = sizeof(init_net.ipv4.ip_local_ports.range), diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 91cb4768a860..0cc4b5a630cd 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -2411,12 +2411,15 @@ static int __net_init tcp_sk_init(struct net *net) goto fail; *per_cpu_ptr(net->ipv4.tcp_sk, cpu) = sk; } + net->ipv4.sysctl_tcp_ecn = 2; + net->ipv4.sysctl_tcp_ecn_fallback = 1; + net->ipv4.sysctl_tcp_base_mss = TCP_BASE_MSS; net->ipv4.sysctl_tcp_probe_threshold = TCP_PROBE_THRESHOLD; net->ipv4.sysctl_tcp_probe_interval = TCP_PROBE_INTERVAL; - return 0; + return 0; fail: tcp_sk_exit(net); diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 08c2cc40b26d..e29d43b5a0bb 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -350,6 +350,15 @@ static void tcp_ecn_send_syn(struct sock *sk, struct sk_buff *skb) } } +static void tcp_ecn_clear_syn(struct sock *sk, struct sk_buff *skb) +{ + if (sock_net(sk)->ipv4.sysctl_tcp_ecn_fallback) + /* tp->ecn_flags are cleared at a later point in time when + * SYN ACK is ultimatively being received. + */ + TCP_SKB_CB(skb)->tcp_flags &= ~(TCPHDR_ECE | TCPHDR_CWR); +} + static void tcp_ecn_make_synack(const struct request_sock *req, struct tcphdr *th, struct sock *sk) @@ -2615,6 +2624,10 @@ int __tcp_retransmit_skb(struct sock *sk, struct sk_buff *skb) } } + /* RFC3168, section 6.1.1.1. ECN fallback */ + if ((TCP_SKB_CB(skb)->tcp_flags & TCPHDR_SYN_ECN) == TCPHDR_SYN_ECN) + tcp_ecn_clear_syn(sk, skb); + tcp_retrans_try_collapse(sk, skb, cur_mss); /* Make a copy, if the first transmission SKB clone we made -- cgit v1.2.3 From f2411da746985e60d4d087f3a43e271c61785927 Mon Sep 17 00:00:00 2001 From: "Luis R. Rodriguez" Date: Mon, 30 Mar 2015 16:20:05 -0700 Subject: driver-core: add driver module asynchronous probe support Some init systems may wish to express the desire to have device drivers run their probe() code asynchronously. This implements support for this and allows userspace to request async probe as a preference through a generic shared device driver module parameter, async_probe. Implementation for async probe is supported through a module parameter given that since synchronous probe has been prevalent for years some userspace might exist which relies on the fact that the device driver will probe synchronously and the assumption that devices it provides will be immediately available after this. Signed-off-by: Luis R. Rodriguez Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- Documentation/kernel-parameters.txt | 3 +++ drivers/base/dd.c | 8 +++++++- include/linux/device.h | 8 +++++--- include/linux/module.h | 2 ++ kernel/module.c | 12 ++++++++++-- 5 files changed, 27 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..e89fdd5aa605 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -943,6 +943,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. auto selects the default scheme, which automatically enables eagerfpu restore for xsaveopt. + module.async_probe [KNL] + Enable asynchronous probe on this module. + early_ioremap_debug [KNL] Enable debug messages in early_ioremap support. This is useful for tracking down temporary early mappings diff --git a/drivers/base/dd.c b/drivers/base/dd.c index 2ad33b21888c..7a2fa5dcead7 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -419,7 +419,13 @@ int driver_probe_device(struct device_driver *drv, struct device *dev) bool driver_allows_async_probing(struct device_driver *drv) { - return drv->probe_type == PROBE_PREFER_ASYNCHRONOUS; + if (drv->probe_type == PROBE_PREFER_ASYNCHRONOUS) + return true; + + if (drv->owner && drv->owner->async_probe_requested) + return true; + + return false; } struct device_attach_data { diff --git a/include/linux/device.h b/include/linux/device.h index 7857b46c548b..77b7cd9e5467 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -201,10 +201,12 @@ extern struct klist *bus_get_device_klist(struct bus_type *bus); * respective probe routines. This tells the core what to * expect and prefer. * - * @PROBE_SYNCHRONOUS: Default. Drivers expect their probe routines + * @PROBE_DEFAULT_STRATEGY: Drivers expect their probe routines * to run synchronously with driver and device registration * (with the exception of -EPROBE_DEFER handling - re-probing - * always ends up being done asynchronously). + * always ends up being done asynchronously) unless user + * explicitly requested asynchronous probing via module + * parameter. * @PROBE_PREFER_ASYNCHRONOUS: Drivers for "slow" devices which * probing order is not essential for booting the system may * opt into executing their probes asynchronously. @@ -216,7 +218,7 @@ extern struct klist *bus_get_device_klist(struct bus_type *bus); * drivers. */ enum probe_type { - PROBE_SYNCHRONOUS, + PROBE_DEFAULT_STRATEGY, PROBE_PREFER_ASYNCHRONOUS, }; diff --git a/include/linux/module.h b/include/linux/module.h index c883b86ea964..f46a47d3c0dc 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -257,6 +257,8 @@ struct module { bool sig_ok; #endif + bool async_probe_requested; + /* symbols that will be GPL-only in the near future. */ const struct kernel_symbol *gpl_future_syms; const unsigned long *gpl_future_crcs; diff --git a/kernel/module.c b/kernel/module.c index 24d1f31d02f2..ea941bc327d5 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -3107,7 +3107,7 @@ static noinline int do_init_module(struct module *mod) * * http://thread.gmane.org/gmane.linux.kernel/1420814 */ - if (current->flags & PF_USED_ASYNC) + if (!mod->async_probe_requested && (current->flags & PF_USED_ASYNC)) async_synchronize_full(); mutex_lock(&module_mutex); @@ -3240,8 +3240,16 @@ out: static int unknown_module_param_cb(char *param, char *val, const char *modname, void *arg) { + struct module *mod = arg; + int ret; + + if (strcmp(param, "async_probe") == 0) { + mod->async_probe_requested = true; + return 0; + } + /* Check for magic 'dyndbg' arg */ - int ret = ddebug_dyndbg_module_param_cb(param, val, modname); + ret = ddebug_dyndbg_module_param_cb(param, val, modname); if (ret != 0) pr_warn("%s: unknown parameter '%s' ignored\n", modname, param); return 0; -- cgit v1.2.3 From 0506b2986c0971a987d7c63ac728f39c722f358a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 16 Mar 2015 21:04:06 +0100 Subject: ARM: at91: declare the at91rm9200 memory controller as a syscon The at91rm9200 memory controller is not simply an SDRAM controller. It also controls the EBI (External Bus Interface), the SMC (Static Memory Controller)and the Burst Flash Controller. Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre --- Documentation/devicetree/bindings/arm/atmel-at91.txt | 2 +- arch/arm/boot/dts/at91rm9200.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 2e99b5b57350..424ac8cbfa08 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -98,7 +98,7 @@ Example: }; RAMC SDRAM/DDR Controller required properties: -- compatible: Should be "atmel,at91rm9200-sdramc", +- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 4fb333bd1f85..6d0fa9b87f46 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -92,7 +92,7 @@ }; ramc0: ramc@ffffff00 { - compatible = "atmel,at91rm9200-sdramc"; + compatible = "atmel,at91rm9200-sdramc", "syscon"; reg = <0xffffff00 0x100>; }; -- cgit v1.2.3 From 17e484686be2e9ecb88cc7913a4baaf6783275e3 Mon Sep 17 00:00:00 2001 From: "jean-michel.hautbois@vodalys.com" Date: Wed, 18 Mar 2015 07:21:47 -0300 Subject: [media] v4l2-subdev: allow subdev to send an event to the v4l2_device notify function All drivers use custom notifications, in particular when source changes. The bridge only has to map the subdev that sends it to whatever video node it is connected to. Signed-off-by: Jean-Michel Hautbois Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/v4l2-framework.txt | 4 ++++ include/media/v4l2-subdev.h | 2 ++ 2 files changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/video4linux/v4l2-framework.txt b/Documentation/video4linux/v4l2-framework.txt index 59e619f9bbf5..75d5c18d689a 100644 --- a/Documentation/video4linux/v4l2-framework.txt +++ b/Documentation/video4linux/v4l2-framework.txt @@ -1129,6 +1129,10 @@ available event type is 'class base + 1'. An example on how the V4L2 events may be used can be found in the OMAP 3 ISP driver (drivers/media/platform/omap3isp). +A subdev can directly send an event to the v4l2_device notify function with +V4L2_DEVICE_NOTIFY_EVENT. This allows the bridge to map the subdev that sends +the event to the video node(s) associated with the subdev that need to be +informed about such an event. V4L2 clocks ----------- diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index 8f5da73dacff..dc20102ff600 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -40,6 +40,8 @@ #define V4L2_SUBDEV_IR_TX_NOTIFY _IOW('v', 1, u32) #define V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ 0x00000001 +#define V4L2_DEVICE_NOTIFY_EVENT _IOW('v', 2, struct v4l2_event) + struct v4l2_device; struct v4l2_ctrl_handler; struct v4l2_event_subscription; -- cgit v1.2.3 From e3fb57c83239c84ca06ed5b06eb224db3e48d17e Mon Sep 17 00:00:00 2001 From: Qipan Li Date: Tue, 19 May 2015 14:41:12 +0000 Subject: spi: sirf: add support for USP-based SPI USP is a general purpose serial port in SiRFSoC, which can work as SPI. the most data flow of USP and pure SPI is same with main differences in registers layout. this patch moves registers layout to private data, and use flags to differentiate other minor differences between prima2-spi, prima2-usp and atlas7-usp for hardware configuration. Signed-off-by: Qipan Li Signed-off-by: Barry Song Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-sirf.txt | 3 +- drivers/spi/spi-sirf.c | 792 +++++++++++++++------ 2 files changed, 586 insertions(+), 209 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-sirf.txt b/Documentation/devicetree/bindings/spi/spi-sirf.txt index 4c7adb8f777c..ddd78ff68fae 100644 --- a/Documentation/devicetree/bindings/spi/spi-sirf.txt +++ b/Documentation/devicetree/bindings/spi/spi-sirf.txt @@ -1,7 +1,8 @@ * CSR SiRFprimaII Serial Peripheral Interface Required properties: -- compatible : Should be "sirf,prima2-spi" +- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp" + or "sirf,atlas7-usp" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI interrupt - resets: phandle to the reset controller asserting this device in diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c index ae4bd1154141..dd87ba6fddab 100644 --- a/drivers/spi/spi-sirf.c +++ b/drivers/spi/spi-sirf.c @@ -26,28 +26,6 @@ #include #define DRIVER_NAME "sirfsoc_spi" - -#define SIRFSOC_SPI_CTRL 0x0000 -#define SIRFSOC_SPI_CMD 0x0004 -#define SIRFSOC_SPI_TX_RX_EN 0x0008 -#define SIRFSOC_SPI_INT_EN 0x000C -#define SIRFSOC_SPI_INT_STATUS 0x0010 -#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100 -#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104 -#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108 -#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C -#define SIRFSOC_SPI_TXFIFO_OP 0x0110 -#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114 -#define SIRFSOC_SPI_TXFIFO_DATA 0x0118 -#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120 -#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124 -#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128 -#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C -#define SIRFSOC_SPI_RXFIFO_OP 0x0130 -#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134 -#define SIRFSOC_SPI_RXFIFO_DATA 0x0138 -#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144 - /* SPI CTRL register defines */ #define SIRFSOC_SPI_SLV_MODE BIT(16) #define SIRFSOC_SPI_CMD_MODE BIT(17) @@ -80,8 +58,6 @@ #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9) #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10) -#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF - /* Interrupt status */ #define SIRFSOC_SPI_RX_DONE BIT(0) #define SIRFSOC_SPI_TX_DONE BIT(1) @@ -110,20 +86,66 @@ #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0) #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0) #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0) - -/* FIFO Status */ -#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF -#define SIRFSOC_SPI_FIFO_FULL BIT(8) -#define SIRFSOC_SPI_FIFO_EMPTY BIT(9) - -/* 256 bytes rx/tx FIFO */ -#define SIRFSOC_SPI_FIFO_SIZE 256 -#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024) - -#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F) -#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10) -#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20) -#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2) +/* USP related */ +#define SIRFSOC_USP_SYNC_MODE BIT(0) +#define SIRFSOC_USP_SLV_MODE BIT(1) +#define SIRFSOC_USP_LSB BIT(4) +#define SIRFSOC_USP_EN BIT(5) +#define SIRFSOC_USP_RXD_FALLING_EDGE BIT(6) +#define SIRFSOC_USP_TXD_FALLING_EDGE BIT(7) +#define SIRFSOC_USP_CS_HIGH_VALID BIT(9) +#define SIRFSOC_USP_SCLK_IDLE_STAT BIT(11) +#define SIRFSOC_USP_TFS_IO_MODE BIT(14) +#define SIRFSOC_USP_TFS_IO_INPUT BIT(19) + +#define SIRFSOC_USP_RXD_DELAY_LEN_MASK 0xFF +#define SIRFSOC_USP_TXD_DELAY_LEN_MASK 0xFF +#define SIRFSOC_USP_RXD_DELAY_OFFSET 0 +#define SIRFSOC_USP_TXD_DELAY_OFFSET 8 +#define SIRFSOC_USP_RXD_DELAY_LEN 1 +#define SIRFSOC_USP_TXD_DELAY_LEN 1 +#define SIRFSOC_USP_CLK_DIVISOR_OFFSET 21 +#define SIRFSOC_USP_CLK_DIVISOR_MASK 0x3FF +#define SIRFSOC_USP_CLK_10_11_MASK 0x3 +#define SIRFSOC_USP_CLK_10_11_OFFSET 30 +#define SIRFSOC_USP_CLK_12_15_MASK 0xF +#define SIRFSOC_USP_CLK_12_15_OFFSET 24 + +#define SIRFSOC_USP_TX_DATA_OFFSET 0 +#define SIRFSOC_USP_TX_SYNC_OFFSET 8 +#define SIRFSOC_USP_TX_FRAME_OFFSET 16 +#define SIRFSOC_USP_TX_SHIFTER_OFFSET 24 + +#define SIRFSOC_USP_TX_DATA_MASK 0xFF +#define SIRFSOC_USP_TX_SYNC_MASK 0xFF +#define SIRFSOC_USP_TX_FRAME_MASK 0xFF +#define SIRFSOC_USP_TX_SHIFTER_MASK 0x1F + +#define SIRFSOC_USP_RX_DATA_OFFSET 0 +#define SIRFSOC_USP_RX_FRAME_OFFSET 8 +#define SIRFSOC_USP_RX_SHIFTER_OFFSET 16 + +#define SIRFSOC_USP_RX_DATA_MASK 0xFF +#define SIRFSOC_USP_RX_FRAME_MASK 0xFF +#define SIRFSOC_USP_RX_SHIFTER_MASK 0x1F +#define SIRFSOC_USP_CS_HIGH_VALUE BIT(1) + +#define SIRFSOC_SPI_FIFO_SC_OFFSET 0 +#define SIRFSOC_SPI_FIFO_LC_OFFSET 10 +#define SIRFSOC_SPI_FIFO_HC_OFFSET 20 + +#define SIRFSOC_SPI_FIFO_FULL_MASK(s) (1 << ((s)->fifo_full_offset)) +#define SIRFSOC_SPI_FIFO_EMPTY_MASK(s) (1 << ((s)->fifo_full_offset + 1)) +#define SIRFSOC_SPI_FIFO_THD_MASK(s) ((s)->fifo_size - 1) +#define SIRFSOC_SPI_FIFO_THD_OFFSET 2 +#define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val) \ + ((val) & (s)->fifo_level_chk_mask) + +enum sirf_spi_type { + SIRF_REAL_SPI, + SIRF_USP_SPI_P2, + SIRF_USP_SPI_A7, +}; /* * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma @@ -137,6 +159,123 @@ #define SIRFSOC_MAX_CMD_BYTES 4 #define SIRFSOC_SPI_DEFAULT_FRQ 1000000 +struct sirf_spi_register { + /*SPI and USP-SPI common*/ + u32 tx_rx_en; + u32 int_en; + u32 int_st; + u32 tx_dma_io_ctrl; + u32 tx_dma_io_len; + u32 txfifo_ctrl; + u32 txfifo_level_chk; + u32 txfifo_op; + u32 txfifo_st; + u32 txfifo_data; + u32 rx_dma_io_ctrl; + u32 rx_dma_io_len; + u32 rxfifo_ctrl; + u32 rxfifo_level_chk; + u32 rxfifo_op; + u32 rxfifo_st; + u32 rxfifo_data; + /*SPI self*/ + u32 spi_ctrl; + u32 spi_cmd; + u32 spi_dummy_delay_ctrl; + /*USP-SPI self*/ + u32 usp_mode1; + u32 usp_mode2; + u32 usp_tx_frame_ctrl; + u32 usp_rx_frame_ctrl; + u32 usp_pin_io_data; + u32 usp_risc_dsp_mode; + u32 usp_async_param_reg; + u32 usp_irda_x_mode_div; + u32 usp_sm_cfg; + u32 usp_int_en_clr; +}; + +static const struct sirf_spi_register real_spi_register = { + .tx_rx_en = 0x8, + .int_en = 0xc, + .int_st = 0x10, + .tx_dma_io_ctrl = 0x100, + .tx_dma_io_len = 0x104, + .txfifo_ctrl = 0x108, + .txfifo_level_chk = 0x10c, + .txfifo_op = 0x110, + .txfifo_st = 0x114, + .txfifo_data = 0x118, + .rx_dma_io_ctrl = 0x120, + .rx_dma_io_len = 0x124, + .rxfifo_ctrl = 0x128, + .rxfifo_level_chk = 0x12c, + .rxfifo_op = 0x130, + .rxfifo_st = 0x134, + .rxfifo_data = 0x138, + .spi_ctrl = 0x0, + .spi_cmd = 0x4, + .spi_dummy_delay_ctrl = 0x144, +}; + +static const struct sirf_spi_register usp_spi_register = { + .tx_rx_en = 0x10, + .int_en = 0x14, + .int_st = 0x18, + .tx_dma_io_ctrl = 0x100, + .tx_dma_io_len = 0x104, + .txfifo_ctrl = 0x108, + .txfifo_level_chk = 0x10c, + .txfifo_op = 0x110, + .txfifo_st = 0x114, + .txfifo_data = 0x118, + .rx_dma_io_ctrl = 0x120, + .rx_dma_io_len = 0x124, + .rxfifo_ctrl = 0x128, + .rxfifo_level_chk = 0x12c, + .rxfifo_op = 0x130, + .rxfifo_st = 0x134, + .rxfifo_data = 0x138, + .usp_mode1 = 0x0, + .usp_mode2 = 0x4, + .usp_tx_frame_ctrl = 0x8, + .usp_rx_frame_ctrl = 0xc, + .usp_pin_io_data = 0x1c, + .usp_risc_dsp_mode = 0x20, + .usp_async_param_reg = 0x24, + .usp_irda_x_mode_div = 0x28, + .usp_sm_cfg = 0x2c, + .usp_int_en_clr = 0x140, +}; + +struct sirf_spi_comp_data { + const struct sirf_spi_register *regs; + enum sirf_spi_type type; + unsigned int dat_max_frm_len; + unsigned int fifo_size; +}; + +static const struct sirf_spi_comp_data sirf_real_spi = { + .regs = &real_spi_register, + .type = SIRF_REAL_SPI, + .dat_max_frm_len = 64 * 1024, + .fifo_size = 256, +}; + +static const struct sirf_spi_comp_data sirf_usp_spi_p2 = { + .regs = &usp_spi_register, + .type = SIRF_USP_SPI_P2, + .dat_max_frm_len = 1024 * 1024, + .fifo_size = 128, +}; + +static const struct sirf_spi_comp_data sirf_usp_spi_a7 = { + .regs = &usp_spi_register, + .type = SIRF_USP_SPI_A7, + .dat_max_frm_len = 1024 * 1024, + .fifo_size = 512, +}; + struct sirfsoc_spi { struct spi_bitbang bitbang; struct completion rx_done; @@ -173,6 +312,14 @@ struct sirfsoc_spi { */ bool tx_by_cmd; bool hw_cs; + enum sirf_spi_type type; + const struct sirf_spi_register *regs; + unsigned int fifo_size; + /* fifo empty offset is (fifo full offset + 1)*/ + unsigned int fifo_full_offset; + /* fifo_level_chk_mask is (fifo_size/4 - 1) */ + unsigned int fifo_level_chk_mask; + unsigned int dat_max_frm_len; }; static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) @@ -180,7 +327,7 @@ static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) u32 data; u8 *rx = sspi->rx; - data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); + data = readl(sspi->base + sspi->regs->rxfifo_data); if (rx) { *rx++ = (u8) data; @@ -199,8 +346,7 @@ static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi) data = *tx++; sspi->tx = tx; } - - writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); + writel(data, sspi->base + sspi->regs->txfifo_data); sspi->left_tx_word--; } @@ -209,7 +355,7 @@ static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi) u32 data; u16 *rx = sspi->rx; - data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); + data = readl(sspi->base + sspi->regs->rxfifo_data); if (rx) { *rx++ = (u16) data; @@ -229,7 +375,7 @@ static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi) sspi->tx = tx; } - writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); + writel(data, sspi->base + sspi->regs->txfifo_data); sspi->left_tx_word--; } @@ -238,7 +384,7 @@ static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi) u32 data; u32 *rx = sspi->rx; - data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); + data = readl(sspi->base + sspi->regs->rxfifo_data); if (rx) { *rx++ = (u32) data; @@ -259,41 +405,59 @@ static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi) sspi->tx = tx; } - writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); + writel(data, sspi->base + sspi->regs->txfifo_data); sspi->left_tx_word--; } static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id) { struct sirfsoc_spi *sspi = dev_id; - u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); - if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) { + u32 spi_stat; + + spi_stat = readl(sspi->base + sspi->regs->int_st); + if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI + && (spi_stat & SIRFSOC_SPI_FRM_END)) { complete(&sspi->tx_done); - writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); - writel(SIRFSOC_SPI_INT_MASK_ALL, - sspi->base + SIRFSOC_SPI_INT_STATUS); + writel(0x0, sspi->base + sspi->regs->int_en); + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); return IRQ_HANDLED; } - /* Error Conditions */ if (spi_stat & SIRFSOC_SPI_RX_OFLOW || spi_stat & SIRFSOC_SPI_TX_UFLOW) { complete(&sspi->tx_done); complete(&sspi->rx_done); - writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); - writel(SIRFSOC_SPI_INT_MASK_ALL, - sspi->base + SIRFSOC_SPI_INT_STATUS); + switch (sspi->type) { + case SIRF_REAL_SPI: + case SIRF_USP_SPI_P2: + writel(0x0, sspi->base + sspi->regs->int_en); + break; + case SIRF_USP_SPI_A7: + writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); + break; + } + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); return IRQ_HANDLED; } if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY) complete(&sspi->tx_done); - while (!(readl(sspi->base + SIRFSOC_SPI_INT_STATUS) & + while (!(readl(sspi->base + sspi->regs->int_st) & SIRFSOC_SPI_RX_IO_DMA)) cpu_relax(); complete(&sspi->rx_done); - writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); - writel(SIRFSOC_SPI_INT_MASK_ALL, - sspi->base + SIRFSOC_SPI_INT_STATUS); + switch (sspi->type) { + case SIRF_REAL_SPI: + case SIRF_USP_SPI_P2: + writel(0x0, sspi->base + sspi->regs->int_en); + break; + case SIRF_USP_SPI_A7: + writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); + break; + } + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); return IRQ_HANDLED; } @@ -313,8 +477,8 @@ static void spi_sirfsoc_cmd_transfer(struct spi_device *spi, u32 cmd; sspi = spi_master_get_devdata(spi->master); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); + writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); + writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); memcpy(&cmd, sspi->tx, t->len); if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) cmd = cpu_to_be32(cmd) >> @@ -322,11 +486,11 @@ static void spi_sirfsoc_cmd_transfer(struct spi_device *spi, if (sspi->word_width == 2 && t->len == 4 && (!(spi->mode & SPI_LSB_FIRST))) cmd = ((cmd & 0xffff) << 16) | (cmd >> 16); - writel(cmd, sspi->base + SIRFSOC_SPI_CMD); + writel(cmd, sspi->base + sspi->regs->spi_cmd); writel(SIRFSOC_SPI_FRM_END_INT_EN, - sspi->base + SIRFSOC_SPI_INT_EN); + sspi->base + sspi->regs->int_en); writel(SIRFSOC_SPI_CMD_TX_EN, - sspi->base + SIRFSOC_SPI_TX_RX_EN); + sspi->base + sspi->regs->tx_rx_en); if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { dev_err(&spi->dev, "cmd transfer timeout\n"); return; @@ -342,25 +506,56 @@ static void spi_sirfsoc_dma_transfer(struct spi_device *spi, int timeout = t->len * 10; sspi = spi_master_get_devdata(spi->master); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(0, sspi->base + SIRFSOC_SPI_INT_EN); - writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); - if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) { - writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | - SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE, - sspi->base + SIRFSOC_SPI_CTRL); - writel(sspi->left_tx_word - 1, - sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); - writel(sspi->left_tx_word - 1, - sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); + writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); + writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); + switch (sspi->type) { + case SIRF_REAL_SPI: + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->rxfifo_op); + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->txfifo_op); + writel(0, sspi->base + sspi->regs->int_en); + break; + case SIRF_USP_SPI_P2: + writel(0x0, sspi->base + sspi->regs->rxfifo_op); + writel(0x0, sspi->base + sspi->regs->txfifo_op); + writel(0, sspi->base + sspi->regs->int_en); + break; + case SIRF_USP_SPI_A7: + writel(0x0, sspi->base + sspi->regs->rxfifo_op); + writel(0x0, sspi->base + sspi->regs->txfifo_op); + writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); + break; + } + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); + if (sspi->left_tx_word < sspi->dat_max_frm_len) { + switch (sspi->type) { + case SIRF_REAL_SPI: + writel(readl(sspi->base + sspi->regs->spi_ctrl) | + SIRFSOC_SPI_ENA_AUTO_CLR | + SIRFSOC_SPI_MUL_DAT_MODE, + sspi->base + sspi->regs->spi_ctrl); + writel(sspi->left_tx_word - 1, + sspi->base + sspi->regs->tx_dma_io_len); + writel(sspi->left_tx_word - 1, + sspi->base + sspi->regs->rx_dma_io_len); + break; + case SIRF_USP_SPI_P2: + case SIRF_USP_SPI_A7: + /*USP simulate SPI, tx/rx_dma_io_len indicates bytes*/ + writel(sspi->left_tx_word * sspi->word_width, + sspi->base + sspi->regs->tx_dma_io_len); + writel(sspi->left_tx_word * sspi->word_width, + sspi->base + sspi->regs->rx_dma_io_len); + break; + } } else { - writel(readl(sspi->base + SIRFSOC_SPI_CTRL), - sspi->base + SIRFSOC_SPI_CTRL); - writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); - writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); + if (sspi->type == SIRF_REAL_SPI) + writel(readl(sspi->base + sspi->regs->spi_ctrl), + sspi->base + sspi->regs->spi_ctrl); + writel(0, sspi->base + sspi->regs->tx_dma_io_len); + writel(0, sspi->base + sspi->regs->rx_dma_io_len); } sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, (t->tx_buf != t->rx_buf) ? @@ -385,7 +580,14 @@ static void spi_sirfsoc_dma_transfer(struct spi_device *spi, dma_async_issue_pending(sspi->tx_chan); dma_async_issue_pending(sspi->rx_chan); writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, - sspi->base + SIRFSOC_SPI_TX_RX_EN); + sspi->base + sspi->regs->tx_rx_en); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) { + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->rxfifo_op); + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->txfifo_op); + } if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) { dev_err(&spi->dev, "transfer timeout\n"); dmaengine_terminate_all(sspi->rx_chan); @@ -398,15 +600,21 @@ static void spi_sirfsoc_dma_transfer(struct spi_device *spi, */ if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { dev_err(&spi->dev, "transfer timeout\n"); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) + writel(0, sspi->base + sspi->regs->tx_rx_en); dmaengine_terminate_all(sspi->tx_chan); } dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE); dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE); /* TX, RX FIFO stop */ - writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX) - writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); + writel(0, sspi->base + sspi->regs->rxfifo_op); + writel(0, sspi->base + sspi->regs->txfifo_op); + if (sspi->left_tx_word >= sspi->dat_max_frm_len) + writel(0, sspi->base + sspi->regs->tx_rx_en); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) + writel(0, sspi->base + sspi->regs->tx_rx_en); } static void spi_sirfsoc_pio_transfer(struct spi_device *spi, @@ -414,55 +622,103 @@ static void spi_sirfsoc_pio_transfer(struct spi_device *spi, { struct sirfsoc_spi *sspi; int timeout = t->len * 10; + unsigned int data_units; sspi = spi_master_get_devdata(spi->master); do { writel(SIRFSOC_SPI_FIFO_RESET, - sspi->base + SIRFSOC_SPI_RXFIFO_OP); + sspi->base + sspi->regs->rxfifo_op); writel(SIRFSOC_SPI_FIFO_RESET, - sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, - sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, - sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(0, sspi->base + SIRFSOC_SPI_INT_EN); - writel(SIRFSOC_SPI_INT_MASK_ALL, - sspi->base + SIRFSOC_SPI_INT_STATUS); - writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | - SIRFSOC_SPI_MUL_DAT_MODE | SIRFSOC_SPI_ENA_AUTO_CLR, - sspi->base + SIRFSOC_SPI_CTRL); - writel(min(sspi->left_tx_word, (u32)(256 / sspi->word_width)) - - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); - writel(min(sspi->left_rx_word, (u32)(256 / sspi->word_width)) - - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); - while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) - & SIRFSOC_SPI_FIFO_FULL)) && sspi->left_tx_word) + sspi->base + sspi->regs->txfifo_op); + switch (sspi->type) { + case SIRF_USP_SPI_P2: + writel(0x0, sspi->base + sspi->regs->rxfifo_op); + writel(0x0, sspi->base + sspi->regs->txfifo_op); + writel(0, sspi->base + sspi->regs->int_en); + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); + writel(min((sspi->left_tx_word * sspi->word_width), + sspi->fifo_size), + sspi->base + sspi->regs->tx_dma_io_len); + writel(min((sspi->left_rx_word * sspi->word_width), + sspi->fifo_size), + sspi->base + sspi->regs->rx_dma_io_len); + break; + case SIRF_USP_SPI_A7: + writel(0x0, sspi->base + sspi->regs->rxfifo_op); + writel(0x0, sspi->base + sspi->regs->txfifo_op); + writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); + writel(min((sspi->left_tx_word * sspi->word_width), + sspi->fifo_size), + sspi->base + sspi->regs->tx_dma_io_len); + writel(min((sspi->left_rx_word * sspi->word_width), + sspi->fifo_size), + sspi->base + sspi->regs->rx_dma_io_len); + break; + case SIRF_REAL_SPI: + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->rxfifo_op); + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->txfifo_op); + writel(0, sspi->base + sspi->regs->int_en); + writel(readl(sspi->base + sspi->regs->int_st), + sspi->base + sspi->regs->int_st); + writel(readl(sspi->base + sspi->regs->spi_ctrl) | + SIRFSOC_SPI_MUL_DAT_MODE | + SIRFSOC_SPI_ENA_AUTO_CLR, + sspi->base + sspi->regs->spi_ctrl); + data_units = sspi->fifo_size / sspi->word_width; + writel(min(sspi->left_tx_word, data_units) - 1, + sspi->base + sspi->regs->tx_dma_io_len); + writel(min(sspi->left_rx_word, data_units) - 1, + sspi->base + sspi->regs->rx_dma_io_len); + break; + } + while (!((readl(sspi->base + sspi->regs->txfifo_st) + & SIRFSOC_SPI_FIFO_FULL_MASK(sspi))) && + sspi->left_tx_word) sspi->tx_word(sspi); writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN | SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_RX_IO_DMA_INT_EN, - sspi->base + SIRFSOC_SPI_INT_EN); + sspi->base + sspi->regs->int_en); writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, - sspi->base + SIRFSOC_SPI_TX_RX_EN); + sspi->base + sspi->regs->tx_rx_en); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) { + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->rxfifo_op); + writel(SIRFSOC_SPI_FIFO_START, + sspi->base + sspi->regs->txfifo_op); + } if (!wait_for_completion_timeout(&sspi->tx_done, timeout) || !wait_for_completion_timeout(&sspi->rx_done, timeout)) { dev_err(&spi->dev, "transfer timeout\n"); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) + writel(0, sspi->base + sspi->regs->tx_rx_en); break; } - while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS) - & SIRFSOC_SPI_FIFO_EMPTY)) && sspi->left_rx_word) + while (!((readl(sspi->base + sspi->regs->rxfifo_st) + & SIRFSOC_SPI_FIFO_EMPTY_MASK(sspi))) && + sspi->left_rx_word) sspi->rx_word(sspi); - writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) + writel(0, sspi->base + sspi->regs->tx_rx_en); + writel(0, sspi->base + sspi->regs->rxfifo_op); + writel(0, sspi->base + sspi->regs->txfifo_op); } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0); } static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) { struct sirfsoc_spi *sspi; - sspi = spi_master_get_devdata(spi->master); + sspi = spi_master_get_devdata(spi->master); sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage; sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage; sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width; @@ -473,7 +729,7 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) * null, just fill command data into command register and wait for its * completion. */ - if (sspi->tx_by_cmd) + if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd) spi_sirfsoc_cmd_transfer(spi, t); else if (IS_DMA_VALID(t)) spi_sirfsoc_dma_transfer(spi, t); @@ -488,22 +744,49 @@ static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); if (sspi->hw_cs) { - u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); - switch (value) { - case BITBANG_CS_ACTIVE: - if (spi->mode & SPI_CS_HIGH) - regval |= SIRFSOC_SPI_CS_IO_OUT; - else - regval &= ~SIRFSOC_SPI_CS_IO_OUT; + u32 regval; + + switch (sspi->type) { + case SIRF_REAL_SPI: + regval = readl(sspi->base + sspi->regs->spi_ctrl); + switch (value) { + case BITBANG_CS_ACTIVE: + if (spi->mode & SPI_CS_HIGH) + regval |= SIRFSOC_SPI_CS_IO_OUT; + else + regval &= ~SIRFSOC_SPI_CS_IO_OUT; + break; + case BITBANG_CS_INACTIVE: + if (spi->mode & SPI_CS_HIGH) + regval &= ~SIRFSOC_SPI_CS_IO_OUT; + else + regval |= SIRFSOC_SPI_CS_IO_OUT; + break; + } + writel(regval, sspi->base + sspi->regs->spi_ctrl); break; - case BITBANG_CS_INACTIVE: - if (spi->mode & SPI_CS_HIGH) - regval &= ~SIRFSOC_SPI_CS_IO_OUT; - else - regval |= SIRFSOC_SPI_CS_IO_OUT; + case SIRF_USP_SPI_P2: + case SIRF_USP_SPI_A7: + regval = readl(sspi->base + + sspi->regs->usp_pin_io_data); + switch (value) { + case BITBANG_CS_ACTIVE: + if (spi->mode & SPI_CS_HIGH) + regval |= SIRFSOC_USP_CS_HIGH_VALUE; + else + regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE); + break; + case BITBANG_CS_INACTIVE: + if (spi->mode & SPI_CS_HIGH) + regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE); + else + regval |= SIRFSOC_USP_CS_HIGH_VALUE; + break; + } + writel(regval, + sspi->base + sspi->regs->usp_pin_io_data); break; } - writel(regval, sspi->base + SIRFSOC_SPI_CTRL); } else { switch (value) { case BITBANG_CS_ACTIVE: @@ -518,27 +801,102 @@ static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) } } +static int spi_sirfsoc_config_mode(struct spi_device *spi) +{ + struct sirfsoc_spi *sspi; + u32 regval, usp_mode1; + + sspi = spi_master_get_devdata(spi->master); + regval = readl(sspi->base + sspi->regs->spi_ctrl); + usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1); + if (!(spi->mode & SPI_CS_HIGH)) { + regval |= SIRFSOC_SPI_CS_IDLE_STAT; + usp_mode1 &= ~SIRFSOC_USP_CS_HIGH_VALID; + } else { + regval &= ~SIRFSOC_SPI_CS_IDLE_STAT; + usp_mode1 |= SIRFSOC_USP_CS_HIGH_VALID; + } + if (!(spi->mode & SPI_LSB_FIRST)) { + regval |= SIRFSOC_SPI_TRAN_MSB; + usp_mode1 &= ~SIRFSOC_USP_LSB; + } else { + regval &= ~SIRFSOC_SPI_TRAN_MSB; + usp_mode1 |= SIRFSOC_USP_LSB; + } + if (spi->mode & SPI_CPOL) { + regval |= SIRFSOC_SPI_CLK_IDLE_STAT; + usp_mode1 |= SIRFSOC_USP_SCLK_IDLE_STAT; + } else { + regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT; + usp_mode1 &= ~SIRFSOC_USP_SCLK_IDLE_STAT; + } + /* + * Data should be driven at least 1/2 cycle before the fetch edge + * to make sure that data gets stable at the fetch edge. + */ + if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || + (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) { + regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; + usp_mode1 |= (SIRFSOC_USP_TXD_FALLING_EDGE | + SIRFSOC_USP_RXD_FALLING_EDGE); + } else { + regval |= SIRFSOC_SPI_DRV_POS_EDGE; + usp_mode1 &= ~(SIRFSOC_USP_RXD_FALLING_EDGE | + SIRFSOC_USP_TXD_FALLING_EDGE); + } + writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) << + SIRFSOC_SPI_FIFO_SC_OFFSET) | + (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) << + SIRFSOC_SPI_FIFO_LC_OFFSET) | + (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) << + SIRFSOC_SPI_FIFO_HC_OFFSET), + sspi->base + sspi->regs->txfifo_level_chk); + writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) << + SIRFSOC_SPI_FIFO_SC_OFFSET) | + (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) << + SIRFSOC_SPI_FIFO_LC_OFFSET) | + (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) << + SIRFSOC_SPI_FIFO_HC_OFFSET), + sspi->base + sspi->regs->rxfifo_level_chk); + /* + * it should never set to hardware cs mode because in hardware cs mode, + * cs signal can't controlled by driver. + */ + switch (sspi->type) { + case SIRF_REAL_SPI: + regval |= SIRFSOC_SPI_CS_IO_MODE; + writel(regval, sspi->base + sspi->regs->spi_ctrl); + break; + case SIRF_USP_SPI_P2: + case SIRF_USP_SPI_A7: + usp_mode1 |= SIRFSOC_USP_SYNC_MODE; + usp_mode1 |= SIRFSOC_USP_TFS_IO_MODE; + usp_mode1 &= ~SIRFSOC_USP_TFS_IO_INPUT; + writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); + break; + } + + return 0; +} + static int spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { struct sirfsoc_spi *sspi; u8 bits_per_word = 0; int hz = 0; - u32 regval; - u32 txfifo_ctrl, rxfifo_ctrl; - u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4; + u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2; sspi = spi_master_get_devdata(spi->master); bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; - regval = (sspi->ctrl_freq / (2 * hz)) - 1; + usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1; if (regval > 0xFFFF || regval < 0) { dev_err(&spi->dev, "Speed %d not supported\n", hz); return -EINVAL; } - switch (bits_per_word) { case 8: regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; @@ -562,69 +920,87 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) dev_err(&spi->dev, "bpw %d not supported\n", bits_per_word); return -EINVAL; } - sspi->word_width = DIV_ROUND_UP(bits_per_word, 8); - txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | - (sspi->word_width >> 1); - rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | - (sspi->word_width >> 1); - - if (!(spi->mode & SPI_CS_HIGH)) - regval |= SIRFSOC_SPI_CS_IDLE_STAT; - if (!(spi->mode & SPI_LSB_FIRST)) - regval |= SIRFSOC_SPI_TRAN_MSB; - if (spi->mode & SPI_CPOL) - regval |= SIRFSOC_SPI_CLK_IDLE_STAT; - - /* - * Data should be driven at least 1/2 cycle before the fetch edge - * to make sure that data gets stable at the fetch edge. - */ - if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || - (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) - regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; - else - regval |= SIRFSOC_SPI_DRV_POS_EDGE; - - writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) | - SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | - SIRFSOC_SPI_FIFO_HC(2), - sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK); - writel(SIRFSOC_SPI_FIFO_SC(2) | - SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | - SIRFSOC_SPI_FIFO_HC(fifo_size - 2), - sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK); - writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL); - writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL); - - if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) { - regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | - SIRFSOC_SPI_CMD_MODE); - sspi->tx_by_cmd = true; - } else { - regval &= ~SIRFSOC_SPI_CMD_MODE; - sspi->tx_by_cmd = false; + txfifo_ctrl = (((sspi->fifo_size / 2) & + SIRFSOC_SPI_FIFO_THD_MASK(sspi)) + << SIRFSOC_SPI_FIFO_THD_OFFSET) | + (sspi->word_width >> 1); + rxfifo_ctrl = (((sspi->fifo_size / 2) & + SIRFSOC_SPI_FIFO_THD_MASK(sspi)) + << SIRFSOC_SPI_FIFO_THD_OFFSET) | + (sspi->word_width >> 1); + writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); + writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); + if (sspi->type == SIRF_USP_SPI_P2 || + sspi->type == SIRF_USP_SPI_A7) { + tx_frm_ctl = 0; + tx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_TX_DATA_MASK) + << SIRFSOC_USP_TX_DATA_OFFSET; + tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN + - 1) & SIRFSOC_USP_TX_SYNC_MASK) << + SIRFSOC_USP_TX_SYNC_OFFSET; + tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN + + 2 - 1) & SIRFSOC_USP_TX_FRAME_MASK) << + SIRFSOC_USP_TX_FRAME_OFFSET; + tx_frm_ctl |= ((bits_per_word - 1) & + SIRFSOC_USP_TX_SHIFTER_MASK) << + SIRFSOC_USP_TX_SHIFTER_OFFSET; + rx_frm_ctl = 0; + rx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_RX_DATA_MASK) + << SIRFSOC_USP_RX_DATA_OFFSET; + rx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_RXD_DELAY_LEN + + 2 - 1) & SIRFSOC_USP_RX_FRAME_MASK) << + SIRFSOC_USP_RX_FRAME_OFFSET; + rx_frm_ctl |= ((bits_per_word - 1) + & SIRFSOC_USP_RX_SHIFTER_MASK) << + SIRFSOC_USP_RX_SHIFTER_OFFSET; + writel(tx_frm_ctl | (((usp_mode2 >> 10) & + SIRFSOC_USP_CLK_10_11_MASK) << + SIRFSOC_USP_CLK_10_11_OFFSET), + sspi->base + sspi->regs->usp_tx_frame_ctrl); + writel(rx_frm_ctl | (((usp_mode2 >> 12) & + SIRFSOC_USP_CLK_12_15_MASK) << + SIRFSOC_USP_CLK_12_15_OFFSET), + sspi->base + sspi->regs->usp_rx_frame_ctrl); + writel(readl(sspi->base + sspi->regs->usp_mode2) | + ((usp_mode2 & SIRFSOC_USP_CLK_DIVISOR_MASK) << + SIRFSOC_USP_CLK_DIVISOR_OFFSET) | + (SIRFSOC_USP_RXD_DELAY_LEN << + SIRFSOC_USP_RXD_DELAY_OFFSET) | + (SIRFSOC_USP_TXD_DELAY_LEN << + SIRFSOC_USP_TXD_DELAY_OFFSET), + sspi->base + sspi->regs->usp_mode2); + } + if (sspi->type == SIRF_REAL_SPI) + writel(regval, sspi->base + sspi->regs->spi_ctrl); + spi_sirfsoc_config_mode(spi); + if (sspi->type == SIRF_REAL_SPI) { + if (t && t->tx_buf && !t->rx_buf && + (t->len <= SIRFSOC_MAX_CMD_BYTES)) { + sspi->tx_by_cmd = true; + writel(readl(sspi->base + sspi->regs->spi_ctrl) | + (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | + SIRFSOC_SPI_CMD_MODE), + sspi->base + sspi->regs->spi_ctrl); + } else { + sspi->tx_by_cmd = false; + writel(readl(sspi->base + sspi->regs->spi_ctrl) & + ~SIRFSOC_SPI_CMD_MODE, + sspi->base + sspi->regs->spi_ctrl); + } } - /* - * it should never set to hardware cs mode because in hardware cs mode, - * cs signal can't controlled by driver. - */ - regval |= SIRFSOC_SPI_CS_IO_MODE; - writel(regval, sspi->base + SIRFSOC_SPI_CTRL); - if (IS_DMA_VALID(t)) { /* Enable DMA mode for RX, TX */ - writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); + writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); writel(SIRFSOC_SPI_RX_DMA_FLUSH, - sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); + sspi->base + sspi->regs->rx_dma_io_ctrl); } else { /* Enable IO mode for RX, TX */ writel(SIRFSOC_SPI_IO_MODE_SEL, - sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); + sspi->base + sspi->regs->tx_dma_io_ctrl); writel(SIRFSOC_SPI_IO_MODE_SEL, - sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); + sspi->base + sspi->regs->rx_dma_io_ctrl); } - return 0; } @@ -634,7 +1010,6 @@ static int spi_sirfsoc_setup(struct spi_device *spi) int ret = 0; sspi = spi_master_get_devdata(spi->master); - if (spi->cs_gpio == -ENOENT) sspi->hw_cs = true; else { @@ -659,8 +1034,7 @@ static int spi_sirfsoc_setup(struct spi_device *spi) spi_set_ctldata(spi, cs); } } - writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | SIRFSOC_SPI_CS_IO_MODE, - sspi->base + SIRFSOC_SPI_CTRL); + spi_sirfsoc_config_mode(spi); spi_sirfsoc_chipselect(spi, BITBANG_CS_INACTIVE); exit: return ret; @@ -674,13 +1048,23 @@ static void spi_sirfsoc_cleanup(struct spi_device *spi) } } +static const struct of_device_id spi_sirfsoc_of_match[] = { + { .compatible = "sirf,prima2-spi", .data = &sirf_real_spi}, + { .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2}, + { .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7}, + {} +}; +MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match); + static int spi_sirfsoc_probe(struct platform_device *pdev) { struct sirfsoc_spi *sspi; struct spi_master *master; struct resource *mem_res; + struct sirf_spi_comp_data *spi_comp_data; int irq; int ret; + const struct of_device_id *match; ret = device_reset(&pdev->dev); if (ret) { @@ -693,16 +1077,22 @@ static int spi_sirfsoc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Unable to allocate SPI master\n"); return -ENOMEM; } + match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node); platform_set_drvdata(pdev, master); sspi = spi_master_get_devdata(master); - + sspi->fifo_full_offset = ilog2(sspi->fifo_size); + spi_comp_data = (struct sirf_spi_comp_data *)match->data; + sspi->regs = spi_comp_data->regs; + sspi->type = spi_comp_data->type; + sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1; + sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len; + sspi->fifo_size = spi_comp_data->fifo_size; mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); sspi->base = devm_ioremap_resource(&pdev->dev, mem_res); if (IS_ERR(sspi->base)) { ret = PTR_ERR(sspi->base); goto free_master; } - irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = -ENXIO; @@ -751,13 +1141,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev) init_completion(&sspi->rx_done); init_completion(&sspi->tx_done); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - /* We are not using dummy delay between command and data */ - writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL); - sspi->dummypage = devm_kzalloc(&pdev->dev, 2 * PAGE_SIZE, GFP_KERNEL); if (!sspi->dummypage) { ret = -ENOMEM; @@ -790,7 +1173,6 @@ static int spi_sirfsoc_remove(struct platform_device *pdev) master = platform_get_drvdata(pdev); sspi = spi_master_get_devdata(master); - spi_bitbang_stop(&sspi->bitbang); clk_disable_unprepare(sspi->clk); clk_put(sspi->clk); @@ -821,24 +1203,17 @@ static int spi_sirfsoc_resume(struct device *dev) struct sirfsoc_spi *sspi = spi_master_get_devdata(master); clk_enable(sspi->clk); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); - writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); - - return spi_master_resume(master); + writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); + writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); + writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); + writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op); + return 0; } #endif static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend, spi_sirfsoc_resume); -static const struct of_device_id spi_sirfsoc_of_match[] = { - { .compatible = "sirf,prima2-spi", }, - {} -}; -MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match); - static struct platform_driver spi_sirfsoc_driver = { .driver = { .name = DRIVER_NAME, @@ -852,4 +1227,5 @@ module_platform_driver(spi_sirfsoc_driver); MODULE_DESCRIPTION("SiRF SoC SPI master driver"); MODULE_AUTHOR("Zhiwu Song "); MODULE_AUTHOR("Barry Song "); +MODULE_AUTHOR("Qipan Li "); MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 8064887e02fd684fa0576cbbcdbc29ceab125c4c Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 20 May 2015 00:03:52 +0200 Subject: ARM: vf610: enable Cortex-M4 configuration on Vybrid SoC This patch allows to build the Kernel for Vybrid (VF6xx) SoC when ARMv7-M CPU is selected. The resulting image runs on the secondary Cortex-M4 core. This core has equally access to all peripherals as the main Cortex-A5 core. However, there is no resource control mechanism, hence when both cores are used simultaneously, orthogonal device tree's are required. The boot CPU is dependent on the SoC variant. The available boards use mostly variants where the Cortex-A5 is the primary and hence the boot CPU. Booting the secondary Cortex-M4 CPU needs SoC specific registers written. There is no in kernel support for this right now, a external userspace utility called "m4boot" can be used to boot the kernel: m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb Signed-off-by: Stefan Agner Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/fsl.txt | 3 +++ arch/arm/mach-imx/Kconfig | 38 +++++++++++++++------------ arch/arm/mach-imx/Makefile.boot | 0 arch/arm/mach-imx/mach-vf610.c | 1 + 4 files changed, 25 insertions(+), 17 deletions(-) create mode 100644 arch/arm/mach-imx/Makefile.boot (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index a5462b6b3c30..2a3ba73f0c5c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -81,12 +81,15 @@ Freescale Vybrid Platform Device Tree Bindings For the Vybrid SoC familiy all variants with DDR controller are supported, which is the VF5xx and VF6xx series. Out of historical reasons, in most places the kernel uses vf610 to refer to the whole familiy. +The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 +core support. Required root node compatible property (one of them): - compatible = "fsl,vf500"; - compatible = "fsl,vf510"; - compatible = "fsl,vf600"; - compatible = "fsl,vf610"; + - compatible = "fsl,vf610m4"; Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3a3d3e9d7bfd..2e3c45832674 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,5 +1,5 @@ menuconfig ARCH_MXC - bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 + bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM select CLKSRC_MMIO @@ -496,10 +496,10 @@ config MACH_VPR200 endif -if ARCH_MULTI_V5 - comment "Device tree only" +if ARCH_MULTI_V5 + config SOC_IMX25 bool "i.MX25 support" select ARCH_MXC_IOMUX_V3 @@ -512,7 +512,7 @@ endif if ARCH_MULTI_V7 -comment "Device tree only" +comment "Cortex-A platforms" config SOC_IMX5 bool @@ -582,10 +582,24 @@ config SOC_IMX6SX help This enables support for Freescale i.MX6 SoloX processor. +config SOC_LS1021A + bool "Freescale LS1021A support" + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select PCI_DOMAINS if PCI + select ZONE_DMA if ARM_LPAE + help + This enables support for Freescale LS1021A processor. + +endif + +comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" + +if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M + config SOC_VF610 bool "Vybrid Family VF610 support" - select IRQ_DOMAIN_HIERARCHY - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select PINCTRL_VF610 select PL310_ERRATA_769419 if CACHE_L2X0 select SMP_ON_UP if SMP @@ -599,7 +613,7 @@ choice default VF_USE_ARM_GLOBAL_TIMER config VF_USE_ARM_GLOBAL_TIMER - bool "Use ARM Global Timer" + bool "Use ARM Global Timer" if ARCH_MULTI_V7 select ARM_GLOBAL_TIMER select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK help @@ -613,16 +627,6 @@ choice endchoice -config SOC_LS1021A - bool "Freescale LS1021A support" - select ARM_GIC - select HAVE_ARM_ARCH_TIMER - select PCI_DOMAINS if PCI - select ZONE_DMA if ARM_LPAE - - help - This enables support for Freescale LS1021A processor. - endif source "arch/arm/mach-imx/devices/Kconfig" diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index 2e7c75b66fe0..b20f6c14eda5 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -17,6 +17,7 @@ static const char * const vf610_dt_compat[] __initconst = { "fsl,vf510", "fsl,vf600", "fsl,vf610", + "fsl,vf610m4", NULL, }; -- cgit v1.2.3 From 301c5d29402e590ea893fe7ddc83a00a71994cba Mon Sep 17 00:00:00 2001 From: Zhiwu Song Date: Wed, 20 May 2015 08:50:33 +0000 Subject: clk: sirf: add CSR atlas7 clk and reset support the hardware node includes both clock and reset support, so it is named as "car". this patch implements Flexible clocks(mux, divider, gate), Selectable clock(mux, divider, gate), root clock(gate),leaf clock(gate), others. it also implements the reset controller functionality. Signed-off-by: Zhiwu Song Signed-off-by: Guo Zeng Signed-off-by: Barry Song Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/csr,atlas7-car.txt | 55 + drivers/clk/sirf/Makefile | 2 +- drivers/clk/sirf/clk-atlas7.c | 1632 ++++++++++++++++++++ 3 files changed, 1688 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/csr,atlas7-car.txt create mode 100644 drivers/clk/sirf/clk-atlas7.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt b/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt new file mode 100644 index 000000000000..54d6d1358339 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt @@ -0,0 +1,55 @@ +* Clock and reset bindings for CSR atlas7 + +Required properties: +- compatible: Should be "sirf,atlas7-car" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- #reset-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c + +The reset consumer should specify the desired reset by having the reset +ID in its "reset" phandle cell. +The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c + +Examples: Clock and reset controller node: + +car: clock-controller@18620000 { + compatible = "sirf,atlas7-car"; + reg = <0x18620000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; + +Examples: Consumers using clock or reset: + +timer@10dc0000 { + compatible = "sirf,macro-tick"; + reg = <0x10dc0000 0x1000>; + clocks = <&car 54>; + interrupts = <0 0 0>, + <0 1 0>, + <0 2 0>, + <0 49 0>, + <0 50 0>, + <0 51 0>; +}; + +uart1: uart@18020000 { + cell-index = <1>; + compatible = "sirf,macro-uart"; + reg = <0x18020000 0x1000>; + clocks = <&clks 95>; + interrupts = <0 18 0>; + fifosize = <32>; +}; + +vpp@13110000 { + compatible = "sirf,prima2-vpp"; + reg = <0x13110000 0x10000>; + interrupts = <0 31 0>; + clocks = <&car 85>; + resets = <&car 29>; +}; diff --git a/drivers/clk/sirf/Makefile b/drivers/clk/sirf/Makefile index 36b8e203f6e7..09b4210d9124 100644 --- a/drivers/clk/sirf/Makefile +++ b/drivers/clk/sirf/Makefile @@ -2,4 +2,4 @@ # Makefile for sirf specific clk # -obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o +obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o clk-atlas7.o diff --git a/drivers/clk/sirf/clk-atlas7.c b/drivers/clk/sirf/clk-atlas7.c new file mode 100644 index 000000000000..db8ab691dbf6 --- /dev/null +++ b/drivers/clk/sirf/clk-atlas7.c @@ -0,0 +1,1632 @@ +/* + * Clock tree for CSR SiRFAtlas7 + * + * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIRFSOC_CLKC_MEMPLL_AB_FREQ 0x0000 +#define SIRFSOC_CLKC_MEMPLL_AB_SSC 0x0004 +#define SIRFSOC_CLKC_MEMPLL_AB_CTRL0 0x0008 +#define SIRFSOC_CLKC_MEMPLL_AB_CTRL1 0x000c +#define SIRFSOC_CLKC_MEMPLL_AB_STATUS 0x0010 +#define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR 0x0014 +#define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA 0x0018 + +#define SIRFSOC_CLKC_CPUPLL_AB_FREQ 0x001c +#define SIRFSOC_CLKC_CPUPLL_AB_SSC 0x0020 +#define SIRFSOC_CLKC_CPUPLL_AB_CTRL0 0x0024 +#define SIRFSOC_CLKC_CPUPLL_AB_CTRL1 0x0028 +#define SIRFSOC_CLKC_CPUPLL_AB_STATUS 0x002c + +#define SIRFSOC_CLKC_SYS0PLL_AB_FREQ 0x0030 +#define SIRFSOC_CLKC_SYS0PLL_AB_SSC 0x0034 +#define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0 0x0038 +#define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1 0x003c +#define SIRFSOC_CLKC_SYS0PLL_AB_STATUS 0x0040 + +#define SIRFSOC_CLKC_SYS1PLL_AB_FREQ 0x0044 +#define SIRFSOC_CLKC_SYS1PLL_AB_SSC 0x0048 +#define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0 0x004c +#define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1 0x0050 +#define SIRFSOC_CLKC_SYS1PLL_AB_STATUS 0x0054 + +#define SIRFSOC_CLKC_SYS2PLL_AB_FREQ 0x0058 +#define SIRFSOC_CLKC_SYS2PLL_AB_SSC 0x005c +#define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0 0x0060 +#define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1 0x0064 +#define SIRFSOC_CLKC_SYS2PLL_AB_STATUS 0x0068 + +#define SIRFSOC_CLKC_SYS3PLL_AB_FREQ 0x006c +#define SIRFSOC_CLKC_SYS3PLL_AB_SSC 0x0070 +#define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0 0x0074 +#define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1 0x0078 +#define SIRFSOC_CLKC_SYS3PLL_AB_STATUS 0x007c + +#define SIRFSOC_ABPLL_CTRL0_SSEN 0x00001000 +#define SIRFSOC_ABPLL_CTRL0_BYPASS 0x00000010 +#define SIRFSOC_ABPLL_CTRL0_RESET 0x00000001 + +#define SIRFSOC_CLKC_AUDIO_DTO_INC 0x0088 +#define SIRFSOC_CLKC_DISP0_DTO_INC 0x008c +#define SIRFSOC_CLKC_DISP1_DTO_INC 0x0090 + +#define SIRFSOC_CLKC_AUDIO_DTO_SRC 0x0094 +#define SIRFSOC_CLKC_AUDIO_DTO_ENA 0x0098 +#define SIRFSOC_CLKC_AUDIO_DTO_DROFF 0x009c + +#define SIRFSOC_CLKC_DISP0_DTO_SRC 0x00a0 +#define SIRFSOC_CLKC_DISP0_DTO_ENA 0x00a4 +#define SIRFSOC_CLKC_DISP0_DTO_DROFF 0x00a8 + +#define SIRFSOC_CLKC_DISP1_DTO_SRC 0x00ac +#define SIRFSOC_CLKC_DISP1_DTO_ENA 0x00b0 +#define SIRFSOC_CLKC_DISP1_DTO_DROFF 0x00b4 + +#define SIRFSOC_CLKC_I2S_CLK_SEL 0x00b8 +#define SIRFSOC_CLKC_I2S_SEL_STAT 0x00bc + +#define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG 0x00c0 +#define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA 0x00c4 +#define SIRFSOC_CLKC_USBPHY_CLK_SEL 0x00c8 +#define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT 0x00cc + +#define SIRFSOC_CLKC_BTSS_CLKDIV_CFG 0x00d0 +#define SIRFSOC_CLKC_BTSS_CLKDIV_ENA 0x00d4 +#define SIRFSOC_CLKC_BTSS_CLK_SEL 0x00d8 +#define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT 0x00dc + +#define SIRFSOC_CLKC_RGMII_CLKDIV_CFG 0x00e0 +#define SIRFSOC_CLKC_RGMII_CLKDIV_ENA 0x00e4 +#define SIRFSOC_CLKC_RGMII_CLK_SEL 0x00e8 +#define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT 0x00ec + +#define SIRFSOC_CLKC_CPU_CLKDIV_CFG 0x00f0 +#define SIRFSOC_CLKC_CPU_CLKDIV_ENA 0x00f4 +#define SIRFSOC_CLKC_CPU_CLK_SEL 0x00f8 +#define SIRFSOC_CLKC_CPU_CLK_SEL_STAT 0x00fc + +#define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG 0x0100 +#define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA 0x0104 +#define SIRFSOC_CLKC_SDPHY01_CLK_SEL 0x0108 +#define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT 0x010c + +#define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG 0x0110 +#define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA 0x0114 +#define SIRFSOC_CLKC_SDPHY23_CLK_SEL 0x0118 +#define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT 0x011c + +#define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG 0x0120 +#define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA 0x0124 +#define SIRFSOC_CLKC_SDPHY45_CLK_SEL 0x0128 +#define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT 0x012c + +#define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG 0x0130 +#define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA 0x0134 +#define SIRFSOC_CLKC_SDPHY67_CLK_SEL 0x0138 +#define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT 0x013c + +#define SIRFSOC_CLKC_CAN_CLKDIV_CFG 0x0140 +#define SIRFSOC_CLKC_CAN_CLKDIV_ENA 0x0144 +#define SIRFSOC_CLKC_CAN_CLK_SEL 0x0148 +#define SIRFSOC_CLKC_CAN_CLK_SEL_STAT 0x014c + +#define SIRFSOC_CLKC_DEINT_CLKDIV_CFG 0x0150 +#define SIRFSOC_CLKC_DEINT_CLKDIV_ENA 0x0154 +#define SIRFSOC_CLKC_DEINT_CLK_SEL 0x0158 +#define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT 0x015c + +#define SIRFSOC_CLKC_NAND_CLKDIV_CFG 0x0160 +#define SIRFSOC_CLKC_NAND_CLKDIV_ENA 0x0164 +#define SIRFSOC_CLKC_NAND_CLK_SEL 0x0168 +#define SIRFSOC_CLKC_NAND_CLK_SEL_STAT 0x016c + +#define SIRFSOC_CLKC_DISP0_CLKDIV_CFG 0x0170 +#define SIRFSOC_CLKC_DISP0_CLKDIV_ENA 0x0174 +#define SIRFSOC_CLKC_DISP0_CLK_SEL 0x0178 +#define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT 0x017c + +#define SIRFSOC_CLKC_DISP1_CLKDIV_CFG 0x0180 +#define SIRFSOC_CLKC_DISP1_CLKDIV_ENA 0x0184 +#define SIRFSOC_CLKC_DISP1_CLK_SEL 0x0188 +#define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT 0x018c + +#define SIRFSOC_CLKC_GPU_CLKDIV_CFG 0x0190 +#define SIRFSOC_CLKC_GPU_CLKDIV_ENA 0x0194 +#define SIRFSOC_CLKC_GPU_CLK_SEL 0x0198 +#define SIRFSOC_CLKC_GPU_CLK_SEL_STAT 0x019c + +#define SIRFSOC_CLKC_GNSS_CLKDIV_CFG 0x01a0 +#define SIRFSOC_CLKC_GNSS_CLKDIV_ENA 0x01a4 +#define SIRFSOC_CLKC_GNSS_CLK_SEL 0x01a8 +#define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT 0x01ac + +#define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0 0x01b0 +#define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1 0x01b4 +#define SIRFSOC_CLKC_SHARED_DIVIDER_ENA 0x01b8 + +#define SIRFSOC_CLKC_SYS_CLK_SEL 0x01bc +#define SIRFSOC_CLKC_SYS_CLK_SEL_STAT 0x01c0 +#define SIRFSOC_CLKC_IO_CLK_SEL 0x01c4 +#define SIRFSOC_CLKC_IO_CLK_SEL_STAT 0x01c8 +#define SIRFSOC_CLKC_G2D_CLK_SEL 0x01cc +#define SIRFSOC_CLKC_G2D_CLK_SEL_STAT 0x01d0 +#define SIRFSOC_CLKC_JPENC_CLK_SEL 0x01d4 +#define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT 0x01d8 +#define SIRFSOC_CLKC_VDEC_CLK_SEL 0x01dc +#define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT 0x01e0 +#define SIRFSOC_CLKC_GMAC_CLK_SEL 0x01e4 +#define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT 0x01e8 +#define SIRFSOC_CLKC_USB_CLK_SEL 0x01ec +#define SIRFSOC_CLKC_USB_CLK_SEL_STAT 0x01f0 +#define SIRFSOC_CLKC_KAS_CLK_SEL 0x01f4 +#define SIRFSOC_CLKC_KAS_CLK_SEL_STAT 0x01f8 +#define SIRFSOC_CLKC_SEC_CLK_SEL 0x01fc +#define SIRFSOC_CLKC_SEC_CLK_SEL_STAT 0x0200 +#define SIRFSOC_CLKC_SDR_CLK_SEL 0x0204 +#define SIRFSOC_CLKC_SDR_CLK_SEL_STAT 0x0208 +#define SIRFSOC_CLKC_VIP_CLK_SEL 0x020c +#define SIRFSOC_CLKC_VIP_CLK_SEL_STAT 0x0210 +#define SIRFSOC_CLKC_NOCD_CLK_SEL 0x0214 +#define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT 0x0218 +#define SIRFSOC_CLKC_NOCR_CLK_SEL 0x021c +#define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT 0x0220 +#define SIRFSOC_CLKC_TPIU_CLK_SEL 0x0224 +#define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT 0x0228 + +#define SIRFSOC_CLKC_ROOT_CLK_EN0_SET 0x022c +#define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR 0x0230 +#define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT 0x0234 +#define SIRFSOC_CLKC_ROOT_CLK_EN1_SET 0x0238 +#define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR 0x023c +#define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT 0x0240 + +#define SIRFSOC_CLKC_LEAF_CLK_EN0_SET 0x0244 +#define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR 0x0248 +#define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT 0x024c + +#define SIRFSOC_CLKC_RSTC_A7_SW_RST 0x0308 + +#define SIRFSOC_CLKC_LEAF_CLK_EN1_SET 0x04a0 +#define SIRFSOC_CLKC_LEAF_CLK_EN2_SET 0x04b8 +#define SIRFSOC_CLKC_LEAF_CLK_EN3_SET 0x04d0 +#define SIRFSOC_CLKC_LEAF_CLK_EN4_SET 0x04e8 +#define SIRFSOC_CLKC_LEAF_CLK_EN5_SET 0x0500 +#define SIRFSOC_CLKC_LEAF_CLK_EN6_SET 0x0518 +#define SIRFSOC_CLKC_LEAF_CLK_EN7_SET 0x0530 +#define SIRFSOC_CLKC_LEAF_CLK_EN8_SET 0x0548 + + +static void __iomem *sirfsoc_clk_vbase; +static struct clk_onecell_data clk_data; + +static const struct clk_div_table pll_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 16 }, + { .val = 5, .div = 32 }, +}; + +struct clk_pll { + struct clk_hw hw; + u16 regofs; /* register offset */ +}; +#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) + +struct clk_dto { + struct clk_hw hw; + u16 inc_offset; /* dto increment offset */ + u16 src_offset; /* dto src offset */ +}; +#define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw) + +struct clk_unit { + struct clk_hw hw; + u16 regofs; + u16 bit; + spinlock_t *lock; +}; +#define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw) + +struct atlas7_div_init_data { + const char *div_name; + const char *parent_name; + const char *gate_name; + unsigned long flags; + u8 divider_flags; + u8 gate_flags; + u32 div_offset; + u8 shift; + u8 width; + u32 gate_offset; + u8 gate_bit; + spinlock_t *lock; +}; + +struct atlas7_mux_init_data { + const char *mux_name; + const char * const *parent_names; + u8 parent_num; + unsigned long flags; + u8 mux_flags; + u32 mux_offset; + u8 shift; + u8 width; +}; + +struct atlas7_unit_init_data { + u32 index; + const char *unit_name; + const char *parent_name; + unsigned long flags; + u32 regofs; + u8 bit; + spinlock_t *lock; +}; + +struct atlas7_reset_desc { + const char *name; + u32 clk_ofs; + u8 clk_bit; + u32 rst_ofs; + u8 rst_bit; + spinlock_t *lock; +}; + +static DEFINE_SPINLOCK(cpupll_ctrl1_lock); +static DEFINE_SPINLOCK(mempll_ctrl1_lock); +static DEFINE_SPINLOCK(sys0pll_ctrl1_lock); +static DEFINE_SPINLOCK(sys1pll_ctrl1_lock); +static DEFINE_SPINLOCK(sys2pll_ctrl1_lock); +static DEFINE_SPINLOCK(sys3pll_ctrl1_lock); +static DEFINE_SPINLOCK(usbphy_div_lock); +static DEFINE_SPINLOCK(btss_div_lock); +static DEFINE_SPINLOCK(rgmii_div_lock); +static DEFINE_SPINLOCK(cpu_div_lock); +static DEFINE_SPINLOCK(sdphy01_div_lock); +static DEFINE_SPINLOCK(sdphy23_div_lock); +static DEFINE_SPINLOCK(sdphy45_div_lock); +static DEFINE_SPINLOCK(sdphy67_div_lock); +static DEFINE_SPINLOCK(can_div_lock); +static DEFINE_SPINLOCK(deint_div_lock); +static DEFINE_SPINLOCK(nand_div_lock); +static DEFINE_SPINLOCK(disp0_div_lock); +static DEFINE_SPINLOCK(disp1_div_lock); +static DEFINE_SPINLOCK(gpu_div_lock); +static DEFINE_SPINLOCK(gnss_div_lock); +/* gate register shared */ +static DEFINE_SPINLOCK(share_div_lock); +static DEFINE_SPINLOCK(root0_gate_lock); +static DEFINE_SPINLOCK(root1_gate_lock); +static DEFINE_SPINLOCK(leaf0_gate_lock); +static DEFINE_SPINLOCK(leaf1_gate_lock); +static DEFINE_SPINLOCK(leaf2_gate_lock); +static DEFINE_SPINLOCK(leaf3_gate_lock); +static DEFINE_SPINLOCK(leaf4_gate_lock); +static DEFINE_SPINLOCK(leaf5_gate_lock); +static DEFINE_SPINLOCK(leaf6_gate_lock); +static DEFINE_SPINLOCK(leaf7_gate_lock); +static DEFINE_SPINLOCK(leaf8_gate_lock); + +static inline unsigned long clkc_readl(unsigned reg) +{ + return readl(sirfsoc_clk_vbase + reg); +} + +static inline void clkc_writel(u32 val, unsigned reg) +{ + writel(val, sirfsoc_clk_vbase + reg); +} + +/* +* ABPLL +* integer mode: Fvco = Fin * 2 * NF / NR +* Spread Spectrum mode: Fvco = Fin * SSN / NR +* SSN = 2^24 / (256 * ((ssdiv >> ssdepth) << ssdepth) + (ssmod << ssdepth)) +*/ +static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long fin = parent_rate; + struct clk_pll *clk = to_pllclk(hw); + u64 rate; + u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 - + SIRFSOC_CLKC_MEMPLL_AB_FREQ); + u32 regfreq = clkc_readl(clk->regofs); + u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC - + SIRFSOC_CLKC_MEMPLL_AB_FREQ); + u32 nr = (regfreq >> 16 & (BIT(3) - 1)) + 1; + u32 nf = (regfreq & (BIT(9) - 1)) + 1; + u32 ssdiv = regssc >> 8 & (BIT(12) - 1); + u32 ssdepth = regssc >> 20 & (BIT(2) - 1); + u32 ssmod = regssc & (BIT(8) - 1); + + if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS) + return fin; + + if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) { + rate = fin; + rate *= 1 << 24; + do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth) + + (ssmod << ssdepth))); + } else { + rate = 2 * fin; + rate *= nf; + do_div(rate, nr); + } + return rate; +} + +static const struct clk_ops ab_pll_ops = { + .recalc_rate = pll_clk_recalc_rate, +}; + +static const char * const pll_clk_parents[] = { + "xin", +}; + +static struct clk_init_data clk_cpupll_init = { + .name = "cpupll_vco", + .ops = &ab_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_cpupll = { + .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ, + .hw = { + .init = &clk_cpupll_init, + }, +}; + +static struct clk_init_data clk_mempll_init = { + .name = "mempll_vco", + .ops = &ab_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_mempll = { + .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ, + .hw = { + .init = &clk_mempll_init, + }, +}; + +static struct clk_init_data clk_sys0pll_init = { + .name = "sys0pll_vco", + .ops = &ab_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_sys0pll = { + .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ, + .hw = { + .init = &clk_sys0pll_init, + }, +}; + +static struct clk_init_data clk_sys1pll_init = { + .name = "sys1pll_vco", + .ops = &ab_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_sys1pll = { + .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ, + .hw = { + .init = &clk_sys1pll_init, + }, +}; + +static struct clk_init_data clk_sys2pll_init = { + .name = "sys2pll_vco", + .ops = &ab_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_sys2pll = { + .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ, + .hw = { + .init = &clk_sys2pll_init, + }, +}; + +static struct clk_init_data clk_sys3pll_init = { + .name = "sys3pll_vco", + .ops = &ab_pll_ops, + .parent_names = pll_clk_parents, + .num_parents = ARRAY_SIZE(pll_clk_parents), +}; + +static struct clk_pll clk_sys3pll = { + .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ, + .hw = { + .init = &clk_sys3pll_init, + }, +}; + +/* + * DTO in clkc, default enable double resolution mode + * double resolution mode:fout = fin * finc / 2^29 + * normal mode:fout = fin * finc / 2^28 + */ +static int dto_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_dto *clk = to_dtoclk(hw); + int reg; + + reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; + + return !!(clkc_readl(reg) & BIT(0)); +} + +static int dto_clk_enable(struct clk_hw *hw) +{ + u32 val, reg; + struct clk_dto *clk = to_dtoclk(hw); + + reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; + + val = clkc_readl(reg) | BIT(0); + clkc_writel(val, reg); + return 0; +} + +static void dto_clk_disable(struct clk_hw *hw) +{ + u32 val, reg; + struct clk_dto *clk = to_dtoclk(hw); + + reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; + + val = clkc_readl(reg) & ~BIT(0); + clkc_writel(val, reg); +} + +static unsigned long dto_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 rate = parent_rate; + struct clk_dto *clk = to_dtoclk(hw); + u32 finc = clkc_readl(clk->inc_offset); + u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); + + rate *= finc; + if (droff & BIT(0)) + /* Double resolution off */ + do_div(rate, 1 << 28); + else + do_div(rate, 1 << 29); + + return rate; +} + +static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u64 dividend = rate * (1 << 29); + + do_div(dividend, *parent_rate); + dividend *= *parent_rate; + do_div(dividend, 1 << 29); + + return dividend; +} + +static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + u64 dividend = rate * (1 << 29); + struct clk_dto *clk = to_dtoclk(hw); + + do_div(dividend, parent_rate); + clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); + clkc_writel(dividend, clk->inc_offset); + + return 0; +} + +static u8 dto_clk_get_parent(struct clk_hw *hw) +{ + struct clk_dto *clk = to_dtoclk(hw); + + return clkc_readl(clk->src_offset); +} + +/* + * dto need CLK_SET_PARENT_GATE + */ +static int dto_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_dto *clk = to_dtoclk(hw); + + clkc_writel(index, clk->src_offset); + return 0; +} + +static const struct clk_ops dto_ops = { + .is_enabled = dto_clk_is_enabled, + .enable = dto_clk_enable, + .disable = dto_clk_disable, + .recalc_rate = dto_clk_recalc_rate, + .round_rate = dto_clk_round_rate, + .set_rate = dto_clk_set_rate, + .get_parent = dto_clk_get_parent, + .set_parent = dto_clk_set_parent, +}; + +/* dto parent clock as syspllvco/clk1 */ +static const char * const audiodto_clk_parents[] = { + "sys0pll_clk1", + "sys1pll_clk1", + "sys3pll_clk1", +}; + +static struct clk_init_data clk_audiodto_init = { + .name = "audio_dto", + .ops = &dto_ops, + .parent_names = audiodto_clk_parents, + .num_parents = ARRAY_SIZE(audiodto_clk_parents), +}; + +static struct clk_dto clk_audio_dto = { + .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC, + .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC, + .hw = { + .init = &clk_audiodto_init, + }, +}; + +static const char * const disp0dto_clk_parents[] = { + "sys0pll_clk1", + "sys1pll_clk1", + "sys3pll_clk1", +}; + +static struct clk_init_data clk_disp0dto_init = { + .name = "disp0_dto", + .ops = &dto_ops, + .parent_names = disp0dto_clk_parents, + .num_parents = ARRAY_SIZE(disp0dto_clk_parents), +}; + +static struct clk_dto clk_disp0_dto = { + .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC, + .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC, + .hw = { + .init = &clk_disp0dto_init, + }, +}; + +static const char * const disp1dto_clk_parents[] = { + "sys0pll_clk1", + "sys1pll_clk1", + "sys3pll_clk1", +}; + +static struct clk_init_data clk_disp1dto_init = { + .name = "disp1_dto", + .ops = &dto_ops, + .parent_names = disp1dto_clk_parents, + .num_parents = ARRAY_SIZE(disp1dto_clk_parents), +}; + +static struct clk_dto clk_disp1_dto = { + .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC, + .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC, + .hw = { + .init = &clk_disp1dto_init, + }, +}; + +static struct atlas7_div_init_data divider_list[] __initdata = { + /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */ + { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock }, + { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock }, + { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock }, + { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock }, + { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock }, + { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock }, + { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock }, + { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock }, + { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock }, + { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock }, + { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock }, + { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock }, + { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock }, + { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock }, + { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock }, + { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock }, + { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock }, + { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock }, + { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock }, + { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock }, + { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock }, + { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock }, + { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock }, + { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock }, + { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock }, + { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock }, + { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock }, + { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock }, + { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock }, + { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock }, + { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock }, + { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock }, + { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock }, + { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock }, + { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock }, + { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock }, + { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock }, + { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock }, + { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock }, + { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock }, + { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock }, + { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock }, + { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock }, + { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock }, + { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock }, + { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock }, + { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock }, + { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock }, + { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock }, + { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock }, + { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock }, + { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock }, + { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock }, + { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock }, + { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock }, + { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock }, + { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock }, + { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock }, + { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock }, + { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock }, + { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock }, + { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock }, + { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock }, + { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock }, +}; + +static const char * const i2s_clk_parents[] = { + "xin", + "xinw", + "audio_dto", + /* "pwm_i2s01" */ +}; + +static const char * const usbphy_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a1", + "sys1pll_a1", + "sys2pll_a1", + "sys3pll_a1", +}; + +static const char * const btss_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a2", + "sys1pll_a2", + "sys2pll_a2", + "sys3pll_a2", +}; + +static const char * const rgmii_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a3", + "sys1pll_a3", + "sys2pll_a3", + "sys3pll_a3", +}; + +static const char * const cpu_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a4", + "sys1pll_a4", + "cpupll_clk1", +}; + +static const char * const sdphy01_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a5", + "sys1pll_a5", + "sys2pll_a5", + "sys3pll_a5", +}; + +static const char * const sdphy23_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a6", + "sys1pll_a6", + "sys2pll_a6", + "sys3pll_a6", +}; + +static const char * const sdphy45_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a7", + "sys1pll_a7", + "sys2pll_a7", + "sys3pll_a7", +}; + +static const char * const sdphy67_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a8", + "sys1pll_a8", + "sys2pll_a8", + "sys3pll_a8", +}; + +static const char * const can_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a9", + "sys1pll_a9", + "sys2pll_a9", + "sys3pll_a9", +}; + +static const char * const deint_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a10", + "sys1pll_a10", + "sys2pll_a10", + "sys3pll_a10", +}; + +static const char * const nand_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a11", + "sys1pll_a11", + "sys2pll_a11", + "sys3pll_a11", +}; + +static const char * const disp0_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a12", + "sys1pll_a12", + "sys2pll_a12", + "sys3pll_a12", + "disp0_dto", +}; + +static const char * const disp1_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a13", + "sys1pll_a13", + "sys2pll_a13", + "sys3pll_a13", + "disp1_dto", +}; + +static const char * const gpu_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a14", + "sys1pll_a14", + "sys2pll_a14", + "sys3pll_a14", +}; + +static const char * const gnss_clk_parents[] = { + "xin", + "xinw", + "sys0pll_a15", + "sys1pll_a15", + "sys2pll_a15", + "sys3pll_a15", +}; + +static const char * const sys_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const io_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const g2d_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const jpenc_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const vdec_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const gmac_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const usb_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const kas_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const sec_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const sdr_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const vip_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const nocd_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const nocr_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static const char * const tpiu_clk_parents[] = { + "xin", + "xinw", + "sys2pll_a20", + "sys1pll_a20", + "sys1pll_a19", + "sys1pll_a18", + "sys0pll_a20", + "sys1pll_a17", +}; + +static struct atlas7_mux_init_data mux_list[] __initdata = { + /* mux_name, parent_names, parent_num, flags, mux_flags, mux_offset, shift, width */ + { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 }, + { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 }, + { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 }, + { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 }, + { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 }, + { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 }, + { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 }, + { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 }, + { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 }, + { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 }, + { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 }, + { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 }, + { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 }, + { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 }, + { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 }, + { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 }, + { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 }, + { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 }, + { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 }, + { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 }, + { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 }, + { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 }, + { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 }, + { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 }, + { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 }, + { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 }, + { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 }, + { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 }, + { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 }, + { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 }, +}; + + /* new unit should add start from the tail of list */ +static struct atlas7_unit_init_data unit_list[] __initdata = { + /* unit_name, parent_name, flags, regofs, bit, lock */ + { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, &root0_gate_lock }, + { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, &root0_gate_lock }, + { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, &root0_gate_lock }, + { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, &root0_gate_lock }, + { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, &root0_gate_lock }, + { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, &root0_gate_lock }, + { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, &root0_gate_lock }, + { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, &root0_gate_lock }, + { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, &root0_gate_lock }, + { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, &root0_gate_lock }, + { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, &root0_gate_lock }, + { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, &root0_gate_lock }, + { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, &root0_gate_lock }, + { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, &root0_gate_lock }, + { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, &root0_gate_lock }, + { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, &root0_gate_lock }, + { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, &root0_gate_lock }, + { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, &root0_gate_lock }, + { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, &root0_gate_lock }, + { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, &root0_gate_lock }, + { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, &root0_gate_lock }, + { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, &root0_gate_lock }, + { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, &root0_gate_lock }, + { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, &root1_gate_lock }, + { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, &root1_gate_lock }, + { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, &root1_gate_lock }, + { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, &root1_gate_lock }, + { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, &root1_gate_lock }, + { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, &root1_gate_lock }, + { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, &root1_gate_lock }, + { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, &root1_gate_lock }, + { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, &root1_gate_lock }, + { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, &root1_gate_lock }, + { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, &root1_gate_lock }, + { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, &root1_gate_lock }, + { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, &root1_gate_lock }, + { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, &root1_gate_lock }, + { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, &root1_gate_lock }, + { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, &root1_gate_lock }, + { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, &root1_gate_lock }, + { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, &root1_gate_lock }, + { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, &root1_gate_lock }, + { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, &root1_gate_lock }, + { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, &root1_gate_lock }, + { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, &root1_gate_lock }, + { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, &root1_gate_lock }, + { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, &leaf1_gate_lock }, + { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, &leaf1_gate_lock }, + { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, &leaf1_gate_lock }, + { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, &leaf1_gate_lock }, + { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, &leaf1_gate_lock }, + { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, &leaf1_gate_lock }, + { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, &leaf1_gate_lock }, + { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, &leaf1_gate_lock }, + { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, &leaf1_gate_lock }, + { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, &leaf1_gate_lock }, + { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, &leaf1_gate_lock }, + { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, &leaf1_gate_lock }, + { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, &leaf1_gate_lock }, + { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, &leaf1_gate_lock }, + { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, &leaf1_gate_lock }, + { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, &leaf1_gate_lock }, + { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, &leaf1_gate_lock }, + { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, &leaf1_gate_lock }, + { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, &leaf1_gate_lock }, + { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, &leaf1_gate_lock }, + { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, &leaf2_gate_lock }, + { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, &leaf2_gate_lock }, + { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, &leaf2_gate_lock }, + { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, &leaf2_gate_lock }, + { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, &leaf2_gate_lock }, + { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, &leaf2_gate_lock }, + { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, &leaf2_gate_lock }, + { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, &leaf2_gate_lock }, + { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, &leaf2_gate_lock }, + { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, &leaf2_gate_lock }, + { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, &leaf2_gate_lock }, + { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, &leaf2_gate_lock }, + { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, &leaf2_gate_lock }, + { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, &leaf2_gate_lock }, + { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, &leaf2_gate_lock }, + { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, &leaf2_gate_lock }, + { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, &leaf2_gate_lock }, + { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, &leaf2_gate_lock }, + { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, &leaf2_gate_lock }, + { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, &leaf2_gate_lock }, + { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, &leaf3_gate_lock }, + { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, &leaf3_gate_lock }, + { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, &leaf3_gate_lock }, + { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, &leaf3_gate_lock }, + { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, &leaf3_gate_lock }, + { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, &leaf3_gate_lock }, + { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, &leaf3_gate_lock }, + { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, &leaf3_gate_lock }, + { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, &leaf3_gate_lock }, + { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, &leaf3_gate_lock }, + { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, &leaf3_gate_lock }, + { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, &leaf3_gate_lock }, + { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, &leaf3_gate_lock }, + { 99, "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, &leaf3_gate_lock }, + { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, &leaf3_gate_lock }, + { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, &leaf3_gate_lock }, + { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, &leaf4_gate_lock }, + { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, &leaf4_gate_lock }, + { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, &leaf4_gate_lock }, + { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, &leaf4_gate_lock }, + { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, &leaf4_gate_lock }, + { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, &leaf4_gate_lock }, + { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, &leaf4_gate_lock }, + { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, &leaf4_gate_lock }, + { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, &leaf4_gate_lock }, + { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, &leaf4_gate_lock }, + { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, &leaf4_gate_lock }, + { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, &leaf4_gate_lock }, + { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, &leaf4_gate_lock }, + { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, &leaf4_gate_lock }, + { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, &leaf4_gate_lock }, + { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, &leaf4_gate_lock }, + { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, &leaf5_gate_lock }, + { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, &leaf5_gate_lock }, + { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, &leaf5_gate_lock }, + { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, &leaf5_gate_lock }, + { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, &leaf6_gate_lock }, + { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, &leaf6_gate_lock }, + { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, &leaf6_gate_lock }, + { 125, "thcpum_cpudiv4", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock }, + { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, &leaf7_gate_lock }, + { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, &leaf7_gate_lock }, + { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, &leaf7_gate_lock }, + { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, &leaf8_gate_lock }, + { 130, "dmac4_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, &leaf8_gate_lock }, + { 131, "uart6_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, &leaf8_gate_lock }, + { 132, "usp3_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, &leaf8_gate_lock }, + { 133, "a7ca_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, &leaf8_gate_lock }, + { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, &leaf8_gate_lock }, + { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, &leaf8_gate_lock }, + { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, &root1_gate_lock }, + { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, &leaf8_gate_lock }, +}; + +static struct clk *atlas7_clks[ARRAY_SIZE(unit_list)]; + +static int unit_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_unit *clk = to_unitclk(hw); + u32 reg; + + reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; + + return !!(clkc_readl(reg) & BIT(clk->bit)); +} + +static int unit_clk_enable(struct clk_hw *hw) +{ + u32 reg; + struct clk_unit *clk = to_unitclk(hw); + unsigned long flags; + + reg = clk->regofs; + + spin_lock_irqsave(clk->lock, flags); + clkc_writel(BIT(clk->bit), reg); + spin_unlock_irqrestore(clk->lock, flags); + return 0; +} + +static void unit_clk_disable(struct clk_hw *hw) +{ + u32 reg; + struct clk_unit *clk = to_unitclk(hw); + unsigned long flags; + + reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; + + spin_lock_irqsave(clk->lock, flags); + clkc_writel(BIT(clk->bit), reg); + spin_unlock_irqrestore(clk->lock, flags); +} + +static const struct clk_ops unit_clk_ops = { + .is_enabled = unit_clk_is_enabled, + .enable = unit_clk_enable, + .disable = unit_clk_disable, +}; + +static struct clk * __init +atlas7_unit_clk_register(struct device *dev, const char *name, + const char * const parent_name, unsigned long flags, + u32 regofs, u8 bit, spinlock_t *lock) +{ + struct clk *clk; + struct clk_unit *unit; + struct clk_init_data init; + + unit = kzalloc(sizeof(*unit), GFP_KERNEL); + if (!unit) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.parent_names = &parent_name; + init.num_parents = 1; + init.ops = &unit_clk_ops; + init.flags = flags; + + unit->hw.init = &init; + unit->regofs = regofs; + unit->bit = bit; + unit->lock = lock; + + clk = clk_register(dev, &unit->hw); + if (IS_ERR(clk)) + kfree(unit); + + return clk; +} + +static struct atlas7_reset_desc atlas7_reset_unit[] = { + { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock }, /* 0-5 */ + { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock }, + { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock }, + { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock }, + { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock }, + { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock }, + { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock }, /* 6-10 */ + { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock }, + { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock }, + { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock }, + { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock }, + { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock }, /* 11-15 */ + { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock }, + { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock }, + { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock }, + { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock }, + { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock }, /* 16-20 */ + { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock }, + { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock }, + { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock }, + { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock }, + { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock }, /* 21-25 */ + { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock }, + { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock }, + { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock }, + { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock }, + { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock }, /* 26-30 */ + { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock }, + { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock }, + { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock }, + { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock }, + { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock }, /* 31-35 */ + { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock }, + { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock }, + { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock }, + { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock }, + { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock }, /* 36-40 */ + { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock }, + { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock }, + { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock }, + { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock }, + { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock }, /* 41-45 */ + { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock }, + { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock }, + { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock }, + { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock }, + { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock }, /* 46-50 */ + { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock }, + { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock }, + { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock }, + { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock }, + { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock }, /* 51-55 */ + { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock }, + { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock }, + { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock }, + { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock }, + { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock }, /* 56-60 */ + { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock }, + { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock }, + { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock }, + { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock }, + { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock }, /* 61-65 */ + { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock }, + { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock }, + { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock }, + { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock }, + { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock }, /* 66-70 */ + { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock }, + { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock }, + { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock }, + { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock }, + { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock }, /* 71-75 */ + { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock }, + { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock }, + { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock }, + { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock }, + { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock }, /* 76- */ + { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock }, + { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock }, + { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock }, + { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock }, +}; + +static int atlas7_reset_module(struct reset_controller_dev *rcdev, + unsigned long reset_idx) +{ + struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx]; + unsigned long flags; + + /* + * HW suggest unit reset sequence: + * assert sw reset (0) + * setting sw clk_en to if the clock was disabled before reset + * delay 16 clocks + * disable clock (sw clk_en = 0) + * de-assert reset (1) + * after this sequence, restore clock or not is decided by SW + */ + + spin_lock_irqsave(reset->lock, flags); + /* clock enable or not */ + if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) { + clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4); + udelay(2); + clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4); + clkc_writel(1 << reset->rst_bit, reset->rst_ofs); + /* restore clock enable */ + clkc_writel(1 << reset->clk_bit, reset->clk_ofs); + } else { + clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4); + clkc_writel(1 << reset->clk_bit, reset->clk_ofs); + udelay(2); + clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4); + clkc_writel(1 << reset->rst_bit, reset->rst_ofs); + } + spin_unlock_irqrestore(reset->lock, flags); + + return 0; +} + +static struct reset_control_ops atlas7_rst_ops = { + .reset = atlas7_reset_module, +}; + +static struct reset_controller_dev atlas7_rst_ctlr = { + .ops = &atlas7_rst_ops, + .owner = THIS_MODULE, + .of_reset_n_cells = 1, +}; + +static void __init atlas7_clk_init(struct device_node *np) +{ + struct clk *clk; + struct atlas7_div_init_data *div; + struct atlas7_mux_init_data *mux; + struct atlas7_unit_init_data *unit; + int i; + int ret; + + sirfsoc_clk_vbase = of_iomap(np, 0); + if (!sirfsoc_clk_vbase) + panic("unable to map clkc registers\n"); + + of_node_put(np); + + clk = clk_register(NULL, &clk_cpupll.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_mempll.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_sys0pll.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_sys1pll.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_sys2pll.hw); + BUG_ON(!clk); + clk = clk_register(NULL, &clk_sys3pll.hw); + BUG_ON(!clk); + + clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0, + pll_div_table, &cpupll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0, + pll_div_table, &cpupll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0, + pll_div_table, &cpupll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0, + pll_div_table, &mempll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0, + pll_div_table, &mempll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0, + pll_div_table, &mempll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0, + pll_div_table, &sys0pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0, + pll_div_table, &sys0pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0, + pll_div_table, &sys0pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco", + CLK_SET_RATE_PARENT, 1, 2); + + clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0, + pll_div_table, &sys1pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0, + pll_div_table, &sys1pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0, + pll_div_table, &sys1pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco", + CLK_SET_RATE_PARENT, 1, 2); + + clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0, + pll_div_table, &sys2pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0, + pll_div_table, &sys2pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0, + pll_div_table, &sys2pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco", + CLK_SET_RATE_PARENT, 1, 2); + + clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0, + pll_div_table, &sys3pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0, + pll_div_table, &sys3pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0, + sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0, + pll_div_table, &sys3pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco", + CLK_SET_RATE_PARENT, 1, 2); + + BUG_ON(!clk); + clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw", + CLK_SET_RATE_PARENT, 1, 4); + + BUG_ON(!clk); + clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, + 12, 0, &cpupll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, + 13, 0, &cpupll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, + 14, 0, &cpupll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, + 12, 0, &mempll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, + 13, 0, &mempll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, + 14, 0, &mempll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, + 12, 0, &sys0pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, + 13, 0, &sys0pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, + 14, 0, &sys0pll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, + 12, 0, &sys1pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, + 13, 0, &sys1pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, + 14, 0, &sys1pll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, + 12, 0, &sys2pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, + 13, 0, &sys2pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, + 14, 0, &sys2pll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, + 12, 0, &sys3pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, + 13, 0, &sys3pll_ctrl1_lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3", + CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, + 14, 0, &sys3pll_ctrl1_lock); + BUG_ON(!clk); + + clk = clk_register(NULL, &clk_audio_dto.hw); + BUG_ON(!clk); + + clk = clk_register(NULL, &clk_disp0_dto.hw); + BUG_ON(!clk); + + clk = clk_register(NULL, &clk_disp1_dto.hw); + BUG_ON(!clk); + + for (i = 0; i < ARRAY_SIZE(divider_list); i++) { + div = ÷r_list[i]; + clk = clk_register_divider(NULL, div->div_name, + div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset, + div->shift, div->width, 0, div->lock); + BUG_ON(!clk); + clk = clk_register_gate(NULL, div->gate_name, div->div_name, + div->gate_flags, sirfsoc_clk_vbase + div->gate_offset, + div->gate_bit, 0, div->lock); + BUG_ON(!clk); + } + /* ignore selector status register check */ + for (i = 0; i < ARRAY_SIZE(mux_list); i++) { + mux = &mux_list[i]; + clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names, + mux->parent_num, mux->flags, + sirfsoc_clk_vbase + mux->mux_offset, + mux->shift, mux->width, + mux->mux_flags, NULL); + BUG_ON(!clk); + } + + for (i = 0; i < ARRAY_SIZE(unit_list); i++) { + unit = &unit_list[i]; + atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name, + unit->flags, unit->regofs, unit->bit, unit->lock); + BUG_ON(!atlas7_clks[i]); + } + + clk_data.clks = atlas7_clks; + clk_data.clk_num = ARRAY_SIZE(unit_list); + + ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + BUG_ON(ret); + + atlas7_rst_ctlr.of_node = np; + atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit); + reset_controller_register(&atlas7_rst_ctlr); +} +CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init); -- cgit v1.2.3 From 9d699bf4dbe29d8f26769ea81dec4a8c91edcd5a Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 18 May 2015 18:33:47 +0900 Subject: phy: rcar-gen2: Add support for R-Car E2 This patch adds a compatible string to support for R-Car E2. Signed-off-by: Yoshihiro Shimoda Acked-by: Geert Uytterhoeven Acked-by: Simon Horman Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt | 1 + drivers/phy/phy-rcar-gen2.c | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt index 00fc52a034b7..d564ba4f1cf6 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt @@ -6,6 +6,7 @@ This file provides information on what the device node for the R-Car generation Required properties: - compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. + "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. - reg: offset and length of the register block. - #address-cells: number of address cells for the USB channel subnodes, must be <1>. diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index f47bfd8a5368..0050301dce7a 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -195,6 +195,7 @@ static struct phy_ops rcar_gen2_phy_ops = { static const struct of_device_id rcar_gen2_phy_match_table[] = { { .compatible = "renesas,usb-phy-r8a7790" }, { .compatible = "renesas,usb-phy-r8a7791" }, + { .compatible = "renesas,usb-phy-r8a7794" }, { } }; MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table); -- cgit v1.2.3 From 6438de9f3fb5180d78a0422695d0b88c687757d3 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Sat, 11 Apr 2015 17:13:06 +0200 Subject: ima: skip measurement of cgroupfs files and update documentation This patch adds a rule in the default measurement policy to skip inodes in the cgroupfs filesystem. Measurements for this filesystem can be avoided, as all the digests collected have the same value of the digest of an empty file. Furthermore, this patch updates the documentation of IMA policies in Documentation/ABI/testing/ima_policy to make it consistent with the policies set in security/integrity/ima/ima_policy.c. Signed-off-by: Roberto Sassu Signed-off-by: Mimi Zohar --- Documentation/ABI/testing/ima_policy | 17 ++++++++++++----- security/integrity/ima/ima_policy.c | 2 ++ 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/ima_policy b/Documentation/ABI/testing/ima_policy index d0d0c578324c..232e174aa5de 100644 --- a/Documentation/ABI/testing/ima_policy +++ b/Documentation/ABI/testing/ima_policy @@ -49,11 +49,22 @@ Description: dont_measure fsmagic=0x01021994 dont_appraise fsmagic=0x01021994 # RAMFS_MAGIC - dont_measure fsmagic=0x858458f6 dont_appraise fsmagic=0x858458f6 + # DEVPTS_SUPER_MAGIC + dont_measure fsmagic=0x1cd1 + dont_appraise fsmagic=0x1cd1 + # BINFMTFS_MAGIC + dont_measure fsmagic=0x42494e4d + dont_appraise fsmagic=0x42494e4d # SECURITYFS_MAGIC dont_measure fsmagic=0x73636673 dont_appraise fsmagic=0x73636673 + # SELINUX_MAGIC + dont_measure fsmagic=0xf97cff8c + dont_appraise fsmagic=0xf97cff8c + # CGROUP_SUPER_MAGIC + dont_measure fsmagic=0x27e0eb + dont_appraise fsmagic=0x27e0eb measure func=BPRM_CHECK measure func=FILE_MMAP mask=MAY_EXEC @@ -70,10 +81,6 @@ Description: Examples of LSM specific definitions: SELinux: - # SELINUX_MAGIC - dont_measure fsmagic=0xf97cff8c - dont_appraise fsmagic=0xf97cff8c - dont_measure obj_type=var_log_t dont_appraise obj_type=var_log_t dont_measure obj_type=auditd_log_t diff --git a/security/integrity/ima/ima_policy.c b/security/integrity/ima/ima_policy.c index e86b58d459e6..e4244fc43cf1 100644 --- a/security/integrity/ima/ima_policy.c +++ b/security/integrity/ima/ima_policy.c @@ -79,6 +79,8 @@ static struct ima_rule_entry default_rules[] = { {.action = DONT_MEASURE, .fsmagic = BINFMTFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_MEASURE, .fsmagic = SECURITYFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_MEASURE, .fsmagic = SELINUX_MAGIC, .flags = IMA_FSMAGIC}, + {.action = DONT_MEASURE, .fsmagic = CGROUP_SUPER_MAGIC, + .flags = IMA_FSMAGIC}, {.action = MEASURE, .func = MMAP_CHECK, .mask = MAY_EXEC, .flags = IMA_FUNC | IMA_MASK}, {.action = MEASURE, .func = BPRM_CHECK, .mask = MAY_EXEC, -- cgit v1.2.3 From cd025f7f94108995383edddfb61fc8afea6c66a9 Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Tue, 21 Apr 2015 16:54:24 -0400 Subject: ima: do not measure or appraise the NSFS filesystem Include don't appraise or measure rules for the NSFS filesystem in the builtin ima_tcb and ima_appraise_tcb policies. Changelog: - Update documentation Signed-off-by: Mimi Zohar Cc: stable@vger.kernel.org # 3.19 --- Documentation/ABI/testing/ima_policy | 3 +++ security/integrity/ima/ima_policy.c | 2 ++ 2 files changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/ima_policy b/Documentation/ABI/testing/ima_policy index 232e174aa5de..8ae3f57090d4 100644 --- a/Documentation/ABI/testing/ima_policy +++ b/Documentation/ABI/testing/ima_policy @@ -65,6 +65,9 @@ Description: # CGROUP_SUPER_MAGIC dont_measure fsmagic=0x27e0eb dont_appraise fsmagic=0x27e0eb + # NSFS_MAGIC + dont_measure fsmagic=0x6e736673 + dont_appraise fsmagic=0x6e736673 measure func=BPRM_CHECK measure func=FILE_MMAP mask=MAY_EXEC diff --git a/security/integrity/ima/ima_policy.c b/security/integrity/ima/ima_policy.c index e4244fc43cf1..f2421f7fa3c8 100644 --- a/security/integrity/ima/ima_policy.c +++ b/security/integrity/ima/ima_policy.c @@ -81,6 +81,7 @@ static struct ima_rule_entry default_rules[] = { {.action = DONT_MEASURE, .fsmagic = SELINUX_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_MEASURE, .fsmagic = CGROUP_SUPER_MAGIC, .flags = IMA_FSMAGIC}, + {.action = DONT_MEASURE, .fsmagic = NSFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = MEASURE, .func = MMAP_CHECK, .mask = MAY_EXEC, .flags = IMA_FUNC | IMA_MASK}, {.action = MEASURE, .func = BPRM_CHECK, .mask = MAY_EXEC, @@ -101,6 +102,7 @@ static struct ima_rule_entry default_appraise_rules[] = { {.action = DONT_APPRAISE, .fsmagic = BINFMTFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_APPRAISE, .fsmagic = SECURITYFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_APPRAISE, .fsmagic = SELINUX_MAGIC, .flags = IMA_FSMAGIC}, + {.action = DONT_APPRAISE, .fsmagic = NSFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_APPRAISE, .fsmagic = CGROUP_SUPER_MAGIC, .flags = IMA_FSMAGIC}, #ifndef CONFIG_IMA_APPRAISE_SIGNED_INIT {.action = APPRAISE, .fowner = GLOBAL_ROOT_UID, .flags = IMA_FOWNER}, -- cgit v1.2.3 From e465bf6fc55d5ce21fb45a75c3fa613505e6be20 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 21 May 2015 16:06:49 -0700 Subject: DT: i2c: Deprecate adi,adxl34x compatible string DT nodes should use the more specific adi,adxl345 and adi,adxl346 compatible values instead. As the ADXL346 is backward-compatible with the ADXL345, ADXL346 nodes must list both adi,adxl346 and adi,adxl345, in that order. Signed-off-by: Laurent Pinchart Acked-by: Wolfram Sang Signed-off-by: Geert Uytterhoeven Signed-off-by: Dmitry Torokhov --- Documentation/devicetree/bindings/i2c/trivial-devices.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index aaa8325004d2..03db59125569 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -19,8 +19,7 @@ adi,adt7475 +/-1C TDM Extended Temp Range I.C adi,adt7476 +/-1C TDM Extended Temp Range I.C adi,adt7490 +/-1C TDM Extended Temp Range I.C adi,adxl345 Three-Axis Digital Accelerometer -adi,adxl346 Three-Axis Digital Accelerometer -adi,adxl34x Three-Axis Digital Accelerometer +adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) at,24c08 i2c serial eeprom (24cxx) atmel,24c00 i2c serial eeprom (24cxx) atmel,24c01 i2c serial eeprom (24cxx) -- cgit v1.2.3 From 0576722919f13da8430d00e47aa58ba151505d90 Mon Sep 17 00:00:00 2001 From: Stephan Mueller Date: Wed, 20 May 2015 15:21:54 +0200 Subject: crypto: doc - change header file locations Due to the recent update of the kernel crypto API header files, locations of function definitions and their documentation have changed. Signed-off-by: Stephan Mueller Signed-off-by: Herbert Xu --- Documentation/DocBook/crypto-API.tmpl | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/crypto-API.tmpl b/Documentation/DocBook/crypto-API.tmpl index efc8d90a9a3f..5b0551034aa1 100644 --- a/Documentation/DocBook/crypto-API.tmpl +++ b/Documentation/DocBook/crypto-API.tmpl @@ -1671,7 +1671,7 @@ read(opfd, out, outlen); Programming Interface Block Cipher Context Data Structures !Pinclude/linux/crypto.h Block Cipher Context Data Structures -!Finclude/linux/crypto.h aead_request +!Finclude/crypto/aead.h aead_request Block Cipher Algorithm Definitions !Pinclude/linux/crypto.h Block Cipher Algorithm Definitions @@ -1680,7 +1680,7 @@ read(opfd, out, outlen); !Finclude/linux/crypto.h aead_alg !Finclude/linux/crypto.h blkcipher_alg !Finclude/linux/crypto.h cipher_alg -!Finclude/linux/crypto.h rng_alg +!Finclude/crypto/rng.h rng_alg Asynchronous Block Cipher API !Pinclude/linux/crypto.h Asynchronous Block Cipher API @@ -1704,26 +1704,26 @@ read(opfd, out, outlen); !Finclude/linux/crypto.h ablkcipher_request_set_crypt Authenticated Encryption With Associated Data (AEAD) Cipher API -!Pinclude/linux/crypto.h Authenticated Encryption With Associated Data (AEAD) Cipher API -!Finclude/linux/crypto.h crypto_alloc_aead -!Finclude/linux/crypto.h crypto_free_aead -!Finclude/linux/crypto.h crypto_aead_ivsize -!Finclude/linux/crypto.h crypto_aead_authsize -!Finclude/linux/crypto.h crypto_aead_blocksize -!Finclude/linux/crypto.h crypto_aead_setkey -!Finclude/linux/crypto.h crypto_aead_setauthsize -!Finclude/linux/crypto.h crypto_aead_encrypt -!Finclude/linux/crypto.h crypto_aead_decrypt +!Pinclude/crypto/aead.h Authenticated Encryption With Associated Data (AEAD) Cipher API +!Finclude/crypto/aead.h crypto_alloc_aead +!Finclude/crypto/aead.h crypto_free_aead +!Finclude/crypto/aead.h crypto_aead_ivsize +!Finclude/crypto/aead.h crypto_aead_authsize +!Finclude/crypto/aead.h crypto_aead_blocksize +!Finclude/crypto/aead.h crypto_aead_setkey +!Finclude/crypto/aead.h crypto_aead_setauthsize +!Finclude/crypto/aead.h crypto_aead_encrypt +!Finclude/crypto/aead.h crypto_aead_decrypt Asynchronous AEAD Request Handle -!Pinclude/linux/crypto.h Asynchronous AEAD Request Handle -!Finclude/linux/crypto.h crypto_aead_reqsize -!Finclude/linux/crypto.h aead_request_set_tfm -!Finclude/linux/crypto.h aead_request_alloc -!Finclude/linux/crypto.h aead_request_free -!Finclude/linux/crypto.h aead_request_set_callback -!Finclude/linux/crypto.h aead_request_set_crypt -!Finclude/linux/crypto.h aead_request_set_assoc +!Pinclude/crypto/aead.h Asynchronous AEAD Request Handle +!Finclude/crypto/aead.h crypto_aead_reqsize +!Finclude/crypto/aead.h aead_request_set_tfm +!Finclude/crypto/aead.h aead_request_alloc +!Finclude/crypto/aead.h aead_request_free +!Finclude/crypto/aead.h aead_request_set_callback +!Finclude/crypto/aead.h aead_request_set_crypt +!Finclude/crypto/aead.h aead_request_set_assoc Synchronous Block Cipher API !Pinclude/linux/crypto.h Synchronous Block Cipher API -- cgit v1.2.3 From b34e96bdcf2908086a5993827bce1114576a2e75 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 17 Mar 2015 17:15:48 +0100 Subject: USB: atmel: update DT bindings documentation Add documentation for the missing clocks, clock-names, reg and interrupts properties. Signed-off-by: Boris Brezillon Signed-off-by: Nicolas Ferre --- .../devicetree/bindings/usb/atmel-usb.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index e180d56c75db..1be8d7a26c15 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -5,6 +5,13 @@ OHCI Required properties: - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers used in host mode. + - reg: Address and length of the register set for the device + - interrupts: Should contain ehci interrupt + - clocks: Should reference the peripheral, host and system clocks + - clock-names: Should contains two strings + "ohci_clk" for the peripheral clock + "hclk" for the host clock + "uhpck" for the system clock - num-ports: Number of ports. - atmel,vbus-gpio: If present, specifies a gpio that needs to be activated for the bus to be powered. @@ -14,6 +21,8 @@ Required properties: usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; interrupts = <20 4>; num-ports = <2>; }; @@ -23,11 +32,19 @@ EHCI Required properties: - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers used in host mode. + - reg: Address and length of the register set for the device + - interrupts: Should contain ehci interrupt + - clocks: Should reference the peripheral and the UTMI clocks + - clock-names: Should contains two strings + "ehci_clk" for the peripheral clock + "usb_clk" for the UTMI clock usb1: ehci@00800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 4>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; }; AT91 USB device controller @@ -53,6 +70,8 @@ usb1: gadget@fffa4000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfffa4000 0x4000>; interrupts = <10 4>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; atmel,vbus-gpio = <&pioC 5 0>; }; @@ -65,6 +84,10 @@ Required properties: "sama5d3-udc" - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt + - clocks: Should reference the peripheral and host clocks + - clock-names: Should contains two strings + "pclk" for the peripheral clock + "hclk" for the host clock - ep childnode: To specify the number of endpoints and their properties. Optional properties: @@ -86,6 +109,8 @@ usb2: gadget@fff78000 { reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 4 0>; + clocks = <&utmi>, <&udphs_clk>; + clock-names = "hclk", "pclk"; atmel,vbus-gpio = <&pioB 19 0>; ep0 { -- cgit v1.2.3 From 5972edbd8386020347656a37dc014ae838a0adff Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 12 May 2015 16:28:20 -0700 Subject: Documentation: devicetree: add Broadcom SATA PHY binding For 28nm STB chips, based on BCM7445. Signed-off-by: Brian Norris Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/brcm,brcmstb-sata-phy.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt new file mode 100644 index 000000000000..7f81ef90146a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt @@ -0,0 +1,40 @@ +* Broadcom SATA3 PHY for STB + +Required properties: +- compatible: should be one or more of + "brcm,bcm7445-sata-phy" + "brcm,phy-sata3" +- address-cells: should be 1 +- size-cells: should be 0 +- reg: register range for the PHY PCB interface +- reg-names: should be "phy" + +Sub-nodes: + Each port's PHY should be represented as a sub-node. + +Sub-nodes required properties: +- reg: the PHY number +- phy-cells: generic PHY binding; must be 0 +Optional: +- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port + + +Example: + + sata-phy@f0458100 { + compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; + reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + + sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; -- cgit v1.2.3 From b202836a548c1985137b5b648a4afe3cc5959f4b Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 21 May 2015 22:53:45 +0100 Subject: ASoC: qcom: Document apq8016 bindings. This patch updates lpass bindings with apq8016 specific bindings. Tested-by: Kenneth Westfield Acked-by: Kenneth Westfield Signed-off-by: Srinivas Kandagatla Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt index e00732dac939..21c648328be9 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.txt @@ -4,12 +4,21 @@ This node models the Qualcomm Technologies Low-Power Audio SubSystem (LPASS). Required properties: -- compatible : "qcom,lpass-cpu" +- compatible : "qcom,lpass-cpu" or "qcom,apq8016-lpass-cpu" - clocks : Must contain an entry for each entry in clock-names. - clock-names : A list which must include the following entries: * "ahbix-clk" * "mi2s-osr-clk" * "mi2s-bit-clk" + : required clocks for "qcom,lpass-cpu-apq8016" + * "ahbix-clk" + * "mi2s-bit-clk0" + * "mi2s-bit-clk1" + * "mi2s-bit-clk2" + * "mi2s-bit-clk3" + * "pcnoc-mport-clk" + * "pcnoc-sway-clk" + - interrupts : Must contain an entry for each entry in interrupt-names. - interrupt-names : A list which must include the following entries: @@ -22,6 +31,8 @@ Required properties: - reg-names : A list which must include the following entries: * "lpass-lpaif" + + Optional properties: - qcom,adsp : Phandle for the audio DSP node -- cgit v1.2.3 From c2ffa9737878ad9843d1e0e904dc9a086438aff8 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 23 Apr 2015 16:10:23 +0530 Subject: regulator: max8973: add DT parsing of platform specific parameter There are some platform specific parameter required to configure the device like enable external control, DVS gpio etc. Add DT parsing of such properties to make platform specific data. Update DT binding doc accordingly. Signed-off-by: Laxman Dewangan Signed-off-by: Mark Brown --- .../bindings/regulator/max8973-regulator.txt | 14 ++++ drivers/regulator/max8973-regulator.c | 85 +++++++++++++++++----- 2 files changed, 79 insertions(+), 20 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt index 4f15d8a1bfd0..f63de7d8dc23 100644 --- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt @@ -8,6 +8,20 @@ Required properties: Any standard regulator properties can be used to configure the single max8973 DCDC. +Optional properties: + +-maxim,externally-enable: boolean, externally control the regulator output + enable/disable. +-maxim,dvs-gpio: GPIO which is connected to DVS pin of device. +-maxim,dvs-default-state: Default state of GPIO during initialisation. + 1 for HIGH and 0 for LOW. +-maxim,enable-remote-sense: boolean, enable reote sense. +-maxim,enable-falling-slew-rate: boolean, enable falling slew rate. +-maxim,enable-active-discharge: boolean: enable active discharge. +-maxim,enable-frequency-shift: boolean, enable 9% frequency shift. +-maxim,enable-bias-control: boolean, enable bias control. By enabling this + startup delay can be reduce to 20us from 220us. + Example: max8973@1b { diff --git a/drivers/regulator/max8973-regulator.c b/drivers/regulator/max8973-regulator.c index 190db9c3e6b7..1442f920c80e 100644 --- a/drivers/regulator/max8973-regulator.c +++ b/drivers/regulator/max8973-regulator.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -364,6 +365,46 @@ static const struct regmap_config max8973_regmap_config = { .cache_type = REGCACHE_RBTREE, }; +static struct max8973_regulator_platform_data *max8973_parse_dt( + struct device *dev) +{ + struct max8973_regulator_platform_data *pdata; + struct device_node *np = dev->of_node; + int ret; + u32 pval; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return NULL; + + pdata->enable_ext_control = of_property_read_bool(np, + "maxim,externally-enable"); + pdata->dvs_gpio = of_get_named_gpio(np, "maxim,dvs-gpio", 0); + + ret = of_property_read_u32(np, "maxim,dvs-default-state", &pval); + if (!ret) + pdata->dvs_def_state = pval; + + if (of_property_read_bool(np, "maxim,enable-remote-sense")) + pdata->control_flags |= MAX8973_CONTROL_REMOTE_SENSE_ENABLE; + + if (of_property_read_bool(np, "maxim,enable-falling-slew-rate")) + pdata->control_flags |= + MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE; + + if (of_property_read_bool(np, "maxim,enable-active-discharge")) + pdata->control_flags |= + MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE; + + if (of_property_read_bool(np, "maxim,enable-frequency-shift")) + pdata->control_flags |= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE; + + if (of_property_read_bool(np, "maxim,enable-bias-control")) + pdata->control_flags |= MAX8973_BIAS_ENABLE; + + return pdata; +} + static int max8973_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -371,15 +412,24 @@ static int max8973_probe(struct i2c_client *client, struct regulator_config config = { }; struct regulator_dev *rdev; struct max8973_chip *max; + bool pdata_from_dt = false; int ret; pdata = dev_get_platdata(&client->dev); - if (!pdata && !client->dev.of_node) { + if (!pdata && client->dev.of_node) { + pdata = max8973_parse_dt(&client->dev); + pdata_from_dt = true; + } + + if (!pdata) { dev_err(&client->dev, "No Platform data"); return -EIO; } + if (pdata->dvs_gpio == -EPROBE_DEFER) + return -EPROBE_DEFER; + max = devm_kzalloc(&client->dev, sizeof(*max), GFP_KERNEL); if (!max) return -ENOMEM; @@ -403,7 +453,7 @@ static int max8973_probe(struct i2c_client *client, max->desc.uV_step = MAX8973_VOLATGE_STEP; max->desc.n_voltages = MAX8973_BUCK_N_VOLTAGE; - if (!pdata || !pdata->enable_ext_control) { + if (!pdata->enable_ext_control) { max->desc.enable_reg = MAX8973_VOUT; max->desc.enable_mask = MAX8973_VOUT_ENABLE; max->ops.enable = regulator_enable_regmap; @@ -411,15 +461,10 @@ static int max8973_probe(struct i2c_client *client, max->ops.is_enabled = regulator_is_enabled_regmap; } - if (pdata) { - max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL; - max->enable_external_control = pdata->enable_ext_control; - max->curr_gpio_val = pdata->dvs_def_state; - max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state; - } else { - max->dvs_gpio = -EINVAL; - max->curr_vout_reg = MAX8973_VOUT; - } + max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL; + max->enable_external_control = pdata->enable_ext_control; + max->curr_gpio_val = pdata->dvs_def_state; + max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state; max->lru_index[0] = max->curr_vout_reg; @@ -448,18 +493,18 @@ static int max8973_probe(struct i2c_client *client, max->lru_index[max->curr_vout_reg] = 0; } - if (pdata) { - ret = max8973_init_dcdc(max, pdata); - if (ret < 0) { - dev_err(max->dev, "Max8973 Init failed, err = %d\n", ret); - return ret; - } + if (pdata_from_dt) + pdata->reg_init_data = of_get_regulator_init_data(&client->dev, + client->dev.of_node, &max->desc); + + ret = max8973_init_dcdc(max, pdata); + if (ret < 0) { + dev_err(max->dev, "Max8973 Init failed, err = %d\n", ret); + return ret; } config.dev = &client->dev; - config.init_data = pdata ? pdata->reg_init_data : - of_get_regulator_init_data(&client->dev, client->dev.of_node, - &max->desc); + config.init_data = pdata->reg_init_data; config.driver_data = max; config.of_node = client->dev.of_node; config.regmap = max->regmap; -- cgit v1.2.3 From 69eb0980ab4ced06f7c2b4774575337ce32912fb Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 23 Apr 2015 16:10:24 +0530 Subject: regulator: max8973: add mechanism to enable/disable through GPIO MAX8973 supports the voltage output enable/disable through its EN pin. This EN pin can be connected through GPIO from host processor. Add support to provide GPIO number from platform/DT and if it is valid GPIO then enable external control default. Signed-off-by: Laxman Dewangan Signed-off-by: Mark Brown --- .../bindings/regulator/max8973-regulator.txt | 2 ++ drivers/regulator/max8973-regulator.c | 29 +++++++++++++++++----- include/linux/regulator/max8973-regulator.h | 4 +++ 3 files changed, 29 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt index f63de7d8dc23..201a26337387 100644 --- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt @@ -12,6 +12,8 @@ Optional properties: -maxim,externally-enable: boolean, externally control the regulator output enable/disable. +-maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided + then externally enable control will be considered. -maxim,dvs-gpio: GPIO which is connected to DVS pin of device. -maxim,dvs-default-state: Default state of GPIO during initialisation. 1 for HIGH and 0 for LOW. diff --git a/drivers/regulator/max8973-regulator.c b/drivers/regulator/max8973-regulator.c index 1442f920c80e..00cf91cc4c85 100644 --- a/drivers/regulator/max8973-regulator.c +++ b/drivers/regulator/max8973-regulator.c @@ -96,6 +96,7 @@ struct max8973_chip { struct regulator_desc desc; struct regmap *regmap; bool enable_external_control; + int enable_gpio; int dvs_gpio; int lru_index[MAX8973_MAX_VOUT_REG]; int curr_vout_val[MAX8973_MAX_VOUT_REG]; @@ -379,6 +380,7 @@ static struct max8973_regulator_platform_data *max8973_parse_dt( pdata->enable_ext_control = of_property_read_bool(np, "maxim,externally-enable"); + pdata->enable_gpio = of_get_named_gpio(np, "maxim,enable-gpio", 0); pdata->dvs_gpio = of_get_named_gpio(np, "maxim,dvs-gpio", 0); ret = of_property_read_u32(np, "maxim,dvs-default-state", &pval); @@ -409,6 +411,7 @@ static int max8973_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct max8973_regulator_platform_data *pdata; + struct regulator_init_data *ridata; struct regulator_config config = { }; struct regulator_dev *rdev; struct max8973_chip *max; @@ -427,7 +430,8 @@ static int max8973_probe(struct i2c_client *client, return -EIO; } - if (pdata->dvs_gpio == -EPROBE_DEFER) + if ((pdata->dvs_gpio == -EPROBE_DEFER) || + (pdata->enable_gpio == -EPROBE_DEFER)) return -EPROBE_DEFER; max = devm_kzalloc(&client->dev, sizeof(*max), GFP_KERNEL); @@ -453,6 +457,15 @@ static int max8973_probe(struct i2c_client *client, max->desc.uV_step = MAX8973_VOLATGE_STEP; max->desc.n_voltages = MAX8973_BUCK_N_VOLTAGE; + max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL; + max->enable_gpio = (pdata->enable_gpio) ? pdata->enable_gpio : -EINVAL; + max->enable_external_control = pdata->enable_ext_control; + max->curr_gpio_val = pdata->dvs_def_state; + max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state; + + if (gpio_is_valid(max->enable_gpio)) + max->enable_external_control = true; + if (!pdata->enable_ext_control) { max->desc.enable_reg = MAX8973_VOUT; max->desc.enable_mask = MAX8973_VOUT_ENABLE; @@ -461,11 +474,6 @@ static int max8973_probe(struct i2c_client *client, max->ops.is_enabled = regulator_is_enabled_regmap; } - max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL; - max->enable_external_control = pdata->enable_ext_control; - max->curr_gpio_val = pdata->dvs_def_state; - max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state; - max->lru_index[0] = max->curr_vout_reg; if (gpio_is_valid(max->dvs_gpio)) { @@ -509,6 +517,15 @@ static int max8973_probe(struct i2c_client *client, config.of_node = client->dev.of_node; config.regmap = max->regmap; + if (gpio_is_valid(max->enable_gpio)) { + ridata = pdata->reg_init_data; + config.ena_gpio_flags = GPIOF_OUT_INIT_LOW; + if (ridata && (ridata->constraints.always_on || + ridata->constraints.boot_on)) + config.ena_gpio_flags = GPIOF_OUT_INIT_HIGH; + config.ena_gpio = max->enable_gpio; + } + /* Register the regulators */ rdev = devm_regulator_register(&client->dev, &max->desc, &config); if (IS_ERR(rdev)) { diff --git a/include/linux/regulator/max8973-regulator.h b/include/linux/regulator/max8973-regulator.h index f8acc052e353..f6a8a16a0d4d 100644 --- a/include/linux/regulator/max8973-regulator.h +++ b/include/linux/regulator/max8973-regulator.h @@ -58,6 +58,9 @@ * control signal from EN input pin. If it is false then * voltage output will be enabled/disabled through EN bit of * device register. + * @enable_gpio: Enable GPIO. If EN pin is controlled through GPIO from host + * then GPIO number can be provided. If no GPIO controlled then + * it should be -1. * @dvs_gpio: GPIO for dvs. It should be -1 if this is tied with fixed logic. * @dvs_def_state: Default state of dvs. 1 if it is high else 0. */ @@ -65,6 +68,7 @@ struct max8973_regulator_platform_data { struct regulator_init_data *reg_init_data; unsigned long control_flags; bool enable_ext_control; + int enable_gpio; int dvs_gpio; unsigned dvs_def_state:1; }; -- cgit v1.2.3 From 41e177b37bd558980d50609116f7810b46fe4ce0 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Wed, 20 May 2015 11:42:37 +0100 Subject: Documentation: bindings: Add DT bindings for ARM Juno boards. List the required properties and nodes used to describe the ARM Juno boards. Signed-off-by: Liviu Dudau --- Documentation/devicetree/bindings/arm/arm-boards | 66 ++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index b78564b2b201..1a709970e7f7 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -157,3 +157,69 @@ Example: }; }; + +ARM Versatile Express Boards +----------------------------- +For details on the device tree bindings for ARM Versatile Express boards +please consult the vexpress.txt file in the same directory as this file. + +ARM Juno Boards +---------------- +The Juno boards are targeting development for AArch64 systems. The first +iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64, +with the second iteration, Juno r1, mainly aimed at development of PCIe +based systems. Juno r1 also has support for AXI masters placed on the TLX +connectors to join the coherency domain. + +Juno boards are described in a similar way to ARM Versatile Express boards, +with the motherboard part of the hardware being described in a separate file +to highlight the fact that is part of the support infrastructure for the SoC. +Juno device tree bindings also share the Versatile Express bindings as +described under the RS1 memory mapping. + +Required properties (in root node): + compatible = "arm,juno"; /* For Juno r0 board */ + compatible = "arm,juno-r1"; /* For Juno r1 board */ + +Required nodes: +The description for the board must include: + - a "psci" node describing the boot method used for the secondary CPUs. + A detailed description of the bindings used for "psci" nodes is present + in the psci.txt file. + - a "cpus" node describing the available cores and their associated + "enable-method"s. For more details see cpus.txt file. + +Example: + +/dts-v1/; +/ { + model = "ARM Juno development board (r0)"; + compatible = "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A57_0: cpu@0 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + ..... + + A53_0: cpu@100 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + }; + + ..... + }; + +}; -- cgit v1.2.3 From 11e285d8ff3289ce976d4b5b9748c87ac3db8c9d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 21 May 2015 13:57:07 +0200 Subject: DMA-API: Spelling s/This/Think/ Also remove spaces before TABs while we're at it. Signed-off-by: Geert Uytterhoeven Signed-off-by: Jonathan Corbet --- Documentation/DMA-API-HOWTO.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DMA-API-HOWTO.txt b/Documentation/DMA-API-HOWTO.txt index 0f7afb2bb442..16b6f9509cb6 100644 --- a/Documentation/DMA-API-HOWTO.txt +++ b/Documentation/DMA-API-HOWTO.txt @@ -240,7 +240,7 @@ the case would look like this: if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) { using_dac = 1; - consistent_using_dac = 1; + consistent_using_dac = 1; } else if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) { using_dac = 0; consistent_using_dac = 0; @@ -353,7 +353,7 @@ There are two types of DMA mappings: transfer, unmapped right after it (unless you use dma_sync_* below) and for which hardware can optimize for sequential accesses. - This of "streaming" as "asynchronous" or "outside the coherency + Think of "streaming" as "asynchronous" or "outside the coherency domain". Good examples of what to use streaming mappings for are: -- cgit v1.2.3 From cbfa2c52818ada02ca3084e0c50aba8745311bc1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 21 May 2015 14:07:50 +0200 Subject: gpiolib: Grammar s/an negative/a negative/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Jonathan Corbet --- Documentation/gpio/consumer.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt index c21c1313f09e..15ec6d69102c 100644 --- a/Documentation/gpio/consumer.txt +++ b/Documentation/gpio/consumer.txt @@ -290,7 +290,7 @@ corresponding to a given GPIO using the following call: int gpiod_to_irq(const struct gpio_desc *desc) -It will return an IRQ number, or an negative errno code if the mapping can't be +It will return an IRQ number, or a negative errno code if the mapping can't be done (most likely because that particular GPIO cannot be used as IRQ). It is an unchecked error to use a GPIO that wasn't set up as an input using gpiod_direction_input(), or to use an IRQ number that didn't originally come -- cgit v1.2.3 From bde1b29420d71a17d87332db8e20229f251d6c14 Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Wed, 13 May 2015 22:01:07 +0200 Subject: stable: Update documentation to clarify preferred procedure Clearly specify that "Cc: stable@vger.kernel.org" is strongly preferred so that developers understand that the other options should only be used when absolutely required. Also specify how upstream commit ids should be referenced in patches submitted directly to stable (I gathered this from looking at the stable archives), and specify that any modified patches for stable should be clearly documented in the patch description. Signed-off-by: Christoffer Dall Signed-off-by: Jonathan Corbet --- Documentation/stable_kernel_rules.txt | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/stable_kernel_rules.txt b/Documentation/stable_kernel_rules.txt index 58d0ac4df946..3049a612291b 100644 --- a/Documentation/stable_kernel_rules.txt +++ b/Documentation/stable_kernel_rules.txt @@ -59,11 +59,20 @@ For all other submissions, choose one of the following procedures: changelog of your submission, as well as the kernel version you wish it to be applied to. -Option 1 is probably the easiest and most common. Options 2 and 3 are more -useful if the patch isn't deemed worthy at the time it is applied to a public -git tree (for instance, because it deserves more regression testing first). -Option 3 is especially useful if the patch needs some special handling to apply -to an older kernel (e.g., if API's have changed in the meantime). +Option 1 is *strongly* preferred, is the easiest and most common. Options 2 and +3 are more useful if the patch isn't deemed worthy at the time it is applied to +a public git tree (for instance, because it deserves more regression testing +first). Option 3 is especially useful if the patch needs some special handling +to apply to an older kernel (e.g., if API's have changed in the meantime). + +Note that for Option 3, if the patch deviates from the original upstream patch +(for example because it had to be backported) this must be very clearly +documented and justified in the patch description. + +The upstream commit ID must be specified with a separate line above the commit +text, like this: + + commit upstream. Additionally, some patches submitted via Option 1 may have additional patch prerequisites which can be cherry-picked. This can be specified in the following -- cgit v1.2.3 From d012827e8171193e89be83f78b51c9c3fa8f74e4 Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Thu, 21 May 2015 12:15:56 +0200 Subject: pktgen: remove obsolete "max_before_softirq" from pktgen doc And cleanup some whitespaces in pktgen.txt. Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index 747faccc4120..62f5ebb9a2d5 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -1,6 +1,6 @@ - HOWTO for the linux packet generator + HOWTO for the linux packet generator ------------------------------------ Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel @@ -52,11 +52,10 @@ For ixgbe use e.g. "30" resulting in approx 33K interrupts/sec (1/30*10^6): Viewing threads =============== -/proc/net/pktgen/kpktgend_0 -Name: kpktgend_0 max_before_softirq: 10000 -Running: -Stopped: eth1 -Result: OK: max_before_softirq=10000 +/proc/net/pktgen/kpktgend_0 +Running: +Stopped: eth1 +Result: OK: add_device=eth1 Most important are the devices assigned to the thread. Note that a device can only belong to one thread. @@ -69,7 +68,7 @@ The Params section holds configured information. The Current section holds running statistics. The Result is printed after a run or after interruption. Example: -/proc/net/pktgen/eth1 +/proc/net/pktgen/eth1 Params: count 10000000 min_pkt_size: 60 max_pkt_size: 60 frags: 0 delay: 0 clone_skb: 1000000 ifname: eth1 @@ -126,7 +125,7 @@ Examples: To select queue 1 of a given device, use queue_map_min=1 and queue_map_max=1 - pgset "src_mac_count 1" Sets the number of MACs we'll range through. + pgset "src_mac_count 1" Sets the number of MACs we'll range through. The 'minimum' MAC is what you set with srcmac. pgset "dst_mac_count 1" Sets the number of MACs we'll range through. @@ -247,7 +246,6 @@ stop add_device rem_device_all -max_before_softirq ** Device commands: @@ -262,7 +260,7 @@ delay src_mac_count dst_mac_count -pkt_size +pkt_size min_pkt_size max_pkt_size -- cgit v1.2.3 From 91db4b3c89ac2fc33baa6ed0481037115de80beb Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Thu, 21 May 2015 12:16:26 +0200 Subject: pktgen: doc were missing several config options The pktgen.txt documentation over available config options were not complete. Making the list complete by adding the following. Pgcontrol commands: reset Device commands: burst queue_map_min queue_map_max skb_priority tos traffic_class node spi dst6_max dst6_min vlan_cfi vlan_id vlan_p svlan_cfi svlan_id svlan_p Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index 62f5ebb9a2d5..d255434926d1 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -241,6 +241,7 @@ Current commands and configuration options start stop +reset ** Thread commands: @@ -252,6 +253,7 @@ rem_device_all count clone_skb +burst debug frags @@ -264,6 +266,13 @@ pkt_size min_pkt_size max_pkt_size +queue_map_min +queue_map_max +skb_priority + +tos (ipv4) +traffic_class (ipv6) + mpls udp_src_min @@ -272,6 +281,8 @@ udp_src_max udp_dst_min udp_dst_max +node + flag IPSRC_RND IPDST_RND @@ -292,6 +303,8 @@ flag NODE_ALLOC NO_TIMESTAMP +spi (ipsec) + dst_min dst_max @@ -303,8 +316,10 @@ src_mac clear_counters -dst6 src6 +dst6 +dst6_max +dst6_min flows flowlen @@ -314,6 +329,14 @@ ratep xmit_mode +vlan_cfi +vlan_id +vlan_p + +svlan_cfi +svlan_id +svlan_p + References: ftp://robur.slu.se/pub/Linux/net-development/pktgen-testing/ -- cgit v1.2.3 From 2a1ddf27e8189e1d68336c55dd2f305b224ae8f1 Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Thu, 21 May 2015 12:16:40 +0200 Subject: pktgen: document ability to add same device to several threads The pktgen.txt documentation still claimed that adding same device to multiple threads were not supported, but it have been since 2008 via commit e6fce5b916cd7 ("pktgen: multiqueue etc."). Document this and describe the naming scheme dev@X, as the procfile name still need to be unique. Fixes: e6fce5b916cd7 ("pktgen: multiqueue etc.") Signed-off-by: Jesper Dangaard Brouer Acked-by: Alexei Starovoitov Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 77 ++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 27 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index d255434926d1..e7ae8b2939a8 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -50,16 +50,33 @@ For ixgbe use e.g. "30" resulting in approx 33K interrupts/sec (1/30*10^6): # ethtool -C ethX rx-usecs 30 -Viewing threads -=============== -/proc/net/pktgen/kpktgend_0 -Running: -Stopped: eth1 -Result: OK: add_device=eth1 +Kernel threads +============== +Pktgen creates a thread for each CPU with affinity to that CPU. +Which is controlled through procfile /proc/net/pktgen/kpktgend_X. + +Example: /proc/net/pktgen/kpktgend_0 + + Running: + Stopped: eth4@0 + Result: OK: add_device=eth4@0 + +Most important are the devices assigned to the thread. -Most important are the devices assigned to the thread. Note that a -device can only belong to one thread. +The two basic thread commands are: + * add_device DEVICE@NAME -- adds a single device + * rem_device_all -- remove all associated devices +When adding a device to a thread, a corrosponding procfile is created +which is used for configuring this device. Thus, device names need to +be unique. + +To support adding the same device to multiple threads, which is useful +with multi queue NICs, a the device naming scheme is extended with "@": + device@something + +The part after "@" can be anything, but it is custom to use the thread +number. Viewing devices =============== @@ -68,29 +85,32 @@ The Params section holds configured information. The Current section holds running statistics. The Result is printed after a run or after interruption. Example: -/proc/net/pktgen/eth1 +/proc/net/pktgen/eth4@0 -Params: count 10000000 min_pkt_size: 60 max_pkt_size: 60 - frags: 0 delay: 0 clone_skb: 1000000 ifname: eth1 + Params: count 100000 min_pkt_size: 60 max_pkt_size: 60 + frags: 0 delay: 0 clone_skb: 64 ifname: eth4@0 flows: 0 flowlen: 0 - dst_min: 10.10.11.2 dst_max: - src_min: src_max: - src_mac: 00:00:00:00:00:00 dst_mac: 00:04:23:AC:FD:82 - udp_src_min: 9 udp_src_max: 9 udp_dst_min: 9 udp_dst_max: 9 - src_mac_count: 0 dst_mac_count: 0 - Flags: -Current: - pkts-sofar: 10000000 errors: 39664 - started: 1103053986245187us stopped: 1103053999346329us idle: 880401us - seq_num: 10000011 cur_dst_mac_offset: 0 cur_src_mac_offset: 0 - cur_saddr: 0x10a0a0a cur_daddr: 0x20b0a0a - cur_udp_dst: 9 cur_udp_src: 9 + queue_map_min: 0 queue_map_max: 0 + dst_min: 192.168.81.2 dst_max: + src_min: src_max: + src_mac: 90:e2:ba:0a:56:b4 dst_mac: 00:1b:21:3c:9d:f8 + udp_src_min: 9 udp_src_max: 109 udp_dst_min: 9 udp_dst_max: 9 + src_mac_count: 0 dst_mac_count: 0 + Flags: UDPSRC_RND NO_TIMESTAMP QUEUE_MAP_CPU + Current: + pkts-sofar: 100000 errors: 0 + started: 623913381008us stopped: 623913396439us idle: 25us + seq_num: 100001 cur_dst_mac_offset: 0 cur_src_mac_offset: 0 + cur_saddr: 192.168.8.3 cur_daddr: 192.168.81.2 + cur_udp_dst: 9 cur_udp_src: 42 + cur_queue_map: 0 flows: 0 -Result: OK: 13101142(c12220741+d880401) usec, 10000000 (60byte,0frags) - 763292pps 390Mb/sec (390805504bps) errors: 39664 + Result: OK: 15430(c15405+d25) usec, 100000 (60byte,0frags) + 6480562pps 3110Mb/sec (3110669760bps) errors: 0 + -Configuring threads and devices -================================ +Configuring devices +=================== This is done via the /proc interface, and most easily done via pgset as defined in the sample scripts. @@ -221,6 +241,9 @@ Note that when adding devices to a specific CPU it is a good idea to also assign /proc/irq/XX/smp_affinity so that the TX interrupts are bound to the same CPU. This reduces cache bouncing when freeing skbs. +Plus using the device flag QUEUE_MAP_CPU, which maps the SKBs TX queue +to the running threads CPU (directly from smp_processor_id()). + Enable IPsec ============ Default IPsec transformation with ESP encapsulation plus transport mode -- cgit v1.2.3 From 6f09479758be247fef02188a275383ebaddbe291 Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Thu, 21 May 2015 12:17:33 +0200 Subject: pktgen: add sample script pktgen_sample01_simple.sh Add the first basic pktgen samples script pktgen_sample01_simple.sh, which demonstrates the a simple use of the helper functions. Removing pktgen.conf-1-1 as that example should be covered now. The naming scheme pktgen_sampleNN, where NN is a number, should encourage reading the samples in a specific order. Script cause pktgen sending with a single thread and single interface, and introduce flow variation via random UDP source port. Usage example and help: ./pktgen_sample01_simple.sh -i eth4 -m 00:1B:21:3C:9D:F8 -d 192.168.8.2 Usage: ./pktgen_sample01_simple.sh [-vx] -i ethX -i : ($DEV) output interface/device (required) -s : ($PKT_SIZE) packet size -d : ($DEST_IP) destination IP -m : ($DST_MAC) destination MAC-addr -c : ($SKB_CLONE) SKB clones send before alloc new SKB -v : ($VERBOSE) verbose -x : ($DEBUG) debug Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 29 ++++++++++--- samples/pktgen/pktgen.conf-1-1 | 59 -------------------------- samples/pktgen/pktgen_sample01_simple.sh | 71 ++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 65 deletions(-) delete mode 100755 samples/pktgen/pktgen.conf-1-1 create mode 100755 samples/pktgen/pktgen_sample01_simple.sh (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index e7ae8b2939a8..f2f103368a6f 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -219,10 +219,30 @@ Examples: Sample scripts ============== -A collection of small tutorial scripts for pktgen is in the -samples/pktgen directory: +A collection of tutorial scripts and helpers for pktgen is in the +samples/pktgen directory. The helper parameters.sh file support easy +and consistant parameter parsing across the sample scripts. + +Usage example and help: + ./pktgen_sample01_simple.sh -i eth4 -m 00:1B:21:3C:9D:F8 -d 192.168.8.2 + +Usage: ./pktgen_sample01_simple.sh [-vx] -i ethX + -i : ($DEV) output interface/device (required) + -s : ($PKT_SIZE) packet size + -d : ($DEST_IP) destination IP + -m : ($DST_MAC) destination MAC-addr + -t : ($THREADS) threads to start + -c : ($SKB_CLONE) SKB clones send before alloc new SKB + -b : ($BURST) HW level bursting of SKBs + -v : ($VERBOSE) verbose + -x : ($DEBUG) debug + +The global variables being set are also listed. E.g. the required +interface/device parameter "-i" sets variable $DEV. Copy the +pktgen_sampleXX scripts and modify them to fit your own needs. + +The old scripts: -pktgen.conf-1-1 # 1 CPU 1 dev pktgen.conf-1-2 # 1 CPU 2 dev pktgen.conf-2-1 # 2 CPU's 1 dev pktgen.conf-2-2 # 2 CPU's 2 dev @@ -231,9 +251,6 @@ pktgen.conf-1-1-ip6 # 1 CPU 1 dev ipv6 pktgen.conf-1-1-ip6-rdos # 1 CPU 1 dev ipv6 w. route DoS pktgen.conf-1-1-flows # 1 CPU 1 dev multiple flows. -Run in shell: ./pktgen.conf-X-Y -This does all the setup including sending. - Interrupt affinity =================== diff --git a/samples/pktgen/pktgen.conf-1-1 b/samples/pktgen/pktgen.conf-1-1 deleted file mode 100755 index f91daad9e916..000000000000 --- a/samples/pktgen/pktgen.conf-1-1 +++ /dev/null @@ -1,59 +0,0 @@ -#!/bin/bash - -#modprobe pktgen - - -function pgset() { - local result - - echo $1 > $PGDEV - - result=`cat $PGDEV | fgrep "Result: OK:"` - if [ "$result" = "" ]; then - cat $PGDEV | fgrep Result: - fi -} - -# Config Start Here ----------------------------------------------------------- - - -# thread config -# Each CPU has its own thread. One CPU example. We add eth1. - -PGDEV=/proc/net/pktgen/kpktgend_0 - echo "Removing all devices" - pgset "rem_device_all" - echo "Adding eth1" - pgset "add_device eth1" - - -# device config -# delay 0 means maximum speed. - -CLONE_SKB="clone_skb 1000000" -# NIC adds 4 bytes CRC -PKT_SIZE="pkt_size 60" - -# COUNT 0 means forever -#COUNT="count 0" -COUNT="count 10000000" -DELAY="delay 0" - -PGDEV=/proc/net/pktgen/eth1 - echo "Configuring $PGDEV" - pgset "$COUNT" - pgset "$CLONE_SKB" - pgset "$PKT_SIZE" - pgset "$DELAY" - pgset "dst 10.10.11.2" - pgset "dst_mac 00:04:23:08:91:dc" - - -# Time to run -PGDEV=/proc/net/pktgen/pgctrl - - echo "Running... ctrl^C to stop" - trap true INT - pgset "start" - echo "Done" - cat /proc/net/pktgen/eth1 diff --git a/samples/pktgen/pktgen_sample01_simple.sh b/samples/pktgen/pktgen_sample01_simple.sh new file mode 100755 index 000000000000..8c9d318c221b --- /dev/null +++ b/samples/pktgen/pktgen_sample01_simple.sh @@ -0,0 +1,71 @@ +#!/bin/bash +# +# Simple example: +# * pktgen sending with single thread and single interface +# * flow variation via random UDP source port +# +basedir=`dirname $0` +source ${basedir}/functions.sh +root_check_run_with_sudo "$@" + +# Parameter parsing via include +# - go look in parameters.sh to see which setting are avail +# - required param is the interface "-i" stored in $DEV +source ${basedir}/parameters.sh +# +# Set some default params, if they didn't get set +[ -z "$DEST_IP" ] && DEST_IP="198.18.0.42" +[ -z "$CLONE_SKB" ] && CLONE_SKB="0" +# Example enforce param "-m" for dst_mac +[ -z "$DST_MAC" ] && usage && err 2 "Must specify -m dst_mac" + +# Base Config +DELAY="0" # Zero means max speed +COUNT="100000" # Zero means indefinitely + +# Flow variation random source port between min and max +UDP_MIN=9 +UDP_MAX=109 + +# General cleanup everything since last run +# (especially important if other threads were configured by other scripts) +pg_ctrl "reset" + +# Add remove all other devices and add_device $DEV to thread 0 +thread=0 +pg_thread $thread "rem_device_all" +pg_thread $thread "add_device" $DEV + +# How many packets to send (zero means indefinitely) +pg_set $DEV "count $COUNT" + +# Reduce alloc cost by sending same SKB many times +# - this obviously affects the randomness within the packet +pg_set $DEV "clone_skb $CLONE_SKB" + +# Set packet size +pg_set $DEV "pkt_size $PKT_SIZE" + +# Delay between packets (zero means max speed) +pg_set $DEV "delay $DELAY" + +# Flag example disabling timestamping +pg_set $DEV "flag NO_TIMESTAMP" + +# Destination +pg_set $DEV "dst_mac $DST_MAC" +pg_set $DEV "dst $DEST_IP" + +# Setup random UDP port src range +pg_set $DEV "flag UDPSRC_RND" +pg_set $DEV "udp_src_min $UDP_MIN" +pg_set $DEV "udp_src_max $UDP_MAX" + +# start_run +echo "Running... ctrl^C to stop" >&2 +pg_ctrl "start" +echo "Done" >&2 + +# Print results +echo "Result device: $DEV" +cat /proc/net/pktgen/$DEV -- cgit v1.2.3 From 282fb58947e129dea8badf48972ea89d027a76dc Mon Sep 17 00:00:00 2001 From: Jesper Dangaard Brouer Date: Thu, 21 May 2015 12:17:48 +0200 Subject: pktgen: add sample script pktgen_sample02_multiqueue.sh Add the pktgen samples script pktgen_sample02_multiqueue.sh that demonstrates generating packets on multiqueue NICs. Specifically notice the options "-t" that specifies how many kernel threads to activate. Also notice the flag QUEUE_MAP_CPU, which cause the SKB TX queue to be mapped to the CPU running the kernel thread. For best scalability people are also encourage to map NIC IRQ /proc/irq/*/smp_affinity to CPU number. Usage example with "-t" 4 threads and help: ./pktgen_sample02_multiqueue.sh -i eth4 -m 00:1B:21:3C:9D:F8 -t 4 Usage: ./pktgen_sample02_multiqueue.sh [-vx] -i ethX -i : ($DEV) output interface/device (required) -s : ($PKT_SIZE) packet size -d : ($DEST_IP) destination IP -m : ($DST_MAC) destination MAC-addr -t : ($THREADS) threads to start -c : ($SKB_CLONE) SKB clones send before alloc new SKB -b : ($BURST) HW level bursting of SKBs -v : ($VERBOSE) verbose -x : ($DEBUG) debug Removing pktgen.conf-2-1 and pktgen.conf-2-2 as these examples should be covered now. Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller --- Documentation/networking/pktgen.txt | 2 - samples/pktgen/pktgen.conf-2-1 | 66 ------------------------ samples/pktgen/pktgen.conf-2-2 | 73 --------------------------- samples/pktgen/pktgen_sample02_multiqueue.sh | 75 ++++++++++++++++++++++++++++ 4 files changed, 75 insertions(+), 141 deletions(-) delete mode 100755 samples/pktgen/pktgen.conf-2-1 delete mode 100755 samples/pktgen/pktgen.conf-2-2 create mode 100755 samples/pktgen/pktgen_sample02_multiqueue.sh (limited to 'Documentation') diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt index f2f103368a6f..f4be85e96005 100644 --- a/Documentation/networking/pktgen.txt +++ b/Documentation/networking/pktgen.txt @@ -244,8 +244,6 @@ pktgen_sampleXX scripts and modify them to fit your own needs. The old scripts: pktgen.conf-1-2 # 1 CPU 2 dev -pktgen.conf-2-1 # 2 CPU's 1 dev -pktgen.conf-2-2 # 2 CPU's 2 dev pktgen.conf-1-1-rdos # 1 CPU 1 dev w. route DoS pktgen.conf-1-1-ip6 # 1 CPU 1 dev ipv6 pktgen.conf-1-1-ip6-rdos # 1 CPU 1 dev ipv6 w. route DoS diff --git a/samples/pktgen/pktgen.conf-2-1 b/samples/pktgen/pktgen.conf-2-1 deleted file mode 100755 index e108e97d6d89..000000000000 --- a/samples/pktgen/pktgen.conf-2-1 +++ /dev/null @@ -1,66 +0,0 @@ -#!/bin/bash - -#modprobe pktgen - - -function pgset() { - local result - - echo $1 > $PGDEV - - result=`cat $PGDEV | fgrep "Result: OK:"` - if [ "$result" = "" ]; then - cat $PGDEV | fgrep Result: - fi -} - -# Config Start Here ----------------------------------------------------------- - - -# thread config -# Each CPU has its own thread. Two CPU example. We add eth1 to the first -# and leave the second idle. - -PGDEV=/proc/net/pktgen/kpktgend_0 - echo "Removing all devices" - pgset "rem_device_all" - echo "Adding eth1" - pgset "add_device eth1" - -# We need to remove old config since we dont use this thread. We can only -# one NIC on one CPU due to affinity reasons. - -PGDEV=/proc/net/pktgen/kpktgend_1 - echo "Removing all devices" - pgset "rem_device_all" - -# device config -# delay 0 means maximum speed. - -CLONE_SKB="clone_skb 1000000" -# NIC adds 4 bytes CRC -PKT_SIZE="pkt_size 60" - -# COUNT 0 means forever -#COUNT="count 0" -COUNT="count 10000000" -DELAY="delay 0" - -PGDEV=/proc/net/pktgen/eth1 - echo "Configuring $PGDEV" - pgset "$COUNT" - pgset "$CLONE_SKB" - pgset "$PKT_SIZE" - pgset "$DELAY" - pgset "dst 10.10.11.2" - pgset "dst_mac 00:04:23:08:91:dc" - - -# Time to run -PGDEV=/proc/net/pktgen/pgctrl - - echo "Running... ctrl^C to stop" - trap true INT - pgset "start" - echo "Done" - cat /proc/net/pktgen/eth1 diff --git a/samples/pktgen/pktgen.conf-2-2 b/samples/pktgen/pktgen.conf-2-2 deleted file mode 100755 index acea15503e71..000000000000 --- a/samples/pktgen/pktgen.conf-2-2 +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/bash - -#modprobe pktgen - - -function pgset() { - local result - - echo $1 > $PGDEV - - result=`cat $PGDEV | fgrep "Result: OK:"` - if [ "$result" = "" ]; then - cat $PGDEV | fgrep Result: - fi -} - -# Config Start Here ----------------------------------------------------------- - - -# thread config -# Each CPU has its own thread. Two CPU example. We add eth1, eth2 respectively. - -PGDEV=/proc/net/pktgen/kpktgend_0 - echo "Removing all devices" - pgset "rem_device_all" - echo "Adding eth1" - pgset "add_device eth1" - -PGDEV=/proc/net/pktgen/kpktgend_1 - echo "Removing all devices" - pgset "rem_device_all" - echo "Adding eth2" - pgset "add_device eth2" - - -# device config -# delay 0 means maximum speed. - -CLONE_SKB="clone_skb 1000000" -# NIC adds 4 bytes CRC -PKT_SIZE="pkt_size 60" - -# COUNT 0 means forever -#COUNT="count 0" -COUNT="count 10000000" -DELAY="delay 0" - -PGDEV=/proc/net/pktgen/eth1 - echo "Configuring $PGDEV" - pgset "$COUNT" - pgset "$CLONE_SKB" - pgset "$PKT_SIZE" - pgset "$DELAY" - pgset "dst 10.10.11.2" - pgset "dst_mac 00:04:23:08:91:dc" - -PGDEV=/proc/net/pktgen/eth2 - echo "Configuring $PGDEV" - pgset "$COUNT" - pgset "$CLONE_SKB" - pgset "$PKT_SIZE" - pgset "$DELAY" - pgset "dst 192.168.2.2" - pgset "dst_mac 00:04:23:08:91:de" - -# Time to run -PGDEV=/proc/net/pktgen/pgctrl - - echo "Running... ctrl^C to stop" - trap true INT - pgset "start" - echo "Done" - cat /proc/net/pktgen/eth1 /proc/net/pktgen/eth2 diff --git a/samples/pktgen/pktgen_sample02_multiqueue.sh b/samples/pktgen/pktgen_sample02_multiqueue.sh new file mode 100755 index 000000000000..32467aea8e47 --- /dev/null +++ b/samples/pktgen/pktgen_sample02_multiqueue.sh @@ -0,0 +1,75 @@ +#!/bin/bash +# +# Multiqueue: Using pktgen threads for sending on multiple CPUs +# * adding devices to kernel threads +# * notice the naming scheme for keeping device names unique +# * nameing scheme: dev@thread_number +# * flow variation via random UDP source port +# +basedir=`dirname $0` +source ${basedir}/functions.sh +root_check_run_with_sudo "$@" +# +# Required param: -i dev in $DEV +source ${basedir}/parameters.sh + +# Base Config +DELAY="0" # Zero means max speed +COUNT="100000" # Zero means indefinitely +[ -z "$CLONE_SKB" ] && CLONE_SKB="0" + +# Flow variation random source port between min and max +UDP_MIN=9 +UDP_MAX=109 + +# (example of setting default params in your script) +[ -z "$DEST_IP" ] && DEST_IP="198.18.0.42" +[ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff" + +# General cleanup everything since last run +pg_ctrl "reset" + +# Threads are specified with parameter -t value in $THREADS +for ((thread = 0; thread < $THREADS; thread++)); do + # The device name is extended with @name, using thread number to + # make then unique, but any name will do. + dev=${DEV}@${thread} + + # Add remove all other devices and add_device $dev to thread + pg_thread $thread "rem_device_all" + pg_thread $thread "add_device" $dev + + # Notice config queue to map to cpu (mirrors smp_processor_id()) + # It is beneficial to map IRQ /proc/irq/*/smp_affinity 1:1 to CPU number + pg_set $dev "flag QUEUE_MAP_CPU" + + # Base config of dev + pg_set $dev "count $COUNT" + pg_set $dev "clone_skb $CLONE_SKB" + pg_set $dev "pkt_size $PKT_SIZE" + pg_set $dev "delay $DELAY" + + # Flag example disabling timestamping + pg_set $dev "flag NO_TIMESTAMP" + + # Destination + pg_set $dev "dst_mac $DST_MAC" + pg_set $dev "dst $DEST_IP" + + # Setup random UDP port src range + pg_set $dev "flag UDPSRC_RND" + pg_set $dev "udp_src_min $UDP_MIN" + pg_set $dev "udp_src_max $UDP_MAX" +done + +# start_run +echo "Running... ctrl^C to stop" >&2 +pg_ctrl "start" +echo "Done" >&2 + +# Print results +for ((thread = 0; thread < $THREADS; thread++)); do + dev=${DEV}@${thread} + echo "Device: $dev" + cat /proc/net/pktgen/$dev | grep -A2 "Result:" +done -- cgit v1.2.3 From 2f4adaeebfb6f30fd6cd7a1a1dffe31f8e93a4c9 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 18 May 2015 11:19:19 +0200 Subject: Documentation: bindings: document the Berlin ADC driver Following the addition of a Berlin ADC driver, this patch adds the corresponding bindings documentation. Signed-off-by: Antoine Tenart Acked-by: Jonathan Cameron Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/berlin2_adc.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt b/Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt new file mode 100644 index 000000000000..908334c6b07f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/berlin2_adc.txt @@ -0,0 +1,19 @@ +* Berlin Analog to Digital Converter (ADC) + +The Berlin ADC has 8 channels, with one connected to a temperature sensor. +It is part of the system controller register set. The ADC node should be a +sub-node of the system controller node. + +Required properties: +- compatible: must be "marvell,berlin2-adc" +- interrupts: the interrupts for the ADC and the temperature sensor +- interrupt-names: should be "adc" and "tsen" + +Example: + +adc: adc { + compatible = "marvell,berlin2-adc"; + interrupt-parent = <&sic>; + interrupts = <12>, <14>; + interrupt-names = "adc", "tsen"; +}; -- cgit v1.2.3 From 1ce87f21edf6a071a7cc6bc77d628d7c7650d0d8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 22 May 2015 18:17:38 +0200 Subject: iio: Add I/Q modifiers I/Q modifiers can be used to denote signals which are represented by a in-phase and a quadrature component. The ABI documentation describes the I and Q modifiers for current and voltage channels for now as those will be the most likely users. Signed-off-by: Lars-Peter Clausen Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 46 +++++++++++++++++++++++++++++++++ drivers/iio/industrialio-core.c | 2 ++ include/uapi/linux/iio/types.h | 2 ++ 3 files changed, 50 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index f66262c64e2f..bbed111c31b4 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -71,6 +71,8 @@ Description: What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_raw What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_raw +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_raw +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_raw KernelVersion: 2.6.35 Contact: linux-iio@vger.kernel.org Description: @@ -81,6 +83,11 @@ Description: unique to allow association with event codes. Units after application of scale and offset are millivolts. + Channels with 'i' and 'q' modifiers always exist in pairs and both + channels refer to the same signal. The 'i' channel contains the in-phase + component of the signal while the 'q' channel contains the quadrature + component. + What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_raw KernelVersion: 2.6.35 Contact: linux-iio@vger.kernel.org @@ -246,8 +253,16 @@ What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_offset What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_offset What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_offset What: /sys/bus/iio/devices/iio:deviceX/in_voltage_offset +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_offset +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_offset +What: /sys/bus/iio/devices/iio:deviceX/in_voltage_q_offset +What: /sys/bus/iio/devices/iio:deviceX/in_voltage_i_offset What: /sys/bus/iio/devices/iio:deviceX/in_currentY_offset What: /sys/bus/iio/devices/iio:deviceX/in_current_offset +What: /sys/bus/iio/devices/iio:deviceX/in_currentY_i_offset +What: /sys/bus/iio/devices/iio:deviceX/in_currentY_q_offset +What: /sys/bus/iio/devices/iio:deviceX/in_current_q_offset +What: /sys/bus/iio/devices/iio:deviceX/in_current_i_offset What: /sys/bus/iio/devices/iio:deviceX/in_tempY_offset What: /sys/bus/iio/devices/iio:deviceX/in_temp_offset What: /sys/bus/iio/devices/iio:deviceX/in_pressureY_offset @@ -273,14 +288,22 @@ Description: to the _raw output. What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_scale +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_scale +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_scale What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_scale What: /sys/bus/iio/devices/iio:deviceX/in_voltage_scale +What: /sys/bus/iio/devices/iio:deviceX/in_voltage_i_scale +What: /sys/bus/iio/devices/iio:deviceX/in_voltage_q_scale What: /sys/bus/iio/devices/iio:deviceX/in_voltage-voltage_scale What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_scale What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_scale What: /sys/bus/iio/devices/iio:deviceX/in_currentY_scale What: /sys/bus/iio/devices/iio:deviceX/in_currentY_supply_scale What: /sys/bus/iio/devices/iio:deviceX/in_current_scale +What: /sys/bus/iio/devices/iio:deviceX/in_currentY_i_scale +What: /sys/bus/iio/devices/iio:deviceX/in_currentY_q_scale +What: /sys/bus/iio/devices/iio:deviceX/in_current_i_scale +What: /sys/bus/iio/devices/iio:deviceX/in_current_q_scale What: /sys/bus/iio/devices/iio:deviceX/in_accel_scale What: /sys/bus/iio/devices/iio:deviceX/in_accel_peak_scale What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_scale @@ -328,6 +351,10 @@ Description: What /sys/bus/iio/devices/iio:deviceX/in_voltageY_calibscale What /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_calibscale +What /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_calibscale +What /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_calibscale +What /sys/bus/iio/devices/iio:deviceX/in_voltage_i_calibscale +What /sys/bus/iio/devices/iio:deviceX/in_voltage_q_calibscale What /sys/bus/iio/devices/iio:deviceX/in_voltage_calibscale What /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale What /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale @@ -1046,6 +1073,10 @@ What: /sys/.../iio:deviceX/scan_elements/in_timestamp_en What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_en What: /sys/.../iio:deviceX/scan_elements/in_voltageY_en What: /sys/.../iio:deviceX/scan_elements/in_voltageY-voltageZ_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_en +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_en +What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_en +What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_en What: /sys/.../iio:deviceX/scan_elements/in_incli_x_en What: /sys/.../iio:deviceX/scan_elements/in_incli_y_en What: /sys/.../iio:deviceX/scan_elements/in_pressureY_en @@ -1064,6 +1095,10 @@ What: /sys/.../iio:deviceX/scan_elements/in_incli_type What: /sys/.../iio:deviceX/scan_elements/in_voltageY_type What: /sys/.../iio:deviceX/scan_elements/in_voltage_type What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_type +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_type +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_type +What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_type +What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_type What: /sys/.../iio:deviceX/scan_elements/in_timestamp_type What: /sys/.../iio:deviceX/scan_elements/in_pressureY_type What: /sys/.../iio:deviceX/scan_elements/in_pressure_type @@ -1101,6 +1136,10 @@ Description: What: /sys/.../iio:deviceX/scan_elements/in_voltageY_index What: /sys/.../iio:deviceX/scan_elements/in_voltageY_supply_index +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_i_index +What: /sys/.../iio:deviceX/scan_elements/in_voltageY_q_index +What: /sys/.../iio:deviceX/scan_elements/in_voltage_i_index +What: /sys/.../iio:deviceX/scan_elements/in_voltage_q_index What: /sys/.../iio:deviceX/scan_elements/in_accel_x_index What: /sys/.../iio:deviceX/scan_elements/in_accel_y_index What: /sys/.../iio:deviceX/scan_elements/in_accel_z_index @@ -1260,6 +1299,8 @@ Description: or without compensation from tilt sensors. What: /sys/bus/iio/devices/iio:deviceX/in_currentX_raw +What: /sys/bus/iio/devices/iio:deviceX/in_currentX_i_raw +What: /sys/bus/iio/devices/iio:deviceX/in_currentX_q_raw KernelVersion: 3.18 Contact: linux-iio@vger.kernel.org Description: @@ -1268,6 +1309,11 @@ Description: present, output should be considered as processed with the unit in milliamps. + Channels with 'i' and 'q' modifiers always exist in pairs and both + channels refer to the same signal. The 'i' channel contains the in-phase + component of the signal while the 'q' channel contains the quadrature + component. + What: /sys/.../iio:deviceX/in_energy_en What: /sys/.../iio:deviceX/in_distance_en What: /sys/.../iio:deviceX/in_velocity_sqrt(x^2+y^2+z^2)_en diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 9688a88b6198..3524b0de8721 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -101,6 +101,8 @@ static const char * const iio_modifier_names[] = { [IIO_MOD_WALKING] = "walking", [IIO_MOD_STILL] = "still", [IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z] = "sqrt(x^2+y^2+z^2)", + [IIO_MOD_I] = "i", + [IIO_MOD_Q] = "q", }; /* relies on pairs of these shared then separate */ diff --git a/include/uapi/linux/iio/types.h b/include/uapi/linux/iio/types.h index 5c4601935005..2f8b11722204 100644 --- a/include/uapi/linux/iio/types.h +++ b/include/uapi/linux/iio/types.h @@ -70,6 +70,8 @@ enum iio_modifier { IIO_MOD_WALKING, IIO_MOD_STILL, IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z, + IIO_MOD_I, + IIO_MOD_Q, }; enum iio_event_type { -- cgit v1.2.3 From 2a67dfba7fae36af0233452d19b40594f62bc019 Mon Sep 17 00:00:00 2001 From: Urs Fässler Date: Mon, 18 May 2015 15:22:44 +0200 Subject: iio:adc128s052: add support for adc122s021 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Urs Fässler Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/ti-adc128s052.txt | 4 +-- drivers/iio/adc/Kconfig | 4 +-- drivers/iio/adc/ti-adc128s052.c | 30 +++++++++++++++++----- 3 files changed, 28 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt index 42ca7deec97d..15ca6b47958e 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt +++ b/Documentation/devicetree/bindings/iio/adc/ti-adc128s052.txt @@ -1,7 +1,7 @@ -* Texas Instruments' ADC128S052 ADC chip +* Texas Instruments' ADC128S052 and ADC122S021 ADC chip Required properties: - - compatible: Should be "ti,adc128s052" + - compatible: Should be "ti,adc128s052" or "ti,adc122s021" - reg: spi chip select number for the device - vref-supply: The regulator supply for ADC reference voltage diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index cee50de76fb1..7c5565891cb8 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -292,11 +292,11 @@ config TI_ADC081C called ti-adc081c. config TI_ADC128S052 - tristate "Texas Instruments ADC128S052" + tristate "Texas Instruments ADC128S052/ADC122S021" depends on SPI help If you say yes here you get support for Texas Instruments ADC128S052 - chip. + and ADC122S021 chips. This driver can also be built as a module. If so, the module will be called ti-adc128s052. diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c index 655cb564ec54..915be6b60097 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -1,9 +1,10 @@ /* * Copyright (C) 2014 Angelo Compagnucci * - * Driver for Texas Instruments' ADC128S052 ADC chip. - * Datasheet can be found here: + * Driver for Texas Instruments' ADC128S052 and ADC122S021 ADC chip. + * Datasheets can be found here: * http://www.ti.com/lit/ds/symlink/adc128s052.pdf + * http://www.ti.com/lit/ds/symlink/adc122s021.pdf * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,6 +17,11 @@ #include #include +struct adc128_configuration { + const struct iio_chan_spec *channels; + u8 num_channels; +}; + struct adc128 { struct spi_device *spi; @@ -92,7 +98,7 @@ static int adc128_read_raw(struct iio_dev *indio_dev, .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ } -static const struct iio_chan_spec adc128_channels[] = { +static const struct iio_chan_spec adc128s052_channels[] = { ADC128_VOLTAGE_CHANNEL(0), ADC128_VOLTAGE_CHANNEL(1), ADC128_VOLTAGE_CHANNEL(2), @@ -103,6 +109,16 @@ static const struct iio_chan_spec adc128_channels[] = { ADC128_VOLTAGE_CHANNEL(7), }; +static const struct iio_chan_spec adc122s021_channels[] = { + ADC128_VOLTAGE_CHANNEL(0), + ADC128_VOLTAGE_CHANNEL(1), +}; + +static const struct adc128_configuration adc128_config[] = { + { adc128s052_channels, ARRAY_SIZE(adc128s052_channels) }, + { adc122s021_channels, ARRAY_SIZE(adc122s021_channels) }, +}; + static const struct iio_info adc128_info = { .read_raw = adc128_read_raw, .driver_module = THIS_MODULE, @@ -112,6 +128,7 @@ static int adc128_probe(struct spi_device *spi) { struct iio_dev *indio_dev; struct adc128 *adc; + int config = spi_get_device_id(spi)->driver_data; int ret; indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); @@ -128,8 +145,8 @@ static int adc128_probe(struct spi_device *spi) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &adc128_info; - indio_dev->channels = adc128_channels; - indio_dev->num_channels = ARRAY_SIZE(adc128_channels); + indio_dev->channels = adc128_config[config].channels; + indio_dev->num_channels = adc128_config[config].num_channels; adc->reg = devm_regulator_get(&spi->dev, "vref"); if (IS_ERR(adc->reg)) @@ -158,7 +175,8 @@ static int adc128_remove(struct spi_device *spi) } static const struct spi_device_id adc128_id[] = { - { "adc128s052", 0}, + { "adc128s052", 0}, /* index into adc128_config */ + { "adc122s021", 1}, { } }; MODULE_DEVICE_TABLE(spi, adc128_id); -- cgit v1.2.3 From 2219a935963e5eeb19e5abfb99475fcc06bbb804 Mon Sep 17 00:00:00 2001 From: Laurentiu Palcu Date: Thu, 16 Apr 2015 12:31:16 +0300 Subject: power_supply: Add TI BQ24257 charger driver Based on the datasheet found here: http://www.ti.com/lit/ds/symlink/bq24257.pdf Signed-off-by: Laurentiu Palcu Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/bq24257.txt | 21 + drivers/power/Kconfig | 7 + drivers/power/Makefile | 1 + drivers/power/bq24257_charger.c | 863 +++++++++++++++++++++ 4 files changed, 892 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/bq24257.txt create mode 100644 drivers/power/bq24257_charger.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/bq24257.txt b/Documentation/devicetree/bindings/power/bq24257.txt new file mode 100644 index 000000000000..5c9d3940d07c --- /dev/null +++ b/Documentation/devicetree/bindings/power/bq24257.txt @@ -0,0 +1,21 @@ +Binding for TI bq24257 Li-Ion Charger + +Required properties: +- compatible: Should contain one of the following: + * "ti,bq24257" +- reg: integer, i2c address of the device. +- ti,battery-regulation-voltage: integer, maximum charging voltage in uV. +- ti,charge-current: integer, maximum charging current in uA. +- ti,termination-current: integer, charge will be terminated when current in + constant-voltage phase drops below this value (in uA). + +Example: + +bq24257 { + compatible = "ti,bq24257"; + reg = <0x6a>; + + ti,battery-regulation-voltage = <4200000>; + ti,charge-current = <1000000>; + ti,termination-current = <50000>; +}; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 4091fb092d06..20352a7a0081 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -388,6 +388,13 @@ config CHARGER_BQ24190 help Say Y to enable support for the TI BQ24190 battery charger. +config CHARGER_BQ24257 + tristate "TI BQ24257 battery charger driver" + depends on I2C && GPIOLIB + depends on REGMAP_I2C + help + Say Y to enable support for the TI BQ24257 battery charger. + config CHARGER_BQ24735 tristate "TI BQ24735 battery charger support" depends on I2C && GPIOLIB diff --git a/drivers/power/Makefile b/drivers/power/Makefile index b7b0181c95e5..19a1f4186d4d 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o obj-$(CONFIG_CHARGER_BQ2415X) += bq2415x_charger.o obj-$(CONFIG_CHARGER_BQ24190) += bq24190_charger.o +obj-$(CONFIG_CHARGER_BQ24257) += bq24257_charger.o obj-$(CONFIG_CHARGER_BQ24735) += bq24735-charger.o obj-$(CONFIG_POWER_AVS) += avs/ obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o diff --git a/drivers/power/bq24257_charger.c b/drivers/power/bq24257_charger.c new file mode 100644 index 000000000000..ce7f5bbfd5e3 --- /dev/null +++ b/drivers/power/bq24257_charger.c @@ -0,0 +1,863 @@ +/* + * TI BQ24257 charger driver + * + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define BQ24257_REG_1 0x00 +#define BQ24257_REG_2 0x01 +#define BQ24257_REG_3 0x02 +#define BQ24257_REG_4 0x03 +#define BQ24257_REG_5 0x04 +#define BQ24257_REG_6 0x05 +#define BQ24257_REG_7 0x06 + +#define BQ24257_MANUFACTURER "Texas Instruments" +#define BQ24257_STAT_IRQ "stat" +#define BQ24257_PG_GPIO "pg" + +#define BQ24257_ILIM_SET_DELAY 1000 /* msec */ + +enum bq24257_fields { + F_WD_FAULT, F_WD_EN, F_STAT, F_FAULT, /* REG 1 */ + F_RESET, F_IILIMIT, F_EN_STAT, F_EN_TERM, F_CE, F_HZ_MODE, /* REG 2 */ + F_VBAT, F_USB_DET, /* REG 3 */ + F_ICHG, F_ITERM, /* REG 4 */ + F_LOOP_STATUS, F_LOW_CHG, F_DPDM_EN, F_CE_STATUS, F_VINDPM, /* REG 5 */ + F_X2_TMR_EN, F_TMR, F_SYSOFF, F_TS_STAT, /* REG 6 */ + F_VOVP, F_CLR_VDP, F_FORCE_BATDET, F_FORCE_PTM, /* REG 7 */ + + F_MAX_FIELDS +}; + +/* initial field values, converted from uV/uA */ +struct bq24257_init_data { + u8 ichg; /* charge current */ + u8 vbat; /* regulation voltage */ + u8 iterm; /* termination current */ +}; + +struct bq24257_state { + u8 status; + u8 fault; + bool power_good; +}; + +struct bq24257_device { + struct i2c_client *client; + struct device *dev; + struct power_supply *charger; + + struct regmap *rmap; + struct regmap_field *rmap_fields[F_MAX_FIELDS]; + + struct gpio_desc *pg; + + struct delayed_work iilimit_setup_work; + + struct bq24257_init_data init_data; + struct bq24257_state state; + + struct mutex lock; /* protect state data */ +}; + +static bool bq24257_is_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case BQ24257_REG_2: + case BQ24257_REG_4: + return false; + + default: + return true; + } +} + +static const struct regmap_config bq24257_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = BQ24257_REG_7, + .cache_type = REGCACHE_RBTREE, + + .volatile_reg = bq24257_is_volatile_reg, +}; + +static const struct reg_field bq24257_reg_fields[] = { + /* REG 1 */ + [F_WD_FAULT] = REG_FIELD(BQ24257_REG_1, 7, 7), + [F_WD_EN] = REG_FIELD(BQ24257_REG_1, 6, 6), + [F_STAT] = REG_FIELD(BQ24257_REG_1, 4, 5), + [F_FAULT] = REG_FIELD(BQ24257_REG_1, 0, 3), + /* REG 2 */ + [F_RESET] = REG_FIELD(BQ24257_REG_2, 7, 7), + [F_IILIMIT] = REG_FIELD(BQ24257_REG_2, 4, 6), + [F_EN_STAT] = REG_FIELD(BQ24257_REG_2, 3, 3), + [F_EN_TERM] = REG_FIELD(BQ24257_REG_2, 2, 2), + [F_CE] = REG_FIELD(BQ24257_REG_2, 1, 1), + [F_HZ_MODE] = REG_FIELD(BQ24257_REG_2, 0, 0), + /* REG 3 */ + [F_VBAT] = REG_FIELD(BQ24257_REG_3, 2, 7), + [F_USB_DET] = REG_FIELD(BQ24257_REG_3, 0, 1), + /* REG 4 */ + [F_ICHG] = REG_FIELD(BQ24257_REG_4, 3, 7), + [F_ITERM] = REG_FIELD(BQ24257_REG_4, 0, 2), + /* REG 5 */ + [F_LOOP_STATUS] = REG_FIELD(BQ24257_REG_5, 6, 7), + [F_LOW_CHG] = REG_FIELD(BQ24257_REG_5, 5, 5), + [F_DPDM_EN] = REG_FIELD(BQ24257_REG_5, 4, 4), + [F_CE_STATUS] = REG_FIELD(BQ24257_REG_5, 3, 3), + [F_VINDPM] = REG_FIELD(BQ24257_REG_5, 0, 2), + /* REG 6 */ + [F_X2_TMR_EN] = REG_FIELD(BQ24257_REG_6, 7, 7), + [F_TMR] = REG_FIELD(BQ24257_REG_6, 5, 6), + [F_SYSOFF] = REG_FIELD(BQ24257_REG_6, 4, 4), + [F_TS_STAT] = REG_FIELD(BQ24257_REG_6, 0, 2), + /* REG 7 */ + [F_VOVP] = REG_FIELD(BQ24257_REG_7, 5, 7), + [F_CLR_VDP] = REG_FIELD(BQ24257_REG_7, 4, 4), + [F_FORCE_BATDET] = REG_FIELD(BQ24257_REG_7, 3, 3), + [F_FORCE_PTM] = REG_FIELD(BQ24257_REG_7, 2, 2) +}; + +static const u32 bq24257_vbat_map[] = { + 3500000, 3520000, 3540000, 3560000, 3580000, 3600000, 3620000, 3640000, + 3660000, 3680000, 3700000, 3720000, 3740000, 3760000, 3780000, 3800000, + 3820000, 3840000, 3860000, 3880000, 3900000, 3920000, 3940000, 3960000, + 3980000, 4000000, 4020000, 4040000, 4060000, 4080000, 4100000, 4120000, + 4140000, 4160000, 4180000, 4200000, 4220000, 4240000, 4260000, 4280000, + 4300000, 4320000, 4340000, 4360000, 4380000, 4400000, 4420000, 4440000 +}; + +#define BQ24257_VBAT_MAP_SIZE ARRAY_SIZE(bq24257_vbat_map) + +static const u32 bq24257_ichg_map[] = { + 500000, 550000, 600000, 650000, 700000, 750000, 800000, 850000, 900000, + 950000, 1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, + 1350000, 1400000, 1450000, 1500000, 1550000, 1600000, 1650000, 1700000, + 1750000, 1800000, 1850000, 1900000, 1950000, 2000000 +}; + +#define BQ24257_ICHG_MAP_SIZE ARRAY_SIZE(bq24257_ichg_map) + +static const u32 bq24257_iterm_map[] = { + 50000, 75000, 100000, 125000, 150000, 175000, 200000, 225000 +}; + +#define BQ24257_ITERM_MAP_SIZE ARRAY_SIZE(bq24257_iterm_map) + +static int bq24257_field_read(struct bq24257_device *bq, + enum bq24257_fields field_id) +{ + int ret; + int val; + + ret = regmap_field_read(bq->rmap_fields[field_id], &val); + if (ret < 0) + return ret; + + return val; +} + +static int bq24257_field_write(struct bq24257_device *bq, + enum bq24257_fields field_id, u8 val) +{ + return regmap_field_write(bq->rmap_fields[field_id], val); +} + +static u8 bq24257_find_idx(u32 value, const u32 *map, u8 map_size) +{ + u8 idx; + + for (idx = 1; idx < map_size; idx++) + if (value < map[idx]) + break; + + return idx - 1; +} + +enum bq24257_status { + STATUS_READY, + STATUS_CHARGE_IN_PROGRESS, + STATUS_CHARGE_DONE, + STATUS_FAULT, +}; + +enum bq24257_fault { + FAULT_NORMAL, + FAULT_INPUT_OVP, + FAULT_INPUT_UVLO, + FAULT_SLEEP, + FAULT_BAT_TS, + FAULT_BAT_OVP, + FAULT_TS, + FAULT_TIMER, + FAULT_NO_BAT, + FAULT_ISET, + FAULT_INPUT_LDO_LOW, +}; + +static int bq24257_power_supply_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct bq24257_device *bq = power_supply_get_drvdata(psy); + struct bq24257_state state; + + mutex_lock(&bq->lock); + state = bq->state; + mutex_unlock(&bq->lock); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (!state.power_good) + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + else if (state.status == STATUS_READY) + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + else if (state.status == STATUS_CHARGE_IN_PROGRESS) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + else if (state.status == STATUS_CHARGE_DONE) + val->intval = POWER_SUPPLY_STATUS_FULL; + else + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + break; + + case POWER_SUPPLY_PROP_MANUFACTURER: + val->strval = BQ24257_MANUFACTURER; + break; + + case POWER_SUPPLY_PROP_ONLINE: + val->intval = state.power_good; + break; + + case POWER_SUPPLY_PROP_HEALTH: + switch (state.fault) { + case FAULT_NORMAL: + val->intval = POWER_SUPPLY_HEALTH_GOOD; + break; + + case FAULT_INPUT_OVP: + case FAULT_BAT_OVP: + val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + break; + + case FAULT_TS: + case FAULT_BAT_TS: + val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; + break; + + case FAULT_TIMER: + val->intval = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; + break; + + default: + val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + break; + } + + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: + val->intval = bq24257_ichg_map[bq->init_data.ichg]; + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: + val->intval = bq24257_ichg_map[BQ24257_ICHG_MAP_SIZE - 1]; + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + val->intval = bq24257_vbat_map[bq->init_data.vbat]; + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX: + val->intval = bq24257_vbat_map[BQ24257_VBAT_MAP_SIZE - 1]; + break; + + case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT: + val->intval = bq24257_iterm_map[bq->init_data.iterm]; + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int bq24257_get_chip_state(struct bq24257_device *bq, + struct bq24257_state *state) +{ + int ret; + + ret = bq24257_field_read(bq, F_STAT); + if (ret < 0) + return ret; + + state->status = ret; + + ret = bq24257_field_read(bq, F_FAULT); + if (ret < 0) + return ret; + + state->fault = ret; + + state->power_good = !gpiod_get_value_cansleep(bq->pg); + + return 0; +} + +static bool bq24257_state_changed(struct bq24257_device *bq, + struct bq24257_state *new_state) +{ + int ret; + + mutex_lock(&bq->lock); + ret = (bq->state.status != new_state->status || + bq->state.fault != new_state->fault || + bq->state.power_good != new_state->power_good); + mutex_unlock(&bq->lock); + + return ret; +} + +enum bq24257_loop_status { + LOOP_STATUS_NONE, + LOOP_STATUS_IN_DPM, + LOOP_STATUS_IN_CURRENT_LIMIT, + LOOP_STATUS_THERMAL, +}; + +enum bq24257_in_ilimit { + IILIMIT_100, + IILIMIT_150, + IILIMIT_500, + IILIMIT_900, + IILIMIT_1500, + IILIMIT_2000, + IILIMIT_EXT, + IILIMIT_NONE, +}; + +enum bq24257_port_type { + PORT_TYPE_DCP, /* Dedicated Charging Port */ + PORT_TYPE_CDP, /* Charging Downstream Port */ + PORT_TYPE_SDP, /* Standard Downstream Port */ + PORT_TYPE_NON_STANDARD, +}; + +enum bq24257_safety_timer { + SAFETY_TIMER_45, + SAFETY_TIMER_360, + SAFETY_TIMER_540, + SAFETY_TIMER_NONE, +}; + +static int bq24257_iilimit_autoset(struct bq24257_device *bq) +{ + int loop_status; + int iilimit; + int port_type; + int ret; + const u8 new_iilimit[] = { + [PORT_TYPE_DCP] = IILIMIT_2000, + [PORT_TYPE_CDP] = IILIMIT_2000, + [PORT_TYPE_SDP] = IILIMIT_500, + [PORT_TYPE_NON_STANDARD] = IILIMIT_500 + }; + + ret = bq24257_field_read(bq, F_LOOP_STATUS); + if (ret < 0) + goto error; + + loop_status = ret; + + ret = bq24257_field_read(bq, F_IILIMIT); + if (ret < 0) + goto error; + + iilimit = ret; + + /* + * All USB ports should be able to handle 500mA. If not, DPM will lower + * the charging current to accommodate the power source. No need to set + * a lower IILIMIT value. + */ + if (loop_status == LOOP_STATUS_IN_DPM && iilimit == IILIMIT_500) + return 0; + + ret = bq24257_field_read(bq, F_USB_DET); + if (ret < 0) + goto error; + + port_type = ret; + + ret = bq24257_field_write(bq, F_IILIMIT, new_iilimit[port_type]); + if (ret < 0) + goto error; + + ret = bq24257_field_write(bq, F_TMR, SAFETY_TIMER_360); + if (ret < 0) + goto error; + + ret = bq24257_field_write(bq, F_CLR_VDP, 1); + if (ret < 0) + goto error; + + dev_dbg(bq->dev, "port/loop = %d/%d -> iilimit = %d\n", + port_type, loop_status, new_iilimit[port_type]); + + return 0; + +error: + dev_err(bq->dev, "%s: Error communicating with the chip.\n", __func__); + return ret; +} + +static void bq24257_iilimit_setup_work(struct work_struct *work) +{ + struct bq24257_device *bq = container_of(work, struct bq24257_device, + iilimit_setup_work.work); + + bq24257_iilimit_autoset(bq); +} + +static void bq24257_handle_state_change(struct bq24257_device *bq, + struct bq24257_state *new_state) +{ + int ret; + struct bq24257_state old_state; + bool reset_iilimit = false; + bool config_iilimit = false; + + mutex_lock(&bq->lock); + old_state = bq->state; + mutex_unlock(&bq->lock); + + if (!new_state->power_good) { /* power removed */ + cancel_delayed_work_sync(&bq->iilimit_setup_work); + + /* activate D+/D- port detection algorithm */ + ret = bq24257_field_write(bq, F_DPDM_EN, 1); + if (ret < 0) + goto error; + + reset_iilimit = true; + } else if (!old_state.power_good) { /* power inserted */ + config_iilimit = true; + } else if (new_state->fault == FAULT_NO_BAT) { /* battery removed */ + cancel_delayed_work_sync(&bq->iilimit_setup_work); + + reset_iilimit = true; + } else if (old_state.fault == FAULT_NO_BAT) { /* battery connected */ + config_iilimit = true; + } else if (new_state->fault == FAULT_TIMER) { /* safety timer expired */ + dev_err(bq->dev, "Safety timer expired! Battery dead?\n"); + } + + if (reset_iilimit) { + ret = bq24257_field_write(bq, F_IILIMIT, IILIMIT_500); + if (ret < 0) + goto error; + } else if (config_iilimit) { + schedule_delayed_work(&bq->iilimit_setup_work, + msecs_to_jiffies(BQ24257_ILIM_SET_DELAY)); + } + + return; + +error: + dev_err(bq->dev, "%s: Error communicating with the chip.\n", __func__); +} + +static irqreturn_t bq24257_irq_handler_thread(int irq, void *private) +{ + int ret; + struct bq24257_device *bq = private; + struct bq24257_state state; + + ret = bq24257_get_chip_state(bq, &state); + if (ret < 0) + return IRQ_HANDLED; + + if (!bq24257_state_changed(bq, &state)) + return IRQ_HANDLED; + + dev_dbg(bq->dev, "irq(state changed): status/fault/pg = %d/%d/%d\n", + state.status, state.fault, state.power_good); + + bq24257_handle_state_change(bq, &state); + + mutex_lock(&bq->lock); + bq->state = state; + mutex_unlock(&bq->lock); + + power_supply_changed(bq->charger); + + return IRQ_HANDLED; +} + +static int bq24257_hw_init(struct bq24257_device *bq) +{ + int ret; + int i; + struct bq24257_state state; + + const struct { + int field; + u32 value; + } init_data[] = { + {F_ICHG, bq->init_data.ichg}, + {F_VBAT, bq->init_data.vbat}, + {F_ITERM, bq->init_data.iterm} + }; + + /* + * Disable the watchdog timer to prevent the IC from going back to + * default settings after 50 seconds of I2C inactivity. + */ + ret = bq24257_field_write(bq, F_WD_EN, 0); + if (ret < 0) + return ret; + + /* configure the charge currents and voltages */ + for (i = 0; i < ARRAY_SIZE(init_data); i++) { + ret = bq24257_field_write(bq, init_data[i].field, + init_data[i].value); + if (ret < 0) + return ret; + } + + ret = bq24257_get_chip_state(bq, &state); + if (ret < 0) + return ret; + + mutex_lock(&bq->lock); + bq->state = state; + mutex_unlock(&bq->lock); + + if (!state.power_good) + /* activate D+/D- detection algorithm */ + ret = bq24257_field_write(bq, F_DPDM_EN, 1); + else if (state.fault != FAULT_NO_BAT) + ret = bq24257_iilimit_autoset(bq); + + return ret; +} + +static enum power_supply_property bq24257_power_supply_props[] = { + POWER_SUPPLY_PROP_MANUFACTURER, + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX, + POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT, +}; + +static char *bq24257_charger_supplied_to[] = { + "main-battery", +}; + +static const struct power_supply_desc bq24257_power_supply_desc = { + .name = "bq24257-charger", + .type = POWER_SUPPLY_TYPE_USB, + .properties = bq24257_power_supply_props, + .num_properties = ARRAY_SIZE(bq24257_power_supply_props), + .get_property = bq24257_power_supply_get_property, +}; + +static int bq24257_power_supply_init(struct bq24257_device *bq) +{ + struct power_supply_config psy_cfg = { .drv_data = bq, }; + + psy_cfg.supplied_to = bq24257_charger_supplied_to; + psy_cfg.num_supplicants = ARRAY_SIZE(bq24257_charger_supplied_to); + + bq->charger = power_supply_register(bq->dev, &bq24257_power_supply_desc, + &psy_cfg); + if (IS_ERR(bq->charger)) + return PTR_ERR(bq->charger); + + return 0; +} + +static int bq24257_irq_probe(struct bq24257_device *bq) +{ + int ret; + struct gpio_desc *stat_irq; + + stat_irq = devm_gpiod_get_index(bq->dev, BQ24257_STAT_IRQ, 0); + if (IS_ERR(stat_irq)) { + dev_err(bq->dev, "could not probe stat_irq pin\n"); + return PTR_ERR(stat_irq); + } + + ret = gpiod_direction_input(stat_irq); + if (ret < 0) + return ret; + + return gpiod_to_irq(stat_irq); +} + +static int bq24257_pg_gpio_probe(struct bq24257_device *bq) +{ + bq->pg = devm_gpiod_get_index(bq->dev, BQ24257_PG_GPIO, 0); + if (IS_ERR(bq->pg)) { + dev_err(bq->dev, "could not probe PG pin\n"); + return PTR_ERR(bq->pg); + } + + return gpiod_direction_input(bq->pg); +} + +static int bq24257_fw_probe(struct bq24257_device *bq) +{ + int ret; + u32 property; + + ret = device_property_read_u32(bq->dev, "ti,charge-current", &property); + if (ret < 0) + return ret; + + bq->init_data.ichg = bq24257_find_idx(property, bq24257_ichg_map, + BQ24257_ICHG_MAP_SIZE); + + ret = device_property_read_u32(bq->dev, "ti,battery-regulation-voltage", + &property); + if (ret < 0) + return ret; + + bq->init_data.vbat = bq24257_find_idx(property, bq24257_vbat_map, + BQ24257_VBAT_MAP_SIZE); + + ret = device_property_read_u32(bq->dev, "ti,termination-current", + &property); + if (ret < 0) + return ret; + + bq->init_data.iterm = bq24257_find_idx(property, bq24257_iterm_map, + BQ24257_ITERM_MAP_SIZE); + + return 0; +} + +static int bq24257_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + struct device *dev = &client->dev; + struct bq24257_device *bq; + int ret; + int i; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_err(dev, "No support for SMBUS_BYTE_DATA\n"); + return -ENODEV; + } + + bq = devm_kzalloc(dev, sizeof(*bq), GFP_KERNEL); + if (!bq) + return -ENOMEM; + + bq->client = client; + bq->dev = dev; + + mutex_init(&bq->lock); + + bq->rmap = devm_regmap_init_i2c(client, &bq24257_regmap_config); + if (IS_ERR(bq->rmap)) { + dev_err(dev, "failed to allocate register map\n"); + return PTR_ERR(bq->rmap); + } + + for (i = 0; i < ARRAY_SIZE(bq24257_reg_fields); i++) { + const struct reg_field *reg_fields = bq24257_reg_fields; + + bq->rmap_fields[i] = devm_regmap_field_alloc(dev, bq->rmap, + reg_fields[i]); + if (IS_ERR(bq->rmap_fields[i])) { + dev_err(dev, "cannot allocate regmap field\n"); + return PTR_ERR(bq->rmap_fields[i]); + } + } + + i2c_set_clientdata(client, bq); + + INIT_DELAYED_WORK(&bq->iilimit_setup_work, bq24257_iilimit_setup_work); + + if (!dev->platform_data) { + ret = bq24257_fw_probe(bq); + if (ret < 0) { + dev_err(dev, "Cannot read device properties.\n"); + return ret; + } + } else { + return -ENODEV; + } + + /* we can only check Power Good status by probing the PG pin */ + ret = bq24257_pg_gpio_probe(bq); + if (ret < 0) + return ret; + + /* reset all registers to defaults */ + ret = bq24257_field_write(bq, F_RESET, 1); + if (ret < 0) + return ret; + + /* + * Put the RESET bit back to 0, in cache. For some reason the HW always + * returns 1 on this bit, so this is the only way to avoid resetting the + * chip every time we update another field in this register. + */ + ret = bq24257_field_write(bq, F_RESET, 0); + if (ret < 0) + return ret; + + ret = bq24257_hw_init(bq); + if (ret < 0) { + dev_err(dev, "Cannot initialize the chip.\n"); + return ret; + } + + if (client->irq <= 0) + client->irq = bq24257_irq_probe(bq); + + if (client->irq < 0) { + dev_err(dev, "no irq resource found\n"); + return client->irq; + } + + ret = devm_request_threaded_irq(dev, client->irq, NULL, + bq24257_irq_handler_thread, + IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + BQ24257_STAT_IRQ, bq); + if (ret) + return ret; + + ret = bq24257_power_supply_init(bq); + if (ret < 0) + dev_err(dev, "Failed to register power supply\n"); + + return ret; +} + +static int bq24257_remove(struct i2c_client *client) +{ + struct bq24257_device *bq = i2c_get_clientdata(client); + + cancel_delayed_work_sync(&bq->iilimit_setup_work); + + power_supply_unregister(bq->charger); + + bq24257_field_write(bq, F_RESET, 1); /* reset to defaults */ + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int bq24257_suspend(struct device *dev) +{ + struct bq24257_device *bq = dev_get_drvdata(dev); + int ret = 0; + + cancel_delayed_work_sync(&bq->iilimit_setup_work); + + /* reset all registers to default (and activate standalone mode) */ + ret = bq24257_field_write(bq, F_RESET, 1); + if (ret < 0) + dev_err(bq->dev, "Cannot reset chip to standalone mode.\n"); + + return ret; +} + +static int bq24257_resume(struct device *dev) +{ + int ret; + struct bq24257_device *bq = dev_get_drvdata(dev); + + ret = regcache_drop_region(bq->rmap, BQ24257_REG_1, BQ24257_REG_7); + if (ret < 0) + return ret; + + ret = bq24257_field_write(bq, F_RESET, 0); + if (ret < 0) + return ret; + + ret = bq24257_hw_init(bq); + if (ret < 0) { + dev_err(bq->dev, "Cannot init chip after resume.\n"); + return ret; + } + + /* signal userspace, maybe state changed while suspended */ + power_supply_changed(bq->charger); + + return 0; +} +#endif + +static const struct dev_pm_ops bq24257_pm = { + SET_SYSTEM_SLEEP_PM_OPS(bq24257_suspend, bq24257_resume) +}; + +static const struct i2c_device_id bq24257_i2c_ids[] = { + { "bq24257", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, bq24257_i2c_ids); + +static const struct of_device_id bq24257_of_match[] = { + { .compatible = "ti,bq24257", }, + { }, +}; +MODULE_DEVICE_TABLE(of, bq24257_of_match); + +static const struct acpi_device_id bq24257_acpi_match[] = { + {"BQ242570", 0}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, bq24257_acpi_match); + +static struct i2c_driver bq24257_driver = { + .driver = { + .name = "bq24257-charger", + .of_match_table = of_match_ptr(bq24257_of_match), + .acpi_match_table = ACPI_PTR(bq24257_acpi_match), + .pm = &bq24257_pm, + }, + .probe = bq24257_probe, + .remove = bq24257_remove, + .id_table = bq24257_i2c_ids, +}; +module_i2c_driver(bq24257_driver); + +MODULE_AUTHOR("Laurentiu Palcu "); +MODULE_DESCRIPTION("bq24257 charger driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 7e9f8a25a94e21adbcfbe89843a552da191c0079 Mon Sep 17 00:00:00 2001 From: Laurentiu Palcu Date: Tue, 19 May 2015 16:24:39 +0300 Subject: Documentation: devicetree: Add TI BQ25890 bindings Signed-off-by: Laurentiu Palcu Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/bq25890.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/bq25890.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/bq25890.txt b/Documentation/devicetree/bindings/power/bq25890.txt new file mode 100644 index 000000000000..c9dd17d142ad --- /dev/null +++ b/Documentation/devicetree/bindings/power/bq25890.txt @@ -0,0 +1,46 @@ +Binding for TI bq25890 Li-Ion Charger + +Required properties: +- compatible: Should contain one of the following: + * "ti,bq25890" +- reg: integer, i2c address of the device. +- ti,battery-regulation-voltage: integer, maximum charging voltage (in uV); +- ti,charge-current: integer, maximum charging current (in uA); +- ti,termination-current: integer, charge will be terminated when current in + constant-voltage phase drops below this value (in uA); +- ti,precharge-current: integer, maximum charge current during precharge + phase (in uA); +- ti,minimum-sys-voltage: integer, when battery is charging and it is below + minimum system voltage, the system will be regulated above + minimum-sys-voltage setting (in uV); +- ti,boost-voltage: integer, VBUS voltage level in boost mode (in uV); +- ti,boost-max-current: integer, maximum allowed current draw in boost mode + (in uA). + +Optional properties: +- ti,boost-low-freq: boolean, if present boost mode frequency will be 500kHz, + otherwise 1.5MHz; +- ti,use-ilim-pin: boolean, if present the ILIM resistor will be used and the + input current will be the lower between the resistor setting and the IINLIM + register setting; +- ti,thermal-regulation-threshold: integer, temperature above which the charge + current is lowered, to avoid overheating (in degrees Celsius). If omitted, + the default setting will be used (120 degrees); + +Example: + +bq25890 { + compatible = "ti,bq25890"; + reg = <0x6a>; + + ti,battery-regulation-voltage = <4200000>; + ti,charge-current = <1000000>; + ti,termination-current = <50000>; + ti,precharge-current = <128000>; + ti,minimum-sys-voltage = <3600000>; + ti,boost-voltage = <5000000>; + ti,boost-max-current = <1000000>; + + ti,use-ilim-pin; + ti,thermal-regulation-threshold = <120>; +}; -- cgit v1.2.3 From 40f2f2a3255314fc826325f49add1a2fbfc811bd Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Sat, 16 May 2015 17:17:40 +0200 Subject: USB: ehci-platform: support EHCIs with transaction translator Some EHCI controllers have a Transaction Translator built into the root hub. Support this feature in device tree when using the ehci-platform driver by adding a feature flag for it. This is needed to get USB working on NXP LPC18xx/43xx platforms. Signed-off-by: Joachim Eastwood Acked-by: Alan Stern Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/usb-ehci.txt | 2 ++ drivers/usb/host/ehci-platform.c | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt index 0b04fdff9d5a..a12d6012a40f 100644 --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt @@ -13,6 +13,8 @@ Optional properties: - big-endian-desc : boolean, set this for hcds with big-endian descriptors - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc - needs-reset-on-resume : boolean, set this to force EHCI reset after resume + - has-transaction-translator : boolean, set this if EHCI have a Transaction + Translator built into the root hub. - clocks : a list of phandle + clock specifier pairs - phys : phandle + phy specifier pair - phy-names : "usb" diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c index d8a75a51d6d4..ba07f16b13e0 100644 --- a/drivers/usb/host/ehci-platform.c +++ b/drivers/usb/host/ehci-platform.c @@ -202,6 +202,10 @@ static int ehci_platform_probe(struct platform_device *dev) "needs-reset-on-resume")) pdata->reset_on_resume = 1; + if (of_property_read_bool(dev->dev.of_node, + "has-transaction-translator")) + pdata->has_tt = 1; + priv->num_phys = of_count_phandle_with_args(dev->dev.of_node, "phys", "#phy-cells"); priv->num_phys = priv->num_phys > 0 ? priv->num_phys : 1; -- cgit v1.2.3 From 2e1cdfe184b5202d51e0611d7a051e2bea303946 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:09 -0600 Subject: coresight-etm4x: Adding CoreSight ETM4x driver This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block to support HW assisted tracing on ARMv7 and ARMv8 architectures. Signed-off-by: Pratik Patel Signed-off-by: Kaixu Xia Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 15 + drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-etm4x.c | 697 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 391 ++++++++++++ 5 files changed, 1115 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x.h (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x new file mode 100644 index 000000000000..d1e513991fcb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -0,0 +1,15 @@ +What: /sys/bus/coresight/devices/.etm/enable_source +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Enable/disable tracing on this specific trace entiry. + Enabling a source implies the source has been configured + properly and a sink has been identidifed for it. The path + of coresight components linking the source to the sink is + configured and managed automatically by the coresight framework. + +What: /sys/bus/coresight/devices/.etm/cpu +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) The CPU this tracing entity is associated with. diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index fc1f1ae7a49d..8fac01eedee7 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -58,4 +58,15 @@ config CORESIGHT_SOURCE_ETM3X which allows tracing the instructions that a processor is executing This is primarily useful for instruction level tracing. Depending the ETM version data tracing may also be available. + +config CORESIGHT_SOURCE_ETM4X + bool "CoreSight Embedded Trace Macrocell 4.x driver" + depends on ARM64 + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for the ETM4.x tracer module, tracing the + instructions that a processor is executing. This is primarily useful + for instruction level tracing. Depending on the implemented version + data tracing may also be available. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4b4bec890ef5..0af28d43465c 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o +obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c new file mode 100644 index 000000000000..169d8011c8b5 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -0,0 +1,697 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-etm4x.h" + +static int boot_enable; +module_param_named(boot_enable, boot_enable, int, S_IRUGO); + +/* The number of ETMv4 currently registered */ +static int etm4_count; +static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; + +static void etm4_os_unlock(void *info) +{ + struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info; + + /* Writing any value to ETMOSLAR unlocks the trace registers */ + writel_relaxed(0x0, drvdata->base + TRCOSLAR); + isb(); +} + +static bool etm4_arch_supported(u8 arch) +{ + switch (arch) { + case ETM_ARCH_V4: + break; + default: + return false; + } + return true; +} + +static int etm4_trace_id(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + int trace_id = -1; + + if (!drvdata->enable) + return drvdata->trcid; + + pm_runtime_get_sync(drvdata->dev); + spin_lock_irqsave(&drvdata->spinlock, flags); + + CS_UNLOCK(drvdata->base); + trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR); + trace_id &= ETM_TRACEID_MASK; + CS_LOCK(drvdata->base); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + pm_runtime_put(drvdata->dev); + + return trace_id; +} + +static void etm4_enable_hw(void *info) +{ + int i; + struct etmv4_drvdata *drvdata = info; + + CS_UNLOCK(drvdata->base); + + etm4_os_unlock(drvdata); + + /* Disable the trace unit before programming trace registers */ + writel_relaxed(0, drvdata->base + TRCPRGCTLR); + + /* wait for TRCSTATR.IDLE to go up */ + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) + dev_err(drvdata->dev, + "timeout observed when probing at offset %#x\n", + TRCSTATR); + + writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR); + writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR); + /* nothing specific implemented */ + writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); + writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R); + writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R); + writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR); + writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR); + writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR); + writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR); + writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR); + writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR); + writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR); + writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR); + writel_relaxed(drvdata->vissctlr, + drvdata->base + TRCVISSCTLR); + writel_relaxed(drvdata->vipcssctlr, + drvdata->base + TRCVIPCSSCTLR); + for (i = 0; i < drvdata->nrseqstate - 1; i++) + writel_relaxed(drvdata->seq_ctrl[i], + drvdata->base + TRCSEQEVRn(i)); + writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR); + writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR); + writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR); + for (i = 0; i < drvdata->nr_cntr; i++) { + writel_relaxed(drvdata->cntrldvr[i], + drvdata->base + TRCCNTRLDVRn(i)); + writel_relaxed(drvdata->cntr_ctrl[i], + drvdata->base + TRCCNTCTLRn(i)); + writel_relaxed(drvdata->cntr_val[i], + drvdata->base + TRCCNTVRn(i)); + } + for (i = 0; i < drvdata->nr_resource; i++) + writel_relaxed(drvdata->res_ctrl[i], + drvdata->base + TRCRSCTLRn(i)); + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + writel_relaxed(drvdata->ss_ctrl[i], + drvdata->base + TRCSSCCRn(i)); + writel_relaxed(drvdata->ss_status[i], + drvdata->base + TRCSSCSRn(i)); + writel_relaxed(drvdata->ss_pe_cmp[i], + drvdata->base + TRCSSPCICRn(i)); + } + for (i = 0; i < drvdata->nr_addr_cmp; i++) { + writeq_relaxed(drvdata->addr_val[i], + drvdata->base + TRCACVRn(i)); + writeq_relaxed(drvdata->addr_acc[i], + drvdata->base + TRCACATRn(i)); + } + for (i = 0; i < drvdata->numcidc; i++) + writeq_relaxed(drvdata->ctxid_val[i], + drvdata->base + TRCCIDCVRn(i)); + writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0); + writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); + + for (i = 0; i < drvdata->numvmidc; i++) + writeq_relaxed(drvdata->vmid_val[i], + drvdata->base + TRCVMIDCVRn(i)); + writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); + writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); + + /* Enable the trace unit */ + writel_relaxed(1, drvdata->base + TRCPRGCTLR); + + /* wait for TRCSTATR.IDLE to go back down to '0' */ + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) + dev_err(drvdata->dev, + "timeout observed when probing at offset %#x\n", + TRCSTATR); + + CS_LOCK(drvdata->base); + + dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); +} + +static int etm4_enable(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + + pm_runtime_get_sync(drvdata->dev); + spin_lock(&drvdata->spinlock); + + /* + * Executing etm4_enable_hw on the cpu whose ETM is being enabled + * ensures that register writes occur when cpu is powered. + */ + ret = smp_call_function_single(drvdata->cpu, + etm4_enable_hw, drvdata, 1); + if (ret) + goto err; + drvdata->enable = true; + drvdata->sticky_enable = true; + + spin_unlock(&drvdata->spinlock); + + dev_info(drvdata->dev, "ETM tracing enabled\n"); + return 0; +err: + spin_unlock(&drvdata->spinlock); + pm_runtime_put(drvdata->dev); + return ret; +} + +static void etm4_disable_hw(void *info) +{ + u32 control; + struct etmv4_drvdata *drvdata = info; + + CS_UNLOCK(drvdata->base); + + control = readl_relaxed(drvdata->base + TRCPRGCTLR); + + /* EN, bit[0] Trace unit enable bit */ + control &= ~0x1; + + /* make sure everything completes before disabling */ + mb(); + isb(); + writel_relaxed(control, drvdata->base + TRCPRGCTLR); + + CS_LOCK(drvdata->base); + + dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); +} + +static void etm4_disable(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* + * Taking hotplug lock here protects from clocks getting disabled + * with tracing being left on (crash scenario) if user disable occurs + * after cpu online mask indicates the cpu is offline but before the + * DYING hotplug callback is serviced by the ETM driver. + */ + get_online_cpus(); + spin_lock(&drvdata->spinlock); + + /* + * Executing etm4_disable_hw on the cpu whose ETM is being disabled + * ensures that register writes occur when cpu is powered. + */ + smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); + drvdata->enable = false; + + spin_unlock(&drvdata->spinlock); + put_online_cpus(); + + pm_runtime_put(drvdata->dev); + + dev_info(drvdata->dev, "ETM tracing disabled\n"); +} + +static const struct coresight_ops_source etm4_source_ops = { + .trace_id = etm4_trace_id, + .enable = etm4_enable, + .disable = etm4_disable, +}; + +static const struct coresight_ops etm4_cs_ops = { + .source_ops = &etm4_source_ops, +}; + +static ssize_t cpu_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->cpu; + return scnprintf(buf, PAGE_SIZE, "%d\n", val); + +} +static DEVICE_ATTR_RO(cpu); + +static struct attribute *coresight_etmv4_attrs[] = { + &dev_attr_cpu.attr, + NULL, +}; +ATTRIBUTE_GROUPS(coresight_etmv4); + +static void etm4_init_arch_data(void *info) +{ + u32 etmidr0; + u32 etmidr1; + u32 etmidr2; + u32 etmidr3; + u32 etmidr4; + u32 etmidr5; + struct etmv4_drvdata *drvdata = info; + + CS_UNLOCK(drvdata->base); + + /* find all capabilities of the tracing unit */ + etmidr0 = readl_relaxed(drvdata->base + TRCIDR0); + + /* INSTP0, bits[2:1] P0 tracing support field */ + if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + drvdata->instrp0 = true; + else + drvdata->instrp0 = false; + + /* TRCBB, bit[5] Branch broadcast tracing support bit */ + if (BMVAL(etmidr0, 5, 5)) + drvdata->trcbb = true; + else + drvdata->trcbb = false; + + /* TRCCOND, bit[6] Conditional instruction tracing support bit */ + if (BMVAL(etmidr0, 6, 6)) + drvdata->trccond = true; + else + drvdata->trccond = false; + + /* TRCCCI, bit[7] Cycle counting instruction bit */ + if (BMVAL(etmidr0, 7, 7)) + drvdata->trccci = true; + else + drvdata->trccci = false; + + /* RETSTACK, bit[9] Return stack bit */ + if (BMVAL(etmidr0, 9, 9)) + drvdata->retstack = true; + else + drvdata->retstack = false; + + /* NUMEVENT, bits[11:10] Number of events field */ + drvdata->nr_event = BMVAL(etmidr0, 10, 11); + /* QSUPP, bits[16:15] Q element support field */ + drvdata->q_support = BMVAL(etmidr0, 15, 16); + /* TSSIZE, bits[28:24] Global timestamp size field */ + drvdata->ts_size = BMVAL(etmidr0, 24, 28); + + /* base architecture of trace unit */ + etmidr1 = readl_relaxed(drvdata->base + TRCIDR1); + /* + * TRCARCHMIN, bits[7:4] architecture the minor version number + * TRCARCHMAJ, bits[11:8] architecture major versin number + */ + drvdata->arch = BMVAL(etmidr1, 4, 11); + + /* maximum size of resources */ + etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); + /* CIDSIZE, bits[9:5] Indicates the Context ID size */ + drvdata->ctxid_size = BMVAL(etmidr2, 5, 9); + /* VMIDSIZE, bits[14:10] Indicates the VMID size */ + drvdata->vmid_size = BMVAL(etmidr2, 10, 14); + /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ + drvdata->ccsize = BMVAL(etmidr2, 25, 28); + + etmidr3 = readl_relaxed(drvdata->base + TRCIDR3); + /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ + drvdata->ccitmin = BMVAL(etmidr3, 0, 11); + /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ + drvdata->s_ex_level = BMVAL(etmidr3, 16, 19); + /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ + drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23); + + /* + * TRCERR, bit[24] whether a trace unit can trace a + * system error exception. + */ + if (BMVAL(etmidr3, 24, 24)) + drvdata->trc_error = true; + else + drvdata->trc_error = false; + + /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ + if (BMVAL(etmidr3, 25, 25)) + drvdata->syncpr = true; + else + drvdata->syncpr = false; + + /* STALLCTL, bit[26] is stall control implemented? */ + if (BMVAL(etmidr3, 26, 26)) + drvdata->stallctl = true; + else + drvdata->stallctl = false; + + /* SYSSTALL, bit[27] implementation can support stall control? */ + if (BMVAL(etmidr3, 27, 27)) + drvdata->sysstall = true; + else + drvdata->sysstall = false; + + /* NUMPROC, bits[30:28] the number of PEs available for tracing */ + drvdata->nr_pe = BMVAL(etmidr3, 28, 30); + + /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ + if (BMVAL(etmidr3, 31, 31)) + drvdata->nooverflow = true; + else + drvdata->nooverflow = false; + + /* number of resources trace unit supports */ + etmidr4 = readl_relaxed(drvdata->base + TRCIDR4); + /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ + drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3); + /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ + drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15); + /* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */ + drvdata->nr_resource = BMVAL(etmidr4, 16, 19); + /* + * NUMSSCC, bits[23:20] the number of single-shot + * comparator control for tracing + */ + drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); + /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ + drvdata->numcidc = BMVAL(etmidr4, 24, 27); + /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ + drvdata->numvmidc = BMVAL(etmidr4, 28, 31); + + etmidr5 = readl_relaxed(drvdata->base + TRCIDR5); + /* NUMEXTIN, bits[8:0] number of external inputs implemented */ + drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); + /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ + drvdata->trcid_size = BMVAL(etmidr5, 16, 21); + /* ATBTRIG, bit[22] implementation can support ATB triggers? */ + if (BMVAL(etmidr5, 22, 22)) + drvdata->atbtrig = true; + else + drvdata->atbtrig = false; + /* + * LPOVERRIDE, bit[23] implementation supports + * low-power state override + */ + if (BMVAL(etmidr5, 23, 23)) + drvdata->lpoverride = true; + else + drvdata->lpoverride = false; + /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ + drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); + /* NUMCNTR, bits[30:28] number of counters available for tracing */ + drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); + CS_LOCK(drvdata->base); +} + +static void etm4_init_default_data(struct etmv4_drvdata *drvdata) +{ + int i; + + drvdata->pe_sel = 0x0; + drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID | + ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK); + + /* disable all events tracing */ + drvdata->eventctrl0 = 0x0; + drvdata->eventctrl1 = 0x0; + + /* disable stalling */ + drvdata->stall_ctrl = 0x0; + + /* disable timestamp event */ + drvdata->ts_ctrl = 0x0; + + /* enable trace synchronization every 4096 bytes for trace */ + if (drvdata->syncpr == false) + drvdata->syncfreq = 0xC; + + /* + * enable viewInst to trace everything with start-stop logic in + * started state + */ + drvdata->vinst_ctrl |= BIT(0); + /* set initial state of start-stop logic */ + if (drvdata->nr_addr_cmp) + drvdata->vinst_ctrl |= BIT(9); + + /* no address range filtering for ViewInst */ + drvdata->viiectlr = 0x0; + /* no start-stop filtering for ViewInst */ + drvdata->vissctlr = 0x0; + + /* disable seq events */ + for (i = 0; i < drvdata->nrseqstate-1; i++) + drvdata->seq_ctrl[i] = 0x0; + drvdata->seq_rst = 0x0; + drvdata->seq_state = 0x0; + + /* disable external input events */ + drvdata->ext_inp = 0x0; + + for (i = 0; i < drvdata->nr_cntr; i++) { + drvdata->cntrldvr[i] = 0x0; + drvdata->cntr_ctrl[i] = 0x0; + drvdata->cntr_val[i] = 0x0; + } + + for (i = 2; i < drvdata->nr_resource * 2; i++) + drvdata->res_ctrl[i] = 0x0; + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->ss_ctrl[i] = 0x0; + drvdata->ss_pe_cmp[i] = 0x0; + } + + if (drvdata->nr_addr_cmp >= 1) { + drvdata->addr_val[0] = (unsigned long)_stext; + drvdata->addr_val[1] = (unsigned long)_etext; + drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE; + drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE; + } + + for (i = 0; i < drvdata->numcidc; i++) + drvdata->ctxid_val[i] = 0x0; + drvdata->ctxid_mask0 = 0x0; + drvdata->ctxid_mask1 = 0x0; + + for (i = 0; i < drvdata->numvmidc; i++) + drvdata->vmid_val[i] = 0x0; + drvdata->vmid_mask0 = 0x0; + drvdata->vmid_mask1 = 0x0; + + /* + * A trace ID value of 0 is invalid, so let's start at some + * random value that fits in 7 bits. ETMv3.x has 0x10 so let's + * start at 0x20. + */ + drvdata->trcid = 0x20 + drvdata->cpu; +} + +static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action, + void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + + if (!etmdrvdata[cpu]) + goto out; + + switch (action & (~CPU_TASKS_FROZEN)) { + case CPU_STARTING: + spin_lock(&etmdrvdata[cpu]->spinlock); + if (!etmdrvdata[cpu]->os_unlock) { + etm4_os_unlock(etmdrvdata[cpu]); + etmdrvdata[cpu]->os_unlock = true; + } + + if (etmdrvdata[cpu]->enable) + etm4_enable_hw(etmdrvdata[cpu]); + spin_unlock(&etmdrvdata[cpu]->spinlock); + break; + + case CPU_ONLINE: + if (etmdrvdata[cpu]->boot_enable && + !etmdrvdata[cpu]->sticky_enable) + coresight_enable(etmdrvdata[cpu]->csdev); + break; + + case CPU_DYING: + spin_lock(&etmdrvdata[cpu]->spinlock); + if (etmdrvdata[cpu]->enable) + etm4_disable_hw(etmdrvdata[cpu]); + spin_unlock(&etmdrvdata[cpu]->spinlock); + break; + } +out: + return NOTIFY_OK; +} + +static struct notifier_block etm4_cpu_notifier = { + .notifier_call = etm4_cpu_callback, +}; + +static int etm4_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata = NULL; + struct etmv4_drvdata *drvdata; + struct resource *res = &adev->res; + struct coresight_desc *desc; + struct device_node *np = adev->dev.of_node; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + if (np) { + pdata = of_get_coresight_platform_data(dev, np); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + } + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->cpu = pdata ? pdata->cpu : 0; + + get_online_cpus(); + etmdrvdata[drvdata->cpu] = drvdata; + + if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1)) + drvdata->os_unlock = true; + + if (smp_call_function_single(drvdata->cpu, + etm4_init_arch_data, drvdata, 1)) + dev_err(dev, "ETM arch init failed\n"); + + if (!etm4_count++) + register_hotcpu_notifier(&etm4_cpu_notifier); + + put_online_cpus(); + + if (etm4_arch_supported(drvdata->arch) == false) { + ret = -EINVAL; + goto err_arch_supported; + } + etm4_init_default_data(drvdata); + + pm_runtime_put(&adev->dev); + + desc->type = CORESIGHT_DEV_TYPE_SOURCE; + desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; + desc->ops = &etm4_cs_ops; + desc->pdata = pdata; + desc->dev = dev; + desc->groups = coresight_etmv4_groups; + drvdata->csdev = coresight_register(desc); + if (IS_ERR(drvdata->csdev)) { + ret = PTR_ERR(drvdata->csdev); + goto err_coresight_register; + } + + dev_info(dev, "%s initialized\n", (char *)id->data); + + if (boot_enable) { + coresight_enable(drvdata->csdev); + drvdata->boot_enable = true; + } + + return 0; + +err_arch_supported: + pm_runtime_put(&adev->dev); +err_coresight_register: + if (--etm4_count == 0) + unregister_hotcpu_notifier(&etm4_cpu_notifier); + return ret; +} + +static int etm4_remove(struct amba_device *adev) +{ + struct etmv4_drvdata *drvdata = amba_get_drvdata(adev); + + coresight_unregister(drvdata->csdev); + if (--etm4_count == 0) + unregister_hotcpu_notifier(&etm4_cpu_notifier); + + return 0; +} + +static struct amba_id etm4_ids[] = { + { /* ETM 4.0 - Qualcomm */ + .id = 0x0003b95d, + .mask = 0x0003ffff, + .data = "ETM 4.0", + }, + { /* ETM 4.0 - Juno board */ + .id = 0x000bb95e, + .mask = 0x000fffff, + .data = "ETM 4.0", + }, + { 0, 0}, +}; + +static struct amba_driver etm4x_driver = { + .drv = { + .name = "coresight-etm4x", + }, + .probe = etm4_probe, + .remove = etm4_remove, + .id_table = etm4_ids, +}; + +module_amba_driver(etm4x_driver); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h new file mode 100644 index 000000000000..e08e983dd2d9 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -0,0 +1,391 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CORESIGHT_CORESIGHT_ETM_H +#define _CORESIGHT_CORESIGHT_ETM_H + +#include +#include "coresight-priv.h" + +/* + * Device registers: + * 0x000 - 0x2FC: Trace registers + * 0x300 - 0x314: Management registers + * 0x318 - 0xEFC: Trace registers + * 0xF00: Management registers + * 0xFA0 - 0xFA4: Trace registers + * 0xFA8 - 0xFFC: Management registers + */ +/* Trace registers (0x000-0x2FC) */ +/* Main control and configuration registers */ +#define TRCPRGCTLR 0x004 +#define TRCPROCSELR 0x008 +#define TRCSTATR 0x00C +#define TRCCONFIGR 0x010 +#define TRCAUXCTLR 0x018 +#define TRCEVENTCTL0R 0x020 +#define TRCEVENTCTL1R 0x024 +#define TRCSTALLCTLR 0x02C +#define TRCTSCTLR 0x030 +#define TRCSYNCPR 0x034 +#define TRCCCCTLR 0x038 +#define TRCBBCTLR 0x03C +#define TRCTRACEIDR 0x040 +#define TRCQCTLR 0x044 +/* Filtering control registers */ +#define TRCVICTLR 0x080 +#define TRCVIIECTLR 0x084 +#define TRCVISSCTLR 0x088 +#define TRCVIPCSSCTLR 0x08C +#define TRCVDCTLR 0x0A0 +#define TRCVDSACCTLR 0x0A4 +#define TRCVDARCCTLR 0x0A8 +/* Derived resources registers */ +#define TRCSEQEVRn(n) (0x100 + (n * 4)) +#define TRCSEQRSTEVR 0x118 +#define TRCSEQSTR 0x11C +#define TRCEXTINSELR 0x120 +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) +#define TRCCNTVRn(n) (0x160 + (n * 4)) +/* ID registers */ +#define TRCIDR8 0x180 +#define TRCIDR9 0x184 +#define TRCIDR10 0x188 +#define TRCIDR11 0x18C +#define TRCIDR12 0x190 +#define TRCIDR13 0x194 +#define TRCIMSPEC0 0x1C0 +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) +#define TRCIDR0 0x1E0 +#define TRCIDR1 0x1E4 +#define TRCIDR2 0x1E8 +#define TRCIDR3 0x1EC +#define TRCIDR4 0x1F0 +#define TRCIDR5 0x1F4 +#define TRCIDR6 0x1F8 +#define TRCIDR7 0x1FC +/* Resource selection registers */ +#define TRCRSCTLRn(n) (0x200 + (n * 4)) +/* Single-shot comparator registers */ +#define TRCSSCCRn(n) (0x280 + (n * 4)) +#define TRCSSCSRn(n) (0x2A0 + (n * 4)) +#define TRCSSPCICRn(n) (0x2C0 + (n * 4)) +/* Management registers (0x300-0x314) */ +#define TRCOSLAR 0x300 +#define TRCOSLSR 0x304 +#define TRCPDCR 0x310 +#define TRCPDSR 0x314 +/* Trace registers (0x318-0xEFC) */ +/* Comparator registers */ +#define TRCACVRn(n) (0x400 + (n * 8)) +#define TRCACATRn(n) (0x480 + (n * 8)) +#define TRCDVCVRn(n) (0x500 + (n * 16)) +#define TRCDVCMRn(n) (0x580 + (n * 16)) +#define TRCCIDCVRn(n) (0x600 + (n * 8)) +#define TRCVMIDCVRn(n) (0x640 + (n * 8)) +#define TRCCIDCCTLR0 0x680 +#define TRCCIDCCTLR1 0x684 +#define TRCVMIDCCTLR0 0x688 +#define TRCVMIDCCTLR1 0x68C +/* Management register (0xF00) */ +/* Integration control registers */ +#define TRCITCTRL 0xF00 +/* Trace registers (0xFA0-0xFA4) */ +/* Claim tag registers */ +#define TRCCLAIMSET 0xFA0 +#define TRCCLAIMCLR 0xFA4 +/* Management registers (0xFA8-0xFFC) */ +#define TRCDEVAFF0 0xFA8 +#define TRCDEVAFF1 0xFAC +#define TRCLAR 0xFB0 +#define TRCLSR 0xFB4 +#define TRCAUTHSTATUS 0xFB8 +#define TRCDEVARCH 0xFBC +#define TRCDEVID 0xFC8 +#define TRCDEVTYPE 0xFCC +#define TRCPIDR4 0xFD0 +#define TRCPIDR5 0xFD4 +#define TRCPIDR6 0xFD8 +#define TRCPIDR7 0xFDC +#define TRCPIDR0 0xFE0 +#define TRCPIDR1 0xFE4 +#define TRCPIDR2 0xFE8 +#define TRCPIDR3 0xFEC +#define TRCCIDR0 0xFF0 +#define TRCCIDR1 0xFF4 +#define TRCCIDR2 0xFF8 +#define TRCCIDR3 0xFFC + +/* ETMv4 resources */ +#define ETM_MAX_NR_PE 8 +#define ETMv4_MAX_CNTR 4 +#define ETM_MAX_SEQ_STATES 4 +#define ETM_MAX_EXT_INP_SEL 4 +#define ETM_MAX_EXT_INP 256 +#define ETM_MAX_EXT_OUT 4 +#define ETM_MAX_SINGLE_ADDR_CMP 16 +#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) +#define ETM_MAX_DATA_VAL_CMP 8 +#define ETMv4_MAX_CTXID_CMP 8 +#define ETM_MAX_VMID_CMP 8 +#define ETM_MAX_PE_CMP 8 +#define ETM_MAX_RES_SEL 16 +#define ETM_MAX_SS_CMP 8 + +#define ETM_ARCH_V4 0x40 +#define ETMv4_SYNC_MASK 0x1F +#define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETMv4_EVENT_MASK 0xFF +#define ETM_CNTR_MAX_VAL 0xFFFF +#define ETM_TRACEID_MASK 0x3f + +/* ETMv4 programming modes */ +#define ETM_MODE_EXCLUDE BIT(0) +#define ETM_MODE_LOAD BIT(1) +#define ETM_MODE_STORE BIT(2) +#define ETM_MODE_LOAD_STORE BIT(3) +#define ETM_MODE_BB BIT(4) +#define ETMv4_MODE_CYCACC BIT(5) +#define ETMv4_MODE_CTXID BIT(6) +#define ETM_MODE_VMID BIT(7) +#define ETM_MODE_COND(val) BMVAL(val, 8, 10) +#define ETMv4_MODE_TIMESTAMP BIT(11) +#define ETM_MODE_RETURNSTACK BIT(12) +#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) +#define ETM_MODE_DATA_TRACE_ADDR BIT(15) +#define ETM_MODE_DATA_TRACE_VAL BIT(16) +#define ETM_MODE_ISTALL BIT(17) +#define ETM_MODE_DSTALL BIT(18) +#define ETM_MODE_ATB_TRIGGER BIT(19) +#define ETM_MODE_LPOVERRIDE BIT(20) +#define ETM_MODE_ISTALL_EN BIT(21) +#define ETM_MODE_DSTALL_EN BIT(22) +#define ETM_MODE_INSTPRIO BIT(23) +#define ETM_MODE_NOOVERFLOW BIT(24) +#define ETM_MODE_TRACE_RESET BIT(25) +#define ETM_MODE_TRACE_ERR BIT(26) +#define ETM_MODE_VIEWINST_STARTSTOP BIT(27) +#define ETMv4_MODE_ALL 0xFFFFFFF + +#define TRCSTATR_IDLE_BIT 0 + +/** + * struct etm4_drvdata - specifics associated to an ETM component + * @base: Memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: Component vitals needed by the framework. + * @spinlock: Only one at a time pls. + * @cpu: The cpu this component is affined to. + * @arch: ETM version number. + * @enable: Is this ETM currently tracing. + * @sticky_enable: true if ETM base configuration has been done. + * @boot_enable:True if we should start tracing at boot time. + * @os_unlock: True if access to management registers is allowed. + * @nr_pe: The number of processing entity available for tracing. + * @nr_pe_cmp: The number of processing entity comparator inputs that are + * available for tracing. + * @nr_addr_cmp:Number of pairs of address comparators available + * as found in ETMIDR4 0-3. + * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. + * @nr_ext_inp: Number of external input. + * @numcidc: Number of contextID comparators. + * @numvmidc: Number of VMID comparators. + * @nrseqstate: The number of sequencer states that are implemented. + * @nr_event: Indicates how many events the trace unit support. + * @nr_resource:The number of resource selection pairs available for tracing. + * @nr_ss_cmp: Number of single-shot comparator controls that are available. + * @mode: Controls various modes supported by this ETM. + * @trcid: value of the current ID for this component. + * @trcid_size: Indicates the trace ID width. + * @instrp0: Tracing of load and store instructions + * as P0 elements is supported. + * @trccond: If the trace unit supports conditional + * instruction tracing. + * @retstack: Indicates if the implementation supports a return stack. + * @trc_error: Whether a trace unit can trace a system + * error exception. + * @atbtrig: If the implementation can support ATB triggers + * @lpoverride: If the implementation can support low-power state over. + * @pe_sel: Controls which PE to trace. + * @cfg: Controls the tracing options. + * @eventctrl0: Controls the tracing of arbitrary events. + * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. + * @stallctl: If functionality that prevents trace unit buffer overflows + * is available. + * @sysstall: Does the system support stall control of the PE? + * @nooverflow: Indicate if overflow prevention is supported. + * @stall_ctrl: Enables trace unit functionality that prevents trace + * unit buffer overflows. + * @ts_size: Global timestamp size field. + * @ts_ctrl: Controls the insertion of global timestamps in the + * trace streams. + * @syncpr: Indicates if an implementation has a fixed + * synchronization period. + * @syncfreq: Controls how often trace synchronization requests occur. + * @trccci: Indicates if the trace unit supports cycle counting + * for instruction. + * @ccsize: Indicates the size of the cycle counter in bits. + * @ccitmin: minimum value that can be programmed in + * the TRCCCCTLR register. + * @ccctlr: Sets the threshold value for cycle counting. + * @trcbb: Indicates if the trace unit supports branch broadcast tracing. + * @q_support: Q element support characteristics. + * @vinst_ctrl: Controls instruction trace filtering. + * @viiectlr: Set or read, the address range comparators. + * @vissctlr: Set, or read, the single address comparators that control the + * ViewInst start-stop logic. + * @vipcssctlr: Set, or read, which PE comparator inputs can control the + * ViewInst start-stop logic. + * @seq_idx: Sequencor index selector. + * @seq_ctrl: Control for the sequencer state transition control register. + * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. + * @seq_state: Set, or read the sequencer state. + * @cntr_idx: Counter index seletor. + * @cntrldvr: Sets or returns the reload count value for a counter. + * @cntr_ctrl: Controls the operation of a counter. + * @cntr_val: Sets or returns the value for a counter. + * @res_idx: Resource index selector. + * @res_ctrl: Controls the selection of the resources in the trace unit. + * @ss_ctrl: Controls the corresponding single-shot comparator resource. + * @ss_status: The status of the corresponding single-shot comparator. + * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. + * @addr_idx: Address comparator index selector. + * @addr_val: Value for address comparator. + * @addr_acc: Address comparator access type. + * @addr_type: Current status of the comparator register. + * @ctxid_idx: Context ID index selector. + * @ctxid_size: Size of the context ID field to consider. + * @ctxid_val: Value of the context ID comparator. + * @ctxid_mask0:Context ID comparator mask for comparator 0-3. + * @ctxid_mask1:Context ID comparator mask for comparator 4-7. + * @vmid_idx: VM ID index selector. + * @vmid_size: Size of the VM ID comparator to consider. + * @vmid_val: Value of the VM ID comparator. + * @vmid_mask0: VM ID comparator mask for comparator 0-3. + * @vmid_mask1: VM ID comparator mask for comparator 4-7. + * @s_ex_level: In secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @ns_ex_level:In non-secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @ext_inp: External input selection. + */ +struct etmv4_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + int cpu; + u8 arch; + bool enable; + bool sticky_enable; + bool boot_enable; + bool os_unlock; + u8 nr_pe; + u8 nr_pe_cmp; + u8 nr_addr_cmp; + u8 nr_cntr; + u8 nr_ext_inp; + u8 numcidc; + u8 numvmidc; + u8 nrseqstate; + u8 nr_event; + u8 nr_resource; + u8 nr_ss_cmp; + u32 mode; + u8 trcid; + u8 trcid_size; + bool instrp0; + bool trccond; + bool retstack; + bool trc_error; + bool atbtrig; + bool lpoverride; + u32 pe_sel; + u32 cfg; + u32 eventctrl0; + u32 eventctrl1; + bool stallctl; + bool sysstall; + bool nooverflow; + u32 stall_ctrl; + u8 ts_size; + u32 ts_ctrl; + bool syncpr; + u32 syncfreq; + bool trccci; + u8 ccsize; + u8 ccitmin; + u32 ccctlr; + bool trcbb; + u32 bb_ctrl; + bool q_support; + u32 vinst_ctrl; + u32 viiectlr; + u32 vissctlr; + u32 vipcssctlr; + u8 seq_idx; + u32 seq_ctrl[ETM_MAX_SEQ_STATES]; + u32 seq_rst; + u32 seq_state; + u8 cntr_idx; + u32 cntrldvr[ETMv4_MAX_CNTR]; + u32 cntr_ctrl[ETMv4_MAX_CNTR]; + u32 cntr_val[ETMv4_MAX_CNTR]; + u8 res_idx; + u32 res_ctrl[ETM_MAX_RES_SEL]; + u32 ss_ctrl[ETM_MAX_SS_CMP]; + u32 ss_status[ETM_MAX_SS_CMP]; + u32 ss_pe_cmp[ETM_MAX_SS_CMP]; + u8 addr_idx; + u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; + u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; + u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; + u8 ctxid_idx; + u8 ctxid_size; + u64 ctxid_val[ETMv4_MAX_CTXID_CMP]; + u32 ctxid_mask0; + u32 ctxid_mask1; + u8 vmid_idx; + u8 vmid_size; + u64 vmid_val[ETM_MAX_VMID_CMP]; + u32 vmid_mask0; + u32 vmid_mask1; + u8 s_ex_level; + u8 ns_ex_level; + u32 ext_inp; +}; + +/* Address comparator access types */ +enum etm_addr_acctype { + ETM_INSTR_ADDR, + ETM_DATA_LOAD_ADDR, + ETM_DATA_STORE_ADDR, + ETM_DATA_LOAD_STORE_ADDR, +}; + +/* Address comparator context types */ +enum etm_addr_ctxtype { + ETM_CTX_NONE, + ETM_CTX_CTXID, + ETM_CTX_VMID, + ETM_CTX_CTXID_VMID, +}; + +enum etm_addr_type { + ETM_ADDR_TYPE_NONE, + ETM_ADDR_TYPE_SINGLE, + ETM_ADDR_TYPE_RANGE, + ETM_ADDR_TYPE_START, + ETM_ADDR_TYPE_STOP, +}; +#endif -- cgit v1.2.3 From c0ddbfea722298db7fa66b921c30f2ee9190da04 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:10 -0600 Subject: coresight-etm4x: Controls pertaining to tracer configuration Tracers can be configured with various options at synthesis time and knowing what resources are available is important for SW configuration purposes. As such adding RO sysfs entries for characteristics related to the tracer implementation. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 62 +++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 117 +++++++++++++++++++++ 2 files changed, 179 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index d1e513991fcb..c731ed9943b3 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -13,3 +13,65 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) The CPU this tracing entity is associated with. + +What: /sys/bus/coresight/devices/.etm/nr_pe_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of PE comparator inputs that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/nr_addr_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of address comparator pairs that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/nr_cntr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of counters that are available for + tracing. + +What: /sys/bus/coresight/devices/.etm/nr_ext_inp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates how many external inputs are implemented. + +What: /sys/bus/coresight/devices/.etm/numcidc +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of Context ID comparators that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/numvmidc +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of VMID comparators that are available + for tracing. + +What: /sys/bus/coresight/devices/.etm/nrseqstate +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of sequencer states that are + implemented. + +What: /sys/bus/coresight/devices/.etm/nr_resource +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of resource selection pairs that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/nr_ss_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of single-shot comparator controls that + are available for tracing. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 169d8011c8b5..859e061722d8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -268,6 +268,114 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static ssize_t nr_pe_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_pe_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_pe_cmp); + +static ssize_t nr_addr_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_addr_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_addr_cmp); + +static ssize_t nr_cntr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_cntr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_cntr); + +static ssize_t nr_ext_inp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_ext_inp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_ext_inp); + +static ssize_t numcidc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->numcidc; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(numcidc); + +static ssize_t numvmidc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->numvmidc; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(numvmidc); + +static ssize_t nrseqstate_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nrseqstate; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nrseqstate); + +static ssize_t nr_resource_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_resource; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_resource); + +static ssize_t nr_ss_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_ss_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_ss_cmp); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -281,6 +389,15 @@ static ssize_t cpu_show(struct device *dev, static DEVICE_ATTR_RO(cpu); static struct attribute *coresight_etmv4_attrs[] = { + &dev_attr_nr_pe_cmp.attr, + &dev_attr_nr_addr_cmp.attr, + &dev_attr_nr_cntr.attr, + &dev_attr_nr_ext_inp.attr, + &dev_attr_numcidc.attr, + &dev_attr_numvmidc.attr, + &dev_attr_nrseqstate.attr, + &dev_attr_nr_resource.attr, + &dev_attr_nr_ss_cmp.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From d8c66962084f83c00fd0aecb243d6d074a5bba0f Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:11 -0600 Subject: coresight-etm4x: Controls pertaining to the reset, mode, pe and events Adding sysfs entries to: . set the tracing entity with default values. . set various mode associated to the tracing entity. . select the processing entity the tracing entity relates to. . select various events of interest. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 33 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 441 +++++++++++++++++++++ 2 files changed, 474 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index c731ed9943b3..7917a180cfc6 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -75,3 +75,36 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. + +What: /sys/bus/coresight/devices/.etm/reset +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (W) Cancels all configuration on a trace unit and set it back + to its boot configuration. + +What: /sys/bus/coresight/devices/.etm/mode +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls various modes supported by this ETM, for example + P0 instruction tracing, branch broadcast, cycle counting and + context ID tracing. + +What: /sys/bus/coresight/devices/.etm/pe +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls which PE to trace. + +What: /sys/bus/coresight/devices/.etm/event +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. + +What: /sys/bus/coresight/devices/.etm/event_instren +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls the behavior of the events in bank 0 to 3. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 859e061722d8..e9f58a5d2934 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -268,6 +268,46 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude) +{ + u8 idx = drvdata->addr_idx; + + /* + * TRCACATRn.TYPE bit[1:0]: type of comparison + * the trace unit performs + */ + if (BMVAL(drvdata->addr_acc[idx], 0, 1) == ETM_INSTR_ADDR) { + if (idx % 2 != 0) + return -EINVAL; + + /* + * We are performing instruction address comparison. Set the + * relevant bit of ViewInst Include/Exclude Control register + * for corresponding address comparator pair. + */ + if (drvdata->addr_type[idx] != ETM_ADDR_TYPE_RANGE || + drvdata->addr_type[idx + 1] != ETM_ADDR_TYPE_RANGE) + return -EINVAL; + + if (exclude == true) { + /* + * Set exclude bit and unset the include bit + * corresponding to comparator pair + */ + drvdata->viiectlr |= BIT(idx / 2 + 16); + drvdata->viiectlr &= ~BIT(idx / 2); + } else { + /* + * Set include bit and unset exclude bit + * corresponding to comparator pair + */ + drvdata->viiectlr |= BIT(idx / 2); + drvdata->viiectlr &= ~BIT(idx / 2 + 16); + } + } + return 0; +} + static ssize_t nr_pe_cmp_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -376,6 +416,402 @@ static ssize_t nr_ss_cmp_show(struct device *dev, } static DEVICE_ATTR_RO(nr_ss_cmp); +static ssize_t reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int i; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->mode = 0x0; + + /* Disable data tracing: do not trace load and store data transfers */ + drvdata->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE); + drvdata->cfg &= ~(BIT(1) | BIT(2)); + + /* Disable data value and data address tracing */ + drvdata->mode &= ~(ETM_MODE_DATA_TRACE_ADDR | + ETM_MODE_DATA_TRACE_VAL); + drvdata->cfg &= ~(BIT(16) | BIT(17)); + + /* Disable all events tracing */ + drvdata->eventctrl0 = 0x0; + drvdata->eventctrl1 = 0x0; + + /* Disable timestamp event */ + drvdata->ts_ctrl = 0x0; + + /* Disable stalling */ + drvdata->stall_ctrl = 0x0; + + /* Reset trace synchronization period to 2^8 = 256 bytes*/ + if (drvdata->syncpr == false) + drvdata->syncfreq = 0x8; + + /* + * Enable ViewInst to trace everything with start-stop logic in + * started state. ARM recommends start-stop logic is set before + * each trace run. + */ + drvdata->vinst_ctrl |= BIT(0); + if (drvdata->nr_addr_cmp == true) { + drvdata->mode |= ETM_MODE_VIEWINST_STARTSTOP; + /* SSSTATUS, bit[9] */ + drvdata->vinst_ctrl |= BIT(9); + } + + /* No address range filtering for ViewInst */ + drvdata->viiectlr = 0x0; + + /* No start-stop filtering for ViewInst */ + drvdata->vissctlr = 0x0; + + /* Disable seq events */ + for (i = 0; i < drvdata->nrseqstate-1; i++) + drvdata->seq_ctrl[i] = 0x0; + drvdata->seq_rst = 0x0; + drvdata->seq_state = 0x0; + + /* Disable external input events */ + drvdata->ext_inp = 0x0; + + drvdata->cntr_idx = 0x0; + for (i = 0; i < drvdata->nr_cntr; i++) { + drvdata->cntrldvr[i] = 0x0; + drvdata->cntr_ctrl[i] = 0x0; + drvdata->cntr_val[i] = 0x0; + } + + drvdata->res_idx = 0x0; + for (i = 0; i < drvdata->nr_resource; i++) + drvdata->res_ctrl[i] = 0x0; + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->ss_ctrl[i] = 0x0; + drvdata->ss_pe_cmp[i] = 0x0; + } + + drvdata->addr_idx = 0x0; + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + drvdata->addr_val[i] = 0x0; + drvdata->addr_acc[i] = 0x0; + drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE; + } + + drvdata->ctxid_idx = 0x0; + for (i = 0; i < drvdata->numcidc; i++) + drvdata->ctxid_val[i] = 0x0; + drvdata->ctxid_mask0 = 0x0; + drvdata->ctxid_mask1 = 0x0; + + drvdata->vmid_idx = 0x0; + for (i = 0; i < drvdata->numvmidc; i++) + drvdata->vmid_val[i] = 0x0; + drvdata->vmid_mask0 = 0x0; + drvdata->vmid_mask1 = 0x0; + + drvdata->trcid = drvdata->cpu + 1; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_WO(reset); + +static ssize_t mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->mode; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val, mode; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->mode = val & ETMv4_MODE_ALL; + + if (drvdata->mode & ETM_MODE_EXCLUDE) + etm4_set_mode_exclude(drvdata, true); + else + etm4_set_mode_exclude(drvdata, false); + + if (drvdata->instrp0 == true) { + /* start by clearing instruction P0 field */ + drvdata->cfg &= ~(BIT(1) | BIT(2)); + if (drvdata->mode & ETM_MODE_LOAD) + /* 0b01 Trace load instructions as P0 instructions */ + drvdata->cfg |= BIT(1); + if (drvdata->mode & ETM_MODE_STORE) + /* 0b10 Trace store instructions as P0 instructions */ + drvdata->cfg |= BIT(2); + if (drvdata->mode & ETM_MODE_LOAD_STORE) + /* + * 0b11 Trace load and store instructions + * as P0 instructions + */ + drvdata->cfg |= BIT(1) | BIT(2); + } + + /* bit[3], Branch broadcast mode */ + if ((drvdata->mode & ETM_MODE_BB) && (drvdata->trcbb == true)) + drvdata->cfg |= BIT(3); + else + drvdata->cfg &= ~BIT(3); + + /* bit[4], Cycle counting instruction trace bit */ + if ((drvdata->mode & ETMv4_MODE_CYCACC) && + (drvdata->trccci == true)) + drvdata->cfg |= BIT(4); + else + drvdata->cfg &= ~BIT(4); + + /* bit[6], Context ID tracing bit */ + if ((drvdata->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size)) + drvdata->cfg |= BIT(6); + else + drvdata->cfg &= ~BIT(6); + + if ((drvdata->mode & ETM_MODE_VMID) && (drvdata->vmid_size)) + drvdata->cfg |= BIT(7); + else + drvdata->cfg &= ~BIT(7); + + /* bits[10:8], Conditional instruction tracing bit */ + mode = ETM_MODE_COND(drvdata->mode); + if (drvdata->trccond == true) { + drvdata->cfg &= ~(BIT(8) | BIT(9) | BIT(10)); + drvdata->cfg |= mode << 8; + } + + /* bit[11], Global timestamp tracing bit */ + if ((drvdata->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size)) + drvdata->cfg |= BIT(11); + else + drvdata->cfg &= ~BIT(11); + + /* bit[12], Return stack enable bit */ + if ((drvdata->mode & ETM_MODE_RETURNSTACK) && + (drvdata->retstack == true)) + drvdata->cfg |= BIT(12); + else + drvdata->cfg &= ~BIT(12); + + /* bits[14:13], Q element enable field */ + mode = ETM_MODE_QELEM(drvdata->mode); + /* start by clearing QE bits */ + drvdata->cfg &= ~(BIT(13) | BIT(14)); + /* if supported, Q elements with instruction counts are enabled */ + if ((mode & BIT(0)) && (drvdata->q_support & BIT(0))) + drvdata->cfg |= BIT(13); + /* + * if supported, Q elements with and without instruction + * counts are enabled + */ + if ((mode & BIT(1)) && (drvdata->q_support & BIT(1))) + drvdata->cfg |= BIT(14); + + /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ + if ((drvdata->mode & ETM_MODE_ATB_TRIGGER) && + (drvdata->atbtrig == true)) + drvdata->eventctrl1 |= BIT(11); + else + drvdata->eventctrl1 &= ~BIT(11); + + /* bit[12], Low-power state behavior override bit */ + if ((drvdata->mode & ETM_MODE_LPOVERRIDE) && + (drvdata->lpoverride == true)) + drvdata->eventctrl1 |= BIT(12); + else + drvdata->eventctrl1 &= ~BIT(12); + + /* bit[8], Instruction stall bit */ + if (drvdata->mode & ETM_MODE_ISTALL_EN) + drvdata->stall_ctrl |= BIT(8); + else + drvdata->stall_ctrl &= ~BIT(8); + + /* bit[10], Prioritize instruction trace bit */ + if (drvdata->mode & ETM_MODE_INSTPRIO) + drvdata->stall_ctrl |= BIT(10); + else + drvdata->stall_ctrl &= ~BIT(10); + + /* bit[13], Trace overflow prevention bit */ + if ((drvdata->mode & ETM_MODE_NOOVERFLOW) && + (drvdata->nooverflow == true)) + drvdata->stall_ctrl |= BIT(13); + else + drvdata->stall_ctrl &= ~BIT(13); + + /* bit[9] Start/stop logic control bit */ + if (drvdata->mode & ETM_MODE_VIEWINST_STARTSTOP) + drvdata->vinst_ctrl |= BIT(9); + else + drvdata->vinst_ctrl &= ~BIT(9); + + /* bit[10], Whether a trace unit must trace a Reset exception */ + if (drvdata->mode & ETM_MODE_TRACE_RESET) + drvdata->vinst_ctrl |= BIT(10); + else + drvdata->vinst_ctrl &= ~BIT(10); + + /* bit[11], Whether a trace unit must trace a system error exception */ + if ((drvdata->mode & ETM_MODE_TRACE_ERR) && + (drvdata->trc_error == true)) + drvdata->vinst_ctrl |= BIT(11); + else + drvdata->vinst_ctrl &= ~BIT(11); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(mode); + +static ssize_t pe_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->pe_sel; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t pe_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val > drvdata->nr_pe) { + spin_unlock(&drvdata->spinlock); + return -EINVAL; + } + + drvdata->pe_sel = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(pe); + +static ssize_t event_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->eventctrl0; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + switch (drvdata->nr_event) { + case 0x0: + /* EVENT0, bits[7:0] */ + drvdata->eventctrl0 = val & 0xFF; + break; + case 0x1: + /* EVENT1, bits[15:8] */ + drvdata->eventctrl0 = val & 0xFFFF; + break; + case 0x2: + /* EVENT2, bits[23:16] */ + drvdata->eventctrl0 = val & 0xFFFFFF; + break; + case 0x3: + /* EVENT3, bits[31:24] */ + drvdata->eventctrl0 = val; + break; + default: + break; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event); + +static ssize_t event_instren_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = BMVAL(drvdata->eventctrl1, 0, 3); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_instren_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* start by clearing all instruction event enable bits */ + drvdata->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); + switch (drvdata->nr_event) { + case 0x0: + /* generate Event element for event 1 */ + drvdata->eventctrl1 |= val & BIT(1); + break; + case 0x1: + /* generate Event element for event 1 and 2 */ + drvdata->eventctrl1 |= val & (BIT(0) | BIT(1)); + break; + case 0x2: + /* generate Event element for event 1, 2 and 3 */ + drvdata->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); + break; + case 0x3: + /* generate Event element for all 4 events */ + drvdata->eventctrl1 |= val & 0xF; + break; + default: + break; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event_instren); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -398,6 +834,11 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_nrseqstate.attr, &dev_attr_nr_resource.attr, &dev_attr_nr_ss_cmp.attr, + &dev_attr_reset.attr, + &dev_attr_mode.attr, + &dev_attr_pe.attr, + &dev_attr_event.attr, + &dev_attr_event_instren.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From b460daf87b42f83f5c7030589f190a3215167bb8 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:12 -0600 Subject: coresight-etm4x: Controls pertaining to various configuration options Adding sysfs entries to configure: . global timestamp. . how often trace synchronisation occur. . the threashold value for cycle counting. . branch and broadcasting regions. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 26 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 124 +++++++++++++++++++++ 2 files changed, 150 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 7917a180cfc6..7e5f9bf1d508 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -108,3 +108,29 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the behavior of the events in bank 0 to 3. + +What: /sys/bus/coresight/devices/.etm/event_ts +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls the insertion of global timestamps in the trace + streams. + +What: /sys/bus/coresight/devices/.etm/syncfreq +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls how often trace synchronization requests occur. + +What: /sys/bus/coresight/devices/.etm/cyc_threshold +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Sets the threshold value for cycle counting. + +What: /sys/bus/coresight/devices/.etm/bb_ctrl +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls which regions in the memory map are enabled to + use branch broadcasting. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index e9f58a5d2934..51fbda837026 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -812,6 +812,126 @@ static ssize_t event_instren_store(struct device *dev, } static DEVICE_ATTR_RW(event_instren); +static ssize_t event_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->ts_ctrl; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!drvdata->ts_size) + return -EINVAL; + + drvdata->ts_ctrl = val & ETMv4_EVENT_MASK; + return size; +} +static DEVICE_ATTR_RW(event_ts); + +static ssize_t syncfreq_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->syncfreq; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t syncfreq_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (drvdata->syncpr == true) + return -EINVAL; + + drvdata->syncfreq = val & ETMv4_SYNC_MASK; + return size; +} +static DEVICE_ATTR_RW(syncfreq); + +static ssize_t cyc_threshold_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->ccctlr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cyc_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val < drvdata->ccitmin) + return -EINVAL; + + drvdata->ccctlr = val & ETM_CYC_THRESHOLD_MASK; + return size; +} +static DEVICE_ATTR_RW(cyc_threshold); + +static ssize_t bb_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->bb_ctrl; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t bb_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (drvdata->trcbb == false) + return -EINVAL; + if (!drvdata->nr_addr_cmp) + return -EINVAL; + /* + * Bit[7:0] selects which address range comparator is used for + * branch broadcast control. + */ + if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp) + return -EINVAL; + + drvdata->bb_ctrl = val; + return size; +} +static DEVICE_ATTR_RW(bb_ctrl); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -839,6 +959,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_pe.attr, &dev_attr_event.attr, &dev_attr_event_instren.attr, + &dev_attr_event_ts.attr, + &dev_attr_syncfreq.attr, + &dev_attr_cyc_threshold.attr, + &dev_attr_bb_ctrl.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From 43ba6a7b00ebca1f95bd5a64ceed4f3bae8aeca4 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:13 -0600 Subject: coresight-etm4x: Controls pertaining to the ViewInst register Adding sysfs entries to control the ViewInst register's event selector along with secure and non-secure exception level instruction tracing. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 98 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 7e5f9bf1d508..ca0a51838e35 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -134,3 +134,23 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. + +What: /sys/bus/coresight/devices/.etm/event_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls instruction trace filtering. + +What: /sys/bus/coresight/devices/.etm/s_exlevel_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) In Secure state, each bit controls whether instruction + tracing is enabled for the corresponding exception level. + +What: /sys/bus/coresight/devices/.etm/ns_exlevel_vinst +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) In non-secure state, each bit controls whether instruction + tracing is enabled for the corresponding exception level. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 51fbda837026..e44cc8464134 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -932,6 +932,101 @@ static ssize_t bb_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(bb_ctrl); +static ssize_t event_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->vinst_ctrl & ETMv4_EVENT_MASK; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t event_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + val &= ETMv4_EVENT_MASK; + drvdata->vinst_ctrl &= ~ETMv4_EVENT_MASK; + drvdata->vinst_ctrl |= val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(event_vinst); + +static ssize_t s_exlevel_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = BMVAL(drvdata->vinst_ctrl, 16, 19); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t s_exlevel_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ + drvdata->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* enable instruction tracing for corresponding exception level */ + val &= drvdata->s_ex_level; + drvdata->vinst_ctrl |= (val << 16); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(s_exlevel_vinst); + +static ssize_t ns_exlevel_vinst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* EXLEVEL_NS, bits[23:20] */ + val = BMVAL(drvdata->vinst_ctrl, 20, 23); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ns_exlevel_vinst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* clear EXLEVEL_NS bits (bit[23] is never implemented */ + drvdata->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* enable instruction tracing for corresponding exception level */ + val &= drvdata->ns_ex_level; + drvdata->vinst_ctrl |= (val << 20); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ns_exlevel_vinst); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -963,6 +1058,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_syncfreq.attr, &dev_attr_cyc_threshold.attr, &dev_attr_bb_ctrl.attr, + &dev_attr_event_vinst.attr, + &dev_attr_s_exlevel_vinst.attr, + &dev_attr_ns_exlevel_vinst.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From 35c9b29bc8367fe9fdd8eb65492d485a5eeddf79 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:14 -0600 Subject: coresight-etm4x: Controls pertaining to the address comparator functions Adding sysfs entries to control the various mode the address comparator registers can enact, i.e, start/top, single, and range. Also supplementing with address comparator types configuration registers access, mandatory to complete the configuration of the comparator functions. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 25 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 423 +++++++++++++++++++++ 2 files changed, 448 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index ca0a51838e35..6a4d2b57bc39 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -154,3 +154,28 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. + +What: /sys/bus/coresight/devices/.etm/addr_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Select which address comparator or pair (of comparators) to + work with. + +What: /sys/bus/coresight/devices/.etm/addr_instdatatype +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls what type of comparison the trace unit performs. + +What: /sys/bus/coresight/devices/.etm/addr_single +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Used to setup single address comparator values. + +What: /sys/bus/coresight/devices/.etm/addr_range +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Used to setup address range comparator values. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index e44cc8464134..4c3d919b0ed3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1027,6 +1027,421 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, } static DEVICE_ATTR_RW(ns_exlevel_vinst); +static ssize_t addr_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->addr_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_addr_cmp * 2) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->addr_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_idx); + +static ssize_t addr_instdatatype_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t len; + u8 val, idx; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + val = BMVAL(drvdata->addr_acc[idx], 0, 1); + len = scnprintf(buf, PAGE_SIZE, "%s\n", + val == ETM_INSTR_ADDR ? "instr" : + (val == ETM_DATA_LOAD_ADDR ? "data_load" : + (val == ETM_DATA_STORE_ADDR ? "data_store" : + "data_load_store"))); + spin_unlock(&drvdata->spinlock); + return len; +} + +static ssize_t addr_instdatatype_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + char str[20] = ""; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (strlen(buf) >= 20) + return -EINVAL; + if (sscanf(buf, "%s", str) != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!strcmp(str, "instr")) + /* TYPE, bits[1:0] */ + drvdata->addr_acc[idx] &= ~(BIT(0) | BIT(1)); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_instdatatype); + +static ssize_t addr_single_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + idx = drvdata->addr_idx; + spin_lock(&drvdata->spinlock); + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + val = (unsigned long)drvdata->addr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_single_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_single); + +static ssize_t addr_range_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (idx % 2 != 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || + (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val1 = (unsigned long)drvdata->addr_val[idx]; + val2 = (unsigned long)drvdata->addr_val[idx + 1]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} + +static ssize_t addr_range_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + /* lower address comparator cannot have a higher address value */ + if (val1 > val2) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (idx % 2 != 0) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || + (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE && + drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val1; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE; + drvdata->addr_val[idx + 1] = (u64)val2; + drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE; + /* + * Program include or exclude control bits for vinst or vdata + * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE + */ + if (drvdata->mode & ETM_MODE_EXCLUDE) + etm4_set_mode_exclude(drvdata, true); + else + etm4_set_mode_exclude(drvdata, false); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_range); + +static ssize_t addr_start_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val = (unsigned long)drvdata->addr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_start_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!drvdata->nr_addr_cmp) { + spin_unlock(&drvdata->spinlock); + return -EINVAL; + } + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_START; + drvdata->vissctlr |= BIT(idx); + /* SSSTATUS, bit[9] - turn on start/stop logic */ + drvdata->vinst_ctrl |= BIT(9); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_start); + +static ssize_t addr_stop_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + val = (unsigned long)drvdata->addr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_stop_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!drvdata->nr_addr_cmp) { + spin_unlock(&drvdata->spinlock); + return -EINVAL; + } + if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE || + drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) { + spin_unlock(&drvdata->spinlock); + return -EPERM; + } + + drvdata->addr_val[idx] = (u64)val; + drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP; + drvdata->vissctlr |= BIT(idx + 16); + /* SSSTATUS, bit[9] - turn on start/stop logic */ + drvdata->vinst_ctrl |= BIT(9); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_stop); + +static ssize_t addr_ctxtype_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t len; + u8 idx, val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + /* CONTEXTTYPE, bits[3:2] */ + val = BMVAL(drvdata->addr_acc[idx], 2, 3); + len = scnprintf(buf, PAGE_SIZE, "%s\n", val == ETM_CTX_NONE ? "none" : + (val == ETM_CTX_CTXID ? "ctxid" : + (val == ETM_CTX_VMID ? "vmid" : "all"))); + spin_unlock(&drvdata->spinlock); + return len; +} + +static ssize_t addr_ctxtype_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + char str[10] = ""; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (strlen(buf) >= 10) + return -EINVAL; + if (sscanf(buf, "%s", str) != 1) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + if (!strcmp(str, "none")) + /* start by clearing context type bits */ + drvdata->addr_acc[idx] &= ~(BIT(2) | BIT(3)); + else if (!strcmp(str, "ctxid")) { + /* 0b01 The trace unit performs a Context ID */ + if (drvdata->numcidc) { + drvdata->addr_acc[idx] |= BIT(2); + drvdata->addr_acc[idx] &= ~BIT(3); + } + } else if (!strcmp(str, "vmid")) { + /* 0b10 The trace unit performs a VMID */ + if (drvdata->numvmidc) { + drvdata->addr_acc[idx] &= ~BIT(2); + drvdata->addr_acc[idx] |= BIT(3); + } + } else if (!strcmp(str, "all")) { + /* + * 0b11 The trace unit performs a Context ID + * comparison and a VMID + */ + if (drvdata->numcidc) + drvdata->addr_acc[idx] |= BIT(2); + if (drvdata->numvmidc) + drvdata->addr_acc[idx] |= BIT(3); + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_ctxtype); + +static ssize_t addr_context_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + /* context ID comparator bits[6:4] */ + val = BMVAL(drvdata->addr_acc[idx], 4, 6); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_context_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if ((drvdata->numcidc <= 1) && (drvdata->numvmidc <= 1)) + return -EINVAL; + if (val >= (drvdata->numcidc >= drvdata->numvmidc ? + drvdata->numcidc : drvdata->numvmidc)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->addr_idx; + /* clear context ID comparator bits[6:4] */ + drvdata->addr_acc[idx] &= ~(BIT(4) | BIT(5) | BIT(6)); + drvdata->addr_acc[idx] |= (val << 4); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_context); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1061,6 +1476,14 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_event_vinst.attr, &dev_attr_s_exlevel_vinst.attr, &dev_attr_ns_exlevel_vinst.attr, + &dev_attr_addr_idx.attr, + &dev_attr_addr_instdatatype.attr, + &dev_attr_addr_single.attr, + &dev_attr_addr_range.attr, + &dev_attr_addr_start.attr, + &dev_attr_addr_stop.attr, + &dev_attr_addr_ctxtype.attr, + &dev_attr_addr_context.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From 5e5ff3440633b07b47f58ddda1d984e367e12e90 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:15 -0600 Subject: coresight-etm4x: Controls pertaining to the sequencer functions Adding sysfs entries to access the sequencers related registers, more specifically the sequencer state, the sequencer state transition and the sequencer reset control registers. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 25 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 129 +++++++++++++++++++++ 2 files changed, 154 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 6a4d2b57bc39..6fb43e4c5939 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -179,3 +179,28 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup address range comparator values. + +What: /sys/bus/coresight/devices/.etm/seq_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Select which sequensor. + +What: /sys/bus/coresight/devices/.etm/seq_state +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Use this to set, or read, the sequencer state. + +What: /sys/bus/coresight/devices/.etm/seq_event +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Moves the sequencer state to a specific state. + +What: /sys/bus/coresight/devices/.etm/seq_reset_event +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Moves the sequencer to state 0 when a programmed event + occurs. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4c3d919b0ed3..aa9009fd2377 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1442,6 +1442,131 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t seq_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->seq_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nrseqstate - 1) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->seq_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(seq_idx); + +static ssize_t seq_state_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->seq_state; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_state_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nrseqstate) + return -EINVAL; + + drvdata->seq_state = val; + return size; +} +static DEVICE_ATTR_RW(seq_state); + +static ssize_t seq_event_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->seq_idx; + val = drvdata->seq_ctrl[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_event_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->seq_idx; + /* RST, bits[7:0] */ + drvdata->seq_ctrl[idx] = val & 0xFF; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(seq_event); + +static ssize_t seq_reset_event_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->seq_rst; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t seq_reset_event_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!(drvdata->nrseqstate)) + return -EINVAL; + + drvdata->seq_rst = val & ETMv4_EVENT_MASK; + return size; +} +static DEVICE_ATTR_RW(seq_reset_event); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1484,6 +1609,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_seq_idx.attr, + &dev_attr_seq_state.attr, + &dev_attr_seq_event.attr, + &dev_attr_seq_reset_event.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From add2d5d0d15fe391e42b8b220590ed02ba0aad16 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:16 -0600 Subject: coresight-etm4x: Controls pertaining to the counter functions Adding sysfs entries related to the counter functionality, more specifically to set, control and reload the counters. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 26 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 144 +++++++++++++++++++++ 2 files changed, 170 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 6fb43e4c5939..104f3951c998 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -204,3 +204,29 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. + +What: /sys/bus/coresight/devices/.etm/cntr_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Select which counter unit to work with. + +What: /sys/bus/coresight/devices/.etm/cntrldvr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) This sets or returns the reload count value of the + specific counter. + +What: /sys/bus/coresight/devices/.etm/cntr_val +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) This sets or returns the current count value of the + specific counter. + +What: /sys/bus/coresight/devices/.etm/cntr_ctrl +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls the operation of the selected counter. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index aa9009fd2377..2c394e41b0c8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1567,6 +1567,146 @@ static ssize_t seq_reset_event_store(struct device *dev, } static DEVICE_ATTR_RW(seq_reset_event); +static ssize_t cntr_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->cntr_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntr_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_cntr) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->cntr_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntr_idx); + +static ssize_t cntrldvr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + val = drvdata->cntrldvr[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntrldvr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val > ETM_CNTR_MAX_VAL) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + drvdata->cntrldvr[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntrldvr); + +static ssize_t cntr_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + val = drvdata->cntr_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntr_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val > ETM_CNTR_MAX_VAL) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + drvdata->cntr_val[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntr_val); + +static ssize_t cntr_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + val = drvdata->cntr_ctrl[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t cntr_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->cntr_idx; + drvdata->cntr_ctrl[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cntr_ctrl); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1613,6 +1753,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, &dev_attr_seq_reset_event.attr, + &dev_attr_cntr_idx.attr, + &dev_attr_cntrldvr.attr, + &dev_attr_cntr_val.attr, + &dev_attr_cntr_ctrl.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From 6afa8a1387aa4af73e8c3b81019d958ef8a2a4d0 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:17 -0600 Subject: coresight-etm4x: Controls pertaining to the selection of resources Adding sysfs entries to control the selection of the resources the trace unit will use as triggers to perform a trace run. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 12 ++++ drivers/hwtracing/coresight/coresight-etm4x.c | 75 ++++++++++++++++++++++ 2 files changed, 87 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 104f3951c998..5c7391d4e33a 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -230,3 +230,15 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the operation of the selected counter. + +What: /sys/bus/coresight/devices/.etm/res_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Select which resource selection unit to work with. + +What: /sys/bus/coresight/devices/.etm/res_ctrl +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Controls the selection of the resources in the trace unit. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 2c394e41b0c8..308a48df4338 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1707,6 +1707,79 @@ static ssize_t cntr_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(cntr_ctrl); +static ssize_t res_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->res_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t res_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + /* Resource selector pair 0 is always implemented and reserved */ + if ((val == 0) || (val >= drvdata->nr_resource)) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->res_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(res_idx); + +static ssize_t res_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->res_idx; + val = drvdata->res_ctrl[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t res_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->res_idx; + /* For odd idx pair inversal bit is RES0 */ + if (idx % 2 != 0) + /* PAIRINV, bit[21] */ + val &= ~BIT(21); + drvdata->res_ctrl[idx] = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(res_ctrl); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1757,6 +1830,8 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_cntrldvr.attr, &dev_attr_cntr_val.attr, &dev_attr_cntr_ctrl.attr, + &dev_attr_res_idx.attr, + &dev_attr_res_ctrl.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From 4a584be1d0061f7992a661f7c1a20c8688a50a19 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:18 -0600 Subject: coresight-etm4x: Controls pertaining to the context ID functions Adding sysfs entries to access and configure specifics about the context ID comparator functions. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 19 +++ drivers/hwtracing/coresight/coresight-etm4x.c | 187 +++++++++++++++++++++ 2 files changed, 206 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 5c7391d4e33a..f251b2c17f5b 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -242,3 +242,22 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the selection of the resources in the trace unit. + +What: /sys/bus/coresight/devices/.etm/ctxid_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Select which context ID comparator to work with. + +What: /sys/bus/coresight/devices/.etm/ctxid_val +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Get/Set the context ID comparator value to trigger on. + +What: /sys/bus/coresight/devices/.etm/ctxid_masks +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Mask for all 8 context ID comparator value + registers (if implemented). diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 308a48df4338..e94784fe68c4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1780,6 +1780,190 @@ static ssize_t res_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(res_ctrl); +static ssize_t ctxid_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->ctxid_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ctxid_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->numcidc) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->ctxid_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ctxid_idx); + +static ssize_t ctxid_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + idx = drvdata->ctxid_idx; + val = (unsigned long)drvdata->ctxid_val[idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t ctxid_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* + * only implemented when ctxid tracing is enabled, i.e. at least one + * ctxid comparator is implemented and ctxid is greater than 0 bits + * in length + */ + if (!drvdata->ctxid_size || !drvdata->numcidc) + return -EINVAL; + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = drvdata->ctxid_idx; + drvdata->ctxid_val[idx] = (u64)val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ctxid_val); + +static ssize_t ctxid_masks_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + val1 = drvdata->ctxid_mask0; + val2 = drvdata->ctxid_mask1; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} + +static ssize_t ctxid_masks_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 i, j, maskbyte; + unsigned long val1, val2, mask; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* + * only implemented when ctxid tracing is enabled, i.e. at least one + * ctxid comparator is implemented and ctxid is greater than 0 bits + * in length + */ + if (!drvdata->ctxid_size || !drvdata->numcidc) + return -EINVAL; + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* + * each byte[0..3] controls mask value applied to ctxid + * comparator[0..3] + */ + switch (drvdata->numcidc) { + case 0x1: + /* COMP0, bits[7:0] */ + drvdata->ctxid_mask0 = val1 & 0xFF; + break; + case 0x2: + /* COMP1, bits[15:8] */ + drvdata->ctxid_mask0 = val1 & 0xFFFF; + break; + case 0x3: + /* COMP2, bits[23:16] */ + drvdata->ctxid_mask0 = val1 & 0xFFFFFF; + break; + case 0x4: + /* COMP3, bits[31:24] */ + drvdata->ctxid_mask0 = val1; + break; + case 0x5: + /* COMP4, bits[7:0] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2 & 0xFF; + break; + case 0x6: + /* COMP5, bits[15:8] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2 & 0xFFFF; + break; + case 0x7: + /* COMP6, bits[23:16] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2 & 0xFFFFFF; + break; + case 0x8: + /* COMP7, bits[31:24] */ + drvdata->ctxid_mask0 = val1; + drvdata->ctxid_mask1 = val2; + break; + default: + break; + } + /* + * If software sets a mask bit to 1, it must program relevant byte + * of ctxid comparator value 0x0, otherwise behavior is unpredictable. + * For example, if bit[3] of ctxid_mask0 is 1, we must clear bits[31:24] + * of ctxid comparator0 value (corresponding to byte 0) register. + */ + mask = drvdata->ctxid_mask0; + for (i = 0; i < drvdata->numcidc; i++) { + /* mask value of corresponding ctxid comparator */ + maskbyte = mask & ETMv4_EVENT_MASK; + /* + * each bit corresponds to a byte of respective ctxid comparator + * value register + */ + for (j = 0; j < 8; j++) { + if (maskbyte & 1) + drvdata->ctxid_val[i] &= ~(0xFF << (j * 8)); + maskbyte >>= 1; + } + /* Select the next ctxid comparator mask value */ + if (i == 3) + /* ctxid comparators[4-7] */ + mask = drvdata->ctxid_mask1; + else + mask >>= 0x8; + } + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(ctxid_masks); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1832,6 +2016,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_cntr_ctrl.attr, &dev_attr_res_idx.attr, &dev_attr_res_ctrl.attr, + &dev_attr_ctxid_idx.attr, + &dev_attr_ctxid_val.attr, + &dev_attr_ctxid_masks.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From 40d8ebf0715f86b0231927a80bbc068869cc5ef1 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Wed, 13 May 2015 10:34:19 -0600 Subject: coresight-etm4x: Controls pertaining to the VM ID functions Adding sysfs entries to access and configure specifics about the virtual machine ID comparator functions. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 20 +++ drivers/hwtracing/coresight/coresight-etm4x.c | 178 +++++++++++++++++++++ 2 files changed, 198 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index f251b2c17f5b..648f28ded226 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -261,3 +261,23 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). + +What: /sys/bus/coresight/devices/.etm/vmid_idx +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Select which virtual machine ID comparator to work with. + +What: /sys/bus/coresight/devices/.etm/vmid_val +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Get/Set the virtual machine ID comparator value to + trigger on. + +What: /sys/bus/coresight/devices/.etm/vmid_masks +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (RW) Mask for all 8 virtual machine ID comparator value + registers (if implemented). diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index e94784fe68c4..02ee6fc97ddf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1964,6 +1964,181 @@ static ssize_t ctxid_masks_store(struct device *dev, } static DEVICE_ATTR_RW(ctxid_masks); +static ssize_t vmid_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->vmid_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t vmid_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->numvmidc) + return -EINVAL; + + /* + * Use spinlock to ensure index doesn't change while it gets + * dereferenced multiple times within a spinlock block elsewhere. + */ + spin_lock(&drvdata->spinlock); + drvdata->vmid_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vmid_idx); + +static ssize_t vmid_val_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = (unsigned long)drvdata->vmid_val[drvdata->vmid_idx]; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t vmid_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + /* + * only implemented when vmid tracing is enabled, i.e. at least one + * vmid comparator is implemented and at least 8 bit vmid size + */ + if (!drvdata->vmid_size || !drvdata->numvmidc) + return -EINVAL; + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->vmid_val[drvdata->vmid_idx] = (u64)val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vmid_val); + +static ssize_t vmid_masks_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val1, val2; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + val1 = drvdata->vmid_mask0; + val2 = drvdata->vmid_mask1; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} + +static ssize_t vmid_masks_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 i, j, maskbyte; + unsigned long val1, val2, mask; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + /* + * only implemented when vmid tracing is enabled, i.e. at least one + * vmid comparator is implemented and at least 8 bit vmid size + */ + if (!drvdata->vmid_size || !drvdata->numvmidc) + return -EINVAL; + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + + /* + * each byte[0..3] controls mask value applied to vmid + * comparator[0..3] + */ + switch (drvdata->numvmidc) { + case 0x1: + /* COMP0, bits[7:0] */ + drvdata->vmid_mask0 = val1 & 0xFF; + break; + case 0x2: + /* COMP1, bits[15:8] */ + drvdata->vmid_mask0 = val1 & 0xFFFF; + break; + case 0x3: + /* COMP2, bits[23:16] */ + drvdata->vmid_mask0 = val1 & 0xFFFFFF; + break; + case 0x4: + /* COMP3, bits[31:24] */ + drvdata->vmid_mask0 = val1; + break; + case 0x5: + /* COMP4, bits[7:0] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2 & 0xFF; + break; + case 0x6: + /* COMP5, bits[15:8] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2 & 0xFFFF; + break; + case 0x7: + /* COMP6, bits[23:16] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2 & 0xFFFFFF; + break; + case 0x8: + /* COMP7, bits[31:24] */ + drvdata->vmid_mask0 = val1; + drvdata->vmid_mask1 = val2; + break; + default: + break; + } + + /* + * If software sets a mask bit to 1, it must program relevant byte + * of vmid comparator value 0x0, otherwise behavior is unpredictable. + * For example, if bit[3] of vmid_mask0 is 1, we must clear bits[31:24] + * of vmid comparator0 value (corresponding to byte 0) register. + */ + mask = drvdata->vmid_mask0; + for (i = 0; i < drvdata->numvmidc; i++) { + /* mask value of corresponding vmid comparator */ + maskbyte = mask & ETMv4_EVENT_MASK; + /* + * each bit corresponds to a byte of respective vmid comparator + * value register + */ + for (j = 0; j < 8; j++) { + if (maskbyte & 1) + drvdata->vmid_val[i] &= ~(0xFF << (j * 8)); + maskbyte >>= 1; + } + /* Select the next vmid comparator mask value */ + if (i == 3) + /* vmid comparators[4-7] */ + mask = drvdata->vmid_mask1; + else + mask >>= 0x8; + } + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vmid_masks); + static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -2019,6 +2194,9 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_ctxid_idx.attr, &dev_attr_ctxid_val.attr, &dev_attr_ctxid_masks.attr, + &dev_attr_vmid_idx.attr, + &dev_attr_vmid_val.attr, + &dev_attr_vmid_masks.attr, &dev_attr_cpu.attr, NULL, }; -- cgit v1.2.3 From a467dae11d57c60dabf9f85d7691e6ce097fc424 Mon Sep 17 00:00:00 2001 From: Mathieu Poirier Date: Wed, 13 May 2015 10:34:20 -0600 Subject: coresight-etm4x: Read only access to the main management registers Having access to the ETMv4 management registers is very useful as they give meaningful information on how the IP block has been configured at synthesis time. Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 77 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 53 ++++++++++++++- 2 files changed, 129 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 648f28ded226..bde788dfd3f7 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -281,3 +281,80 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). + +What: /sys/bus/coresight/devices/.etm/mgmt/trcoslsr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the OS Lock Status Register (0x304). + The value it taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpdcr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Power Down Control Register + (0x310). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpdsr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Power Down Status Register + (0x314). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trclsr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the SW Lock Status Register + (0xFB4). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcauthstatus +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Authentication Status Register + (0xFB8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcdevid +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Device ID Register + (0xFC8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcdevtype +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Device Type Register + (0xFCC). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr0 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID0 Register + (0xFE0). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr1 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID1 Register + (0xFE4). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr2 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID2 Register + (0xFE8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr3 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID3 Register + (0xFEC). The value is taken directly from the HW. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 02ee6fc97ddf..0568e4413411 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -2200,7 +2200,58 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_cpu.attr, NULL, }; -ATTRIBUTE_GROUPS(coresight_etmv4); + +#define coresight_simple_func(name, offset) \ +static ssize_t name##_show(struct device *_dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct etmv4_drvdata *drvdata = dev_get_drvdata(_dev->parent); \ + return scnprintf(buf, PAGE_SIZE, "0x%x\n", \ + readl_relaxed(drvdata->base + offset)); \ +} \ +DEVICE_ATTR_RO(name) + +coresight_simple_func(trcoslsr, TRCOSLSR); +coresight_simple_func(trcpdcr, TRCPDCR); +coresight_simple_func(trcpdsr, TRCPDSR); +coresight_simple_func(trclsr, TRCLSR); +coresight_simple_func(trcauthstatus, TRCAUTHSTATUS); +coresight_simple_func(trcdevid, TRCDEVID); +coresight_simple_func(trcdevtype, TRCDEVTYPE); +coresight_simple_func(trcpidr0, TRCPIDR0); +coresight_simple_func(trcpidr1, TRCPIDR1); +coresight_simple_func(trcpidr2, TRCPIDR2); +coresight_simple_func(trcpidr3, TRCPIDR3); + +static struct attribute *coresight_etmv4_mgmt_attrs[] = { + &dev_attr_trcoslsr.attr, + &dev_attr_trcpdcr.attr, + &dev_attr_trcpdsr.attr, + &dev_attr_trclsr.attr, + &dev_attr_trcauthstatus.attr, + &dev_attr_trcdevid.attr, + &dev_attr_trcdevtype.attr, + &dev_attr_trcpidr0.attr, + &dev_attr_trcpidr1.attr, + &dev_attr_trcpidr2.attr, + &dev_attr_trcpidr3.attr, + NULL, +}; + +static const struct attribute_group coresight_etmv4_group = { + .attrs = coresight_etmv4_attrs, +}; + +static const struct attribute_group coresight_etmv4_mgmt_group = { + .attrs = coresight_etmv4_mgmt_attrs, + .name = "mgmt", +}; + +static const struct attribute_group *coresight_etmv4_groups[] = { + &coresight_etmv4_group, + &coresight_etmv4_mgmt_group, + NULL, +}; static void etm4_init_arch_data(void *info) { -- cgit v1.2.3 From 5625988e1e21261e20e18a64f275236eb47a9944 Mon Sep 17 00:00:00 2001 From: Mathieu Poirier Date: Wed, 13 May 2015 10:34:21 -0600 Subject: coresight-etm4x: Read only access to the tracer's ID registers ETM ID registers contain valuable information about the capabilities of the implementation and are very useful when configuring the device for various trace scenarios. Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 90 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 37 +++++++++ 2 files changed, 127 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index bde788dfd3f7..2fe2e3dae487 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -358,3 +358,93 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr0 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr1 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr2 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the maximum size of the data value, data address, + VMID, context ID and instuction address in the trace unit + (0x1E8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr3 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the value associated with various resources + available to the trace unit. See the Trace Macrocell + architecture specification for more details (0x1E8). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr4 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns how many resources the trace unit supports (0x1F0). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr5 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns how many resources the trace unit supports (0x1F4). + The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr8 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the maximum speculation depth of the instruction + trace stream. (0x180). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr9 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of P0 right-hand keys that the trace unit + can use (0x184). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr10 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of P1 right-hand keys that the trace unit + can use (0x188). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr11 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of special P1 right-hand keys that the + trace unit can use (0x18C). The value is taken directly from + the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr12 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of conditional P1 right-hand keys that + the trace unit can use (0x190). The value is taken directly + from the HW. + +What: /sys/bus/coresight/devices/.etm/trcidr/trcidr13 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Returns the number of special conditional P1 right-hand keys + that the trace unit can use (0x194). The value is taken + directly from the HW. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 0568e4413411..f0b50af4fc30 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -2238,6 +2238,37 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { NULL, }; +coresight_simple_func(trcidr0, TRCIDR0); +coresight_simple_func(trcidr1, TRCIDR1); +coresight_simple_func(trcidr2, TRCIDR2); +coresight_simple_func(trcidr3, TRCIDR3); +coresight_simple_func(trcidr4, TRCIDR4); +coresight_simple_func(trcidr5, TRCIDR5); +/* trcidr[6,7] are reserved */ +coresight_simple_func(trcidr8, TRCIDR8); +coresight_simple_func(trcidr9, TRCIDR9); +coresight_simple_func(trcidr10, TRCIDR10); +coresight_simple_func(trcidr11, TRCIDR11); +coresight_simple_func(trcidr12, TRCIDR12); +coresight_simple_func(trcidr13, TRCIDR13); + +static struct attribute *coresight_etmv4_trcidr_attrs[] = { + &dev_attr_trcidr0.attr, + &dev_attr_trcidr1.attr, + &dev_attr_trcidr2.attr, + &dev_attr_trcidr3.attr, + &dev_attr_trcidr4.attr, + &dev_attr_trcidr5.attr, + /* trcidr[6,7] are reserved */ + &dev_attr_trcidr8.attr, + &dev_attr_trcidr9.attr, + &dev_attr_trcidr10.attr, + &dev_attr_trcidr11.attr, + &dev_attr_trcidr12.attr, + &dev_attr_trcidr13.attr, + NULL, +}; + static const struct attribute_group coresight_etmv4_group = { .attrs = coresight_etmv4_attrs, }; @@ -2247,9 +2278,15 @@ static const struct attribute_group coresight_etmv4_mgmt_group = { .name = "mgmt", }; +static const struct attribute_group coresight_etmv4_trcidr_group = { + .attrs = coresight_etmv4_trcidr_attrs, + .name = "trcidr", +}; + static const struct attribute_group *coresight_etmv4_groups[] = { &coresight_etmv4_group, &coresight_etmv4_mgmt_group, + &coresight_etmv4_trcidr_group, NULL, }; -- cgit v1.2.3 From 70dd9d2f0af0e9ebe1c508dfa9a2ba0524f56cd5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 May 2015 10:55:19 -0600 Subject: coresight: document the bindings for the ATCLK Put in a blurb in the device tree bindings indicating that coresight blocks may have an optional ATCLK. Signed-off-by: Linus Walleij Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/arm/coresight.txt | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 88602b75418e..8711c1065479 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -21,11 +21,14 @@ its hardware characteristcs. * reg: physical base address and length of the register set(s) of the component. - * clocks: the clock associated to this component. - - * clock-names: the name of the clock as referenced by the code. - Since we are using the AMBA framework, the name should be - "apb_pclk". + * clocks: the clocks associated to this component. + + * clock-names: the name of the clocks referenced by the code. + Since we are using the AMBA framework, the name of the clock + providing the interconnect should be "apb_pclk", and some + coresight blocks also have an additional clock "atclk", which + clocks the core of that coresight component. The latter clock + is optional. * port or ports: The representation of the component's port layout using the generic DT graph presentation found in -- cgit v1.2.3 From 620cf787c121f39b5223e43bad3d1b7c66ecead5 Mon Sep 17 00:00:00 2001 From: Pratik Patel Date: Tue, 19 May 2015 10:55:21 -0600 Subject: coresight: replicator: Add Qualcomm CoreSight Replicator driver This driver manages Qualcomm CoreSight Replicator device, which resides on the AMBA bus. Replicator has been made programmable to allow software to turn of the replicator branch to sink that is not being used. This avoids trace traffic to the unused/non-current sink from causing back pressure that results in overflows at the source. Signed-off-by: Pratik Patel Signed-off-by: Ivan T. Ivanov Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/arm/coresight.txt | 1 + drivers/hwtracing/coresight/Kconfig | 8 + drivers/hwtracing/coresight/Makefile | 1 + .../coresight/coresight-replicator-qcom.c | 214 +++++++++++++++++++++ 4 files changed, 224 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-replicator-qcom.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 8711c1065479..65a6db2271a2 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "qcom,coresight-replicator1x", "arm,primecell"; * reg: physical base address and length of the register set(s) of the component. diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 8fac01eedee7..6c8921140f02 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -69,4 +69,12 @@ config CORESIGHT_SOURCE_ETM4X for instruction level tracing. Depending on the implemented version data tracing may also be available. +config CORESIGHT_QCOM_REPLICATOR + bool "Qualcomm CoreSight Replicator driver" + depends on CORESIGHT_LINKS_AND_SINKS + help + This enables support for Qualcomm CoreSight link driver. The + programmable ATB replicator sends the ATB trace stream from the + ETB/ETF to the TPIUi and ETR. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 0af28d43465c..99f8e5f6256e 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o +obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c new file mode 100644 index 000000000000..deacea49af36 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-replicator-qcom.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" + +#define REPLICATOR_IDFILTER0 0x000 +#define REPLICATOR_IDFILTER1 0x004 + +/** + * struct replicator_state - specifics associated to a replicator component + * @base: memory mapped base address for this component. + * @dev: the device entity associated with this component + * @atclk: optional clock for the core parts of the replicator. + * @csdev: component vitals needed by the framework + */ +struct replicator_state { + void __iomem *base; + struct device *dev; + struct clk *atclk; + struct coresight_device *csdev; +}; + +static int replicator_enable(struct coresight_device *csdev, int inport, + int outport) +{ + struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent); + + pm_runtime_get_sync(drvdata->dev); + + CS_UNLOCK(drvdata->base); + + /* + * Ensure that the other port is disabled + * 0x00 - passing through the replicator unimpeded + * 0xff - disable (or impede) the flow of ATB data + */ + if (outport == 0) { + writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0); + writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); + } else { + writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1); + writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); + } + + CS_LOCK(drvdata->base); + + dev_info(drvdata->dev, "REPLICATOR enabled\n"); + return 0; +} + +static void replicator_disable(struct coresight_device *csdev, int inport, + int outport) +{ + struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent); + + CS_UNLOCK(drvdata->base); + + /* disable the flow of ATB data through port */ + if (outport == 0) + writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); + else + writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); + + CS_LOCK(drvdata->base); + + pm_runtime_put(drvdata->dev); + + dev_info(drvdata->dev, "REPLICATOR disabled\n"); +} + +static const struct coresight_ops_link replicator_link_ops = { + .enable = replicator_enable, + .disable = replicator_disable, +}; + +static const struct coresight_ops replicator_cs_ops = { + .link_ops = &replicator_link_ops, +}; + +static int replicator_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + struct device *dev = &adev->dev; + struct resource *res = &adev->res; + struct coresight_platform_data *pdata = NULL; + struct replicator_state *drvdata; + struct coresight_desc *desc; + struct device_node *np = adev->dev.of_node; + void __iomem *base; + + if (np) { + pdata = of_get_coresight_platform_data(dev, np); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + } + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ + if (!IS_ERR(drvdata->atclk)) { + ret = clk_prepare_enable(drvdata->atclk); + if (ret) + return ret; + } + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + dev_set_drvdata(dev, drvdata); + pm_runtime_put(&adev->dev); + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + desc->type = CORESIGHT_DEV_TYPE_LINK; + desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; + desc->ops = &replicator_cs_ops; + desc->pdata = adev->dev.platform_data; + desc->dev = &adev->dev; + drvdata->csdev = coresight_register(desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + dev_info(dev, "%s initialized\n", (char *)id->data); + return 0; +} + +static int replicator_remove(struct amba_device *adev) +{ + struct replicator_state *drvdata = amba_get_drvdata(adev); + + pm_runtime_disable(&adev->dev); + coresight_unregister(drvdata->csdev); + return 0; +} + +#ifdef CONFIG_PM +static int replicator_runtime_suspend(struct device *dev) +{ + struct replicator_state *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_disable_unprepare(drvdata->atclk); + + return 0; +} + +static int replicator_runtime_resume(struct device *dev) +{ + struct replicator_state *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_prepare_enable(drvdata->atclk); + + return 0; +} +#endif + +static const struct dev_pm_ops replicator_dev_pm_ops = { + SET_RUNTIME_PM_OPS(replicator_runtime_suspend, + replicator_runtime_resume, + NULL) +}; + +static struct amba_id replicator_ids[] = { + { + .id = 0x0003b909, + .mask = 0x0003ffff, + .data = "REPLICATOR 1.0", + }, + { 0, 0 }, +}; + +static struct amba_driver replicator_driver = { + .drv = { + .name = "coresight-replicator-qcom", + .pm = &replicator_dev_pm_ops, + }, + .probe = replicator_probe, + .remove = replicator_remove, + .id_table = replicator_ids, +}; + +module_amba_driver(replicator_driver); -- cgit v1.2.3 From c93b76b34b4d8dbe8e3443eb27e49ac60034342b Mon Sep 17 00:00:00 2001 From: Tomas Winkler Date: Thu, 7 May 2015 15:54:02 +0300 Subject: mei: bus: report also uuid in module alias In order to automate modules matching add device uuid which is reported in client enumeration, keep also the name that is needed in for nfc distinguishing radio vendor Report mei:name:uuid Cc: linux-api@vger.kernel.org Cc: Samuel Ortiz Signed-off-by: Tomas Winkler Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-bus-mei | 2 +- drivers/misc/mei/bus.c | 42 ++++++++++++++++++++++++++------- drivers/misc/mei/mei_dev.h | 2 ++ drivers/nfc/mei_phy.h | 3 +++ drivers/nfc/microread/mei.c | 2 +- drivers/nfc/pn544/mei.c | 2 +- include/linux/mod_devicetable.h | 13 ++++++++++ scripts/mod/devicetable-offsets.c | 1 + scripts/mod/file2alias.c | 18 ++++++++++++-- 9 files changed, 72 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-mei b/Documentation/ABI/testing/sysfs-bus-mei index 2066f0bbd453..91967a70313a 100644 --- a/Documentation/ABI/testing/sysfs-bus-mei +++ b/Documentation/ABI/testing/sysfs-bus-mei @@ -4,4 +4,4 @@ KernelVersion: 3.10 Contact: Samuel Ortiz linux-mei@linux.intel.com Description: Stores the same MODALIAS value emitted by uevent - Format: mei: + Format: mei::: diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index 1101d6efaf27..17b00baa53b1 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -30,23 +30,40 @@ #define to_mei_cl_driver(d) container_of(d, struct mei_cl_driver, driver) #define to_mei_cl_device(d) container_of(d, struct mei_cl_device, dev) +static inline uuid_le uuid_le_cast(const __u8 uuid[16]) +{ + return *(uuid_le *)uuid; +} + static int mei_cl_device_match(struct device *dev, struct device_driver *drv) { struct mei_cl_device *device = to_mei_cl_device(dev); struct mei_cl_driver *driver = to_mei_cl_driver(drv); const struct mei_cl_device_id *id; + const uuid_le *uuid; + const char *name; if (!device) return 0; + uuid = mei_me_cl_uuid(device->me_cl); + name = device->name; + if (!driver || !driver->id_table) return 0; id = driver->id_table; - while (id->name[0]) { - if (!strncmp(dev_name(dev), id->name, sizeof(id->name))) - return 1; + while (uuid_le_cmp(NULL_UUID_LE, uuid_le_cast(id->uuid))) { + + if (!uuid_le_cmp(*uuid, uuid_le_cast(id->uuid))) { + if (id->name[0]) { + if (!strncmp(name, id->name, sizeof(id->name))) + return 1; + } else { + return 1; + } + } id++; } @@ -69,7 +86,7 @@ static int mei_cl_device_probe(struct device *dev) dev_dbg(dev, "Device probe\n"); - strlcpy(id.name, dev_name(dev), sizeof(id.name)); + strlcpy(id.name, device->name, sizeof(id.name)); return driver->probe(device, &id); } @@ -100,9 +117,12 @@ static int mei_cl_device_remove(struct device *dev) static ssize_t modalias_show(struct device *dev, struct device_attribute *a, char *buf) { - int len; + struct mei_cl_device *device = to_mei_cl_device(dev); + const uuid_le *uuid = mei_me_cl_uuid(device->me_cl); + size_t len; - len = snprintf(buf, PAGE_SIZE, "mei:%s\n", dev_name(dev)); + len = snprintf(buf, PAGE_SIZE, "mei:%s:" MEI_CL_UUID_FMT ":", + device->name, MEI_CL_UUID_ARGS(uuid->b)); return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len; } @@ -116,7 +136,11 @@ ATTRIBUTE_GROUPS(mei_cl_dev); static int mei_cl_uevent(struct device *dev, struct kobj_uevent_env *env) { - if (add_uevent_var(env, "MODALIAS=mei:%s", dev_name(dev))) + struct mei_cl_device *device = to_mei_cl_device(dev); + const uuid_le *uuid = mei_me_cl_uuid(device->me_cl); + + if (add_uevent_var(env, "MODALIAS=mei:%s:" MEI_CL_UUID_FMT ":", + device->name, MEI_CL_UUID_ARGS(uuid->b))) return -ENOMEM; return 0; @@ -185,7 +209,9 @@ struct mei_cl_device *mei_cl_add_device(struct mei_device *dev, device->dev.bus = &mei_cl_bus_type; device->dev.type = &mei_cl_device_type; - dev_set_name(&device->dev, "%s", name); + strlcpy(device->name, name, sizeof(device->name)); + + dev_set_name(&device->dev, "mei:%s:%pUl", name, mei_me_cl_uuid(me_cl)); status = device_register(&device->dev); if (status) { diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index 79ab78184523..ab719e674edf 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -376,6 +376,7 @@ struct mei_cl *mei_cl_bus_find_cl_by_uuid(struct mei_device *dev, uuid_le uuid); * @dev: linux driver model device pointer * @me_cl: me client * @cl: mei client + * @name: device name * @ops: ME transport ops * @event_work: async work to execute event callback * @event_cb: Drivers register this callback to get asynchronous ME @@ -389,6 +390,7 @@ struct mei_cl_device { struct mei_me_client *me_cl; struct mei_cl *cl; + char name[MEI_CL_NAME_SIZE]; const struct mei_cl_ops *ops; diff --git a/drivers/nfc/mei_phy.h b/drivers/nfc/mei_phy.h index d669900f8278..06608c28ff14 100644 --- a/drivers/nfc/mei_phy.h +++ b/drivers/nfc/mei_phy.h @@ -3,7 +3,10 @@ #include #include +#include +#define MEI_NFC_UUID __UUID_LE(0x0bb17a78, 0x2a8e, 0x4c50, \ + 0x94, 0xd4, 0x50, 0x26, 0x67, 0x23, 0x77, 0x5c) #define MEI_NFC_HEADER_SIZE 10 #define MEI_NFC_MAX_HCI_PAYLOAD 300 diff --git a/drivers/nfc/microread/mei.c b/drivers/nfc/microread/mei.c index 2d1395be64ae..f9f5fc97cdd7 100644 --- a/drivers/nfc/microread/mei.c +++ b/drivers/nfc/microread/mei.c @@ -67,7 +67,7 @@ static int microread_mei_remove(struct mei_cl_device *device) } static struct mei_cl_device_id microread_mei_tbl[] = { - { MICROREAD_DRIVER_NAME }, + { MICROREAD_DRIVER_NAME, MEI_NFC_UUID}, /* required last entry */ { } diff --git a/drivers/nfc/pn544/mei.c b/drivers/nfc/pn544/mei.c index 330cd4031009..101a37e12efa 100644 --- a/drivers/nfc/pn544/mei.c +++ b/drivers/nfc/pn544/mei.c @@ -67,7 +67,7 @@ static int pn544_mei_remove(struct mei_cl_device *device) } static struct mei_cl_device_id pn544_mei_tbl[] = { - { PN544_DRIVER_NAME }, + { PN544_DRIVER_NAME, MEI_NFC_UUID}, /* required last entry */ { } diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 3bfd56778c29..2d2b2b571d61 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -599,9 +599,22 @@ struct ipack_device_id { #define MEI_CL_MODULE_PREFIX "mei:" #define MEI_CL_NAME_SIZE 32 +#define MEI_CL_UUID_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" +#define MEI_CL_UUID_ARGS(_u) \ + _u[0], _u[1], _u[2], _u[3], _u[4], _u[5], _u[6], _u[7], \ + _u[8], _u[9], _u[10], _u[11], _u[12], _u[13], _u[14], _u[15] +/** + * struct mei_cl_device_id - MEI client device identifier + * @name: helper name + * @uuid: client uuid + * @driver_info: information used by the driver. + * + * identifies mei client device by uuid and name + */ struct mei_cl_device_id { char name[MEI_CL_NAME_SIZE]; + __u8 uuid[16]; kernel_ulong_t driver_info; }; diff --git a/scripts/mod/devicetable-offsets.c b/scripts/mod/devicetable-offsets.c index fce36d0f6898..091f6290a651 100644 --- a/scripts/mod/devicetable-offsets.c +++ b/scripts/mod/devicetable-offsets.c @@ -182,6 +182,7 @@ int main(void) DEVID(mei_cl_device_id); DEVID_FIELD(mei_cl_device_id, name); + DEVID_FIELD(mei_cl_device_id, uuid); DEVID(rio_device_id); DEVID_FIELD(rio_device_id, did); diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c index 78691d51a479..62c517f4b592 100644 --- a/scripts/mod/file2alias.c +++ b/scripts/mod/file2alias.c @@ -131,6 +131,15 @@ static inline void add_wildcard(char *str) strcat(str + len, "*"); } +static inline void add_uuid(char *str, __u8 uuid[16]) +{ + int len = strlen(str); + int i; + + for (i = 0; i < 16; i++) + sprintf(str + len + (i << 1), "%02x", uuid[i]); +} + /** * Check that sizeof(device_id type) are consistent with size of section * in .o file. If in-consistent then userspace and kernel does not agree @@ -1160,13 +1169,18 @@ static int do_cpu_entry(const char *filename, void *symval, char *alias) } ADD_TO_DEVTABLE("cpu", cpu_feature, do_cpu_entry); -/* Looks like: mei:S */ +/* Looks like: mei:S:uuid */ static int do_mei_entry(const char *filename, void *symval, char *alias) { DEF_FIELD_ADDR(symval, mei_cl_device_id, name); + DEF_FIELD_ADDR(symval, mei_cl_device_id, uuid); + + sprintf(alias, MEI_CL_MODULE_PREFIX); + sprintf(alias + strlen(alias), "%s:", (*name)[0] ? *name : "*"); + add_uuid(alias, *uuid); - sprintf(alias, MEI_CL_MODULE_PREFIX "%s", *name); + strcat(alias, ":*"); return 1; } -- cgit v1.2.3 From 007d64eb2232b91aa86b51abc1742936807e0bd4 Mon Sep 17 00:00:00 2001 From: Tomas Winkler Date: Thu, 7 May 2015 15:54:03 +0300 Subject: mei: bus: add name and uuid into device attributes Export name and uuid via sysfs and uevent Cc: linux-api@vger.kernel.org Signed-off-by: Tomas Winkler Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-bus-mei | 14 ++++++++++++++ drivers/misc/mei/bus.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-mei b/Documentation/ABI/testing/sysfs-bus-mei index 91967a70313a..20e4d1638bac 100644 --- a/Documentation/ABI/testing/sysfs-bus-mei +++ b/Documentation/ABI/testing/sysfs-bus-mei @@ -5,3 +5,17 @@ Contact: Samuel Ortiz linux-mei@linux.intel.com Description: Stores the same MODALIAS value emitted by uevent Format: mei::: + +What: /sys/bus/mei/devices/.../name +Date: May 2015 +KernelVersion: 4.2 +Contact: Tomas Winkler +Description: Stores mei client device name + Format: string + +What: /sys/bus/mei/devices/.../uuid +Date: May 2015 +KernelVersion: 4.2 +Contact: Tomas Winkler +Description: Stores mei client device uuid + Format: xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index 17b00baa53b1..e76d94aa6e12 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -114,6 +114,31 @@ static int mei_cl_device_remove(struct device *dev) return driver->remove(device); } +static ssize_t name_show(struct device *dev, struct device_attribute *a, + char *buf) +{ + struct mei_cl_device *device = to_mei_cl_device(dev); + size_t len; + + len = snprintf(buf, PAGE_SIZE, "%s", device->name); + + return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len; +} +static DEVICE_ATTR_RO(name); + +static ssize_t uuid_show(struct device *dev, struct device_attribute *a, + char *buf) +{ + struct mei_cl_device *device = to_mei_cl_device(dev); + const uuid_le *uuid = mei_me_cl_uuid(device->me_cl); + size_t len; + + len = snprintf(buf, PAGE_SIZE, "%pUl", uuid); + + return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len; +} +static DEVICE_ATTR_RO(uuid); + static ssize_t modalias_show(struct device *dev, struct device_attribute *a, char *buf) { @@ -129,6 +154,8 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *a, static DEVICE_ATTR_RO(modalias); static struct attribute *mei_cl_dev_attrs[] = { + &dev_attr_name.attr, + &dev_attr_uuid.attr, &dev_attr_modalias.attr, NULL, }; @@ -139,6 +166,12 @@ static int mei_cl_uevent(struct device *dev, struct kobj_uevent_env *env) struct mei_cl_device *device = to_mei_cl_device(dev); const uuid_le *uuid = mei_me_cl_uuid(device->me_cl); + if (add_uevent_var(env, "MEI_CL_UUID=%pUl", uuid)) + return -ENOMEM; + + if (add_uevent_var(env, "MEI_CL_NAME=%s", device->name)) + return -ENOMEM; + if (add_uevent_var(env, "MODALIAS=mei:%s:" MEI_CL_UUID_FMT ":", device->name, MEI_CL_UUID_ARGS(uuid->b))) return -ENOMEM; -- cgit v1.2.3 From c3098356927254be270e5dc186a2ca144b64463b Mon Sep 17 00:00:00 2001 From: Dmitry Khromov Date: Tue, 12 May 2015 22:29:44 +0300 Subject: w1: introduce an ability to specify microseconds bus scanning intervals Some of 1-Wire devices commonly associated with physical access control systems are attached/generate presence for as short as 100 ms - hence the tens-to-hundreds milliseconds scan intervals are required. Signed-off-by: Dmitry Khromov Acked-by: Evgeniy Polyakov Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/stable/sysfs-bus-w1 | 11 +++++++++++ Documentation/w1/w1.generic | 30 +++++++++++++++++++----------- drivers/w1/w1.c | 17 ++++++++++++++++- 3 files changed, 46 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/stable/sysfs-bus-w1 (limited to 'Documentation') diff --git a/Documentation/ABI/stable/sysfs-bus-w1 b/Documentation/ABI/stable/sysfs-bus-w1 new file mode 100644 index 000000000000..140d85b4ae92 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-bus-w1 @@ -0,0 +1,11 @@ +What: /sys/bus/w1/devices/.../w1_master_timeout_us +Date: April 2015 +Contact: Dmitry Khromov +Description: Bus scanning interval, microseconds component. + Some of 1-Wire devices commonly associated with physical access + control systems are attached/generate presence for as short as + 100 ms - hence the tens-to-hundreds milliseconds scan intervals + are required. + see Documentation/w1/w1.generic for detailed information. +Users: any user space application which wants to know bus scanning + interval diff --git a/Documentation/w1/w1.generic b/Documentation/w1/w1.generic index b2033c64c7da..b3ffaf8cfab2 100644 --- a/Documentation/w1/w1.generic +++ b/Documentation/w1/w1.generic @@ -76,21 +76,24 @@ See struct w1_bus_master definition in w1.h for details. w1 master sysfs interface ------------------------------------------------------------------ - - a directory for a found device. The format is family-serial + - A directory for a found device. The format is family-serial bus - (standard) symlink to the w1 bus driver - (standard) symlink to the w1 driver -w1_master_add - Manually register a slave device -w1_master_attempts - the number of times a search was attempted +w1_master_add - (rw) manually register a slave device +w1_master_attempts - (ro) the number of times a search was attempted w1_master_max_slave_count - - maximum number of slaves to search for at a time -w1_master_name - the name of the device (w1_bus_masterX) -w1_master_pullup - 5V strong pullup 0 enabled, 1 disabled -w1_master_remove - Manually remove a slave device -w1_master_search - the number of searches left to do, -1=continual (default) + - (rw) maximum number of slaves to search for at a time +w1_master_name - (ro) the name of the device (w1_bus_masterX) +w1_master_pullup - (rw) 5V strong pullup 0 enabled, 1 disabled +w1_master_remove - (rw) manually remove a slave device +w1_master_search - (rw) the number of searches left to do, + -1=continual (default) w1_master_slave_count - - the number of slaves found -w1_master_slaves - the names of the slaves, one per line -w1_master_timeout - the delay in seconds between searches + - (ro) the number of slaves found +w1_master_slaves - (ro) the names of the slaves, one per line +w1_master_timeout - (ro) the delay in seconds between searches +w1_master_timeout_us + - (ro) the delay in microseconds beetwen searches If you have a w1 bus that never changes (you don't add or remove devices), you can set the module parameter search_count to a small positive number @@ -101,6 +104,11 @@ generally only make sense when searching is disabled, as a search will redetect manually removed devices that are present and timeout manually added devices that aren't on the bus. +Bus searches occur at an interval, specified as a summ of timeout and +timeout_us module parameters (either of which may be 0) for as long as +w1_master_search remains greater than 0 or is -1. Each search attempt +decrements w1_master_search by 1 (down to 0) and increments +w1_master_attempts by 1. w1 slave sysfs interface ------------------------------------------------------------------ diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c index 181f41cb960b..c9a7ff67d395 100644 --- a/drivers/w1/w1.c +++ b/drivers/w1/w1.c @@ -46,11 +46,15 @@ MODULE_AUTHOR("Evgeniy Polyakov "); MODULE_DESCRIPTION("Driver for 1-wire Dallas network protocol."); static int w1_timeout = 10; +static int w1_timeout_us = 0; int w1_max_slave_count = 64; int w1_max_slave_ttl = 10; module_param_named(timeout, w1_timeout, int, 0); MODULE_PARM_DESC(timeout, "time in seconds between automatic slave searches"); +module_param_named(timeout_us, w1_timeout_us, int, 0); +MODULE_PARM_DESC(timeout, "time in microseconds between automatic slave" + " searches"); /* A search stops when w1_max_slave_count devices have been found in that * search. The next search will start over and detect the same set of devices * on a static 1-wire bus. Memory is not allocated based on this number, just @@ -317,6 +321,14 @@ static ssize_t w1_master_attribute_show_timeout(struct device *dev, struct devic return count; } +static ssize_t w1_master_attribute_show_timeout_us(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t count; + count = sprintf(buf, "%d\n", w1_timeout_us); + return count; +} + static ssize_t w1_master_attribute_store_max_slave_count(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -543,6 +555,7 @@ static W1_MASTER_ATTR_RO(slave_count, S_IRUGO); static W1_MASTER_ATTR_RW(max_slave_count, S_IRUGO | S_IWUSR | S_IWGRP); static W1_MASTER_ATTR_RO(attempts, S_IRUGO); static W1_MASTER_ATTR_RO(timeout, S_IRUGO); +static W1_MASTER_ATTR_RO(timeout_us, S_IRUGO); static W1_MASTER_ATTR_RO(pointer, S_IRUGO); static W1_MASTER_ATTR_RW(search, S_IRUGO | S_IWUSR | S_IWGRP); static W1_MASTER_ATTR_RW(pullup, S_IRUGO | S_IWUSR | S_IWGRP); @@ -556,6 +569,7 @@ static struct attribute *w1_master_default_attrs[] = { &w1_master_attribute_max_slave_count.attr, &w1_master_attribute_attempts.attr, &w1_master_attribute_timeout.attr, + &w1_master_attribute_timeout_us.attr, &w1_master_attribute_pointer.attr, &w1_master_attribute_search.attr, &w1_master_attribute_pullup.attr, @@ -1108,7 +1122,8 @@ int w1_process(void *data) /* As long as w1_timeout is only set by a module parameter the sleep * time can be calculated in jiffies once. */ - const unsigned long jtime = msecs_to_jiffies(w1_timeout * 1000); + const unsigned long jtime = + usecs_to_jiffies(w1_timeout * 1000000 + w1_timeout_us); /* remainder if it woke up early */ unsigned long jremain = 0; -- cgit v1.2.3 From d9411e57dc7fcdbf28eb825d090b06b4248a95bc Mon Sep 17 00:00:00 2001 From: Matt Campbell Date: Tue, 28 Apr 2015 07:44:17 -0400 Subject: w1: Add support for DS28EA00 sequence to w1-therm This patch provides support for the DS28EA00 digital thermometer. The DS28EA00 provides an additional two pins for implementing a sequence detection algorithm. This feature allows you to determine the physical location of the chip in the 1-wire bus without needing pre-existing knowledge of the bus ordering. Support is provided through the sysfs w1_seq file. The file will contain a single line with an integer value representing the device index in the bus starting at 0. Signed-off-by: Matt Campbell Acked-by: Evgeniy Polyakov Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 | 6 ++ Documentation/w1/slaves/w1_therm | 11 ++- drivers/w1/slaves/w1_therm.c | 102 +++++++++++++++++++++- 3 files changed, 117 insertions(+), 2 deletions(-) create mode 100644 Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 (limited to 'Documentation') diff --git a/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 b/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 new file mode 100644 index 000000000000..e928def14f28 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 @@ -0,0 +1,6 @@ +What: /sys/bus/w1/devices/.../w1_seq +Date: Apr 2015 +Contact: Matt Campbell +Description: Support for the DS28EA00 chain sequence function + see Documentation/w1/slaves/w1_therm for detailed information +Users: any user space application which wants to communicate with DS28EA00 diff --git a/Documentation/w1/slaves/w1_therm b/Documentation/w1/slaves/w1_therm index cc62a95e4776..13411fe52f7f 100644 --- a/Documentation/w1/slaves/w1_therm +++ b/Documentation/w1/slaves/w1_therm @@ -11,12 +11,14 @@ Author: Evgeniy Polyakov Description ----------- -w1_therm provides basic temperature conversion for ds18*20 devices. +w1_therm provides basic temperature conversion for ds18*20 devices, and the +ds28ea00 device. supported family codes: W1_THERM_DS18S20 0x10 W1_THERM_DS1822 0x22 W1_THERM_DS18B20 0x28 W1_THERM_DS1825 0x3B +W1_THERM_DS28EA00 0x42 Support is provided through the sysfs w1_slave file. Each open and read sequence will initiate a temperature conversion then provide two @@ -48,3 +50,10 @@ resistor). The DS18b20 temperature sensor specification lists a maximum current draw of 1.5mA and that a 5k pullup resistor is not sufficient. The strong pullup is designed to provide the additional current required. + +The DS28EA00 provides an additional two pins for implementing a sequence +detection algorithm. This feature allows you to determine the physical +location of the chip in the 1-wire bus without needing pre-existing +knowledge of the bus ordering. Support is provided through the sysfs +w1_seq file. The file will contain a single line with an integer value +representing the device index in the bus starting at 0. diff --git a/drivers/w1/slaves/w1_therm.c b/drivers/w1/slaves/w1_therm.c index 55eb86c9e214..d21e6864b06f 100644 --- a/drivers/w1/slaves/w1_therm.c +++ b/drivers/w1/slaves/w1_therm.c @@ -92,13 +92,24 @@ static void w1_therm_remove_slave(struct w1_slave *sl) static ssize_t w1_slave_show(struct device *device, struct device_attribute *attr, char *buf); +static ssize_t w1_seq_show(struct device *device, + struct device_attribute *attr, char *buf); + static DEVICE_ATTR_RO(w1_slave); +static DEVICE_ATTR_RO(w1_seq); static struct attribute *w1_therm_attrs[] = { &dev_attr_w1_slave.attr, NULL, }; + +static struct attribute *w1_ds28ea00_attrs[] = { + &dev_attr_w1_slave.attr, + &dev_attr_w1_seq.attr, + NULL, +}; ATTRIBUTE_GROUPS(w1_therm); +ATTRIBUTE_GROUPS(w1_ds28ea00); static struct w1_family_ops w1_therm_fops = { .add_slave = w1_therm_add_slave, @@ -106,6 +117,12 @@ static struct w1_family_ops w1_therm_fops = { .groups = w1_therm_groups, }; +static struct w1_family_ops w1_ds28ea00_fops = { + .add_slave = w1_therm_add_slave, + .remove_slave = w1_therm_remove_slave, + .groups = w1_ds28ea00_groups, +}; + static struct w1_family w1_therm_family_DS18S20 = { .fid = W1_THERM_DS18S20, .fops = &w1_therm_fops, @@ -123,7 +140,7 @@ static struct w1_family w1_therm_family_DS1822 = { static struct w1_family w1_therm_family_DS28EA00 = { .fid = W1_THERM_DS28EA00, - .fops = &w1_therm_fops, + .fops = &w1_ds28ea00_fops, }; static struct w1_family w1_therm_family_DS1825 = { @@ -316,6 +333,89 @@ post_unlock: return ret; } +#define W1_42_CHAIN 0x99 +#define W1_42_CHAIN_OFF 0x3C +#define W1_42_CHAIN_OFF_INV 0xC3 +#define W1_42_CHAIN_ON 0x5A +#define W1_42_CHAIN_ON_INV 0xA5 +#define W1_42_CHAIN_DONE 0x96 +#define W1_42_CHAIN_DONE_INV 0x69 +#define W1_42_COND_READ 0x0F +#define W1_42_SUCCESS_CONFIRM_BYTE 0xAA +#define W1_42_FINISHED_BYTE 0xFF +static ssize_t w1_seq_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + ssize_t c = PAGE_SIZE; + int rv; + int i; + u8 ack; + u64 rn; + struct w1_reg_num *reg_num; + int seq = 0; + + mutex_lock(&sl->master->mutex); + /* Place all devices in CHAIN state */ + if (w1_reset_bus(sl->master)) + goto error; + w1_write_8(sl->master, W1_SKIP_ROM); + w1_write_8(sl->master, W1_42_CHAIN); + w1_write_8(sl->master, W1_42_CHAIN_ON); + w1_write_8(sl->master, W1_42_CHAIN_ON_INV); + msleep(sl->master->pullup_duration); + + /* check for acknowledgment */ + ack = w1_read_8(sl->master); + if (ack != W1_42_SUCCESS_CONFIRM_BYTE) + goto error; + + /* In case the bus fails to send 0xFF, limit*/ + for (i = 0; i <= 64; i++) { + if (w1_reset_bus(sl->master)) + goto error; + + w1_write_8(sl->master, W1_42_COND_READ); + rv = w1_read_block(sl->master, (u8 *)&rn, 8); + reg_num = (struct w1_reg_num *) &rn; + if ((char)reg_num->family == W1_42_FINISHED_BYTE) + break; + if (sl->reg_num.id == reg_num->id) + seq = i; + + w1_write_8(sl->master, W1_42_CHAIN); + w1_write_8(sl->master, W1_42_CHAIN_DONE); + w1_write_8(sl->master, W1_42_CHAIN_DONE_INV); + w1_read_block(sl->master, &ack, sizeof(ack)); + + /* check for acknowledgment */ + ack = w1_read_8(sl->master); + if (ack != W1_42_SUCCESS_CONFIRM_BYTE) + goto error; + + } + + /* Exit from CHAIN state */ + if (w1_reset_bus(sl->master)) + goto error; + w1_write_8(sl->master, W1_SKIP_ROM); + w1_write_8(sl->master, W1_42_CHAIN); + w1_write_8(sl->master, W1_42_CHAIN_OFF); + w1_write_8(sl->master, W1_42_CHAIN_OFF_INV); + + /* check for acknowledgment */ + ack = w1_read_8(sl->master); + if (ack != W1_42_SUCCESS_CONFIRM_BYTE) + goto error; + mutex_unlock(&sl->master->mutex); + + c -= snprintf(buf + PAGE_SIZE - c, c, "%d\n", seq); + return PAGE_SIZE - c; +error: + mutex_unlock(&sl->master->bus_mutex); + return -EIO; +} + static int __init w1_therm_init(void) { int err, i; -- cgit v1.2.3 From 7df20f2d893db42eaa1ea1e30a2573c971ec9238 Mon Sep 17 00:00:00 2001 From: Sudeep Dutt Date: Wed, 29 Apr 2015 05:32:28 -0700 Subject: misc: mic: SCIF header file and IOCTL interface This patch introduces the SCIF documentation in the header file and describes the IOCTL interface for user mode. mic_overview.txt is updated with documentation on SCIF and a new document describing SCIF in more details is available in scif_overview.txt. Reviewed-by: Nikhil Rao Reviewed-by: Ashutosh Dixit Signed-off-by: Sudeep Dutt Signed-off-by: Greg Kroah-Hartman --- Documentation/mic/mic_overview.txt | 28 +- Documentation/mic/scif_overview.txt | 98 ++++ include/linux/scif.h | 993 ++++++++++++++++++++++++++++++++++++ include/uapi/linux/Kbuild | 1 + include/uapi/linux/scif_ioctl.h | 130 +++++ 5 files changed, 1238 insertions(+), 12 deletions(-) create mode 100644 Documentation/mic/scif_overview.txt create mode 100644 include/linux/scif.h create mode 100644 include/uapi/linux/scif_ioctl.h (limited to 'Documentation') diff --git a/Documentation/mic/mic_overview.txt b/Documentation/mic/mic_overview.txt index 77c541802ad9..1a2f2c8ec59e 100644 --- a/Documentation/mic/mic_overview.txt +++ b/Documentation/mic/mic_overview.txt @@ -24,6 +24,10 @@ a virtual bus called mic bus is created and virtual dma devices are created on it by the host/card drivers. On host the channels are private and used only by the host driver to transfer data for the virtio devices. +The Symmetric Communication Interface (SCIF (pronounced as skiff)) is a +low level communications API across PCIe currently implemented for MIC. +More details are available at scif_overview.txt. + Here is a block diagram of the various components described above. The virtio backends are situated on the host rather than the card given better single threaded performance for the host compared to MIC, the ability of @@ -47,18 +51,18 @@ the fact that the virtio block storage backend can only be on the host. | | | Virtio over PCIe IOCTLs | | | +--------------------------+ +-----------+ | | | +-----------+ -| MIC DMA | | | | | MIC DMA | -| Driver | | | | | Driver | -+-----------+ | | | +-----------+ - | | | | | -+---------------+ | | | +----------------+ -|MIC virtual Bus| | | | |MIC virtual Bus | -+---------------+ | | | +----------------+ - | | | | | - | +--------------+ | +---------------+ | - | |Intel MIC | | |Intel MIC | | - +---|Card Driver | | |Host Driver | | - +--------------+ | +---------------+-----+ +| MIC DMA | | +----------+ | +-----------+ | | MIC DMA | +| Driver | | | SCIF | | | SCIF | | | Driver | ++-----------+ | +----------+ | +-----------+ | +-----------+ + | | | | | | | ++---------------+ | +-----+-----+ | +-----+-----+ | +---------------+ +|MIC virtual Bus| | |SCIF HW Bus| | |SCIF HW BUS| | |MIC virtual Bus| ++---------------+ | +-----------+ | +-----+-----+ | +---------------+ + | | | | | | | + | +--------------+ | | | +---------------+ | + | |Intel MIC | | | | |Intel MIC | | + +---|Card Driver +----+ | | |Host Driver | | + +--------------+ | +----+---------------+-----+ | | | +-------------------------------------------------------------+ | | diff --git a/Documentation/mic/scif_overview.txt b/Documentation/mic/scif_overview.txt new file mode 100644 index 000000000000..0a280d986731 --- /dev/null +++ b/Documentation/mic/scif_overview.txt @@ -0,0 +1,98 @@ +The Symmetric Communication Interface (SCIF (pronounced as skiff)) is a low +level communications API across PCIe currently implemented for MIC. Currently +SCIF provides inter-node communication within a single host platform, where a +node is a MIC Coprocessor or Xeon based host. SCIF abstracts the details of +communicating over the PCIe bus while providing an API that is symmetric +across all the nodes in the PCIe network. An important design objective for SCIF +is to deliver the maximum possible performance given the communication +abilities of the hardware. SCIF has been used to implement an offload compiler +runtime and OFED support for MPI implementations for MIC coprocessors. + +==== SCIF API Components ==== +The SCIF API has the following parts: +1. Connection establishment using a client server model +2. Byte stream messaging intended for short messages +3. Node enumeration to determine online nodes +4. Poll semantics for detection of incoming connections and messages +5. Memory registration to pin down pages +6. Remote memory mapping for low latency CPU accesses via mmap +7. Remote DMA (RDMA) for high bandwidth DMA transfers +8. Fence APIs for RDMA synchronization + +SCIF exposes the notion of a connection which can be used by peer processes on +nodes in a SCIF PCIe "network" to share memory "windows" and to communicate. A +process in a SCIF node initiates a SCIF connection to a peer process on a +different node via a SCIF "endpoint". SCIF endpoints support messaging APIs +which are similar to connection oriented socket APIs. Connected SCIF endpoints +can also register local memory which is followed by data transfer using either +DMA, CPU copies or remote memory mapping via mmap. SCIF supports both user and +kernel mode clients which are functionally equivalent. + +==== SCIF Performance for MIC ==== +DMA bandwidth comparison between the TCP (over ethernet over PCIe) stack versus +SCIF shows the performance advantages of SCIF for HPC applications and runtimes. + + Comparison of TCP and SCIF based BW + + Throughput (GB/sec) + 8 + PCIe Bandwidth ****** + + TCP ###### + 7 + ************************************** SCIF %%%%%% + | %%%%%%%%%%%%%%%%%%% + 6 + %%%% + | %% + | %%% + 5 + %% + | %% + 4 + %% + | %% + 3 + %% + | % + 2 + %% + | %% + | % + 1 + + + ###################################### + 0 +++---+++--+--+-+--+--+-++-+--+-++-+--+-++-+- + 1 10 100 1000 10000 100000 + Transfer Size (KBytes) + +SCIF allows memory sharing via mmap(..) between processes on different PCIe +nodes and thus provides bare-metal PCIe latency. The round trip SCIF mmap +latency from the host to an x100 MIC for an 8 byte message is 0.44 usecs. + +SCIF has a user space library which is a thin IOCTL wrapper providing a user +space API similar to the kernel API in scif.h. The SCIF user space library +is distributed @ https://software.intel.com/en-us/mic-developer + +Here is some pseudo code for an example of how two applications on two PCIe +nodes would typically use the SCIF API: + +Process A (on node A) Process B (on node B) + +/* get online node information */ +scif_get_node_ids(..) scif_get_node_ids(..) +scif_open(..) scif_open(..) +scif_bind(..) scif_bind(..) +scif_listen(..) +scif_accept(..) scif_connect(..) +/* SCIF connection established */ + +/* Send and receive short messages */ +scif_send(..)/scif_recv(..) scif_send(..)/scif_recv(..) + +/* Register memory */ +scif_register(..) scif_register(..) + +/* RDMA */ +scif_readfrom(..)/scif_writeto(..) scif_readfrom(..)/scif_writeto(..) + +/* Fence DMAs */ +scif_fence_signal(..) scif_fence_signal(..) + +mmap(..) mmap(..) + +/* Access remote registered memory */ + +/* Close the endpoints */ +scif_close(..) scif_close(..) diff --git a/include/linux/scif.h b/include/linux/scif.h new file mode 100644 index 000000000000..44f4f3898bbe --- /dev/null +++ b/include/linux/scif.h @@ -0,0 +1,993 @@ +/* + * Intel MIC Platform Software Stack (MPSS) + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2014 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * BSD LICENSE + * + * Copyright(c) 2014 Intel Corporation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Intel SCIF driver. + * + */ +#ifndef __SCIF_H__ +#define __SCIF_H__ + +#include +#include +#include + +#define SCIF_ACCEPT_SYNC 1 +#define SCIF_SEND_BLOCK 1 +#define SCIF_RECV_BLOCK 1 + +enum { + SCIF_PROT_READ = (1 << 0), + SCIF_PROT_WRITE = (1 << 1) +}; + +enum { + SCIF_MAP_FIXED = 0x10, + SCIF_MAP_KERNEL = 0x20, +}; + +enum { + SCIF_FENCE_INIT_SELF = (1 << 0), + SCIF_FENCE_INIT_PEER = (1 << 1), + SCIF_SIGNAL_LOCAL = (1 << 4), + SCIF_SIGNAL_REMOTE = (1 << 5) +}; + +enum { + SCIF_RMA_USECPU = (1 << 0), + SCIF_RMA_USECACHE = (1 << 1), + SCIF_RMA_SYNC = (1 << 2), + SCIF_RMA_ORDERED = (1 << 3) +}; + +/* End of SCIF Admin Reserved Ports */ +#define SCIF_ADMIN_PORT_END 1024 + +/* End of SCIF Reserved Ports */ +#define SCIF_PORT_RSVD 1088 + +typedef struct scif_endpt *scif_epd_t; + +#define SCIF_OPEN_FAILED ((scif_epd_t)-1) +#define SCIF_REGISTER_FAILED ((off_t)-1) +#define SCIF_MMAP_FAILED ((void *)-1) + +/** + * scif_open() - Create an endpoint + * + * Return: + * Upon successful completion, scif_open() returns an endpoint descriptor to + * be used in subsequent SCIF functions calls to refer to that endpoint; + * otherwise in user mode SCIF_OPEN_FAILED (that is ((scif_epd_t)-1)) is + * returned and errno is set to indicate the error; in kernel mode a NULL + * scif_epd_t is returned. + * + * Errors: + * ENOMEM - Insufficient kernel memory was available + */ +scif_epd_t scif_open(void); + +/** + * scif_bind() - Bind an endpoint to a port + * @epd: endpoint descriptor + * @pn: port number + * + * scif_bind() binds endpoint epd to port pn, where pn is a port number on the + * local node. If pn is zero, a port number greater than or equal to + * SCIF_PORT_RSVD is assigned and returned. Each endpoint may be bound to + * exactly one local port. Ports less than 1024 when requested can only be bound + * by system (or root) processes or by processes executed by privileged users. + * + * Return: + * Upon successful completion, scif_bind() returns the port number to which epd + * is bound; otherwise in user mode -1 is returned and errno is set to + * indicate the error; in kernel mode the negative of one of the following + * errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * EINVAL - the endpoint or the port is already bound + * EISCONN - The endpoint is already connected + * ENOSPC - No port number available for assignment + * EACCES - The port requested is protected and the user is not the superuser + */ +int scif_bind(scif_epd_t epd, u16 pn); + +/** + * scif_listen() - Listen for connections on an endpoint + * @epd: endpoint descriptor + * @backlog: maximum pending connection requests + * + * scif_listen() marks the endpoint epd as a listening endpoint - that is, as + * an endpoint that will be used to accept incoming connection requests. Once + * so marked, the endpoint is said to be in the listening state and may not be + * used as the endpoint of a connection. + * + * The endpoint, epd, must have been bound to a port. + * + * The backlog argument defines the maximum length to which the queue of + * pending connections for epd may grow. If a connection request arrives when + * the queue is full, the client may receive an error with an indication that + * the connection was refused. + * + * Return: + * Upon successful completion, scif_listen() returns 0; otherwise in user mode + * -1 is returned and errno is set to indicate the error; in kernel mode the + * negative of one of the following errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * EINVAL - the endpoint is not bound to a port + * EISCONN - The endpoint is already connected or listening + */ +int scif_listen(scif_epd_t epd, int backlog); + +/** + * scif_connect() - Initiate a connection on a port + * @epd: endpoint descriptor + * @dst: global id of port to which to connect + * + * The scif_connect() function requests the connection of endpoint epd to remote + * port dst. If the connection is successful, a peer endpoint, bound to dst, is + * created on node dst.node. On successful return, the connection is complete. + * + * If the endpoint epd has not already been bound to a port, scif_connect() + * will bind it to an unused local port. + * + * A connection is terminated when an endpoint of the connection is closed, + * either explicitly by scif_close(), or when a process that owns one of the + * endpoints of the connection is terminated. + * + * In user space, scif_connect() supports an asynchronous connection mode + * if the application has set the O_NONBLOCK flag on the endpoint via the + * fcntl() system call. Setting this flag will result in the calling process + * not to wait during scif_connect(). + * + * Return: + * Upon successful completion, scif_connect() returns the port ID to which the + * endpoint, epd, is bound; otherwise in user mode -1 is returned and errno is + * set to indicate the error; in kernel mode the negative of one of the + * following errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNREFUSED - The destination was not listening for connections or refused + * the connection request + * EINVAL - dst.port is not a valid port ID + * EISCONN - The endpoint is already connected + * ENOMEM - No buffer space is available + * ENODEV - The destination node does not exist, or the node is lost or existed, + * but is not currently in the network since it may have crashed + * ENOSPC - No port number available for assignment + * EOPNOTSUPP - The endpoint is listening and cannot be connected + */ +int scif_connect(scif_epd_t epd, struct scif_port_id *dst); + +/** + * scif_accept() - Accept a connection on an endpoint + * @epd: endpoint descriptor + * @peer: global id of port to which connected + * @newepd: new connected endpoint descriptor + * @flags: flags + * + * The scif_accept() call extracts the first connection request from the queue + * of pending connections for the port on which epd is listening. scif_accept() + * creates a new endpoint, bound to the same port as epd, and allocates a new + * SCIF endpoint descriptor, returned in newepd, for the endpoint. The new + * endpoint is connected to the endpoint through which the connection was + * requested. epd is unaffected by this call, and remains in the listening + * state. + * + * On successful return, peer holds the global port identifier (node id and + * local port number) of the port which requested the connection. + * + * A connection is terminated when an endpoint of the connection is closed, + * either explicitly by scif_close(), or when a process that owns one of the + * endpoints of the connection is terminated. + * + * The number of connections that can (subsequently) be accepted on epd is only + * limited by system resources (memory). + * + * The flags argument is formed by OR'ing together zero or more of the + * following values. + * SCIF_ACCEPT_SYNC - block until a connection request is presented. If + * SCIF_ACCEPT_SYNC is not in flags, and no pending + * connections are present on the queue, scif_accept() + * fails with an EAGAIN error + * + * In user mode, the select() and poll() functions can be used to determine + * when there is a connection request. In kernel mode, the scif_poll() + * function may be used for this purpose. A readable event will be delivered + * when a connection is requested. + * + * Return: + * Upon successful completion, scif_accept() returns 0; otherwise in user mode + * -1 is returned and errno is set to indicate the error; in kernel mode the + * negative of one of the following errors is returned. + * + * Errors: + * EAGAIN - SCIF_ACCEPT_SYNC is not set and no connections are present to be + * accepted or SCIF_ACCEPT_SYNC is not set and remote node failed to complete + * its connection request + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * EINTR - Interrupted function + * EINVAL - epd is not a listening endpoint, or flags is invalid, or peer is + * NULL, or newepd is NULL + * ENODEV - The requesting node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOMEM - Not enough space + * ENOENT - Secondary part of epd registration failed + */ +int scif_accept(scif_epd_t epd, struct scif_port_id *peer, scif_epd_t + *newepd, int flags); + +/** + * scif_close() - Close an endpoint + * @epd: endpoint descriptor + * + * scif_close() closes an endpoint and performs necessary teardown of + * facilities associated with that endpoint. + * + * If epd is a listening endpoint then it will no longer accept connection + * requests on the port to which it is bound. Any pending connection requests + * are rejected. + * + * If epd is a connected endpoint, then its peer endpoint is also closed. RMAs + * which are in-process through epd or its peer endpoint will complete before + * scif_close() returns. Registered windows of the local and peer endpoints are + * released as if scif_unregister() was called against each window. + * + * Closing a SCIF endpoint does not affect local registered memory mapped by + * a SCIF endpoint on a remote node. The local memory remains mapped by the peer + * SCIF endpoint explicitly removed by calling munmap(..) by the peer. + * + * If the peer endpoint's receive queue is not empty at the time that epd is + * closed, then the peer endpoint can be passed as the endpoint parameter to + * scif_recv() until the receive queue is empty. + * + * epd is freed and may no longer be accessed. + * + * Return: + * Upon successful completion, scif_close() returns 0; otherwise in user mode + * -1 is returned and errno is set to indicate the error; in kernel mode the + * negative of one of the following errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + */ +int scif_close(scif_epd_t epd); + +/** + * scif_send() - Send a message + * @epd: endpoint descriptor + * @msg: message buffer address + * @len: message length + * @flags: blocking mode flags + * + * scif_send() sends data to the peer of endpoint epd. Up to len bytes of data + * are copied from memory starting at address msg. On successful execution the + * return value of scif_send() is the number of bytes that were sent, and is + * zero if no bytes were sent because len was zero. scif_send() may be called + * only when the endpoint is in a connected state. + * + * If a scif_send() call is non-blocking, then it sends only those bytes which + * can be sent without waiting, up to a maximum of len bytes. + * + * If a scif_send() call is blocking, then it normally returns after sending + * all len bytes. If a blocking call is interrupted or the connection is + * reset, the call is considered successful if some bytes were sent or len is + * zero, otherwise the call is considered unsuccessful. + * + * In user mode, the select() and poll() functions can be used to determine + * when the send queue is not full. In kernel mode, the scif_poll() function + * may be used for this purpose. + * + * It is recommended that scif_send()/scif_recv() only be used for short + * control-type message communication between SCIF endpoints. The SCIF RMA + * APIs are expected to provide better performance for transfer sizes of + * 1024 bytes or longer for the current MIC hardware and software + * implementation. + * + * scif_send() will block until the entire message is sent if SCIF_SEND_BLOCK + * is passed as the flags argument. + * + * Return: + * Upon successful completion, scif_send() returns the number of bytes sent; + * otherwise in user mode -1 is returned and errno is set to indicate the + * error; in kernel mode the negative of one of the following errors is + * returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EFAULT - An invalid address was specified for a parameter + * EINVAL - flags is invalid, or len is negative + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOMEM - Not enough space + * ENOTCONN - The endpoint is not connected + */ +int scif_send(scif_epd_t epd, void *msg, int len, int flags); + +/** + * scif_recv() - Receive a message + * @epd: endpoint descriptor + * @msg: message buffer address + * @len: message buffer length + * @flags: blocking mode flags + * + * scif_recv() receives data from the peer of endpoint epd. Up to len bytes of + * data are copied to memory starting at address msg. On successful execution + * the return value of scif_recv() is the number of bytes that were received, + * and is zero if no bytes were received because len was zero. scif_recv() may + * be called only when the endpoint is in a connected state. + * + * If a scif_recv() call is non-blocking, then it receives only those bytes + * which can be received without waiting, up to a maximum of len bytes. + * + * If a scif_recv() call is blocking, then it normally returns after receiving + * all len bytes. If the blocking call was interrupted due to a disconnection, + * subsequent calls to scif_recv() will copy all bytes received upto the point + * of disconnection. + * + * In user mode, the select() and poll() functions can be used to determine + * when data is available to be received. In kernel mode, the scif_poll() + * function may be used for this purpose. + * + * It is recommended that scif_send()/scif_recv() only be used for short + * control-type message communication between SCIF endpoints. The SCIF RMA + * APIs are expected to provide better performance for transfer sizes of + * 1024 bytes or longer for the current MIC hardware and software + * implementation. + * + * scif_recv() will block until the entire message is received if + * SCIF_RECV_BLOCK is passed as the flags argument. + * + * Return: + * Upon successful completion, scif_recv() returns the number of bytes + * received; otherwise in user mode -1 is returned and errno is set to + * indicate the error; in kernel mode the negative of one of the following + * errors is returned. + * + * Errors: + * EAGAIN - The destination node is returning from a low power state + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EFAULT - An invalid address was specified for a parameter + * EINVAL - flags is invalid, or len is negative + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOMEM - Not enough space + * ENOTCONN - The endpoint is not connected + */ +int scif_recv(scif_epd_t epd, void *msg, int len, int flags); + +/** + * scif_register() - Mark a memory region for remote access. + * @epd: endpoint descriptor + * @addr: starting virtual address + * @len: length of range + * @offset: offset of window + * @prot_flags: read/write protection flags + * @map_flags: mapping flags + * + * The scif_register() function opens a window, a range of whole pages of the + * registered address space of the endpoint epd, starting at offset po and + * continuing for len bytes. The value of po, further described below, is a + * function of the parameters offset and len, and the value of map_flags. Each + * page of the window represents the physical memory page which backs the + * corresponding page of the range of virtual address pages starting at addr + * and continuing for len bytes. addr and len are constrained to be multiples + * of the page size. A successful scif_register() call returns po. + * + * When SCIF_MAP_FIXED is set in the map_flags argument, po will be offset + * exactly, and offset is constrained to be a multiple of the page size. The + * mapping established by scif_register() will not replace any existing + * registration; an error is returned if any page within the range [offset, + * offset + len - 1] intersects an existing window. + * + * When SCIF_MAP_FIXED is not set, the implementation uses offset in an + * implementation-defined manner to arrive at po. The po value so chosen will + * be an area of the registered address space that the implementation deems + * suitable for a mapping of len bytes. An offset value of 0 is interpreted as + * granting the implementation complete freedom in selecting po, subject to + * constraints described below. A non-zero value of offset is taken to be a + * suggestion of an offset near which the mapping should be placed. When the + * implementation selects a value for po, it does not replace any extant + * window. In all cases, po will be a multiple of the page size. + * + * The physical pages which are so represented by a window are available for + * access in calls to mmap(), scif_readfrom(), scif_writeto(), + * scif_vreadfrom(), and scif_vwriteto(). While a window is registered, the + * physical pages represented by the window will not be reused by the memory + * subsystem for any other purpose. Note that the same physical page may be + * represented by multiple windows. + * + * Subsequent operations which change the memory pages to which virtual + * addresses are mapped (such as mmap(), munmap()) have no effect on + * existing window. + * + * If the process will fork(), it is recommended that the registered + * virtual address range be marked with MADV_DONTFORK. Doing so will prevent + * problems due to copy-on-write semantics. + * + * The prot_flags argument is formed by OR'ing together one or more of the + * following values. + * SCIF_PROT_READ - allow read operations from the window + * SCIF_PROT_WRITE - allow write operations to the window + * + * The map_flags argument can be set to SCIF_MAP_FIXED which interprets a + * fixed offset. + * + * Return: + * Upon successful completion, scif_register() returns the offset at which the + * mapping was placed (po); otherwise in user mode SCIF_REGISTER_FAILED (that + * is (off_t *)-1) is returned and errno is set to indicate the error; in + * kernel mode the negative of one of the following errors is returned. + * + * Errors: + * EADDRINUSE - SCIF_MAP_FIXED is set in map_flags, and pages in the range + * [offset, offset + len -1] are already registered + * EAGAIN - The mapping could not be performed due to lack of resources + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EFAULT - Addresses in the range [addr, addr + len - 1] are invalid + * EINVAL - map_flags is invalid, or prot_flags is invalid, or SCIF_MAP_FIXED is + * set in flags, and offset is not a multiple of the page size, or addr is not a + * multiple of the page size, or len is not a multiple of the page size, or is + * 0, or offset is negative + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOMEM - Not enough space + * ENOTCONN -The endpoint is not connected + */ +off_t scif_register(scif_epd_t epd, void *addr, size_t len, off_t offset, + int prot_flags, int map_flags); + +/** + * scif_unregister() - Mark a memory region for remote access. + * @epd: endpoint descriptor + * @offset: start of range to unregister + * @len: length of range to unregister + * + * The scif_unregister() function closes those previously registered windows + * which are entirely within the range [offset, offset + len - 1]. It is an + * error to specify a range which intersects only a subrange of a window. + * + * On a successful return, pages within the window may no longer be specified + * in calls to mmap(), scif_readfrom(), scif_writeto(), scif_vreadfrom(), + * scif_vwriteto(), scif_get_pages, and scif_fence_signal(). The window, + * however, continues to exist until all previous references against it are + * removed. A window is referenced if there is a mapping to it created by + * mmap(), or if scif_get_pages() was called against the window + * (and the pages have not been returned via scif_put_pages()). A window is + * also referenced while an RMA, in which some range of the window is a source + * or destination, is in progress. Finally a window is referenced while some + * offset in that window was specified to scif_fence_signal(), and the RMAs + * marked by that call to scif_fence_signal() have not completed. While a + * window is in this state, its registered address space pages are not + * available for use in a new registered window. + * + * When all such references to the window have been removed, its references to + * all the physical pages which it represents are removed. Similarly, the + * registered address space pages of the window become available for + * registration in a new window. + * + * Return: + * Upon successful completion, scif_unregister() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. In the event of an + * error, no windows are unregistered. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EINVAL - the range [offset, offset + len - 1] intersects a subrange of a + * window, or offset is negative + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENXIO - Offsets in the range [offset, offset + len - 1] are invalid for the + * registered address space of epd + */ +int scif_unregister(scif_epd_t epd, off_t offset, size_t len); + +/** + * scif_readfrom() - Copy from a remote address space + * @epd: endpoint descriptor + * @loffset: offset in local registered address space to + * which to copy + * @len: length of range to copy + * @roffset: offset in remote registered address space + * from which to copy + * @rma_flags: transfer mode flags + * + * scif_readfrom() copies len bytes from the remote registered address space of + * the peer of endpoint epd, starting at the offset roffset to the local + * registered address space of epd, starting at the offset loffset. + * + * Each of the specified ranges [loffset, loffset + len - 1] and [roffset, + * roffset + len - 1] must be within some registered window or windows of the + * local and remote nodes. A range may intersect multiple registered windows, + * but only if those windows are contiguous in the registered address space. + * + * If rma_flags includes SCIF_RMA_USECPU, then the data is copied using + * programmed read/writes. Otherwise the data is copied using DMA. If rma_- + * flags includes SCIF_RMA_SYNC, then scif_readfrom() will return after the + * transfer is complete. Otherwise, the transfer may be performed asynchron- + * ously. The order in which any two asynchronous RMA operations complete + * is non-deterministic. The synchronization functions, scif_fence_mark()/ + * scif_fence_wait() and scif_fence_signal(), can be used to synchronize to + * the completion of asynchronous RMA operations on the same endpoint. + * + * The DMA transfer of individual bytes is not guaranteed to complete in + * address order. If rma_flags includes SCIF_RMA_ORDERED, then the last + * cacheline or partial cacheline of the source range will become visible on + * the destination node after all other transferred data in the source + * range has become visible on the destination node. + * + * The optimal DMA performance will likely be realized if both + * loffset and roffset are cacheline aligned (are a multiple of 64). Lower + * performance will likely be realized if loffset and roffset are not + * cacheline aligned but are separated by some multiple of 64. The lowest level + * of performance is likely if loffset and roffset are not separated by a + * multiple of 64. + * + * The rma_flags argument is formed by ORing together zero or more of the + * following values. + * SCIF_RMA_USECPU - perform the transfer using the CPU, otherwise use the DMA + * engine. + * SCIF_RMA_SYNC - perform the transfer synchronously, returning after the + * transfer has completed. Passing this flag results in the + * current implementation busy waiting and consuming CPU cycles + * while the DMA transfer is in progress for best performance by + * avoiding the interrupt latency. + * SCIF_RMA_ORDERED - ensure that the last cacheline or partial cacheline of + * the source range becomes visible on the destination node + * after all other transferred data in the source range has + * become visible on the destination + * + * Return: + * Upon successful completion, scif_readfrom() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. + * + * Errors: + * EACCESS - Attempt to write to a read-only range + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EINVAL - rma_flags is invalid + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENXIO - The range [loffset, loffset + len - 1] is invalid for the registered + * address space of epd, or, The range [roffset, roffset + len - 1] is invalid + * for the registered address space of the peer of epd, or loffset or roffset + * is negative + */ +int scif_readfrom(scif_epd_t epd, off_t loffset, size_t len, off_t + roffset, int rma_flags); + +/** + * scif_writeto() - Copy to a remote address space + * @epd: endpoint descriptor + * @loffset: offset in local registered address space + * from which to copy + * @len: length of range to copy + * @roffset: offset in remote registered address space to + * which to copy + * @rma_flags: transfer mode flags + * + * scif_writeto() copies len bytes from the local registered address space of + * epd, starting at the offset loffset to the remote registered address space + * of the peer of endpoint epd, starting at the offset roffset. + * + * Each of the specified ranges [loffset, loffset + len - 1] and [roffset, + * roffset + len - 1] must be within some registered window or windows of the + * local and remote nodes. A range may intersect multiple registered windows, + * but only if those windows are contiguous in the registered address space. + * + * If rma_flags includes SCIF_RMA_USECPU, then the data is copied using + * programmed read/writes. Otherwise the data is copied using DMA. If rma_- + * flags includes SCIF_RMA_SYNC, then scif_writeto() will return after the + * transfer is complete. Otherwise, the transfer may be performed asynchron- + * ously. The order in which any two asynchronous RMA operations complete + * is non-deterministic. The synchronization functions, scif_fence_mark()/ + * scif_fence_wait() and scif_fence_signal(), can be used to synchronize to + * the completion of asynchronous RMA operations on the same endpoint. + * + * The DMA transfer of individual bytes is not guaranteed to complete in + * address order. If rma_flags includes SCIF_RMA_ORDERED, then the last + * cacheline or partial cacheline of the source range will become visible on + * the destination node after all other transferred data in the source + * range has become visible on the destination node. + * + * The optimal DMA performance will likely be realized if both + * loffset and roffset are cacheline aligned (are a multiple of 64). Lower + * performance will likely be realized if loffset and roffset are not cacheline + * aligned but are separated by some multiple of 64. The lowest level of + * performance is likely if loffset and roffset are not separated by a multiple + * of 64. + * + * The rma_flags argument is formed by ORing together zero or more of the + * following values. + * SCIF_RMA_USECPU - perform the transfer using the CPU, otherwise use the DMA + * engine. + * SCIF_RMA_SYNC - perform the transfer synchronously, returning after the + * transfer has completed. Passing this flag results in the + * current implementation busy waiting and consuming CPU cycles + * while the DMA transfer is in progress for best performance by + * avoiding the interrupt latency. + * SCIF_RMA_ORDERED - ensure that the last cacheline or partial cacheline of + * the source range becomes visible on the destination node + * after all other transferred data in the source range has + * become visible on the destination + * + * Return: + * Upon successful completion, scif_readfrom() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. + * + * Errors: + * EACCESS - Attempt to write to a read-only range + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EINVAL - rma_flags is invalid + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENXIO - The range [loffset, loffset + len - 1] is invalid for the registered + * address space of epd, or, The range [roffset , roffset + len -1] is invalid + * for the registered address space of the peer of epd, or loffset or roffset + * is negative + */ +int scif_writeto(scif_epd_t epd, off_t loffset, size_t len, off_t + roffset, int rma_flags); + +/** + * scif_vreadfrom() - Copy from a remote address space + * @epd: endpoint descriptor + * @addr: address to which to copy + * @len: length of range to copy + * @roffset: offset in remote registered address space + * from which to copy + * @rma_flags: transfer mode flags + * + * scif_vreadfrom() copies len bytes from the remote registered address + * space of the peer of endpoint epd, starting at the offset roffset, to local + * memory, starting at addr. + * + * The specified range [roffset, roffset + len - 1] must be within some + * registered window or windows of the remote nodes. The range may + * intersect multiple registered windows, but only if those windows are + * contiguous in the registered address space. + * + * If rma_flags includes SCIF_RMA_USECPU, then the data is copied using + * programmed read/writes. Otherwise the data is copied using DMA. If rma_- + * flags includes SCIF_RMA_SYNC, then scif_vreadfrom() will return after the + * transfer is complete. Otherwise, the transfer may be performed asynchron- + * ously. The order in which any two asynchronous RMA operations complete + * is non-deterministic. The synchronization functions, scif_fence_mark()/ + * scif_fence_wait() and scif_fence_signal(), can be used to synchronize to + * the completion of asynchronous RMA operations on the same endpoint. + * + * The DMA transfer of individual bytes is not guaranteed to complete in + * address order. If rma_flags includes SCIF_RMA_ORDERED, then the last + * cacheline or partial cacheline of the source range will become visible on + * the destination node after all other transferred data in the source + * range has become visible on the destination node. + * + * If rma_flags includes SCIF_RMA_USECACHE, then the physical pages which back + * the specified local memory range may be remain in a pinned state even after + * the specified transfer completes. This may reduce overhead if some or all of + * the same virtual address range is referenced in a subsequent call of + * scif_vreadfrom() or scif_vwriteto(). + * + * The optimal DMA performance will likely be realized if both + * addr and roffset are cacheline aligned (are a multiple of 64). Lower + * performance will likely be realized if addr and roffset are not + * cacheline aligned but are separated by some multiple of 64. The lowest level + * of performance is likely if addr and roffset are not separated by a + * multiple of 64. + * + * The rma_flags argument is formed by ORing together zero or more of the + * following values. + * SCIF_RMA_USECPU - perform the transfer using the CPU, otherwise use the DMA + * engine. + * SCIF_RMA_USECACHE - enable registration caching + * SCIF_RMA_SYNC - perform the transfer synchronously, returning after the + * transfer has completed. Passing this flag results in the + * current implementation busy waiting and consuming CPU cycles + * while the DMA transfer is in progress for best performance by + * avoiding the interrupt latency. + * SCIF_RMA_ORDERED - ensure that the last cacheline or partial cacheline of + * the source range becomes visible on the destination node + * after all other transferred data in the source range has + * become visible on the destination + * + * Return: + * Upon successful completion, scif_vreadfrom() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. + * + * Errors: + * EACCESS - Attempt to write to a read-only range + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EFAULT - Addresses in the range [addr, addr + len - 1] are invalid + * EINVAL - rma_flags is invalid + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENXIO - Offsets in the range [roffset, roffset + len - 1] are invalid for the + * registered address space of epd + */ +int scif_vreadfrom(scif_epd_t epd, void *addr, size_t len, off_t roffset, + int rma_flags); + +/** + * scif_vwriteto() - Copy to a remote address space + * @epd: endpoint descriptor + * @addr: address from which to copy + * @len: length of range to copy + * @roffset: offset in remote registered address space to + * which to copy + * @rma_flags: transfer mode flags + * + * scif_vwriteto() copies len bytes from the local memory, starting at addr, to + * the remote registered address space of the peer of endpoint epd, starting at + * the offset roffset. + * + * The specified range [roffset, roffset + len - 1] must be within some + * registered window or windows of the remote nodes. The range may intersect + * multiple registered windows, but only if those windows are contiguous in the + * registered address space. + * + * If rma_flags includes SCIF_RMA_USECPU, then the data is copied using + * programmed read/writes. Otherwise the data is copied using DMA. If rma_- + * flags includes SCIF_RMA_SYNC, then scif_vwriteto() will return after the + * transfer is complete. Otherwise, the transfer may be performed asynchron- + * ously. The order in which any two asynchronous RMA operations complete + * is non-deterministic. The synchronization functions, scif_fence_mark()/ + * scif_fence_wait() and scif_fence_signal(), can be used to synchronize to + * the completion of asynchronous RMA operations on the same endpoint. + * + * The DMA transfer of individual bytes is not guaranteed to complete in + * address order. If rma_flags includes SCIF_RMA_ORDERED, then the last + * cacheline or partial cacheline of the source range will become visible on + * the destination node after all other transferred data in the source + * range has become visible on the destination node. + * + * If rma_flags includes SCIF_RMA_USECACHE, then the physical pages which back + * the specified local memory range may be remain in a pinned state even after + * the specified transfer completes. This may reduce overhead if some or all of + * the same virtual address range is referenced in a subsequent call of + * scif_vreadfrom() or scif_vwriteto(). + * + * The optimal DMA performance will likely be realized if both + * addr and offset are cacheline aligned (are a multiple of 64). Lower + * performance will likely be realized if addr and offset are not cacheline + * aligned but are separated by some multiple of 64. The lowest level of + * performance is likely if addr and offset are not separated by a multiple of + * 64. + * + * The rma_flags argument is formed by ORing together zero or more of the + * following values. + * SCIF_RMA_USECPU - perform the transfer using the CPU, otherwise use the DMA + * engine. + * SCIF_RMA_USECACHE - allow registration caching + * SCIF_RMA_SYNC - perform the transfer synchronously, returning after the + * transfer has completed. Passing this flag results in the + * current implementation busy waiting and consuming CPU cycles + * while the DMA transfer is in progress for best performance by + * avoiding the interrupt latency. + * SCIF_RMA_ORDERED - ensure that the last cacheline or partial cacheline of + * the source range becomes visible on the destination node + * after all other transferred data in the source range has + * become visible on the destination + * + * Return: + * Upon successful completion, scif_vwriteto() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. + * + * Errors: + * EACCESS - Attempt to write to a read-only range + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EFAULT - Addresses in the range [addr, addr + len - 1] are invalid + * EINVAL - rma_flags is invalid + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENXIO - Offsets in the range [roffset, roffset + len - 1] are invalid for the + * registered address space of epd + */ +int scif_vwriteto(scif_epd_t epd, void *addr, size_t len, off_t roffset, + int rma_flags); + +/** + * scif_fence_mark() - Mark previously issued RMAs + * @epd: endpoint descriptor + * @flags: control flags + * @mark: marked value returned as output. + * + * scif_fence_mark() returns after marking the current set of all uncompleted + * RMAs initiated through the endpoint epd or the current set of all + * uncompleted RMAs initiated through the peer of endpoint epd. The RMAs are + * marked with a value returned at mark. The application may subsequently call + * scif_fence_wait(), passing the value returned at mark, to await completion + * of all RMAs so marked. + * + * The flags argument has exactly one of the following values. + * SCIF_FENCE_INIT_SELF - RMA operations initiated through endpoint + * epd are marked + * SCIF_FENCE_INIT_PEER - RMA operations initiated through the peer + * of endpoint epd are marked + * + * Return: + * Upon successful completion, scif_fence_mark() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EINVAL - flags is invalid + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENOMEM - Insufficient kernel memory was available + */ +int scif_fence_mark(scif_epd_t epd, int flags, int *mark); + +/** + * scif_fence_wait() - Wait for completion of marked RMAs + * @epd: endpoint descriptor + * @mark: mark request + * + * scif_fence_wait() returns after all RMAs marked with mark have completed. + * The value passed in mark must have been obtained in a previous call to + * scif_fence_mark(). + * + * Return: + * Upon successful completion, scif_fence_wait() returns 0; otherwise in user + * mode -1 is returned and errno is set to indicate the error; in kernel mode + * the negative of one of the following errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENOMEM - Insufficient kernel memory was available + */ +int scif_fence_wait(scif_epd_t epd, int mark); + +/** + * scif_fence_signal() - Request a memory update on completion of RMAs + * @epd: endpoint descriptor + * @loff: local offset + * @lval: local value to write to loffset + * @roff: remote offset + * @rval: remote value to write to roffset + * @flags: flags + * + * scif_fence_signal() returns after marking the current set of all uncompleted + * RMAs initiated through the endpoint epd or marking the current set of all + * uncompleted RMAs initiated through the peer of endpoint epd. + * + * If flags includes SCIF_SIGNAL_LOCAL, then on completion of the RMAs in the + * marked set, lval is written to memory at the address corresponding to offset + * loff in the local registered address space of epd. loff must be within a + * registered window. If flags includes SCIF_SIGNAL_REMOTE, then on completion + * of the RMAs in the marked set, rval is written to memory at the address + * corresponding to offset roff in the remote registered address space of epd. + * roff must be within a remote registered window of the peer of epd. Note + * that any specified offset must be DWORD (4 byte / 32 bit) aligned. + * + * The flags argument is formed by OR'ing together the following. + * Exactly one of the following values. + * SCIF_FENCE_INIT_SELF - RMA operations initiated through endpoint + * epd are marked + * SCIF_FENCE_INIT_PEER - RMA operations initiated through the peer + * of endpoint epd are marked + * One or more of the following values. + * SCIF_SIGNAL_LOCAL - On completion of the marked set of RMAs, write lval to + * memory at the address corresponding to offset loff in the local + * registered address space of epd. + * SCIF_SIGNAL_REMOTE - On completion of the marked set of RMAs, write rval to + * memory at the address corresponding to offset roff in the remote + * registered address space of epd. + * + * Return: + * Upon successful completion, scif_fence_signal() returns 0; otherwise in + * user mode -1 is returned and errno is set to indicate the error; in kernel + * mode the negative of one of the following errors is returned. + * + * Errors: + * EBADF, ENOTTY - epd is not a valid endpoint descriptor + * ECONNRESET - Connection reset by peer + * EINVAL - flags is invalid, or loff or roff are not DWORD aligned + * ENODEV - The remote node is lost or existed, but is not currently in the + * network since it may have crashed + * ENOTCONN - The endpoint is not connected + * ENXIO - loff is invalid for the registered address of epd, or roff is invalid + * for the registered address space, of the peer of epd + */ +int scif_fence_signal(scif_epd_t epd, off_t loff, u64 lval, off_t roff, + u64 rval, int flags); + +/** + * scif_get_node_ids() - Return information about online nodes + * @nodes: array in which to return online node IDs + * @len: number of entries in the nodes array + * @self: address to place the node ID of the local node + * + * scif_get_node_ids() fills in the nodes array with up to len node IDs of the + * nodes in the SCIF network. If there is not enough space in nodes, as + * indicated by the len parameter, only len node IDs are returned in nodes. The + * return value of scif_get_node_ids() is the total number of nodes currently in + * the SCIF network. By checking the return value against the len parameter, + * the user may determine if enough space for nodes was allocated. + * + * The node ID of the local node is returned at self. + * + * Return: + * Upon successful completion, scif_get_node_ids() returns the actual number of + * online nodes in the SCIF network including 'self'; otherwise in user mode + * -1 is returned and errno is set to indicate the error; in kernel mode no + * errors are returned. + * + * Errors: + * EFAULT - Bad address + */ +int scif_get_node_ids(u16 *nodes, int len, u16 *self); + +#endif /* __SCIF_H__ */ diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild index 1a0006a76b00..4ad65eebbff8 100644 --- a/include/uapi/linux/Kbuild +++ b/include/uapi/linux/Kbuild @@ -352,6 +352,7 @@ header-y += rtc.h header-y += rtnetlink.h header-y += scc.h header-y += sched.h +header-y += scif_ioctl.h header-y += screen_info.h header-y += sctp.h header-y += sdla.h diff --git a/include/uapi/linux/scif_ioctl.h b/include/uapi/linux/scif_ioctl.h new file mode 100644 index 000000000000..4a94d917cf99 --- /dev/null +++ b/include/uapi/linux/scif_ioctl.h @@ -0,0 +1,130 @@ +/* + * Intel MIC Platform Software Stack (MPSS) + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2014 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * BSD LICENSE + * + * Copyright(c) 2014 Intel Corporation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Intel SCIF driver. + * + */ +/* + * ----------------------------------------- + * SCIF IOCTL interface information + * ----------------------------------------- + */ +#ifndef SCIF_IOCTL_H +#define SCIF_IOCTL_H + +#include + +/** + * struct scif_port_id - SCIF port information + * @node: node on which port resides + * @port: local port number + */ +struct scif_port_id { + __u16 node; + __u16 port; +}; + +/** + * struct scifioctl_connect - used for SCIF_CONNECT IOCTL + * @self: used to read back the assigned port_id + * @peer: destination node and port to connect to + */ +struct scifioctl_connect { + struct scif_port_id self; + struct scif_port_id peer; +}; + +/** + * struct scifioctl_accept - used for SCIF_ACCEPTREQ IOCTL + * @flags: flags + * @peer: global id of peer endpoint + * @endpt: new connected endpoint descriptor + */ +struct scifioctl_accept { + __s32 flags; + struct scif_port_id peer; + __u64 endpt; +}; + +/** + * struct scifioctl_msg - used for SCIF_SEND/SCIF_RECV IOCTL + * @msg: message buffer address + * @len: message length + * @flags: flags + * @out_len: number of bytes sent/received + */ +struct scifioctl_msg { + __u64 msg; + __s32 len; + __s32 flags; + __s32 out_len; +}; + +/** + * struct scifioctl_node_ids - used for SCIF_GET_NODEIDS IOCTL + * @nodes: pointer to an array of node_ids + * @self: ID of the current node + * @len: length of array + */ +struct scifioctl_node_ids { + __u64 nodes; + __u64 self; + __s32 len; +}; + +#define SCIF_BIND _IOWR('s', 1, __u64) +#define SCIF_LISTEN _IOW('s', 2, __s32) +#define SCIF_CONNECT _IOWR('s', 3, struct scifioctl_connect) +#define SCIF_ACCEPTREQ _IOWR('s', 4, struct scifioctl_accept) +#define SCIF_ACCEPTREG _IOWR('s', 5, __u64) +#define SCIF_SEND _IOWR('s', 6, struct scifioctl_msg) +#define SCIF_RECV _IOWR('s', 7, struct scifioctl_msg) +#define SCIF_GET_NODEIDS _IOWR('s', 14, struct scifioctl_node_ids) + +#endif /* SCIF_IOCTL_H */ -- cgit v1.2.3 From f5c48149b961012caf3bd0986fc500325647d5d7 Mon Sep 17 00:00:00 2001 From: Sudeep Dutt Date: Wed, 29 Apr 2015 05:32:40 -0700 Subject: misc: mic: add support for loading/unloading SCIF driver modprobe SCIF driver upon start and remove it upon unload Reviewed-by: Nikhil Rao Reviewed-by: Ashutosh Dixit Signed-off-by: Sudeep Dutt Signed-off-by: Greg Kroah-Hartman --- Documentation/mic/mpssd/mpss | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/mic/mpssd/mpss b/Documentation/mic/mpssd/mpss index cacbdb0aefb9..582aad4811ae 100755 --- a/Documentation/mic/mpssd/mpss +++ b/Documentation/mic/mpssd/mpss @@ -35,6 +35,7 @@ exec=/usr/sbin/mpssd sysfs="/sys/class/mic" +mic_modules="mic_host mic_x100_dma scif" start() { @@ -48,18 +49,15 @@ start() fi echo -e $"Starting MPSS Stack" - echo -e $"Loading MIC_X100_DMA & MIC_HOST Modules" + echo -e $"Loading MIC drivers:" $mic_modules - for f in "mic_host" "mic_x100_dma" - do - modprobe $f - RETVAL=$? - if [ $RETVAL -ne 0 ]; then - failure - echo - return $RETVAL - fi - done + modprobe -a $mic_modules + RETVAL=$? + if [ $RETVAL -ne 0 ]; then + failure + echo + return $RETVAL + fi # Start the daemon echo -n $"Starting MPSSD " @@ -170,8 +168,8 @@ unload() stop sleep 5 - echo -n $"Removing MIC_HOST & MIC_X100_DMA Modules: " - modprobe -r mic_host mic_x100_dma + echo -n $"Removing MIC drivers:" $mic_modules + modprobe -r $mic_modules RETVAL=$? [ $RETVAL -ne 0 ] && failure || success echo -- cgit v1.2.3 From 2539b258ec028351af954c169ea1b0ff72023a9f Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 8 May 2015 14:45:34 +0100 Subject: drivers/base: cacheinfo: fix annoying typo when DT nodes are absent s/hierarcy/hierarchy/ Maybe the typo will annoy people enough so that they add the missing nodes to their device-tree files, but I still think this is better off fixed. Signed-off-by: Will Deacon Acked-by: Sudeep Holla Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-devices-system-cpu | 2 +- drivers/base/cacheinfo.c | 4 ++-- include/linux/cacheinfo.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index 99983e67c13c..0908fb43566d 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -243,7 +243,7 @@ Description: Parameters for the CPU cache attributes coherency_line_size: the minimum amount of data in bytes that gets transferred from memory to cache - level: the cache hierarcy in the multi-level cache configuration + level: the cache hierarchy in the multi-level cache configuration number_of_sets: total number of sets in the cache, a set is a collection of cache lines with the same cache index diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 9c2ba1c97c42..c75bda89821b 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -191,12 +191,12 @@ static int detect_cache_attributes(unsigned int cpu) if (ret) goto free_ci; /* - * For systems using DT for cache hierarcy, of_node and shared_cpu_map + * For systems using DT for cache hierarchy, of_node and shared_cpu_map * will be set up here only if they are not populated already */ ret = cache_shared_cpu_map_setup(cpu); if (ret) { - pr_warn("Unable to detect cache hierarcy from DT for CPU %d\n", + pr_warn("Unable to detect cache hierarchy from DT for CPU %d\n", cpu); goto free_ci; } diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 3daf5ed392c9..2189935075b4 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -19,7 +19,7 @@ enum cache_type { /** * struct cacheinfo - represent a cache leaf node * @type: type of the cache - data, inst or unified - * @level: represents the hierarcy in the multi-level cache + * @level: represents the hierarchy in the multi-level cache * @coherency_line_size: size of each cache line usually representing * the minimum amount of data that gets transferred from memory * @number_of_sets: total number of sets, a set is a collection of cache -- cgit v1.2.3 From 3c99121ca5c5f79959c172a6297572a273f54fb6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 May 2015 19:46:24 +0200 Subject: serial: sh-sci: Add DMA support to the DT binding documentation Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index ae73bb0e9ad9..b91fcff4b7d4 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -44,6 +44,11 @@ Required properties: Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node. +Optional properties: + - dmas: Must contain a list of two references to DMA specifiers, one for + transmission, and one for reception. + - dma-names: Must contain a list of two DMA names, "tx" and "rx". + Example: aliases { serial0 = &scifa0; @@ -56,4 +61,6 @@ Example: interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; }; -- cgit v1.2.3 From 0dd1e247fd39aed20fd2baacc62ca44d82534798 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 21 May 2015 17:26:23 +0100 Subject: drivers: PL011: add support for the ARM SBSA generic UART The ARM Server Base System Architecture[1] document describes a generic UART which is a subset of the PL011 UART. It lacks DMA support, baud rate control and modem status line control, among other things. The idea is to move the UART initialization and setup into the firmware (which does this job today already) and let the kernel just use the UART for sending and receiving characters. We use the recent refactoring to build a new struct uart_ops variable which points to some new functions avoiding access to the missing registers. We reuse as much existing PL011 code as possible. In contrast to the PL011 the SBSA UART does not define any AMBA or PrimeCell relations, so we go with a pretty generic probe function which only uses platform device functions. A DT binding is provided with this patch, ACPI support is added in a separate one. Signed-off-by: Andre Przywara Tested-by: Mark Langsdorf Tested-by: Naresh Bhat Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/arm_sbsa_uart.txt | 10 ++ drivers/tty/serial/amba-pl011.c | 171 +++++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt b/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt new file mode 100644 index 000000000000..4163e7eb7763 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt @@ -0,0 +1,10 @@ +* ARM SBSA defined generic UART +This UART uses a subset of the PL011 registers and consequently lives +in the PL011 driver. It's baudrate and other communication parameters +cannot be adjusted at runtime, so it lacks a clock specifier here. + +Required properties: +- compatible: must be "arm,sbsa-uart" +- reg: exactly one register range +- interrupts: exactly one interrupt specifier +- current-speed: the (fixed) baud rate set by the firmware diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 6558400f766f..c0850f3cc439 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -101,6 +101,14 @@ static struct vendor_data vendor_arm = { .get_fifosize = get_fifosize_arm, }; +static struct vendor_data vendor_sbsa = { + .oversampling = false, + .dma_threshold = false, + .cts_event_workaround = false, + .always_enabled = true, + .fixed_options = true, +}; + static unsigned int get_fifosize_st(struct amba_device *dev) { return 64; @@ -1641,6 +1649,28 @@ static int pl011_startup(struct uart_port *port) return retval; } +static int sbsa_uart_startup(struct uart_port *port) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + int retval; + + retval = pl011_hwinit(port); + if (retval) + return retval; + + retval = pl011_allocate_irq(uap); + if (retval) + return retval; + + /* The SBSA UART does not support any modem status lines. */ + uap->old_status = 0; + + pl011_enable_interrupts(uap); + + return 0; +} + static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh) { @@ -1721,6 +1751,19 @@ static void pl011_shutdown(struct uart_port *port) uap->port.ops->flush_buffer(port); } +static void sbsa_uart_shutdown(struct uart_port *port) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + + pl011_disable_interrupts(uap); + + free_irq(uap->port.irq, uap); + + if (uap->port.ops->flush_buffer) + uap->port.ops->flush_buffer(port); +} + static void pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) { @@ -1872,6 +1915,27 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, spin_unlock_irqrestore(&port->lock, flags); } +static void +sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + unsigned long flags; + + tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); + + /* The SBSA UART only supports 8n1 without hardware flow control. */ + termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); + termios->c_cflag &= ~(CMSPAR | CRTSCTS); + termios->c_cflag |= CS8 | CLOCAL; + + spin_lock_irqsave(&port->lock, flags); + uart_update_timeout(port, CS8, uap->fixed_baud); + pl011_setup_status_masks(port, termios); + spin_unlock_irqrestore(&port->lock, flags); +} + static const char *pl011_type(struct uart_port *port) { struct uart_amba_port *uap = @@ -1947,6 +2011,37 @@ static struct uart_ops amba_pl011_pops = { #endif }; +static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static const struct uart_ops sbsa_uart_pops = { + .tx_empty = pl011_tx_empty, + .set_mctrl = sbsa_uart_set_mctrl, + .get_mctrl = sbsa_uart_get_mctrl, + .stop_tx = pl011_stop_tx, + .start_tx = pl011_start_tx, + .stop_rx = pl011_stop_rx, + .startup = sbsa_uart_startup, + .shutdown = sbsa_uart_shutdown, + .set_termios = sbsa_uart_set_termios, + .type = pl011_type, + .release_port = pl011_release_port, + .request_port = pl011_request_port, + .config_port = pl011_config_port, + .verify_port = pl011_verify_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_init = pl011_hwinit, + .poll_get_char = pl011_get_poll_char, + .poll_put_char = pl011_put_poll_char, +#endif +}; + static struct uart_amba_port *amba_ports[UART_NR]; #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE @@ -2327,6 +2422,79 @@ static int pl011_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); +static int sbsa_uart_probe(struct platform_device *pdev) +{ + struct uart_amba_port *uap; + struct resource *r; + int portnr, ret; + int baudrate; + + /* + * Check the mandatory baud rate parameter in the DT node early + * so that we can easily exit with the error. + */ + if (pdev->dev.of_node) { + struct device_node *np = pdev->dev.of_node; + + ret = of_property_read_u32(np, "current-speed", &baudrate); + if (ret) + return ret; + } else { + baudrate = 115200; + } + + portnr = pl011_find_free_port(); + if (portnr < 0) + return portnr; + + uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), + GFP_KERNEL); + if (!uap) + return -ENOMEM; + + uap->vendor = &vendor_sbsa; + uap->fifosize = 32; + uap->port.irq = platform_get_irq(pdev, 0); + uap->port.ops = &sbsa_uart_pops; + uap->fixed_baud = baudrate; + + snprintf(uap->type, sizeof(uap->type), "SBSA"); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + ret = pl011_setup_port(&pdev->dev, uap, r, portnr); + if (ret) + return ret; + + platform_set_drvdata(pdev, uap); + + return pl011_register_port(uap); +} + +static int sbsa_uart_remove(struct platform_device *pdev) +{ + struct uart_amba_port *uap = platform_get_drvdata(pdev); + + uart_remove_one_port(&amba_reg, &uap->port); + pl011_unregister_port(uap); + return 0; +} + +static const struct of_device_id sbsa_uart_of_match[] = { + { .compatible = "arm,sbsa-uart", }, + {}, +}; +MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); + +static struct platform_driver arm_sbsa_uart_platform_driver = { + .probe = sbsa_uart_probe, + .remove = sbsa_uart_remove, + .driver = { + .name = "sbsa-uart", + .of_match_table = of_match_ptr(sbsa_uart_of_match), + }, +}; + static struct amba_id pl011_ids[] = { { .id = 0x00041011, @@ -2357,11 +2525,14 @@ static int __init pl011_init(void) { printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); + if (platform_driver_register(&arm_sbsa_uart_platform_driver)) + pr_warn("could not register SBSA UART platform driver\n"); return amba_driver_register(&pl011_driver); } static void __exit pl011_exit(void) { + platform_driver_unregister(&arm_sbsa_uart_platform_driver); amba_driver_unregister(&pl011_driver); } -- cgit v1.2.3 From e3e694f8217ecff7f6f6f3e9d98a32b235161b49 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 12 May 2015 16:28:19 -0700 Subject: Documentation: devicetree: add Broadcom SATA binding Signed-off-by: Brian Norris Signed-off-by: Tejun Heo --- .../devicetree/bindings/ata/brcm,sata-brcmstb.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt new file mode 100644 index 000000000000..20ac9bbfa1fd --- /dev/null +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt @@ -0,0 +1,34 @@ +* Broadcom SATA3 AHCI Controller for STB + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, may contain "brcm,bcm7445-ahci" and/or + "brcm,sata3-ahci" +- reg : register mappings for AHCI and SATA_TOP_CTRL +- reg-names : "ahci" and "top-ctrl" +- interrupts : interrupt mapping for SATA IRQ + +Also see ahci-platform.txt. + +Example: + + sata@f045a000 { + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; + reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; + reg-names = "ahci", "top-ctrl"; + interrupts = <0 30 0>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + }; + }; -- cgit v1.2.3 From 638a9818f2bfd9ada6d4319116097e4ed70815cf Mon Sep 17 00:00:00 2001 From: Andreas Fenkart Date: Thu, 16 Apr 2015 10:03:14 +0200 Subject: mmc: pwrseq: dt: example with reset clock and active low pin Signed-off-by: Andreas Fenkart Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt index a462c50f19a8..ce0e76749671 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt @@ -21,5 +21,7 @@ Example: sdhci0_pwrseq { compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio1 12 0>; + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + clocks = <&clk_32768_ck>; + clock-names = "ext_clock"; } -- cgit v1.2.3 From d4855eeb9f7b71b1338ea0d66efbecceea840824 Mon Sep 17 00:00:00 2001 From: Ingi Kim Date: Tue, 12 May 2015 01:37:55 -0700 Subject: of: Add vendor prefix for Kinetic technologies This patch adds vendor prefix for Kinetic technologies Signed-off-by: Ingi Kim Acked-by: Rob Herring Acked-by: Seung-Woo Kim Reviewed-by: Varka Bhadram Signed-off-by: Bryan Wu --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..d48e9c8f1d84 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -107,6 +107,7 @@ isee ISEE 2007 S.L. isil Intersil karo Ka-Ro electronics GmbH keymile Keymile GmbH +kinetic Kinetic Technologies lacie LaCie lantiq Lantiq Semiconductor lenovo Lenovo Group Ltd. -- cgit v1.2.3 From 84b5def48fde3468539b9c81c6cdf2799e04913e Mon Sep 17 00:00:00 2001 From: Ingi Kim Date: Tue, 12 May 2015 01:37:56 -0700 Subject: leds: ktd2692: add device tree bindings for ktd2692 This patch adds the device tree bindings for ktd2692 flash LEDs. Add Optional properties of child node for Flash LED Signed-off-by: Ingi Kim Acked-by: Seung-Woo Kim Reviewed-by: Varka Bhadram Acked-by: Jacek Anaszewski Signed-off-by: Bryan Wu --- .../devicetree/bindings/leds/leds-ktd2692.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-ktd2692.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-ktd2692.txt b/Documentation/devicetree/bindings/leds/leds-ktd2692.txt new file mode 100644 index 000000000000..853737452580 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-ktd2692.txt @@ -0,0 +1,50 @@ +* Kinetic Technologies - KTD2692 Flash LED Driver + +KTD2692 is the ideal power solution for high-power flash LEDs. +It uses ExpressWire single-wire programming for maximum flexibility. + +The ExpressWire interface through CTRL pin can control LED on/off and +enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current, +Flash timeout, LVP(low voltage protection). + +Also, When the AUX pin is pulled high while CTRL pin is high, +LED current will be ramped up to the flash-mode current level. + +Required properties: +- compatible : Should be "kinetic,ktd2692". +- ctrl-gpios : Specifier of the GPIO connected to CTRL pin. +- aux-gpios : Specifier of the GPIO connected to AUX pin. + +Optional properties: +- vin-supply : "vin" LED supply (2.7V to 5.5V). + See Documentation/devicetree/bindings/regulator/regulator.txt + +A discrete LED element connected to the device must be represented by a child +node - See Documentation/devicetree/bindings/leds/common.txt + +Required properties for flash LED child nodes: + See Documentation/devicetree/bindings/leds/common.txt +- led-max-microamp : Minimum Threshold for Timer protection + is defined internally (Maximum 300mA). +- flash-max-microamp : Flash LED maximum current + Formula : I(mA) = 15000 / Rset. +- flash-max-timeout-us : Flash LED maximum timeout. + +Optional properties for flash LED child nodes: +- label : See Documentation/devicetree/bindings/leds/common.txt + +Example: + +ktd2692 { + compatible = "kinetic,ktd2692"; + ctrl-gpios = <&gpc0 1 0>; + aux-gpios = <&gpc0 2 0>; + vin-supply = <&vbat>; + + flash-led { + label = "ktd2692-flash"; + led-max-microamp = <300000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <1835000>; + }; +}; -- cgit v1.2.3 From 7ff6b23251955dc1cf108eb4619b4a2eeac75bca Mon Sep 17 00:00:00 2001 From: Toshi Kikuchi Date: Tue, 12 May 2015 18:15:14 -0700 Subject: Documentation: leds-lp5523: describe master fader attributes Add the usage of the new attributes for master faders. Signed-off-by: Toshi Kikuchi Acked-by: Milo Kim Acked-by: Jacek Anaszewski Signed-off-by: Bryan Wu --- Documentation/leds/leds-lp5523.txt | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'Documentation') diff --git a/Documentation/leds/leds-lp5523.txt b/Documentation/leds/leds-lp5523.txt index 5b3e91d4ac59..0dbbd279c9b9 100644 --- a/Documentation/leds/leds-lp5523.txt +++ b/Documentation/leds/leds-lp5523.txt @@ -49,6 +49,36 @@ There are two ways to run LED patterns. 2) Firmware interface - LP55xx common interface For the details, please refer to 'firmware' section in leds-lp55xx.txt +LP5523 has three master faders. If a channel is mapped to one of +the master faders, its output is dimmed based on the value of the master +fader. + +For example, + + echo "123000123" > master_fader_leds + +creates the following channel-fader mappings: + + channel 0,6 to master_fader1 + channel 1,7 to master_fader2 + channel 2,8 to master_fader3 + +Then, to have 25% of the original output on channel 0,6: + + echo 64 > master_fader1 + +To have 0% of the original output (i.e. no output) channel 1,7: + + echo 0 > master_fader2 + +To have 100% of the original output (i.e. no dimming) on channel 2,8: + + echo 255 > master_fader3 + +To clear all master fader controls: + + echo "000000000" > master_fader_leds + Selftest uses always the current from the platform data. Each channel contains led current settings. -- cgit v1.2.3 From c87cc34273dae2774d24d1ddd4edcadcce571a4e Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Thu, 21 May 2015 10:11:09 -0700 Subject: leds: add DT binding for BCM6358 LED controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds device tree binding documentation for the Broadcom BCM6358 LED controller. Signed-off-by: Álvaro Fernández Rojas Acked-by: Jacek Anaszewski Signed-off-by: Bryan Wu --- .../devicetree/bindings/leds/leds-bcm6358.txt | 145 +++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-bcm6358.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-bcm6358.txt b/Documentation/devicetree/bindings/leds/leds-bcm6358.txt new file mode 100644 index 000000000000..b22a55bcc65d --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-bcm6358.txt @@ -0,0 +1,145 @@ +LEDs connected to Broadcom BCM6358 controller + +This controller is present on BCM6358 and BCM6368. +In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), +which can either be controlled by software (exporting the 74x164 as spi-gpio. +See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +by hardware using this driver. + +Required properties: + - compatible : should be "brcm,bcm6358-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6358 LED controller address and size. + +Optional properties: + - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8. + Default : 1 + - brcm,clk-dat-low : Boolean, makes clock and data signals active low. + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6358-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 31 are valid). + +LED sub-node optional properties: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + - default-state : see + Documentation/devicetree/bindings/leds/leds-gpio.txt + - linux,default-trigger : see + Documentation/devicetree/bindings/leds/common.txt + +Examples: +Scenario 1 : BCM6358 + leds0: led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe00d0 0x8>; + + alarm_white { + reg = <0>; + active-low; + label = "white:alarm"; + }; + tv_white { + reg = <2>; + active-low; + label = "white:tv"; + }; + tel_white { + reg = <3>; + active-low; + label = "white:tel"; + }; + adsl_white { + reg = <4>; + active-low; + label = "white:adsl"; + }; + }; + +Scenario 2 : BCM6368 + leds0: led-controller@100000d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100000d0 0x8>; + brcm,pol-low; + brcm,clk-div = <4>; + + power_red { + reg = <0>; + active-low; + label = "red:power"; + }; + power_green { + reg = <1>; + active-low; + label = "green:power"; + default-state = "on"; + }; + power_blue { + reg = <2>; + label = "blue:power"; + }; + broadband_red { + reg = <3>; + active-low; + label = "red:broadband"; + }; + broadband_green { + reg = <4>; + label = "green:broadband"; + }; + broadband_blue { + reg = <5>; + active-low; + label = "blue:broadband"; + }; + wireless_red { + reg = <6>; + active-low; + label = "red:wireless"; + }; + wireless_green { + reg = <7>; + active-low; + label = "green:wireless"; + }; + wireless_blue { + reg = <8>; + label = "blue:wireless"; + }; + phone_red { + reg = <9>; + active-low; + label = "red:phone"; + }; + phone_green { + reg = <10>; + active-low; + label = "green:phone"; + }; + phone_blue { + reg = <11>; + label = "blue:phone"; + }; + upgrading_red { + reg = <12>; + active-low; + label = "red:upgrading"; + }; + upgrading_green { + reg = <13>; + active-low; + label = "green:upgrading"; + }; + upgrading_blue { + reg = <14>; + label = "blue:upgrading"; + }; + }; -- cgit v1.2.3 From 16eea6b487de81228ced60eca3ac2977d8400812 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Mon, 25 May 2015 23:29:18 +0200 Subject: Documentation: dmaengine: pxa-dma design Document the new design of the pxa dma driver. Signed-off-by: Robert Jarzmik Signed-off-by: Vinod Koul --- Documentation/dmaengine/pxa_dma.txt | 153 ++++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 Documentation/dmaengine/pxa_dma.txt (limited to 'Documentation') diff --git a/Documentation/dmaengine/pxa_dma.txt b/Documentation/dmaengine/pxa_dma.txt new file mode 100644 index 000000000000..413ef9cfaa4d --- /dev/null +++ b/Documentation/dmaengine/pxa_dma.txt @@ -0,0 +1,153 @@ +PXA/MMP - DMA Slave controller +============================== + +Constraints +----------- + a) Transfers hot queuing + A driver submitting a transfer and issuing it should be granted the transfer + is queued even on a running DMA channel. + This implies that the queuing doesn't wait for the previous transfer end, + and that the descriptor chaining is not only done in the irq/tasklet code + triggered by the end of the transfer. + A transfer which is submitted and issued on a phy doesn't wait for a phy to + stop and restart, but is submitted on a "running channel". The other + drivers, especially mmp_pdma waited for the phy to stop before relaunching + a new transfer. + + b) All transfers having asked for confirmation should be signaled + Any issued transfer with DMA_PREP_INTERRUPT should trigger a callback call. + This implies that even if an irq/tasklet is triggered by end of tx1, but + at the time of irq/dma tx2 is already finished, tx1->complete() and + tx2->complete() should be called. + + c) Channel running state + A driver should be able to query if a channel is running or not. For the + multimedia case, such as video capture, if a transfer is submitted and then + a check of the DMA channel reports a "stopped channel", the transfer should + not be issued until the next "start of frame interrupt", hence the need to + know if a channel is in running or stopped state. + + d) Bandwidth guarantee + The PXA architecture has 4 levels of DMAs priorities : high, normal, low. + The high prorities get twice as much bandwidth as the normal, which get twice + as much as the low priorities. + A driver should be able to request a priority, especially the real-time + ones such as pxa_camera with (big) throughputs. + +Design +------ + a) Virtual channels + Same concept as in sa11x0 driver, ie. a driver was assigned a "virtual + channel" linked to the requestor line, and the physical DMA channel is + assigned on the fly when the transfer is issued. + + b) Transfer anatomy for a scatter-gather transfer + +------------+-----+---------------+----------------+-----------------+ + | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker | + +------------+-----+---------------+----------------+-----------------+ + + This structure is pointed by dma->sg_cpu. + The descriptors are used as follows : + - desc-sg[i]: i-th descriptor, transferring the i-th sg + element to the video buffer scatter gather + - status updater + Transfers a single u32 to a well known dma coherent memory to leave + a trace that this transfer is done. The "well known" is unique per + physical channel, meaning that a read of this value will tell which + is the last finished transfer at that point in time. + - finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN + - linker: has ddadr= desc-sg[0] of next transfer, dcmd=0 + + c) Transfers hot-chaining + Suppose the running chain is : + Buffer 1 Buffer 2 + +---------+----+---+ +----+----+----+---+ + | d0 | .. | dN | l | | d0 | .. | dN | f | + +---------+----+-|-+ ^----+----+----+---+ + | | + +----+ + + After a call to dmaengine_submit(b3), the chain will look like : + Buffer 1 Buffer 2 Buffer 3 + +---------+----+---+ +----+----+----+---+ +----+----+----+---+ + | d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f | + +---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+ + | | | | + +----+ +----+ + new_link + + If while new_link was created the DMA channel stopped, it is _not_ + restarted. Hot-chaining doesn't break the assumption that + dma_async_issue_pending() is to be used to ensure the transfer is actually started. + + One exception to this rule : + - if Buffer1 and Buffer2 had all their addresses 8 bytes aligned + - and if Buffer3 has at least one address not 4 bytes aligned + - then hot-chaining cannot happen, as the channel must be stopped, the + "align bit" must be set, and the channel restarted As a consequence, + such a transfer tx_submit() will be queued on the submitted queue, and + this specific case if the DMA is already running in aligned mode. + + d) Transfers completion updater + Each time a transfer is completed on a channel, an interrupt might be + generated or not, up to the client's request. But in each case, the last + descriptor of a transfer, the "status updater", will write the latest + transfer being completed into the physical channel's completion mark. + + This will speed up residue calculation, for large transfers such as video + buffers which hold around 6k descriptors or more. This also allows without + any lock to find out what is the latest completed transfer in a running + DMA chain. + + e) Transfers completion, irq and tasklet + When a transfer flagged as "DMA_PREP_INTERRUPT" is finished, the dma irq + is raised. Upon this interrupt, a tasklet is scheduled for the physical + channel. + The tasklet is responsible for : + - reading the physical channel last updater mark + - calling all the transfer callbacks of finished transfers, based on + that mark, and each transfer flags. + If a transfer is completed while this handling is done, a dma irq will + be raised, and the tasklet will be scheduled once again, having a new + updater mark. + + f) Residue + Residue granularity will be descriptor based. The issued but not completed + transfers will be scanned for all of their descriptors against the + currently running descriptor. + + g) Most complicated case of driver's tx queues + The most tricky situation is when : + - there are not "acked" transfers (tx0) + - a driver submitted an aligned tx1, not chained + - a driver submitted an aligned tx2 => tx2 is cold chained to tx1 + - a driver issued tx1+tx2 => channel is running in aligned mode + - a driver submitted an aligned tx3 => tx3 is hot-chained + - a driver submitted an unaligned tx4 => tx4 is put in submitted queue, + not chained + - a driver issued tx4 => tx4 is put in issued queue, not chained + - a driver submitted an aligned tx5 => tx5 is put in submitted queue, not + chained + - a driver submitted an aligned tx6 => tx6 is put in submitted queue, + cold chained to tx5 + + This translates into (after tx4 is issued) : + - issued queue + +-----+ +-----+ +-----+ +-----+ + | tx1 | | tx2 | | tx3 | | tx4 | + +---|-+ ^---|-+ ^-----+ +-----+ + | | | | + +---+ +---+ + - submitted queue + +-----+ +-----+ + | tx5 | | tx6 | + +---|-+ ^-----+ + | | + +---+ + - completed queue : empty + - allocated queue : tx0 + + It should be noted that after tx3 is completed, the channel is stopped, and + restarted in "unaligned mode" to handle tx4. + +Author: Robert Jarzmik -- cgit v1.2.3 From 7cc99f1e9ae0e657c9a9126d042a342ea786ef08 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 8 Apr 2015 19:42:24 +0900 Subject: usb: renesas_usbhs: Revise the binding document about the dma-names Since the DT should describe the hardware (not the driver limitation), This patch revises the binding document about the dma-names to change simple numbering as "ch%d" instead of "tx" and "rx". Also this patch fixes the actual code of renesas_usbhs driver to handle the new dma-names. Signed-off-by: Yoshihiro Shimoda Acked-by: Mark Rutland Acked-by: Geert Uytterhoeven Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/renesas_usbhs.txt | 6 ++---- drivers/usb/renesas_usbhs/fifo.c | 24 ++++++++++++++-------- 2 files changed, 17 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index dc2a18f0b3a1..ddbe304beb21 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -15,10 +15,8 @@ Optional properties: - phys: phandle + phy specifier pair - phy-names: must be "usb" - dmas: Must contain a list of references to DMA specifiers. - - dma-names : Must contain a list of DMA names: - - tx0 ... tx - - rx0 ... rx - - This means DnFIFO in USBHS module. + - dma-names : named "ch%d", where %d is the channel number ranging from zero + to the number of channels (DnFIFOs) minus one. Example: usbhs: usb@e6590000 { diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c index 8597cf9cfceb..bc23b4a2c415 100644 --- a/drivers/usb/renesas_usbhs/fifo.c +++ b/drivers/usb/renesas_usbhs/fifo.c @@ -1227,15 +1227,21 @@ static void usbhsf_dma_init_dt(struct device *dev, struct usbhs_fifo *fifo, { char name[16]; - snprintf(name, sizeof(name), "tx%d", channel); - fifo->tx_chan = dma_request_slave_channel_reason(dev, name); - if (IS_ERR(fifo->tx_chan)) - fifo->tx_chan = NULL; - - snprintf(name, sizeof(name), "rx%d", channel); - fifo->rx_chan = dma_request_slave_channel_reason(dev, name); - if (IS_ERR(fifo->rx_chan)) - fifo->rx_chan = NULL; + /* + * To avoid complex handing for DnFIFOs, the driver uses each + * DnFIFO as TX or RX direction (not bi-direction). + * So, the driver uses odd channels for TX, even channels for RX. + */ + snprintf(name, sizeof(name), "ch%d", channel); + if (channel & 1) { + fifo->tx_chan = dma_request_slave_channel_reason(dev, name); + if (IS_ERR(fifo->tx_chan)) + fifo->tx_chan = NULL; + } else { + fifo->rx_chan = dma_request_slave_channel_reason(dev, name); + if (IS_ERR(fifo->rx_chan)) + fifo->rx_chan = NULL; + } } static void usbhsf_dma_init(struct usbhs_priv *priv, struct usbhs_fifo *fifo, -- cgit v1.2.3 From af6e613bb1b60fcbfe48c893b76c104c8952b599 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 18 May 2015 20:04:15 +0900 Subject: usb: renesas_usbhs: Add support for R-Car E2 This patch adds a compatible string to support for R-Car E2. Signed-off-by: Yoshihiro Shimoda Acked-by: Geert Uytterhoeven " in patch 2 Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 + drivers/usb/renesas_usbhs/common.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index ddbe304beb21..64a4ca6cf96f 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must contain one of the following: - "renesas,usbhs-r8a7790" - "renesas,usbhs-r8a7791" + - "renesas,usbhs-r8a7794" - reg: Base address and length of the register for the USBHS - interrupts: Interrupt specifier for the USBHS - clocks: A list of phandle + clock specifier pairs diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c index b56bb9d882fc..e8bf40808b39 100644 --- a/drivers/usb/renesas_usbhs/common.c +++ b/drivers/usb/renesas_usbhs/common.c @@ -472,6 +472,10 @@ static const struct of_device_id usbhs_of_match[] = { .compatible = "renesas,usbhs-r8a7791", .data = (void *)USBHS_TYPE_RCAR_GEN2, }, + { + .compatible = "renesas,usbhs-r8a7794", + .data = (void *)USBHS_TYPE_RCAR_GEN2, + }, { }, }; MODULE_DEVICE_TABLE(of, usbhs_of_match); -- cgit v1.2.3 From f5e4edb8c888958a970b2d42c47d2871a1a4fcdf Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Mon, 23 Mar 2015 09:52:48 +1100 Subject: power: twl4030_charger: find associated phy by more reliable means. twl4030_charger currently finds the associated phy using usb_get_phy() which will return the first USB2 phy. If your platform has multiple such phys (as mine does), this is not reliable (and reliably fails on the GTA04). Change to use devm_usb_get_phy_by_node(), having found the node by looking for an appropriately named sibling in device-tree. This makes usb-charging dependent on correct device-tree configuration. Acked-By: Sebastian Reichel Acked-by: Pavel Machek Signed-off-by: NeilBrown Signed-off-by: Felipe Balbi --- .../devicetree/bindings/power/twl-charger.txt | 10 ++++++++++ .../devicetree/bindings/usb/twlxxxx-usb.txt | 3 +++ drivers/power/twl4030_charger.c | 21 +++++++++------------ 3 files changed, 22 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/twl-charger.txt b/Documentation/devicetree/bindings/power/twl-charger.txt index d5c706216df5..3b4ea1b73b38 100644 --- a/Documentation/devicetree/bindings/power/twl-charger.txt +++ b/Documentation/devicetree/bindings/power/twl-charger.txt @@ -1,5 +1,15 @@ TWL BCI (Battery Charger Interface) +The battery charger needs to interact with the USB phy in order +to know when charging is permissible, and when there is a connection +or disconnection. + +The choice of phy cannot be configured at a hardware level, so there +is no value in explicit configuration in device-tree. Rather +if there is a sibling of the BCI node which is compatible with +"ti,twl4030-usb", then that is used to determine when and how +use USB power for charging. + Required properties: - compatible: - "ti,twl4030-bci" diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt index 0aee0ad3f035..17327a296110 100644 --- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt +++ b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt @@ -30,6 +30,9 @@ TWL4030 USB PHY AND COMPARATOR - usb_mode : The mode used by the phy to connect to the controller. "1" specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode. +If a sibling node is compatible "ti,twl4030-bci", then it will find +this device and query it for USB power status. + twl4030-usb { compatible = "ti,twl4030-usb"; interrupts = < 10 4 >; diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c index 02a522cb7753..022b8910e443 100644 --- a/drivers/power/twl4030_charger.c +++ b/drivers/power/twl4030_charger.c @@ -638,10 +638,15 @@ static int __init twl4030_bci_probe(struct platform_device *pdev) INIT_WORK(&bci->work, twl4030_bci_usb_work); - bci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); - if (!IS_ERR_OR_NULL(bci->transceiver)) { - bci->usb_nb.notifier_call = twl4030_bci_usb_ncb; - usb_register_notifier(bci->transceiver, &bci->usb_nb); + bci->usb_nb.notifier_call = twl4030_bci_usb_ncb; + if (bci->dev->of_node) { + struct device_node *phynode; + + phynode = of_find_compatible_node(bci->dev->of_node->parent, + NULL, "ti,twl4030-usb"); + if (phynode) + bci->transceiver = devm_usb_get_phy_by_node( + bci->dev, phynode, &bci->usb_nb); } /* Enable interrupts now. */ @@ -671,10 +676,6 @@ static int __init twl4030_bci_probe(struct platform_device *pdev) return 0; fail_unmask_interrupts: - if (!IS_ERR_OR_NULL(bci->transceiver)) { - usb_unregister_notifier(bci->transceiver, &bci->usb_nb); - usb_put_phy(bci->transceiver); - } free_irq(bci->irq_bci, bci); fail_bci_irq: free_irq(bci->irq_chg, bci); @@ -703,10 +704,6 @@ static int __exit twl4030_bci_remove(struct platform_device *pdev) twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, TWL4030_INTERRUPTS_BCIIMR2A); - if (!IS_ERR_OR_NULL(bci->transceiver)) { - usb_unregister_notifier(bci->transceiver, &bci->usb_nb); - usb_put_phy(bci->transceiver); - } free_irq(bci->irq_bci, bci); free_irq(bci->irq_chg, bci); power_supply_unregister(bci->usb); -- cgit v1.2.3 From b251d4de671ca0623d19b88a8af7f038499db631 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 25 May 2015 15:38:29 +0300 Subject: Documentation/networking/ieee802154.txt: fix various inaccuracies. * Update the linux-zigbee git:// repository URL. * Remove the MLME section as the current kernel does not provide a full 802.15.4 MLME implementation. * The hardmac example driver 'fakehard' was removed some time ago. * The IEEE 802.15.4 device drivers live in drivers/net/ieee802154/, not in drivers/ieee802154/. * The IEEE 802.15.4 MTU is 127 bytes, not 128 bytes. * Some of the 6LoWPAN code lives in net/6lowpan/. Signed-off-by: Lennert Buytenhek Reviewed-by: Stefan Schmidt Acked-by: Alexander Aring Signed-off-by: Marcel Holtmann --- Documentation/networking/ieee802154.txt | 32 +++++++++++--------------------- 1 file changed, 11 insertions(+), 21 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/ieee802154.txt b/Documentation/networking/ieee802154.txt index 22bbc7225f8e..1700756af057 100644 --- a/Documentation/networking/ieee802154.txt +++ b/Documentation/networking/ieee802154.txt @@ -30,8 +30,8 @@ int sd = socket(PF_IEEE802154, SOCK_DGRAM, 0); The address family, socket addresses etc. are defined in the include/net/af_ieee802154.h header or in the special header -in our userspace package (see either linux-zigbee sourceforge download page -or git tree at git://linux-zigbee.git.sourceforge.net/gitroot/linux-zigbee). +in the userspace package (see either http://wpan.cakelab.org/ or the +git tree at https://github.com/linux-wpan/wpan-tools). One can use SOCK_RAW for passing raw data towards device xmit function. YMMV. @@ -49,15 +49,6 @@ Like with WiFi, there are several types of devices implementing IEEE 802.15.4. Those types of devices require different approach to be hooked into Linux kernel. -MLME - MAC Level Management -============================ - -Most of IEEE 802.15.4 MLME interfaces are directly mapped on netlink commands. -See the include/net/nl802154.h header. Our userspace tools package -(see above) provides CLI configuration utility for radio interfaces and simple -coordinator for IEEE 802.15.4 networks as an example users of MLME protocol. - - HardMAC ======= @@ -75,8 +66,6 @@ net_device with a pointer to struct ieee802154_mlme_ops instance. The fields assoc_req, assoc_resp, disassoc_req, start_req, and scan_req are optional. All other fields are required. -We provide an example of simple HardMAC driver at drivers/ieee802154/fakehard.c - SoftMAC ======= @@ -89,7 +78,8 @@ stack interface for network sniffers (e.g. WireShark). This layer is going to be extended soon. -See header include/net/mac802154.h and several drivers in drivers/ieee802154/. +See header include/net/mac802154.h and several drivers in +drivers/net/ieee802154/. Device drivers API @@ -114,18 +104,17 @@ Moreover IEEE 802.15.4 device operations structure should be filled. Fake drivers ============ -In addition there are two drivers available which simulate real devices with -HardMAC (fakehard) and SoftMAC (fakelb - IEEE 802.15.4 loopback driver) -interfaces. This option provides possibility to test and debug stack without -usage of real hardware. +In addition there is a driver available which simulates a real device with +SoftMAC (fakelb - IEEE 802.15.4 loopback driver) interface. This option +provides possibility to test and debug stack without usage of real hardware. -See sources in drivers/ieee802154 folder for more details. +See sources in drivers/net/ieee802154 folder for more details. 6LoWPAN Linux implementation ============================ -The IEEE 802.15.4 standard specifies an MTU of 128 bytes, yielding about 80 +The IEEE 802.15.4 standard specifies an MTU of 127 bytes, yielding about 80 octets of actual MAC payload once security is turned on, on a wireless link with a link throughput of 250 kbps or less. The 6LoWPAN adaptation format [RFC4944] was specified to carry IPv6 datagrams over such constrained links, @@ -140,7 +129,8 @@ In Semptember 2011 the standard update was published - [RFC6282]. It deprecates HC1 and HC2 compression and defines IPHC encoding format which is used in this Linux implementation. -All the code related to 6lowpan you may find in files: net/ieee802154/6lowpan.* +All the code related to 6lowpan you may find in files: net/6lowpan/* +and net/ieee802154/6lowpan/* To setup 6lowpan interface you need (busybox release > 1.17.0): 1. Add IEEE802.15.4 interface and initialize PANid; -- cgit v1.2.3 From 7133fb51db0ace5c7563d0169ef1c91f81dc85b7 Mon Sep 17 00:00:00 2001 From: Thomas Niederprüm Date: Tue, 31 Mar 2015 20:27:09 +0200 Subject: of: Add Solomon Systech vendor prefix. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the solomon prefix for Solomon Systech Limited. Signed-off-by: Thomas Niederprüm Acked-by: Rob Herring Signed-off-by: Tomi Valkeinen --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..ce4a23e42ca2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -181,6 +181,7 @@ skyworks Skyworks Solutions, Inc. smsc Standard Microsystems Corporation snps Synopsys, Inc. solidrun SolidRun +solomon Solomon Systech Limited sony Sony Corporation spansion Spansion Inc. sprd Spreadtrum Communications Inc. -- cgit v1.2.3 From c89eacfc700675912b53df770953c30930c2554f Mon Sep 17 00:00:00 2001 From: Thomas Niederprüm Date: Tue, 31 Mar 2015 20:27:10 +0200 Subject: fbdev: ssd1307fb: Unify init code and obtain hw specific bits from DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 130X controllers are very similar from the configuration point of view. The configuration registers for the SSD1305/6/7 are bit identical (except the the VHCOM register and the the default values for clock setup register). This patch unifies the init code of the controller and adds hardware specific properties to DT that are needed to correctly initialize the device. The SSD130X can be wired to the OLED panel in various ways. Even for the same controller this wiring can differ from one display module to another and can not be probed by software. The added DT properties reflect these hardware decisions of the display module manufacturer. The 'com-sequential', 'com-lrremap' and 'com-invdir' values define different possibilities for the COM signals pin configuration and readout direction of the video memory. The 'segment-no-remap' allows the inversion of the memory-to-pin mapping ultimately inverting the order of the controllers output pins. The 'prechargepX' values need to be adapted according to the capacitance of the OLEDs pixel cells. So far these hardware specific bits are hard coded in the init code, making the driver usable only for one certain wiring of the controller. This patch makes the driver usable with all possible hardware setups, given a valid hw description in DT. If these values are not set in DT the default values, as they are set in the ssd1307 init code right now, are used. This implies that without the corresponding DT property "segment-no-remap" the segment remap of the ssd130X controller gets activated. Even though this is not the default behaviour according to the datasheet it maintains backward compatibility with older DTBs. Note that the SSD1306 does not seem to be using the configuration written to the registers at all. Therefore this patch does not try to maintain these values without changes in DT. For reference an example is added to the DT bindings documentation that reproduces the configuration that is set in the current init code. Signed-off-by: Thomas Niederprüm Tested-by: Olliver Schinagl Acked-by: Maxime Ripard Signed-off-by: Tomi Valkeinen --- .../devicetree/bindings/video/ssd1307fb.txt | 21 +++ drivers/video/fbdev/ssd1307fb.c | 177 ++++++++++++--------- 2 files changed, 125 insertions(+), 73 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt b/Documentation/devicetree/bindings/video/ssd1307fb.txt index 7a125427ff4b..635efa3b2b27 100644 --- a/Documentation/devicetree/bindings/video/ssd1307fb.txt +++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt @@ -15,6 +15,16 @@ Required properties: Optional properties: - reset-active-low: Is the reset gpio is active on physical low? + - solomon,segment-no-remap: Display needs normal (non-inverted) data column + to segment mapping + - solomon,com-seq: Display uses sequential COM pin configuration + - solomon,com-lrremap: Display uses left-right COM pin remap + - solomon,com-invdir: Display uses inverted COM pin scan direction + - solomon,com-offset: Number of the COM pin wired to the first display line + - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles. + - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles. + This needs to be the higher, the higher the capacitance + of the OLED's pixels is [0]: Documentation/devicetree/bindings/pwm/pwm.txt @@ -26,3 +36,14 @@ ssd1307: oled@3c { reset-gpios = <&gpio2 7>; reset-active-low; }; + +ssd1306: oled@3c { + compatible = "solomon,ssd1306fb-i2c"; + reg = <0x3c>; + pwms = <&pwm 4 3000>; + reset-gpios = <&gpio2 7>; + reset-active-low; + solomon,com-lrremap; + solomon,com-invdir; + solomon,com-offset = <32>; +}; diff --git a/drivers/video/fbdev/ssd1307fb.c b/drivers/video/fbdev/ssd1307fb.c index 8d34c5651187..8667c7769d8a 100644 --- a/drivers/video/fbdev/ssd1307fb.c +++ b/drivers/video/fbdev/ssd1307fb.c @@ -40,20 +40,34 @@ struct ssd1307fb_par; -struct ssd1307fb_ops { - int (*init)(struct ssd1307fb_par *); - int (*remove)(struct ssd1307fb_par *); +struct ssd1307fb_deviceinfo { + u32 default_vcomh; + u32 default_dclk_div; + u32 default_dclk_frq; + int need_pwm; + int need_chargepump; }; struct ssd1307fb_par { + u32 com_invdir; + u32 com_lrremap; + u32 com_offset; + u32 com_seq; + u32 contrast; + u32 dclk_div; + u32 dclk_frq; + struct ssd1307fb_deviceinfo *device_info; struct i2c_client *client; u32 height; struct fb_info *info; - struct ssd1307fb_ops *ops; u32 page_offset; + u32 prechargep1; + u32 prechargep2; struct pwm_device *pwm; u32 pwm_period; int reset; + u32 seg_remap; + u32 vcomh; u32 width; }; @@ -254,69 +268,46 @@ static struct fb_deferred_io ssd1307fb_defio = { .deferred_io = ssd1307fb_deferred_io, }; -static int ssd1307fb_ssd1307_init(struct ssd1307fb_par *par) +static int ssd1307fb_init(struct ssd1307fb_par *par) { int ret; + u32 precharge, dclk, com_invdir, compins; - par->pwm = pwm_get(&par->client->dev, NULL); - if (IS_ERR(par->pwm)) { - dev_err(&par->client->dev, "Could not get PWM from device tree!\n"); - return PTR_ERR(par->pwm); - } - - par->pwm_period = pwm_get_period(par->pwm); - /* Enable the PWM */ - pwm_config(par->pwm, par->pwm_period / 2, par->pwm_period); - pwm_enable(par->pwm); - - dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n", - par->pwm->pwm, par->pwm_period); - - /* Map column 127 of the OLED to segment 0 */ - ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON); - if (ret < 0) - return ret; - - /* Turn on the display */ - ret = ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_ON); - if (ret < 0) - return ret; - - return 0; -} + if (par->device_info->need_pwm) { + par->pwm = pwm_get(&par->client->dev, NULL); + if (IS_ERR(par->pwm)) { + dev_err(&par->client->dev, "Could not get PWM from device tree!\n"); + return PTR_ERR(par->pwm); + } -static int ssd1307fb_ssd1307_remove(struct ssd1307fb_par *par) -{ - pwm_disable(par->pwm); - pwm_put(par->pwm); - return 0; -} + par->pwm_period = pwm_get_period(par->pwm); + /* Enable the PWM */ + pwm_config(par->pwm, par->pwm_period / 2, par->pwm_period); + pwm_enable(par->pwm); -static struct ssd1307fb_ops ssd1307fb_ssd1307_ops = { - .init = ssd1307fb_ssd1307_init, - .remove = ssd1307fb_ssd1307_remove, -}; - -static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) -{ - int ret; + dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n", + par->pwm->pwm, par->pwm_period); + }; /* Set initial contrast */ ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST); if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0x7f); - if (ret < 0) - return ret; - - /* Set COM direction */ - ret = ssd1307fb_write_cmd(par->client, 0xc8); + ret = ssd1307fb_write_cmd(par->client, par->contrast); if (ret < 0) return ret; /* Set segment re-map */ - ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON); + if (par->seg_remap) { + ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON); + if (ret < 0) + return ret; + }; + + /* Set COM direction */ + com_invdir = 0xc0 | (par->com_invdir & 0x1) << 3; + ret = ssd1307fb_write_cmd(par->client, com_invdir); if (ret < 0) return ret; @@ -334,7 +325,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0x20); + ret = ssd1307fb_write_cmd(par->client, par->com_offset); if (ret < 0) return ret; @@ -343,7 +334,8 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0xf0); + dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4; + ret = ssd1307fb_write_cmd(par->client, dclk); if (ret < 0) return ret; @@ -352,7 +344,8 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0x22); + precharge = (par->prechargep1 & 0xf) | (par->prechargep2 & 0xf) << 4; + ret = ssd1307fb_write_cmd(par->client, precharge); if (ret < 0) return ret; @@ -361,7 +354,9 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0x22); + compins = 0x02 | (!par->com_seq & 0x1) << 4 + | (par->com_lrremap & 0x1) << 5; + ret = ssd1307fb_write_cmd(par->client, compins); if (ret < 0) return ret; @@ -370,7 +365,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0x49); + ret = ssd1307fb_write_cmd(par->client, par->vcomh); if (ret < 0) return ret; @@ -379,7 +374,8 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; - ret = ssd1307fb_write_cmd(par->client, 0x14); + ret = ssd1307fb_write_cmd(par->client, + (par->device_info->need_chargepump & 0x1 << 2) & 0x14); if (ret < 0) return ret; @@ -393,6 +389,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; + /* Set column range */ ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COL_RANGE); if (ret < 0) return ret; @@ -405,6 +402,7 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) if (ret < 0) return ret; + /* Set page range */ ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PAGE_RANGE); if (ret < 0) return ret; @@ -426,18 +424,28 @@ static int ssd1307fb_ssd1306_init(struct ssd1307fb_par *par) return 0; } -static struct ssd1307fb_ops ssd1307fb_ssd1306_ops = { - .init = ssd1307fb_ssd1306_init, +static struct ssd1307fb_deviceinfo ssd1307fb_ssd1306_deviceinfo = { + .default_vcomh = 0x20, + .default_dclk_div = 1, + .default_dclk_frq = 8, + .need_chargepump = 1, +}; + +static struct ssd1307fb_deviceinfo ssd1307fb_ssd1307_deviceinfo = { + .default_vcomh = 0x20, + .default_dclk_div = 2, + .default_dclk_frq = 12, + .need_pwm = 1, }; static const struct of_device_id ssd1307fb_of_match[] = { { .compatible = "solomon,ssd1306fb-i2c", - .data = (void *)&ssd1307fb_ssd1306_ops, + .data = (void *)&ssd1307fb_ssd1306_deviceinfo, }, { .compatible = "solomon,ssd1307fb-i2c", - .data = (void *)&ssd1307fb_ssd1307_ops, + .data = (void *)&ssd1307fb_ssd1307_deviceinfo, }, {}, }; @@ -468,8 +476,8 @@ static int ssd1307fb_probe(struct i2c_client *client, par->info = info; par->client = client; - par->ops = (struct ssd1307fb_ops *)of_match_device(ssd1307fb_of_match, - &client->dev)->data; + par->device_info = (struct ssd1307fb_deviceinfo *)of_match_device( + ssd1307fb_of_match, &client->dev)->data; par->reset = of_get_named_gpio(client->dev.of_node, "reset-gpios", 0); @@ -487,6 +495,27 @@ static int ssd1307fb_probe(struct i2c_client *client, if (of_property_read_u32(node, "solomon,page-offset", &par->page_offset)) par->page_offset = 1; + if (of_property_read_u32(node, "solomon,com-offset", &par->com_offset)) + par->com_offset = 0; + + if (of_property_read_u32(node, "solomon,prechargep1", &par->prechargep1)) + par->prechargep1 = 2; + + if (of_property_read_u32(node, "solomon,prechargep2", &par->prechargep2)) + par->prechargep2 = 2; + + par->seg_remap = !of_property_read_bool(node, "solomon,segment-no-remap"); + par->com_seq = of_property_read_bool(node, "solomon,com-seq"); + par->com_lrremap = of_property_read_bool(node, "solomon,com-lrremap"); + par->com_invdir = of_property_read_bool(node, "solomon,com-invdir"); + + par->contrast = 127; + par->vcomh = par->device_info->default_vcomh; + + /* Setup display timing */ + par->dclk_div = par->device_info->default_dclk_div; + par->dclk_frq = par->device_info->default_dclk_frq; + vmem_size = par->width * par->height / 8; vmem = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, @@ -539,11 +568,9 @@ static int ssd1307fb_probe(struct i2c_client *client, gpio_set_value(par->reset, 1); udelay(4); - if (par->ops->init) { - ret = par->ops->init(par); - if (ret) - goto reset_oled_error; - } + ret = ssd1307fb_init(par); + if (ret) + goto reset_oled_error; ret = register_framebuffer(info); if (ret) { @@ -556,8 +583,10 @@ static int ssd1307fb_probe(struct i2c_client *client, return 0; panel_init_error: - if (par->ops->remove) - par->ops->remove(par); + if (par->device_info->need_pwm) { + pwm_disable(par->pwm); + pwm_put(par->pwm); + }; reset_oled_error: fb_deferred_io_cleanup(info); fb_alloc_error: @@ -571,8 +600,10 @@ static int ssd1307fb_remove(struct i2c_client *client) struct ssd1307fb_par *par = info->par; unregister_framebuffer(info); - if (par->ops->remove) - par->ops->remove(par); + if (par->device_info->need_pwm) { + pwm_disable(par->pwm); + pwm_put(par->pwm); + }; fb_deferred_io_cleanup(info); __free_pages(__va(info->fix.smem_start), get_order(info->fix.smem_len)); framebuffer_release(info); -- cgit v1.2.3 From 5f2d36b3cf629ae1d70ee8476599ff53f0d1d1f1 Mon Sep 17 00:00:00 2001 From: Thomas Niederprüm Date: Tue, 31 Mar 2015 20:27:12 +0200 Subject: fbdev: ssd1307fb: Add support for SSD1305 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds support for the SSD1305 OLED controller. Signed-off-by: Thomas Niederprüm Acked-by: Maxime Ripard Signed-off-by: Tomi Valkeinen --- Documentation/devicetree/bindings/video/ssd1307fb.txt | 2 +- drivers/video/fbdev/ssd1307fb.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt b/Documentation/devicetree/bindings/video/ssd1307fb.txt index 635efa3b2b27..d1be78db63f5 100644 --- a/Documentation/devicetree/bindings/video/ssd1307fb.txt +++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt @@ -2,7 +2,7 @@ Required properties: - compatible: Should be "solomon,fb-". The only supported bus for - now is i2c, and the supported chips are ssd1306 and ssd1307. + now is i2c, and the supported chips are ssd1305, ssd1306 and ssd1307. - reg: Should contain address of the controller on the I2C bus. Most likely 0x3c or 0x3d - pwm: Should contain the pwm to use according to the OF device tree PWM diff --git a/drivers/video/fbdev/ssd1307fb.c b/drivers/video/fbdev/ssd1307fb.c index 8667c7769d8a..f685d244fa2a 100644 --- a/drivers/video/fbdev/ssd1307fb.c +++ b/drivers/video/fbdev/ssd1307fb.c @@ -424,6 +424,12 @@ static int ssd1307fb_init(struct ssd1307fb_par *par) return 0; } +static struct ssd1307fb_deviceinfo ssd1307fb_ssd1305_deviceinfo = { + .default_vcomh = 0x34, + .default_dclk_div = 1, + .default_dclk_frq = 7, +}; + static struct ssd1307fb_deviceinfo ssd1307fb_ssd1306_deviceinfo = { .default_vcomh = 0x20, .default_dclk_div = 1, @@ -439,6 +445,10 @@ static struct ssd1307fb_deviceinfo ssd1307fb_ssd1307_deviceinfo = { }; static const struct of_device_id ssd1307fb_of_match[] = { + { + .compatible = "solomon,ssd1305fb-i2c", + .data = (void *)&ssd1307fb_ssd1305_deviceinfo, + }, { .compatible = "solomon,ssd1306fb-i2c", .data = (void *)&ssd1307fb_ssd1306_deviceinfo, @@ -612,6 +622,7 @@ static int ssd1307fb_remove(struct i2c_client *client) } static const struct i2c_device_id ssd1307fb_i2c_id[] = { + { "ssd1305fb", 0 }, { "ssd1306fb", 0 }, { "ssd1307fb", 0 }, { } -- cgit v1.2.3 From 54fd15780526c47fa29a85b066cf69996be59a59 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Tue, 26 May 2015 10:28:18 +0200 Subject: x86/Documentation: Move kernel-stacks doc one level up ... to Documentation/x86/ as it is going to collect more and not only 64-bit specific info. Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Michal Marek Cc: Peter Zijlstra Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: live-patching@vger.kernel.org Link: http://lkml.kernel.org/r/1432628901-18044-16-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/kernel-stacks | 101 +++++++++++++++++++++++++++++++++ Documentation/x86/x86_64/kernel-stacks | 101 --------------------------------- 2 files changed, 101 insertions(+), 101 deletions(-) create mode 100644 Documentation/x86/kernel-stacks delete mode 100644 Documentation/x86/x86_64/kernel-stacks (limited to 'Documentation') diff --git a/Documentation/x86/kernel-stacks b/Documentation/x86/kernel-stacks new file mode 100644 index 000000000000..e3c8a49d1a2f --- /dev/null +++ b/Documentation/x86/kernel-stacks @@ -0,0 +1,101 @@ +Most of the text from Keith Owens, hacked by AK + +x86_64 page size (PAGE_SIZE) is 4K. + +Like all other architectures, x86_64 has a kernel stack for every +active thread. These thread stacks are THREAD_SIZE (2*PAGE_SIZE) big. +These stacks contain useful data as long as a thread is alive or a +zombie. While the thread is in user space the kernel stack is empty +except for the thread_info structure at the bottom. + +In addition to the per thread stacks, there are specialized stacks +associated with each CPU. These stacks are only used while the kernel +is in control on that CPU; when a CPU returns to user space the +specialized stacks contain no useful data. The main CPU stacks are: + +* Interrupt stack. IRQSTACKSIZE + + Used for external hardware interrupts. If this is the first external + hardware interrupt (i.e. not a nested hardware interrupt) then the + kernel switches from the current task to the interrupt stack. Like + the split thread and interrupt stacks on i386, this gives more room + for kernel interrupt processing without having to increase the size + of every per thread stack. + + The interrupt stack is also used when processing a softirq. + +Switching to the kernel interrupt stack is done by software based on a +per CPU interrupt nest counter. This is needed because x86-64 "IST" +hardware stacks cannot nest without races. + +x86_64 also has a feature which is not available on i386, the ability +to automatically switch to a new stack for designated events such as +double fault or NMI, which makes it easier to handle these unusual +events on x86_64. This feature is called the Interrupt Stack Table +(IST). There can be up to 7 IST entries per CPU. The IST code is an +index into the Task State Segment (TSS). The IST entries in the TSS +point to dedicated stacks; each stack can be a different size. + +An IST is selected by a non-zero value in the IST field of an +interrupt-gate descriptor. When an interrupt occurs and the hardware +loads such a descriptor, the hardware automatically sets the new stack +pointer based on the IST value, then invokes the interrupt handler. If +the interrupt came from user mode, then the interrupt handler prologue +will switch back to the per-thread stack. If software wants to allow +nested IST interrupts then the handler must adjust the IST values on +entry to and exit from the interrupt handler. (This is occasionally +done, e.g. for debug exceptions.) + +Events with different IST codes (i.e. with different stacks) can be +nested. For example, a debug interrupt can safely be interrupted by an +NMI. arch/x86_64/kernel/entry.S::paranoidentry adjusts the stack +pointers on entry to and exit from all IST events, in theory allowing +IST events with the same code to be nested. However in most cases, the +stack size allocated to an IST assumes no nesting for the same code. +If that assumption is ever broken then the stacks will become corrupt. + +The currently assigned IST stacks are :- + +* STACKFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE). + + Used for interrupt 12 - Stack Fault Exception (#SS). + + This allows the CPU to recover from invalid stack segments. Rarely + happens. + +* DOUBLEFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE). + + Used for interrupt 8 - Double Fault Exception (#DF). + + Invoked when handling one exception causes another exception. Happens + when the kernel is very confused (e.g. kernel stack pointer corrupt). + Using a separate stack allows the kernel to recover from it well enough + in many cases to still output an oops. + +* NMI_STACK. EXCEPTION_STKSZ (PAGE_SIZE). + + Used for non-maskable interrupts (NMI). + + NMI can be delivered at any time, including when the kernel is in the + middle of switching stacks. Using IST for NMI events avoids making + assumptions about the previous state of the kernel stack. + +* DEBUG_STACK. DEBUG_STKSZ + + Used for hardware debug interrupts (interrupt 1) and for software + debug interrupts (INT3). + + When debugging a kernel, debug interrupts (both hardware and + software) can occur at any time. Using IST for these interrupts + avoids making assumptions about the previous state of the kernel + stack. + +* MCE_STACK. EXCEPTION_STKSZ (PAGE_SIZE). + + Used for interrupt 18 - Machine Check Exception (#MC). + + MCE can be delivered at any time, including when the kernel is in the + middle of switching stacks. Using IST for MCE events avoids making + assumptions about the previous state of the kernel stack. + +For more details see the Intel IA32 or AMD AMD64 architecture manuals. diff --git a/Documentation/x86/x86_64/kernel-stacks b/Documentation/x86/x86_64/kernel-stacks deleted file mode 100644 index e3c8a49d1a2f..000000000000 --- a/Documentation/x86/x86_64/kernel-stacks +++ /dev/null @@ -1,101 +0,0 @@ -Most of the text from Keith Owens, hacked by AK - -x86_64 page size (PAGE_SIZE) is 4K. - -Like all other architectures, x86_64 has a kernel stack for every -active thread. These thread stacks are THREAD_SIZE (2*PAGE_SIZE) big. -These stacks contain useful data as long as a thread is alive or a -zombie. While the thread is in user space the kernel stack is empty -except for the thread_info structure at the bottom. - -In addition to the per thread stacks, there are specialized stacks -associated with each CPU. These stacks are only used while the kernel -is in control on that CPU; when a CPU returns to user space the -specialized stacks contain no useful data. The main CPU stacks are: - -* Interrupt stack. IRQSTACKSIZE - - Used for external hardware interrupts. If this is the first external - hardware interrupt (i.e. not a nested hardware interrupt) then the - kernel switches from the current task to the interrupt stack. Like - the split thread and interrupt stacks on i386, this gives more room - for kernel interrupt processing without having to increase the size - of every per thread stack. - - The interrupt stack is also used when processing a softirq. - -Switching to the kernel interrupt stack is done by software based on a -per CPU interrupt nest counter. This is needed because x86-64 "IST" -hardware stacks cannot nest without races. - -x86_64 also has a feature which is not available on i386, the ability -to automatically switch to a new stack for designated events such as -double fault or NMI, which makes it easier to handle these unusual -events on x86_64. This feature is called the Interrupt Stack Table -(IST). There can be up to 7 IST entries per CPU. The IST code is an -index into the Task State Segment (TSS). The IST entries in the TSS -point to dedicated stacks; each stack can be a different size. - -An IST is selected by a non-zero value in the IST field of an -interrupt-gate descriptor. When an interrupt occurs and the hardware -loads such a descriptor, the hardware automatically sets the new stack -pointer based on the IST value, then invokes the interrupt handler. If -the interrupt came from user mode, then the interrupt handler prologue -will switch back to the per-thread stack. If software wants to allow -nested IST interrupts then the handler must adjust the IST values on -entry to and exit from the interrupt handler. (This is occasionally -done, e.g. for debug exceptions.) - -Events with different IST codes (i.e. with different stacks) can be -nested. For example, a debug interrupt can safely be interrupted by an -NMI. arch/x86_64/kernel/entry.S::paranoidentry adjusts the stack -pointers on entry to and exit from all IST events, in theory allowing -IST events with the same code to be nested. However in most cases, the -stack size allocated to an IST assumes no nesting for the same code. -If that assumption is ever broken then the stacks will become corrupt. - -The currently assigned IST stacks are :- - -* STACKFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE). - - Used for interrupt 12 - Stack Fault Exception (#SS). - - This allows the CPU to recover from invalid stack segments. Rarely - happens. - -* DOUBLEFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE). - - Used for interrupt 8 - Double Fault Exception (#DF). - - Invoked when handling one exception causes another exception. Happens - when the kernel is very confused (e.g. kernel stack pointer corrupt). - Using a separate stack allows the kernel to recover from it well enough - in many cases to still output an oops. - -* NMI_STACK. EXCEPTION_STKSZ (PAGE_SIZE). - - Used for non-maskable interrupts (NMI). - - NMI can be delivered at any time, including when the kernel is in the - middle of switching stacks. Using IST for NMI events avoids making - assumptions about the previous state of the kernel stack. - -* DEBUG_STACK. DEBUG_STKSZ - - Used for hardware debug interrupts (interrupt 1) and for software - debug interrupts (INT3). - - When debugging a kernel, debug interrupts (both hardware and - software) can occur at any time. Using IST for these interrupts - avoids making assumptions about the previous state of the kernel - stack. - -* MCE_STACK. EXCEPTION_STKSZ (PAGE_SIZE). - - Used for interrupt 18 - Machine Check Exception (#MC). - - MCE can be delivered at any time, including when the kernel is in the - middle of switching stacks. Using IST for MCE events avoids making - assumptions about the previous state of the kernel stack. - -For more details see the Intel IA32 or AMD AMD64 architecture manuals. -- cgit v1.2.3 From d724a9a52b0026ac6a05440c079c9a618acfd8cf Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Tue, 26 May 2015 10:28:19 +0200 Subject: x86/Documentation: Remove STACKFAULT_STACK bulletpoint Update the documentation after 6f442be2fb22 ("x86_64, traps: Stop using IST for #SS"). Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Michal Marek Cc: Peter Zijlstra Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: live-patching@vger.kernel.org Link: http://lkml.kernel.org/r/1432628901-18044-17-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/kernel-stacks | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/x86/kernel-stacks b/Documentation/x86/kernel-stacks index e3c8a49d1a2f..c3c935b9d56e 100644 --- a/Documentation/x86/kernel-stacks +++ b/Documentation/x86/kernel-stacks @@ -1,3 +1,6 @@ +Kernel stacks on x86-64 bit +--------------------------- + Most of the text from Keith Owens, hacked by AK x86_64 page size (PAGE_SIZE) is 4K. @@ -56,13 +59,6 @@ If that assumption is ever broken then the stacks will become corrupt. The currently assigned IST stacks are :- -* STACKFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE). - - Used for interrupt 12 - Stack Fault Exception (#SS). - - This allows the CPU to recover from invalid stack segments. Rarely - happens. - * DOUBLEFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE). Used for interrupt 8 - Double Fault Exception (#DF). -- cgit v1.2.3 From 113b5e3720e79ad938374163c1b8e295521dc9cf Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Tue, 26 May 2015 10:28:20 +0200 Subject: x86/Documentation: Adapt Ingo's explanation on printing backtraces Hold it down for future reference, as the question about the question mark in stack traces keeps popping up. Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Michal Marek Cc: Peter Zijlstra Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: live-patching@vger.kernel.org Link: http://lkml.kernel.org/r/1432628901-18044-18-git-send-email-bp@alien8.de Link: http://lkml.kernel.org/r/20150521101614.GA10889@gmail.com Signed-off-by: Ingo Molnar --- Documentation/x86/kernel-stacks | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'Documentation') diff --git a/Documentation/x86/kernel-stacks b/Documentation/x86/kernel-stacks index c3c935b9d56e..0f3a6c201943 100644 --- a/Documentation/x86/kernel-stacks +++ b/Documentation/x86/kernel-stacks @@ -95,3 +95,47 @@ The currently assigned IST stacks are :- assumptions about the previous state of the kernel stack. For more details see the Intel IA32 or AMD AMD64 architecture manuals. + + +Printing backtraces on x86 +-------------------------- + +The question about the '?' preceding function names in an x86 stacktrace +keeps popping up, here's an indepth explanation. It helps if the reader +stares at print_context_stack() and the whole machinery in and around +arch/x86/kernel/dumpstack.c. + +Adapted from Ingo's mail, Message-ID: <20150521101614.GA10889@gmail.com>: + +We always scan the full kernel stack for return addresses stored on +the kernel stack(s) [*], from stack top to stack bottom, and print out +anything that 'looks like' a kernel text address. + +If it fits into the frame pointer chain, we print it without a question +mark, knowing that it's part of the real backtrace. + +If the address does not fit into our expected frame pointer chain we +still print it, but we print a '?'. It can mean two things: + + - either the address is not part of the call chain: it's just stale + values on the kernel stack, from earlier function calls. This is + the common case. + + - or it is part of the call chain, but the frame pointer was not set + up properly within the function, so we don't recognize it. + +This way we will always print out the real call chain (plus a few more +entries), regardless of whether the frame pointer was set up correctly +or not - but in most cases we'll get the call chain right as well. The +entries printed are strictly in stack order, so you can deduce more +information from that as well. + +The most important property of this method is that we _never_ lose +information: we always strive to print _all_ addresses on the stack(s) +that look like kernel text addresses, so if debug information is wrong, +we still print out the real call chain as well - just with more question +marks than ideal. + +[*] For things like IRQ and IST stacks, we also scan those stacks, in + the right order, and try to cross from one stack into another + reconstructing the call chain. This works most of the time. -- cgit v1.2.3 From 2f9e897353fcb99effd6eff22f7b464f8e2a659a Mon Sep 17 00:00:00 2001 From: "Luis R. Rodriguez" Date: Tue, 26 May 2015 10:28:12 +0200 Subject: x86/mm/mtrr, pat: Document Write Combining MTRR type effects on PAT / non-PAT pages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As part of the effort to phase out MTRR use document write-combining MTRR effects on pages with different non-PAT page attributes flags and different PAT entry values. Extend arch_phys_wc_add() documentation to clarify power of two sizes / boundary requirements as we phase out mtrr_add() use. Lastly hint towards ioremap_uc() for corner cases on device drivers working with devices with mixed regions where MTRR size requirements would otherwise not enable write-combining effective memory types. Signed-off-by: Luis R. Rodriguez Signed-off-by: Borislav Petkov Cc: Andy Lutomirski Cc: Antonino Daplas Cc: Borislav Petkov Cc: Brian Gerst Cc: Daniel Vetter Cc: Dave Airlie Cc: Dave Hansen Cc: Davidlohr Bueso Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Jean-Christophe Plagniol-Villard Cc: Jonathan Corbet Cc: Juergen Gross Cc: Linus Torvalds Cc: Mel Gorman Cc: Peter Zijlstra Cc: Suresh Siddha Cc: Thomas Gleixner Cc: Tomi Valkeinen Cc: Ville Syrjälä Cc: Vlastimil Babka Cc: linux-fbdev@vger.kernel.org Link: http://lkml.kernel.org/r/1430343851-967-3-git-send-email-mcgrof@do-not-panic.com Link: http://lkml.kernel.org/r/1432628901-18044-10-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/mtrr.txt | 18 +++++++++++++++--- Documentation/x86/pat.txt | 35 ++++++++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mtrr/main.c | 3 +++ 3 files changed, 52 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/x86/mtrr.txt b/Documentation/x86/mtrr.txt index cc071dc333c2..860bc3adc223 100644 --- a/Documentation/x86/mtrr.txt +++ b/Documentation/x86/mtrr.txt @@ -1,7 +1,19 @@ MTRR (Memory Type Range Register) control -3 Jun 1999 -Richard Gooch - + +Richard Gooch - 3 Jun 1999 +Luis R. Rodriguez - April 9, 2015 + +=============================================================================== +Phasing out MTRR use + +MTRR use is replaced on modern x86 hardware with PAT. Over time the only type +of effective MTRR that is expected to be supported will be for write-combining. +As MTRR use is phased out device drivers should use arch_phys_wc_add() to make +MTRR effective on non-PAT systems while a no-op on PAT enabled systems. + +For details refer to Documentation/x86/pat.txt. + +=============================================================================== On Intel P6 family processors (Pentium Pro, Pentium II and later) the Memory Type Range Registers (MTRRs) may be used to control diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt index cf08c9fff3cd..521bd8adc3b8 100644 --- a/Documentation/x86/pat.txt +++ b/Documentation/x86/pat.txt @@ -34,6 +34,8 @@ ioremap | -- | UC- | UC- | | | | | ioremap_cache | -- | WB | WB | | | | | +ioremap_uc | -- | UC | UC | + | | | | ioremap_nocache | -- | UC- | UC- | | | | | ioremap_wc | -- | -- | WC | @@ -102,7 +104,38 @@ wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc() as step 0 above and also track the usage of those pages and use set_memory_wb() before the page is freed to free pool. - +MTRR effects on PAT / non-PAT systems +------------------------------------- + +The following table provides the effects of using write-combining MTRRs when +using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally +mtrr_add() usage will be phased out in favor of arch_phys_wc_add() which will +be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add() +is made, should already have been ioremapped with WC attributes or PAT entries, +this can be done by using ioremap_wc() / set_memory_wc(). Devices which +combine areas of IO memory desired to remain uncacheable with areas where +write-combining is desirable should consider use of ioremap_uc() followed by +set_memory_wc() to white-list effective write-combined areas. Such use is +nevertheless discouraged as the effective memory type is considered +implementation defined, yet this strategy can be used as last resort on devices +with size-constrained regions where otherwise MTRR write-combining would +otherwise not be effective. + +---------------------------------------------------------------------- +MTRR Non-PAT PAT Linux ioremap value Effective memory type +---------------------------------------------------------------------- + Non-PAT | PAT + PAT + |PCD + ||PWT + ||| +WC 000 WB _PAGE_CACHE_MODE_WB WC | WC +WC 001 WC _PAGE_CACHE_MODE_WC WC* | WC +WC 010 UC- _PAGE_CACHE_MODE_UC_MINUS WC* | UC +WC 011 UC _PAGE_CACHE_MODE_UC UC | UC +---------------------------------------------------------------------- + +(*) denotes implementation defined and is discouraged Notes: diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c index ea5f363a1948..04aceb7e6443 100644 --- a/arch/x86/kernel/cpu/mtrr/main.c +++ b/arch/x86/kernel/cpu/mtrr/main.c @@ -538,6 +538,9 @@ EXPORT_SYMBOL(mtrr_del); * attempts to add a WC MTRR covering size bytes starting at base and * logs an error if this fails. * + * The called should provide a power of two size on an equivalent + * power of two boundary. + * * Drivers must store the return value to pass to mtrr_del_wc_if_needed, * but drivers should not try to interpret that return value. */ -- cgit v1.2.3 From 06931e62246844c73fba24d7aeb4a5dc897a2739 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 26 May 2015 15:11:28 +0200 Subject: sched/topology: Rename topology_thread_cpumask() to topology_sibling_cpumask() Rename topology_thread_cpumask() to topology_sibling_cpumask() for more consistency with scheduler code. Signed-off-by: Bartosz Golaszewski Reviewed-by: Thomas Gleixner Acked-by: Russell King Acked-by: Catalin Marinas Cc: Benoit Cousson Cc: Fenghua Yu Cc: Guenter Roeck Cc: Jean Delvare Cc: Jonathan Corbet Cc: Linus Torvalds Cc: Oleg Drokin Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Russell King Cc: Viresh Kumar Link: http://lkml.kernel.org/r/1432645896-12588-2-git-send-email-bgolaszewski@baylibre.com Signed-off-by: Ingo Molnar --- Documentation/cputopology.txt | 2 +- arch/arm/include/asm/topology.h | 2 +- arch/arm64/include/asm/topology.h | 2 +- arch/ia64/include/asm/topology.h | 2 +- arch/mips/include/asm/topology.h | 2 +- arch/powerpc/include/asm/topology.h | 2 +- arch/powerpc/mm/tlb_nohash.c | 2 +- arch/s390/include/asm/topology.h | 3 ++- arch/sparc/include/asm/topology_64.h | 2 +- arch/tile/include/asm/topology.h | 2 +- arch/x86/include/asm/topology.h | 2 +- arch/x86/kernel/cpu/perf_event_intel.c | 6 +++--- block/blk-mq-cpumap.c | 2 +- drivers/acpi/acpi_pad.c | 2 +- drivers/base/topology.c | 2 +- drivers/net/ethernet/sfc/efx.c | 2 +- drivers/staging/lustre/lustre/libcfs/linux/linux-cpu.c | 2 +- drivers/staging/lustre/lustre/ptlrpc/service.c | 4 ++-- include/linux/topology.h | 6 +++--- lib/cpu_rmap.c | 2 +- 20 files changed, 26 insertions(+), 25 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cputopology.txt b/Documentation/cputopology.txt index 0aad6deb2d96..428a961ff063 100644 --- a/Documentation/cputopology.txt +++ b/Documentation/cputopology.txt @@ -44,7 +44,7 @@ these macros in include/asm-XXX/topology.h: #define topology_physical_package_id(cpu) #define topology_core_id(cpu) #define topology_book_id(cpu) -#define topology_thread_cpumask(cpu) +#define topology_sibling_cpumask(cpu) #define topology_core_cpumask(cpu) #define topology_book_cpumask(cpu) diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index 2fe85fff5cca..370f7a732900 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h @@ -18,7 +18,7 @@ extern struct cputopo_arm cpu_topology[NR_CPUS]; #define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) -#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) +#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) void init_cpu_topology(void); void store_cpu_topology(unsigned int cpuid); diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 7ebcd31ce51c..225ec3524fbf 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -18,7 +18,7 @@ extern struct cpu_topology cpu_topology[NR_CPUS]; #define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) -#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) +#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) void init_cpu_topology(void); void store_cpu_topology(unsigned int cpuid); diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h index 6437ca21f61b..3ad8f6988363 100644 --- a/arch/ia64/include/asm/topology.h +++ b/arch/ia64/include/asm/topology.h @@ -53,7 +53,7 @@ void build_cpu_to_node_map(void); #define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id) #define topology_core_id(cpu) (cpu_data(cpu)->core_id) #define topology_core_cpumask(cpu) (&cpu_core_map[cpu]) -#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) +#define topology_sibling_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) #endif extern void arch_fix_phys_package_id(int num, u32 slot); diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h index 3e307ec2afba..7afda4150a59 100644 --- a/arch/mips/include/asm/topology.h +++ b/arch/mips/include/asm/topology.h @@ -15,7 +15,7 @@ #define topology_physical_package_id(cpu) (cpu_data[cpu].package) #define topology_core_id(cpu) (cpu_data[cpu].core) #define topology_core_cpumask(cpu) (&cpu_core_map[cpu]) -#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) +#define topology_sibling_cpumask(cpu) (&cpu_sibling_map[cpu]) #endif #endif /* __ASM_TOPOLOGY_H */ diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h index 5f1048eaa5b6..8b3b46b7b0f2 100644 --- a/arch/powerpc/include/asm/topology.h +++ b/arch/powerpc/include/asm/topology.h @@ -87,7 +87,7 @@ static inline int prrn_is_enabled(void) #include #define topology_physical_package_id(cpu) (cpu_to_chip_id(cpu)) -#define topology_thread_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) +#define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) #define topology_core_id(cpu) (cpu_to_core_id(cpu)) #endif diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index cbd3d069897f..723a099f6be3 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c @@ -217,7 +217,7 @@ static DEFINE_RAW_SPINLOCK(tlbivax_lock); static int mm_is_core_local(struct mm_struct *mm) { return cpumask_subset(mm_cpumask(mm), - topology_thread_cpumask(smp_processor_id())); + topology_sibling_cpumask(smp_processor_id())); } struct tlb_flush_param { diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h index b1453a2ae1ca..4990f6c66288 100644 --- a/arch/s390/include/asm/topology.h +++ b/arch/s390/include/asm/topology.h @@ -22,7 +22,8 @@ DECLARE_PER_CPU(struct cpu_topology_s390, cpu_topology); #define topology_physical_package_id(cpu) (per_cpu(cpu_topology, cpu).socket_id) #define topology_thread_id(cpu) (per_cpu(cpu_topology, cpu).thread_id) -#define topology_thread_cpumask(cpu) (&per_cpu(cpu_topology, cpu).thread_mask) +#define topology_sibling_cpumask(cpu) \ + (&per_cpu(cpu_topology, cpu).thread_mask) #define topology_core_id(cpu) (per_cpu(cpu_topology, cpu).core_id) #define topology_core_cpumask(cpu) (&per_cpu(cpu_topology, cpu).core_mask) #define topology_book_id(cpu) (per_cpu(cpu_topology, cpu).book_id) diff --git a/arch/sparc/include/asm/topology_64.h b/arch/sparc/include/asm/topology_64.h index ed8f071132e4..9a928fcb7a9b 100644 --- a/arch/sparc/include/asm/topology_64.h +++ b/arch/sparc/include/asm/topology_64.h @@ -41,7 +41,7 @@ static inline int pcibus_to_node(struct pci_bus *pbus) #define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) #define topology_core_id(cpu) (cpu_data(cpu).core_id) #define topology_core_cpumask(cpu) (&cpu_core_map[cpu]) -#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) +#define topology_sibling_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) #endif /* CONFIG_SMP */ extern cpumask_t cpu_core_map[NR_CPUS]; diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h index 938311844233..76b0d0ebb244 100644 --- a/arch/tile/include/asm/topology.h +++ b/arch/tile/include/asm/topology.h @@ -55,7 +55,7 @@ static inline const struct cpumask *cpumask_of_node(int node) #define topology_physical_package_id(cpu) ((void)(cpu), 0) #define topology_core_id(cpu) (cpu) #define topology_core_cpumask(cpu) ((void)(cpu), cpu_online_mask) -#define topology_thread_cpumask(cpu) cpumask_of(cpu) +#define topology_sibling_cpumask(cpu) cpumask_of(cpu) #endif #endif /* _ASM_TILE_TOPOLOGY_H */ diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 0e8f04f2c26f..5a77593fdace 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -124,7 +124,7 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu); #ifdef ENABLE_TOPO_DEFINES #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) -#define topology_thread_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) +#define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) #endif static inline void arch_fix_phys_package_id(int num, u32 slot) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 3998131d1a68..324817735771 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2621,7 +2621,7 @@ static void intel_pmu_cpu_starting(int cpu) if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED]; - for_each_cpu(i, topology_thread_cpumask(cpu)) { + for_each_cpu(i, topology_sibling_cpumask(cpu)) { struct intel_shared_regs *pc; pc = per_cpu(cpu_hw_events, i).shared_regs; @@ -2641,7 +2641,7 @@ static void intel_pmu_cpu_starting(int cpu) if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { int h = x86_pmu.num_counters >> 1; - for_each_cpu(i, topology_thread_cpumask(cpu)) { + for_each_cpu(i, topology_sibling_cpumask(cpu)) { struct intel_excl_cntrs *c; c = per_cpu(cpu_hw_events, i).excl_cntrs; @@ -3403,7 +3403,7 @@ static __init int fixup_ht_bug(void) if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) return 0; - w = cpumask_weight(topology_thread_cpumask(cpu)); + w = cpumask_weight(topology_sibling_cpumask(cpu)); if (w > 1) { pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); return 0; diff --git a/block/blk-mq-cpumap.c b/block/blk-mq-cpumap.c index 5f13f4d0bcce..1e28ddb656b8 100644 --- a/block/blk-mq-cpumap.c +++ b/block/blk-mq-cpumap.c @@ -24,7 +24,7 @@ static int get_first_sibling(unsigned int cpu) { unsigned int ret; - ret = cpumask_first(topology_thread_cpumask(cpu)); + ret = cpumask_first(topology_sibling_cpumask(cpu)); if (ret < nr_cpu_ids) return ret; diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 6bc9cbc01ad6..00b39802d7ec 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -105,7 +105,7 @@ static void round_robin_cpu(unsigned int tsk_index) mutex_lock(&round_robin_lock); cpumask_clear(tmp); for_each_cpu(cpu, pad_busy_cpus) - cpumask_or(tmp, tmp, topology_thread_cpumask(cpu)); + cpumask_or(tmp, tmp, topology_sibling_cpumask(cpu)); cpumask_andnot(tmp, cpu_online_mask, tmp); /* avoid HT sibilings if possible */ if (cpumask_empty(tmp)) diff --git a/drivers/base/topology.c b/drivers/base/topology.c index 6491f45200a7..8b7d7f8e5851 100644 --- a/drivers/base/topology.c +++ b/drivers/base/topology.c @@ -61,7 +61,7 @@ static DEVICE_ATTR_RO(physical_package_id); define_id_show_func(core_id); static DEVICE_ATTR_RO(core_id); -define_siblings_show_func(thread_siblings, thread_cpumask); +define_siblings_show_func(thread_siblings, sibling_cpumask); static DEVICE_ATTR_RO(thread_siblings); static DEVICE_ATTR_RO(thread_siblings_list); diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c index 4b00545a3ace..65944dd8bf6b 100644 --- a/drivers/net/ethernet/sfc/efx.c +++ b/drivers/net/ethernet/sfc/efx.c @@ -1304,7 +1304,7 @@ static unsigned int efx_wanted_parallelism(struct efx_nic *efx) if (!cpumask_test_cpu(cpu, thread_mask)) { ++count; cpumask_or(thread_mask, thread_mask, - topology_thread_cpumask(cpu)); + topology_sibling_cpumask(cpu)); } } diff --git a/drivers/staging/lustre/lustre/libcfs/linux/linux-cpu.c b/drivers/staging/lustre/lustre/libcfs/linux/linux-cpu.c index cc3ab351943e..f9262243f935 100644 --- a/drivers/staging/lustre/lustre/libcfs/linux/linux-cpu.c +++ b/drivers/staging/lustre/lustre/libcfs/linux/linux-cpu.c @@ -87,7 +87,7 @@ static void cfs_cpu_core_siblings(int cpu, cpumask_t *mask) /* return cpumask of HTs in the same core */ static void cfs_cpu_ht_siblings(int cpu, cpumask_t *mask) { - cpumask_copy(mask, topology_thread_cpumask(cpu)); + cpumask_copy(mask, topology_sibling_cpumask(cpu)); } static void cfs_node_to_cpumask(int node, cpumask_t *mask) diff --git a/drivers/staging/lustre/lustre/ptlrpc/service.c b/drivers/staging/lustre/lustre/ptlrpc/service.c index 8e61421515cb..344189ac5698 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/service.c +++ b/drivers/staging/lustre/lustre/ptlrpc/service.c @@ -557,7 +557,7 @@ ptlrpc_server_nthreads_check(struct ptlrpc_service *svc, * there are. */ /* weight is # of HTs */ - if (cpumask_weight(topology_thread_cpumask(0)) > 1) { + if (cpumask_weight(topology_sibling_cpumask(0)) > 1) { /* depress thread factor for hyper-thread */ factor = factor - (factor >> 1) + (factor >> 3); } @@ -2768,7 +2768,7 @@ int ptlrpc_hr_init(void) init_waitqueue_head(&ptlrpc_hr.hr_waitq); - weight = cpumask_weight(topology_thread_cpumask(0)); + weight = cpumask_weight(topology_sibling_cpumask(0)); cfs_percpt_for_each(hrp, i, ptlrpc_hr.hr_partitions) { hrp->hrp_cpt = i; diff --git a/include/linux/topology.h b/include/linux/topology.h index 909b6e43b694..73ddad1e0fa3 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -191,8 +191,8 @@ static inline int cpu_to_mem(int cpu) #ifndef topology_core_id #define topology_core_id(cpu) ((void)(cpu), 0) #endif -#ifndef topology_thread_cpumask -#define topology_thread_cpumask(cpu) cpumask_of(cpu) +#ifndef topology_sibling_cpumask +#define topology_sibling_cpumask(cpu) cpumask_of(cpu) #endif #ifndef topology_core_cpumask #define topology_core_cpumask(cpu) cpumask_of(cpu) @@ -201,7 +201,7 @@ static inline int cpu_to_mem(int cpu) #ifdef CONFIG_SCHED_SMT static inline const struct cpumask *cpu_smt_mask(int cpu) { - return topology_thread_cpumask(cpu); + return topology_sibling_cpumask(cpu); } #endif diff --git a/lib/cpu_rmap.c b/lib/cpu_rmap.c index 4f134d8907a7..f610b2a10b3e 100644 --- a/lib/cpu_rmap.c +++ b/lib/cpu_rmap.c @@ -191,7 +191,7 @@ int cpu_rmap_update(struct cpu_rmap *rmap, u16 index, /* Update distances based on topology */ for_each_cpu(cpu, update_mask) { if (cpu_rmap_copy_neigh(rmap, cpu, - topology_thread_cpumask(cpu), 1)) + topology_sibling_cpumask(cpu), 1)) continue; if (cpu_rmap_copy_neigh(rmap, cpu, topology_core_cpumask(cpu), 2)) -- cgit v1.2.3 From 54a5369487fc0a9506bbf31ab2e00e5dc5d6d4cd Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 26 May 2015 15:11:29 +0200 Subject: Documentation: Update cputopology.txt The documentation on cpu topology seems to be a bit out-of-date. It doesn't mention the **_siblings_list attributes and uses old names for topology_**_cpumask() macros. Add information on missing attributes plus some additional clarifications. Signed-off-by: Bartosz Golaszewski Cc: Benoit Cousson Cc: Catalin Marinas Cc: Fenghua Yu Cc: Guenter Roeck Cc: Jean Delvare Cc: Jonathan Corbet Cc: Linus Torvalds Cc: Oleg Drokin Cc: Peter Zijlstra Cc: Rafael J. Wysocki Cc: Russell King Cc: Thomas Gleixner Cc: Viresh Kumar Link: http://lkml.kernel.org/r/1432645896-12588-3-git-send-email-bgolaszewski@baylibre.com Signed-off-by: Ingo Molnar --- Documentation/cputopology.txt | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cputopology.txt b/Documentation/cputopology.txt index 428a961ff063..12b1b25b4da9 100644 --- a/Documentation/cputopology.txt +++ b/Documentation/cputopology.txt @@ -1,6 +1,6 @@ Export CPU topology info via sysfs. Items (attributes) are similar -to /proc/cpuinfo. +to /proc/cpuinfo output of some architectures: 1) /sys/devices/system/cpu/cpuX/topology/physical_package_id: @@ -23,20 +23,35 @@ to /proc/cpuinfo. 4) /sys/devices/system/cpu/cpuX/topology/thread_siblings: internal kernel map of cpuX's hardware threads within the same - core as cpuX + core as cpuX. -5) /sys/devices/system/cpu/cpuX/topology/core_siblings: +5) /sys/devices/system/cpu/cpuX/topology/thread_siblings_list: + + human-readable list of cpuX's hardware threads within the same + core as cpuX. + +6) /sys/devices/system/cpu/cpuX/topology/core_siblings: internal kernel map of cpuX's hardware threads within the same physical_package_id. -6) /sys/devices/system/cpu/cpuX/topology/book_siblings: +7) /sys/devices/system/cpu/cpuX/topology/core_siblings_list: + + human-readable list of cpuX's hardware threads within the same + physical_package_id. + +8) /sys/devices/system/cpu/cpuX/topology/book_siblings: internal kernel map of cpuX's hardware threads within the same book_id. +9) /sys/devices/system/cpu/cpuX/topology/book_siblings_list: + + human-readable list of cpuX's hardware threads within the same + book_id. + To implement it in an architecture-neutral way, a new source file, -drivers/base/topology.c, is to export the 4 or 6 attributes. The two book +drivers/base/topology.c, is to export the 6 or 9 attributes. The three book related sysfs files will only be created if CONFIG_SCHED_BOOK is selected. For an architecture to support this feature, it must define some of @@ -48,16 +63,18 @@ these macros in include/asm-XXX/topology.h: #define topology_core_cpumask(cpu) #define topology_book_cpumask(cpu) -The type of **_id is int. -The type of siblings is (const) struct cpumask *. +The type of **_id macros is int. +The type of **_cpumask macros is (const) struct cpumask *. The latter +correspond with appropriate **_siblings sysfs attributes (except for +topology_sibling_cpumask() which corresponds with thread_siblings). To be consistent on all architectures, include/linux/topology.h provides default definitions for any of the above macros that are not defined by include/asm-XXX/topology.h: 1) physical_package_id: -1 2) core_id: 0 -3) thread_siblings: just the given CPU -4) core_siblings: just the given CPU +3) sibling_cpumask: just the given CPU +4) core_cpumask: just the given CPU For architectures that don't support books (CONFIG_SCHED_BOOK) there are no default definitions for topology_book_id() and topology_book_cpumask(). -- cgit v1.2.3 From c208358c2cc832eeb5b341a465eee30be19cd5a0 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Wed, 27 May 2015 14:14:22 +0100 Subject: efi: Add 'systab' information to Documentation/ABI It's not clear right now that the order in which entries are displayed in /sys/firmware/efi/systab actually forms an ABI that userspace tools rely upon. Document the ABI along with the userspace tool that cares. Suggested-by: Ard Biesheuvel Acked-by: Ard Biesheuvel Reviewed-by: Jean Delvare Cc: Leif Lindholm Cc: Ivan Khoronzhuk Signed-off-by: Matt Fleming --- Documentation/ABI/testing/sysfs-firmware-efi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-firmware-efi b/Documentation/ABI/testing/sysfs-firmware-efi index 05874da7ce80..e794eac32a90 100644 --- a/Documentation/ABI/testing/sysfs-firmware-efi +++ b/Documentation/ABI/testing/sysfs-firmware-efi @@ -18,3 +18,13 @@ Contact: Dave Young Description: It shows the physical address of config table entry in the EFI system table. Users: Kexec + +What: /sys/firmware/efi/systab +Date: April 2005 +Contact: linux-efi@vger.kernel.org +Description: Displays the physical addresses of all EFI Configuration + Tables found via the EFI System Table. The order in + which the tables are printed forms an ABI and newer + versions are always printed first, i.e. ACPI20 comes + before ACPI. +Users: dmidecode -- cgit v1.2.3 From 07f4c90062f8fc7c8c26f8f95324cbe8fa3145a5 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Sun, 24 May 2015 14:49:35 -0700 Subject: tcp/dccp: try to not exhaust ip_local_port_range in connect() A long standing problem on busy servers is the tiny available TCP port range (/proc/sys/net/ipv4/ip_local_port_range) and the default sequential allocation of source ports in connect() system call. If a host is having a lot of active TCP sessions, chances are very high that all ports are in use by at least one flow, and subsequent bind(0) attempts fail, or have to scan a big portion of space to find a slot. In this patch, I changed the starting point in __inet_hash_connect() so that we try to favor even [1] ports, leaving odd ports for bind() users. We still perform a sequential search, so there is no guarantee, but if connect() targets are very different, end result is we leave more ports available to bind(), and we spread them all over the range, lowering time for both connect() and bind() to find a slot. This strategy only works well if /proc/sys/net/ipv4/ip_local_port_range is even, ie if start/end values have different parity. Therefore, default /proc/sys/net/ipv4/ip_local_port_range was changed to 32768 - 60999 (instead of 32768 - 61000) There is no change on security aspects here, only some poor hashing schemes could be eventually impacted by this change. [1] : The odd/even property depends on ip_local_port_range values parity Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller --- Documentation/networking/ip-sysctl.txt | 8 +++++--- net/ipv4/af_inet.c | 2 +- net/ipv4/inet_hashtables.c | 10 ++++++++-- 3 files changed, 14 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index cb083e0d682c..5fae7704daab 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -751,8 +751,10 @@ IP Variables: ip_local_port_range - 2 INTEGERS Defines the local port range that is used by TCP and UDP to choose the local port. The first number is the first, the - second the last local port number. The default values are - 32768 and 61000 respectively. + second the last local port number. + If possible, it is better these numbers have different parity. + (one even and one odd values) + The default values are 32768 and 60999 respectively. ip_local_reserved_ports - list of comma separated ranges Specify the ports which are reserved for known third-party @@ -775,7 +777,7 @@ ip_local_reserved_ports - list of comma separated ranges ip_local_port_range, e.g.: $ cat /proc/sys/net/ipv4/ip_local_port_range - 32000 61000 + 32000 60999 $ cat /proc/sys/net/ipv4/ip_local_reserved_ports 8080,9148 diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 235d36afece3..6ad0f7a711c9 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -1595,7 +1595,7 @@ static __net_init int inet_init_net(struct net *net) */ seqlock_init(&net->ipv4.ip_local_ports.lock); net->ipv4.ip_local_ports.range[0] = 32768; - net->ipv4.ip_local_ports.range[1] = 61000; + net->ipv4.ip_local_ports.range[1] = 60999; seqlock_init(&net->ipv4.ping_group_range.lock); /* diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c index 185efef0f125..1b336dc179f8 100644 --- a/net/ipv4/inet_hashtables.c +++ b/net/ipv4/inet_hashtables.c @@ -502,8 +502,14 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row, inet_get_local_port_range(net, &low, &high); remaining = (high - low) + 1; + /* By starting with offset being an even number, + * we tend to leave about 50% of ports for other uses, + * like bind(0). + */ + offset &= ~1; + local_bh_disable(); - for (i = 1; i <= remaining; i++) { + for (i = 0; i < remaining; i++) { port = low + (i + offset) % remaining; if (inet_is_local_reserved_port(net, port)) continue; @@ -547,7 +553,7 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row, return -EADDRNOTAVAIL; ok: - hint += i; + hint += (i + 2) & ~1; /* Head lock still held and bh's disabled */ inet_bind_hash(sk, tb, port); -- cgit v1.2.3 From 4dacccfac69494ba70248b134352f299171c41b7 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 26 May 2015 11:44:43 +0200 Subject: spi: orion: Fix extended baud rates for each Armada SoCs The commit df59fa7f4bca "spi: orion: support armada extended baud rates" made the assumptions that all the Armada SoCs supported the same maximum frequency. However, according the hardware datasheet, the maximum frequency supported by the Armada 370 SoC is tclk/4, for the Armada XP, Armada 38x and Armada 39x SoCs the limitation is 50MHz and for the Armada 375 it is tclk/15. This patch introduces new compatible strings to handle all these case. In order to be future proof a compatible was created for each SoC even if currently some SoCs seem using the same IP. Signed-off-by: Gregory CLEMENT Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-orion.txt | 8 +++- drivers/spi/spi-orion.c | 47 ++++++++++++++++++++-- 2 files changed, 50 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt index 50c3a3de61c1..98bc69815eb3 100644 --- a/Documentation/devicetree/bindings/spi/spi-orion.txt +++ b/Documentation/devicetree/bindings/spi/spi-orion.txt @@ -1,7 +1,13 @@ Marvell Orion SPI device Required properties: -- compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi". +- compatible : should be on of the following: + - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs + - "marvell,armada-370-spi", for the Armada 370 SoCs + - "marvell,armada-375-spi", for the Armada 375 SoCs + - "marvell,armada-380-spi", for the Armada 38x SoCs + - "marvell,armada-390-spi", for the Armada 39x SoCs + - "marvell,armada-xp-spi", for the Armada XP SoCs - reg : offset and length of the register set for the device - cell-index : Which of multiple SPI controllers is this. Optional properties: diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index ff97cabdaa81..8cad107a5b3f 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c @@ -391,7 +391,7 @@ static const struct orion_spi_dev orion_spi_dev_data = { .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, }; -static const struct orion_spi_dev armada_spi_dev_data = { +static const struct orion_spi_dev armada_370_spi_dev_data = { .typ = ARMADA_SPI, .min_divisor = 4, .max_divisor = 1920, @@ -399,9 +399,46 @@ static const struct orion_spi_dev armada_spi_dev_data = { .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, }; +static const struct orion_spi_dev armada_xp_spi_dev_data = { + .typ = ARMADA_SPI, + .max_hz = 50000000, + .max_divisor = 1920, + .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, +}; + +static const struct orion_spi_dev armada_375_spi_dev_data = { + .typ = ARMADA_SPI, + .min_divisor = 15, + .max_divisor = 1920, + .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, +}; + static const struct of_device_id orion_spi_of_match_table[] = { - { .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, }, - { .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, }, + { + .compatible = "marvell,orion-spi", + .data = &orion_spi_dev_data, + }, + { + .compatible = "marvell,armada-370-spi", + .data = &armada_370_spi_dev_data, + }, + { + .compatible = "marvell,armada-375-spi", + .data = &armada_375_spi_dev_data, + }, + { + .compatible = "marvell,armada-380-spi", + .data = &armada_xp_spi_dev_data, + }, + { + .compatible = "marvell,armada-390-spi", + .data = &armada_xp_spi_dev_data, + }, + { + .compatible = "marvell,armada-xp-spi", + .data = &armada_xp_spi_dev_data, + }, + {} }; MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); @@ -473,9 +510,11 @@ static int orion_spi_probe(struct platform_device *pdev) "marvell,armada-370-spi")) master->max_speed_hz = min(devdata->max_hz, DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); - else + else if (devdata->min_divisor) master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor); + else + master->max_speed_hz = devdata->max_hz; master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- cgit v1.2.3 From cf9fbf8017e2ab5cb33b6602b626f7f005718124 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 20 Apr 2015 06:09:27 -0700 Subject: documentation: RCU-protected array indexes no longer supported Signed-off-by: Paul E. McKenney --- Documentation/RCU/arrayRCU.txt | 20 ++++++++++++++++---- Documentation/RCU/lockdep.txt | 10 ---------- Documentation/RCU/rcu_dereference.txt | 33 ++++++++++++--------------------- Documentation/RCU/whatisRCU.txt | 2 -- 4 files changed, 28 insertions(+), 37 deletions(-) (limited to 'Documentation') diff --git a/Documentation/RCU/arrayRCU.txt b/Documentation/RCU/arrayRCU.txt index 453ebe6953ee..f05a9afb2c39 100644 --- a/Documentation/RCU/arrayRCU.txt +++ b/Documentation/RCU/arrayRCU.txt @@ -10,7 +10,19 @@ also be used to protect arrays. Three situations are as follows: 3. Resizeable Arrays -Each of these situations are discussed below. +Each of these three situations involves an RCU-protected pointer to an +array that is separately indexed. It might be tempting to consider use +of RCU to instead protect the index into an array, however, this use +case is -not- supported. The problem with RCU-protected indexes into +arrays is that compilers can play way too many optimization games with +integers, which means that the rules governing handling of these indexes +are far more trouble than they are worth. If RCU-protected indexes into +arrays prove to be particularly valuable (which they have not thus far), +explicit cooperation from the compiler will be required to permit them +to be safely used. + +That aside, each of the three RCU-protected pointer situations are +described in the following sections. Situation 1: Hash Tables @@ -36,9 +48,9 @@ Quick Quiz: Why is it so important that updates be rare when Situation 3: Resizeable Arrays Use of RCU for resizeable arrays is demonstrated by the grow_ary() -function used by the System V IPC code. The array is used to map from -semaphore, message-queue, and shared-memory IDs to the data structure -that represents the corresponding IPC construct. The grow_ary() +function formerly used by the System V IPC code. The array is used +to map from semaphore, message-queue, and shared-memory IDs to the data +structure that represents the corresponding IPC construct. The grow_ary() function does not acquire any locks; instead its caller must hold the ids->sem semaphore. diff --git a/Documentation/RCU/lockdep.txt b/Documentation/RCU/lockdep.txt index cd83d2348fef..da51d3068850 100644 --- a/Documentation/RCU/lockdep.txt +++ b/Documentation/RCU/lockdep.txt @@ -47,11 +47,6 @@ checking of rcu_dereference() primitives: Use explicit check expression "c" along with srcu_read_lock_held()(). This is useful in code that is invoked by both SRCU readers and updaters. - rcu_dereference_index_check(p, c): - Use explicit check expression "c", but the caller - must supply one of the rcu_read_lock_held() functions. - This is useful in code that uses RCU-protected arrays - that is invoked by both RCU readers and updaters. rcu_dereference_raw(p): Don't check. (Use sparingly, if at all.) rcu_dereference_protected(p, c): @@ -64,11 +59,6 @@ checking of rcu_dereference() primitives: but retain the compiler constraints that prevent duplicating or coalescsing. This is useful when when testing the value of the pointer itself, for example, against NULL. - rcu_access_index(idx): - Return the value of the index and omit all barriers, but - retain the compiler constraints that prevent duplicating - or coalescsing. This is useful when when testing the - value of the index itself, for example, against -1. The rcu_dereference_check() check expression can be any boolean expression, but would normally include a lockdep expression. However, diff --git a/Documentation/RCU/rcu_dereference.txt b/Documentation/RCU/rcu_dereference.txt index ceb05da5a5ac..66864d2a7f60 100644 --- a/Documentation/RCU/rcu_dereference.txt +++ b/Documentation/RCU/rcu_dereference.txt @@ -25,17 +25,6 @@ o You must use one of the rcu_dereference() family of primitives for an example where the compiler can in fact deduce the exact value of the pointer, and thus cause misordering. -o Do not use single-element RCU-protected arrays. The compiler - is within its right to assume that the value of an index into - such an array must necessarily evaluate to zero. The compiler - could then substitute the constant zero for the computation, so - that the array index no longer depended on the value returned - by rcu_dereference(). If the array index no longer depends - on rcu_dereference(), then both the compiler and the CPU - are within their rights to order the array access before the - rcu_dereference(), which can cause the array access to return - garbage. - o Avoid cancellation when using the "+" and "-" infix arithmetic operators. For example, for a given variable "x", avoid "(x-x)". There are similar arithmetic pitfalls from other @@ -76,14 +65,15 @@ o Do not use the results from the boolean "&&" and "||" when dereferencing. For example, the following (rather improbable) code is buggy: - int a[2]; - int index; - int force_zero_index = 1; + int *p; + int *q; ... - r1 = rcu_dereference(i1) - r2 = a[r1 && force_zero_index]; /* BUGGY!!! */ + p = rcu_dereference(gp) + q = &global_q; + q += p != &oom_p1 && p != &oom_p2; + r1 = *q; /* BUGGY!!! */ The reason this is buggy is that "&&" and "||" are often compiled using branches. While weak-memory machines such as ARM or PowerPC @@ -94,14 +84,15 @@ o Do not use the results from relational operators ("==", "!=", ">", ">=", "<", or "<=") when dereferencing. For example, the following (quite strange) code is buggy: - int a[2]; - int index; - int flip_index = 0; + int *p; + int *q; ... - r1 = rcu_dereference(i1) - r2 = a[r1 != flip_index]; /* BUGGY!!! */ + p = rcu_dereference(gp) + q = &global_q; + q += p > &oom_p; + r1 = *q; /* BUGGY!!! */ As before, the reason this is buggy is that relational operators are often compiled using branches. And as before, although diff --git a/Documentation/RCU/whatisRCU.txt b/Documentation/RCU/whatisRCU.txt index 88dfce182f66..b201d4cd77f9 100644 --- a/Documentation/RCU/whatisRCU.txt +++ b/Documentation/RCU/whatisRCU.txt @@ -879,9 +879,7 @@ SRCU: Initialization/cleanup All: lockdep-checked RCU-protected pointer access - rcu_access_index rcu_access_pointer - rcu_dereference_index_check rcu_dereference_raw rcu_lockdep_assert rcu_sleep_check -- cgit v1.2.3 From d956028e99b30726b0bce0ca684b40b1ad67b514 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 31 Mar 2015 09:39:41 +0100 Subject: documentation: memory-barriers: Fix smp_mb__before_spinlock() semantics Our current documentation claims that, when followed by an ACQUIRE, smp_mb__before_spinlock() orders prior loads against subsequent loads and stores, which isn't the intent. This commit therefore fixes the documentation to state that this sequence orders only prior stores against subsequent loads and stores. In addition, the original intent of smp_mb__before_spinlock() was to only order prior loads against subsequent stores, however, people have started using it as if it ordered prior loads against subsequent loads and stores. This commit therefore also updates smp_mb__before_spinlock()'s header comment to reflect this new reality. Cc: Oleg Nesterov Cc: "Paul E. McKenney" Cc: Peter Zijlstra Signed-off-by: Will Deacon Signed-off-by: Paul E. McKenney --- Documentation/memory-barriers.txt | 7 +++---- include/linux/spinlock.h | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index f95746189b5d..1f362fd2ecb4 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1784,10 +1784,9 @@ for each construct. These operations all imply certain barriers: Memory operations issued before the ACQUIRE may be completed after the ACQUIRE operation has completed. An smp_mb__before_spinlock(), - combined with a following ACQUIRE, orders prior loads against - subsequent loads and stores and also orders prior stores against - subsequent stores. Note that this is weaker than smp_mb()! The - smp_mb__before_spinlock() primitive is free on many architectures. + combined with a following ACQUIRE, orders prior stores against + subsequent loads and stores. Note that this is weaker than smp_mb()! + The smp_mb__before_spinlock() primitive is free on many architectures. (2) RELEASE operation implication: diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index 3e18379dfa6f..0063b24b4f36 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -120,7 +120,7 @@ do { \ /* * Despite its name it doesn't necessarily has to be a full barrier. * It should only guarantee that a STORE before the critical section - * can not be reordered with a LOAD inside this section. + * can not be reordered with LOADs and STOREs inside this section. * spin_lock() is the one-way barrier, this LOAD can not escape out * of the region. So the default implementation simply ensures that * a STORE can not move into the critical section, smp_wmb() should -- cgit v1.2.3 From ee7c29be3695996536395f647e8a2ed6b1ab3a0d Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Tue, 7 Apr 2015 12:45:41 -0700 Subject: documentation: Update rcu_dereference.txt based on WG21 discussions This commit provides another caveat for the care and feeding of pointers returned by rcu_dereference() that was pointed out in discussions within the C++ standards committee. Signed-off-by: Paul E. McKenney Reviewed-by: Mathieu Desnoyers --- Documentation/RCU/rcu_dereference.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/RCU/rcu_dereference.txt b/Documentation/RCU/rcu_dereference.txt index ceb05da5a5ac..2d05c9241a33 100644 --- a/Documentation/RCU/rcu_dereference.txt +++ b/Documentation/RCU/rcu_dereference.txt @@ -193,6 +193,11 @@ o Be very careful about comparing pointers obtained from pointer. Note that the volatile cast in rcu_dereference() will normally prevent the compiler from knowing too much. + However, please note that if the compiler knows that the + pointer takes on only one of two values, a not-equal + comparison will provide exactly the information that the + compiler needs to deduce the value of the pointer. + o Disable any value-speculation optimizations that your compiler might provide, especially if you are making use of feedback-based optimizations that take data collected from prior runs. Such -- cgit v1.2.3 From ed38446424dd531f1b7a167677232a6d400d69d5 Mon Sep 17 00:00:00 2001 From: Milos Vyletel Date: Fri, 17 Apr 2015 16:38:04 +0200 Subject: documentation: State that rcu_dereference() reloads pointer Make a note stating that repeated calls of rcu_dereference() may not return the same pointer if update happens while in critical section. Reported-by: Jeff Haran Signed-off-by: Milos Vyletel Reviewed-by: Steven Rostedt Signed-off-by: Paul E. McKenney --- Documentation/RCU/whatisRCU.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/RCU/whatisRCU.txt b/Documentation/RCU/whatisRCU.txt index 88dfce182f66..16622c9e86b5 100644 --- a/Documentation/RCU/whatisRCU.txt +++ b/Documentation/RCU/whatisRCU.txt @@ -256,7 +256,9 @@ rcu_dereference() If you are going to be fetching multiple fields from the RCU-protected structure, using the local variable is of course preferred. Repeated rcu_dereference() calls look - ugly and incur unnecessary overhead on Alpha CPUs. + ugly, do not guarantee that the same pointer will be returned + if an update happened while in the critical section, and incur + unnecessary overhead on Alpha CPUs. Note that the value returned by rcu_dereference() is valid only within the enclosing RCU read-side critical section. -- cgit v1.2.3 From 5af4692a75daf08dddc93dbb4cd2a1b3d3b617af Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Sat, 25 Apr 2015 12:48:29 -0700 Subject: smp: Make control dependencies work on Alpha, improve documentation The current formulation of control dependencies fails on DEC Alpha, which does not respect dependencies of any kind unless an explicit memory barrier is provided. This means that the current fomulation of control dependencies fails on Alpha. This commit therefore creates a READ_ONCE_CTRL() that has the same overhead on non-Alpha systems, but causes Alpha to produce the needed ordering. This commit also applies READ_ONCE_CTRL() to the one known use of control dependencies. Use of READ_ONCE_CTRL() also has the beneficial effect of adding a bit of self-documentation to control dependencies. Signed-off-by: Paul E. McKenney Acked-by: Peter Zijlstra (Intel) --- Documentation/memory-barriers.txt | 55 +++++++++++++++++++++++---------------- include/linux/compiler.h | 16 ++++++++++++ kernel/events/ring_buffer.c | 2 +- 3 files changed, 50 insertions(+), 23 deletions(-) (limited to 'Documentation') diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index f95746189b5d..a3014bcc5b08 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -617,16 +617,16 @@ case what's actually required is: However, stores are not speculated. This means that ordering -is- provided for load-store control dependencies, as in the following example: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); if (q) { ACCESS_ONCE(b) = p; } -Control dependencies pair normally with other types of barriers. -That said, please note that ACCESS_ONCE() is not optional! Without the -ACCESS_ONCE(), might combine the load from 'a' with other loads from -'a', and the store to 'b' with other stores to 'b', with possible highly -counterintuitive effects on ordering. +Control dependencies pair normally with other types of barriers. That +said, please note that READ_ONCE_CTRL() is not optional! Without the +READ_ONCE_CTRL(), the compiler might combine the load from 'a' with +other loads from 'a', and the store to 'b' with other stores to 'b', +with possible highly counterintuitive effects on ordering. Worse yet, if the compiler is able to prove (say) that the value of variable 'a' is always non-zero, it would be well within its rights @@ -636,12 +636,15 @@ as follows: q = a; b = p; /* BUG: Compiler and CPU can both reorder!!! */ -So don't leave out the ACCESS_ONCE(). +Finally, the READ_ONCE_CTRL() includes an smp_read_barrier_depends() +that DEC Alpha needs in order to respect control depedencies. + +So don't leave out the READ_ONCE_CTRL(). It is tempting to try to enforce ordering on identical stores on both branches of the "if" statement as follows: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); if (q) { barrier(); ACCESS_ONCE(b) = p; @@ -655,7 +658,7 @@ branches of the "if" statement as follows: Unfortunately, current compilers will transform this as follows at high optimization levels: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); barrier(); ACCESS_ONCE(b) = p; /* BUG: No ordering vs. load from a!!! */ if (q) { @@ -685,7 +688,7 @@ memory barriers, for example, smp_store_release(): In contrast, without explicit memory barriers, two-legged-if control ordering is guaranteed only when the stores differ, for example: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); if (q) { ACCESS_ONCE(b) = p; do_something(); @@ -694,14 +697,14 @@ ordering is guaranteed only when the stores differ, for example: do_something_else(); } -The initial ACCESS_ONCE() is still required to prevent the compiler from -proving the value of 'a'. +The initial READ_ONCE_CTRL() is still required to prevent the compiler +from proving the value of 'a'. In addition, you need to be careful what you do with the local variable 'q', otherwise the compiler might be able to guess the value and again remove the needed conditional. For example: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); if (q % MAX) { ACCESS_ONCE(b) = p; do_something(); @@ -714,7 +717,7 @@ If MAX is defined to be 1, then the compiler knows that (q % MAX) is equal to zero, in which case the compiler is within its rights to transform the above code into the following: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); ACCESS_ONCE(b) = p; do_something_else(); @@ -725,7 +728,7 @@ is gone, and the barrier won't bring it back. Therefore, if you are relying on this ordering, you should make sure that MAX is greater than one, perhaps as follows: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */ if (q % MAX) { ACCESS_ONCE(b) = p; @@ -742,14 +745,15 @@ of the 'if' statement. You must also be careful not to rely too much on boolean short-circuit evaluation. Consider this example: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); if (a || 1 > 0) ACCESS_ONCE(b) = 1; -Because the second condition is always true, the compiler can transform -this example as following, defeating control dependency: +Because the first condition cannot fault and the second condition is +always true, the compiler can transform this example as following, +defeating control dependency: - q = ACCESS_ONCE(a); + q = READ_ONCE_CTRL(a); ACCESS_ONCE(b) = 1; This example underscores the need to ensure that the compiler cannot @@ -762,8 +766,8 @@ demonstrated by two related examples, with the initial values of x and y both being zero: CPU 0 CPU 1 - ===================== ===================== - r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(y); + ======================= ======================= + r1 = READ_ONCE_CTRL(x); r2 = READ_ONCE_CTRL(y); if (r1 > 0) if (r2 > 0) ACCESS_ONCE(y) = 1; ACCESS_ONCE(x) = 1; @@ -783,7 +787,8 @@ But because control dependencies do -not- provide transitivity, the above assertion can fail after the combined three-CPU example completes. If you need the three-CPU example to provide ordering, you will need smp_mb() between the loads and stores in the CPU 0 and CPU 1 code fragments, -that is, just before or just after the "if" statements. +that is, just before or just after the "if" statements. Furthermore, +the original two-CPU example is very fragile and should be avoided. These two examples are the LB and WWC litmus tests from this paper: http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this @@ -791,6 +796,12 @@ site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html. In summary: + (*) Control dependencies must be headed by READ_ONCE_CTRL(). + Or, as a much less preferable alternative, interpose + be headed by READ_ONCE() or an ACCESS_ONCE() read and must + have smp_read_barrier_depends() between this read and the + control-dependent write. + (*) Control dependencies can order prior loads against later stores. However, they do -not- guarantee any other sort of ordering: Not prior loads against later loads, nor prior stores against diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 867722591be2..5d66777914db 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -252,6 +252,22 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s #define WRITE_ONCE(x, val) \ ({ typeof(x) __val = (val); __write_once_size(&(x), &__val, sizeof(__val)); __val; }) +/** + * READ_ONCE_CTRL - Read a value heading a control dependency + * @x: The value to be read, heading the control dependency + * + * Control dependencies are tricky. See Documentation/memory-barriers.txt + * for important information on how to use them. Note that in many cases, + * use of smp_load_acquire() will be much simpler. Control dependencies + * should be avoided except on the hottest of hotpaths. + */ +#define READ_ONCE_CTRL(x) \ +({ \ + typeof(x) __val = READ_ONCE(x); \ + smp_read_barrier_depends(); /* Enforce control dependency. */ \ + __val; \ +}) + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c index 232f00f273cb..17fcb73c4a50 100644 --- a/kernel/events/ring_buffer.c +++ b/kernel/events/ring_buffer.c @@ -141,7 +141,7 @@ int perf_output_begin(struct perf_output_handle *handle, perf_output_get_handle(handle); do { - tail = ACCESS_ONCE(rb->user_page->data_tail); + tail = READ_ONCE_CTRL(rb->user_page->data_tail); offset = head = local_read(&rb->head); if (!rb->overwrite && unlikely(CIRC_SPACE(head, tail, perf_data_size(rb)) < size)) -- cgit v1.2.3 From 0f41c0ddadfb3d5baffe62351c380e2881aacd58 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Tue, 10 Mar 2015 18:33:20 -0700 Subject: rcu: Provide diagnostic option to slow down grace-period scans Grace-period scans of the rcu_node combining tree normally proceed quite quickly, so that it is very difficult to reproduce races against them. This commit therefore allows grace-period pre-initialization and cleanup to be artificially slowed down, increasing race-reproduction probability. A pair of pairs of new Kconfig parameters are provided, RCU_TORTURE_TEST_SLOW_PREINIT to enable the slowing down of propagating CPU-hotplug changes up the combining tree along with RCU_TORTURE_TEST_SLOW_PREINIT_DELAY to specify the delay in jiffies, and RCU_TORTURE_TEST_SLOW_CLEANUP to enable the slowing down of the end-of-grace-period cleanup scan along with RCU_TORTURE_TEST_SLOW_CLEANUP_DELAY to specify the delay in jiffies. Boot-time parameters named rcutree.gp_preinit_delay and rcutree.gp_cleanup_delay allow these delays to be specified at boot time. Signed-off-by: Paul E. McKenney --- Documentation/kernel-parameters.txt | 16 ++++++- kernel/rcu/tree.c | 29 ++++++++++-- lib/Kconfig.debug | 54 +++++++++++++++++++++- .../selftests/rcutorture/configs/rcu/CFcommon | 2 + 4 files changed, 93 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..10a4fb80c033 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2992,11 +2992,23 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Set maximum number of finished RCU callbacks to process in one batch. + rcutree.gp_cleanup_delay= [KNL] + Set the number of jiffies to delay each step of + RCU grace-period cleanup. This only has effect + when CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP is set. + rcutree.gp_init_delay= [KNL] Set the number of jiffies to delay each step of RCU grace-period initialization. This only has - effect when CONFIG_RCU_TORTURE_TEST_SLOW_INIT is - set. + effect when CONFIG_RCU_TORTURE_TEST_SLOW_INIT + is set. + + rcutree.gp_preinit_delay= [KNL] + Set the number of jiffies to delay each step of + RCU grace-period pre-initialization, that is, + the propagation of recent CPU-hotplug changes up + the rcu_node combining tree. This only has effect + when CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT is set. rcutree.rcu_fanout_leaf= [KNL] Increase the number of CPUs assigned to each diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 9b076b284695..2f3cb5513ca3 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -163,6 +163,14 @@ static int kthread_prio = CONFIG_RCU_KTHREAD_PRIO; module_param(kthread_prio, int, 0644); /* Delay in jiffies for grace-period initialization delays, debug only. */ + +#ifdef CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT +static int gp_preinit_delay = CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT_DELAY; +module_param(gp_preinit_delay, int, 0644); +#else /* #ifdef CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT */ +static const int gp_preinit_delay; +#endif /* #else #ifdef CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT */ + #ifdef CONFIG_RCU_TORTURE_TEST_SLOW_INIT static int gp_init_delay = CONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY; module_param(gp_init_delay, int, 0644); @@ -170,6 +178,13 @@ module_param(gp_init_delay, int, 0644); static const int gp_init_delay; #endif /* #else #ifdef CONFIG_RCU_TORTURE_TEST_SLOW_INIT */ +#ifdef CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP +static int gp_cleanup_delay = CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP_DELAY; +module_param(gp_cleanup_delay, int, 0644); +#else /* #ifdef CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP */ +static const int gp_cleanup_delay; +#endif /* #else #ifdef CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP */ + /* * Number of grace periods between delays, normalized by the duration of * the delay. The longer the the delay, the more the grace periods between @@ -1742,6 +1757,13 @@ static void note_gp_changes(struct rcu_state *rsp, struct rcu_data *rdp) rcu_gp_kthread_wake(rsp); } +static void rcu_gp_slow(struct rcu_state *rsp, int delay) +{ + if (delay > 0 && + !(rsp->gpnum % (rcu_num_nodes * PER_RCU_NODE_PERIOD * delay))) + schedule_timeout_uninterruptible(delay); +} + /* * Initialize a new grace period. Return 0 if no grace period required. */ @@ -1784,6 +1806,7 @@ static int rcu_gp_init(struct rcu_state *rsp) * will handle subsequent offline CPUs. */ rcu_for_each_leaf_node(rsp, rnp) { + rcu_gp_slow(rsp, gp_preinit_delay); raw_spin_lock_irq(&rnp->lock); smp_mb__after_unlock_lock(); if (rnp->qsmaskinit == rnp->qsmaskinitnext && @@ -1840,6 +1863,7 @@ static int rcu_gp_init(struct rcu_state *rsp) * process finishes, because this kthread handles both. */ rcu_for_each_node_breadth_first(rsp, rnp) { + rcu_gp_slow(rsp, gp_init_delay); raw_spin_lock_irq(&rnp->lock); smp_mb__after_unlock_lock(); rdp = this_cpu_ptr(rsp->rda); @@ -1857,10 +1881,6 @@ static int rcu_gp_init(struct rcu_state *rsp) raw_spin_unlock_irq(&rnp->lock); cond_resched_rcu_qs(); WRITE_ONCE(rsp->gp_activity, jiffies); - if (gp_init_delay > 0 && - !(rsp->gpnum % - (rcu_num_nodes * PER_RCU_NODE_PERIOD * gp_init_delay))) - schedule_timeout_uninterruptible(gp_init_delay); } return 1; @@ -1955,6 +1975,7 @@ static void rcu_gp_cleanup(struct rcu_state *rsp) raw_spin_unlock_irq(&rnp->lock); cond_resched_rcu_qs(); WRITE_ONCE(rsp->gp_activity, jiffies); + rcu_gp_slow(rsp, gp_cleanup_delay); } rnp = rcu_get_root(rsp); raw_spin_lock_irq(&rnp->lock); diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index ba2b0c87e65b..e1af93ae246b 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1261,12 +1261,38 @@ config RCU_TORTURE_TEST_RUNNABLE Say N here if you want the RCU torture tests to start only after being manually enabled via /proc. +config RCU_TORTURE_TEST_SLOW_PREINIT + bool "Slow down RCU grace-period pre-initialization to expose races" + depends on RCU_TORTURE_TEST + help + This option delays grace-period pre-initialization (the + propagation of CPU-hotplug changes up the rcu_node combining + tree) for a few jiffies between initializing each pair of + consecutive rcu_node structures. This helps to expose races + involving grace-period pre-initialization, in other words, it + makes your kernel less stable. It can also greatly increase + grace-period latency, especially on systems with large numbers + of CPUs. This is useful when torture-testing RCU, but in + almost no other circumstance. + + Say Y here if you want your system to crash and hang more often. + Say N if you want a sane system. + +config RCU_TORTURE_TEST_SLOW_PREINIT_DELAY + int "How much to slow down RCU grace-period pre-initialization" + range 0 5 + default 3 + depends on RCU_TORTURE_TEST_SLOW_PREINIT + help + This option specifies the number of jiffies to wait between + each rcu_node structure pre-initialization step. + config RCU_TORTURE_TEST_SLOW_INIT bool "Slow down RCU grace-period initialization to expose races" depends on RCU_TORTURE_TEST help - This option makes grace-period initialization block for a - few jiffies between initializing each pair of consecutive + This option delays grace-period initialization for a few + jiffies between initializing each pair of consecutive rcu_node structures. This helps to expose races involving grace-period initialization, in other words, it makes your kernel less stable. It can also greatly increase grace-period @@ -1286,6 +1312,30 @@ config RCU_TORTURE_TEST_SLOW_INIT_DELAY This option specifies the number of jiffies to wait between each rcu_node structure initialization. +config RCU_TORTURE_TEST_SLOW_CLEANUP + bool "Slow down RCU grace-period cleanup to expose races" + depends on RCU_TORTURE_TEST + help + This option delays grace-period cleanup for a few jiffies + between cleaning up each pair of consecutive rcu_node + structures. This helps to expose races involving grace-period + cleanup, in other words, it makes your kernel less stable. + It can also greatly increase grace-period latency, especially + on systems with large numbers of CPUs. This is useful when + torture-testing RCU, but in almost no other circumstance. + + Say Y here if you want your system to crash and hang more often. + Say N if you want a sane system. + +config RCU_TORTURE_TEST_SLOW_CLEANUP_DELAY + int "How much to slow down RCU grace-period cleanup" + range 0 5 + default 3 + depends on RCU_TORTURE_TEST_SLOW_CLEANUP + help + This option specifies the number of jiffies to wait between + each rcu_node structure cleanup operation. + config RCU_CPU_STALL_TIMEOUT int "RCU CPU stall timeout in seconds" depends on RCU_STALL_COMMON diff --git a/tools/testing/selftests/rcutorture/configs/rcu/CFcommon b/tools/testing/selftests/rcutorture/configs/rcu/CFcommon index 49701218dc62..f824b4c9d9d9 100644 --- a/tools/testing/selftests/rcutorture/configs/rcu/CFcommon +++ b/tools/testing/selftests/rcutorture/configs/rcu/CFcommon @@ -1,3 +1,5 @@ CONFIG_RCU_TORTURE_TEST=y CONFIG_PRINTK_TIME=y +CONFIG_RCU_TORTURE_TEST_SLOW_CLEANUP=y CONFIG_RCU_TORTURE_TEST_SLOW_INIT=y +CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT=y -- cgit v1.2.3 From 7fa270010e0ddd3693381431f373b3e3135b0695 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 20 Apr 2015 10:27:15 -0700 Subject: rcu: Convert CONFIG_RCU_FANOUT_EXACT to boot parameter The CONFIG_RCU_FANOUT_EXACT Kconfig parameter is used primarily (and perhaps only) by rcutorture to verify that RCU works correctly in specific rcu_node combining-tree configurations. It therefore does not make much sense have this as a question to people attempting to configure their kernels. So this commit creates an rcutree.rcu_fanout_exact= boot parameter that rcutorture can use, and eliminates the original CONFIG_RCU_FANOUT_EXACT Kconfig parameter. Reported-by: Ingo Molnar Signed-off-by: Paul E. McKenney Reviewed-by: Pranith Kumar --- Documentation/kernel-parameters.txt | 6 ++++++ init/Kconfig | 14 -------------- kernel/rcu/tree.c | 7 +++++-- kernel/rcu/tree_plugin.h | 2 +- 4 files changed, 12 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 10a4fb80c033..f5582dcdf80d 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -3010,6 +3010,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. the rcu_node combining tree. This only has effect when CONFIG_RCU_TORTURE_TEST_SLOW_PREINIT is set. + rcutree.rcu_fanout_exact= [KNL] + Disable autobalancing of the rcu_node combining + tree. This is used by rcutorture, and might + possibly be useful for architectures having high + cache-to-cache transfer latencies. + rcutree.rcu_fanout_leaf= [KNL] Increase the number of CPUs assigned to each leaf rcu_node structure. Useful for very large diff --git a/init/Kconfig b/init/Kconfig index 927210810189..0ec82362cfc0 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -611,20 +611,6 @@ config RCU_FANOUT_LEAF Take the default if unsure. -config RCU_FANOUT_EXACT - bool "Disable tree-based hierarchical RCU auto-balancing" - depends on TREE_RCU || PREEMPT_RCU - default n - help - This option forces use of the exact RCU_FANOUT value specified, - regardless of imbalances in the hierarchy. This is useful for - testing RCU itself, and might one day be useful on systems with - strong NUMA behavior. - - Without RCU_FANOUT_EXACT, the code will balance the hierarchy. - - Say N if unsure. - config RCU_FAST_NO_HZ bool "Accelerate last non-dyntick-idle CPU's grace periods" depends on NO_HZ_COMMON && SMP diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 2f3cb5513ca3..b49c474e1fff 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -113,6 +113,9 @@ RCU_STATE_INITIALIZER(rcu_bh, 'b', call_rcu_bh); static struct rcu_state *rcu_state_p; LIST_HEAD(rcu_struct_flavors); +/* Control rcu_node-tree auto-balancing at boot time. */ +static bool rcu_fanout_exact; +module_param(rcu_fanout_exact, bool, 0444); /* Increase (but not decrease) the CONFIG_RCU_FANOUT_LEAF at boot time. */ static int rcu_fanout_leaf = CONFIG_RCU_FANOUT_LEAF; module_param(rcu_fanout_leaf, int, 0444); @@ -3956,13 +3959,13 @@ void rcu_scheduler_starting(void) /* * Compute the per-level fanout, either using the exact fanout specified - * or balancing the tree, depending on CONFIG_RCU_FANOUT_EXACT. + * or balancing the tree, depending on the rcu_fanout_exact boot parameter. */ static void __init rcu_init_levelspread(struct rcu_state *rsp) { int i; - if (IS_ENABLED(CONFIG_RCU_FANOUT_EXACT)) { + if (rcu_fanout_exact) { rsp->levelspread[rcu_num_lvls - 1] = rcu_fanout_leaf; for (i = rcu_num_lvls - 2; i >= 0; i--) rsp->levelspread[i] = CONFIG_RCU_FANOUT; diff --git a/kernel/rcu/tree_plugin.h b/kernel/rcu/tree_plugin.h index 58b1ebdc4387..eb460ec747ef 100644 --- a/kernel/rcu/tree_plugin.h +++ b/kernel/rcu/tree_plugin.h @@ -64,7 +64,7 @@ static void __init rcu_bootup_announce_oddness(void) (!IS_ENABLED(CONFIG_64BIT) && CONFIG_RCU_FANOUT != 32)) pr_info("\tCONFIG_RCU_FANOUT set to non-default value of %d\n", CONFIG_RCU_FANOUT); - if (IS_ENABLED(CONFIG_RCU_FANOUT_EXACT)) + if (rcu_fanout_exact) pr_info("\tHierarchical RCU autobalancing is disabled.\n"); if (IS_ENABLED(CONFIG_RCU_FAST_NO_HZ)) pr_info("\tRCU dyntick-idle grace-period acceleration is enabled.\n"); -- cgit v1.2.3 From a3dc2948cec80f20a89e9b646d0c01b121e48e02 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 20 Apr 2015 11:40:50 -0700 Subject: rcu: Enable diagnostic dump of rcu_node combining tree The purpose of this commit is to make it easier to verify that RCU's combining tree is set up correctly, which is useful to have when making changes in how that tree is initialized. Signed-off-by: Paul E. McKenney Reviewed-by: Pranith Kumar [ paulmck: Fold fix found by Fengguang's 0-day test robot. ] --- Documentation/kernel-parameters.txt | 5 +++++ kernel/rcu/tree.c | 27 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index f5582dcdf80d..a1cb88d9864e 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2992,6 +2992,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Set maximum number of finished RCU callbacks to process in one batch. + rcutree.dump_tree= [KNL] + Dump the structure of the rcu_node combining tree + out at early boot. This is used for diagnostic + purposes, to verify correct tree setup. + rcutree.gp_cleanup_delay= [KNL] Set the number of jiffies to delay each step of RCU grace-period cleanup. This only has effect diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index b49c474e1fff..1bc14c670641 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -113,6 +113,9 @@ RCU_STATE_INITIALIZER(rcu_bh, 'b', call_rcu_bh); static struct rcu_state *rcu_state_p; LIST_HEAD(rcu_struct_flavors); +/* Dump rcu_node combining tree at boot to verify correct setup. */ +static bool dump_tree; +module_param(dump_tree, bool, 0444); /* Control rcu_node-tree auto-balancing at boot time. */ static bool rcu_fanout_exact; module_param(rcu_fanout_exact, bool, 0444); @@ -4144,6 +4147,28 @@ static void __init rcu_init_geometry(void) rcu_num_nodes -= n; } +/* + * Dump out the structure of the rcu_node combining tree associated + * with the rcu_state structure referenced by rsp. + */ +static void __init rcu_dump_rcu_node_tree(struct rcu_state *rsp) +{ + int level = 0; + struct rcu_node *rnp; + + pr_info("rcu_node tree layout dump\n"); + pr_info(" "); + rcu_for_each_node_breadth_first(rsp, rnp) { + if (rnp->level != level) { + pr_cont("\n"); + pr_info(" "); + level = rnp->level; + } + pr_cont("%d:%d ^%d ", rnp->grplo, rnp->grphi, rnp->grpnum); + } + pr_cont("\n"); +} + void __init rcu_init(void) { int cpu; @@ -4154,6 +4179,8 @@ void __init rcu_init(void) rcu_init_geometry(); rcu_init_one(&rcu_bh_state, &rcu_bh_data); rcu_init_one(&rcu_sched_state, &rcu_sched_data); + if (dump_tree) + rcu_dump_rcu_node_tree(&rcu_sched_state); __rcu_init_preempt(); open_softirq(RCU_SOFTIRQ, rcu_process_callbacks); -- cgit v1.2.3 From 3838cc1850ccd09f93e729e9047ec1995026f83e Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 12 Mar 2015 13:55:48 -0700 Subject: rcutorture: Allow negative values of nreaders to oversubscribe By default, with rcutorture.nreaders equal to -1, rcutorture provisions N-1 reader kthreads, where N is the number of CPUs. This avoids rcutorture-induced stalls, but also avoids heavier levels of torture. This commit therefore allows negative values of rcutorture.nreaders to specify larger numbers of reader kthreads, so that for example rcutorture.nreaders=-2 provisions N kthreads and rcutorture.nreaders=-5 provisions N+3 kthreads. Signed-off-by: Paul E. McKenney [ paulmck: Update documentation, as suggested by Josh Triplett. ] --- Documentation/kernel-parameters.txt | 6 +++++- kernel/rcu/rcutorture.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..04b811086dca 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -3101,7 +3101,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted. test, hence the "fake". rcutorture.nreaders= [KNL] - Set number of RCU readers. + Set number of RCU readers. The value -1 selects + N-1, where N is the number of CPUs. A value + "n" less than -1 selects N-n-2, where N is again + the number of CPUs. For example, -2 selects N + (the number of CPUs), -3 selects N+1, and so on. rcutorture.object_debug= [KNL] Enable debug-object double-call_rcu() testing. diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index a67ef6ff86b0..7294d605c481 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -1701,7 +1701,7 @@ rcu_torture_init(void) if (nreaders >= 0) { nrealreaders = nreaders; } else { - nrealreaders = num_online_cpus() - 1; + nrealreaders = num_online_cpus() - 2 - nreaders; if (nrealreaders <= 0) nrealreaders = 1; } -- cgit v1.2.3 From 0385d4464012f5b9a602311acfaa4902183d0ad5 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 21 Jul 2014 17:25:26 -0700 Subject: devicetree: cadence_ttc: Document binding for timer width Modern TTC implementations can extend the timer width to 32 bit. This feature is not self identifying so the driver needs to be made aware via device tree. Signed-off-by: Peter Crosthwaite Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt index 993695c659e1..eeee6cd51e5c 100644 --- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt +++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt @@ -6,6 +6,9 @@ Required properties: - interrupts : A list of 3 interrupts; one per timer channel. - clocks: phandle to the source clock +Optional properties: +- timer-width: Bit width of the timer, necessary if not 16. + Example: ttc0: ttc0@f8001000 { @@ -14,4 +17,5 @@ ttc0: ttc0@f8001000 { compatible = "cdns,ttc"; reg = <0xF8001000 0x1000>; clocks = <&cpu_clk 3>; + timer-width = <32>; }; -- cgit v1.2.3 From a6e86403d1acb562f7e6c3cd9edcdfdabe0305b2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 2 Oct 2014 12:36:45 +0200 Subject: PCI: xilinx: Trivial fix in DT example Good to have it properly describe for c&p cases. Signed-off-by: Michal Simek Acked-by: Mark Rutland --- Documentation/devicetree/bindings/pci/xilinx-pcie.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt index 3e2c88d97ad4..02f979a48aeb 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt @@ -58,5 +58,5 @@ Example: interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; - } + }; }; -- cgit v1.2.3 From f8266389c838e919adf941bd91d9cdd837503329 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 9 Apr 2015 08:22:41 +0200 Subject: of: Add vendor prefix for Ceva Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..cc5f529185d5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -40,6 +40,7 @@ calxeda Calxeda capella Capella Microsystems, Inc cavium Cavium, Inc. cdns Cadence Design Systems Inc. +ceva Ceva, Inc. chipidea Chipidea, Inc chipone ChipOne chipspark ChipSPARK -- cgit v1.2.3 From 8db087a72334ec40ca4f0c3dcf28444aea4dfe58 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 28 May 2015 09:49:49 -0700 Subject: of: Add vendor prefix for Toby Churchill Ltd. Toby Churchill Ltd is a global provider of assistive technology. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..86e842a58257 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -189,6 +189,7 @@ ste ST-Ericsson stericsson ST-Ericsson synology Synology, Inc. tbs TBS Technologies +tcl Toby Churchill Ltd. thine THine Electronics, Inc. ti Texas Instruments tlm Trusted Logic Mobility -- cgit v1.2.3 From a73e528ab1499505c29e14091b19cb041e20e038 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 27 May 2015 17:25:58 +0100 Subject: Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU This patch adds device-tree bindings for ARM SMMUv3 IOMMU devices. Cc: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Joerg Roedel --- .../devicetree/bindings/iommu/arm,smmu-v3.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt new file mode 100644 index 000000000000..c03eec116872 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -0,0 +1,37 @@ +* ARM SMMUv3 Architecture Implementation + +The SMMUv3 architecture is a significant deparature from previous +revisions, replacing the MMIO register interface with in-memory command +and event queues and adding support for the ATS and PRI components of +the PCIe specification. + +** SMMUv3 required properties: + +- compatible : Should include: + + * "arm,smmu-v3" for any SMMUv3 compliant + implementation. This entry should be last in the + compatible list. + +- reg : Base address and size of the SMMU. + +- interrupts : Non-secure interrupt list describing the wired + interrupt sources corresponding to entries in + interrupt-names. If no wired interrupts are + present then this property may be omitted. + +- interrupt-names : When the interrupts property is present, should + include the following: + * "eventq" - Event Queue not empty + * "priq" - PRI Queue not empty + * "cmdq-sync" - CMD_SYNC complete + * "gerror" - Global Error activated + +** SMMUv3 optional properties: + +- dma-coherent : Present if DMA operations made by the SMMU (page + table walks, stream table accesses etc) are cache + coherent with the CPU. + + NOTE: this only applies to the SMMU itself, not + masters connected upstream of the SMMU. -- cgit v1.2.3 From ee66e6a24bd2f8a294f018ab90f660f23d8a7ff5 Mon Sep 17 00:00:00 2001 From: Loc Ho Date: Fri, 22 May 2015 17:32:58 -0600 Subject: Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding Add documentation for the APM X-Gene SoC EDAC DTS binding. Signed-off-by: Loc Ho Acked-by: Arnd Bergmann Cc: devicetree@vger.kernel.org Cc: dougthompson@xmission.com Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac Cc: mark.rutland@arm.com Cc: mchehab@osg.samsung.com Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1432337580-3750-4-git-send-email-lho@apm.com Signed-off-by: Borislav Petkov --- .../devicetree/bindings/edac/apm-xgene-edac.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file mode 100644 index 000000000000..480911c38ff9 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt @@ -0,0 +1,78 @@ +* APM X-Gene SoC EDAC node + +EDAC node is defined to describe on-chip error detection and correction. +The follow error types are supported: + + memory controller - Memory controller + PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache + +The following section describes the EDAC DT node binding. + +Required properties: +- compatible : Shall be "apm,xgene-edac". +- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. +- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. +- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. +- regmap-efuse : Regmap of the PMD efuse resource. +- reg : First resource shall be the CPU bus (PCP) resource. +- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error + IRQ(s). + +Required properties for memory controller subnode: +- compatible : Shall be "apm,xgene-edac-mc". +- reg : First resource shall be the memory controller unit + (MCU) resource. +- memory-controller : Instance number of the memory controller. + +Required properties for PMD subnode: +- compatible : Shall be "apm,xgene-edac-pmd". +- reg : First resource shall be the PMD resource. +- pmd-controller : Instance number of the PMD controller. + +Example: + csw: csw@7e200000 { + compatible = "apm,xgene-csw", "syscon"; + reg = <0x0 0x7e200000 0x0 0x1000>; + }; + + mcba: mcba@7e700000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e700000 0x0 0x1000>; + }; + + mcbb: mcbb@7e720000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e720000 0x0 0x1000>; + }; + + efuse: efuse@1054a000 { + compatible = "apm,xgene-efuse", "syscon"; + reg = <0x0 0x1054a000 0x0 0x20>; + }; + + edac@78800000 { + compatible = "apm,xgene-edac"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + reg = <0x0 0x78800000 0x0 0x100>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + }; -- cgit v1.2.3 From a95791efa72a08d3824713a75235d0407c0715dc Mon Sep 17 00:00:00 2001 From: "Suzuki K. Poulose" Date: Tue, 26 May 2015 10:53:15 +0100 Subject: arm-cci: Add CCI-500 PMU support CCI-500 provides 8 event counters which can count any of the supported events independently. The PMU event id is a 9-bit value made of two parts. bits [8:5] - Source port 0x0-0x6 Slave Ports 0x8-0xD Master Ports 0xf Global Events to CCI 0x7,0xe Reserved bits [0:4] - Event code (specific to each type of port) The generic CCI-500 controlling interface remains the same with CCI-400. However there are some differences in the PMU event counters. - No cycle counter - Upto 8 counters(4 in CCI-400) - Each counter area is 64K(4K in CCI400) - The counter0 starts at offset 0x10000 from the base of CCI Cc: Punit Agrawal Cc: Mark Rutland Cc: Will Deacon Cc: devicetree@vger.kernel.org Signed-off-by: Suzuki K. Poulose Acked-by: Punit Agrawal Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/cci.txt | 4 +- drivers/bus/Kconfig | 14 +++ drivers/bus/arm-cci.c | 133 ++++++++++++++++++++++++++ 3 files changed, 150 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt index 3c5c631328d3..aef1d200a9b2 100644 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -31,8 +31,9 @@ specific to ARM. - compatible Usage: required Value type: - Definition: must be set to + Definition: must contain one of the following: "arm,cci-400" + "arm,cci-500" - reg Usage: required @@ -99,6 +100,7 @@ specific to ARM. "arm,cci-400-pmu,r1" "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has secure acces to CCI registers + "arm,cci-500-pmu,r0" - reg: Usage: required Value type: Integer cells. A register entry, expressed diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index a857936beac8..1a82f3a17681 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -34,6 +34,20 @@ config ARM_CCI400_PORT_CTRL Low level power management driver for CCI400 cache coherent interconnect for ARM platforms. +config ARM_CCI500_PMU + bool "ARM CCI500 PMU support" + default y + depends on (ARM && CPU_V7) || ARM64 + depends on PERF_EVENTS + select ARM_CCI_PMU + help + Support for PMU events monitoring on the ARM CCI-500 cache coherent + interconnect. CCI-500 provides 8 independent event counters, which + can count events pertaining to the slave/master interfaces as well + as the internal events to the CCI. + + If unsure, say Y + config ARM_CCN bool "ARM CCN driver support" depends on ARM || ARM64 diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index df1c2c61d304..1475eafbd25c 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -51,6 +51,9 @@ static const struct cci_nb_ports cci400_ports = { static const struct of_device_id arm_cci_matches[] = { #ifdef CONFIG_ARM_CCI400_COMMON {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA }, +#endif +#ifdef CONFIG_ARM_CCI500_PMU + { .compatible = "arm,cci-500", }, #endif {}, }; @@ -89,6 +92,9 @@ static const struct of_device_id arm_cci_matches[] = { enum { CCI_IF_SLAVE, CCI_IF_MASTER, +#ifdef CONFIG_ARM_CCI500_PMU + CCI_IF_GLOBAL, +#endif CCI_IF_MAX, }; @@ -144,6 +150,9 @@ enum cci_models { #ifdef CONFIG_ARM_CCI400_PMU CCI400_R0, CCI400_R1, +#endif +#ifdef CONFIG_ARM_CCI500_PMU + CCI500_R0, #endif CCI_MODEL_MAX }; @@ -294,6 +303,101 @@ static inline struct cci_pmu_model *probe_cci_model(struct platform_device *pdev } #endif /* CONFIG_ARM_CCI400_PMU */ +#ifdef CONFIG_ARM_CCI500_PMU + +/* + * CCI500 provides 8 independent event counters that can count + * any of the events available. + * + * CCI500 PMU event id is an 9-bit value made of two parts. + * bits [8:5] - Source for the event + * 0x0-0x6 - Slave interfaces + * 0x8-0xD - Master interfaces + * 0xf - Global Events + * 0x7,0xe - Reserved + * + * bits [4:0] - Event code (specific to type of interface) + */ + +/* Port ids */ +#define CCI500_PORT_S0 0x0 +#define CCI500_PORT_S1 0x1 +#define CCI500_PORT_S2 0x2 +#define CCI500_PORT_S3 0x3 +#define CCI500_PORT_S4 0x4 +#define CCI500_PORT_S5 0x5 +#define CCI500_PORT_S6 0x6 + +#define CCI500_PORT_M0 0x8 +#define CCI500_PORT_M1 0x9 +#define CCI500_PORT_M2 0xa +#define CCI500_PORT_M3 0xb +#define CCI500_PORT_M4 0xc +#define CCI500_PORT_M5 0xd + +#define CCI500_PORT_GLOBAL 0xf + +#define CCI500_PMU_EVENT_MASK 0x1ffUL +#define CCI500_PMU_EVENT_SOURCE_SHIFT 0x5 +#define CCI500_PMU_EVENT_SOURCE_MASK 0xf +#define CCI500_PMU_EVENT_CODE_SHIFT 0x0 +#define CCI500_PMU_EVENT_CODE_MASK 0x1f + +#define CCI500_PMU_EVENT_SOURCE(event) \ + ((event >> CCI500_PMU_EVENT_SOURCE_SHIFT) & CCI500_PMU_EVENT_SOURCE_MASK) +#define CCI500_PMU_EVENT_CODE(event) \ + ((event >> CCI500_PMU_EVENT_CODE_SHIFT) & CCI500_PMU_EVENT_CODE_MASK) + +#define CCI500_SLAVE_PORT_MIN_EV 0x00 +#define CCI500_SLAVE_PORT_MAX_EV 0x1f +#define CCI500_MASTER_PORT_MIN_EV 0x00 +#define CCI500_MASTER_PORT_MAX_EV 0x06 +#define CCI500_GLOBAL_PORT_MIN_EV 0x00 +#define CCI500_GLOBAL_PORT_MAX_EV 0x0f + +static int cci500_validate_hw_event(struct cci_pmu *cci_pmu, + unsigned long hw_event) +{ + u32 ev_source = CCI500_PMU_EVENT_SOURCE(hw_event); + u32 ev_code = CCI500_PMU_EVENT_CODE(hw_event); + int if_type; + + if (hw_event & ~CCI500_PMU_EVENT_MASK) + return -ENOENT; + + switch (ev_source) { + case CCI500_PORT_S0: + case CCI500_PORT_S1: + case CCI500_PORT_S2: + case CCI500_PORT_S3: + case CCI500_PORT_S4: + case CCI500_PORT_S5: + case CCI500_PORT_S6: + if_type = CCI_IF_SLAVE; + break; + case CCI500_PORT_M0: + case CCI500_PORT_M1: + case CCI500_PORT_M2: + case CCI500_PORT_M3: + case CCI500_PORT_M4: + case CCI500_PORT_M5: + if_type = CCI_IF_MASTER; + break; + case CCI500_PORT_GLOBAL: + if_type = CCI_IF_GLOBAL; + break; + default: + return -ENOENT; + } + + if (ev_code >= cci_pmu->model->event_ranges[if_type].min && + ev_code <= cci_pmu->model->event_ranges[if_type].max) + return hw_event; + + return -ENOENT; +} +#endif /* CONFIG_ARM_CCI500_PMU */ + static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx) { return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu); @@ -981,6 +1085,29 @@ static struct cci_pmu_model cci_pmu_models[] = { .get_event_idx = cci400_get_event_idx, }, #endif +#ifdef CONFIG_ARM_CCI500_PMU + [CCI500_R0] = { + .name = "CCI_500", + .fixed_hw_cntrs = 0, + .num_hw_cntrs = 8, + .cntr_size = SZ_64K, + .event_ranges = { + [CCI_IF_SLAVE] = { + CCI500_SLAVE_PORT_MIN_EV, + CCI500_SLAVE_PORT_MAX_EV, + }, + [CCI_IF_MASTER] = { + CCI500_MASTER_PORT_MIN_EV, + CCI500_MASTER_PORT_MAX_EV, + }, + [CCI_IF_GLOBAL] = { + CCI500_GLOBAL_PORT_MIN_EV, + CCI500_GLOBAL_PORT_MAX_EV, + }, + }, + .validate_hw_event = cci500_validate_hw_event, + }, +#endif }; static const struct of_device_id arm_cci_pmu_matches[] = { @@ -997,6 +1124,12 @@ static const struct of_device_id arm_cci_pmu_matches[] = { .compatible = "arm,cci-400-pmu,r1", .data = &cci_pmu_models[CCI400_R1], }, +#endif +#ifdef CONFIG_ARM_CCI500_PMU + { + .compatible = "arm,cci-500-pmu,r0", + .data = &cci_pmu_models[CCI500_R0], + }, #endif {}, }; -- cgit v1.2.3 From e7a9a5bbaa78e92e6b76bdb51d4c4f6da35c0812 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Thu, 16 Apr 2015 15:43:40 -0700 Subject: tps6507x.txt: Remove executable permission Documention text files shouldn't be executable. Signed-off-by: Joe Perches Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/mfd/tps6507x.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 Documentation/devicetree/bindings/mfd/tps6507x.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/tps6507x.txt b/Documentation/devicetree/bindings/mfd/tps6507x.txt old mode 100755 new mode 100644 -- cgit v1.2.3 From 0f4106b32f36165a4f40b6aad0372e02ff14cf34 Mon Sep 17 00:00:00 2001 From: Heinz Mauelshagen Date: Wed, 29 Apr 2015 14:03:07 +0200 Subject: dm raid: fixup documentation for discard support Remove comment above parse_raid_params() that claims "devices_handle_discard_safely" is a table line argument when it is actually is a module parameter. Also, backfill dm-raid target version 1.6.0 documentation. Signed-off-by: Heinz Mauelshagen Reviewed-by: Jonathan Brassow Signed-off-by: Mike Snitzer --- Documentation/device-mapper/dm-raid.txt | 1 + drivers/md/dm-raid.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/device-mapper/dm-raid.txt b/Documentation/device-mapper/dm-raid.txt index ef8ba9fa58c4..85b74b15fa9c 100644 --- a/Documentation/device-mapper/dm-raid.txt +++ b/Documentation/device-mapper/dm-raid.txt @@ -224,3 +224,4 @@ Version History New status (STATUSTYPE_INFO) fields: sync_action and mismatch_cnt. 1.5.1 Add ability to restore transiently failed devices on resume. 1.5.2 'mismatch_cnt' is zero unless [last_]sync_action is "check". +1.6.0 Add discard support (and devices_handle_discard_safely module param). diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c index 88e4c7f24986..423e42e9a1ad 100644 --- a/drivers/md/dm-raid.c +++ b/drivers/md/dm-raid.c @@ -477,8 +477,6 @@ too_many: * will form the "stripe" * [[no]sync] Force or prevent recovery of the * entire array - * [devices_handle_discard_safely] Allow discards on RAID4/5/6; useful if RAID - * member device(s) properly support TRIM/UNMAP * [rebuild ] Rebuild the drive indicated by the index * [daemon_sleep ] Time between bitmap daemon work to * clear bits -- cgit v1.2.3 From 0cf4503174c12025ac7ea61048cb7c1d4d1ed85c Mon Sep 17 00:00:00 2001 From: Heinz Mauelshagen Date: Wed, 29 Apr 2015 14:03:04 +0200 Subject: dm raid: add support for the MD RAID0 personality Add dm-raid access to the MD RAID0 personality to enable single zone striping. The following changes enable that access: - add type definition to raid_types array - make bitmap creation conditonal in super_validate(), because bitmaps are not allowed in raid0 - set rdev->sectors to the data image size in super_validate() to allow the raid0 personality to calculate the MD array size properly - use mdddev(un)lock() functions instead of direct mutex_(un)lock() (wrapped in here because it's a trivial change) - enhance raid_status() to always report full sync for raid0 so that userspace checks for 100% sync will succeed and allow for resize (and takeover/reshape once added in future paches) - enhance raid_resume() to not load bitmap in case of raid0 - add merge function to avoid data corruption (seen with readahead) that resulted from bio payloads that grew too large. This problem did not occur with the other raid levels because it either did not apply without striping (raid1) or was avoided via stripe caching. - raise version to 1.7.0 because of the raid0 API change Signed-off-by: Heinz Mauelshagen Reviewed-by: Jonathan Brassow Signed-off-by: Mike Snitzer --- Documentation/device-mapper/dm-raid.txt | 1 + drivers/md/dm-raid.c | 132 ++++++++++++++++++++------------ 2 files changed, 85 insertions(+), 48 deletions(-) (limited to 'Documentation') diff --git a/Documentation/device-mapper/dm-raid.txt b/Documentation/device-mapper/dm-raid.txt index 85b74b15fa9c..cb12af3b51c2 100644 --- a/Documentation/device-mapper/dm-raid.txt +++ b/Documentation/device-mapper/dm-raid.txt @@ -225,3 +225,4 @@ Version History 1.5.1 Add ability to restore transiently failed devices on resume. 1.5.2 'mismatch_cnt' is zero unless [last_]sync_action is "check". 1.6.0 Add discard support (and devices_handle_discard_safely module param). +1.7.0 Add support for MD RAID0 mappings. diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c index af49ddebaa62..2daa67793511 100644 --- a/drivers/md/dm-raid.c +++ b/drivers/md/dm-raid.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2010-2011 Neil Brown - * Copyright (C) 2010-2014 Red Hat, Inc. All rights reserved. + * Copyright (C) 2010-2015 Red Hat, Inc. All rights reserved. * * This file is released under the GPL. */ @@ -82,6 +82,7 @@ static struct raid_type { const unsigned level; /* RAID level. */ const unsigned algorithm; /* RAID algorithm. */ } raid_types[] = { + {"raid0", "RAID0 (striping)", 0, 2, 0, 0 /* NONE */}, {"raid1", "RAID1 (mirroring)", 0, 2, 1, 0 /* NONE */}, {"raid10", "RAID10 (striped mirrors)", 0, 2, 10, UINT_MAX /* Varies */}, {"raid4", "RAID4 (dedicated parity disk)", 1, 2, 5, ALGORITHM_PARITY_0}, @@ -719,7 +720,7 @@ static int parse_raid_params(struct raid_set *rs, char **argv, rs->md.layout = raid10_format_to_md_layout(raid10_format, raid10_copies); rs->md.new_layout = rs->md.layout; - } else if ((rs->raid_type->level > 1) && + } else if ((!rs->raid_type->level || rs->raid_type->level > 1) && sector_div(sectors_per_dev, (rs->md.raid_disks - rs->raid_type->parity_devs))) { rs->ti->error = "Target length not divisible by number of data devices"; @@ -1025,8 +1026,9 @@ static int super_init_validation(struct mddev *mddev, struct md_rdev *rdev) return 0; } -static int super_validate(struct mddev *mddev, struct md_rdev *rdev) +static int super_validate(struct raid_set *rs, struct md_rdev *rdev) { + struct mddev *mddev = &rs->md; struct dm_raid_superblock *sb = page_address(rdev->sb_page); /* @@ -1036,8 +1038,10 @@ static int super_validate(struct mddev *mddev, struct md_rdev *rdev) if (!mddev->events && super_init_validation(mddev, rdev)) return -EINVAL; - mddev->bitmap_info.offset = 4096 >> 9; /* Enable bitmap creation */ - rdev->mddev->bitmap_info.default_offset = 4096 >> 9; + /* Enable bitmap creation for RAID levels != 0 */ + mddev->bitmap_info.offset = (rs->raid_type->level) ? to_sector(4096) : 0; + rdev->mddev->bitmap_info.default_offset = mddev->bitmap_info.offset; + if (!test_bit(FirstUse, &rdev->flags)) { rdev->recovery_offset = le64_to_cpu(sb->disk_recovery_offset); if (rdev->recovery_offset != MaxSector) @@ -1081,6 +1085,8 @@ static int analyse_superblocks(struct dm_target *ti, struct raid_set *rs) * that the "sync" directive is disallowed during the * reshape. */ + rdev->sectors = to_sector(i_size_read(rdev->bdev->bd_inode)); + if (rs->ctr_flags & CTR_FLAG_SYNC) continue; @@ -1139,11 +1145,11 @@ static int analyse_superblocks(struct dm_target *ti, struct raid_set *rs) * validation for the remaining devices. */ ti->error = "Unable to assemble array: Invalid superblocks"; - if (super_validate(mddev, freshest)) + if (super_validate(rs, freshest)) return -EINVAL; rdev_for_each(rdev, mddev) - if ((rdev != freshest) && super_validate(mddev, rdev)) + if ((rdev != freshest) && super_validate(rs, rdev)) return -EINVAL; return 0; @@ -1281,10 +1287,11 @@ static int raid_ctr(struct dm_target *ti, unsigned argc, char **argv) */ configure_discard_support(ti, rs); - mutex_lock(&rs->md.reconfig_mutex); + /* Has to be held on running the array */ + mddev_lock_nointr(&rs->md); ret = md_run(&rs->md); rs->md.in_sync = 0; /* Assume already marked dirty */ - mutex_unlock(&rs->md.reconfig_mutex); + mddev_unlock(&rs->md); if (ret) { ti->error = "Fail to run raid array"; @@ -1367,34 +1374,40 @@ static void raid_status(struct dm_target *ti, status_type_t type, case STATUSTYPE_INFO: DMEMIT("%s %d ", rs->raid_type->name, rs->md.raid_disks); - if (test_bit(MD_RECOVERY_RUNNING, &rs->md.recovery)) - sync = rs->md.curr_resync_completed; - else - sync = rs->md.recovery_cp; - - if (sync >= rs->md.resync_max_sectors) { - /* - * Sync complete. - */ + if (rs->raid_type->level) { + if (test_bit(MD_RECOVERY_RUNNING, &rs->md.recovery)) + sync = rs->md.curr_resync_completed; + else + sync = rs->md.recovery_cp; + + if (sync >= rs->md.resync_max_sectors) { + /* + * Sync complete. + */ + array_in_sync = 1; + sync = rs->md.resync_max_sectors; + } else if (test_bit(MD_RECOVERY_REQUESTED, &rs->md.recovery)) { + /* + * If "check" or "repair" is occurring, the array has + * undergone and initial sync and the health characters + * should not be 'a' anymore. + */ + array_in_sync = 1; + } else { + /* + * The array may be doing an initial sync, or it may + * be rebuilding individual components. If all the + * devices are In_sync, then it is the array that is + * being initialized. + */ + for (i = 0; i < rs->md.raid_disks; i++) + if (!test_bit(In_sync, &rs->dev[i].rdev.flags)) + array_in_sync = 1; + } + } else { + /* RAID0 */ array_in_sync = 1; sync = rs->md.resync_max_sectors; - } else if (test_bit(MD_RECOVERY_REQUESTED, &rs->md.recovery)) { - /* - * If "check" or "repair" is occurring, the array has - * undergone and initial sync and the health characters - * should not be 'a' anymore. - */ - array_in_sync = 1; - } else { - /* - * The array may be doing an initial sync, or it may - * be rebuilding individual components. If all the - * devices are In_sync, then it is the array that is - * being initialized. - */ - for (i = 0; i < rs->md.raid_disks; i++) - if (!test_bit(In_sync, &rs->dev[i].rdev.flags)) - array_in_sync = 1; } /* @@ -1683,26 +1696,48 @@ static void raid_resume(struct dm_target *ti) { struct raid_set *rs = ti->private; - set_bit(MD_CHANGE_DEVS, &rs->md.flags); - if (!rs->bitmap_loaded) { - bitmap_load(&rs->md); - rs->bitmap_loaded = 1; - } else { - /* - * A secondary resume while the device is active. - * Take this opportunity to check whether any failed - * devices are reachable again. - */ - attempt_restore_of_faulty_devices(rs); + if (rs->raid_type->level) { + set_bit(MD_CHANGE_DEVS, &rs->md.flags); + + if (!rs->bitmap_loaded) { + bitmap_load(&rs->md); + rs->bitmap_loaded = 1; + } else { + /* + * A secondary resume while the device is active. + * Take this opportunity to check whether any failed + * devices are reachable again. + */ + attempt_restore_of_faulty_devices(rs); + } + + clear_bit(MD_RECOVERY_FROZEN, &rs->md.recovery); } - clear_bit(MD_RECOVERY_FROZEN, &rs->md.recovery); mddev_resume(&rs->md); } +static int raid_merge(struct dm_target *ti, struct bvec_merge_data *bvm, + struct bio_vec *biovec, int max_size) +{ + struct raid_set *rs = ti->private; + struct md_personality *pers = rs->md.pers; + + if (pers && pers->mergeable_bvec) + return min(max_size, pers->mergeable_bvec(&rs->md, bvm, biovec)); + + /* + * In case we can't request the personality because + * the raid set is not running yet + * + * -> return safe minimum + */ + return rs->md.chunk_sectors; +} + static struct target_type raid_target = { .name = "raid", - .version = {1, 6, 0}, + .version = {1, 7, 0}, .module = THIS_MODULE, .ctr = raid_ctr, .dtr = raid_dtr, @@ -1714,6 +1749,7 @@ static struct target_type raid_target = { .presuspend = raid_presuspend, .postsuspend = raid_postsuspend, .resume = raid_resume, + .merge = raid_merge, }; static int __init dm_raid_init(void) -- cgit v1.2.3 From 8770d0898af7f0f0a8e88ce702b02a9ca326254f Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Fri, 29 May 2015 21:32:11 +0200 Subject: ARM: dts: Fix n900 dts file to work around 4.1 touchscreen regression on n900 Fix dts to match what the Linux kernel expects. This works around touchscreen problems in 4.1 linux on Nokia n900. Signed-off-by: Pavel Machek Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt | 4 ++-- arch/arm/boot/dts/omap3-n900.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt index 4b641c7bf1c2..09089a6d69ed 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt @@ -32,8 +32,8 @@ Example: touchscreen-fuzz-x = <4>; touchscreen-fuzz-y = <7>; touchscreen-fuzz-pressure = <2>; - touchscreen-max-x = <4096>; - touchscreen-max-y = <4096>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; touchscreen-max-pressure = <2048>; ti,x-plate-ohms = <280>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 5c16145920ea..5f5e0f3d5b64 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -832,8 +832,8 @@ touchscreen-fuzz-x = <4>; touchscreen-fuzz-y = <7>; touchscreen-fuzz-pressure = <2>; - touchscreen-max-x = <4096>; - touchscreen-max-y = <4096>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; touchscreen-max-pressure = <2048>; ti,x-plate-ohms = <280>; -- cgit v1.2.3 From 3a9ad0b4fdcd57f775d3615004c8c64c021a9e7d Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Wed, 27 May 2015 17:23:51 -0700 Subject: PCI: Add pci_bus_addr_t David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows") fails to boot on sparc/T5-8: pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000) The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA addresses, i.e., bus addresses returned via the DMA API (dma_map_single(), etc.), while the PCI core assumed dma_addr_t could hold *any* bus address, including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that tripped over this mismatch. Add pci_bus_addr_t, which is wide enough to hold any PCI bus address, including both raw BAR values and DMA addresses. This will be 64 bits on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then dma_addr_t only needs to be wide enough to hold addresses from the DMA API. [bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at least as wide as dma_addr_t, documentation] Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows") Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB") Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231 Reported-by: David Ahern Tested-by: David Ahern Signed-off-by: Yinghai Lu Signed-off-by: Bjorn Helgaas Acked-by: David S. Miller CC: stable@vger.kernel.org # v3.19+ --- Documentation/DMA-API-HOWTO.txt | 29 +++++++++++++++++------------ Documentation/DMA-API.txt | 30 +++++++++++++++--------------- drivers/pci/Kconfig | 4 ++++ drivers/pci/bus.c | 10 +++++----- drivers/pci/probe.c | 12 ++++++------ include/linux/pci.h | 12 +++++++++--- include/linux/types.h | 12 ++++++++++-- 7 files changed, 66 insertions(+), 43 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DMA-API-HOWTO.txt b/Documentation/DMA-API-HOWTO.txt index 0f7afb2bb442..aef8cc5a677b 100644 --- a/Documentation/DMA-API-HOWTO.txt +++ b/Documentation/DMA-API-HOWTO.txt @@ -25,13 +25,18 @@ physical addresses. These are the addresses in /proc/iomem. The physical address is not directly useful to a driver; it must use ioremap() to map the space and produce a virtual address. -I/O devices use a third kind of address: a "bus address" or "DMA address". -If a device has registers at an MMIO address, or if it performs DMA to read -or write system memory, the addresses used by the device are bus addresses. -In some systems, bus addresses are identical to CPU physical addresses, but -in general they are not. IOMMUs and host bridges can produce arbitrary +I/O devices use a third kind of address: a "bus address". If a device has +registers at an MMIO address, or if it performs DMA to read or write system +memory, the addresses used by the device are bus addresses. In some +systems, bus addresses are identical to CPU physical addresses, but in +general they are not. IOMMUs and host bridges can produce arbitrary mappings between physical and bus addresses. +From a device's point of view, DMA uses the bus address space, but it may +be restricted to a subset of that space. For example, even if a system +supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU +so devices only need to use 32-bit DMA addresses. + Here's a picture and some examples: CPU CPU Bus @@ -72,11 +77,11 @@ can use virtual address X to access the buffer, but the device itself cannot because DMA doesn't go through the CPU virtual memory system. In some simple systems, the device can do DMA directly to physical address -Y. But in many others, there is IOMMU hardware that translates bus +Y. But in many others, there is IOMMU hardware that translates DMA addresses to physical addresses, e.g., it translates Z to Y. This is part of the reason for the DMA API: the driver can give a virtual address X to an interface like dma_map_single(), which sets up any required IOMMU -mapping and returns the bus address Z. The driver then tells the device to +mapping and returns the DMA address Z. The driver then tells the device to do DMA to Z, and the IOMMU maps it to the buffer at address Y in system RAM. @@ -98,7 +103,7 @@ First of all, you should make sure #include is in your driver, which provides the definition of dma_addr_t. This type -can hold any valid DMA or bus address for the platform and should be used +can hold any valid DMA address for the platform and should be used everywhere you hold a DMA address returned from the DMA mapping functions. What memory is DMA'able? @@ -316,7 +321,7 @@ There are two types of DMA mappings: Think of "consistent" as "synchronous" or "coherent". The current default is to return consistent memory in the low 32 - bits of the bus space. However, for future compatibility you should + bits of the DMA space. However, for future compatibility you should set the consistent mask even if this default is fine for your driver. @@ -403,7 +408,7 @@ dma_alloc_coherent() returns two values: the virtual address which you can use to access it from the CPU and dma_handle which you pass to the card. -The CPU virtual address and the DMA bus address are both +The CPU virtual address and the DMA address are both guaranteed to be aligned to the smallest PAGE_SIZE order which is greater than or equal to the requested size. This invariant exists (for example) to guarantee that if you allocate a chunk @@ -645,8 +650,8 @@ PLEASE NOTE: The 'nents' argument to the dma_unmap_sg call must be dma_map_sg call. Every dma_map_{single,sg}() call should have its dma_unmap_{single,sg}() -counterpart, because the bus address space is a shared resource and -you could render the machine unusable by consuming all bus addresses. +counterpart, because the DMA address space is a shared resource and +you could render the machine unusable by consuming all DMA addresses. If you need to use the same streaming DMA region multiple times and touch the data in between the DMA transfers, the buffer needs to be synced diff --git a/Documentation/DMA-API.txt b/Documentation/DMA-API.txt index 52088408668a..7eba542eff7c 100644 --- a/Documentation/DMA-API.txt +++ b/Documentation/DMA-API.txt @@ -18,10 +18,10 @@ Part I - dma_ API To get the dma_ API, you must #include . This provides dma_addr_t and the interfaces described below. -A dma_addr_t can hold any valid DMA or bus address for the platform. It -can be given to a device to use as a DMA source or target. A CPU cannot -reference a dma_addr_t directly because there may be translation between -its physical address space and the bus address space. +A dma_addr_t can hold any valid DMA address for the platform. It can be +given to a device to use as a DMA source or target. A CPU cannot reference +a dma_addr_t directly because there may be translation between its physical +address space and the DMA address space. Part Ia - Using large DMA-coherent buffers ------------------------------------------ @@ -42,7 +42,7 @@ It returns a pointer to the allocated region (in the processor's virtual address space) or NULL if the allocation failed. It also returns a which may be cast to an unsigned integer the -same width as the bus and given to the device as the bus address base of +same width as the bus and given to the device as the DMA address base of the region. Note: consistent memory can be expensive on some platforms, and the @@ -193,7 +193,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction direction) Maps a piece of processor virtual memory so it can be accessed by the -device and returns the bus address of the memory. +device and returns the DMA address of the memory. The direction for both APIs may be converted freely by casting. However the dma_ API uses a strongly typed enumerator for its @@ -212,20 +212,20 @@ contiguous piece of memory. For this reason, memory to be mapped by this API should be obtained from sources which guarantee it to be physically contiguous (like kmalloc). -Further, the bus address of the memory must be within the +Further, the DMA address of the memory must be within the dma_mask of the device (the dma_mask is a bit mask of the -addressable region for the device, i.e., if the bus address of -the memory ANDed with the dma_mask is still equal to the bus +addressable region for the device, i.e., if the DMA address of +the memory ANDed with the dma_mask is still equal to the DMA address, then the device can perform DMA to the memory). To ensure that the memory allocated by kmalloc is within the dma_mask, the driver may specify various platform-dependent flags to restrict -the bus address range of the allocation (e.g., on x86, GFP_DMA -guarantees to be within the first 16MB of available bus addresses, +the DMA address range of the allocation (e.g., on x86, GFP_DMA +guarantees to be within the first 16MB of available DMA addresses, as required by ISA devices). Note also that the above constraints on physical contiguity and dma_mask may not apply if the platform has an IOMMU (a device which -maps an I/O bus address to a physical memory address). However, to be +maps an I/O DMA address to a physical memory address). However, to be portable, device driver writers may *not* assume that such an IOMMU exists. @@ -296,7 +296,7 @@ reduce current DMA mapping usage or delay and try again later). dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction) -Returns: the number of bus address segments mapped (this may be shorter +Returns: the number of DMA address segments mapped (this may be shorter than passed in if some elements of the scatter/gather list are physically or virtually adjacent and an IOMMU maps them with a single entry). @@ -340,7 +340,7 @@ must be the same as those and passed in to the scatter/gather mapping API. Note: must be the number you passed in, *not* the number of -bus address entries returned. +DMA address entries returned. void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, @@ -507,7 +507,7 @@ it's asked for coherent memory for this device. phys_addr is the CPU physical address to which the memory is currently assigned (this will be ioremapped so the CPU can access the region). -device_addr is the bus address the device needs to be programmed +device_addr is the DMA address the device needs to be programmed with to actually address this memory (this will be handed out as the dma_addr_t in dma_alloc_coherent()). diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 7a8f1c5e65af..73de4efcbe6e 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -1,6 +1,10 @@ # # PCI configuration # +config PCI_BUS_ADDR_T_64BIT + def_bool y if (ARCH_DMA_ADDR_T_64BIT || 64BIT) + depends on PCI + config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 90fa3a78fb7c..6fbd3f2b5992 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -92,11 +92,11 @@ void pci_bus_remove_resources(struct pci_bus *bus) } static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL}; -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT +#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT static struct pci_bus_region pci_64_bit = {0, - (dma_addr_t) 0xffffffffffffffffULL}; -static struct pci_bus_region pci_high = {(dma_addr_t) 0x100000000ULL, - (dma_addr_t) 0xffffffffffffffffULL}; + (pci_bus_addr_t) 0xffffffffffffffffULL}; +static struct pci_bus_region pci_high = {(pci_bus_addr_t) 0x100000000ULL, + (pci_bus_addr_t) 0xffffffffffffffffULL}; #endif /* @@ -200,7 +200,7 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, resource_size_t), void *alignf_data) { -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT +#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT int rc; if (res->flags & IORESOURCE_MEM_64) { diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6675a7a1b9fc..c91185721345 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -254,8 +254,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, } if (res->flags & IORESOURCE_MEM_64) { - if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) && - sz64 > 0x100000000ULL) { + if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) + && sz64 > 0x100000000ULL) { res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; res->start = 0; res->end = 0; @@ -264,7 +264,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, goto out; } - if ((sizeof(dma_addr_t) < 8) && l) { + if ((sizeof(pci_bus_addr_t) < 8) && l) { /* Above 32-bit boundary; try to reallocate */ res->flags |= IORESOURCE_UNSET; res->start = 0; @@ -399,7 +399,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child) struct pci_dev *dev = child->self; u16 mem_base_lo, mem_limit_lo; u64 base64, limit64; - dma_addr_t base, limit; + pci_bus_addr_t base, limit; struct pci_bus_region region; struct resource *res; @@ -426,8 +426,8 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child) } } - base = (dma_addr_t) base64; - limit = (dma_addr_t) limit64; + base = (pci_bus_addr_t) base64; + limit = (pci_bus_addr_t) limit64; if (base != base64) { dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", diff --git a/include/linux/pci.h b/include/linux/pci.h index 353db8dc4c6e..956f74bad37a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -577,9 +577,15 @@ int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, int reg, int len, u32 val); +#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT +typedef u64 pci_bus_addr_t; +#else +typedef u32 pci_bus_addr_t; +#endif + struct pci_bus_region { - dma_addr_t start; - dma_addr_t end; + pci_bus_addr_t start; + pci_bus_addr_t end; }; struct pci_dynids { @@ -1128,7 +1134,7 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus, int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); -static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) +static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) { struct pci_bus_region region; diff --git a/include/linux/types.h b/include/linux/types.h index 59698be03490..8715287c3b1f 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -139,12 +139,20 @@ typedef unsigned long blkcnt_t; */ #define pgoff_t unsigned long -/* A dma_addr_t can hold any valid DMA or bus address for the platform */ +/* + * A dma_addr_t can hold any valid DMA address, i.e., any address returned + * by the DMA API. + * + * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 + * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, + * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, + * so they don't care about the size of the actual bus addresses. + */ #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT typedef u64 dma_addr_t; #else typedef u32 dma_addr_t; -#endif /* dma_addr_t */ +#endif typedef unsigned __bitwise__ gfp_t; typedef unsigned __bitwise__ fmode_t; -- cgit v1.2.3 From eb82b9062bfe1fb63917d122790f2de607b4b6eb Mon Sep 17 00:00:00 2001 From: Anda-Maria Nicolae Date: Fri, 29 May 2015 17:25:43 +0300 Subject: of: Add vendor prefix for Richtek Technology Corporation Signed-off-by: Anda-Maria Nicolae Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..7b8c1295fd90 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -161,6 +161,7 @@ ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation +richtek Richtek Technology Corporation ricoh Ricoh Co. Ltd. rockchip Fuzhou Rockchip Electronics Co., Ltd samsung Samsung Semiconductor -- cgit v1.2.3 From 21472a54a1243fe92161b5b70123dd442da3b4be Mon Sep 17 00:00:00 2001 From: Anda-Maria Nicolae Date: Fri, 29 May 2015 17:25:44 +0300 Subject: Documentation: devicetree: Add Richtek RT9455 bindings Signed-off-by: Anda-Maria Nicolae Reviewed-by: Krzysztof Kozlowski [added default values to optional properties] Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/rt9455_charger.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/rt9455_charger.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/rt9455_charger.txt b/Documentation/devicetree/bindings/power/rt9455_charger.txt new file mode 100644 index 000000000000..5d9ad5cf2c5a --- /dev/null +++ b/Documentation/devicetree/bindings/power/rt9455_charger.txt @@ -0,0 +1,48 @@ +Binding for Richtek rt9455 battery charger + +Required properties: +- compatible: it should contain one of the following: + "richtek,rt9455". +- reg: integer, i2c address of the device. +- interrupt-parent: the phandle for the interrupt controller that + services interrupts for this device. +- interrupts: interrupt mapping for GPIO IRQ, it should be + configured with IRQ_TYPE_LEVEL_LOW flag. +- richtek,output-charge-current: integer, output current from the charger to the + battery, in uA. +- richtek,end-of-charge-percentage: integer, percent of the output charge current. + When the current in constant-voltage phase drops + below output_charge_current x end-of-charge-percentage, + charge is terminated. +- richtek,battery-regulation-voltage: integer, maximum battery voltage in uV. +- richtek,boost-output-voltage: integer, maximum voltage provided to consumer + devices, when the charger is in boost mode, in uV. + +Optional properties: +- richtek,min-input-voltage-regulation: integer, input voltage level in uV, used to + decrease voltage level when the over current + of the input power source occurs. + This prevents input voltage drop due to insufficient + current provided by the power source. + Default: 4500000 uV (4.5V) +- richtek,avg-input-current-regulation: integer, input current value in uA drained by the + charger from the power source. + Default: 500000 uA (500mA) + +Example: + +rt9455@22 { + compatible = "richtek,rt9455"; + reg = <0x22>; + + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + richtek,output-charge-current = <500000>; + richtek,end-of-charge-percentage = <10>; + richtek,battery-regulation-voltage = <4200000>; + richtek,boost-output-voltage = <5050000>; + + richtek,min-input-voltage-regulation = <4500000>; + richtek,avg-input-current-regulation = <500000>; +}; -- cgit v1.2.3 From 39b9ce2c6c25c5aeb39d0502e714924333a8007a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 13:38:01 -0300 Subject: [media] DocBook: Update DVB supported standards at introduction The list of standards at the media docbook is incomplete, and it is mentioning that the DVB-S2 & friends is "currently being updated". That's wrong, as such update occurred back in 2008. So, provide a more complete list of supported standards and add a reference to the actual list. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media_api.tmpl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 03f9a1f8d413..60d0c877ea16 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -67,8 +67,9 @@ API used for digital TV and Internet reception via one of the several digital tv standards. While it is called as DVB API, in fact it covers several different video standards including - DVB-T, DVB-S, DVB-C and ATSC. The API is currently being updated - to document support also for DVB-S2, ISDB-T and ISDB-S. + DVB-T/T2, DVB-S/S2, DVB-C, ATSC, ISDB-T, ISDB-S,etc. The complete + list of supported standards can be found at + . The third part covers the Remote Controller API. The fourth part covers the Media Controller API. For additional information and for the latest development code, -- cgit v1.2.3 From 9f67bc5203fa327378a22d37a62c4ef26d861f15 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 13:39:48 -0300 Subject: [media] DocBook: add a note about the ALSA API The Docbook mistakenly makes to believe that all needed APIs for media devices are there. Add a note there pointing that some sub-devices are actually be controlled via ALSA API. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media_api.tmpl | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 60d0c877ea16..c71ebe3277b1 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -72,6 +72,9 @@ . The third part covers the Remote Controller API. The fourth part covers the Media Controller API. + It should also be noticed that a media device may also have audio + components, like mixers, PCM capture, PCM playback, etc, with + are controlled via ALSA API. For additional information and for the latest development code, see: http://linuxtv.org. For discussing improvements, reporting troubles, sending new drivers, etc, please mail to: Linux Media Mailing List (LMML).. -- cgit v1.2.3 From a1ef3eeabe5278ecbe758ba09d4605b64897c533 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 13:40:28 -0300 Subject: [media] DocBook: add drawing with a typical media device An illustration of what's considered a typical media device may help people to better understand the contents of the media infrastructure API docbook. So, add it. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/.gitignore | 1 + Documentation/DocBook/media/Makefile | 2 +- .../DocBook/media/typical_media_device.svg | 28 ++++++++++++++++++++++ Documentation/DocBook/media_api.tmpl | 16 ++++++++++++- 4 files changed, 45 insertions(+), 2 deletions(-) create mode 100644 Documentation/DocBook/media/.gitignore create mode 100644 Documentation/DocBook/media/typical_media_device.svg (limited to 'Documentation') diff --git a/Documentation/DocBook/media/.gitignore b/Documentation/DocBook/media/.gitignore new file mode 100644 index 000000000000..e461c585fde8 --- /dev/null +++ b/Documentation/DocBook/media/.gitignore @@ -0,0 +1 @@ +!*.svg diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index 8bf7c6191296..f2f57861f0c8 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -195,7 +195,7 @@ DVB_DOCUMENTED = \ # install_media_images = \ - $(Q)-cp $(OBJIMGFILES) $(MEDIA_SRC_DIR)/v4l/*.svg $(MEDIA_OBJ_DIR)/media_api + $(Q)-cp $(OBJIMGFILES) $(MEDIA_SRC_DIR)/*.svg $(MEDIA_SRC_DIR)/v4l/*.svg $(MEDIA_OBJ_DIR)/media_api $(MEDIA_OBJ_DIR)/%: $(MEDIA_SRC_DIR)/%.b64 $(Q)base64 -d $< >$@ diff --git a/Documentation/DocBook/media/typical_media_device.svg b/Documentation/DocBook/media/typical_media_device.svg new file mode 100644 index 000000000000..f0c82f72c4b6 --- /dev/null +++ b/Documentation/DocBook/media/typical_media_device.svg @@ -0,0 +1,28 @@ + +Audio decoder +Video decoder +Audio encoder +Button Key/IR input logic +EEPROM +Sensor +System Bus +Demux +Conditional Access Module +Video encoder +Radio / Analog TV +Digital TV +PS.: picture is not complete: other blocks may be present +Webcam +Processing blocks +Smartcard +TunerFM/TV +Satellite Equipment Control (SEC) +Demod +I2C Bus (control bus) +Digital TV Frontend + +CPU +PCI, USB, SPI, I2C, ... +Bridge + DMA + diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index c71ebe3277b1..d15c9c61e730 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -60,7 +60,21 @@ analog and digital TV receiver cards, AM/FM receiver cards, streaming capture and output devices, codec devices and remote controllers. - It is divided into four parts. + A typical media device hardware is shown at + . +
+ Typical Media Device + + + + + + Typical Media Device Block Diagram + + +
+ The media infrastructure API was designed to control such + devices. It is divided into four parts. The first part covers radio, video capture and output, cameras, analog TV devices and codecs. The second part covers the -- cgit v1.2.3 From 0b0f1a00564ebc76c9b070236fb182b133ba254e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 14:31:02 -0300 Subject: [media] DocBook: fix emphasis at the DVB documentation Currently, it is using 'role="tt"', but this is not defined at the DocBook 4.5 spec. The net result is that no emphasis happens. So, replace them to bold emphasis. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/audio.xml | 6 +++--- Documentation/DocBook/media/dvb/ca.xml | 4 ++-- Documentation/DocBook/media/dvb/demux.xml | 10 +++++----- Documentation/DocBook/media/dvb/frontend.xml | 4 ++-- Documentation/DocBook/media/dvb/intro.xml | 26 +++++++++++++------------- Documentation/DocBook/media/dvb/kdapi.xml | 4 ++-- Documentation/DocBook/media/dvb/net.xml | 4 ++-- Documentation/DocBook/media/dvb/video.xml | 10 +++++----- 8 files changed, 34 insertions(+), 34 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/audio.xml b/Documentation/DocBook/media/dvb/audio.xml index a7ea56c71a27..a853e5b81ec7 100644 --- a/Documentation/DocBook/media/dvb/audio.xml +++ b/Documentation/DocBook/media/dvb/audio.xml @@ -1,7 +1,7 @@ DVB Audio Device The DVB audio device controls the MPEG2 audio decoder of the DVB hardware. It -can be accessed through /dev/dvb/adapter0/audio0. Data types and and -ioctl definitions can be accessed by including linux/dvb/audio.h in your +can be accessed through /dev/dvb/adapter0/audio0. Data types and and +ioctl definitions can be accessed by including linux/dvb/audio.h in your application. Please note that some DVB cards don’t have their own MPEG decoder, which results in @@ -32,7 +32,7 @@ typedef enum { AUDIO_SOURCE_DEMUX selects the demultiplexer (fed either by the frontend or the DVR device) as the source of the video stream. If AUDIO_SOURCE_MEMORY -is selected the stream comes from the application through the write() system +is selected the stream comes from the application through the write() system call. diff --git a/Documentation/DocBook/media/dvb/ca.xml b/Documentation/DocBook/media/dvb/ca.xml index 85eaf4fe2931..bf9e790d674f 100644 --- a/Documentation/DocBook/media/dvb/ca.xml +++ b/Documentation/DocBook/media/dvb/ca.xml @@ -1,7 +1,7 @@ DVB CA Device The DVB CA device controls the conditional access hardware. It can be accessed through -/dev/dvb/adapter0/ca0. Data types and and ioctl definitions can be accessed by -including linux/dvb/ca.h in your application. +/dev/dvb/adapter0/ca0. Data types and and ioctl definitions can be accessed by +including linux/dvb/ca.h in your application.
diff --git a/Documentation/DocBook/media/dvb/demux.xml b/Documentation/DocBook/media/dvb/demux.xml index c8683d66f059..fae0e0556ca5 100644 --- a/Documentation/DocBook/media/dvb/demux.xml +++ b/Documentation/DocBook/media/dvb/demux.xml @@ -1,8 +1,8 @@ DVB Demux Device The DVB demux device controls the filters of the DVB hardware/software. It can be -accessed through /dev/adapter0/demux0. Data types and and ioctl definitions can be -accessed by including linux/dvb/dmx.h in your application. +accessed through /dev/adapter0/demux0. Data types and and ioctl definitions can be +accessed by including linux/dvb/dmx.h in your application.
Demux Data Types @@ -21,11 +21,11 @@ typedef enum DMX_OUT_TSDEMUX_TAP /⋆ Like TS_TAP but retrieved from the DMX device ⋆/ } dmx_output_t; -DMX_OUT_TAP delivers the stream output to the demux device on which the ioctl is +DMX_OUT_TAP delivers the stream output to the demux device on which the ioctl is called. -DMX_OUT_TS_TAP routes output to the logical DVR device /dev/dvb/adapter0/dvr0, -which delivers a TS multiplexed from all filters for which DMX_OUT_TS_TAP was +DMX_OUT_TS_TAP routes output to the logical DVR device /dev/dvb/adapter0/dvr0, +which delivers a TS multiplexed from all filters for which DMX_OUT_TS_TAP was specified.
diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 8a6a6ff27af5..956b8f6882e0 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -2,9 +2,9 @@ The DVB frontend device controls the tuner and DVB demodulator hardware. It can be accessed through /dev/dvb/adapter0/frontend0. Data types and and +role="bold">/dev/dvb/adapter0/frontend0. Data types and and ioctl definitions can be accessed by including linux/dvb/frontend.h in your application. +role="bold">linux/dvb/frontend.h in your application. DVB frontends come in three varieties: DVB-S (satellite), DVB-C (cable) and DVB-T (terrestrial). Transmission via the internet (DVB-IP) diff --git a/Documentation/DocBook/media/dvb/intro.xml b/Documentation/DocBook/media/dvb/intro.xml index 2048b53d19b9..4a34ef4783a4 100644 --- a/Documentation/DocBook/media/dvb/intro.xml +++ b/Documentation/DocBook/media/dvb/intro.xml @@ -129,41 +129,41 @@ hardware. It can depend on the individual security requirements of the platform, if and how many of the CA functions are made available to the application through this device. -All devices can be found in the /dev -tree under /dev/dvb. The individual devices +All devices can be found in the /dev +tree under /dev/dvb. The individual devices are called: -/dev/dvb/adapterN/audioM, +/dev/dvb/adapterN/audioM, -/dev/dvb/adapterN/videoM, +/dev/dvb/adapterN/videoM, -/dev/dvb/adapterN/frontendM, +/dev/dvb/adapterN/frontendM, -/dev/dvb/adapterN/netM, +/dev/dvb/adapterN/netM, -/dev/dvb/adapterN/demuxM, +/dev/dvb/adapterN/demuxM, -/dev/dvb/adapterN/dvrM, +/dev/dvb/adapterN/dvrM, -/dev/dvb/adapterN/caM, +/dev/dvb/adapterN/caM, where N enumerates the DVB PCI cards in a system starting from 0, and M enumerates the devices of each type within each adapter, starting from 0, too. We will omit the “/dev/dvb/adapterN/” in the further dicussion +role="bold">/dev/dvb/adapterN/” in the further dicussion of these devices. The naming scheme for the devices is the same wheter devfs is used or not. @@ -203,9 +203,9 @@ a partial path like: To enable applications to support different API version, an additional include file linux/dvb/version.h exists, which defines the -constant DVB_API_VERSION. This document -describes DVB_API_VERSION 5.8. +role="bold">linux/dvb/version.h exists, which defines the +constant DVB_API_VERSION. This document +describes DVB_API_VERSION 5.8.
diff --git a/Documentation/DocBook/media/dvb/kdapi.xml b/Documentation/DocBook/media/dvb/kdapi.xml index 6c11ec52cbee..f648115f7149 100644 --- a/Documentation/DocBook/media/dvb/kdapi.xml +++ b/Documentation/DocBook/media/dvb/kdapi.xml @@ -1,8 +1,8 @@ Kernel Demux API The kernel demux API defines a driver-internal interface for registering low-level, hardware specific driver to a hardware independent demux layer. It is only of interest for -DVB device driver writers. The header file for this API is named demux.h and located in -drivers/media/dvb-core. +DVB device driver writers. The header file for this API is named demux.h and located in +drivers/media/dvb-core. Maintainer note: This section must be reviewed. It is probably out of date. diff --git a/Documentation/DocBook/media/dvb/net.xml b/Documentation/DocBook/media/dvb/net.xml index a193e86941b5..d4ef21764959 100644 --- a/Documentation/DocBook/media/dvb/net.xml +++ b/Documentation/DocBook/media/dvb/net.xml @@ -1,8 +1,8 @@ DVB Network API The DVB net device enables feeding of MPE (multi protocol encapsulation) packets received via DVB into the Linux network protocol stack, e.g. for internet via satellite -applications. It can be accessed through /dev/dvb/adapter0/net0. Data types and -and ioctl definitions can be accessed by including linux/dvb/net.h in your +applications. It can be accessed through /dev/dvb/adapter0/net0. Data types and +and ioctl definitions can be accessed by including linux/dvb/net.h in your application.
diff --git a/Documentation/DocBook/media/dvb/video.xml b/Documentation/DocBook/media/dvb/video.xml index 3ea1ca7e785e..1ea786f9b798 100644 --- a/Documentation/DocBook/media/dvb/video.xml +++ b/Documentation/DocBook/media/dvb/video.xml @@ -1,12 +1,12 @@ DVB Video Device The DVB video device controls the MPEG2 video decoder of the DVB hardware. It -can be accessed through /dev/dvb/adapter0/video0. Data types and and -ioctl definitions can be accessed by including linux/dvb/video.h in your +can be accessed through /dev/dvb/adapter0/video0. Data types and and +ioctl definitions can be accessed by including linux/dvb/video.h in your application. Note that the DVB video device only controls decoding of the MPEG video stream, not its presentation on the TV or computer screen. On PCs this is typically handled by an -associated video4linux device, e.g. /dev/video, which allows scaling and defining output +associated video4linux device, e.g. /dev/video, which allows scaling and defining output windows. Some DVB cards don’t have their own MPEG decoder, which results in the omission of @@ -24,7 +24,7 @@ have been created to replace that functionality.
video_format_t -The video_format_t data type defined by +The video_format_t data type defined by typedef enum { @@ -74,7 +74,7 @@ typedef enum { VIDEO_SOURCE_DEMUX selects the demultiplexer (fed either by the frontend or the DVR device) as the source of the video stream. If VIDEO_SOURCE_MEMORY -is selected the stream comes from the application through the write() system +is selected the stream comes from the application through the write() system call.
-- cgit v1.2.3 From ee072ed7e3acaa2e09051535cbed5ce7a9247879 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 14:24:38 -0300 Subject: [media] DocBook: Improve DVB frontend description The DVB frontend API got bitrotten. Update it. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 46 ++++++++++++++++++---------- 1 file changed, 29 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 956b8f6882e0..98443c4c2818 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -1,21 +1,33 @@ DVB Frontend API -The DVB frontend device controls the tuner and DVB demodulator -hardware. It can be accessed through /dev/dvb/adapter0/frontend0. Data types and and -ioctl definitions can be accessed by including linux/dvb/frontend.h in your application. - -DVB frontends come in three varieties: DVB-S (satellite), DVB-C -(cable) and DVB-T (terrestrial). Transmission via the internet (DVB-IP) -is not yet handled by this API but a future extension is possible. For -DVB-S the frontend device also supports satellite equipment control -(SEC) via DiSEqC and V-SEC protocols. The DiSEqC (digital SEC) -specification is available from -Eutelsat. +The DVB frontend API was designed to support three types of delivery systems: + + Terrestrial systems: DVB-T, DVB-T2, ATSC, ATSC M/H, ISDB-T, DVB-H, DTMB, CMMB + Cable systems: DVB-C Annex A/C, ClearQAM (DVB-C Annex B), ISDB-C + Satellital systems: DVB-S, DVB-S2, DVB Turbo, ISDB-S, DSS + +The DVB frontend controls several sub-devices including: + + Tuner, + Digital TV demodulator + Low noise amplifier (LNA) + Satellite Equipment Control (SEC) hardware (only for Satellite). + +The frontend can be accessed through + /dev/dvb/adapter?/frontend?. Data types and + ioctl definitions can be accessed by including + linux/dvb/frontend.h in your application. + -Note that the DVB API may also be used for MPEG decoder-only PCI -cards, in which case there exists no frontend device. +NOTE: Transmission via the internet (DVB-IP) + is not yet handled by this API but a future extension is possible. +On Satellital systems, the API support for the Satellite Equipment Control + (SEC) allows to power control and to send/receive signals to control the + antenna subsystem, selecting the polarization and choosing the Intermediate + Frequency IF) of the Low Noise Block Converter Feed Horn (LNBf). It + supports the DiSEqC and V-SEC protocols. The DiSEqC (digital SEC) +specification is available at +Eutelsat.
Frontend Data Types @@ -23,8 +35,8 @@ cards, in which case there exists no frontend device.
Frontend type -For historical reasons, frontend types are named by the type of modulation used in -transmission. The fontend types are given by fe_type_t type, defined as: +For historical reasons, frontend types are named by the type of modulation + used in transmission. The fontend types are given by fe_type_t type, defined as:
Frontend types -- cgit v1.2.3 From a8d3e4b4d9298bdc36934a0b49a7d540d8eaf8f9 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 16:44:40 -0300 Subject: [media] DocBook: move DVBv3 frontend bits to a separate section Although the recommended usage is the DVBv5 API calls, the documentation doesn't make it clear about what's the recommended calls and what's legacy. So, move the legacy API bits to a separate xml, putting them into a new section. Please notice that more changes are needed, since some of the bits there are cross-referenced elsewhere. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 605 +-------------------- .../DocBook/media/dvb/frontend_legacy_api.xml | 603 ++++++++++++++++++++ 2 files changed, 618 insertions(+), 590 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/frontend_legacy_api.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 98443c4c2818..3b3973aee8eb 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -29,58 +29,6 @@ specification is available at Eutelsat. -
-Frontend Data Types - -
-Frontend type - -For historical reasons, frontend types are named by the type of modulation - used in transmission. The fontend types are given by fe_type_t type, defined as: - -
-Frontend types - - &cs-def; - - - fe_type - Description - DTV_DELIVERY_SYSTEM equivalent type - - - - - FE_QPSK - For DVB-S standard - SYS_DVBS - - - FE_QAM - For DVB-C annex A standard - SYS_DVBC_ANNEX_A - - - FE_OFDM - For DVB-T standard - SYS_DVBT - - - FE_ATSC - For ATSC standard (terrestrial) or for DVB-C Annex B (cable) used in US. - SYS_ATSC (terrestrial) or SYS_DVBC_ANNEX_B (cable) - -
- -Newer formats like DVB-S2, ISDB-T, ISDB-S and DVB-T2 are not described at the above, as they're -supported via the new FE_GET_PROPERTY/FE_GET_SET_PROPERTY ioctl's, using the DTV_DELIVERY_SYSTEM parameter. - - -The usage of this field is deprecated, as it doesn't report all supported standards, and -will provide an incomplete information for frontends that support multiple delivery systems. -Please use DTV_ENUM_DELSYS instead. - -
frontend capabilities @@ -157,6 +105,7 @@ a specific frontend type. };
+
diseqc slave reply @@ -258,90 +207,8 @@ typedef enum fe_status { recommended to reset DiSEqC, tone and parameters -
-
-frontend parameters -The kind of parameters passed to the frontend device for tuning depend on -the kind of hardware you are using. -The struct dvb_frontend_parameters uses an -union with specific per-system parameters. However, as newer delivery systems -required more data, the structure size weren't enough to fit, and just -extending its size would break the existing applications. So, those parameters -were replaced by the usage of -FE_GET_PROPERTY/FE_SET_PROPERTY ioctl's. The -new API is flexible enough to add new parameters to existing delivery systems, -and to add newer delivery systems. -So, newer applications should use -FE_GET_PROPERTY/FE_SET_PROPERTY instead, in -order to be able to support the newer System Delivery like DVB-S2, DVB-T2, -DVB-C2, ISDB, etc. -All kinds of parameters are combined as an union in the FrontendParameters structure: - -struct dvb_frontend_parameters { - uint32_t frequency; /⋆ (absolute) frequency in Hz for QAM/OFDM ⋆/ - /⋆ intermediate frequency in kHz for QPSK ⋆/ - fe_spectral_inversion_t inversion; - union { - struct dvb_qpsk_parameters qpsk; - struct dvb_qam_parameters qam; - struct dvb_ofdm_parameters ofdm; - struct dvb_vsb_parameters vsb; - } u; -}; - -In the case of QPSK frontends the frequency field specifies the intermediate -frequency, i.e. the offset which is effectively added to the local oscillator frequency (LOF) of -the LNB. The intermediate frequency has to be specified in units of kHz. For QAM and -OFDM frontends the frequency specifies the absolute frequency and is given in Hz. - - -
-QPSK parameters -For satellite QPSK frontends you have to use the dvb_qpsk_parameters structure: - - struct dvb_qpsk_parameters { - uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ - fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ - }; - -
-
-QAM parameters -for cable QAM frontend you use the dvb_qam_parameters structure: - - struct dvb_qam_parameters { - uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ - fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ - fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ - }; - -
-
-VSB parameters -ATSC frontends are supported by the dvb_vsb_parameters structure: - -struct dvb_vsb_parameters { - fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ -}; - -
-
-OFDM parameters -DVB-T frontends are supported by the dvb_ofdm_parameters structure: - - struct dvb_ofdm_parameters { - fe_bandwidth_t bandwidth; - fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ - fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ - fe_modulation_t constellation; /⋆ modulation type (see above) ⋆/ - fe_transmit_mode_t transmission_mode; - fe_guard_interval_t guard_interval; - fe_hierarchy_t hierarchy_information; - }; - -
frontend spectral inversion The Inversion field can take one of these values: @@ -358,6 +225,7 @@ typedef enum fe_spectral_inversion { itself.
+
frontend code rate The possible values for the fec_inner field used on @@ -384,6 +252,7 @@ typedef enum fe_code_rate { detection.
+
frontend modulation type for QAM, OFDM and VSB For cable and terrestrial frontends, e. g. for @@ -410,8 +279,10 @@ it needs to specify the quadrature modulation mode which can be one of the follo } fe_modulation_t;
+
More OFDM parameters +
Number of carriers per channel @@ -426,6 +297,7 @@ typedef enum fe_transmit_mode { } fe_transmit_mode_t;
+
frontend bandwidth @@ -440,6 +312,7 @@ typedef enum fe_bandwidth { } fe_bandwidth_t;
+
frontend guard inverval @@ -455,6 +328,7 @@ typedef enum fe_guard_interval { } fe_guard_interval_t;
+
frontend hierarchy @@ -466,23 +340,10 @@ typedef enum fe_hierarchy { HIERARCHY_AUTO } fe_hierarchy_t; -
-
-
-
-frontend events - - struct dvb_frontend_event { - fe_status_t status; - struct dvb_frontend_parameters parameters; - }; - -
-
Frontend Function Calls @@ -694,417 +555,6 @@ typedef enum fe_hierarchy {
-
-FE_READ_BER -DESCRIPTION - - -This ioctl call returns the bit error rate for the signal currently - received/demodulated by the front-end. For this command, read-only access to - the device is sufficient. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_READ_BER, - uint32_t ⋆ber); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_READ_BER for this command. - - -uint32_t *ber - -The bit error rate is stored into *ber. - - - -&return-value-dvb; -
- -
-FE_READ_SNR - -DESCRIPTION - - -This ioctl call returns the signal-to-noise ratio for the signal currently received - by the front-end. For this command, read-only access to the device is sufficient. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_READ_SNR, uint16_t - ⋆snr); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_READ_SNR for this command. - - -uint16_t *snr - -The signal-to-noise ratio is stored into *snr. - - - -&return-value-dvb; -
- -
-FE_READ_SIGNAL_STRENGTH -DESCRIPTION - - -This ioctl call returns the signal strength value for the signal currently received - by the front-end. For this command, read-only access to the device is sufficient. - - -SYNOPSIS - - -int ioctl( int fd, int request = - FE_READ_SIGNAL_STRENGTH, uint16_t ⋆strength); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_READ_SIGNAL_STRENGTH for this - command. - - -uint16_t *strength - -The signal strength value is stored into *strength. - - - -&return-value-dvb; -
- -
-FE_READ_UNCORRECTED_BLOCKS -DESCRIPTION - - -This ioctl call returns the number of uncorrected blocks detected by the device - driver during its lifetime. For meaningful measurements, the increment in block - count during a specific time interval should be calculated. For this command, - read-only access to the device is sufficient. - - -Note that the counter will wrap to zero after its maximum count has been - reached. - - -SYNOPSIS - - -int ioctl( int fd, int request = - FE_READ_UNCORRECTED_BLOCKS, uint32_t ⋆ublocks); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_READ_UNCORRECTED_BLOCKS for this - command. - - -uint32_t *ublocks - -The total number of uncorrected blocks seen by the driver - so far. - - - -&return-value-dvb; -
- -
-FE_SET_FRONTEND -DESCRIPTION - - -This ioctl call starts a tuning operation using specified parameters. The result - of this call will be successful if the parameters were valid and the tuning could - be initiated. The result of the tuning operation in itself, however, will arrive - asynchronously as an event (see documentation for FE_GET_EVENT and - FrontendEvent.) If a new FE_SET_FRONTEND operation is initiated before - the previous one was completed, the previous operation will be aborted in favor - of the new one. This command requires read/write access to the device. - - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_SET_FRONTEND, - struct dvb_frontend_parameters ⋆p); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_SET_FRONTEND for this command. - - -struct - dvb_frontend_parameters - *p - -Points to parameters for tuning operation. - - - -&return-value-dvb; - -EINVAL - -Maximum supported symbol rate reached. - - -
- -
-FE_GET_FRONTEND -DESCRIPTION - - -This ioctl call queries the currently effective frontend parameters. For this - command, read-only access to the device is sufficient. - - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_GET_FRONTEND, - struct dvb_frontend_parameters ⋆p); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_SET_FRONTEND for this command. - - -struct - dvb_frontend_parameters - *p - -Points to parameters for tuning operation. - - - -&return-value-dvb; - -EINVAL - -Maximum supported symbol rate reached. - - - -
- -
-FE_GET_EVENT -DESCRIPTION - - -This ioctl call returns a frontend event if available. If an event is not - available, the behavior depends on whether the device is in blocking or - non-blocking mode. In the latter case, the call fails immediately with errno - set to EWOULDBLOCK. In the former case, the call blocks until an event - becomes available. - - -The standard Linux poll() and/or select() system calls can be used with the - device file descriptor to watch for new events. For select(), the file descriptor - should be included in the exceptfds argument, and for poll(), POLLPRI should - be specified as the wake-up condition. Since the event queue allocated is - rather small (room for 8 events), the queue must be serviced regularly to avoid - overflow. If an overflow happens, the oldest event is discarded from the queue, - and an error (EOVERFLOW) occurs the next time the queue is read. After - reporting the error condition in this fashion, subsequent - FE_GET_EVENT - calls will return events from the queue as usual. - - -For the sake of implementation simplicity, this command requires read/write - access to the device. - - - -SYNOPSIS - - -int ioctl(int fd, int request = QPSK_GET_EVENT, - struct dvb_frontend_event ⋆ev); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_GET_EVENT for this command. - - -struct - dvb_frontend_event - *ev - -Points to the location where the event, - - - -if any, is to be stored. - - - -&return-value-dvb; - -EWOULDBLOCK - -There is no event pending, and the device is in - non-blocking mode. - - -EOVERFLOW - -Overflow in event queue - one or more events were lost. - - -
-
FE_GET_INFO DESCRIPTION @@ -1521,40 +971,15 @@ FE_TUNE_MODE_ONESHOT When set, this flag will disable any zigzagging or other "n &return-value-dvb;
-
- FE_DISHNETWORK_SEND_LEGACY_CMD -DESCRIPTION - - -WARNING: This is a very obscure legacy command, used only at stv0299 driver. Should not be used on newer drivers. -It provides a non-standard method for selecting Diseqc voltage on the frontend, for Dish Network legacy switches. -As support for this ioctl were added in 2004, this means that such dishes were already legacy in 2004. - - - -SYNOPSIS - - -int ioctl(int fd, int request = - FE_DISHNETWORK_SEND_LEGACY_CMD, unsigned long cmd); - - - -PARAMETERS - - - unsigned long cmd - - - -sends the specified raw cmd to the dish via DISEqC. - - - - -&return-value-dvb;
+
+DVB Frontend legacy API (a. k. a. DVBv3) +The usage of this API is deprecated, as it doesn't support all digital + TV standards, doesn't provide good statistics measurements and provides + incomplete information. This is kept only to support legacy applications. + +&sub-frontend_legacy_api;
&sub-dvbproperty; diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml new file mode 100644 index 000000000000..f4d300488d12 --- /dev/null +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -0,0 +1,603 @@ +
+Frontend Legacy Data Types + +
+Frontend type + +For historical reasons, frontend types are named by the type of modulation + used in transmission. The fontend types are given by fe_type_t type, defined as: + + +Frontend types + + &cs-def; + + + fe_type + Description + DTV_DELIVERY_SYSTEM equivalent type + + + + + FE_QPSK + For DVB-S standard + SYS_DVBS + + + FE_QAM + For DVB-C annex A standard + SYS_DVBC_ANNEX_A + + + FE_OFDM + For DVB-T standard + SYS_DVBT + + + FE_ATSC + For ATSC standard (terrestrial) or for DVB-C Annex B (cable) used in US. + SYS_ATSC (terrestrial) or SYS_DVBC_ANNEX_B (cable) + +
+ +Newer formats like DVB-S2, ISDB-T, ISDB-S and DVB-T2 are not described at the above, as they're +supported via the new FE_GET_PROPERTY/FE_GET_SET_PROPERTY ioctl's, using the DTV_DELIVERY_SYSTEM parameter. + + +The usage of this field is deprecated, as it doesn't report all supported standards, and +will provide an incomplete information for frontends that support multiple delivery systems. +Please use DTV_ENUM_DELSYS instead. +
+ + +
+frontend parameters +The kind of parameters passed to the frontend device for tuning depend on +the kind of hardware you are using. +The struct dvb_frontend_parameters uses an +union with specific per-system parameters. However, as newer delivery systems +required more data, the structure size weren't enough to fit, and just +extending its size would break the existing applications. So, those parameters +were replaced by the usage of +FE_GET_PROPERTY/FE_SET_PROPERTY ioctl's. The +new API is flexible enough to add new parameters to existing delivery systems, +and to add newer delivery systems. +So, newer applications should use +FE_GET_PROPERTY/FE_SET_PROPERTY instead, in +order to be able to support the newer System Delivery like DVB-S2, DVB-T2, +DVB-C2, ISDB, etc. +All kinds of parameters are combined as an union in the FrontendParameters structure: + +struct dvb_frontend_parameters { + uint32_t frequency; /⋆ (absolute) frequency in Hz for QAM/OFDM ⋆/ + /⋆ intermediate frequency in kHz for QPSK ⋆/ + fe_spectral_inversion_t inversion; + union { + struct dvb_qpsk_parameters qpsk; + struct dvb_qam_parameters qam; + struct dvb_ofdm_parameters ofdm; + struct dvb_vsb_parameters vsb; + } u; +}; + +In the case of QPSK frontends the frequency field specifies the intermediate +frequency, i.e. the offset which is effectively added to the local oscillator frequency (LOF) of +the LNB. The intermediate frequency has to be specified in units of kHz. For QAM and +OFDM frontends the frequency specifies the absolute frequency and is given in Hz. + + +
+QPSK parameters +For satellite QPSK frontends you have to use the dvb_qpsk_parameters structure: + + struct dvb_qpsk_parameters { + uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ + fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ + }; + +
+ +
+QAM parameters +for cable QAM frontend you use the dvb_qam_parameters structure: + + struct dvb_qam_parameters { + uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ + fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ + fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ + }; + +
+ +
+VSB parameters +ATSC frontends are supported by the dvb_vsb_parameters structure: + +struct dvb_vsb_parameters { + fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ +}; + +
+ +
+OFDM parameters +DVB-T frontends are supported by the dvb_ofdm_parameters structure: + + struct dvb_ofdm_parameters { + fe_bandwidth_t bandwidth; + fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ + fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ + fe_modulation_t constellation; /⋆ modulation type (see above) ⋆/ + fe_transmit_mode_t transmission_mode; + fe_guard_interval_t guard_interval; + fe_hierarchy_t hierarchy_information; + }; + +
+
+ +
+frontend events + + struct dvb_frontend_event { + fe_status_t status; + struct dvb_frontend_parameters parameters; + }; + +
+
+ +
+Frontend Legacy Function Calls + +Those functions are defined at DVB version 3. The support is kept in + the kernel due to compatibility issues only. Their usage is strongly + not recommended + +
+FE_READ_BER +DESCRIPTION + + +This ioctl call returns the bit error rate for the signal currently + received/demodulated by the front-end. For this command, read-only access to + the device is sufficient. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_READ_BER, + uint32_t ⋆ber); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_BER for this command. + + +uint32_t *ber + +The bit error rate is stored into *ber. + + + +&return-value-dvb; +
+ +
+FE_READ_SNR + +DESCRIPTION + + +This ioctl call returns the signal-to-noise ratio for the signal currently received + by the front-end. For this command, read-only access to the device is sufficient. + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_READ_SNR, uint16_t + ⋆snr); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_SNR for this command. + + +uint16_t *snr + +The signal-to-noise ratio is stored into *snr. + + + +&return-value-dvb; +
+ +
+FE_READ_SIGNAL_STRENGTH +DESCRIPTION + + +This ioctl call returns the signal strength value for the signal currently received + by the front-end. For this command, read-only access to the device is sufficient. + + +SYNOPSIS + + +int ioctl( int fd, int request = + FE_READ_SIGNAL_STRENGTH, uint16_t ⋆strength); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_SIGNAL_STRENGTH for this + command. + + +uint16_t *strength + +The signal strength value is stored into *strength. + + + +&return-value-dvb; +
+ +
+FE_READ_UNCORRECTED_BLOCKS +DESCRIPTION + + +This ioctl call returns the number of uncorrected blocks detected by the device + driver during its lifetime. For meaningful measurements, the increment in block + count during a specific time interval should be calculated. For this command, + read-only access to the device is sufficient. + + +Note that the counter will wrap to zero after its maximum count has been + reached. + + +SYNOPSIS + + +int ioctl( int fd, int request = + FE_READ_UNCORRECTED_BLOCKS, uint32_t ⋆ublocks); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_READ_UNCORRECTED_BLOCKS for this + command. + + +uint32_t *ublocks + +The total number of uncorrected blocks seen by the driver + so far. + + + +&return-value-dvb; +
+ +
+FE_SET_FRONTEND +DESCRIPTION + + +This ioctl call starts a tuning operation using specified parameters. The result + of this call will be successful if the parameters were valid and the tuning could + be initiated. The result of the tuning operation in itself, however, will arrive + asynchronously as an event (see documentation for FE_GET_EVENT and + FrontendEvent.) If a new FE_SET_FRONTEND operation is initiated before + the previous one was completed, the previous operation will be aborted in favor + of the new one. This command requires read/write access to the device. + + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_SET_FRONTEND, + struct dvb_frontend_parameters ⋆p); + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_FRONTEND for this command. + + +struct + dvb_frontend_parameters + *p + +Points to parameters for tuning operation. + + + +&return-value-dvb; + +EINVAL + +Maximum supported symbol rate reached. + + +
+ +
+FE_GET_FRONTEND +DESCRIPTION + + +This ioctl call queries the currently effective frontend parameters. For this + command, read-only access to the device is sufficient. + + + +SYNOPSIS + + +int ioctl(int fd, int request = FE_GET_FRONTEND, + struct dvb_frontend_parameters ⋆p); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_SET_FRONTEND for this command. + + +struct + dvb_frontend_parameters + *p + +Points to parameters for tuning operation. + + + +&return-value-dvb; + +EINVAL + +Maximum supported symbol rate reached. + + + +
+ +
+FE_GET_EVENT +DESCRIPTION + + +This ioctl call returns a frontend event if available. If an event is not + available, the behavior depends on whether the device is in blocking or + non-blocking mode. In the latter case, the call fails immediately with errno + set to EWOULDBLOCK. In the former case, the call blocks until an event + becomes available. + + +The standard Linux poll() and/or select() system calls can be used with the + device file descriptor to watch for new events. For select(), the file descriptor + should be included in the exceptfds argument, and for poll(), POLLPRI should + be specified as the wake-up condition. Since the event queue allocated is + rather small (room for 8 events), the queue must be serviced regularly to avoid + overflow. If an overflow happens, the oldest event is discarded from the queue, + and an error (EOVERFLOW) occurs the next time the queue is read. After + reporting the error condition in this fashion, subsequent + FE_GET_EVENT + calls will return events from the queue as usual. + + +For the sake of implementation simplicity, this command requires read/write + access to the device. + + + +SYNOPSIS + + +int ioctl(int fd, int request = QPSK_GET_EVENT, + struct dvb_frontend_event ⋆ev); + + + +PARAMETERS + + +int fd + +File descriptor returned by a previous call to open(). + + +int request + +Equals FE_GET_EVENT for this command. + + +struct + dvb_frontend_event + *ev + +Points to the location where the event, + + + +if any, is to be stored. + + + +&return-value-dvb; + +EWOULDBLOCK + +There is no event pending, and the device is in + non-blocking mode. + + +EOVERFLOW + +Overflow in event queue - one or more events were lost. + + +
+ +
+ FE_DISHNETWORK_SEND_LEGACY_CMD +DESCRIPTION + + +WARNING: This is a very obscure legacy command, used only at stv0299 driver. Should not be used on newer drivers. +It provides a non-standard method for selecting Diseqc voltage on the frontend, for Dish Network legacy switches. +As support for this ioctl were added in 2004, this means that such dishes were already legacy in 2004. + + + +SYNOPSIS + + +int ioctl(int fd, int request = + FE_DISHNETWORK_SEND_LEGACY_CMD, unsigned long cmd); + + + +PARAMETERS + + + unsigned long cmd + + + +sends the specified raw cmd to the dish via DISEqC. + + + + +&return-value-dvb; +
+ +
-- cgit v1.2.3 From bb38c5474e306380c5832625d2178f3005358655 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 25 May 2015 22:56:03 -0300 Subject: [media] DocBook: reformat FE_GET_INFO ioctl documentation The DVB part of the docbook has a completely different format than the V4L2 part, as it was written as a separate document. As the V4L2 documentation is on better shape, and its format allows adding more information, let's use it for FE_GET_INFO and gradually update the non-legacy DVB ioctls using the new format. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 374 +++++++++++++++++++-------- 1 file changed, 267 insertions(+), 107 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 3b3973aee8eb..e8032127886b 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -29,70 +29,279 @@ specification is available at Eutelsat. -
-frontend capabilities -Capabilities describe what a frontend can do. Some capabilities can only be supported for -a specific frontend type. - - typedef enum fe_caps { - FE_IS_STUPID = 0, - FE_CAN_INVERSION_AUTO = 0x1, - FE_CAN_FEC_1_2 = 0x2, - FE_CAN_FEC_2_3 = 0x4, - FE_CAN_FEC_3_4 = 0x8, - FE_CAN_FEC_4_5 = 0x10, - FE_CAN_FEC_5_6 = 0x20, - FE_CAN_FEC_6_7 = 0x40, - FE_CAN_FEC_7_8 = 0x80, - FE_CAN_FEC_8_9 = 0x100, - FE_CAN_FEC_AUTO = 0x200, - FE_CAN_QPSK = 0x400, - FE_CAN_QAM_16 = 0x800, - FE_CAN_QAM_32 = 0x1000, - FE_CAN_QAM_64 = 0x2000, - FE_CAN_QAM_128 = 0x4000, - FE_CAN_QAM_256 = 0x8000, - FE_CAN_QAM_AUTO = 0x10000, - FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000, - FE_CAN_BANDWIDTH_AUTO = 0x40000, - FE_CAN_GUARD_INTERVAL_AUTO = 0x80000, - FE_CAN_HIERARCHY_AUTO = 0x100000, - FE_CAN_8VSB = 0x200000, - FE_CAN_16VSB = 0x400000, - FE_HAS_EXTENDED_CAPS = 0x800000, - FE_CAN_MULTISTREAM = 0x4000000, - FE_CAN_TURBO_FEC = 0x8000000, - FE_CAN_2G_MODULATION = 0x10000000, - FE_NEEDS_BENDING = 0x20000000, - FE_CAN_RECOVER = 0x40000000, - FE_CAN_MUTE_TS = 0x80000000 - } fe_caps_t; - -
- -
-frontend information +
+Querying frontend information Information about the frontend ca be queried with FE_GET_INFO. +
- - struct dvb_frontend_info { - char name[128]; - fe_type_t type; - uint32_t frequency_min; - uint32_t frequency_max; - uint32_t frequency_stepsize; - uint32_t frequency_tolerance; - uint32_t symbol_rate_min; - uint32_t symbol_rate_max; - uint32_t symbol_rate_tolerance; /⋆ ppm ⋆/ - uint32_t notifier_delay; /⋆ ms ⋆/ - fe_caps_t caps; - }; - + + + ioctl FE_GET_INFO + &manvol; + + + + FE_GET_INFO + Query DVB frontend capabilities and returns information about + the front-end. This call only requires read-only access to the device + + + + + + int ioctl + int fd + int request + struct dvb_frontend_info *argp + + + + + + Arguments + + + fd + + &fd; + + + + request + + FE_GET_INFO + + + + argp + + pointer to struct &dvb-frontend-info; + + + + + + + Description + + All DVB frontend devices support the +FE_GET_INFO ioctl. It is used to identify +kernel devices compatible with this specification and to obtain +information about driver and hardware capabilities. The ioctl takes a +pointer to dvb_frontend_info which is filled by the driver. When the +driver is not compatible with this specification the ioctl returns an error &return-value-dvb;. + + + + struct <structname>dvb_frontend_info</structname> + + &cs-str; + + + char * + name[128] + Name of the frontend + + fe_type_t + type + DVBv3 type. Should not be used on modern programs, as a + frontend may have more than one type. So, the DVBv5 API should + be used instead to enumerate and select the frontend type. + + uint32_t + frequency_min + Minimal frequency supported by the frontend + + uint32_t + frequency_max + Maximal frequency supported by the frontend + + uint32_t + frequency_stepsize + Frequency step - all frequencies are multiple of this value + + uint32_t + frequency_tolerance + Tolerance of the frequency + + uint32_t + symbol_rate_min + Minimal symbol rate (for Cable/Satellite systems), in bauds + + uint32_t + symbol_rate_max + Maximal symbol rate (for Cable/Satellite systems), in bauds + + uint32_t + symbol_rate_tolerance + Maximal symbol rate tolerance, in ppm + + uint32_t + notifier_delay + Deprecated. Not used by any driver. + + &fe-caps; + caps + Capabilities supported by the frontend + + + +
+ + + NOTE: The frequencies are specified in Hz for Terrestrial and Cable + systems. They're specified in kHz for Satellite systems + +
+frontend capabilities + +Capabilities describe what a frontend can do. Some capabilities are + supported only on some specific frontend types. + + + enum fe_caps + + &cs-def; + + + ID + Description + + + + + FE_IS_STUPID + There's something wrong at the frontend, and it can't + report its capabilities + + + FE_CAN_INVERSION_AUTO + The frontend is capable of auto-detecting inversion + + + FE_CAN_FEC_1_2 + The frontend supports FEC 1/2 + + + FE_CAN_FEC_2_3 + The frontend supports FEC 2/3 + + + FE_CAN_FEC_3_4 + The frontend supports FEC 3/4 + + + FE_CAN_FEC_4_5 + The frontend supports FEC 4/5 + + + FE_CAN_FEC_5_6 + The frontend supports FEC 5/6 + + + FE_CAN_FEC_6_7 + The frontend supports FEC 6/7 + + + FE_CAN_FEC_7_8 + The frontend supports FEC 7/8 + + + FE_CAN_FEC_8_9 + The frontend supports FEC 8/9 + + + FE_CAN_FEC_AUTO + The frontend can autodetect FEC. + + + FE_CAN_QPSK + The frontend supports QPSK modulation + + + FE_CAN_QAM_16 + The frontend supports 16-QAM modulation + + + FE_CAN_QAM_32 + The frontend supports 32-QAM modulation + + + FE_CAN_QAM_64 + The frontend supports 64-QAM modulation + + + FE_CAN_QAM_128 + The frontend supports 128-QAM modulation + + + FE_CAN_QAM_256 + The frontend supports 256-QAM modulation + + + FE_CAN_QAM_AUTO + The frontend can autodetect modulation + + + FE_CAN_TRANSMISSION_MODE_AUTO + The frontend can autodetect the transmission mode + + + FE_CAN_BANDWIDTH_AUTO + The frontend can autodetect the bandwidth + + + FE_CAN_GUARD_INTERVAL_AUTO + The frontend can autodetect the guard interval + + + FE_CAN_HIERARCHY_AUTO + The frontend can autodetect hierarch + + + FE_CAN_8VSB + The frontend supports 8-VSB modulation + + + FE_CAN_16VSB + The frontend supports 16-VSB modulation + + + FE_HAS_EXTENDED_CAPS + Currently, unused + + + FE_CAN_MULTISTREAM + The frontend supports multistream filtering + + + FE_CAN_TURBO_FEC + The frontend supports turbo FEC modulation + + + FE_CAN_2G_MODULATION + The frontend supports "2nd generation modulation" (DVB-S2/T2)> + + + FE_NEEDS_BENDING + Not supported anymore, don't use it + + + FE_CAN_RECOVER + The frontend can recover from a cable unplug automatically + + + FE_CAN_MUTE_TS + The frontend can stop spurious TS data output + + + +
+
diseqc master command @@ -555,55 +764,6 @@ typedef enum fe_hierarchy {
-
-FE_GET_INFO -DESCRIPTION - - -This ioctl call returns information about the front-end. This call only requires - read-only access to the device. - - -SYNOPSIS - - - - int ioctl(int fd, int request = FE_GET_INFO, struct - dvb_frontend_info ⋆info); - - -PARAMETERS - - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_GET_INFO for this command. - - -struct - dvb_frontend_info - *info - -Points to the location where the front-end information is - to be stored. - - -&return-value-dvb; -
FE_DISEQC_RESET_OVERLOAD -- cgit v1.2.3 From 002563e9914180a176da1ddfdc094bc4fa52db5a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 07:39:46 -0300 Subject: [media] DocBook: move FE_GET_INFO to a separate xml file Keeping everything altogether makes harder to reorganize the DocBook. So, move the FE_GET_INFO ioctl and the associated structures into a separate file. No functional changes. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 266 +-------------------- .../DocBook/media/dvb/frontend_get_info.xml | 265 ++++++++++++++++++++ 2 files changed, 266 insertions(+), 265 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/frontend_get_info.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index e8032127886b..86346189e8fb 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -37,271 +37,7 @@ specification is available at FE_GET_INFO.
- - - ioctl FE_GET_INFO - &manvol; - - - - FE_GET_INFO - Query DVB frontend capabilities and returns information about - the front-end. This call only requires read-only access to the device - - - - - - int ioctl - int fd - int request - struct dvb_frontend_info *argp - - - - - - Arguments - - - fd - - &fd; - - - - request - - FE_GET_INFO - - - - argp - - pointer to struct &dvb-frontend-info; - - - - - - - Description - - All DVB frontend devices support the -FE_GET_INFO ioctl. It is used to identify -kernel devices compatible with this specification and to obtain -information about driver and hardware capabilities. The ioctl takes a -pointer to dvb_frontend_info which is filled by the driver. When the -driver is not compatible with this specification the ioctl returns an error &return-value-dvb;. - - - - struct <structname>dvb_frontend_info</structname> - - &cs-str; - - - char * - name[128] - Name of the frontend - - fe_type_t - type - DVBv3 type. Should not be used on modern programs, as a - frontend may have more than one type. So, the DVBv5 API should - be used instead to enumerate and select the frontend type. - - uint32_t - frequency_min - Minimal frequency supported by the frontend - - uint32_t - frequency_max - Maximal frequency supported by the frontend - - uint32_t - frequency_stepsize - Frequency step - all frequencies are multiple of this value - - uint32_t - frequency_tolerance - Tolerance of the frequency - - uint32_t - symbol_rate_min - Minimal symbol rate (for Cable/Satellite systems), in bauds - - uint32_t - symbol_rate_max - Maximal symbol rate (for Cable/Satellite systems), in bauds - - uint32_t - symbol_rate_tolerance - Maximal symbol rate tolerance, in ppm - - uint32_t - notifier_delay - Deprecated. Not used by any driver. - - &fe-caps; - caps - Capabilities supported by the frontend - - - -
- - - NOTE: The frequencies are specified in Hz for Terrestrial and Cable - systems. They're specified in kHz for Satellite systems - -
-frontend capabilities - -Capabilities describe what a frontend can do. Some capabilities are - supported only on some specific frontend types. - - - enum fe_caps - - &cs-def; - - - ID - Description - - - - - FE_IS_STUPID - There's something wrong at the frontend, and it can't - report its capabilities - - - FE_CAN_INVERSION_AUTO - The frontend is capable of auto-detecting inversion - - - FE_CAN_FEC_1_2 - The frontend supports FEC 1/2 - - - FE_CAN_FEC_2_3 - The frontend supports FEC 2/3 - - - FE_CAN_FEC_3_4 - The frontend supports FEC 3/4 - - - FE_CAN_FEC_4_5 - The frontend supports FEC 4/5 - - - FE_CAN_FEC_5_6 - The frontend supports FEC 5/6 - - - FE_CAN_FEC_6_7 - The frontend supports FEC 6/7 - - - FE_CAN_FEC_7_8 - The frontend supports FEC 7/8 - - - FE_CAN_FEC_8_9 - The frontend supports FEC 8/9 - - - FE_CAN_FEC_AUTO - The frontend can autodetect FEC. - - - FE_CAN_QPSK - The frontend supports QPSK modulation - - - FE_CAN_QAM_16 - The frontend supports 16-QAM modulation - - - FE_CAN_QAM_32 - The frontend supports 32-QAM modulation - - - FE_CAN_QAM_64 - The frontend supports 64-QAM modulation - - - FE_CAN_QAM_128 - The frontend supports 128-QAM modulation - - - FE_CAN_QAM_256 - The frontend supports 256-QAM modulation - - - FE_CAN_QAM_AUTO - The frontend can autodetect modulation - - - FE_CAN_TRANSMISSION_MODE_AUTO - The frontend can autodetect the transmission mode - - - FE_CAN_BANDWIDTH_AUTO - The frontend can autodetect the bandwidth - - - FE_CAN_GUARD_INTERVAL_AUTO - The frontend can autodetect the guard interval - - - FE_CAN_HIERARCHY_AUTO - The frontend can autodetect hierarch - - - FE_CAN_8VSB - The frontend supports 8-VSB modulation - - - FE_CAN_16VSB - The frontend supports 16-VSB modulation - - - FE_HAS_EXTENDED_CAPS - Currently, unused - - - FE_CAN_MULTISTREAM - The frontend supports multistream filtering - - - FE_CAN_TURBO_FEC - The frontend supports turbo FEC modulation - - - FE_CAN_2G_MODULATION - The frontend supports "2nd generation modulation" (DVB-S2/T2)> - - - FE_NEEDS_BENDING - Not supported anymore, don't use it - - - FE_CAN_RECOVER - The frontend can recover from a cable unplug automatically - - - FE_CAN_MUTE_TS - The frontend can stop spurious TS data output - - - -
-
- +&sub-frontend_get_info;
diseqc master command diff --git a/Documentation/DocBook/media/dvb/frontend_get_info.xml b/Documentation/DocBook/media/dvb/frontend_get_info.xml new file mode 100644 index 000000000000..d569e386fb15 --- /dev/null +++ b/Documentation/DocBook/media/dvb/frontend_get_info.xml @@ -0,0 +1,265 @@ + + + ioctl FE_GET_INFO + &manvol; + + + + FE_GET_INFO + Query DVB frontend capabilities and returns information about + the front-end. This call only requires read-only access to the device + + + + + + int ioctl + int fd + int request + &dvb-frontend-info; *argp + + + + + + Arguments + + + fd + + &fd; + + + + request + + FE_GET_INFO + + + + argp + + pointer to struct &dvb-frontend-info; + + + + + + + Description + + All DVB frontend devices support the +FE_GET_INFO ioctl. It is used to identify +kernel devices compatible with this specification and to obtain +information about driver and hardware capabilities. The ioctl takes a +pointer to dvb_frontend_info which is filled by the driver. When the +driver is not compatible with this specification the ioctl returns an error &return-value-dvb;. + + + + struct <structname>dvb_frontend_info</structname> + + &cs-str; + + + char * + name[128] + Name of the frontend + + fe_type_t + type + DVBv3 type. Should not be used on modern programs, as a + frontend may have more than one type. So, the DVBv5 API should + be used instead to enumerate and select the frontend type. + + uint32_t + frequency_min + Minimal frequency supported by the frontend + + uint32_t + frequency_max + Maximal frequency supported by the frontend + + uint32_t + frequency_stepsize + Frequency step - all frequencies are multiple of this value + + uint32_t + frequency_tolerance + Tolerance of the frequency + + uint32_t + symbol_rate_min + Minimal symbol rate (for Cable/Satellite systems), in bauds + + uint32_t + symbol_rate_max + Maximal symbol rate (for Cable/Satellite systems), in bauds + + uint32_t + symbol_rate_tolerance + Maximal symbol rate tolerance, in ppm + + uint32_t + notifier_delay + Deprecated. Not used by any driver. + + &fe-caps; + caps + Capabilities supported by the frontend + + + +
+ + + NOTE: The frequencies are specified in Hz for Terrestrial and Cable + systems. They're specified in kHz for Satellite systems + +
+frontend capabilities + +Capabilities describe what a frontend can do. Some capabilities are + supported only on some specific frontend types. + + + enum fe_caps + + &cs-def; + + + ID + Description + + + + + FE_IS_STUPID + There's something wrong at the frontend, and it can't + report its capabilities + + + FE_CAN_INVERSION_AUTO + The frontend is capable of auto-detecting inversion + + + FE_CAN_FEC_1_2 + The frontend supports FEC 1/2 + + + FE_CAN_FEC_2_3 + The frontend supports FEC 2/3 + + + FE_CAN_FEC_3_4 + The frontend supports FEC 3/4 + + + FE_CAN_FEC_4_5 + The frontend supports FEC 4/5 + + + FE_CAN_FEC_5_6 + The frontend supports FEC 5/6 + + + FE_CAN_FEC_6_7 + The frontend supports FEC 6/7 + + + FE_CAN_FEC_7_8 + The frontend supports FEC 7/8 + + + FE_CAN_FEC_8_9 + The frontend supports FEC 8/9 + + + FE_CAN_FEC_AUTO + The frontend can autodetect FEC. + + + FE_CAN_QPSK + The frontend supports QPSK modulation + + + FE_CAN_QAM_16 + The frontend supports 16-QAM modulation + + + FE_CAN_QAM_32 + The frontend supports 32-QAM modulation + + + FE_CAN_QAM_64 + The frontend supports 64-QAM modulation + + + FE_CAN_QAM_128 + The frontend supports 128-QAM modulation + + + FE_CAN_QAM_256 + The frontend supports 256-QAM modulation + + + FE_CAN_QAM_AUTO + The frontend can autodetect modulation + + + FE_CAN_TRANSMISSION_MODE_AUTO + The frontend can autodetect the transmission mode + + + FE_CAN_BANDWIDTH_AUTO + The frontend can autodetect the bandwidth + + + FE_CAN_GUARD_INTERVAL_AUTO + The frontend can autodetect the guard interval + + + FE_CAN_HIERARCHY_AUTO + The frontend can autodetect hierarch + + + FE_CAN_8VSB + The frontend supports 8-VSB modulation + + + FE_CAN_16VSB + The frontend supports 16-VSB modulation + + + FE_HAS_EXTENDED_CAPS + Currently, unused + + + FE_CAN_MULTISTREAM + The frontend supports multistream filtering + + + FE_CAN_TURBO_FEC + The frontend supports turbo FEC modulation + + + FE_CAN_2G_MODULATION + The frontend supports "2nd generation modulation" (DVB-S2/T2)> + + + FE_NEEDS_BENDING + Not supported anymore, don't use it + + + FE_CAN_RECOVER + The frontend can recover from a cable unplug automatically + + + FE_CAN_MUTE_TS + The frontend can stop spurious TS data output + + + +
+
+ -- cgit v1.2.3 From 5b233e1a91f31ec45feffb1ea6a33aae433259e9 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 08:17:53 -0300 Subject: [media] DocBook: improve documentation for FE_READ_STATUS Move the ioctl and enum fe_status to a separate xml file and put it into a better format. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 119 ++------------------- .../DocBook/media/dvb/frontend_read_status.xml | 103 ++++++++++++++++++ 2 files changed, 113 insertions(+), 109 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/frontend_read_status.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 86346189e8fb..28acf5a1e9ff 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -33,12 +33,21 @@ specification is available at
Querying frontend information -Information about the frontend ca be queried with +Information about the frontend can be queried with FE_GET_INFO.
&sub-frontend_get_info; +
+Querying frontend status + +Information about the frontend tuner locking status can be queried with + FE_READ_STATUS. +
+ +&sub-frontend_read_status; +
diseqc master command @@ -109,51 +118,6 @@ spec.
-
-frontend status -Several functions of the frontend device use the fe_status data type defined -by - -typedef enum fe_status { - FE_HAS_SIGNAL = 0x01, - FE_HAS_CARRIER = 0x02, - FE_HAS_VITERBI = 0x04, - FE_HAS_SYNC = 0x08, - FE_HAS_LOCK = 0x10, - FE_TIMEDOUT = 0x20, - FE_REINIT = 0x40, -} fe_status_t; - -to indicate the current state and/or state changes of the frontend hardware: - - - - -FE_HAS_SIGNAL -The frontend has found something above the noise level - -FE_HAS_CARRIER -The frontend has found a DVB signal - -FE_HAS_VITERBI -The frontend FEC inner coding (Viterbi, LDPC or other inner code) is stable - -FE_HAS_SYNC -Synchronization bytes was found - -FE_HAS_LOCK -The DVB were locked and everything is working - -FE_TIMEDOUT -no lock within the last about 2 seconds - -FE_REINIT -The frontend was reinitialized, application is -recommended to reset DiSEqC, tone and parameters - - -
-
frontend spectral inversion The Inversion field can take one of these values: @@ -437,69 +401,6 @@ typedef enum fe_hierarchy {
-
-FE_READ_STATUS -DESCRIPTION - - -This ioctl call returns status information about the front-end. This call only - requires read-only access to the device. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_READ_STATUS, - fe_status_t ⋆status); - - -PARAMETERS - - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_READ_STATUS for this command. - - -struct fe_status_t - *status - -Points to the location where the front-end status word is - to be stored. - - -RETURN VALUE - -EBADF - -fd is not a valid open file descriptor. - - -EFAULT - -status points to invalid address. - - -
-
FE_DISEQC_RESET_OVERLOAD diff --git a/Documentation/DocBook/media/dvb/frontend_read_status.xml b/Documentation/DocBook/media/dvb/frontend_read_status.xml new file mode 100644 index 000000000000..f2d08b6e2422 --- /dev/null +++ b/Documentation/DocBook/media/dvb/frontend_read_status.xml @@ -0,0 +1,103 @@ + + + ioctl FE_READ_STATUS + &manvol; + + + + FE_READ_STATUS + Returns status information about the front-end. This call only + requires read-only access to the device + + + + + + int ioctl + int fd + int request + &fe-status; *argp + + + + + + Arguments + + + fd + + &fd; + + + + request + + FE_READ_STATUS + + + + argp + + pointer to &fe-status; + + + + + + + Description + + All DVB frontend devices support the +FE_READ_STATUS ioctl. It is used to check about the +locking status of the frontend after being tuned. The ioctl takes a +pointer to a 16-bits number where the status will be written. +&return-value-dvb;. + + + +
+enum fe_status + +The enum fe_status is used to indicate the current state + and/or state changes of the frontend hardware. + + + enum fe_status + + &cs-def; + + + ID + Description + + + + + FE_HAS_SIGNAL + The frontend has found something above the noise level + + FE_HAS_CARRIER + The frontend has found a DVB signal + + FE_HAS_VITERBI + The frontend FEC inner coding (Viterbi, LDPC or other inner code) is stable + + FE_HAS_SYNC + Synchronization bytes was found + + FE_HAS_LOCK + The DVB were locked and everything is working + + FE_TIMEDOUT + no lock within the last about 2 seconds + + FE_REINIT + The frontend was reinitialized, application is + recommended to reset DiSEqC, tone and parameters + + + +
+
+ -- cgit v1.2.3 From 56599d419660682804864e59f8909079a59418ce Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 08:47:47 -0300 Subject: [media] DocBook: move DVB properties to happen earlier at the document The DVBv5 API uses DVB properties as the main way to set the frontend and collect statistics. Move the definition to happen earlier, in order to reflect its importance. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 28acf5a1e9ff..659f71ab67ef 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -48,6 +48,8 @@ specification is available at &sub-frontend_read_status; +&sub-dvbproperty; +
diseqc master command @@ -778,5 +780,3 @@ FE_TUNE_MODE_ONESHOT When set, this flag will disable any zigzagging or other "n &sub-frontend_legacy_api;
- -&sub-dvbproperty; -- cgit v1.2.3 From ffec8bceacd605da2a7a273f9ab9c2fff68171e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 08:48:51 -0300 Subject: [media] DocBook: rewrite FE_GET_PROPERTY/FE_SET_PROPERTY to use the std way Use the standard way of documenting ioctls for FE_GET_PROPERTY and FE_SET_PROPERTY. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 214 +++++++++++++----------- 1 file changed, 118 insertions(+), 96 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 7ddab2ba9b40..272d2e5c7488 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -7,6 +7,7 @@ the capability ioctls weren't implemented yet via the new way. The typical usage for the FE_GET_PROPERTY/FE_SET_PROPERTY API is to replace the ioctl's were the struct dvb_frontend_parameters were used. +
DTV stats type @@ -66,102 +67,6 @@ struct dtv_properties {
-
-FE_GET_PROPERTY -DESCRIPTION - - -This ioctl call returns one or more frontend properties. This call only - requires read-only access to the device. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_GET_PROPERTY, - dtv_properties ⋆props); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int num - -Equals FE_GET_PROPERTY for this command. - - -struct dtv_property *props - -Points to the location where the front-end property commands are stored. - - -&return-value-dvb; - - EOPNOTSUPP - Property type not supported. - -
- -
-FE_SET_PROPERTY -DESCRIPTION - - -This ioctl call sets one or more frontend properties. This call - requires read/write access to the device. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_SET_PROPERTY, - dtv_properties ⋆props); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int num - -Equals FE_SET_PROPERTY for this command. - - -struct dtv_property *props - -Points to the location where the front-end property commands are stored. - - -&return-value-dvb; - - EOPNOTSUPP - Property type not supported. - -
-
Property types @@ -1315,3 +1220,120 @@ enum fe_interleaving {
+ + + + ioctl FE_GET_PROPERTY + &manvol; + + + + FE_GET_PROPERTY + Returns one or more frontend properties. This call only + requires read-only access to the device + + + + + + int ioctl + int fd + int request + &dtv-property; *argp + + + + + + Arguments + + + fd + + &fd; + + + + request + + FE_GET_PROPERTY + + + + argp + + pointer to &dtv-property; + + + + + + + Description + + All DVB frontend devices support the +FE_GET_PROPERTY ioctl. It is used to get properties and +statistics from the frontend. +&return-value-dvb;. + + + + + + + ioctl FE_SET_PROPERTY + &manvol; + + + + FE_SET_PROPERTY + Sets one or more frontend properties. This call + requires read/write access to the device + + + + + + int ioctl + int fd + int request + &dtv-property; *argp + + + + + + Arguments + + + fd + + &fd; + + + + request + + FE_SET_PROPERTY + + + + argp + + pointer to &dtv-property; + + + + + + + Description + + All DVB frontend devices support the +FE_SET_PROPERTY ioctl. It is used to sets one or more +frontend properties. This is the basic command to request the frontend to tune +into some frequency and to start decoding the digital TV signal. +&return-value-dvb;. + + + -- cgit v1.2.3 From c130d88b01dba55dcaaa350bff2df3b1776a7bdd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 09:03:55 -0300 Subject: [media] DocBook: fix xref to the FE open() function Instead of going to the V4L2 open(), use the xref to the proper place at the frontend ioctls that were already reformatted. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 4 ++-- Documentation/DocBook/media/dvb/frontend_get_info.xml | 2 +- Documentation/DocBook/media/dvb/frontend_read_status.xml | 2 +- Documentation/DocBook/media_api.tmpl | 1 + 4 files changed, 5 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 272d2e5c7488..f9680b0302b3 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -1250,7 +1250,7 @@ enum fe_interleaving { fd - &fd; + &fe_fd; @@ -1308,7 +1308,7 @@ statistics from the frontend. fd - &fd; + &fe_fd; diff --git a/Documentation/DocBook/media/dvb/frontend_get_info.xml b/Documentation/DocBook/media/dvb/frontend_get_info.xml index d569e386fb15..b98a9a5e74d3 100644 --- a/Documentation/DocBook/media/dvb/frontend_get_info.xml +++ b/Documentation/DocBook/media/dvb/frontend_get_info.xml @@ -27,7 +27,7 @@ fd - &fd; + &fe_fd; diff --git a/Documentation/DocBook/media/dvb/frontend_read_status.xml b/Documentation/DocBook/media/dvb/frontend_read_status.xml index f2d08b6e2422..9c1810ae920d 100644 --- a/Documentation/DocBook/media/dvb/frontend_read_status.xml +++ b/Documentation/DocBook/media/dvb/frontend_read_status.xml @@ -27,7 +27,7 @@ fd - &fd; + &fe_fd; diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index d15c9c61e730..1e194514841c 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -7,6 +7,7 @@ open()."> +open()."> 2C"> Return ValueOn success 0 is returned, on error -1 and the errno variable is set appropriately. The generic error codes are described at the Generic Error Codes chapter."> RETURN VALUEOn success 0 is returned, on error -1 and the errno variable is set appropriately. The generic error codes are described at the Generic Error Codes chapter."> -- cgit v1.2.3 From 277dfcb4e0641f006afd06ef1ce45be424423f37 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 10:28:05 -0300 Subject: [media] DocBook: Merge FE_SET_PROPERTY/FE_GET_PROPERTY ioctl description Instead of having two refentries, merge them into just one, like what's done with other similar ioctls at V4L2 side. That makes the entry cleaner and will allow to add the associated structures together with the refentry. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 2 +- Documentation/DocBook/media/dvb/dvbproperty.xml | 100 +++++++-------------- .../DocBook/media/dvb/frontend_legacy_api.xml | 6 +- 3 files changed, 36 insertions(+), 72 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index f2f57861f0c8..f8380219afbb 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -179,7 +179,6 @@ DOCUMENTED = \ -e "s/v4l2\-mpeg\-vbi\-ITV0/v4l2-mpeg-vbi-itv0-1/g" DVB_DOCUMENTED = \ - -e "s/\(linkend\=\"\)FE_SET_PROPERTY/\1FE_GET_PROPERTY/g" \ -e "s,\(struct\s\+\)\([a-z0-9_]\+\)\(\s\+{\),\1\\2\<\/link\>\3,g" \ -e "s,\(}\s\+\)\([a-z0-9_]\+_t\+\),\1\\2\<\/link\>,g" \ -e "s,\(define\s\+\)\(DTV_[A-Z0-9_]\+\)\(\s\+[0-9]\+\),\1\\2\<\/link\>\3,g" \ @@ -189,6 +188,7 @@ DVB_DOCUMENTED = \ -e "s,DTV-ISDBT-LAYER[A-C],DTV-ISDBT-LAYER,g" \ -e "s,\(define\s\+\)\([A-Z0-9_]\+\)\(\s\+_IO\),\1\\2\<\/link\>\3,g" \ -e "s,\(__.*_OLD\)<\/link>,\1,g" \ + -e "s/\(linkend\=\"\)FE_SET_PROPERTY/\1FE_GET_PROPERTY/g" \ # # Media targets and dependencies diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index f9680b0302b3..28ea62067af6 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -70,7 +70,7 @@ struct dtv_properties {
Property types -On FE_GET_PROPERTY/FE_SET_PROPERTY, +On FE_GET_PROPERTY and FE_SET_PROPERTY, the actual action is determined by the dtv_property cmd/data pairs. With one single ioctl, is possible to get/set up to 64 properties. The actual meaning of each property is described on the next sections. @@ -1223,14 +1223,14 @@ enum fe_interleaving { - ioctl FE_GET_PROPERTY + ioctl FE_SET_PROPERTY, FE_GET_PROPERTY &manvol; - FE_GET_PROPERTY - Returns one or more frontend properties. This call only - requires read-only access to the device + FE_SET_PROPERTY and FE_GET_PROPERTY + FE_SET_PROPERTY sets one or more frontend properties. + FE_GET_PROPERTY returns one or more frontend properties. @@ -1256,7 +1256,7 @@ enum fe_interleaving { request - FE_GET_PROPERTY + FE_SET_PROPERTY, FE_GET_PROPERTY @@ -1272,68 +1272,32 @@ enum fe_interleaving { Description All DVB frontend devices support the -FE_GET_PROPERTY ioctl. It is used to get properties and -statistics from the frontend. +FE_SET_PROPERTY and FE_GET_PROPERTY +ioctls. The supported properties and statistics depends on the delivery system +and on the device: + + + FE_SET_PROPERTY: + +This ioctl is used to set one or more + frontend properties. +This is the basic command to request the frontend to tune into some + frequency and to start decoding the digital TV signal. +This call requires read/write access to the device. +At return, the values are updated to reflect the + actual parameters used. + + + + FE_GET_PROPERTY: + +This ioctl is used to get properties and +statistics from the frontend. +No properties are changed, and statistics aren't reset. +This call only requires read-only access to the device. + + + &return-value-dvb;. - - - - - - - ioctl FE_SET_PROPERTY - &manvol; - - - - FE_SET_PROPERTY - Sets one or more frontend properties. This call - requires read/write access to the device - - - - - - int ioctl - int fd - int request - &dtv-property; *argp - - - - - - Arguments - - - fd - - &fe_fd; - - - - request - - FE_SET_PROPERTY - - - - argp - - pointer to &dtv-property; - - - - - - - Description - - All DVB frontend devices support the -FE_SET_PROPERTY ioctl. It is used to sets one or more -frontend properties. This is the basic command to request the frontend to tune -into some frequency and to start decoding the digital TV signal. -&return-value-dvb;. - diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index f4d300488d12..e2817f830312 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -42,7 +42,7 @@ Newer formats like DVB-S2, ISDB-T, ISDB-S and DVB-T2 are not described at the above, as they're -supported via the new FE_GET_PROPERTY/FE_GET_SET_PROPERTY ioctl's, using the DTV_DELIVERY_SYSTEM parameter. +supported via the new FE_GET_PROPERTY/FE_GET_SET_PROPERTY ioctl's, using the DTV_DELIVERY_SYSTEM parameter. The usage of this field is deprecated, as it doesn't report all supported standards, and @@ -59,11 +59,11 @@ the kind of hardware you are using. union with specific per-system parameters. However, as newer delivery systems required more data, the structure size weren't enough to fit, and just extending its size would break the existing applications. So, those parameters -were replaced by the usage of +were replaced by the usage of FE_GET_PROPERTY/FE_SET_PROPERTY ioctl's. The new API is flexible enough to add new parameters to existing delivery systems, and to add newer delivery systems. -So, newer applications should use +So, newer applications should use FE_GET_PROPERTY/FE_SET_PROPERTY instead, in order to be able to support the newer System Delivery like DVB-S2, DVB-T2, DVB-C2, ISDB, etc. -- cgit v1.2.3 From e4aa18d33c3a05f9ac51a8c8c7863318c807650f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 11:04:14 -0300 Subject: [media] DocBook: Improve the description of the properties API Make the text clearer about what the properties API does. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 37 +++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 28ea62067af6..c10ed0636d02 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -1,8 +1,35 @@ -
-<constant>FE_GET_PROPERTY/FE_SET_PROPERTY</constant> -This section describes the DVB version 5 extension of the DVB-API, also -called "S2API", as this API were added to provide support for DVB-S2. It was -designed to be able to replace the old frontend API. Yet, the DISEQC and +
+DVB Frontend properties +Tuning into a Digital TV physical channel and starting decoding it + requires to change a set of parameters, in order to control the + tuner, the demodulator, the Linear Low-noise Amplifier (LNA) and to set the + antena subsystem via Satellite Equipment Control (SEC), on satellital + systems. The actual parameters are specific to each particular digital + TV standards, and may change as the digital TV specs evolutes. +In the past, the strategy used were to have an union with the parameters + needed to tune for DVB-S, DVB-C, DVB-T and ATSC delivery systems grouped + there. The problem is that, as the second generation standards appeared, + those structs were not big enough to contain the additional parameters. + Also, the union didn't have any space left to be expanded without breaking + userspace. So, the decision was to deprecate the legacy union/struct based + approach, in favor of a properties set approach. +By using a properties set, it is now possible to extend and support any + digital TV without needing to redesign the API +Example: with the properties based approach, in order to set the tuner + to a DVB-C channel at 651 kHz, modulated with 256-QAM, FEC 3/4 and symbol + rate of 5.217 Mbauds, those properties should be sent to + FE_SET_PROPERTY ioctl: + + DTV_FREQUENCY = 651000000 + DTV_MODULATION = QAM_256 + DTV_INVERSION = INVERSION_AUTO + DTV_SYMBOL_RATE = 5217000 + DTV_INNER_FEC = FEC_3_4 + DTV_TUNE + +NOTE: This section describes the DVB version 5 extension of the DVB-API, +also called "S2API", as this API were added to provide support for DVB-S2. It +was designed to be able to replace the old frontend API. Yet, the DISEQC and the capability ioctls weren't implemented yet via the new way. The typical usage for the FE_GET_PROPERTY/FE_SET_PROPERTY API is to replace the ioctl's were the -- cgit v1.2.3 From c569eb707a04772e763d3bfebb9713e93c8b9d61 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 11:35:44 -0300 Subject: [media] DocBook: Add xref links for DTV propeties Create xref links for all DTV properties and link the frontend.h to each. Also use them at the DVB frontent API example. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 14 ++++++++++++++ Documentation/DocBook/media/dvb/dvbproperty.xml | 12 ++++++------ 2 files changed, 20 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index f8380219afbb..723932f85fb6 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -73,6 +73,9 @@ IOCTLS = \ VIDIOC_SUBDEV_G_SELECTION \ VIDIOC_SUBDEV_S_SELECTION \ +DEFINES = \ + $(shell perl -ne 'print "$$1 " if /\#define\s+(DTV_[^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/frontend.h) \ + TYPES = \ $(shell perl -ne 'print "$$1 " if /^typedef\s+[^\s]+\s+([^\s]+)\;/' $(srctree)/include/uapi/linux/videodev2.h) \ $(shell perl -ne 'print "$$1 " if /^}\s+([a-z0-9_]+_t)/' $(srctree)/include/uapi/linux/dvb/frontend.h) @@ -187,8 +190,10 @@ DVB_DOCUMENTED = \ -e "s,\(audio-mixer\|audio-karaoke\|audio-status\|ca-slot-info\|ca-descr-info\|ca-caps\|ca-msg\|ca-descr\|ca-pid\|dmx-filter\|dmx-caps\|video-system\|video-highlight\|video-spu\|video-spu-palette\|video-navi-pack\)-t,\1,g" \ -e "s,DTV-ISDBT-LAYER[A-C],DTV-ISDBT-LAYER,g" \ -e "s,\(define\s\+\)\([A-Z0-9_]\+\)\(\s\+_IO\),\1\\2\<\/link\>\3,g" \ + -e "s,\(define\s\+\)\(DTV_[A-Z0-9_]\+\)\(\s\+\),\1\\2\<\/link\>\3,g" \ -e "s,\(__.*_OLD\)<\/link>,\1,g" \ -e "s/\(linkend\=\"\)FE_SET_PROPERTY/\1FE_GET_PROPERTY/g" \ + -e "s,\(DTV_ISDBS_TS_ID_LEGACY\|DTV_MAX_COMMAND\|DTV_IOCTL_MAX_MSGS\)<\/link>,\1,g" \ # # Media targets and dependencies @@ -306,6 +311,15 @@ $(MEDIA_OBJ_DIR)/media-entities.tmpl: $(MEDIA_OBJ_DIR)/v4l2.xml >>$@ ; \ done) @( \ + echo -e "\n") >>$@ + @( \ + for ident in $(DEFINES) ; do \ + entity=`echo $$ident | tr _ -` ; \ + echo "$$ident\">" \ + >>$@ ; \ + done) + @( \ echo -e "\n") >>$@ @( \ for ident in $(TYPES) ; do \ diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index c10ed0636d02..bb86a74ed7fe 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -20,12 +20,12 @@ rate of 5.217 Mbauds, those properties should be sent to FE_SET_PROPERTY ioctl: - DTV_FREQUENCY = 651000000 - DTV_MODULATION = QAM_256 - DTV_INVERSION = INVERSION_AUTO - DTV_SYMBOL_RATE = 5217000 - DTV_INNER_FEC = FEC_3_4 - DTV_TUNE + &DTV-FREQUENCY; = 651000000 + &DTV-MODULATION; = QAM_256 + &DTV-INVERSION; = INVERSION_AUTO + &DTV-SYMBOL-RATE; = 5217000 + &DTV-INNER-FEC; = FEC_3_4 + &DTV-TUNE; NOTE: This section describes the DVB version 5 extension of the DVB-API, also called "S2API", as this API were added to provide support for DVB-S2. It -- cgit v1.2.3 From 87e4d63748796bcc68128f7287925701bc53d6b3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 12:42:08 -0300 Subject: [media] DocBook: Improve xref check for undocumented ioctls There are several badly documented undocumented ioctls. Currently, it just generates an empty link. Instead of doing that, only add references to the ones that exists, and add a warning for all references that weren't found. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index 723932f85fb6..fdb0027f353c 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -305,10 +305,12 @@ $(MEDIA_OBJ_DIR)/media-entities.tmpl: $(MEDIA_OBJ_DIR)/v4l2.xml @( \ for ident in $(IOCTLS) ; do \ entity=`echo $$ident | tr _ -` ; \ - id=`grep "$$ident" $(MEDIA_OBJ_DIR)/vidioc-*.xml $(MEDIA_OBJ_DIR)/media-ioc-*.xml | sed -r s,"^.*/(.*).xml.*","\1",` ; \ - echo "$$ident" -e "
$$ident\">" \ - >>$@ ; \ + >>$@ ; else \ + echo "Warning: undocumented ioctl: $$ident. Please document it at the media DocBook!" >&2; \ + fi; \ done) @( \ echo -e "\n") >>$@ -- cgit v1.2.3 From 3246c385f3cb58974128835c070b2bdd85bd251d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 16:58:26 -0300 Subject: [media] DocBook: remove duplicated ioctl from v4l2-subdev Those ioctls are already parsed. No need to explicitly add them. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 7 ------- 1 file changed, 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index fdb0027f353c..c82e051f2821 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -65,13 +65,6 @@ IOCTLS = \ $(shell perl -ne 'print "$$1 " if /\#define\s+([^\s]+)\s+_IO/' $(srctree)/include/uapi/linux/dvb/video.h) \ $(shell perl -ne 'print "$$1 " if /\#define\s+([^\s]+)\s+_IO/' $(srctree)/include/uapi/linux/media.h) \ $(shell perl -ne 'print "$$1 " if /\#define\s+([^\s]+)\s+_IO/' $(srctree)/include/uapi/linux/v4l2-subdev.h) \ - VIDIOC_SUBDEV_G_FRAME_INTERVAL \ - VIDIOC_SUBDEV_S_FRAME_INTERVAL \ - VIDIOC_SUBDEV_ENUM_MBUS_CODE \ - VIDIOC_SUBDEV_ENUM_FRAME_SIZE \ - VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL \ - VIDIOC_SUBDEV_G_SELECTION \ - VIDIOC_SUBDEV_S_SELECTION \ DEFINES = \ $(shell perl -ne 'print "$$1 " if /\#define\s+(DTV_[^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/frontend.h) \ -- cgit v1.2.3 From 55d4423a2d0bb54386f3a4ee51dabffb5d2a3394 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 17:29:22 -0300 Subject: [media] DocBook: Fix false positive undefined ioctl references The new code that detects undocumented ioctls hits some false positives: This one is not documented, nor it should, as this is there just to reserve namespace: Warning: can't find reference for VIDIOC_RESERVED ioctl But those are already documented together with other ioctls: Warning: can't find reference for VIDIOC_UNSUBSCRIBE_EVENT ioctl Warning: can't find reference for FE_GET_PROPERTY ioctl Warning: can't find reference for VIDIOC_SUBDEV_G_EDID ioctl Warning: can't find reference for VIDIOC_SUBDEV_S_EDID ioctl Warning: can't find reference for VIDIOC_SUBDEV_S_DV_TIMINGS ioctl Warning: can't find reference for VIDIOC_SUBDEV_G_DV_TIMINGS ioctl Warning: can't find reference for VIDIOC_SUBDEV_QUERY_DV_TIMINGS ioctl So, we need to just be sure to point to the right documentation. Signed-off-by: Mauro Carvalho Chehab Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 2 +- Documentation/DocBook/media/dvb/dvbproperty.xml | 3 ++- Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml | 4 +++- Documentation/DocBook/media/v4l/vidioc-g-edid.xml | 4 +++- Documentation/DocBook/media/v4l/vidioc-query-dv-timings.xml | 3 ++- Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml | 3 ++- 6 files changed, 13 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index c82e051f2821..e07e8844efde 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -296,7 +296,7 @@ $(MEDIA_OBJ_DIR)/media-entities.tmpl: $(MEDIA_OBJ_DIR)/v4l2.xml @( \ echo -e "\n") >>$@ @( \ - for ident in $(IOCTLS) ; do \ + for ident in `echo $(IOCTLS) | sed -e "s,VIDIOC_RESERVED,,"`; do\ entity=`echo $$ident | tr _ -` ; \ id=`grep -e "$$ident" -e "
- FE_SET_PROPERTY and FE_GET_PROPERTY + FE_SET_PROPERTY + FE_GET_PROPERTY FE_SET_PROPERTY sets one or more frontend properties. FE_GET_PROPERTY returns one or more frontend properties. diff --git a/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml b/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml index 764b635ed4cf..06952d7cc770 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-dv-timings.xml @@ -7,6 +7,8 @@ VIDIOC_G_DV_TIMINGS VIDIOC_S_DV_TIMINGS + VIDIOC_SUBDEV_G_DV_TIMINGS + VIDIOC_SUBDEV_S_DV_TIMINGS Get or set DV timings for input or output @@ -34,7 +36,7 @@ request - VIDIOC_G_DV_TIMINGS, VIDIOC_S_DV_TIMINGS + VIDIOC_G_DV_TIMINGS, VIDIOC_S_DV_TIMINGS, VIDIOC_SUBDEV_G_DV_TIMINGS, VIDIOC_SUBDEV_S_DV_TIMINGS diff --git a/Documentation/DocBook/media/v4l/vidioc-g-edid.xml b/Documentation/DocBook/media/v4l/vidioc-g-edid.xml index e44340c1f9f7..2702536bbc7c 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-edid.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-edid.xml @@ -7,6 +7,8 @@ VIDIOC_G_EDID VIDIOC_S_EDID + VIDIOC_SUBDEV_G_EDID + VIDIOC_SUBDEV_S_EDID Get or set the EDID of a video receiver/transmitter @@ -42,7 +44,7 @@ request - VIDIOC_G_EDID, VIDIOC_S_EDID + VIDIOC_G_EDID, VIDIOC_S_EDID, VIDIOC_SUBDEV_G_EDID, VIDIOC_SUBDEV_S_EDID diff --git a/Documentation/DocBook/media/v4l/vidioc-query-dv-timings.xml b/Documentation/DocBook/media/v4l/vidioc-query-dv-timings.xml index e185f149e0a1..e9c70a8f3476 100644 --- a/Documentation/DocBook/media/v4l/vidioc-query-dv-timings.xml +++ b/Documentation/DocBook/media/v4l/vidioc-query-dv-timings.xml @@ -6,6 +6,7 @@ VIDIOC_QUERY_DV_TIMINGS + VIDIOC_SUBDEV_QUERY_DV_TIMINGS Sense the DV preset received by the current input @@ -34,7 +35,7 @@ input request - VIDIOC_QUERY_DV_TIMINGS + VIDIOC_QUERY_DV_TIMINGS, VIDIOC_SUBDEV_QUERY_DV_TIMINGS diff --git a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml index d0332f610929..5fd0ee78f880 100644 --- a/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml +++ b/Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml @@ -5,7 +5,8 @@ - VIDIOC_SUBSCRIBE_EVENT, VIDIOC_UNSUBSCRIBE_EVENT + VIDIOC_SUBSCRIBE_EVENT + VIDIOC_UNSUBSCRIBE_EVENT Subscribe or unsubscribe event -- cgit v1.2.3 From 09c3b4a0af0906c739e2cbe91f97e65d9b096020 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 18:10:43 -0300 Subject: [media] DocBook: Rename ioctl xml files for the xml files describing ioctls, use the same nomenclature as on V4L2: the ioctl name, in lower case, using - instead of _. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-get-info.xml | 265 +++++++++++++++++++++ Documentation/DocBook/media/dvb/fe-read-status.xml | 103 ++++++++ Documentation/DocBook/media/dvb/frontend.xml | 4 +- .../DocBook/media/dvb/frontend_get_info.xml | 265 --------------------- .../DocBook/media/dvb/frontend_read_status.xml | 103 -------- 5 files changed, 370 insertions(+), 370 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-get-info.xml create mode 100644 Documentation/DocBook/media/dvb/fe-read-status.xml delete mode 100644 Documentation/DocBook/media/dvb/frontend_get_info.xml delete mode 100644 Documentation/DocBook/media/dvb/frontend_read_status.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-get-info.xml b/Documentation/DocBook/media/dvb/fe-get-info.xml new file mode 100644 index 000000000000..b98a9a5e74d3 --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-get-info.xml @@ -0,0 +1,265 @@ + + + ioctl FE_GET_INFO + &manvol; + + + + FE_GET_INFO + Query DVB frontend capabilities and returns information about + the front-end. This call only requires read-only access to the device + + + + + + int ioctl + int fd + int request + &dvb-frontend-info; *argp + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_GET_INFO + + + + argp + + pointer to struct &dvb-frontend-info; + + + + + + + Description + + All DVB frontend devices support the +FE_GET_INFO ioctl. It is used to identify +kernel devices compatible with this specification and to obtain +information about driver and hardware capabilities. The ioctl takes a +pointer to dvb_frontend_info which is filled by the driver. When the +driver is not compatible with this specification the ioctl returns an error &return-value-dvb;. + + + + struct <structname>dvb_frontend_info</structname> + + &cs-str; + + + char * + name[128] + Name of the frontend + + fe_type_t + type + DVBv3 type. Should not be used on modern programs, as a + frontend may have more than one type. So, the DVBv5 API should + be used instead to enumerate and select the frontend type. + + uint32_t + frequency_min + Minimal frequency supported by the frontend + + uint32_t + frequency_max + Maximal frequency supported by the frontend + + uint32_t + frequency_stepsize + Frequency step - all frequencies are multiple of this value + + uint32_t + frequency_tolerance + Tolerance of the frequency + + uint32_t + symbol_rate_min + Minimal symbol rate (for Cable/Satellite systems), in bauds + + uint32_t + symbol_rate_max + Maximal symbol rate (for Cable/Satellite systems), in bauds + + uint32_t + symbol_rate_tolerance + Maximal symbol rate tolerance, in ppm + + uint32_t + notifier_delay + Deprecated. Not used by any driver. + + &fe-caps; + caps + Capabilities supported by the frontend + + + +
+ + + NOTE: The frequencies are specified in Hz for Terrestrial and Cable + systems. They're specified in kHz for Satellite systems + +
+frontend capabilities + +Capabilities describe what a frontend can do. Some capabilities are + supported only on some specific frontend types. + + + enum fe_caps + + &cs-def; + + + ID + Description + + + + + FE_IS_STUPID + There's something wrong at the frontend, and it can't + report its capabilities + + + FE_CAN_INVERSION_AUTO + The frontend is capable of auto-detecting inversion + + + FE_CAN_FEC_1_2 + The frontend supports FEC 1/2 + + + FE_CAN_FEC_2_3 + The frontend supports FEC 2/3 + + + FE_CAN_FEC_3_4 + The frontend supports FEC 3/4 + + + FE_CAN_FEC_4_5 + The frontend supports FEC 4/5 + + + FE_CAN_FEC_5_6 + The frontend supports FEC 5/6 + + + FE_CAN_FEC_6_7 + The frontend supports FEC 6/7 + + + FE_CAN_FEC_7_8 + The frontend supports FEC 7/8 + + + FE_CAN_FEC_8_9 + The frontend supports FEC 8/9 + + + FE_CAN_FEC_AUTO + The frontend can autodetect FEC. + + + FE_CAN_QPSK + The frontend supports QPSK modulation + + + FE_CAN_QAM_16 + The frontend supports 16-QAM modulation + + + FE_CAN_QAM_32 + The frontend supports 32-QAM modulation + + + FE_CAN_QAM_64 + The frontend supports 64-QAM modulation + + + FE_CAN_QAM_128 + The frontend supports 128-QAM modulation + + + FE_CAN_QAM_256 + The frontend supports 256-QAM modulation + + + FE_CAN_QAM_AUTO + The frontend can autodetect modulation + + + FE_CAN_TRANSMISSION_MODE_AUTO + The frontend can autodetect the transmission mode + + + FE_CAN_BANDWIDTH_AUTO + The frontend can autodetect the bandwidth + + + FE_CAN_GUARD_INTERVAL_AUTO + The frontend can autodetect the guard interval + + + FE_CAN_HIERARCHY_AUTO + The frontend can autodetect hierarch + + + FE_CAN_8VSB + The frontend supports 8-VSB modulation + + + FE_CAN_16VSB + The frontend supports 16-VSB modulation + + + FE_HAS_EXTENDED_CAPS + Currently, unused + + + FE_CAN_MULTISTREAM + The frontend supports multistream filtering + + + FE_CAN_TURBO_FEC + The frontend supports turbo FEC modulation + + + FE_CAN_2G_MODULATION + The frontend supports "2nd generation modulation" (DVB-S2/T2)> + + + FE_NEEDS_BENDING + Not supported anymore, don't use it + + + FE_CAN_RECOVER + The frontend can recover from a cable unplug automatically + + + FE_CAN_MUTE_TS + The frontend can stop spurious TS data output + + + +
+
+ diff --git a/Documentation/DocBook/media/dvb/fe-read-status.xml b/Documentation/DocBook/media/dvb/fe-read-status.xml new file mode 100644 index 000000000000..9c1810ae920d --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-read-status.xml @@ -0,0 +1,103 @@ + + + ioctl FE_READ_STATUS + &manvol; + + + + FE_READ_STATUS + Returns status information about the front-end. This call only + requires read-only access to the device + + + + + + int ioctl + int fd + int request + &fe-status; *argp + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_READ_STATUS + + + + argp + + pointer to &fe-status; + + + + + + + Description + + All DVB frontend devices support the +FE_READ_STATUS ioctl. It is used to check about the +locking status of the frontend after being tuned. The ioctl takes a +pointer to a 16-bits number where the status will be written. +&return-value-dvb;. + + + +
+enum fe_status + +The enum fe_status is used to indicate the current state + and/or state changes of the frontend hardware. + + + enum fe_status + + &cs-def; + + + ID + Description + + + + + FE_HAS_SIGNAL + The frontend has found something above the noise level + + FE_HAS_CARRIER + The frontend has found a DVB signal + + FE_HAS_VITERBI + The frontend FEC inner coding (Viterbi, LDPC or other inner code) is stable + + FE_HAS_SYNC + Synchronization bytes was found + + FE_HAS_LOCK + The DVB were locked and everything is working + + FE_TIMEDOUT + no lock within the last about 2 seconds + + FE_REINIT + The frontend was reinitialized, application is + recommended to reset DiSEqC, tone and parameters + + + +
+
+ diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 659f71ab67ef..079f631cc848 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -37,7 +37,7 @@ specification is available at FE_GET_INFO.
-&sub-frontend_get_info; +&sub-fe-get-info;
Querying frontend status @@ -46,7 +46,7 @@ specification is available at FE_READ_STATUS.
-&sub-frontend_read_status; +&sub-fe-read-status; &sub-dvbproperty; diff --git a/Documentation/DocBook/media/dvb/frontend_get_info.xml b/Documentation/DocBook/media/dvb/frontend_get_info.xml deleted file mode 100644 index b98a9a5e74d3..000000000000 --- a/Documentation/DocBook/media/dvb/frontend_get_info.xml +++ /dev/null @@ -1,265 +0,0 @@ - - - ioctl FE_GET_INFO - &manvol; - - - - FE_GET_INFO - Query DVB frontend capabilities and returns information about - the front-end. This call only requires read-only access to the device - - - - - - int ioctl - int fd - int request - &dvb-frontend-info; *argp - - - - - - Arguments - - - fd - - &fe_fd; - - - - request - - FE_GET_INFO - - - - argp - - pointer to struct &dvb-frontend-info; - - - - - - - Description - - All DVB frontend devices support the -FE_GET_INFO ioctl. It is used to identify -kernel devices compatible with this specification and to obtain -information about driver and hardware capabilities. The ioctl takes a -pointer to dvb_frontend_info which is filled by the driver. When the -driver is not compatible with this specification the ioctl returns an error &return-value-dvb;. - - - - struct <structname>dvb_frontend_info</structname> - - &cs-str; - - - char * - name[128] - Name of the frontend - - fe_type_t - type - DVBv3 type. Should not be used on modern programs, as a - frontend may have more than one type. So, the DVBv5 API should - be used instead to enumerate and select the frontend type. - - uint32_t - frequency_min - Minimal frequency supported by the frontend - - uint32_t - frequency_max - Maximal frequency supported by the frontend - - uint32_t - frequency_stepsize - Frequency step - all frequencies are multiple of this value - - uint32_t - frequency_tolerance - Tolerance of the frequency - - uint32_t - symbol_rate_min - Minimal symbol rate (for Cable/Satellite systems), in bauds - - uint32_t - symbol_rate_max - Maximal symbol rate (for Cable/Satellite systems), in bauds - - uint32_t - symbol_rate_tolerance - Maximal symbol rate tolerance, in ppm - - uint32_t - notifier_delay - Deprecated. Not used by any driver. - - &fe-caps; - caps - Capabilities supported by the frontend - - - -
- - - NOTE: The frequencies are specified in Hz for Terrestrial and Cable - systems. They're specified in kHz for Satellite systems - -
-frontend capabilities - -Capabilities describe what a frontend can do. Some capabilities are - supported only on some specific frontend types. - - - enum fe_caps - - &cs-def; - - - ID - Description - - - - - FE_IS_STUPID - There's something wrong at the frontend, and it can't - report its capabilities - - - FE_CAN_INVERSION_AUTO - The frontend is capable of auto-detecting inversion - - - FE_CAN_FEC_1_2 - The frontend supports FEC 1/2 - - - FE_CAN_FEC_2_3 - The frontend supports FEC 2/3 - - - FE_CAN_FEC_3_4 - The frontend supports FEC 3/4 - - - FE_CAN_FEC_4_5 - The frontend supports FEC 4/5 - - - FE_CAN_FEC_5_6 - The frontend supports FEC 5/6 - - - FE_CAN_FEC_6_7 - The frontend supports FEC 6/7 - - - FE_CAN_FEC_7_8 - The frontend supports FEC 7/8 - - - FE_CAN_FEC_8_9 - The frontend supports FEC 8/9 - - - FE_CAN_FEC_AUTO - The frontend can autodetect FEC. - - - FE_CAN_QPSK - The frontend supports QPSK modulation - - - FE_CAN_QAM_16 - The frontend supports 16-QAM modulation - - - FE_CAN_QAM_32 - The frontend supports 32-QAM modulation - - - FE_CAN_QAM_64 - The frontend supports 64-QAM modulation - - - FE_CAN_QAM_128 - The frontend supports 128-QAM modulation - - - FE_CAN_QAM_256 - The frontend supports 256-QAM modulation - - - FE_CAN_QAM_AUTO - The frontend can autodetect modulation - - - FE_CAN_TRANSMISSION_MODE_AUTO - The frontend can autodetect the transmission mode - - - FE_CAN_BANDWIDTH_AUTO - The frontend can autodetect the bandwidth - - - FE_CAN_GUARD_INTERVAL_AUTO - The frontend can autodetect the guard interval - - - FE_CAN_HIERARCHY_AUTO - The frontend can autodetect hierarch - - - FE_CAN_8VSB - The frontend supports 8-VSB modulation - - - FE_CAN_16VSB - The frontend supports 16-VSB modulation - - - FE_HAS_EXTENDED_CAPS - Currently, unused - - - FE_CAN_MULTISTREAM - The frontend supports multistream filtering - - - FE_CAN_TURBO_FEC - The frontend supports turbo FEC modulation - - - FE_CAN_2G_MODULATION - The frontend supports "2nd generation modulation" (DVB-S2/T2)> - - - FE_NEEDS_BENDING - Not supported anymore, don't use it - - - FE_CAN_RECOVER - The frontend can recover from a cable unplug automatically - - - FE_CAN_MUTE_TS - The frontend can stop spurious TS data output - - - -
-
- diff --git a/Documentation/DocBook/media/dvb/frontend_read_status.xml b/Documentation/DocBook/media/dvb/frontend_read_status.xml deleted file mode 100644 index 9c1810ae920d..000000000000 --- a/Documentation/DocBook/media/dvb/frontend_read_status.xml +++ /dev/null @@ -1,103 +0,0 @@ - - - ioctl FE_READ_STATUS - &manvol; - - - - FE_READ_STATUS - Returns status information about the front-end. This call only - requires read-only access to the device - - - - - - int ioctl - int fd - int request - &fe-status; *argp - - - - - - Arguments - - - fd - - &fe_fd; - - - - request - - FE_READ_STATUS - - - - argp - - pointer to &fe-status; - - - - - - - Description - - All DVB frontend devices support the -FE_READ_STATUS ioctl. It is used to check about the -locking status of the frontend after being tuned. The ioctl takes a -pointer to a 16-bits number where the status will be written. -&return-value-dvb;. - - - -
-enum fe_status - -The enum fe_status is used to indicate the current state - and/or state changes of the frontend hardware. - - - enum fe_status - - &cs-def; - - - ID - Description - - - - - FE_HAS_SIGNAL - The frontend has found something above the noise level - - FE_HAS_CARRIER - The frontend has found a DVB signal - - FE_HAS_VITERBI - The frontend FEC inner coding (Viterbi, LDPC or other inner code) is stable - - FE_HAS_SYNC - Synchronization bytes was found - - FE_HAS_LOCK - The DVB were locked and everything is working - - FE_TIMEDOUT - no lock within the last about 2 seconds - - FE_REINIT - The frontend was reinitialized, application is - recommended to reset DiSEqC, tone and parameters - - - -
-
- -- cgit v1.2.3 From 0f16290e6fade03dd5aefc9c734b5ad7226b7dfd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 18:15:26 -0300 Subject: [media] DocBook: move FE_GET_PROPERTY to its own xml file That helps the xref logic at the Makefile to point to the right place. Also, it becomes more organized and easier to maintain if each ioctl have its own xml file. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 84 +--------------------- .../DocBook/media/dvb/fe-get-property.xml | 81 +++++++++++++++++++++ 2 files changed, 83 insertions(+), 82 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-get-property.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 48faf5089675..12a31e628d34 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -35,6 +35,8 @@ the capability ioctls weren't implemented yet via the new way. API is to replace the ioctl's were the struct dvb_frontend_parameters were used. +&sub-fe-get-property; +
DTV stats type @@ -1247,85 +1249,3 @@ enum fe_interleaving {
- - - - ioctl FE_SET_PROPERTY, FE_GET_PROPERTY - &manvol; - - - - FE_SET_PROPERTY - FE_GET_PROPERTY - FE_SET_PROPERTY sets one or more frontend properties. - FE_GET_PROPERTY returns one or more frontend properties. - - - - - - int ioctl - int fd - int request - &dtv-property; *argp - - - - - - Arguments - - - fd - - &fe_fd; - - - - request - - FE_SET_PROPERTY, FE_GET_PROPERTY - - - - argp - - pointer to &dtv-property; - - - - - - - Description - - All DVB frontend devices support the -FE_SET_PROPERTY and FE_GET_PROPERTY -ioctls. The supported properties and statistics depends on the delivery system -and on the device: - - - FE_SET_PROPERTY: - -This ioctl is used to set one or more - frontend properties. -This is the basic command to request the frontend to tune into some - frequency and to start decoding the digital TV signal. -This call requires read/write access to the device. -At return, the values are updated to reflect the - actual parameters used. - - - - FE_GET_PROPERTY: - -This ioctl is used to get properties and -statistics from the frontend. -No properties are changed, and statistics aren't reset. -This call only requires read-only access to the device. - - - -&return-value-dvb;. - - diff --git a/Documentation/DocBook/media/dvb/fe-get-property.xml b/Documentation/DocBook/media/dvb/fe-get-property.xml new file mode 100644 index 000000000000..b121fe5380ca --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-get-property.xml @@ -0,0 +1,81 @@ + + + ioctl FE_SET_PROPERTY, FE_GET_PROPERTY + &manvol; + + + + FE_SET_PROPERTY + FE_GET_PROPERTY + FE_SET_PROPERTY sets one or more frontend properties. + FE_GET_PROPERTY returns one or more frontend properties. + + + + + + int ioctl + int fd + int request + &dtv-property; *argp + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_PROPERTY, FE_GET_PROPERTY + + + + argp + + pointer to &dtv-property; + + + + + + + Description + + All DVB frontend devices support the +FE_SET_PROPERTY and FE_GET_PROPERTY +ioctls. The supported properties and statistics depends on the delivery system +and on the device: + + + FE_SET_PROPERTY: + +This ioctl is used to set one or more + frontend properties. +This is the basic command to request the frontend to tune into some + frequency and to start decoding the digital TV signal. +This call requires read/write access to the device. +At return, the values are updated to reflect the + actual parameters used. + + + + FE_GET_PROPERTY: + +This ioctl is used to get properties and +statistics from the frontend. +No properties are changed, and statistics aren't reset. +This call only requires read-only access to the device. + + + +&return-value-dvb;. + + -- cgit v1.2.3 From 3d7f9c9b175c349df3051ecc852691562f2661c3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 18:36:26 -0300 Subject: [media] DocBook: reformat FE_SET_FRONTEND_TUNE_MODE ioctl Use the proper format for FE_SET_FRONTEND_TUNE_MODE documentation. Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb/fe-set-frontend-tune-mode.xml | 64 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 32 +---------- 2 files changed, 65 insertions(+), 31 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml b/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml new file mode 100644 index 000000000000..30bc99dc4c1c --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml @@ -0,0 +1,64 @@ + + + ioctl FE_SET_FRONTEND_TUNE_MODE + &manvol; + + + + FE_SET_FRONTEND_TUNE_MODE + Allow setting tuner mode flags to the frontend. + + + + + + int ioctl + int fd + int request + unsigned int flags + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_FRONTEND_TUNE_MODE + + + + flags + + Valid flags: + + 0 - normal tune mode + FE_TUNE_MODE_ONESHOT - When set, this flag will + disable any zigzagging or other "normal" tuning behaviour. + Additionally, there will be no automatic monitoring of the + lock status, and hence no frontend events will be + generated. If a frontend device is closed, this flag will + be automatically turned off when the device is reopened + read-write. + + + + + + + + Description + + Allow setting tuner mode flags to the frontend, between 0 (normal) + or FE_TUNE_MODE_ONESHOT mode +&return-value-dvb; + + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 079f631cc848..645f92bec767 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -738,37 +738,7 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_SET_FRONTEND_TUNE_MODE -DESCRIPTION - - -Allow setting tuner mode flags to the frontend. - - - -SYNOPSIS - - -int ioctl(int fd, int request = -FE_SET_FRONTEND_TUNE_MODE, unsigned int flags); - - - -PARAMETERS - - - unsigned int flags - - - -FE_TUNE_MODE_ONESHOT When set, this flag will disable any zigzagging or other "normal" tuning behaviour. Additionally, there will be no automatic monitoring of the lock status, and hence no frontend events will be generated. If a frontend device is closed, this flag will be automatically turned off when the device is reopened read-write. - - - - -&return-value-dvb; -
+&sub-fe-set-frontend-tune-mode;
-- cgit v1.2.3 From 50f88f3da09de7e5303b6a22d012d59063141239 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 18:48:33 -0300 Subject: [media] DocBook: reformat FE_ENABLE_HIGH_LNB_VOLTAGE ioctl Use the proper format for FE_ENABLE_HIGH_LNB_VOLTAGE documentation. Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb/fe-enable-high-lnb-voltage.xml | 61 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 50 +----------------- 2 files changed, 62 insertions(+), 49 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml b/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml new file mode 100644 index 000000000000..3ee08a82cc7c --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml @@ -0,0 +1,61 @@ + + + ioctl FE_ENABLE_HIGH_LNB_VOLTAGE + &manvol; + + + + FE_ENABLE_HIGH_LNB_VOLTAGE + Select output DC level between normal LNBf voltages or higher + LNBf voltages. + + + + + + int ioctl + int fd + int request + unsigned int high + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_ENABLE_HIGH_LNB_VOLTAGE + + + + high + + Valid flags: + + 0 - normal 13V and 18V. + >0 - enables slightly higher voltages instead of + 13/18V, in order to compensate for long antena cables. + + + + + + + + Description + + Select output DC level between normal LNBf voltages or higher + LNBf voltages between 0 (normal) or a value grater than 0 for higher + voltages. +&return-value-dvb; + + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 645f92bec767..bb2cd9ef3b03 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -689,55 +689,7 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_ENABLE_HIGH_LNB_VOLTAGE -DESCRIPTION - - -If high != 0 enables slightly higher voltages instead of 13/18V (to compensate - for long cables). This call requires read/write permissions. Not all DVB - adapters support this ioctl. - - - -SYNOPSIS - - -int ioctl(int fd, int request = - FE_ENABLE_HIGH_LNB_VOLTAGE, int high); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_SET_VOLTAGE for this command. - - -int high - -The requested bus voltage. - - - -&return-value-dvb; -
- +&sub-fe-enable-high-lnb-voltage; &sub-fe-set-frontend-tune-mode; -- cgit v1.2.3 From d6b6d346e5605ee2af0f0349e71901121b984258 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 26 May 2015 19:33:58 -0300 Subject: [media] DocBook: better document FE_SET_VOLTAGE ioctl Use the proper format for FE_SET_VOLTAGE documentation and fix the documentation. The description for the enum is not 100%, and it is missing the voltage off value. Also, it is better to keep the enum description together with the ioctl, as both are used together. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-set-voltage.xml | 94 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 62 +------------- include/uapi/linux/dvb/frontend.h | 6 +- 3 files changed, 99 insertions(+), 63 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-set-voltage.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-set-voltage.xml b/Documentation/DocBook/media/dvb/fe-set-voltage.xml new file mode 100644 index 000000000000..a1ee5f9c28e0 --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-set-voltage.xml @@ -0,0 +1,94 @@ + + + ioctl FE_SET_VOLTAGE + &manvol; + + + + FE_SET_VOLTAGE + Allow setting the DC level sent to the antenna subsystem. + + + + + + int ioctl + int fd + int request + &fe-sec-voltage; *voltage + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_VOLTAGE + + + + pointer to &fe-sec-voltage; + + + + + + Description + +This ioctl allows to set the DC voltage level sent through the antenna + cable to 13V, 18V or off. +Usually, a satellital antenna subsystems require that the digital TV + device to send a DC voltage to feed power to the LNBf. Depending on the + LNBf type, the polarization or the intermediate frequency (IF) of the LNBf + can controlled by the voltage level. Other devices (for example, the ones + that implement DISEqC and multipoint LNBf's don't need to control the + voltage level, provided that either 13V or 18V is sent to power up the + LNBf. +NOTE: if more than one device is connected to the same antenna, + setting a voltage level may interfere on other devices, as they may lose + the capability of setting polarization or IF. So, on those + cases, setting the voltage to SEC_VOLTAGE_OFF while the device is not is + used is recommended. + +&return-value-dvb; + + +
+enum fe_sec_voltage + + + enum fe_status + + &cs-def; + + + ID + Description + + + + + SEC_VOLTAGE_13 + Set DC voltage level to 13V + + SEC_VOLTAGE_18 + Set DC voltage level to 18V + + SEC_VOLTAGE_OFF + Don't send any voltage to the antenna + + + +
+
+ + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index bb2cd9ef3b03..584c759b6bbe 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -75,19 +75,6 @@ specification is available at -
-diseqc slave reply -The voltage is usually used with non-DiSEqC capable LNBs to switch the polarzation -(horizontal/vertical). When using DiSEqC epuipment this voltage has to be switched -consistently to the DiSEqC commands as described in the DiSEqC spec. - - typedef enum fe_sec_voltage { - SEC_VOLTAGE_13, - SEC_VOLTAGE_18 - } fe_sec_voltage_t; - -
-
SEC continuous tone @@ -641,54 +628,7 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_SET_VOLTAGE -DESCRIPTION - - -This call is used to set the bus voltage. This call requires read/write - permissions. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_SET_VOLTAGE, - fe_sec_voltage_t voltage); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_SET_VOLTAGE for this command. - - -fe_sec_voltage_t - voltage - -The requested bus voltage. - - - -&return-value-dvb; -
- +&sub-fe-set-voltage; &sub-fe-enable-high-lnb-voltage; &sub-fe-set-frontend-tune-mode; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index ae481bc53a9c..c1ccbc82024c 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -105,11 +105,13 @@ struct dvb_diseqc_slave_reply { }; /* errorcode when no message was received */ -typedef enum fe_sec_voltage { +enum fe_sec_voltage { SEC_VOLTAGE_13, SEC_VOLTAGE_18, SEC_VOLTAGE_OFF -} fe_sec_voltage_t; +}; + +typedef enum fe_sec_voltage fe_sec_voltage_t; typedef enum fe_sec_tone_mode { -- cgit v1.2.3 From 6dc59e7a195fc8852e98d64805f44c46c35e40cd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 27 May 2015 07:15:50 -0300 Subject: [media] DocBook: better document FE_SET_TONE ioctl Use the proper format for FE_SET_TONE documentation and improve the documentation. Keep the enum fe_sec_tone_mode description together with the ioctl, as both are used together. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-set-tone.xml | 88 +++++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 61 +---------------- include/uapi/linux/dvb/frontend.h | 6 +- 3 files changed, 93 insertions(+), 62 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-set-tone.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-set-tone.xml b/Documentation/DocBook/media/dvb/fe-set-tone.xml new file mode 100644 index 000000000000..b4b1f5303170 --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-set-tone.xml @@ -0,0 +1,88 @@ + + + ioctl FE_SET_TONE + &manvol; + + + + FE_SET_TONE + Sets/resets the generation of the continuous 22kHz tone. + + + + + + int ioctl + int fd + int request + &fe-sec-tone-mode; *tone + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_TONE + + + + pointer to &fe-sec-tone-mode; + + + + + + Description + +This ioctl is used to set the generation of the continuous 22kHz tone. + This call requires read/write permissions. +Usually, satellital antenna subsystems require that the digital TV + device to send a 22kHz tone in order to select between high/low band on + some dual-band LNBf. It is also used to send signals to DiSEqC equipment, + but this is done using the DiSEqC ioctls. +NOTE: if more than one device is connected to the same antenna, + setting a tone may interfere on other devices, as they may lose + the capability of selecting the band. So, it is recommended that + applications would change to SEC_TONE_OFF when the device is not used. + +&return-value-dvb; + + +
+enum fe_sec_voltage + + + enum fe_sec_tone_mode + + &cs-def; + + + ID + Description + + + + + SEC_TONE_ON + Sends a 22kHz tone burst to the antenna + + SEC_TONE_OFF + Don't send a 22kHz tone to the antenna + (except if the FE_DISEQC_* ioctls are called) + + + +
+
+ + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 584c759b6bbe..f05da4abb3fe 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -75,21 +75,6 @@ specification is available at -
-SEC continuous tone - -The continuous 22KHz tone is usually used with non-DiSEqC capable LNBs to switch the -high/low band of a dual-band LNB. When using DiSEqC epuipment this voltage has to -be switched consistently to the DiSEqC commands as described in the DiSEqC -spec. - - typedef enum fe_sec_tone_mode { - SEC_TONE_ON, - SEC_TONE_OFF - } fe_sec_tone_mode_t; - -
-
SEC tone burst @@ -582,52 +567,8 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_SET_TONE -DESCRIPTION - - -This call is used to set the generation of the continuous 22kHz tone. This call - requires read/write permissions. - - -SYNOPSIS - - -int ioctl(int fd, int request = FE_SET_TONE, - fe_sec_tone_mode_t tone); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_SET_TONE for this command. - - -fe_sec_tone_mode_t - tone - -The requested tone generation mode (on/off). - - -&return-value-dvb; -
+&sub-fe-set-tone; &sub-fe-set-voltage; &sub-fe-enable-high-lnb-voltage; &sub-fe-set-frontend-tune-mode; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index c1ccbc82024c..1a098819473f 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -114,10 +114,12 @@ enum fe_sec_voltage { typedef enum fe_sec_voltage fe_sec_voltage_t; -typedef enum fe_sec_tone_mode { +enum fe_sec_tone_mode { SEC_TONE_ON, SEC_TONE_OFF -} fe_sec_tone_mode_t; +}; + +typedef enum fe_sec_tone_mode fe_sec_tone_mode_t; typedef enum fe_sec_mini_cmd { -- cgit v1.2.3 From 81959d996a3b6ea542ebffc7e394530f4638c6ca Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 27 May 2015 22:20:14 -0300 Subject: [media] DocBook: better document FE_DISEQC_SEND_BURST ioctl Use the proper format for FE_DISEQC_SEND_BURST documentation and improve the documentation. Keep the enum fe_sec_mini_cmd description together with the ioctl, as both are used together. Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/dvb/fe-diseqc-send-burst.xml | 86 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 67 +---------------- include/uapi/linux/dvb/frontend.h | 6 +- 3 files changed, 91 insertions(+), 68 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml new file mode 100644 index 000000000000..d1a798048641 --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml @@ -0,0 +1,86 @@ + + + ioctl FE_DISEQC_SEND_BURST + &manvol; + + + + FE_DISEQC_SEND_BURST + Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection. + + + + + + int ioctl + int fd + int request + &fe-sec-mini-cmd; *tone + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_DISEQC_SEND_BURST + + + + pointer to &fe-sec-mini-cmd; + + + + + + Description + +This ioctl is used to set the generation of a 22kHz tone burst for mini + DiSEqC satellite + selection for 2x1 switches. + This call requires read/write permissions. +It provides support for what's specified at + Digital Satellite Equipment Control + (DiSEqC) - Simple "ToneBurst" Detection Circuit specification. + +&return-value-dvb; + + +
+enum fe_sec_mini_cmd + + + enum fe_sec_tone_mode + + &cs-def; + + + ID + Description + + + + + SEC_MINI_A + Sends a mini-DiSEqC 22kHz '0' Tone Burst to + select satellite-A + + SEC_MINI_B + Sends a mini-DiSEqC 22kHz '1' Data Burst to + select satellite-B + + + +
+
+ + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index f05da4abb3fe..17050152a48a 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -75,23 +75,6 @@ specification is available at -
-SEC tone burst - -The 22KHz tone burst is usually used with non-DiSEqC capable switches to select -between two connected LNBs/satellites. When using DiSEqC epuipment this voltage has to -be switched consistently to the DiSEqC commands as described in the DiSEqC -spec. - - typedef enum fe_sec_mini_cmd { - SEC_MINI_A, - SEC_MINI_B - } fe_sec_mini_cmd_t; - - - -
-
frontend spectral inversion The Inversion field can take one of these values: @@ -519,55 +502,7 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_DISEQC_SEND_BURST -DESCRIPTION - - -This ioctl call is used to send a 22KHz tone burst. - - - -SYNOPSIS - - -int ioctl(int fd, int request = - FE_DISEQC_SEND_BURST, fe_sec_mini_cmd_t burst); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_DISEQC_SEND_BURST for this command. - - -fe_sec_mini_cmd_t - burst - -burst A or B. - - - -&return-value-dvb; -
- - +&sub-fe-diseqc-send-burst; &sub-fe-set-tone; &sub-fe-set-voltage; &sub-fe-enable-high-lnb-voltage; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 1a098819473f..dd64e6d5d881 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -122,10 +122,12 @@ enum fe_sec_tone_mode { typedef enum fe_sec_tone_mode fe_sec_tone_mode_t; -typedef enum fe_sec_mini_cmd { +enum fe_sec_mini_cmd { SEC_MINI_A, SEC_MINI_B -} fe_sec_mini_cmd_t; +}; + +typedef enum fe_sec_mini_cmd fe_sec_mini_cmd_t; /** -- cgit v1.2.3 From 32b64436584b402e717450b041a31f1f00a7b107 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 12:37:00 -0300 Subject: [media] DocBook: better document FE_DISEQC_RECV_SLAVE_REPLY Use the new format for the ioctl documentation and put the struct dvb_diseqc_slave_reply together with the ioctl. Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb/fe-diseqc-recv-slave-reply.xml | 78 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 64 +----------------- 2 files changed, 79 insertions(+), 63 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml b/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml new file mode 100644 index 000000000000..de68b5b57476 --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml @@ -0,0 +1,78 @@ + + + ioctl FE_DISEQC_RECV_SLAVE_REPLY + &manvol; + + + + FE_DISEQC_RECV_SLAVE_REPLY + Receives reply from a DiSEqC 2.0 command + + + + + + int ioctl + int fd + int request + &dvb-diseqc-slave-reply; *argp + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_DISEQC_RECV_SLAVE_REPLY + + + + argp + + pointer to &dvb-diseqc-slave-reply; + + + + + + + Description + + Receives reply from a DiSEqC 2.0 command. +&return-value-dvb; + + + struct <structname>dvb_diseqc_slave_reply</structname> + + &cs-str; + + + uint8_t + msg[4] + DiSEqC message (framing, data[3]) + + uint8_t + msg_len + Length of the DiSEqC message. Valid values are 0 to 4, + where 0 means no msg + + int + timeout + Return from ioctl after timeout ms with errorcode when no + message was received + + + +
+ + + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 17050152a48a..cba6c355637c 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -62,19 +62,6 @@ specification is available at -
-diseqc slave reply - -A reply to the frontend from DiSEqC 2.0 capable equipment. - - struct dvb_diseqc_slave_reply { - uint8_t msg [4]; /⋆ { framing, data [3] } ⋆/ - uint8_t msg_len; /⋆ valid values are 0...4, 0 means no msg ⋆/ - int timeout; /⋆ return from ioctl after timeout ms with ⋆/ - }; /⋆ errorcode when no message was received ⋆/ - -
-
frontend spectral inversion The Inversion field can take one of these values: @@ -452,56 +439,7 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_DISEQC_RECV_SLAVE_REPLY -DESCRIPTION - - -This ioctl call is used to receive reply to a DiSEqC 2.0 command. - - - -SYNOPSIS - - -int ioctl(int fd, int request = - FE_DISEQC_RECV_SLAVE_REPLY, struct - dvb_diseqc_slave_reply ⋆reply); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_DISEQC_RECV_SLAVE_REPLY for this - command. - - -struct - dvb_diseqc_slave_reply - *reply - -Pointer to the command to be received. - - -&return-value-dvb; -
- +&sub-fe-diseqc-recv-slave-reply; &sub-fe-diseqc-send-burst; &sub-fe-set-tone; &sub-fe-set-voltage; -- cgit v1.2.3 From db2a4ee870cd2743c908673151444382e78c4e07 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 12:49:34 -0300 Subject: [media] DocBook: better document FE_DISEQC_SEND_MASTER_CMD Use the new format for the ioctl documentation and put the struct dvb_diseqc_slave_reply together with the ioctl. Signed-off-by: Mauro Carvalho Chehab --- .../media/dvb/fe-diseqc-send-master-cmd.xml | 72 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 63 +------------------ 2 files changed, 73 insertions(+), 62 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml b/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml new file mode 100644 index 000000000000..d4d6cd8dfc6c --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml @@ -0,0 +1,72 @@ + + + ioctl FE_DISEQC_SEND_MASTER_CMD + &manvol; + + + + FE_DISEQC_SEND_MASTER_CMD + Sends a DiSEqC command + + + + + + int ioctl + int fd + int request + &dvb-diseqc-master-cmd; *argp + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_DISEQC_SEND_MASTER_CMD + + + + argp + + pointer to &dvb-diseqc-master-cmd; + + + + + + + Description + + Sends a DiSEqC command to the antenna subsystem. +&return-value-dvb; + + + struct <structname>dvb_diseqc_master_cmd</structname> + + &cs-str; + + + uint8_t + msg[6] + DiSEqC message (framing, address, command, data[3]) + + uint8_t + msg_len + Length of the DiSEqC message. Valid values are 3 to 6 + + + +
+ + + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index cba6c355637c..f7bb2db07c23 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -50,18 +50,6 @@ specification is available at &sub-dvbproperty; -
-diseqc master command - -A message sent from the frontend to DiSEqC capable equipment. - - struct dvb_diseqc_master_cmd { - uint8_t msg [6]; /⋆ { framing, address, command, data[3] } ⋆/ - uint8_t msg_len; /⋆ valid values are 3...6 ⋆/ - }; - -
-
frontend spectral inversion The Inversion field can take one of these values: @@ -389,56 +377,7 @@ typedef enum fe_hierarchy { &return-value-dvb;
-
-FE_DISEQC_SEND_MASTER_CMD -DESCRIPTION - - -This ioctl call is used to send a a DiSEqC command. - - -SYNOPSIS - - -int ioctl(int fd, int request = - FE_DISEQC_SEND_MASTER_CMD, struct - dvb_diseqc_master_cmd ⋆cmd); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_DISEQC_SEND_MASTER_CMD for this - command. - - -struct - dvb_diseqc_master_cmd - *cmd - -Pointer to the command to be transmitted. - - - -&return-value-dvb; -
- +&sub-fe-diseqc-send-master-cmd; &sub-fe-diseqc-recv-slave-reply; &sub-fe-diseqc-send-burst; &sub-fe-set-tone; -- cgit v1.2.3 From 26b2574fbbff393cde9155d37fb8f958927b3758 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 13:10:38 -0300 Subject: [media] DocBook: better document FE_DISEQC_RESET_OVERLOAD Use the new format for the ioctl documentation and put the struct dvb_diseqc_slave_reply together with the ioctl. Signed-off-by: Mauro Carvalho Chehab --- .../DocBook/media/dvb/fe-diseqc-reset-overload.xml | 51 ++++++++++++++++++++++ Documentation/DocBook/media/dvb/frontend.xml | 45 +------------------ 2 files changed, 52 insertions(+), 44 deletions(-) create mode 100644 Documentation/DocBook/media/dvb/fe-diseqc-reset-overload.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-reset-overload.xml b/Documentation/DocBook/media/dvb/fe-diseqc-reset-overload.xml new file mode 100644 index 000000000000..c104df77ecd0 --- /dev/null +++ b/Documentation/DocBook/media/dvb/fe-diseqc-reset-overload.xml @@ -0,0 +1,51 @@ + + + ioctl FE_DISEQC_RESET_OVERLOAD + &manvol; + + + + FE_DISEQC_RESET_OVERLOAD + Restores the power to the antenna subsystem, if it was powered + off due to power overload. + + + + + + int ioctl + int fd + int request + NULL + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_DISEQC_RESET_OVERLOAD + + + + + + + Description + + If the bus has been automatically powered off due to power overload, this ioctl + call restores the power to the bus. The call requires read/write access to the + device. This call has no effect if the device is manually powered off. Not all + DVB adapters support this ioctl. +&return-value-dvb; + + diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index f7bb2db07c23..86bd9ed9d7f8 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -333,50 +333,7 @@ typedef enum fe_hierarchy { - -
-FE_DISEQC_RESET_OVERLOAD -DESCRIPTION - - -If the bus has been automatically powered off due to power overload, this ioctl - call restores the power to the bus. The call requires read/write access to the - device. This call has no effect if the device is manually powered off. Not all - DVB adapters support this ioctl. - - - -SYNOPSIS - - -int ioctl(int fd, int request = - FE_DISEQC_RESET_OVERLOAD); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals FE_DISEQC_RESET_OVERLOAD for this - command. - - - -&return-value-dvb; -
- +&sub-fe-diseqc-reset-overload; &sub-fe-diseqc-send-master-cmd; &sub-fe-diseqc-recv-slave-reply; &sub-fe-diseqc-send-burst; -- cgit v1.2.3 From b60da5b2037febd80e6ac680365eb828061c83df Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 13:10:52 -0300 Subject: [media] DocBook: better organize the function descriptions for frontend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the function ioctl definitions to the end of the chapter, at their importance. That makes the document better organized, as the DVB frontend system call index will look like: open() close() ioctl FE_GET_INFO — Query DVB frontend capabilities and returns information about the front-end. This call only requires read-only access to the device ioctl FE_READ_STATUS — Returns status information about the front-end. This call only requires read-only access to the device ioctl FE_SET_PROPERTY, FE_GET_PROPERTY — FE_SET_PROPERTY sets one or more frontend properties. FE_GET_PROPERTY returns one or more frontend properties. ioctl FE_DISEQC_RESET_OVERLOAD — Restores the power to the antenna subsystem, if it was powered off due to power overload. ioctl FE_DISEQC_SEND_MASTER_CMD — Sends a DiSEqC command ioctl FE_DISEQC_RECV_SLAVE_REPLY — Receives reply from a DiSEqC 2.0 command ioctl FE_DISEQC_SEND_BURST — Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection. ioctl FE_SET_TONE — Sets/resets the generation of the continuous 22kHz tone. ioctl FE_SET_VOLTAGE — Allow setting the DC level sent to the antenna subsystem. ioctl FE_ENABLE_HIGH_LNB_VOLTAGE — Select output DC level between normal LNBf voltages or higher LNBf voltages. ioctl FE_SET_FRONTEND_TUNE_MODE — Allow setting tuner mode flags to the frontend. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 2 -- Documentation/DocBook/media/dvb/frontend.xml | 7 +++---- 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 12a31e628d34..0fa4ccfd406d 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -35,8 +35,6 @@ the capability ioctls weren't implemented yet via the new way. API is to replace the ioctl's were the struct dvb_frontend_parameters were used. -&sub-fe-get-property; -
DTV stats type diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 86bd9ed9d7f8..bcee1d9fc73d 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -37,8 +37,6 @@ specification is available at FE_GET_INFO.
-&sub-fe-get-info; -
Querying frontend status @@ -46,8 +44,6 @@ specification is available at FE_READ_STATUS.
-&sub-fe-read-status; - &sub-dvbproperty;
@@ -333,6 +329,9 @@ typedef enum fe_hierarchy {
+&sub-fe-get-info; +&sub-fe-read-status; +&sub-fe-get-property; &sub-fe-diseqc-reset-overload; &sub-fe-diseqc-send-master-cmd; &sub-fe-diseqc-recv-slave-reply; -- cgit v1.2.3 From d27518ca0c6a33ecc11b7172fb68eb730301a841 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 14:43:06 -0300 Subject: [media] DocBook: fix FE_READ_STATUS argument description What's written there about the arguments for this ioctl is bogus: it doesn't return an enum (or a typedef) for enum fe_status. Instead, it returns a bitmask with the values defined by enum fe_status. Also, the size of the integer returned is not 16 bits, but, instead, sizeof(fe_status_t), e. g. sizeof(enum), with is arch-dependent. This should of course be fixed, but this should be done on a separate patch. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-read-status.xml | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-read-status.xml b/Documentation/DocBook/media/dvb/fe-read-status.xml index 9c1810ae920d..bbd0b5bb6b12 100644 --- a/Documentation/DocBook/media/dvb/fe-read-status.xml +++ b/Documentation/DocBook/media/dvb/fe-read-status.xml @@ -16,7 +16,7 @@ int ioctl int fd int request - &fe-status; *argp + unsigned int *status @@ -37,9 +37,10 @@ - argp + status - pointer to &fe-status; + pointer to a bitmask integer filled with the values defined by + &fe-status;. @@ -51,16 +52,19 @@ All DVB frontend devices support the FE_READ_STATUS ioctl. It is used to check about the locking status of the frontend after being tuned. The ioctl takes a -pointer to a 16-bits number where the status will be written. -&return-value-dvb;. +pointer to an integer where the status will be written. +NOTE: the size of status is actually sizeof(enum fe_status), with varies + according with the architecture. This needs to be fixed in the future. +&return-value-dvb;
-enum fe_status +int fe_status -The enum fe_status is used to indicate the current state - and/or state changes of the frontend hardware. +The fe_status parameter is used to indicate the current state + and/or state changes of the frontend hardware. It is produced using + the &fe-status; values on a bitmask enum fe_status -- cgit v1.2.3 From be1ad6e76ecaabe586f5687057eaccd46e71c3b2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 14:45:17 -0300 Subject: [media] DocBook: Provide a high-level description for DVB frontend Instead of just showing ioctls, let's add an introdutory text briefly explaining the DVB frontend API. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index bcee1d9fc73d..16a4648043d6 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -29,19 +29,29 @@ specification is available at Eutelsat. -
Querying frontend information -Information about the frontend can be queried with - FE_GET_INFO. +Usually, the first thing to do when the frontend is opened is to + check the frontend capabilities. This is done using FE_GET_INFO. This ioctl will enumerate + the DVB API version and other characteristics about the frontend, and + can be opened either in read only or read/write mode.
-Querying frontend status +Querying frontend status and statistics -Information about the frontend tuner locking status can be queried with - FE_READ_STATUS. +Once FE_SET_PROPERTY + is called, the frontend will run a kernel thread that will periodically + check for the tuner lock status and provide statistics about the quality + of the signal. +The information about the frontend tuner locking status can be queried + using FE_READ_STATUS. +Signal statistics are provided via FE_GET_PROPERTY. + Please notice that several statistics require the demodulator to be fully + locked (e. g. with FE_HAS_LOCK bit set). See + Frontend statistics indicators + for more details.
&sub-dvbproperty; -- cgit v1.2.3 From 2c2bc8ff97d5bde9f2d131d8728facba4a2190e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 15:44:55 -0300 Subject: [media] DocBook: add a proper description for dvb_frontend_info.fe_type The fe_type is deprecated at the DVB API. However, it may still be used by legacy DVBv3 applications. While this works with old devices, modern devices may support more than one delivery system. Add an explanation about that and a point to what should be used, instead, in order for legacy apps to support newer hardware. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend_legacy_api.xml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index e2817f830312..1eedc4ce0e4a 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -45,9 +45,19 @@ supported via the new FE_GET_PROPERTY/FE_GET_SET_PROPERTY ioctl's, using the DTV_DELIVERY_SYSTEM parameter. -The usage of this field is deprecated, as it doesn't report all supported standards, and -will provide an incomplete information for frontends that support multiple delivery systems. -Please use DTV_ENUM_DELSYS instead. +In the old days, &dvb-frontend-info; used to contain + fe_type_t field to indicate the delivery systems, + filled with either FE_QPSK, FE_QAM, FE_OFDM or FE_ATSC. While this is + still filled to keep backward compatibility, the usage of this + field is deprecated, as it can report just one delivery system, but some + devices support multiple delivery systems. Please use + DTV_ENUM_DELSYS instead. + +On devices that support multiple delivery systems, + &dvb-frontend-info;::fe_type_t is filled with the + currently standard, as selected by the last call to + FE_SET_PROPERTY + using the &DTV-DELIVERY-SYSTEM; property. -- cgit v1.2.3 From 997eb9039df27dfd5b1901e26ebae09d5dbe6cff Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 17:21:05 -0300 Subject: [media] DocBook: Better document enum fe_modulation Instead of using programlisting, use a table, as this provides a better view of the structure. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 91 +++++++++++++++++++------ Documentation/DocBook/media/dvb/frontend.xml | 26 ------- include/uapi/linux/dvb/frontend.h | 6 +- 3 files changed, 76 insertions(+), 47 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 0fa4ccfd406d..d9861b54f8c8 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -137,25 +137,78 @@ get/set up to 64 properties. The actual meaning of each property is described on
<constant>DTV_MODULATION</constant> -Specifies the frontend modulation type for cable and satellite types. The modulation can be one of the types bellow: - - typedef enum fe_modulation { - QPSK, - QAM_16, - QAM_32, - QAM_64, - QAM_128, - QAM_256, - QAM_AUTO, - VSB_8, - VSB_16, - PSK_8, - APSK_16, - APSK_32, - DQPSK, - QAM_4_NR, - } fe_modulation_t; - +Specifies the frontend modulation type for delivery systems that supports + more than one modulation type. The modulation can be one of the types + defined by &fe-modulation;. + + +
+Modulation property + +Most of the digital TV standards currently offers more than one possible + modulation (sometimes called as "constellation" on some standards). This + enum contains the values used by the Kernel. Please notice that not all + modulations are supported by a given standard. + +
+ enum fe_modulation + + &cs-def; + + + ID + Description + + + + + QPSK + QPSK modulation + + QAM_16 + 16-QAM modulation + + QAM_32 + 32-QAM modulation + + QAM_64 + 64-QAM modulation + + QAM_128 + 128-QAM modulation + + QAM_256 + 256-QAM modulation + + QAM_AUTO + Autodetect QAM modulation + + VSB_8 + 8-VSB modulation + + VSB_16 + 16-VSB modulation + + PSK_8 + 8-PSK modulation + + APSK_16 + 16-APSK modulation + + APSK_32 + 32-APSK modulation + + DQPSK + DQPSK modulation + + QAM_4_NR + 4-QAM-NR modulation + + + +
+
+
<constant>DTV_BANDWIDTH_HZ</constant> diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 16a4648043d6..07c1284e88c8 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -100,32 +100,6 @@ detection.
-
-frontend modulation type for QAM, OFDM and VSB -For cable and terrestrial frontends, e. g. for -struct dvb_qpsk_parameters, -struct dvb_qam_parameters and -struct dvb_qam_parameters, -it needs to specify the quadrature modulation mode which can be one of the following: - - - typedef enum fe_modulation { - QPSK, - QAM_16, - QAM_32, - QAM_64, - QAM_128, - QAM_256, - QAM_AUTO, - VSB_8, - VSB_16, - PSK_8, - APSK_16, - APSK_32, - DQPSK, - } fe_modulation_t; - -
More OFDM parameters diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index dd64e6d5d881..d4b1718046ae 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -178,7 +178,7 @@ typedef enum fe_code_rate { } fe_code_rate_t; -typedef enum fe_modulation { +enum fe_modulation { QPSK, QAM_16, QAM_32, @@ -193,7 +193,9 @@ typedef enum fe_modulation { APSK_32, DQPSK, QAM_4_NR, -} fe_modulation_t; +}; + +typedef enum fe_modulation fe_modulation_t; typedef enum fe_transmit_mode { TRANSMISSION_MODE_2K, -- cgit v1.2.3 From 704db8050d873b16ec781e69b2928dcc94049684 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 14:32:28 -0300 Subject: [media] DocBook: some fixes at FE_GET_INFO There are a few issues at FE_GET_INFO documentation: - name is a string, not a pointer to a string; - the return text should be after the paragraph. While here, better to bold that two fields of the structure used by FE_GET_INFO are actually deprecated. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-get-info.xml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-get-info.xml b/Documentation/DocBook/media/dvb/fe-get-info.xml index b98a9a5e74d3..4400790b4565 100644 --- a/Documentation/DocBook/media/dvb/fe-get-info.xml +++ b/Documentation/DocBook/media/dvb/fe-get-info.xml @@ -53,8 +53,9 @@ kernel devices compatible with this specification and to obtain information about driver and hardware capabilities. The ioctl takes a pointer to dvb_frontend_info which is filled by the driver. When the -driver is not compatible with this specification the ioctl returns an error &return-value-dvb;. +driver is not compatible with this specification the ioctl returns an error. +&return-value-dvb; struct <structname>dvb_frontend_info</structname> @@ -62,13 +63,13 @@ driver is not compatible with this specification the ioctl returns an error &ret &cs-str; - char * + char name[128] Name of the frontend fe_type_t type - DVBv3 type. Should not be used on modern programs, as a + DEPRECATED. DVBv3 type. Should not be used on modern programs, as a frontend may have more than one type. So, the DVBv5 API should be used instead to enumerate and select the frontend type. @@ -102,7 +103,7 @@ driver is not compatible with this specification the ioctl returns an error &ret uint32_t notifier_delay - Deprecated. Not used by any driver. + DEPRECATED. Not used by any driver. &fe-caps; caps -- cgit v1.2.3 From edcf3cdfcd49ef4a178226c9173b88245fb04dec Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 20:09:45 -0300 Subject: [media] DocBook/Makefile: improve typedef parser The typedef parser is wrong and doesn't get some of the types defined at the DVB API. Improve it, as we want to add cross-references to those types. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index e07e8844efde..dbc9a56e8260 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -70,8 +70,8 @@ DEFINES = \ $(shell perl -ne 'print "$$1 " if /\#define\s+(DTV_[^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/frontend.h) \ TYPES = \ - $(shell perl -ne 'print "$$1 " if /^typedef\s+[^\s]+\s+([^\s]+)\;/' $(srctree)/include/uapi/linux/videodev2.h) \ - $(shell perl -ne 'print "$$1 " if /^}\s+([a-z0-9_]+_t)/' $(srctree)/include/uapi/linux/dvb/frontend.h) + $(shell perl -ne 'print "$$1 " if /^typedef\s+.*\s+(\S+)\;/' $(srctree)/include/uapi/linux/videodev2.h) \ + $(shell perl -ne 'print "$$1 " if /^typedef\s+.*\s+(\S+)\;/' $(srctree)/include/uapi/linux/dvb/frontend.h) ENUMS = \ $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/videodev2.h) \ -- cgit v1.2.3 From 01f18d9633e9d6db323534ef2863b0f87393ade2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 20:12:38 -0300 Subject: [media] DocBook: cross-reference enum fe_modulation where needed At frontend legacy API description, there are three places where fe_modulation_t is defined. Cross-reference it to point to the right place at the documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend_legacy_api.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index 1eedc4ce0e4a..7d5823858df0 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -115,7 +115,7 @@ OFDM frontends the frequency specifies the absolute frequen struct dvb_qam_parameters { uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ - fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ + &fe-modulation-t; modulation; /⋆ modulation type (see above) ⋆/ }; @@ -125,7 +125,7 @@ OFDM frontends the frequency specifies the absolute frequen ATSC frontends are supported by the dvb_vsb_parameters structure: struct dvb_vsb_parameters { - fe_modulation_t modulation; /⋆ modulation type (see above) ⋆/ + &fe-modulation-t; modulation; /⋆ modulation type (see above) ⋆/ }; @@ -138,7 +138,7 @@ struct dvb_vsb_parameters { fe_bandwidth_t bandwidth; fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ - fe_modulation_t constellation; /⋆ modulation type (see above) ⋆/ + &fe-modulation-t; constellation; /⋆ modulation type (see above) ⋆/ fe_transmit_mode_t transmission_mode; fe_guard_interval_t guard_interval; fe_hierarchy_t hierarchy_information; -- cgit v1.2.3 From 58e11cc3c1f7d7e9fa70ba6c3d363456151fcffd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 20:00:43 -0300 Subject: [media] DocBook: improve documentation for DVB spectral inversion Format it as a table and provide more details. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 52 ++++++++++++++++------ Documentation/DocBook/media/dvb/frontend.xml | 17 ------- .../DocBook/media/dvb/frontend_legacy_api.xml | 2 +- include/uapi/linux/dvb/frontend.h | 5 ++- 4 files changed, 43 insertions(+), 33 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index d9861b54f8c8..41085537acfc 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -238,19 +238,45 @@ get/set up to 64 properties. The actual meaning of each property is described on
<constant>DTV_INVERSION</constant> - The Inversion field can take one of these values: - - - typedef enum fe_spectral_inversion { - INVERSION_OFF, - INVERSION_ON, - INVERSION_AUTO - } fe_spectral_inversion_t; - - It indicates if spectral inversion should be presumed or not. In the automatic setting - (INVERSION_AUTO) the hardware will try to figure out the correct setting by - itself. - + + Specifies if the frontend should do spectral inversion or not. + +
+enum fe_modulation: Frontend spectral inversion + +This parameter indicates if spectral inversion should be presumed or not. + In the automatic setting (INVERSION_AUTO) the hardware + will try to figure out the correct setting by itself. If the hardware + doesn't support, the DVB core will try to lock at the carrier first with + inversion off. If it fails, it will try to enable inversion. + + +
+ enum fe_modulation + + &cs-def; + + + ID + Description + + + + + INVERSION_OFF + Don't do spectral band inversion. + + INVERSION_ON + Do spectral band inversion. + + INVERSION_AUTO + Autodetect spectral band inversion. + + + +
+
+
<constant>DTV_DISEQC_MASTER</constant> diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 07c1284e88c8..77dd88ceeedd 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -56,23 +56,6 @@ specification is available at &sub-dvbproperty; -
-frontend spectral inversion -The Inversion field can take one of these values: - - -typedef enum fe_spectral_inversion { - INVERSION_OFF, - INVERSION_ON, - INVERSION_AUTO -} fe_spectral_inversion_t; - -It indicates if spectral inversion should be presumed or not. In the automatic setting -(INVERSION_AUTO) the hardware will try to figure out the correct setting by -itself. - -
-
frontend code rate The possible values for the fec_inner field used on diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index 7d5823858df0..fe1117e91f51 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -82,7 +82,7 @@ DVB-C2, ISDB, etc. struct dvb_frontend_parameters { uint32_t frequency; /⋆ (absolute) frequency in Hz for QAM/OFDM ⋆/ /⋆ intermediate frequency in kHz for QPSK ⋆/ - fe_spectral_inversion_t inversion; + &fe-spectral-inversion-t; inversion; union { struct dvb_qpsk_parameters qpsk; struct dvb_qam_parameters qam; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index d4b1718046ae..223905563676 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -154,12 +154,13 @@ enum fe_status { typedef enum fe_status fe_status_t; -typedef enum fe_spectral_inversion { +enum fe_spectral_inversion { INVERSION_OFF, INVERSION_ON, INVERSION_AUTO -} fe_spectral_inversion_t; +}; +typedef enum fe_spectral_inversion fe_spectral_inversion_t; typedef enum fe_code_rate { FEC_NONE = 0, -- cgit v1.2.3 From 0577a2f6d84a08da96c908a885db16b4d3532dc4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 20:52:52 -0300 Subject: [media] DocBook: improve documentation for OFDM transmission mode Format it as a table and add more details, in special, for the DTMB modes. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 69 +++++++++++++++++----- Documentation/DocBook/media/dvb/frontend.xml | 15 ----- .../DocBook/media/dvb/frontend_legacy_api.xml | 2 +- include/uapi/linux/dvb/frontend.h | 6 +- 4 files changed, 59 insertions(+), 33 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 41085537acfc..06a12f1c57c5 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -827,22 +827,61 @@ typedef enum fe_guard_interval {
<constant>DTV_TRANSMISSION_MODE</constant> - Specifies the number of carriers used by the standard + Specifies the number of carriers used by the standard. + This is used only on OFTM-based standards, e. g. + DVB-T/T2, ISDB-T, DTMB + +
+enum fe_transmit_mode: Number of carriers per channel + + + enum fe_transmit_mode + + &cs-def; + + + ID + Description + + + + + TRANSMISSION_MODE_AUTO + Autodetect transmission mode. The hardware will try to find + the correct FFT-size (if capable) to fill in the missing + parameters. + + TRANSMISSION_MODE_1K + Transmission mode 1K + + TRANSMISSION_MODE_2K + Transmission mode 2K + + TRANSMISSION_MODE_8K + Transmission mode 8K + + TRANSMISSION_MODE_4K + Transmission mode 4K + + TRANSMISSION_MODE_16K + Transmission mode 16K + + TRANSMISSION_MODE_32K + Transmission mode 32K + + TRANSMISSION_MODE_C1 + Single Carrier (C=1) transmission mode (DTMB) + + TRANSMISSION_MODE_C3780 + Multi Carrier (C=3780) transmission mode (DTMB) + + + + +
+
+ - Possible values are: - -typedef enum fe_transmit_mode { - TRANSMISSION_MODE_2K, - TRANSMISSION_MODE_8K, - TRANSMISSION_MODE_AUTO, - TRANSMISSION_MODE_4K, - TRANSMISSION_MODE_1K, - TRANSMISSION_MODE_16K, - TRANSMISSION_MODE_32K, - TRANSMISSION_MODE_C1, - TRANSMISSION_MODE_C3780, -} fe_transmit_mode_t; - Notes: 1) ISDB-T supports three carrier/symbol-size: 8K, 4K, 2K. It is called 'mode' in the standard: Mode 1 is 2K, mode 2 is 4K, mode 3 is 8K diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 77dd88ceeedd..3b6a169ac8f3 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -87,21 +87,6 @@ detection.
More OFDM parameters -
-Number of carriers per channel - -typedef enum fe_transmit_mode { - TRANSMISSION_MODE_2K, - TRANSMISSION_MODE_8K, - TRANSMISSION_MODE_AUTO, - TRANSMISSION_MODE_4K, - TRANSMISSION_MODE_1K, - TRANSMISSION_MODE_16K, - TRANSMISSION_MODE_32K, - } fe_transmit_mode_t; - -
-
frontend bandwidth diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index fe1117e91f51..fa0c6649abfd 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -139,7 +139,7 @@ struct dvb_vsb_parameters { fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ &fe-modulation-t; constellation; /⋆ modulation type (see above) ⋆/ - fe_transmit_mode_t transmission_mode; + &fe-transmit-mode-t; transmission_mode; fe_guard_interval_t guard_interval; fe_hierarchy_t hierarchy_information; }; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 223905563676..c42e6d849f52 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -198,7 +198,7 @@ enum fe_modulation { typedef enum fe_modulation fe_modulation_t; -typedef enum fe_transmit_mode { +enum fe_transmit_mode { TRANSMISSION_MODE_2K, TRANSMISSION_MODE_8K, TRANSMISSION_MODE_AUTO, @@ -208,7 +208,9 @@ typedef enum fe_transmit_mode { TRANSMISSION_MODE_32K, TRANSMISSION_MODE_C1, TRANSMISSION_MODE_C3780, -} fe_transmit_mode_t; +}; + +typedef enum fe_transmit_mode fe_transmit_mode_t; #if defined(__DVB_CORE__) || !defined (__KERNEL__) typedef enum fe_bandwidth { -- cgit v1.2.3 From b174fb71e82eef2355aabece4b50fe1540e67544 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 20:57:53 -0300 Subject: [media] DocBook: move fe_bandwidth to the frontend legacy section fe_bandwidth/fe_bandwidth_t is used only on DVBv3 API. So, move it to the frontend legacy xml, and convert it into a table. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 15 -------- .../DocBook/media/dvb/frontend_legacy_api.xml | 44 +++++++++++++++++++++- include/uapi/linux/dvb/frontend.h | 6 ++- 3 files changed, 47 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 3b6a169ac8f3..93d22486f20c 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -87,21 +87,6 @@ detection.
More OFDM parameters -
-frontend bandwidth - -typedef enum fe_bandwidth { - BANDWIDTH_8_MHZ, - BANDWIDTH_7_MHZ, - BANDWIDTH_6_MHZ, - BANDWIDTH_AUTO, - BANDWIDTH_5_MHZ, - BANDWIDTH_10_MHZ, - BANDWIDTH_1_712_MHZ, -} fe_bandwidth_t; - -
-
frontend guard inverval diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index fa0c6649abfd..ed393f22f7a7 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -60,6 +60,48 @@ supported via the new FE_GET_PROPERTY/FE_GET_SET using the &DTV-DELIVERY-SYSTEM; property.
+
+Frontend bandwidth + + + enum fe_bandwidth + + &cs-def; + + + ID + Description + + + + + BANDWIDTH_AUTO + Autodetect bandwidth (if supported) + + BANDWIDTH_1_712_MHZ + 1.712 MHz + + BANDWIDTH_5_MHZ + 5 MHz + + BANDWIDTH_6_MHZ + 6 MHz + + BANDWIDTH_7_MHZ + 7 MHz + + BANDWIDTH_8_MHZ + 8 MHz + + BANDWIDTH_10_MHZ + 10 MHz + + + + +
+ +
frontend parameters @@ -135,7 +177,7 @@ struct dvb_vsb_parameters { DVB-T frontends are supported by the dvb_ofdm_parameters structure: struct dvb_ofdm_parameters { - fe_bandwidth_t bandwidth; + &fe-bandwidth-t; bandwidth; fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ &fe-modulation-t; constellation; /⋆ modulation type (see above) ⋆/ diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index c42e6d849f52..43e6faf91849 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -213,7 +213,7 @@ enum fe_transmit_mode { typedef enum fe_transmit_mode fe_transmit_mode_t; #if defined(__DVB_CORE__) || !defined (__KERNEL__) -typedef enum fe_bandwidth { +enum fe_bandwidth { BANDWIDTH_8_MHZ, BANDWIDTH_7_MHZ, BANDWIDTH_6_MHZ, @@ -221,7 +221,9 @@ typedef enum fe_bandwidth { BANDWIDTH_5_MHZ, BANDWIDTH_10_MHZ, BANDWIDTH_1_712_MHZ, -} fe_bandwidth_t; +}; + +typedef enum fe_bandwidth fe_bandwidth_t; #endif typedef enum fe_guard_interval { -- cgit v1.2.3 From 2d457b8a9054b9c5b1fcfbc5702b7d0e9f6cda2b Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 21:38:44 -0300 Subject: [media] DocBook: improve documentation for FEC fields Format it as a table and add more details. Also, remove the duplicated occurrences. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 123 ++++++++++++--------- Documentation/DocBook/media/dvb/frontend.xml | 28 ----- .../DocBook/media/dvb/frontend_legacy_api.xml | 8 +- include/uapi/linux/dvb/frontend.h | 6 +- 4 files changed, 78 insertions(+), 87 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 06a12f1c57c5..b96a91a1494d 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -290,25 +290,70 @@ get/set up to 64 properties. The actual meaning of each property is described on <constant>DTV_INNER_FEC</constant> Used cable/satellite transmissions. The acceptable values are: - -typedef enum fe_code_rate { - FEC_NONE = 0, - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_4_5, - FEC_5_6, - FEC_6_7, - FEC_7_8, - FEC_8_9, - FEC_AUTO, - FEC_3_5, - FEC_9_10, - FEC_2_5, -} fe_code_rate_t; - - which correspond to error correction rates of 1/2, 2/3, etc., - no error correction or auto detection. +
+enum fe_code_rate: type of the Forward Error Correction. + + + enum fe_code_rate + + &cs-def; + + + ID + Description + + + + + TRANSMISSION_MODE_AUTO + Autodetect transmission mode. The hardware will try to find + the correct FFT-size (if capable) to fill in the missing + parameters. + + FEC_NONE + No Forward Error Correction Code + + FEC_AUTO + Autodetect Error Correction Code + + FEC_1_2 + Forward Error Correction Code 1/2 + + FEC_2_3 + Forward Error Correction Code 2/3 + + FEC_3_4 + Forward Error Correction Code 3/4 + + FEC_4_5 + Forward Error Correction Code 4/5 + + FEC_5_6 + Forward Error Correction Code 5/6 + + FEC_6_7 + Forward Error Correction Code 6/7 + + FEC_7_8 + Forward Error Correction Code 7/8 + + FEC_8_9 + Forward Error Correction Code 8/9 + + FEC_9_10 + Forward Error Correction Code 9/10 + + FEC_2_5 + Forward Error Correction Code 2/5 + + FEC_3_5 + Forward Error Correction Code 3/5 + + + + +
+
<constant>DTV_VOLTAGE</constant> @@ -757,46 +802,18 @@ typedef enum atscmh_sccc_code_mode {
<constant>DTV_CODE_RATE_HP</constant> - Used on terrestrial transmissions. The acceptable values are: + Used on terrestrial transmissions. The acceptable values are + the ones described at &fe-transmit-mode-t;. - -typedef enum fe_code_rate { - FEC_NONE = 0, - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_4_5, - FEC_5_6, - FEC_6_7, - FEC_7_8, - FEC_8_9, - FEC_AUTO, - FEC_3_5, - FEC_9_10, -} fe_code_rate_t; -
<constant>DTV_CODE_RATE_LP</constant> - Used on terrestrial transmissions. The acceptable values are: + Used on terrestrial transmissions. The acceptable values are + the ones described at &fe-transmit-mode-t;. - -typedef enum fe_code_rate { - FEC_NONE = 0, - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_4_5, - FEC_5_6, - FEC_6_7, - FEC_7_8, - FEC_8_9, - FEC_AUTO, - FEC_3_5, - FEC_9_10, -} fe_code_rate_t; - +
+
<constant>DTV_GUARD_INTERVAL</constant> diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 93d22486f20c..563800eb1216 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -56,34 +56,6 @@ specification is available at &sub-dvbproperty; -
-frontend code rate -The possible values for the fec_inner field used on -struct dvb_qpsk_parameters and -struct dvb_qam_parameters are: - - -typedef enum fe_code_rate { - FEC_NONE = 0, - FEC_1_2, - FEC_2_3, - FEC_3_4, - FEC_4_5, - FEC_5_6, - FEC_6_7, - FEC_7_8, - FEC_8_9, - FEC_AUTO, - FEC_3_5, - FEC_9_10, -} fe_code_rate_t; - -which correspond to error correction rates of 1/2, 2/3, etc., no error correction or auto -detection. - -
- -
More OFDM parameters diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index ed393f22f7a7..c1dfbd8096bd 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -145,7 +145,7 @@ OFDM frontends the frequency specifies the absolute frequen struct dvb_qpsk_parameters { uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ - fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ + &fe-code-rate-t; fec_inner; /⋆ forward error correction (see above) ⋆/ };
@@ -156,7 +156,7 @@ OFDM frontends the frequency specifies the absolute frequen struct dvb_qam_parameters { uint32_t symbol_rate; /⋆ symbol rate in Symbols per second ⋆/ - fe_code_rate_t fec_inner; /⋆ forward error correction (see above) ⋆/ + &fe-code-rate-t; fec_inner; /⋆ forward error correction (see above) ⋆/ &fe-modulation-t; modulation; /⋆ modulation type (see above) ⋆/ }; @@ -178,8 +178,8 @@ struct dvb_vsb_parameters { struct dvb_ofdm_parameters { &fe-bandwidth-t; bandwidth; - fe_code_rate_t code_rate_HP; /⋆ high priority stream code rate ⋆/ - fe_code_rate_t code_rate_LP; /⋆ low priority stream code rate ⋆/ + &fe-code-rate-t; code_rate_HP; /⋆ high priority stream code rate ⋆/ + &fe-code-rate-t; code_rate_LP; /⋆ low priority stream code rate ⋆/ &fe-modulation-t; constellation; /⋆ modulation type (see above) ⋆/ &fe-transmit-mode-t; transmission_mode; fe_guard_interval_t guard_interval; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 43e6faf91849..49f6e980125b 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -162,7 +162,7 @@ enum fe_spectral_inversion { typedef enum fe_spectral_inversion fe_spectral_inversion_t; -typedef enum fe_code_rate { +enum fe_code_rate { FEC_NONE = 0, FEC_1_2, FEC_2_3, @@ -176,7 +176,9 @@ typedef enum fe_code_rate { FEC_3_5, FEC_9_10, FEC_2_5, -} fe_code_rate_t; +}; + +typedef enum fe_code_rate fe_code_rate_t; enum fe_modulation { -- cgit v1.2.3 From 903142e53c648ee61c00f5c3b420b16bc6336ad7 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 22:01:41 -0300 Subject: [media] DocBook: improve documentation for guard interval Format it as a table and add more details, in special for DTMB guard intervals. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 68 +++++++++++++++++----- Documentation/DocBook/media/dvb/frontend.xml | 16 ----- .../DocBook/media/dvb/frontend_legacy_api.xml | 2 +- include/uapi/linux/dvb/frontend.h | 5 +- 4 files changed, 57 insertions(+), 34 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index b96a91a1494d..5f30a28a15b0 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -818,21 +818,59 @@ typedef enum atscmh_sccc_code_mode { <constant>DTV_GUARD_INTERVAL</constant> Possible values are: - -typedef enum fe_guard_interval { - GUARD_INTERVAL_1_32, - GUARD_INTERVAL_1_16, - GUARD_INTERVAL_1_8, - GUARD_INTERVAL_1_4, - GUARD_INTERVAL_AUTO, - GUARD_INTERVAL_1_128, - GUARD_INTERVAL_19_128, - GUARD_INTERVAL_19_256, - GUARD_INTERVAL_PN420, - GUARD_INTERVAL_PN595, - GUARD_INTERVAL_PN945, -} fe_guard_interval_t; - + +
+Modulation guard interval + + + enum fe_guard_interval + + &cs-def; + + + ID + Description + + + + + GUARD_INTERVAL_AUTO + Autodetect the guard interval + + GUARD_INTERVAL_1_128 + Guard interval 1/128 + + GUARD_INTERVAL_1_32 + Guard interval 1/32 + + GUARD_INTERVAL_1_16 + Guard interval 1/16 + + GUARD_INTERVAL_1_8 + Guard interval 1/8 + + GUARD_INTERVAL_1_4 + Guard interval 1/4 + + GUARD_INTERVAL_19_128 + Guard interval 19/128 + + GUARD_INTERVAL_19_256 + Guard interval 19/256 + + GUARD_INTERVAL_PN420 + PN length 420 (1/4) + + GUARD_INTERVAL_PN595 + PN length 595 (1/6) + + GUARD_INTERVAL_PN945 + PN length 945 (1/9) + + + +
+
Notes: 1) If DTV_GUARD_INTERVAL is set the GUARD_INTERVAL_AUTO the hardware will diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 563800eb1216..a005c4b472f5 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -59,22 +59,6 @@ specification is available at
More OFDM parameters -
-frontend guard inverval - -typedef enum fe_guard_interval { - GUARD_INTERVAL_1_32, - GUARD_INTERVAL_1_16, - GUARD_INTERVAL_1_8, - GUARD_INTERVAL_1_4, - GUARD_INTERVAL_AUTO, - GUARD_INTERVAL_1_128, - GUARD_INTERVAL_19_128, - GUARD_INTERVAL_19_256, -} fe_guard_interval_t; - -
-
frontend hierarchy diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index c1dfbd8096bd..d20f1fd75fa9 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -182,7 +182,7 @@ struct dvb_vsb_parameters { &fe-code-rate-t; code_rate_LP; /⋆ low priority stream code rate ⋆/ &fe-modulation-t; constellation; /⋆ modulation type (see above) ⋆/ &fe-transmit-mode-t; transmission_mode; - fe_guard_interval_t guard_interval; + &fe-guard-interval-t; guard_interval; fe_hierarchy_t hierarchy_information; }; diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 49f6e980125b..1d2b7c6dee04 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -228,7 +228,7 @@ enum fe_bandwidth { typedef enum fe_bandwidth fe_bandwidth_t; #endif -typedef enum fe_guard_interval { +enum fe_guard_interval { GUARD_INTERVAL_1_32, GUARD_INTERVAL_1_16, GUARD_INTERVAL_1_8, @@ -240,8 +240,9 @@ typedef enum fe_guard_interval { GUARD_INTERVAL_PN420, GUARD_INTERVAL_PN595, GUARD_INTERVAL_PN945, -} fe_guard_interval_t; +}; +typedef enum fe_guard_interval fe_guard_interval_t; typedef enum fe_hierarchy { HIERARCHY_NONE, -- cgit v1.2.3 From 9df4fc5b8f34383d116a160809e782b4ca50a808 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 28 May 2015 22:06:56 -0300 Subject: [media] DocBook: improve documentation for hierarchy Format it as a table and links it with the legacy API xml. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 46 +++++++++++++++++----- Documentation/DocBook/media/dvb/frontend.xml | 18 --------- .../DocBook/media/dvb/frontend_legacy_api.xml | 2 +- include/uapi/linux/dvb/frontend.h | 6 ++- 4 files changed, 42 insertions(+), 30 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 5f30a28a15b0..ae9bc1e089cc 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -951,15 +951,43 @@ typedef enum atscmh_sccc_code_mode {
<constant>DTV_HIERARCHY</constant> Frontend hierarchy - -typedef enum fe_hierarchy { - HIERARCHY_NONE, - HIERARCHY_1, - HIERARCHY_2, - HIERARCHY_4, - HIERARCHY_AUTO - } fe_hierarchy_t; - + + +
+Frontend hierarchy + + + enum fe_hierarchy + + &cs-def; + + + ID + Description + + + + + HIERARCHY_NONE + No hierarchy + + HIERARCHY_AUTO + Autodetect hierarchy (if supported) + + HIERARCHY_1 + Hierarchy 1 + + HIERARCHY_2 + Hierarchy 2 + + HIERARCHY_4 + Hierarchy 4 + + + +
+
+
<constant>DTV_STREAM_ID</constant> diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index a005c4b472f5..d81b3ff33295 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -56,24 +56,6 @@ specification is available at &sub-dvbproperty; -
-More OFDM parameters - -
-frontend hierarchy - -typedef enum fe_hierarchy { - HIERARCHY_NONE, - HIERARCHY_1, - HIERARCHY_2, - HIERARCHY_4, - HIERARCHY_AUTO - } fe_hierarchy_t; - -
- -
-
Frontend Function Calls diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index d20f1fd75fa9..cb2e18381305 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -183,7 +183,7 @@ struct dvb_vsb_parameters { &fe-modulation-t; constellation; /⋆ modulation type (see above) ⋆/ &fe-transmit-mode-t; transmission_mode; &fe-guard-interval-t; guard_interval; - fe_hierarchy_t hierarchy_information; + &fe-hierarchy-t; hierarchy_information; };
diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 1d2b7c6dee04..3a7ff9002654 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -244,13 +244,15 @@ enum fe_guard_interval { typedef enum fe_guard_interval fe_guard_interval_t; -typedef enum fe_hierarchy { +enum fe_hierarchy { HIERARCHY_NONE, HIERARCHY_1, HIERARCHY_2, HIERARCHY_4, HIERARCHY_AUTO -} fe_hierarchy_t; +}; + +typedef enum fe_hierarchy fe_hierarchy_t; enum fe_interleaving { INTERLEAVING_NONE, -- cgit v1.2.3 From 38fbb98668817a0f1db39ebb2302d534f44a52fd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 29 May 2015 07:34:50 -0300 Subject: [media] DocBook: improve documentation of the properties structs Rename the tytle of the struct documentation to reflect the name of the structures, and use links to do cross-ref. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 14 +++++++------- Documentation/DocBook/media/dvb/fe-get-property.xml | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index ae9bc1e089cc..b91210d646cf 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -36,7 +36,7 @@ API is to replace the ioctl's were the struct dvb_frontend_parameters were used.
-DTV stats type +struct <structname>dtv_stats</structname> struct dtv_stats { __u8 scale; /* enum fecap_scale_params type */ @@ -48,19 +48,19 @@ struct dtv_stats {
-DTV stats type +struct <structname>dtv_fe_stats</structname> #define MAX_DTV_STATS 4 struct dtv_fe_stats { __u8 len; - struct dtv_stats stat[MAX_DTV_STATS]; + &dtv-stats; stat[MAX_DTV_STATS]; } __packed;
-DTV property type +struct <structname>dtv_property</structname> /* Reserved fields should be set to 0 */ @@ -69,7 +69,7 @@ struct dtv_property { __u32 reserved[3]; union { __u32 data; - struct dtv_fe_stats st; + &dtv-fe-stats; st; struct { __u8 data[32]; __u32 len; @@ -85,11 +85,11 @@ struct dtv_property {
-DTV properties type +struct <structname>dtv_properties</structname> struct dtv_properties { __u32 num; - struct dtv_property *props; + &dtv-property; *props; };
diff --git a/Documentation/DocBook/media/dvb/fe-get-property.xml b/Documentation/DocBook/media/dvb/fe-get-property.xml index b121fe5380ca..456ed92133f1 100644 --- a/Documentation/DocBook/media/dvb/fe-get-property.xml +++ b/Documentation/DocBook/media/dvb/fe-get-property.xml @@ -17,7 +17,7 @@ int ioctl int fd int request - &dtv-property; *argp + &dtv-properties; *argp @@ -40,7 +40,7 @@ argp - pointer to &dtv-property; + pointer to &dtv-properties; -- cgit v1.2.3 From e3dae8623d934611c57bc060c5d588de0fccafa5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 29 May 2015 09:39:51 -0300 Subject: [media] DocBook: Add an example for using FE_SET_PROPERTY In order to make it clearer about how to use the DVBv5 calls, add an example of its usage. That should make it clearer about what's actually required for the DVBv5 calls to work. While here, also mentions the libdvbv5 library. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 40 +++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index b91210d646cf..00ba1a9e314c 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -15,11 +15,13 @@ approach, in favor of a properties set approach. By using a properties set, it is now possible to extend and support any digital TV without needing to redesign the API + Example: with the properties based approach, in order to set the tuner to a DVB-C channel at 651 kHz, modulated with 256-QAM, FEC 3/4 and symbol rate of 5.217 Mbauds, those properties should be sent to FE_SET_PROPERTY ioctl: + &DTV-DELIVERY-SYSTEM; = SYS_DVBC_ANNEX_A &DTV-FREQUENCY; = 651000000 &DTV-MODULATION; = QAM_256 &DTV-INVERSION; = INVERSION_AUTO @@ -27,6 +29,44 @@ &DTV-INNER-FEC; = FEC_3_4 &DTV-TUNE; + +The code that would do the above is: + +#include <stdio.h> +#include <fcntl.h> +#include <sys/ioctl.h> +#include <linux/dvb/frontend.h> + +static struct dtv_property props[] = { + { .cmd = DTV_DELIVERY_SYSTEM, .u.data = SYS_DVBC_ANNEX_A }, + { .cmd = DTV_FREQUENCY, .u.data = 651000000 }, + { .cmd = DTV_MODULATION, .u.data = QAM_256 }, + { .cmd = DTV_INVERSION, .u.data = INVERSION_AUTO }, + { .cmd = DTV_SYMBOL_RATE, .u.data = 5217000 }, + { .cmd = DTV_INNER_FEC, .u.data = FEC_3_4 }, + { .cmd = DTV_TUNE } +}; + +static struct dtv_properties dtv_prop = { + .num = 6, .props = props +}; + +int main(void) +{ + int fd = open("/dev/dvb/adapter0/frontend0", O_RDWR); + + if (!fd) { + perror ("open"); + return -1; + } + if (ioctl(fd, FE_SET_PROPERTY, &dtv_prop) == -1) { + perror("ioctl"); + return -1; + } + printf("Frontend set\n"); + return 0; +} + NOTE: This section describes the DVB version 5 extension of the DVB-API, also called "S2API", as this API were added to provide support for DVB-S2. It was designed to be able to replace the old frontend API. Yet, the DISEQC and -- cgit v1.2.3 From ac99edd2e13df8d4a5bd3dd2a8b004121f4fb47d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 29 May 2015 09:39:55 -0300 Subject: [media] DocBook: cleaup the notes about DTV properties The notes there are somewhat confusing and assumes that the reader would have read the DVBv3 way. This is not true anymore, as the DVBv3 is now on a separate section that is marked as deprecated. So, cleanup the notes. While here, add a note about using libdvbv5, instead of using the DVBv5 API directly. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 00ba1a9e314c..a5d0a209d3f3 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -13,8 +13,14 @@ Also, the union didn't have any space left to be expanded without breaking userspace. So, the decision was to deprecate the legacy union/struct based approach, in favor of a properties set approach. -By using a properties set, it is now possible to extend and support any - digital TV without needing to redesign the API + +NOTE: on Linux DVB API version 3, setting a frontend were done via + struct dvb_frontend_parameters. + This got replaced on version 5 (also called "S2API", as this API were + added originally_enabled to provide support for DVB-S2), because the old + API has a very limited support to new standards and new hardware. This + section describes the new and recommended way to set the frontend, with + suppports all digital TV delivery systems. Example: with the properties based approach, in order to set the tuner to a DVB-C channel at 651 kHz, modulated with 256-QAM, FEC 3/4 and symbol @@ -67,13 +73,13 @@ int main(void) return 0; } -NOTE: This section describes the DVB version 5 extension of the DVB-API, -also called "S2API", as this API were added to provide support for DVB-S2. It -was designed to be able to replace the old frontend API. Yet, the DISEQC and -the capability ioctls weren't implemented yet via the new way. -The typical usage for the FE_GET_PROPERTY/FE_SET_PROPERTY -API is to replace the ioctl's were the -struct dvb_frontend_parameters were used. + +NOTE: While it is possible to directly call the Kernel code like the + above example, it is strongly recommended to use + libdvbv5, + as it provides abstraction to work with the supported digital TV standards + and provides methods for usual operations like program scanning and to + read/write channel descriptor files.
struct <structname>dtv_stats</structname> -- cgit v1.2.3 From 87db4553a873976f306d98bab5436a4a86d37882 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 29 May 2015 10:19:55 -0300 Subject: [media] DocBook: Fix arguments on some ioctl documentation Due to a cut-and-paste error, the argument is missing or wrong on 3 ioctl documentation. Fix them. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml | 5 ++++- Documentation/DocBook/media/dvb/fe-set-tone.xml | 5 ++++- Documentation/DocBook/media/dvb/fe-set-voltage.xml | 5 ++++- 3 files changed, 12 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml index d1a798048641..f79c3f21323d 100644 --- a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml +++ b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml @@ -36,7 +36,10 @@ - pointer to &fe-sec-mini-cmd; + tone + + pointer to &fe-sec-mini-cmd; + diff --git a/Documentation/DocBook/media/dvb/fe-set-tone.xml b/Documentation/DocBook/media/dvb/fe-set-tone.xml index b4b1f5303170..f3d965503c25 100644 --- a/Documentation/DocBook/media/dvb/fe-set-tone.xml +++ b/Documentation/DocBook/media/dvb/fe-set-tone.xml @@ -36,7 +36,10 @@ - pointer to &fe-sec-tone-mode; + tone + + pointer to &fe-sec-tone-mode; + diff --git a/Documentation/DocBook/media/dvb/fe-set-voltage.xml b/Documentation/DocBook/media/dvb/fe-set-voltage.xml index a1ee5f9c28e0..d43d51ab8a2d 100644 --- a/Documentation/DocBook/media/dvb/fe-set-voltage.xml +++ b/Documentation/DocBook/media/dvb/fe-set-voltage.xml @@ -36,7 +36,10 @@ - pointer to &fe-sec-voltage; + voltage + + pointer to &fe-sec-voltage; + -- cgit v1.2.3 From 1e35c77dd1f8f3c1c8ef419ec422250fecb31fef Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 29 May 2015 10:52:09 -0300 Subject: [media] DocBook: Update DocBook version and fix a few legacy things The DVB part of the media API documentation has several legacy things on it: - Examples that don't work; - APIs unused and deprecated; - places mentioning the wrong API version. Fix them and bump the documentation version, in order to reflect the cleanup efforts to make it more consistent with the current status of the API. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbapi.xml | 32 ++++++++++++++++++++++------ Documentation/DocBook/media/dvb/examples.xml | 6 ++++-- Documentation/DocBook/media/dvb/intro.xml | 2 +- 3 files changed, 30 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbapi.xml b/Documentation/DocBook/media/dvb/dvbapi.xml index 4c15396c67e5..dc8cb558f9fd 100644 --- a/Documentation/DocBook/media/dvb/dvbapi.xml +++ b/Documentation/DocBook/media/dvb/dvbapi.xml @@ -28,12 +28,22 @@ Convergence GmbH - 2009-2014 + 2009-2015 Mauro Carvalho Chehab + + 2.1.0 + 2015-05-29 + mcc + + DocBook improvements and cleanups, in order to document the + system calls on a more standard way and provide more description + about the current DVB API. + + 2.0.4 2011-05-06 @@ -95,18 +105,26 @@ Added ISDB-T test originally written by Patrick Boettcher &sub-demux; - - &sub-video; - - - &sub-audio; - &sub-ca; &sub-net; + + DVB Deprecated APIs + The APIs described here are kept only for historical reasons. There's + just one driver for a very legacy hardware that uses this API. No + modern drivers should use it. Instead, audio and video should be using + the V4L2 and ALSA APIs, and the pipelines should be set using the + Media Controller API +
+ &sub-video; +
+
+ &sub-audio; +
+ &sub-kdapi; diff --git a/Documentation/DocBook/media/dvb/examples.xml b/Documentation/DocBook/media/dvb/examples.xml index f037e568eb6e..c9f68c7183cc 100644 --- a/Documentation/DocBook/media/dvb/examples.xml +++ b/Documentation/DocBook/media/dvb/examples.xml @@ -1,8 +1,10 @@ Examples In this section we would like to present some examples for using the DVB API. -Maintainer note: This section is out of date. Please refer to the sample programs packaged -with the driver distribution from . +NOTE: This section is out of date, and the code below won't even + compile. Please refer to the + libdvbv5 + for updated/recommended examples.
diff --git a/Documentation/DocBook/media/dvb/intro.xml b/Documentation/DocBook/media/dvb/intro.xml index 4a34ef4783a4..1f7a35a2b365 100644 --- a/Documentation/DocBook/media/dvb/intro.xml +++ b/Documentation/DocBook/media/dvb/intro.xml @@ -205,7 +205,7 @@ a partial path like: additional include file linux/dvb/version.h exists, which defines the constant DVB_API_VERSION. This document -describes DVB_API_VERSION 5.8. +describes DVB_API_VERSION 5.10.
-- cgit v1.2.3 From ddfa6c63f5b5db14e9fcadc0b259a843fadea234 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 15 May 2015 09:11:13 -0300 Subject: [media] DocBook/media: add missing entry for V4L2_PIX_FMT_Y16_BE This format was added but not documented. Do this now. Signed-off-by: Hans Verkuil Acked-by: Ricardo Ribalda Delgado Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/pixfmt-y16-be.xml | 81 +++++++++++++++++++++++ Documentation/DocBook/media/v4l/pixfmt.xml | 1 + 2 files changed, 82 insertions(+) create mode 100644 Documentation/DocBook/media/v4l/pixfmt-y16-be.xml (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/pixfmt-y16-be.xml b/Documentation/DocBook/media/v4l/pixfmt-y16-be.xml new file mode 100644 index 000000000000..cea53e1eaa43 --- /dev/null +++ b/Documentation/DocBook/media/v4l/pixfmt-y16-be.xml @@ -0,0 +1,81 @@ + + + V4L2_PIX_FMT_Y16_BE ('Y16 ' | (1 << 31)) + &manvol; + + + V4L2_PIX_FMT_Y16_BE + Grey-scale image + + + Description + + This is a grey-scale image with a depth of 16 bits per +pixel. The most significant byte is stored at lower memory addresses +(big-endian). Note the actual sampling precision may be lower than +16 bits, for example 10 bits per pixel with values in range 0 to +1023. + + + <constant>V4L2_PIX_FMT_Y16_BE</constant> 4 × 4 +pixel image + + + Byte Order. + Each cell is one byte. + + + + + + start + 0: + Y'00high + Y'00low + Y'01high + Y'01low + Y'02high + Y'02low + Y'03high + Y'03low + + + start + 8: + Y'10high + Y'10low + Y'11high + Y'11low + Y'12high + Y'12low + Y'13high + Y'13low + + + start + 16: + Y'20high + Y'20low + Y'21high + Y'21low + Y'22high + Y'22low + Y'23high + Y'23low + + + start + 24: + Y'30high + Y'30low + Y'31high + Y'31low + Y'32high + Y'32low + Y'33high + Y'33low + + + + + + + + + diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index fcde4e20205e..ddff8d97eb69 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -1429,6 +1429,7 @@ information. &sub-y12; &sub-y10b; &sub-y16; + &sub-y16-be; &sub-uv8; &sub-yuyv; &sub-uyvy; -- cgit v1.2.3 From da0c211bb6670c5e8aa9cac7437948e3e6d00ce3 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 15 May 2015 09:29:06 -0300 Subject: [media] DocBook/media: document COLORSPACE_DEFAULT Document this new colorspace define. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/pixfmt.xml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index ddff8d97eb69..f171b8bbb14f 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -497,6 +497,11 @@ BT.2020 which uses limited range R'G'B' quantization. + + V4L2_COLORSPACE_DEFAULT + The default colorspace. This can be used by applications to let the + driver fill in the colorspace. + V4L2_COLORSPACE_SMPTE170M See . -- cgit v1.2.3 From ed9be0b104ea9719f4bdd84ff2e603071153c3dc Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 15 May 2015 09:29:08 -0300 Subject: [media] DocBook/media: document COLORSPACE_RAW Document this new colorspace define. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/pixfmt.xml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index f171b8bbb14f..6c3d65346076 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -538,6 +538,13 @@ BT.2020 which uses limited range R'G'B' quantization. V4L2_COLORSPACE_JPEG See . + + V4L2_COLORSPACE_RAW + The raw colorspace. This is used for raw image capture where + the image is minimally processed and is using the internal colorspace + of the device. The software that processes an image using this + 'colorspace' will have to know the internals of the capture device. + -- cgit v1.2.3 From 95e130af03b103138ae0d188ef012e5994fe970d Mon Sep 17 00:00:00 2001 From: Mathieu Olivari Date: Wed, 27 May 2015 11:02:50 -0700 Subject: net: stmmac: ipq806x: document device tree bindings Add the device tree bindings documentation for the QCA IPQ806x variant of the Synopsys DesignWare MAC. Signed-off-by: Mathieu Olivari Signed-off-by: David S. Miller --- .../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt new file mode 100644 index 000000000000..6d7ab4e524d4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt @@ -0,0 +1,35 @@ +* IPQ806x DWMAC Ethernet controller + +The device inherits all the properties of the dwmac/stmmac devices +described in the file net/stmmac.txt with the following changes. + +Required properties: + +- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" + and any applicable more detailed version number + described in net/stmmac.txt + +- qcom,nss-common: should contain a phandle to a syscon device mapping the + nss-common registers. + +- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the + qsgmii-csr registers. + +Example: + + gmac: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + }; -- cgit v1.2.3 From e4648b014e03baee45d5f5146c1219b19e4e5f2f Mon Sep 17 00:00:00 2001 From: Ilias Tsitsimpis Date: Thu, 23 Apr 2015 21:30:09 +0300 Subject: target/user: Add support for bidirectional commands Enable TCMU to handle bidirectional SCSI commands. In such cases, entries in iov[] cover both the Data-In and the Data-Out buffers. The first iov_cnt entries correspond to the Data-Out buffer, while the remaining iov_bidi_cnt entries correspond to the Data-In buffer. Signed-off-by: Ilias Tsitsimpis Signed-off-by: Vangelis Koukis Reviewed-by: Andy Grover Signed-off-by: Nicholas Bellinger --- Documentation/target/tcmu-design.txt | 2 +- drivers/target/target_core_user.c | 29 ++++++++++++++++++++++++----- 2 files changed, 25 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcmu-design.txt b/Documentation/target/tcmu-design.txt index 263b907517ac..bef81e42788f 100644 --- a/Documentation/target/tcmu-design.txt +++ b/Documentation/target/tcmu-design.txt @@ -152,7 +152,7 @@ overall shared memory region, not the entry. The data in/out buffers are accessible via tht req.iov[] array. iov_cnt contains the number of entries in iov[] needed to describe either the Data-In or Data-Out buffers. For bidirectional commands, iov_cnt specifies how many iovec -entries cover the Data-Out area, and iov_bidi_count specifies how many +entries cover the Data-Out area, and iov_bidi_cnt specifies how many iovec entries immediately after that in iov[] cover the Data-In area. Just like other fields, iov.iov_base is an offset from the start of the region. diff --git a/drivers/target/target_core_user.c b/drivers/target/target_core_user.c index 2b0d26e268be..60330e00f59d 100644 --- a/drivers/target/target_core_user.c +++ b/drivers/target/target_core_user.c @@ -167,6 +167,11 @@ static struct tcmu_cmd *tcmu_alloc_cmd(struct se_cmd *se_cmd) tcmu_cmd->tcmu_dev = udev; tcmu_cmd->data_length = se_cmd->data_length; + if (se_cmd->se_cmd_flags & SCF_BIDI) { + BUG_ON(!(se_cmd->t_bidi_data_sg && se_cmd->t_bidi_data_nents)); + tcmu_cmd->data_length += se_cmd->t_bidi_data_sg->length; + } + tcmu_cmd->deadline = jiffies + msecs_to_jiffies(TCMU_TIME_OUT); idr_preload(GFP_KERNEL); @@ -387,7 +392,8 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd) * b/c size == offsetof one-past-element. */ base_command_size = max(offsetof(struct tcmu_cmd_entry, - req.iov[se_cmd->t_data_nents + 2]), + req.iov[se_cmd->t_bidi_data_nents + + se_cmd->t_data_nents + 2]), sizeof(struct tcmu_cmd_entry)); command_size = base_command_size + round_up(scsi_command_size(se_cmd->t_task_cdb), TCMU_OP_ALIGN_SIZE); @@ -456,13 +462,19 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd) */ iov = &entry->req.iov[0]; iov_cnt = 0; - copy_to_data_area = (se_cmd->data_direction == DMA_TO_DEVICE); + copy_to_data_area = (se_cmd->data_direction == DMA_TO_DEVICE + || se_cmd->se_cmd_flags & SCF_BIDI); alloc_and_scatter_data_area(udev, se_cmd->t_data_sg, se_cmd->t_data_nents, &iov, &iov_cnt, copy_to_data_area); entry->req.iov_cnt = iov_cnt; - entry->req.iov_bidi_cnt = 0; entry->req.iov_dif_cnt = 0; + /* Handle BIDI commands */ + iov_cnt = 0; + alloc_and_scatter_data_area(udev, se_cmd->t_bidi_data_sg, + se_cmd->t_bidi_data_nents, &iov, &iov_cnt, false); + entry->req.iov_bidi_cnt = iov_cnt; + /* All offsets relative to mb_addr, not start of entry! */ cdb_off = CMDR_OFF + cmd_head + base_command_size; memcpy((void *) mb + cdb_off, se_cmd->t_task_cdb, scsi_command_size(se_cmd->t_task_cdb)); @@ -535,8 +547,15 @@ static void tcmu_handle_completion(struct tcmu_cmd *cmd, struct tcmu_cmd_entry * se_cmd->scsi_sense_length); UPDATE_HEAD(udev->data_tail, cmd->data_length, udev->data_size); - } - else if (se_cmd->data_direction == DMA_FROM_DEVICE) { + } else if (se_cmd->se_cmd_flags & SCF_BIDI) { + /* Discard data_out buffer */ + UPDATE_HEAD(udev->data_tail, + (size_t)se_cmd->t_data_sg->length, udev->data_size); + + /* Get Data-In buffer */ + gather_and_free_data_area(udev, + se_cmd->t_bidi_data_sg, se_cmd->t_bidi_data_nents); + } else if (se_cmd->data_direction == DMA_FROM_DEVICE) { gather_and_free_data_area(udev, se_cmd->t_data_sg, se_cmd->t_data_nents); } else if (se_cmd->data_direction == DMA_TO_DEVICE) { -- cgit v1.2.3 From e1750d20e69477c0d7b26d6e0ba24c3c9ec47530 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 13 Apr 2015 19:51:13 +0200 Subject: target: make the tpg_get_default_depth method optional All fabric drivers except for iSCSI always return 1, so implement that as default behavior. Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 8 -------- drivers/infiniband/ulp/srpt/ib_srpt.c | 6 ------ drivers/scsi/qla2xxx/tcm_qla2xxx.c | 7 ------- drivers/target/loopback/tcm_loop.c | 6 ------ drivers/target/sbp/sbp_target.c | 6 ------ drivers/target/target_core_configfs.c | 4 ---- drivers/target/target_core_tpg.c | 5 ++++- drivers/target/tcm_fc/tfc_conf.c | 6 ------ drivers/usb/gadget/legacy/tcm_usb_gadget.c | 6 ------ drivers/vhost/scsi.c | 6 ------ drivers/xen/xen-scsiback.c | 6 ------ 11 files changed, 4 insertions(+), 62 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 2ba71cea0172..3dab9b28f4f0 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -377,7 +377,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .get_fabric_proto_ident = " + fabric_mod_name + "_get_fabric_proto_ident,\n" buf += " .tpg_get_wwn = " + fabric_mod_name + "_get_fabric_wwn,\n" buf += " .tpg_get_tag = " + fabric_mod_name + "_get_tag,\n" - buf += " .tpg_get_default_depth = " + fabric_mod_name + "_get_default_depth,\n" buf += " .tpg_get_pr_transport_id = " + fabric_mod_name + "_get_pr_transport_id,\n" buf += " .tpg_get_pr_transport_id_len = " + fabric_mod_name + "_get_pr_transport_id_len,\n" buf += " .tpg_parse_pr_out_transport_id = " + fabric_mod_name + "_parse_pr_out_transport_id,\n" @@ -590,13 +589,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "}\n\n" bufi += "u16 " + fabric_mod_name + "_get_tag(struct se_portal_group *);\n" - if re.search('get_default_depth', fo): - buf += "u32 " + fabric_mod_name + "_get_default_depth(struct se_portal_group *se_tpg)\n" - buf += "{\n" - buf += " return 1;\n" - buf += "}\n\n" - bufi += "u32 " + fabric_mod_name + "_get_default_depth(struct se_portal_group *);\n" - if re.search('get_pr_transport_id\)\(', fo): buf += "u32 " + fabric_mod_name + "_get_pr_transport_id(\n" buf += " struct se_portal_group *se_tpg,\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 6fbc7bc824d2..8198d4cb0694 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -3411,11 +3411,6 @@ static u16 srpt_get_tag(struct se_portal_group *tpg) return 1; } -static u32 srpt_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static u32 srpt_get_pr_transport_id(struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, struct t10_pr_registration *pr_reg, @@ -3920,7 +3915,6 @@ static const struct target_core_fabric_ops srpt_template = { .get_fabric_proto_ident = srpt_get_fabric_proto_ident, .tpg_get_wwn = srpt_get_fabric_wwn, .tpg_get_tag = srpt_get_tag, - .tpg_get_default_depth = srpt_get_default_depth, .tpg_get_pr_transport_id = srpt_get_pr_transport_id, .tpg_get_pr_transport_id_len = srpt_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = srpt_parse_pr_out_transport_id, diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index 8a6c87547303..5d69abcf9ed0 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -223,11 +223,6 @@ static u16 tcm_qla2xxx_get_tag(struct se_portal_group *se_tpg) return tpg->lport_tpgt; } -static u32 tcm_qla2xxx_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static u32 tcm_qla2xxx_get_pr_transport_id( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -1991,7 +1986,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { .get_fabric_proto_ident = tcm_qla2xxx_get_fabric_proto_ident, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, .tpg_get_tag = tcm_qla2xxx_get_tag, - .tpg_get_default_depth = tcm_qla2xxx_get_default_depth, .tpg_get_pr_transport_id = tcm_qla2xxx_get_pr_transport_id, .tpg_get_pr_transport_id_len = tcm_qla2xxx_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = tcm_qla2xxx_parse_pr_out_transport_id, @@ -2049,7 +2043,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .get_fabric_proto_ident = tcm_qla2xxx_get_fabric_proto_ident, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, .tpg_get_tag = tcm_qla2xxx_get_tag, - .tpg_get_default_depth = tcm_qla2xxx_get_default_depth, .tpg_get_pr_transport_id = tcm_qla2xxx_get_pr_transport_id, .tpg_get_pr_transport_id_len = tcm_qla2xxx_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = tcm_qla2xxx_parse_pr_out_transport_id, diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index e11bcf3e0889..12b85b03e9ae 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -566,11 +566,6 @@ static u16 tcm_loop_get_tag(struct se_portal_group *se_tpg) return tl_tpg->tl_tpgt; } -static u32 tcm_loop_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static u32 tcm_loop_get_pr_transport_id( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -1378,7 +1373,6 @@ static const struct target_core_fabric_ops loop_ops = { .get_fabric_proto_ident = tcm_loop_get_fabric_proto_ident, .tpg_get_wwn = tcm_loop_get_endpoint_wwn, .tpg_get_tag = tcm_loop_get_tag, - .tpg_get_default_depth = tcm_loop_get_default_depth, .tpg_get_pr_transport_id = tcm_loop_get_pr_transport_id, .tpg_get_pr_transport_id_len = tcm_loop_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = tcm_loop_parse_pr_out_transport_id, diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 61da83be8966..0d70d4f58e43 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -1707,11 +1707,6 @@ static u16 sbp_get_tag(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 sbp_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static struct se_node_acl *sbp_alloc_fabric_acl(struct se_portal_group *se_tpg) { return kzalloc(sizeof(struct se_node_acl), GFP_KERNEL); @@ -2490,7 +2485,6 @@ static const struct target_core_fabric_ops sbp_ops = { .get_fabric_proto_ident = sbp_get_fabric_proto_ident, .tpg_get_wwn = sbp_get_fabric_wwn, .tpg_get_tag = sbp_get_tag, - .tpg_get_default_depth = sbp_get_default_depth, .tpg_get_pr_transport_id = sbp_get_pr_transport_id, .tpg_get_pr_transport_id_len = sbp_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = sbp_parse_pr_out_transport_id, diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c index e7b0430a0575..c87ca0c50545 100644 --- a/drivers/target/target_core_configfs.c +++ b/drivers/target/target_core_configfs.c @@ -330,10 +330,6 @@ static int target_fabric_tf_ops_check(const struct target_core_fabric_ops *tfo) pr_err("Missing tfo->tpg_get_tag()\n"); return -EINVAL; } - if (!tfo->tpg_get_default_depth) { - pr_err("Missing tfo->tpg_get_default_depth()\n"); - return -EINVAL; - } if (!tfo->tpg_get_pr_transport_id) { pr_err("Missing tfo->tpg_get_pr_transport_id()\n"); return -EINVAL; diff --git a/drivers/target/target_core_tpg.c b/drivers/target/target_core_tpg.c index 47f064415bf6..5a9deb2b24af 100644 --- a/drivers/target/target_core_tpg.c +++ b/drivers/target/target_core_tpg.c @@ -282,7 +282,10 @@ struct se_node_acl *core_tpg_check_initiator_node_acl( spin_lock_init(&acl->device_list_lock); spin_lock_init(&acl->nacl_sess_lock); atomic_set(&acl->acl_pr_ref_count, 0); - acl->queue_depth = tpg->se_tpg_tfo->tpg_get_default_depth(tpg); + if (tpg->se_tpg_tfo->tpg_get_default_depth) + acl->queue_depth = tpg->se_tpg_tfo->tpg_get_default_depth(tpg); + else + acl->queue_depth = 1; snprintf(acl->initiatorname, TRANSPORT_IQN_LEN, "%s", initiatorname); acl->se_tpg = tpg; acl->acl_index = scsi_get_new_index(SCSI_AUTH_INTR_INDEX); diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index 65dce1345966..46b4387460e5 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -486,11 +486,6 @@ static u16 ft_get_tag(struct se_portal_group *se_tpg) return tpg->index; } -static u32 ft_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static int ft_check_false(struct se_portal_group *se_tpg) { return 0; @@ -514,7 +509,6 @@ static const struct target_core_fabric_ops ft_fabric_ops = { .get_fabric_proto_ident = fc_get_fabric_proto_ident, .tpg_get_wwn = ft_get_fabric_wwn, .tpg_get_tag = ft_get_tag, - .tpg_get_default_depth = ft_get_default_depth, .tpg_get_pr_transport_id = fc_get_pr_transport_id, .tpg_get_pr_transport_id_len = fc_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = fc_parse_pr_out_transport_id, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index aba80e245e44..b7a78f72fb0e 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1307,11 +1307,6 @@ static u16 usbg_get_tag(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 usbg_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static u32 usbg_get_pr_transport_id( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -1852,7 +1847,6 @@ static const struct target_core_fabric_ops usbg_ops = { .get_fabric_proto_ident = usbg_get_fabric_proto_ident, .tpg_get_wwn = usbg_get_fabric_wwn, .tpg_get_tag = usbg_get_tag, - .tpg_get_default_depth = usbg_get_default_depth, .tpg_get_pr_transport_id = usbg_get_pr_transport_id, .tpg_get_pr_transport_id_len = usbg_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = usbg_parse_pr_out_transport_id, diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index d21f2ba6c899..fb8a93d5bfba 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -326,11 +326,6 @@ static u16 vhost_scsi_get_tpgt(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 vhost_scsi_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static u32 vhost_scsi_get_pr_transport_id(struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -2300,7 +2295,6 @@ static struct target_core_fabric_ops vhost_scsi_ops = { .get_fabric_proto_ident = vhost_scsi_get_fabric_proto_ident, .tpg_get_wwn = vhost_scsi_get_fabric_wwn, .tpg_get_tag = vhost_scsi_get_tpgt, - .tpg_get_default_depth = vhost_scsi_get_default_depth, .tpg_get_pr_transport_id = vhost_scsi_get_pr_transport_id, .tpg_get_pr_transport_id_len = vhost_scsi_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = vhost_scsi_parse_pr_out_transport_id, diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index b7f51504f85a..c0d4aee0eeb5 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -1292,11 +1292,6 @@ static u16 scsiback_get_tag(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 scsiback_get_default_depth(struct se_portal_group *se_tpg) -{ - return 1; -} - static u32 scsiback_get_pr_transport_id(struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -1950,7 +1945,6 @@ static const struct target_core_fabric_ops scsiback_ops = { .get_fabric_proto_ident = scsiback_get_fabric_proto_ident, .tpg_get_wwn = scsiback_get_fabric_wwn, .tpg_get_tag = scsiback_get_tag, - .tpg_get_default_depth = scsiback_get_default_depth, .tpg_get_pr_transport_id = scsiback_get_pr_transport_id, .tpg_get_pr_transport_id_len = scsiback_get_pr_transport_id_len, .tpg_parse_pr_out_transport_id = scsiback_parse_pr_out_transport_id, -- cgit v1.2.3 From c7d6a803926bae9bbf4510a18fc8dd8957cc0e01 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 13 Apr 2015 19:51:14 +0200 Subject: target: refactor init/drop_nodeacl methods By always allocating and adding, respectively removing and freeing the se_node_acl structure in core code we can remove tons of repeated code in the init_nodeacl and drop_nodeacl routines. Additionally this now respects the get_default_queue_depth method in this code path as well. Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 77 ---------------------------- Documentation/target/tcm_mod_builder.txt | 4 +- drivers/infiniband/ulp/srpt/ib_srpt.c | 58 +++++---------------- drivers/scsi/qla2xxx/tcm_qla2xxx.c | 59 +++------------------ drivers/target/iscsi/iscsi_target_configfs.c | 49 ++++-------------- drivers/target/sbp/sbp_target.c | 36 ++----------- drivers/target/target_core_fabric_configfs.c | 22 ++++---- drivers/target/target_core_internal.h | 3 ++ drivers/target/target_core_tpg.c | 46 ++++------------- drivers/target/tcm_fc/tfc_conf.c | 48 +++-------------- drivers/usb/gadget/legacy/tcm_usb_gadget.c | 42 ++------------- drivers/vhost/scsi.c | 39 -------------- drivers/xen/xen-scsiback.c | 6 --- include/target/target_core_fabric.h | 9 +--- 14 files changed, 77 insertions(+), 421 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 3dab9b28f4f0..3e54809b3aa1 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -50,15 +50,6 @@ def tcm_mod_build_FC_include(fabric_mod_dir_var, fabric_mod_name): buf = "#define " + fabric_mod_name.upper() + "_VERSION \"v0.1\"\n" buf += "#define " + fabric_mod_name.upper() + "_NAMELEN 32\n" buf += "\n" - buf += "struct " + fabric_mod_name + "_nacl {\n" - buf += " /* Binary World Wide unique Port Name for FC Initiator Nport */\n" - buf += " u64 nport_wwpn;\n" - buf += " /* ASCII formatted WWPN for FC Initiator Nport */\n" - buf += " char nport_name[" + fabric_mod_name.upper() + "_NAMELEN];\n" - buf += " /* Returned by " + fabric_mod_name + "_make_nodeacl() */\n" - buf += " struct se_node_acl se_node_acl;\n" - buf += "};\n" - buf += "\n" buf += "struct " + fabric_mod_name + "_tpg {\n" buf += " /* FC lport target portal group tag for TCM */\n" buf += " u16 lport_tpgt;\n" @@ -105,14 +96,6 @@ def tcm_mod_build_SAS_include(fabric_mod_dir_var, fabric_mod_name): buf = "#define " + fabric_mod_name.upper() + "_VERSION \"v0.1\"\n" buf += "#define " + fabric_mod_name.upper() + "_NAMELEN 32\n" buf += "\n" - buf += "struct " + fabric_mod_name + "_nacl {\n" - buf += " /* Binary World Wide unique Port Name for SAS Initiator port */\n" - buf += " u64 iport_wwpn;\n" - buf += " /* ASCII formatted WWPN for Sas Initiator port */\n" - buf += " char iport_name[" + fabric_mod_name.upper() + "_NAMELEN];\n" - buf += " /* Returned by " + fabric_mod_name + "_make_nodeacl() */\n" - buf += " struct se_node_acl se_node_acl;\n" - buf += "};\n\n" buf += "struct " + fabric_mod_name + "_tpg {\n" buf += " /* SAS port target portal group tag for TCM */\n" buf += " u16 tport_tpgt;\n" @@ -158,12 +141,6 @@ def tcm_mod_build_iSCSI_include(fabric_mod_dir_var, fabric_mod_name): buf = "#define " + fabric_mod_name.upper() + "_VERSION \"v0.1\"\n" buf += "#define " + fabric_mod_name.upper() + "_NAMELEN 32\n" buf += "\n" - buf += "struct " + fabric_mod_name + "_nacl {\n" - buf += " /* ASCII formatted InitiatorName */\n" - buf += " char iport_name[" + fabric_mod_name.upper() + "_NAMELEN];\n" - buf += " /* Returned by " + fabric_mod_name + "_make_nodeacl() */\n" - buf += " struct se_node_acl se_node_acl;\n" - buf += "};\n\n" buf += "struct " + fabric_mod_name + "_tpg {\n" buf += " /* iSCSI target portal group tag for TCM */\n" buf += " u16 tport_tpgt;\n" @@ -239,54 +216,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "static const struct target_core_fabric_ops " + fabric_mod_name + "_ops;\n\n" - buf += "static struct se_node_acl *" + fabric_mod_name + "_make_nodeacl(\n" - buf += " struct se_portal_group *se_tpg,\n" - buf += " struct config_group *group,\n" - buf += " const char *name)\n" - buf += "{\n" - buf += " struct se_node_acl *se_nacl, *se_nacl_new;\n" - buf += " struct " + fabric_mod_name + "_nacl *nacl;\n" - - if proto_ident == "FC" or proto_ident == "SAS": - buf += " u64 wwpn = 0;\n" - - buf += " u32 nexus_depth;\n\n" - buf += " /* " + fabric_mod_name + "_parse_wwn(name, &wwpn, 1) < 0)\n" - buf += " return ERR_PTR(-EINVAL); */\n" - buf += " se_nacl_new = " + fabric_mod_name + "_alloc_fabric_acl(se_tpg);\n" - buf += " if (!se_nacl_new)\n" - buf += " return ERR_PTR(-ENOMEM);\n" - buf += "//#warning FIXME: Hardcoded nexus depth in " + fabric_mod_name + "_make_nodeacl()\n" - buf += " nexus_depth = 1;\n" - buf += " /*\n" - buf += " * se_nacl_new may be released by core_tpg_add_initiator_node_acl()\n" - buf += " * when converting a NodeACL from demo mode -> explict\n" - buf += " */\n" - buf += " se_nacl = core_tpg_add_initiator_node_acl(se_tpg, se_nacl_new,\n" - buf += " name, nexus_depth);\n" - buf += " if (IS_ERR(se_nacl)) {\n" - buf += " " + fabric_mod_name + "_release_fabric_acl(se_tpg, se_nacl_new);\n" - buf += " return se_nacl;\n" - buf += " }\n" - buf += " /*\n" - buf += " * Locate our struct " + fabric_mod_name + "_nacl and set the FC Nport WWPN\n" - buf += " */\n" - buf += " nacl = container_of(se_nacl, struct " + fabric_mod_name + "_nacl, se_node_acl);\n" - - if proto_ident == "FC" or proto_ident == "SAS": - buf += " nacl->" + fabric_mod_init_port + "_wwpn = wwpn;\n" - - buf += " /* " + fabric_mod_name + "_format_wwn(&nacl->" + fabric_mod_init_port + "_name[0], " + fabric_mod_name.upper() + "_NAMELEN, wwpn); */\n\n" - buf += " return se_nacl;\n" - buf += "}\n\n" - buf += "static void " + fabric_mod_name + "_drop_nodeacl(struct se_node_acl *se_acl)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_nacl *nacl = container_of(se_acl,\n" - buf += " struct " + fabric_mod_name + "_nacl, se_node_acl);\n" - buf += " core_tpg_del_initiator_node_acl(se_acl->se_tpg, se_acl, 1);\n" - buf += " kfree(nacl);\n" - buf += "}\n\n" - buf += "static struct se_portal_group *" + fabric_mod_name + "_make_tpg(\n" buf += " struct se_wwn *wwn,\n" buf += " struct config_group *group,\n" @@ -408,12 +337,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .fabric_drop_wwn = " + fabric_mod_name + "_drop_" + fabric_mod_port + ",\n" buf += " .fabric_make_tpg = " + fabric_mod_name + "_make_tpg,\n" buf += " .fabric_drop_tpg = " + fabric_mod_name + "_drop_tpg,\n" - buf += " .fabric_post_link = NULL,\n" - buf += " .fabric_pre_unlink = NULL,\n" - buf += " .fabric_make_np = NULL,\n" - buf += " .fabric_drop_np = NULL,\n" - buf += " .fabric_make_nodeacl = " + fabric_mod_name + "_make_nodeacl,\n" - buf += " .fabric_drop_nodeacl = " + fabric_mod_name + "_drop_nodeacl,\n" buf += "\n" buf += " .tfc_wwn_attrs = " + fabric_mod_name + "_wwn_attrs;\n" buf += "};\n\n" diff --git a/Documentation/target/tcm_mod_builder.txt b/Documentation/target/tcm_mod_builder.txt index 84533d8e747f..ae22f7005540 100644 --- a/Documentation/target/tcm_mod_builder.txt +++ b/Documentation/target/tcm_mod_builder.txt @@ -13,8 +13,8 @@ fabric skeleton, by simply using: This script will create a new drivers/target/$TCM_NEW_MOD/, and will do the following *) Generate new API callers for drivers/target/target_core_fabric_configs.c logic - ->make_nodeacl(), ->drop_nodeacl(), ->make_tpg(), ->drop_tpg() - ->make_wwn(), ->drop_wwn(). These are created into $TCM_NEW_MOD/$TCM_NEW_MOD_configfs.c + ->make_tpg(), ->drop_tpg(), ->make_wwn(), ->drop_wwn(). These are created + into $TCM_NEW_MOD/$TCM_NEW_MOD_configfs.c *) Generate basic infrastructure for loading/unloading LKMs and TCM/ConfigFS fabric module using a skeleton struct target_core_fabric_ops API template. *) Based on user defined T10 Proto_Ident for the new fabric module being built, diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 8198d4cb0694..c1f3aa52f42b 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -3592,40 +3592,19 @@ out: * configfs callback function invoked for * mkdir /sys/kernel/config/target/$driver/$port/$tpg/acls/$i_port_id */ -static struct se_node_acl *srpt_make_nodeacl(struct se_portal_group *tpg, - struct config_group *group, - const char *name) +static int srpt_init_nodeacl(struct se_node_acl *se_nacl, const char *name) { - struct srpt_port *sport = container_of(tpg, struct srpt_port, port_tpg_1); - struct se_node_acl *se_nacl, *se_nacl_new; - struct srpt_node_acl *nacl; - int ret = 0; - u32 nexus_depth = 1; + struct srpt_port *sport = + container_of(se_nacl->se_tpg, struct srpt_port, port_tpg_1); + struct srpt_node_acl *nacl = + container_of(se_nacl, struct srpt_node_acl, nacl); u8 i_port_id[16]; if (srpt_parse_i_port_id(i_port_id, name) < 0) { pr_err("invalid initiator port ID %s\n", name); - ret = -EINVAL; - goto err; + return -EINVAL; } - se_nacl_new = srpt_alloc_fabric_acl(tpg); - if (!se_nacl_new) { - ret = -ENOMEM; - goto err; - } - /* - * nacl_new may be released by core_tpg_add_initiator_node_acl() - * when converting a node ACL from demo mode to explict - */ - se_nacl = core_tpg_add_initiator_node_acl(tpg, se_nacl_new, name, - nexus_depth); - if (IS_ERR(se_nacl)) { - ret = PTR_ERR(se_nacl); - goto err; - } - /* Locate our struct srpt_node_acl and set sdev and i_port_id. */ - nacl = container_of(se_nacl, struct srpt_node_acl, nacl); memcpy(&nacl->i_port_id[0], &i_port_id[0], 16); nacl->sport = sport; @@ -3633,29 +3612,22 @@ static struct se_node_acl *srpt_make_nodeacl(struct se_portal_group *tpg, list_add_tail(&nacl->list, &sport->port_acl_list); spin_unlock_irq(&sport->port_acl_lock); - return se_nacl; -err: - return ERR_PTR(ret); + return 0; } /* * configfs callback function invoked for * rmdir /sys/kernel/config/target/$driver/$port/$tpg/acls/$i_port_id */ -static void srpt_drop_nodeacl(struct se_node_acl *se_nacl) +static void srpt_cleanup_nodeacl(struct se_node_acl *se_nacl) { - struct srpt_node_acl *nacl; - struct srpt_device *sdev; - struct srpt_port *sport; + struct srpt_node_acl *nacl = + container_of(se_nacl, struct srpt_node_acl, nacl); + struct srpt_port *sport = nacl->sport; - nacl = container_of(se_nacl, struct srpt_node_acl, nacl); - sport = nacl->sport; - sdev = sport->sdev; spin_lock_irq(&sport->port_acl_lock); list_del(&nacl->list); spin_unlock_irq(&sport->port_acl_lock); - core_tpg_del_initiator_node_acl(&sport->port_tpg_1, se_nacl, 1); - srpt_release_fabric_acl(NULL, se_nacl); } static ssize_t srpt_tpg_attrib_show_srp_max_rdma_size( @@ -3948,12 +3920,8 @@ static const struct target_core_fabric_ops srpt_template = { .fabric_drop_wwn = srpt_drop_tport, .fabric_make_tpg = srpt_make_tpg, .fabric_drop_tpg = srpt_drop_tpg, - .fabric_post_link = NULL, - .fabric_pre_unlink = NULL, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, - .fabric_make_nodeacl = srpt_make_nodeacl, - .fabric_drop_nodeacl = srpt_drop_nodeacl, + .fabric_init_nodeacl = srpt_init_nodeacl, + .fabric_cleanup_nodeacl = srpt_cleanup_nodeacl, .tfc_wwn_attrs = srpt_wwn_attrs, .tfc_tpg_base_attrs = srpt_tpg_attrs, diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index 5d69abcf9ed0..a7ab689f5524 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -847,53 +847,20 @@ static void tcm_qla2xxx_shutdown_sess(struct qla_tgt_sess *sess) target_sess_cmd_list_set_waiting(sess->se_sess); } -static struct se_node_acl *tcm_qla2xxx_make_nodeacl( - struct se_portal_group *se_tpg, - struct config_group *group, - const char *name) +static int tcm_qla2xxx_init_nodeacl(struct se_node_acl *se_nacl, + const char *name) { - struct se_node_acl *se_nacl, *se_nacl_new; - struct tcm_qla2xxx_nacl *nacl; + struct tcm_qla2xxx_nacl *nacl = + container_of(se_nacl, struct tcm_qla2xxx_nacl, se_node_acl); u64 wwnn; - u32 qla2xxx_nexus_depth; if (tcm_qla2xxx_parse_wwn(name, &wwnn, 1) < 0) - return ERR_PTR(-EINVAL); - - se_nacl_new = tcm_qla2xxx_alloc_fabric_acl(se_tpg); - if (!se_nacl_new) - return ERR_PTR(-ENOMEM); -/* #warning FIXME: Hardcoded qla2xxx_nexus depth in tcm_qla2xxx_make_nodeacl */ - qla2xxx_nexus_depth = 1; + return -EINVAL; - /* - * se_nacl_new may be released by core_tpg_add_initiator_node_acl() - * when converting a NodeACL from demo mode -> explict - */ - se_nacl = core_tpg_add_initiator_node_acl(se_tpg, se_nacl_new, - name, qla2xxx_nexus_depth); - if (IS_ERR(se_nacl)) { - tcm_qla2xxx_release_fabric_acl(se_tpg, se_nacl_new); - return se_nacl; - } - /* - * Locate our struct tcm_qla2xxx_nacl and set the FC Nport WWPN - */ - nacl = container_of(se_nacl, struct tcm_qla2xxx_nacl, se_node_acl); nacl->nport_wwnn = wwnn; tcm_qla2xxx_format_wwn(&nacl->nport_name[0], TCM_QLA2XXX_NAMELEN, wwnn); - return se_nacl; -} - -static void tcm_qla2xxx_drop_nodeacl(struct se_node_acl *se_acl) -{ - struct se_portal_group *se_tpg = se_acl->se_tpg; - struct tcm_qla2xxx_nacl *nacl = container_of(se_acl, - struct tcm_qla2xxx_nacl, se_node_acl); - - core_tpg_del_initiator_node_acl(se_tpg, se_acl, 1); - kfree(nacl); + return 0; } /* Start items for tcm_qla2xxx_tpg_attrib_cit */ @@ -2024,12 +1991,7 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { .fabric_drop_wwn = tcm_qla2xxx_drop_lport, .fabric_make_tpg = tcm_qla2xxx_make_tpg, .fabric_drop_tpg = tcm_qla2xxx_drop_tpg, - .fabric_post_link = NULL, - .fabric_pre_unlink = NULL, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, - .fabric_make_nodeacl = tcm_qla2xxx_make_nodeacl, - .fabric_drop_nodeacl = tcm_qla2xxx_drop_nodeacl, + .fabric_init_nodeacl = tcm_qla2xxx_init_nodeacl, .tfc_wwn_attrs = tcm_qla2xxx_wwn_attrs, .tfc_tpg_base_attrs = tcm_qla2xxx_tpg_attrs, @@ -2079,12 +2041,7 @@ static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .fabric_drop_wwn = tcm_qla2xxx_npiv_drop_lport, .fabric_make_tpg = tcm_qla2xxx_npiv_make_tpg, .fabric_drop_tpg = tcm_qla2xxx_drop_tpg, - .fabric_post_link = NULL, - .fabric_pre_unlink = NULL, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, - .fabric_make_nodeacl = tcm_qla2xxx_make_nodeacl, - .fabric_drop_nodeacl = tcm_qla2xxx_drop_nodeacl, + .fabric_init_nodeacl = tcm_qla2xxx_init_nodeacl, .tfc_wwn_attrs = tcm_qla2xxx_wwn_attrs, .tfc_tpg_base_attrs = tcm_qla2xxx_npiv_tpg_attrs, diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index 568e478615a5..7d9ff8cbbb5d 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -874,43 +874,19 @@ static struct se_node_acl *lio_tpg_alloc_fabric_acl( return &acl->se_node_acl; } -static struct se_node_acl *lio_target_make_nodeacl( - struct se_portal_group *se_tpg, - struct config_group *group, - const char *name) +static int lio_target_init_nodeacl(struct se_node_acl *se_nacl, + const char *name) { - struct config_group *stats_cg; - struct iscsi_node_acl *acl; - struct se_node_acl *se_nacl_new, *se_nacl; - struct iscsi_portal_group *tpg = container_of(se_tpg, - struct iscsi_portal_group, tpg_se_tpg); - u32 cmdsn_depth; - - se_nacl_new = lio_tpg_alloc_fabric_acl(se_tpg); - if (!se_nacl_new) - return ERR_PTR(-ENOMEM); - - cmdsn_depth = tpg->tpg_attrib.default_cmdsn_depth; - /* - * se_nacl_new may be released by core_tpg_add_initiator_node_acl() - * when converting a NdoeACL from demo mode -> explict - */ - se_nacl = core_tpg_add_initiator_node_acl(se_tpg, se_nacl_new, - name, cmdsn_depth); - if (IS_ERR(se_nacl)) - return se_nacl; - - acl = container_of(se_nacl, struct iscsi_node_acl, se_node_acl); - stats_cg = &se_nacl->acl_fabric_stat_group; + struct iscsi_node_acl *acl = + container_of(se_nacl, struct iscsi_node_acl, se_node_acl); + struct config_group *stats_cg = &se_nacl->acl_fabric_stat_group; stats_cg->default_groups = kmalloc(sizeof(struct config_group *) * 2, GFP_KERNEL); if (!stats_cg->default_groups) { pr_err("Unable to allocate memory for" " stats_cg->default_groups\n"); - core_tpg_del_initiator_node_acl(se_tpg, se_nacl, 1); - kfree(acl); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } stats_cg->default_groups[0] = &acl->node_stat_grps.iscsi_sess_stats_group; @@ -918,13 +894,11 @@ static struct se_node_acl *lio_target_make_nodeacl( config_group_init_type_name(&acl->node_stat_grps.iscsi_sess_stats_group, "iscsi_sess_stats", &iscsi_stat_sess_cit); - return se_nacl; + return 0; } -static void lio_target_drop_nodeacl( - struct se_node_acl *se_nacl) +static void lio_target_cleanup_nodeacl( struct se_node_acl *se_nacl) { - struct se_portal_group *se_tpg = se_nacl->se_tpg; struct iscsi_node_acl *acl = container_of(se_nacl, struct iscsi_node_acl, se_node_acl); struct config_item *df_item; @@ -938,9 +912,6 @@ static void lio_target_drop_nodeacl( config_item_put(df_item); } kfree(stats_cg->default_groups); - - core_tpg_del_initiator_node_acl(se_tpg, se_nacl, 1); - kfree(acl); } /* End items for lio_target_acl_cit */ @@ -2020,8 +1991,8 @@ const struct target_core_fabric_ops iscsi_ops = { .fabric_drop_tpg = lio_target_tiqn_deltpg, .fabric_make_np = lio_target_call_addnptotpg, .fabric_drop_np = lio_target_call_delnpfromtpg, - .fabric_make_nodeacl = lio_target_make_nodeacl, - .fabric_drop_nodeacl = lio_target_drop_nodeacl, + .fabric_init_nodeacl = lio_target_init_nodeacl, + .fabric_cleanup_nodeacl = lio_target_cleanup_nodeacl, .tfc_discovery_attrs = lio_target_discovery_auth_attrs, .tfc_wwn_attrs = lio_target_wwn_attrs, diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 0d70d4f58e43..3a47fe46fbca 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -2085,40 +2085,13 @@ static ssize_t sbp_format_wwn(char *buf, size_t len, u64 wwn) return snprintf(buf, len, "%016llx", wwn); } -static struct se_node_acl *sbp_make_nodeacl( - struct se_portal_group *se_tpg, - struct config_group *group, - const char *name) +static int sbp_init_nodeacl(struct se_node_acl *se_nacl, const char *name) { - struct se_node_acl *se_nacl, *se_nacl_new; u64 guid = 0; - u32 nexus_depth = 1; if (sbp_parse_wwn(name, &guid) < 0) - return ERR_PTR(-EINVAL); - - se_nacl_new = sbp_alloc_fabric_acl(se_tpg); - if (!se_nacl_new) - return ERR_PTR(-ENOMEM); - - /* - * se_nacl_new may be released by core_tpg_add_initiator_node_acl() - * when converting a NodeACL from demo mode -> explict - */ - se_nacl = core_tpg_add_initiator_node_acl(se_tpg, se_nacl_new, - name, nexus_depth); - if (IS_ERR(se_nacl)) { - sbp_release_fabric_acl(se_tpg, se_nacl_new); - return se_nacl; - } - - return se_nacl; -} - -static void sbp_drop_nodeacl(struct se_node_acl *se_acl) -{ - core_tpg_del_initiator_node_acl(se_acl->se_tpg, se_acl, 1); - kfree(se_acl); + return -EINVAL; + return 0; } static int sbp_post_link_lun( @@ -2518,8 +2491,7 @@ static const struct target_core_fabric_ops sbp_ops = { .fabric_pre_unlink = sbp_pre_unlink_lun, .fabric_make_np = NULL, .fabric_drop_np = NULL, - .fabric_make_nodeacl = sbp_make_nodeacl, - .fabric_drop_nodeacl = sbp_drop_nodeacl, + .fabric_init_nodeacl = sbp_init_nodeacl, .tfc_wwn_attrs = sbp_wwn_attrs, .tfc_tpg_base_attrs = sbp_tpg_base_attrs, diff --git a/drivers/target/target_core_fabric_configfs.c b/drivers/target/target_core_fabric_configfs.c index 1f7886bb16bf..f4d9467c3e14 100644 --- a/drivers/target/target_core_fabric_configfs.c +++ b/drivers/target/target_core_fabric_configfs.c @@ -458,10 +458,11 @@ static void target_fabric_nacl_base_release(struct config_item *item) { struct se_node_acl *se_nacl = container_of(to_config_group(item), struct se_node_acl, acl_group); - struct se_portal_group *se_tpg = se_nacl->se_tpg; - struct target_fabric_configfs *tf = se_tpg->se_tpg_wwn->wwn_tf; + struct target_fabric_configfs *tf = se_nacl->se_tpg->se_tpg_wwn->wwn_tf; - tf->tf_ops.fabric_drop_nodeacl(se_nacl); + if (tf->tf_ops.fabric_cleanup_nodeacl) + tf->tf_ops.fabric_cleanup_nodeacl(se_nacl); + core_tpg_del_initiator_node_acl(se_nacl); } static struct configfs_item_operations target_fabric_nacl_base_item_ops = { @@ -501,15 +502,18 @@ static struct config_group *target_fabric_make_nodeacl( struct se_node_acl *se_nacl; struct config_group *nacl_cg; - if (!tf->tf_ops.fabric_make_nodeacl) { - pr_err("tf->tf_ops.fabric_make_nodeacl is NULL\n"); - return ERR_PTR(-ENOSYS); - } - - se_nacl = tf->tf_ops.fabric_make_nodeacl(se_tpg, group, name); + se_nacl = core_tpg_add_initiator_node_acl(se_tpg, name); if (IS_ERR(se_nacl)) return ERR_CAST(se_nacl); + if (tf->tf_ops.fabric_init_nodeacl) { + int ret = tf->tf_ops.fabric_init_nodeacl(se_nacl, name); + if (ret) { + core_tpg_del_initiator_node_acl(se_nacl); + return ERR_PTR(ret); + } + } + nacl_cg = &se_nacl->acl_group; nacl_cg->default_groups = se_nacl->acl_default_groups; nacl_cg->default_groups[0] = &se_nacl->acl_attrib_group; diff --git a/drivers/target/target_core_internal.h b/drivers/target/target_core_internal.h index 75338c348be4..058ca71cda81 100644 --- a/drivers/target/target_core_internal.h +++ b/drivers/target/target_core_internal.h @@ -59,6 +59,9 @@ struct se_lun *core_tpg_alloc_lun(struct se_portal_group *, u32); int core_tpg_add_lun(struct se_portal_group *, struct se_lun *, u32, struct se_device *); void core_tpg_remove_lun(struct se_portal_group *, struct se_lun *); +struct se_node_acl *core_tpg_add_initiator_node_acl(struct se_portal_group *tpg, + const char *initiatorname); +void core_tpg_del_initiator_node_acl(struct se_node_acl *acl); /* target_core_transport.c */ extern struct kmem_cache *se_tmr_req_cache; diff --git a/drivers/target/target_core_tpg.c b/drivers/target/target_core_tpg.c index 5a9deb2b24af..78dd53ada04a 100644 --- a/drivers/target/target_core_tpg.c +++ b/drivers/target/target_core_tpg.c @@ -353,17 +353,11 @@ void core_tpg_clear_object_luns(struct se_portal_group *tpg) } EXPORT_SYMBOL(core_tpg_clear_object_luns); -/* core_tpg_add_initiator_node_acl(): - * - * - */ struct se_node_acl *core_tpg_add_initiator_node_acl( struct se_portal_group *tpg, - struct se_node_acl *se_nacl, - const char *initiatorname, - u32 queue_depth) + const char *initiatorname) { - struct se_node_acl *acl = NULL; + struct se_node_acl *acl; spin_lock_irq(&tpg->acl_node_lock); acl = __core_tpg_get_initiator_node_acl(tpg, initiatorname); @@ -374,14 +368,6 @@ struct se_node_acl *core_tpg_add_initiator_node_acl( " for %s\n", tpg->se_tpg_tfo->get_fabric_name(), tpg->se_tpg_tfo->tpg_get_tag(tpg), initiatorname); spin_unlock_irq(&tpg->acl_node_lock); - /* - * Release the locally allocated struct se_node_acl - * because * core_tpg_add_initiator_node_acl() returned - * a pointer to an existing demo mode node ACL. - */ - if (se_nacl) - tpg->se_tpg_tfo->tpg_release_fabric_acl(tpg, - se_nacl); goto done; } @@ -394,16 +380,11 @@ struct se_node_acl *core_tpg_add_initiator_node_acl( } spin_unlock_irq(&tpg->acl_node_lock); - if (!se_nacl) { + acl = tpg->se_tpg_tfo->tpg_alloc_fabric_acl(tpg); + if (!acl) { pr_err("struct se_node_acl pointer is NULL\n"); return ERR_PTR(-EINVAL); } - /* - * For v4.x logic the se_node_acl_s is hanging off a fabric - * dependent structure allocated via - * struct target_core_fabric_ops->fabric_make_nodeacl() - */ - acl = se_nacl; INIT_LIST_HEAD(&acl->acl_list); INIT_LIST_HEAD(&acl->acl_sess_list); @@ -412,7 +393,10 @@ struct se_node_acl *core_tpg_add_initiator_node_acl( spin_lock_init(&acl->device_list_lock); spin_lock_init(&acl->nacl_sess_lock); atomic_set(&acl->acl_pr_ref_count, 0); - acl->queue_depth = queue_depth; + if (tpg->se_tpg_tfo->tpg_get_default_depth) + acl->queue_depth = tpg->se_tpg_tfo->tpg_get_default_depth(tpg); + else + acl->queue_depth = 1; snprintf(acl->initiatorname, TRANSPORT_IQN_LEN, "%s", initiatorname); acl->se_tpg = tpg; acl->acl_index = scsi_get_new_index(SCSI_AUTH_INTR_INDEX); @@ -443,17 +427,10 @@ done: return acl; } -EXPORT_SYMBOL(core_tpg_add_initiator_node_acl); -/* core_tpg_del_initiator_node_acl(): - * - * - */ -int core_tpg_del_initiator_node_acl( - struct se_portal_group *tpg, - struct se_node_acl *acl, - int force) +void core_tpg_del_initiator_node_acl(struct se_node_acl *acl) { + struct se_portal_group *tpg = acl->se_tpg; LIST_HEAD(sess_list); struct se_session *sess, *sess_tmp; unsigned long flags; @@ -505,9 +482,8 @@ int core_tpg_del_initiator_node_acl( tpg->se_tpg_tfo->tpg_get_tag(tpg), acl->queue_depth, tpg->se_tpg_tfo->get_fabric_name(), acl->initiatorname); - return 0; + tpg->se_tpg_tfo->tpg_release_fabric_acl(tpg, acl); } -EXPORT_SYMBOL(core_tpg_del_initiator_node_acl); /* core_tpg_set_initiator_node_queue_depth(): * diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index 46b4387460e5..e179fdf76ddb 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -198,48 +198,17 @@ static struct configfs_attribute *ft_nacl_base_attrs[] = { * Add ACL for an initiator. The ACL is named arbitrarily. * The port_name and/or node_name are attributes. */ -static struct se_node_acl *ft_add_acl( - struct se_portal_group *se_tpg, - struct config_group *group, - const char *name) +static int ft_init_nodeacl(struct se_node_acl *nacl, const char *name) { - struct ft_node_acl *acl; - struct ft_tpg *tpg; + struct ft_node_acl *acl = + container_of(nacl, struct ft_node_acl, se_node_acl); u64 wwpn; - u32 q_depth; - - pr_debug("add acl %s\n", name); - tpg = container_of(se_tpg, struct ft_tpg, se_tpg); if (ft_parse_wwn(name, &wwpn, 1) < 0) - return ERR_PTR(-EINVAL); + return -EINVAL; - acl = kzalloc(sizeof(struct ft_node_acl), GFP_KERNEL); - if (!acl) - return ERR_PTR(-ENOMEM); acl->node_auth.port_name = wwpn; - - q_depth = 32; /* XXX bogus default - get from tpg? */ - return core_tpg_add_initiator_node_acl(&tpg->se_tpg, - &acl->se_node_acl, name, q_depth); -} - -static void ft_del_acl(struct se_node_acl *se_acl) -{ - struct se_portal_group *se_tpg = se_acl->se_tpg; - struct ft_tpg *tpg; - struct ft_node_acl *acl = container_of(se_acl, - struct ft_node_acl, se_node_acl); - - pr_debug("del acl %s\n", - config_item_name(&se_acl->acl_group.cg_item)); - - tpg = container_of(se_tpg, struct ft_tpg, se_tpg); - pr_debug("del acl %p se_acl %p tpg %p se_tpg %p\n", - acl, se_acl, tpg, &tpg->se_tpg); - - core_tpg_del_initiator_node_acl(&tpg->se_tpg, se_acl, 1); - kfree(acl); + return 0; } struct ft_node_acl *ft_acl_get(struct ft_tpg *tpg, struct fc_rport_priv *rdata) @@ -542,12 +511,7 @@ static const struct target_core_fabric_ops ft_fabric_ops = { .fabric_drop_wwn = &ft_del_wwn, .fabric_make_tpg = &ft_add_tpg, .fabric_drop_tpg = &ft_del_tpg, - .fabric_post_link = NULL, - .fabric_pre_unlink = NULL, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, - .fabric_make_nodeacl = &ft_add_acl, - .fabric_drop_nodeacl = &ft_del_acl, + .fabric_init_nodeacl = &ft_init_nodeacl, .tfc_wwn_attrs = ft_wwn_attrs, .tfc_tpg_nacl_base_attrs = ft_nacl_base_attrs, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index b7a78f72fb0e..fccb0ccb355a 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1476,40 +1476,11 @@ static const char *usbg_check_wwn(const char *name) return n; } -static struct se_node_acl *usbg_make_nodeacl( - struct se_portal_group *se_tpg, - struct config_group *group, - const char *name) -{ - struct se_node_acl *se_nacl, *se_nacl_new; - u32 nexus_depth; - const char *wnn_name; - - wnn_name = usbg_check_wwn(name); - if (!wnn_name) - return ERR_PTR(-EINVAL); - se_nacl_new = usbg_alloc_fabric_acl(se_tpg); - if (!(se_nacl_new)) - return ERR_PTR(-ENOMEM); - - nexus_depth = 1; - /* - * se_nacl_new may be released by core_tpg_add_initiator_node_acl() - * when converting a NodeACL from demo mode -> explict - */ - se_nacl = core_tpg_add_initiator_node_acl(se_tpg, se_nacl_new, - name, nexus_depth); - if (IS_ERR(se_nacl)) { - usbg_release_fabric_acl(se_tpg, se_nacl_new); - return se_nacl; - } - return se_nacl; -} - -static void usbg_drop_nodeacl(struct se_node_acl *se_acl) +static int usbg_init_nodeacl(struct se_node_acl *se_nacl, const char *name) { - core_tpg_del_initiator_node_acl(se_acl->se_tpg, se_acl, 1); - kfree(se_acl); + if (!usbg_check_wwn(name)) + return -EINVAL; + return 0; } struct usbg_tpg *the_only_tpg_I_currently_have; @@ -1879,10 +1850,7 @@ static const struct target_core_fabric_ops usbg_ops = { .fabric_drop_tpg = usbg_drop_tpg, .fabric_post_link = usbg_port_link, .fabric_pre_unlink = usbg_port_unlink, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, - .fabric_make_nodeacl = usbg_make_nodeacl, - .fabric_drop_nodeacl = usbg_drop_nodeacl, + .fabric_init_nodeacl = usbg_init_nodeacl, .tfc_wwn_attrs = usbg_wwn_attrs, .tfc_tpg_base_attrs = usbg_base_attrs, diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index fb8a93d5bfba..8faa7f4abf23 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -1798,41 +1798,6 @@ static void vhost_scsi_port_unlink(struct se_portal_group *se_tpg, mutex_unlock(&vhost_scsi_mutex); } -static struct se_node_acl * -vhost_scsi_make_nodeacl(struct se_portal_group *se_tpg, - struct config_group *group, - const char *name) -{ - struct se_node_acl *se_nacl, *se_nacl_new; - u32 nexus_depth; - - /* vhost_scsi_parse_wwn(name, &wwpn, 1) < 0) - return ERR_PTR(-EINVAL); */ - se_nacl_new = vhost_scsi_alloc_fabric_acl(se_tpg); - if (!se_nacl_new) - return ERR_PTR(-ENOMEM); - - nexus_depth = 1; - /* - * se_nacl_new may be released by core_tpg_add_initiator_node_acl() - * when converting a NodeACL from demo mode -> explict - */ - se_nacl = core_tpg_add_initiator_node_acl(se_tpg, se_nacl_new, - name, nexus_depth); - if (IS_ERR(se_nacl)) { - vhost_scsi_release_fabric_acl(se_tpg, se_nacl_new); - return se_nacl; - } - - return se_nacl; -} - -static void vhost_scsi_drop_nodeacl(struct se_node_acl *se_acl) -{ - core_tpg_del_initiator_node_acl(se_acl->se_tpg, se_acl, 1); - kfree(se_acl); -} - static void vhost_scsi_free_cmd_map_res(struct vhost_scsi_nexus *nexus, struct se_session *se_sess) { @@ -2330,10 +2295,6 @@ static struct target_core_fabric_ops vhost_scsi_ops = { .fabric_drop_tpg = vhost_scsi_drop_tpg, .fabric_post_link = vhost_scsi_port_link, .fabric_pre_unlink = vhost_scsi_port_unlink, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, - .fabric_make_nodeacl = vhost_scsi_make_nodeacl, - .fabric_drop_nodeacl = vhost_scsi_drop_nodeacl, .tfc_wwn_attrs = vhost_scsi_wwn_attrs, .tfc_tpg_base_attrs = vhost_scsi_tpg_attrs, diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index c0d4aee0eeb5..8a130ab71733 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -1980,12 +1980,6 @@ static const struct target_core_fabric_ops scsiback_ops = { .fabric_drop_tpg = scsiback_drop_tpg, .fabric_post_link = scsiback_port_link, .fabric_pre_unlink = scsiback_port_unlink, - .fabric_make_np = NULL, - .fabric_drop_np = NULL, -#if 0 - .fabric_make_nodeacl = scsiback_make_nodeacl, - .fabric_drop_nodeacl = scsiback_drop_nodeacl, -#endif .tfc_wwn_attrs = scsiback_wwn_attrs, .tfc_tpg_base_attrs = scsiback_tpg_attrs, diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h index 24c8d9d0d946..8b570c49f4d1 100644 --- a/include/target/target_core_fabric.h +++ b/include/target/target_core_fabric.h @@ -88,9 +88,8 @@ struct target_core_fabric_ops { struct se_tpg_np *(*fabric_make_np)(struct se_portal_group *, struct config_group *, const char *); void (*fabric_drop_np)(struct se_tpg_np *); - struct se_node_acl *(*fabric_make_nodeacl)(struct se_portal_group *, - struct config_group *, const char *); - void (*fabric_drop_nodeacl)(struct se_node_acl *); + int (*fabric_init_nodeacl)(struct se_node_acl *, const char *); + void (*fabric_cleanup_nodeacl)(struct se_node_acl *); struct configfs_attribute **tfc_discovery_attrs; struct configfs_attribute **tfc_wwn_attrs; @@ -174,10 +173,6 @@ struct se_node_acl *core_tpg_get_initiator_node_acl(struct se_portal_group *tpg, struct se_node_acl *core_tpg_check_initiator_node_acl(struct se_portal_group *, unsigned char *); void core_tpg_clear_object_luns(struct se_portal_group *); -struct se_node_acl *core_tpg_add_initiator_node_acl(struct se_portal_group *, - struct se_node_acl *, const char *, u32); -int core_tpg_del_initiator_node_acl(struct se_portal_group *, - struct se_node_acl *, int); int core_tpg_set_initiator_node_queue_depth(struct se_portal_group *, unsigned char *, u32, int); int core_tpg_set_initiator_node_tag(struct se_portal_group *, -- cgit v1.2.3 From 144bc4c2a42a0f42a32c106d53f5bf2724fbf098 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 13 Apr 2015 19:51:16 +0200 Subject: target: move node ACL allocation to core code Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 27 -------------------------- drivers/infiniband/ulp/srpt/ib_srpt.c | 25 +----------------------- drivers/infiniband/ulp/srpt/ib_srpt.h | 4 ++-- drivers/scsi/qla2xxx/tcm_qla2xxx.c | 29 ++-------------------------- drivers/scsi/qla2xxx/tcm_qla2xxx.h | 4 ++-- drivers/target/iscsi/iscsi_target_configfs.c | 26 +------------------------ drivers/target/loopback/tcm_loop.c | 15 -------------- drivers/target/sbp/sbp_target.c | 14 -------------- drivers/target/target_core_configfs.c | 8 -------- drivers/target/target_core_tpg.c | 9 +++++---- drivers/target/target_core_transport.c | 2 +- drivers/target/tcm_fc/tcm_fc.h | 2 +- drivers/target/tcm_fc/tfc_conf.c | 26 +------------------------ drivers/usb/gadget/legacy/tcm_usb_gadget.c | 14 -------------- drivers/vhost/scsi.c | 15 -------------- drivers/xen/xen-scsiback.c | 15 -------------- include/target/iscsi/iscsi_target_core.h | 2 +- include/target/target_core_fabric.h | 5 +---- 18 files changed, 18 insertions(+), 224 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 3e54809b3aa1..07e7ef3d7429 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -313,8 +313,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .tpg_check_demo_mode_cache = " + fabric_mod_name + "_check_true,\n" buf += " .tpg_check_demo_mode_write_protect = " + fabric_mod_name + "_check_true,\n" buf += " .tpg_check_prod_mode_write_protect = " + fabric_mod_name + "_check_false,\n" - buf += " .tpg_alloc_fabric_acl = " + fabric_mod_name + "_alloc_fabric_acl,\n" - buf += " .tpg_release_fabric_acl = " + fabric_mod_name + "_release_fabric_acl,\n" buf += " .tpg_get_inst_index = " + fabric_mod_name + "_tpg_get_inst_index,\n" buf += " .release_cmd = " + fabric_mod_name + "_release_cmd,\n" buf += " .shutdown_session = " + fabric_mod_name + "_shutdown_session,\n" @@ -624,31 +622,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): bufi += "char *" + fabric_mod_name + "_parse_pr_out_transport_id(struct se_portal_group *,\n" bufi += " const char *, u32 *, char **);\n" - if re.search('alloc_fabric_acl\)\(', fo): - buf += "struct se_node_acl *" + fabric_mod_name + "_alloc_fabric_acl(struct se_portal_group *se_tpg)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_nacl *nacl;\n\n" - buf += " nacl = kzalloc(sizeof(struct " + fabric_mod_name + "_nacl), GFP_KERNEL);\n" - buf += " if (!nacl) {\n" - buf += " printk(KERN_ERR \"Unable to allocate struct " + fabric_mod_name + "_nacl\\n\");\n" - buf += " return NULL;\n" - buf += " }\n\n" - buf += " return &nacl->se_node_acl;\n" - buf += "}\n\n" - bufi += "struct se_node_acl *" + fabric_mod_name + "_alloc_fabric_acl(struct se_portal_group *);\n" - - if re.search('release_fabric_acl\)\(', fo): - buf += "void " + fabric_mod_name + "_release_fabric_acl(\n" - buf += " struct se_portal_group *se_tpg,\n" - buf += " struct se_node_acl *se_nacl)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_nacl *nacl = container_of(se_nacl,\n" - buf += " struct " + fabric_mod_name + "_nacl, se_node_acl);\n" - buf += " kfree(nacl);\n" - buf += "}\n\n" - bufi += "void " + fabric_mod_name + "_release_fabric_acl(struct se_portal_group *,\n" - bufi += " struct se_node_acl *);\n" - if re.search('tpg_get_inst_index\)\(', fo): buf += "u32 " + fabric_mod_name + "_tpg_get_inst_index(struct se_portal_group *se_tpg)\n" buf += "{\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index c1f3aa52f42b..38e51f4a17de 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -3447,28 +3447,6 @@ static char *srpt_parse_pr_out_transport_id(struct se_portal_group *se_tpg, return (char *)tr_id->i_port_id; } -static struct se_node_acl *srpt_alloc_fabric_acl(struct se_portal_group *se_tpg) -{ - struct srpt_node_acl *nacl; - - nacl = kzalloc(sizeof(struct srpt_node_acl), GFP_KERNEL); - if (!nacl) { - pr_err("Unable to allocate struct srpt_node_acl\n"); - return NULL; - } - - return &nacl->nacl; -} - -static void srpt_release_fabric_acl(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - struct srpt_node_acl *nacl; - - nacl = container_of(se_nacl, struct srpt_node_acl, nacl); - kfree(nacl); -} - static u32 srpt_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -3883,6 +3861,7 @@ static struct configfs_attribute *srpt_wwn_attrs[] = { static const struct target_core_fabric_ops srpt_template = { .module = THIS_MODULE, .name = "srpt", + .node_acl_size = sizeof(struct srpt_node_acl), .get_fabric_name = srpt_get_fabric_name, .get_fabric_proto_ident = srpt_get_fabric_proto_ident, .tpg_get_wwn = srpt_get_fabric_wwn, @@ -3894,8 +3873,6 @@ static const struct target_core_fabric_ops srpt_template = { .tpg_check_demo_mode_cache = srpt_check_true, .tpg_check_demo_mode_write_protect = srpt_check_true, .tpg_check_prod_mode_write_protect = srpt_check_false, - .tpg_alloc_fabric_acl = srpt_alloc_fabric_acl, - .tpg_release_fabric_acl = srpt_release_fabric_acl, .tpg_get_inst_index = srpt_tpg_get_inst_index, .release_cmd = srpt_release_cmd, .check_stop_free = srpt_check_stop_free, diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h index 3dae156905de..355f6f5ce8b2 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.h +++ b/drivers/infiniband/ulp/srpt/ib_srpt.h @@ -410,15 +410,15 @@ struct srpt_device { /** * struct srpt_node_acl - Per-initiator ACL data (managed via configfs). + * @nacl: Target core node ACL information. * @i_port_id: 128-bit SRP initiator port ID. * @sport: port information. - * @nacl: Target core node ACL information. * @list: Element of the per-HCA ACL list. */ struct srpt_node_acl { + struct se_node_acl nacl; u8 i_port_id[16]; struct srpt_port *sport; - struct se_node_acl nacl; struct list_head list; }; diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index a7ab689f5524..cb376e5198d0 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -338,29 +338,6 @@ static int tcm_qla2xxx_check_prot_fabric_only(struct se_portal_group *se_tpg) return tpg->tpg_attrib.fabric_prot_type; } -static struct se_node_acl *tcm_qla2xxx_alloc_fabric_acl( - struct se_portal_group *se_tpg) -{ - struct tcm_qla2xxx_nacl *nacl; - - nacl = kzalloc(sizeof(struct tcm_qla2xxx_nacl), GFP_KERNEL); - if (!nacl) { - pr_err("Unable to allocate struct tcm_qla2xxx_nacl\n"); - return NULL; - } - - return &nacl->se_node_acl; -} - -static void tcm_qla2xxx_release_fabric_acl( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - struct tcm_qla2xxx_nacl *nacl = container_of(se_nacl, - struct tcm_qla2xxx_nacl, se_node_acl); - kfree(nacl); -} - static u32 tcm_qla2xxx_tpg_get_inst_index(struct se_portal_group *se_tpg) { struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, @@ -1949,6 +1926,7 @@ static struct configfs_attribute *tcm_qla2xxx_wwn_attrs[] = { static const struct target_core_fabric_ops tcm_qla2xxx_ops = { .module = THIS_MODULE, .name = "qla2xxx", + .node_acl_size = sizeof(struct tcm_qla2xxx_nacl), .get_fabric_name = tcm_qla2xxx_get_fabric_name, .get_fabric_proto_ident = tcm_qla2xxx_get_fabric_proto_ident, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, @@ -1964,8 +1942,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { tcm_qla2xxx_check_prod_write_protect, .tpg_check_prot_fabric_only = tcm_qla2xxx_check_prot_fabric_only, .tpg_check_demo_mode_login_only = tcm_qla2xxx_check_demo_mode_login_only, - .tpg_alloc_fabric_acl = tcm_qla2xxx_alloc_fabric_acl, - .tpg_release_fabric_acl = tcm_qla2xxx_release_fabric_acl, .tpg_get_inst_index = tcm_qla2xxx_tpg_get_inst_index, .check_stop_free = tcm_qla2xxx_check_stop_free, .release_cmd = tcm_qla2xxx_release_cmd, @@ -2001,6 +1977,7 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .module = THIS_MODULE, .name = "qla2xxx_npiv", + .node_acl_size = sizeof(struct tcm_qla2xxx_nacl), .get_fabric_name = tcm_qla2xxx_npiv_get_fabric_name, .get_fabric_proto_ident = tcm_qla2xxx_get_fabric_proto_ident, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, @@ -2014,8 +1991,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .tpg_check_prod_mode_write_protect = tcm_qla2xxx_check_prod_write_protect, .tpg_check_demo_mode_login_only = tcm_qla2xxx_check_demo_mode_login_only, - .tpg_alloc_fabric_acl = tcm_qla2xxx_alloc_fabric_acl, - .tpg_release_fabric_acl = tcm_qla2xxx_release_fabric_acl, .tpg_get_inst_index = tcm_qla2xxx_tpg_get_inst_index, .check_stop_free = tcm_qla2xxx_check_stop_free, .release_cmd = tcm_qla2xxx_release_cmd, diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.h b/drivers/scsi/qla2xxx/tcm_qla2xxx.h index 23295115c9fc..3d805a07061c 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.h +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.h @@ -13,6 +13,8 @@ #include "qla_target.h" struct tcm_qla2xxx_nacl { + struct se_node_acl se_node_acl; + /* From libfc struct fc_rport->port_id */ u32 nport_id; /* Binary World Wide unique Node Name for remote FC Initiator Nport */ @@ -23,8 +25,6 @@ struct tcm_qla2xxx_nacl { struct qla_tgt_sess *qla_tgt_sess; /* Pointer to TCM FC nexus */ struct se_session *nport_nexus; - /* Returned by tcm_qla2xxx_make_nodeacl() */ - struct se_node_acl se_node_acl; }; struct tcm_qla2xxx_tpg_attrib { diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index 7d9ff8cbbb5d..643024c1ee8d 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -860,20 +860,6 @@ static struct configfs_attribute *lio_target_initiator_attrs[] = { NULL, }; -static struct se_node_acl *lio_tpg_alloc_fabric_acl( - struct se_portal_group *se_tpg) -{ - struct iscsi_node_acl *acl; - - acl = kzalloc(sizeof(struct iscsi_node_acl), GFP_KERNEL); - if (!acl) { - pr_err("Unable to allocate memory for struct iscsi_node_acl\n"); - return NULL; - } - - return &acl->se_node_acl; -} - static int lio_target_init_nodeacl(struct se_node_acl *se_nacl, const char *name) { @@ -1868,15 +1854,6 @@ static int lio_tpg_check_prot_fabric_only( return tpg->tpg_attrib.fabric_prot_type; } -static void lio_tpg_release_fabric_acl( - struct se_portal_group *se_tpg, - struct se_node_acl *se_acl) -{ - struct iscsi_node_acl *acl = container_of(se_acl, - struct iscsi_node_acl, se_node_acl); - kfree(acl); -} - /* * Called with spin_lock_bh(struct se_portal_group->session_lock) held.. * @@ -1952,6 +1929,7 @@ static void lio_release_cmd(struct se_cmd *se_cmd) const struct target_core_fabric_ops iscsi_ops = { .module = THIS_MODULE, .name = "iscsi", + .node_acl_size = sizeof(struct iscsi_node_acl), .get_fabric_name = iscsi_get_fabric_name, .get_fabric_proto_ident = iscsi_get_fabric_proto_ident, .tpg_get_wwn = lio_tpg_get_endpoint_wwn, @@ -1967,8 +1945,6 @@ const struct target_core_fabric_ops iscsi_ops = { .tpg_check_prod_mode_write_protect = lio_tpg_check_prod_mode_write_protect, .tpg_check_prot_fabric_only = &lio_tpg_check_prot_fabric_only, - .tpg_alloc_fabric_acl = lio_tpg_alloc_fabric_acl, - .tpg_release_fabric_acl = lio_tpg_release_fabric_acl, .tpg_get_inst_index = lio_tpg_get_inst_index, .check_stop_free = lio_check_stop_free, .release_cmd = lio_release_cmd, diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index 12b85b03e9ae..5a71c9f2ee66 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -698,19 +698,6 @@ static int tcm_loop_check_prot_fabric_only(struct se_portal_group *se_tpg) return tl_tpg->tl_fabric_prot_type; } -static struct se_node_acl *tcm_loop_tpg_alloc_fabric_acl( - struct se_portal_group *se_tpg) -{ - return kzalloc(sizeof(struct se_node_acl), GFP_KERNEL); -} - -static void tcm_loop_tpg_release_fabric_acl( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - kfree(se_nacl); -} - static u32 tcm_loop_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -1383,8 +1370,6 @@ static const struct target_core_fabric_ops loop_ops = { .tpg_check_prod_mode_write_protect = tcm_loop_check_prod_mode_write_protect, .tpg_check_prot_fabric_only = tcm_loop_check_prot_fabric_only, - .tpg_alloc_fabric_acl = tcm_loop_tpg_alloc_fabric_acl, - .tpg_release_fabric_acl = tcm_loop_tpg_release_fabric_acl, .tpg_get_inst_index = tcm_loop_get_inst_index, .check_stop_free = tcm_loop_check_stop_free, .release_cmd = tcm_loop_release_cmd, diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 3a47fe46fbca..5df2a61714fb 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -1707,18 +1707,6 @@ static u16 sbp_get_tag(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static struct se_node_acl *sbp_alloc_fabric_acl(struct se_portal_group *se_tpg) -{ - return kzalloc(sizeof(struct se_node_acl), GFP_KERNEL); -} - -static void sbp_release_fabric_acl( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - kfree(se_nacl); -} - static u32 sbp_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -2465,8 +2453,6 @@ static const struct target_core_fabric_ops sbp_ops = { .tpg_check_demo_mode_cache = sbp_check_true, .tpg_check_demo_mode_write_protect = sbp_check_false, .tpg_check_prod_mode_write_protect = sbp_check_false, - .tpg_alloc_fabric_acl = sbp_alloc_fabric_acl, - .tpg_release_fabric_acl = sbp_release_fabric_acl, .tpg_get_inst_index = sbp_tpg_get_inst_index, .release_cmd = sbp_release_cmd, .shutdown_session = sbp_shutdown_session, diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c index c87ca0c50545..2b10499264d3 100644 --- a/drivers/target/target_core_configfs.c +++ b/drivers/target/target_core_configfs.c @@ -354,14 +354,6 @@ static int target_fabric_tf_ops_check(const struct target_core_fabric_ops *tfo) pr_err("Missing tfo->tpg_check_prod_mode_write_protect()\n"); return -EINVAL; } - if (!tfo->tpg_alloc_fabric_acl) { - pr_err("Missing tfo->tpg_alloc_fabric_acl()\n"); - return -EINVAL; - } - if (!tfo->tpg_release_fabric_acl) { - pr_err("Missing tfo->tpg_release_fabric_acl()\n"); - return -EINVAL; - } if (!tfo->tpg_get_inst_index) { pr_err("Missing tfo->tpg_get_inst_index()\n"); return -EINVAL; diff --git a/drivers/target/target_core_tpg.c b/drivers/target/target_core_tpg.c index 0cd86ff9a792..42f3bd9561c8 100644 --- a/drivers/target/target_core_tpg.c +++ b/drivers/target/target_core_tpg.c @@ -259,7 +259,8 @@ static struct se_node_acl *target_alloc_node_acl(struct se_portal_group *tpg, { struct se_node_acl *acl; - acl = tpg->se_tpg_tfo->tpg_alloc_fabric_acl(tpg); + acl = kzalloc(max(sizeof(*acl), tpg->se_tpg_tfo->node_acl_size), + GFP_KERNEL); if (!acl) return NULL; @@ -290,7 +291,7 @@ static struct se_node_acl *target_alloc_node_acl(struct se_portal_group *tpg, out_free_device_list: core_free_device_list_for_node(acl, tpg); out_free_acl: - tpg->se_tpg_tfo->tpg_release_fabric_acl(tpg, acl); + kfree(acl); return NULL; } @@ -461,7 +462,7 @@ void core_tpg_del_initiator_node_acl(struct se_node_acl *acl) tpg->se_tpg_tfo->tpg_get_tag(tpg), acl->queue_depth, tpg->se_tpg_tfo->get_fabric_name(), acl->initiatorname); - tpg->se_tpg_tfo->tpg_release_fabric_acl(tpg, acl); + kfree(acl); } /* core_tpg_set_initiator_node_queue_depth(): @@ -725,7 +726,7 @@ int core_tpg_deregister(struct se_portal_group *se_tpg) core_tpg_wait_for_nacl_pr_ref(nacl); core_free_device_list_for_node(nacl, se_tpg); - se_tpg->se_tpg_tfo->tpg_release_fabric_acl(se_tpg, nacl); + kfree(nacl); spin_lock_irq(&se_tpg->acl_node_lock); } diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c index 9dc1bd5f0e6b..0fc4f5cb4bea 100644 --- a/drivers/target/target_core_transport.c +++ b/drivers/target/target_core_transport.c @@ -533,7 +533,7 @@ void transport_deregister_session(struct se_session *se_sess) spin_unlock_irqrestore(&se_tpg->acl_node_lock, flags); core_tpg_wait_for_nacl_pr_ref(se_nacl); core_free_device_list_for_node(se_nacl, se_tpg); - se_tfo->tpg_release_fabric_acl(se_tpg, se_nacl); + kfree(se_nacl); comp_nacl = false; spin_lock_irqsave(&se_tpg->acl_node_lock, flags); diff --git a/drivers/target/tcm_fc/tcm_fc.h b/drivers/target/tcm_fc/tcm_fc.h index 881deb3d499a..4ceaeb9a4b93 100644 --- a/drivers/target/tcm_fc/tcm_fc.h +++ b/drivers/target/tcm_fc/tcm_fc.h @@ -80,8 +80,8 @@ struct ft_node_auth { * Node ACL for FC remote port session. */ struct ft_node_acl { - struct ft_node_auth node_auth; struct se_node_acl se_node_acl; + struct ft_node_auth node_auth; }; struct ft_lun { diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index e179fdf76ddb..8da159352315 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -236,29 +236,6 @@ struct ft_node_acl *ft_acl_get(struct ft_tpg *tpg, struct fc_rport_priv *rdata) return found; } -static struct se_node_acl *ft_tpg_alloc_fabric_acl(struct se_portal_group *se_tpg) -{ - struct ft_node_acl *acl; - - acl = kzalloc(sizeof(*acl), GFP_KERNEL); - if (!acl) { - pr_err("Unable to allocate struct ft_node_acl\n"); - return NULL; - } - pr_debug("acl %p\n", acl); - return &acl->se_node_acl; -} - -static void ft_tpg_release_fabric_acl(struct se_portal_group *se_tpg, - struct se_node_acl *se_acl) -{ - struct ft_node_acl *acl = container_of(se_acl, - struct ft_node_acl, se_node_acl); - - pr_debug("acl %p\n", acl); - kfree(acl); -} - /* * local_port port_group (tpg) ops. */ @@ -474,6 +451,7 @@ static u32 ft_tpg_get_inst_index(struct se_portal_group *se_tpg) static const struct target_core_fabric_ops ft_fabric_ops = { .module = THIS_MODULE, .name = "fc", + .node_acl_size = sizeof(struct ft_node_acl), .get_fabric_name = ft_get_fabric_name, .get_fabric_proto_ident = fc_get_fabric_proto_ident, .tpg_get_wwn = ft_get_fabric_wwn, @@ -485,8 +463,6 @@ static const struct target_core_fabric_ops ft_fabric_ops = { .tpg_check_demo_mode_cache = ft_check_false, .tpg_check_demo_mode_write_protect = ft_check_false, .tpg_check_prod_mode_write_protect = ft_check_false, - .tpg_alloc_fabric_acl = ft_tpg_alloc_fabric_acl, - .tpg_release_fabric_acl = ft_tpg_release_fabric_acl, .tpg_get_inst_index = ft_tpg_get_inst_index, .check_stop_free = ft_check_stop_free, .release_cmd = ft_release_cmd, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index fccb0ccb355a..82f4da8bfe41 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1373,18 +1373,6 @@ static char *usbg_parse_pr_out_transport_id( return tid; } -static struct se_node_acl *usbg_alloc_fabric_acl(struct se_portal_group *se_tpg) -{ - return kzalloc(sizeof(struct se_node_acl), GFP_KERNEL); -} - -static void usbg_release_fabric_acl( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - kfree(se_nacl); -} - static u32 usbg_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -1825,8 +1813,6 @@ static const struct target_core_fabric_ops usbg_ops = { .tpg_check_demo_mode_cache = usbg_check_false, .tpg_check_demo_mode_write_protect = usbg_check_false, .tpg_check_prod_mode_write_protect = usbg_check_false, - .tpg_alloc_fabric_acl = usbg_alloc_fabric_acl, - .tpg_release_fabric_acl = usbg_release_fabric_acl, .tpg_get_inst_index = usbg_tpg_get_inst_index, .release_cmd = usbg_release_cmd, .shutdown_session = usbg_shutdown_session, diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 8faa7f4abf23..b93c03935964 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -425,19 +425,6 @@ static int vhost_scsi_check_prot_fabric_only(struct se_portal_group *se_tpg) return tpg->tv_fabric_prot_type; } -static struct se_node_acl * -vhost_scsi_alloc_fabric_acl(struct se_portal_group *se_tpg) -{ - return kzalloc(sizeof(struct se_node_acl), GFP_KERNEL); -} - -static void -vhost_scsi_release_fabric_acl(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - kfree(se_nacl); -} - static u32 vhost_scsi_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -2268,8 +2255,6 @@ static struct target_core_fabric_ops vhost_scsi_ops = { .tpg_check_demo_mode_write_protect = vhost_scsi_check_false, .tpg_check_prod_mode_write_protect = vhost_scsi_check_false, .tpg_check_prot_fabric_only = vhost_scsi_check_prot_fabric_only, - .tpg_alloc_fabric_acl = vhost_scsi_alloc_fabric_acl, - .tpg_release_fabric_acl = vhost_scsi_release_fabric_acl, .tpg_get_inst_index = vhost_scsi_tpg_get_inst_index, .release_cmd = vhost_scsi_release_cmd, .check_stop_free = vhost_scsi_check_stop_free, diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index 8a130ab71733..3756953b385b 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -1449,19 +1449,6 @@ static void scsiback_drop_tport(struct se_wwn *wwn) kfree(tport); } -static struct se_node_acl * -scsiback_alloc_fabric_acl(struct se_portal_group *se_tpg) -{ - return kzalloc(sizeof(struct se_node_acl), GFP_KERNEL); -} - -static void -scsiback_release_fabric_acl(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl) -{ - kfree(se_nacl); -} - static u32 scsiback_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -1952,8 +1939,6 @@ static const struct target_core_fabric_ops scsiback_ops = { .tpg_check_demo_mode_cache = scsiback_check_true, .tpg_check_demo_mode_write_protect = scsiback_check_false, .tpg_check_prod_mode_write_protect = scsiback_check_false, - .tpg_alloc_fabric_acl = scsiback_alloc_fabric_acl, - .tpg_release_fabric_acl = scsiback_release_fabric_acl, .tpg_get_inst_index = scsiback_tpg_get_inst_index, .check_stop_free = scsiback_check_stop_free, .release_cmd = scsiback_release_cmd, diff --git a/include/target/iscsi/iscsi_target_core.h b/include/target/iscsi/iscsi_target_core.h index 39f3d181d39d..f7b16ca67504 100644 --- a/include/target/iscsi/iscsi_target_core.h +++ b/include/target/iscsi/iscsi_target_core.h @@ -745,10 +745,10 @@ struct iscsi_node_stat_grps { }; struct iscsi_node_acl { + struct se_node_acl se_node_acl; struct iscsi_node_attrib node_attrib; struct iscsi_node_auth node_auth; struct iscsi_node_stat_grps node_stat_grps; - struct se_node_acl se_node_acl; }; struct iscsi_tpg_attrib { diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h index 8b570c49f4d1..e5414744bf2d 100644 --- a/include/target/target_core_fabric.h +++ b/include/target/target_core_fabric.h @@ -4,6 +4,7 @@ struct target_core_fabric_ops { struct module *module; const char *name; + size_t node_acl_size; char *(*get_fabric_name)(void); u8 (*get_fabric_proto_ident)(struct se_portal_group *); char *(*tpg_get_wwn)(struct se_portal_group *); @@ -36,10 +37,6 @@ struct target_core_fabric_ops { * WRITE_STRIP and READ_INSERT operations. */ int (*tpg_check_prot_fabric_only)(struct se_portal_group *); - struct se_node_acl *(*tpg_alloc_fabric_acl)( - struct se_portal_group *); - void (*tpg_release_fabric_acl)(struct se_portal_group *, - struct se_node_acl *); u32 (*tpg_get_inst_index)(struct se_portal_group *); /* * Optional to release struct se_cmd and fabric dependent allocated -- cgit v1.2.3 From e4aae5af810eaa61c2cd7ba79d95ebfe0d88fe9b Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 1 May 2015 17:47:56 +0200 Subject: target: change core_tpg_register prototype Remove the unneeded fabric_ptr argument, and change the type argument to pass in a SPC protocol identifier. Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 3 +-- drivers/infiniband/ulp/srpt/ib_srpt.c | 2 +- drivers/scsi/qla2xxx/tcm_qla2xxx.c | 8 +++---- drivers/target/iscsi/iscsi_target_configfs.c | 2 +- drivers/target/iscsi/iscsi_target_tpg.c | 3 +-- drivers/target/loopback/tcm_loop.c | 4 ++-- drivers/target/sbp/sbp_target.c | 3 +-- drivers/target/target_core_tpg.c | 31 ++++++++++++---------------- drivers/target/tcm_fc/tfc_conf.c | 2 +- drivers/usb/gadget/legacy/tcm_usb_gadget.c | 4 ++-- drivers/vhost/scsi.c | 4 ++-- drivers/xen/xen-scsiback.c | 4 ++-- include/target/target_core_base.h | 16 ++++++-------- include/target/target_core_fabric.h | 2 +- 14 files changed, 38 insertions(+), 50 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 07e7ef3d7429..b04846e985d4 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -238,8 +238,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " tpg->" + fabric_mod_port + " = " + fabric_mod_port + ";\n" buf += " tpg->" + fabric_mod_port + "_tpgt = tpgt;\n\n" buf += " ret = core_tpg_register(&" + fabric_mod_name + "_ops, wwn,\n" - buf += " &tpg->se_tpg, tpg,\n" - buf += " TRANSPORT_TPG_TYPE_NORMAL);\n" + buf += " &tpg->se_tpg, SCSI_PROTOCOL_SAS);\n" buf += " if (ret < 0) {\n" buf += " kfree(tpg);\n" buf += " return NULL;\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 38e51f4a17de..8eed6089c5d7 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -3791,7 +3791,7 @@ static struct se_portal_group *srpt_make_tpg(struct se_wwn *wwn, /* Initialize sport->port_wwn and sport->port_tpg_1 */ res = core_tpg_register(&srpt_template, &sport->port_wwn, - &sport->port_tpg_1, sport, TRANSPORT_TPG_TYPE_NORMAL); + &sport->port_tpg_1, SCSI_PROTOCOL_SRP); if (res) return ERR_PTR(res); diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index cb376e5198d0..30cbfa6dc3e6 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -1113,8 +1113,8 @@ static struct se_portal_group *tcm_qla2xxx_make_tpg( tpg->tpg_attrib.cache_dynamic_acls = 1; tpg->tpg_attrib.demo_mode_login_only = 1; - ret = core_tpg_register(&tcm_qla2xxx_ops, wwn, - &tpg->se_tpg, tpg, TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&tcm_qla2xxx_ops, wwn, &tpg->se_tpg, + SCSI_PROTOCOL_FCP); if (ret < 0) { kfree(tpg); return NULL; @@ -1233,8 +1233,8 @@ static struct se_portal_group *tcm_qla2xxx_npiv_make_tpg( tpg->tpg_attrib.cache_dynamic_acls = 1; tpg->tpg_attrib.demo_mode_login_only = 1; - ret = core_tpg_register(&tcm_qla2xxx_npiv_ops, wwn, - &tpg->se_tpg, tpg, TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&tcm_qla2xxx_npiv_ops, wwn, &tpg->se_tpg, + SCSI_PROTOCOL_FCP); if (ret < 0) { kfree(tpg); return NULL; diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index 03b2e15c1b6c..0d5d88817a47 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -1421,7 +1421,7 @@ static struct se_portal_group *lio_target_tiqn_addtpg( return NULL; ret = core_tpg_register(&iscsi_ops, wwn, &tpg->tpg_se_tpg, - tpg, TRANSPORT_TPG_TYPE_NORMAL); + SCSI_PROTOCOL_ISCSI); if (ret < 0) return NULL; diff --git a/drivers/target/iscsi/iscsi_target_tpg.c b/drivers/target/iscsi/iscsi_target_tpg.c index 5e3295fe404d..dcb7ede1d4aa 100644 --- a/drivers/target/iscsi/iscsi_target_tpg.c +++ b/drivers/target/iscsi/iscsi_target_tpg.c @@ -68,8 +68,7 @@ int iscsit_load_discovery_tpg(void) return -1; } - ret = core_tpg_register(&iscsi_ops, NULL, &tpg->tpg_se_tpg, - tpg, TRANSPORT_TPG_TYPE_DISCOVERY); + ret = core_tpg_register(&iscsi_ops, NULL, &tpg->tpg_se_tpg, -1); if (ret < 0) { kfree(tpg); return -1; diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index 9436bdfef091..3f264d436737 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -1204,8 +1204,8 @@ static struct se_portal_group *tcm_loop_make_naa_tpg( /* * Register the tl_tpg as a emulated SAS TCM Target Endpoint */ - ret = core_tpg_register(&loop_ops, wwn, &tl_tpg->tl_se_tpg, tl_tpg, - TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&loop_ops, wwn, &tl_tpg->tl_se_tpg, + tl_hba->tl_proto_id); if (ret < 0) return ERR_PTR(-ENOMEM); diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 5df2a61714fb..40b9f516cf9b 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -2152,8 +2152,7 @@ static struct se_portal_group *sbp_make_tpg( goto out_free_tpg; } - ret = core_tpg_register(&sbp_ops, wwn, &tpg->se_tpg, tpg, - TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&sbp_ops, wwn, &tpg->se_tpg, SCSI_PROTOCOL_SBP); if (ret < 0) goto out_unreg_mgt_agt; diff --git a/drivers/target/target_core_tpg.c b/drivers/target/target_core_tpg.c index 42f3bd9561c8..c0c1f67facb5 100644 --- a/drivers/target/target_core_tpg.c +++ b/drivers/target/target_core_tpg.c @@ -634,8 +634,7 @@ int core_tpg_register( const struct target_core_fabric_ops *tfo, struct se_wwn *se_wwn, struct se_portal_group *se_tpg, - void *tpg_fabric_ptr, - int se_tpg_type) + int proto_id) { struct se_lun *lun; u32 i; @@ -661,8 +660,7 @@ int core_tpg_register( init_completion(&lun->lun_ref_comp); } - se_tpg->se_tpg_type = se_tpg_type; - se_tpg->se_tpg_fabric_ptr = tpg_fabric_ptr; + se_tpg->proto_id = proto_id; se_tpg->se_tpg_tfo = tfo; se_tpg->se_tpg_wwn = se_wwn; atomic_set(&se_tpg->tpg_pr_ref_count, 0); @@ -673,7 +671,7 @@ int core_tpg_register( spin_lock_init(&se_tpg->session_lock); spin_lock_init(&se_tpg->tpg_lun_lock); - if (se_tpg->se_tpg_type == TRANSPORT_TPG_TYPE_NORMAL) { + if (se_tpg->proto_id >= 0) { if (core_tpg_setup_virtual_lun0(se_tpg) < 0) { array_free(se_tpg->tpg_lun_list, TRANSPORT_MAX_LUNS_PER_TPG); @@ -685,11 +683,10 @@ int core_tpg_register( list_add_tail(&se_tpg->se_tpg_node, &tpg_list); spin_unlock_bh(&tpg_lock); - pr_debug("TARGET_CORE[%s]: Allocated %s struct se_portal_group for" - " endpoint: %s, Portal Tag: %u\n", tfo->get_fabric_name(), - (se_tpg->se_tpg_type == TRANSPORT_TPG_TYPE_NORMAL) ? - "Normal" : "Discovery", (tfo->tpg_get_wwn(se_tpg) == NULL) ? - "None" : tfo->tpg_get_wwn(se_tpg), tfo->tpg_get_tag(se_tpg)); + pr_debug("TARGET_CORE[%s]: Allocated portal_group for endpoint: %s, " + "Proto: %d, Portal Tag: %u\n", tfo->get_fabric_name(), + tfo->tpg_get_wwn(se_tpg) ? tfo->tpg_get_wwn(se_tpg) : NULL, + se_tpg->proto_id, tfo->tpg_get_tag(se_tpg)); return 0; } @@ -697,14 +694,13 @@ EXPORT_SYMBOL(core_tpg_register); int core_tpg_deregister(struct se_portal_group *se_tpg) { + const struct target_core_fabric_ops *tfo = se_tpg->se_tpg_tfo; struct se_node_acl *nacl, *nacl_tmp; - pr_debug("TARGET_CORE[%s]: Deallocating %s struct se_portal_group" - " for endpoint: %s Portal Tag %u\n", - (se_tpg->se_tpg_type == TRANSPORT_TPG_TYPE_NORMAL) ? - "Normal" : "Discovery", se_tpg->se_tpg_tfo->get_fabric_name(), - se_tpg->se_tpg_tfo->tpg_get_wwn(se_tpg), - se_tpg->se_tpg_tfo->tpg_get_tag(se_tpg)); + pr_debug("TARGET_CORE[%s]: Deallocating portal_group for endpoint: %s, " + "Proto: %d, Portal Tag: %u\n", tfo->get_fabric_name(), + tfo->tpg_get_wwn(se_tpg) ? tfo->tpg_get_wwn(se_tpg) : NULL, + se_tpg->proto_id, tfo->tpg_get_tag(se_tpg)); spin_lock_bh(&tpg_lock); list_del(&se_tpg->se_tpg_node); @@ -732,10 +728,9 @@ int core_tpg_deregister(struct se_portal_group *se_tpg) } spin_unlock_irq(&se_tpg->acl_node_lock); - if (se_tpg->se_tpg_type == TRANSPORT_TPG_TYPE_NORMAL) + if (se_tpg->proto_id >= 0) core_tpg_remove_lun(se_tpg, &se_tpg->tpg_virt_lun0); - se_tpg->se_tpg_fabric_ptr = NULL; array_free(se_tpg->tpg_lun_list, TRANSPORT_MAX_LUNS_PER_TPG); return 0; } diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index 4bdf7a25ae67..8309c3d91387 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -284,7 +284,7 @@ static struct se_portal_group *ft_add_tpg( } ret = core_tpg_register(&ft_fabric_ops, wwn, &tpg->se_tpg, - tpg, TRANSPORT_TPG_TYPE_NORMAL); + SCSI_PROTOCOL_FCP); if (ret < 0) { destroy_workqueue(wq); kfree(tpg); diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index 82f4da8bfe41..08b4f48aa49e 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1508,8 +1508,8 @@ static struct se_portal_group *usbg_make_tpg( tpg->tport = tport; tpg->tport_tpgt = tpgt; - ret = core_tpg_register(&usbg_ops, wwn, &tpg->se_tpg, tpg, - TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&usbg_ops, wwn, &tpg->se_tpg, + tport->tport_proto_id); if (ret < 0) { destroy_workqueue(tpg->workqueue); kfree(tpg); diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index b93c03935964..8295e7be0fcb 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -2119,8 +2119,8 @@ vhost_scsi_make_tpg(struct se_wwn *wwn, tpg->tport = tport; tpg->tport_tpgt = tpgt; - ret = core_tpg_register(&vhost_scsi_ops, wwn, - &tpg->se_tpg, tpg, TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&vhost_scsi_ops, wwn, &tpg->se_tpg, + tport->tport_proto_id); if (ret < 0) { kfree(tpg); return NULL; diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index 3756953b385b..223d493878eb 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -1883,8 +1883,8 @@ scsiback_make_tpg(struct se_wwn *wwn, tpg->tport = tport; tpg->tport_tpgt = tpgt; - ret = core_tpg_register(&scsiback_ops, wwn, - &tpg->se_tpg, tpg, TRANSPORT_TPG_TYPE_NORMAL); + ret = core_tpg_register(&scsiback_ops, wwn, &tpg->se_tpg, + tport->tport_proto_id); if (ret < 0) { kfree(tpg); return NULL; diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h index 9f8f5a1b527d..c462fb0a47f4 100644 --- a/include/target/target_core_base.h +++ b/include/target/target_core_base.h @@ -125,12 +125,6 @@ enum transport_lun_status_table { TRANSPORT_LUN_STATUS_ACTIVE = 1, }; -/* struct se_portal_group->se_tpg_type */ -enum transport_tpg_type_table { - TRANSPORT_TPG_TYPE_NORMAL = 0, - TRANSPORT_TPG_TYPE_DISCOVERY = 1, -}; - /* Special transport agnostic struct se_cmd->t_states */ enum transport_state_table { TRANSPORT_NO_STATE = 0, @@ -864,8 +858,12 @@ struct se_tpg_np { }; struct se_portal_group { - /* Type of target portal group, see transport_tpg_type_table */ - enum transport_tpg_type_table se_tpg_type; + /* + * PROTOCOL IDENTIFIER value per SPC4, 7.5.1. + * + * Negative values can be used by fabric drivers for internal use TPGs. + */ + int proto_id; /* Number of ACLed Initiator Nodes for this TPG */ u32 num_node_acls; /* Used for PR SPEC_I_PT=1 and REGISTER_AND_MOVE */ @@ -875,8 +873,6 @@ struct se_portal_group { /* Spinlock for adding/removing sessions */ spinlock_t session_lock; spinlock_t tpg_lun_lock; - /* Pointer to $FABRIC_MOD portal group */ - void *se_tpg_fabric_ptr; struct list_head se_tpg_node; /* linked list for initiator ACL list */ struct list_head acl_node_list; diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h index e5414744bf2d..e0adc141de07 100644 --- a/include/target/target_core_fabric.h +++ b/include/target/target_core_fabric.h @@ -175,7 +175,7 @@ int core_tpg_set_initiator_node_queue_depth(struct se_portal_group *, int core_tpg_set_initiator_node_tag(struct se_portal_group *, struct se_node_acl *, const char *); int core_tpg_register(const struct target_core_fabric_ops *, - struct se_wwn *, struct se_portal_group *, void *, int); + struct se_wwn *, struct se_portal_group *, int); int core_tpg_deregister(struct se_portal_group *); /* SAS helpers */ -- cgit v1.2.3 From 2aeeafae6bb9f04dbe17b521bcd8f0d03516c393 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 1 May 2015 17:47:57 +0200 Subject: target: remove the get_fabric_proto_ident method Now that we store the protocol identifier in the tpg structure we don't need this method. Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 31 ---------------------------- drivers/infiniband/ulp/srpt/ib_srpt.c | 6 ------ drivers/scsi/qla2xxx/tcm_qla2xxx.c | 19 ----------------- drivers/target/iscsi/iscsi_target_configfs.c | 1 - drivers/target/loopback/tcm_loop.c | 27 ------------------------ drivers/target/sbp/sbp_target.c | 13 ------------ drivers/target/target_core_configfs.c | 4 ---- drivers/target/target_core_fabric_lib.c | 27 ------------------------ drivers/target/target_core_pr.c | 12 +++++------ drivers/target/target_core_spc.c | 12 ++++------- drivers/target/tcm_fc/tfc_conf.c | 1 - drivers/usb/gadget/legacy/tcm_usb_gadget.c | 18 ---------------- drivers/vhost/scsi.c | 23 --------------------- drivers/xen/xen-scsiback.c | 23 --------------------- include/target/target_core_fabric.h | 4 ---- 15 files changed, 9 insertions(+), 212 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index b04846e985d4..29176c29537c 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -300,9 +300,7 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "static const struct target_core_fabric_ops " + fabric_mod_name + "_ops = {\n" buf += " .module = THIS_MODULE,\n" buf += " .name = " + fabric_mod_name + ",\n" - buf += " .get_fabric_proto_ident = " + fabric_mod_name + "_get_fabric_proto_ident,\n" buf += " .get_fabric_name = " + fabric_mod_name + "_get_fabric_name,\n" - buf += " .get_fabric_proto_ident = " + fabric_mod_name + "_get_fabric_proto_ident,\n" buf += " .tpg_get_wwn = " + fabric_mod_name + "_get_fabric_wwn,\n" buf += " .tpg_get_tag = " + fabric_mod_name + "_get_tag,\n" buf += " .tpg_get_pr_transport_id = " + fabric_mod_name + "_get_pr_transport_id,\n" @@ -461,35 +459,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): bufi += "char *" + fabric_mod_name + "_get_fabric_name(void);\n" continue - if re.search('get_fabric_proto_ident', fo): - buf += "u8 " + fabric_mod_name + "_get_fabric_proto_ident(struct se_portal_group *se_tpg)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_tpg *tpg = container_of(se_tpg,\n" - buf += " struct " + fabric_mod_name + "_tpg, se_tpg);\n" - buf += " struct " + fabric_mod_name + "_" + fabric_mod_port + " *" + fabric_mod_port + " = tpg->" + fabric_mod_port + ";\n" - buf += " u8 proto_id;\n\n" - buf += " switch (" + fabric_mod_port + "->" + fabric_mod_port + "_proto_id) {\n" - if proto_ident == "FC": - buf += " case SCSI_PROTOCOL_FCP:\n" - buf += " default:\n" - buf += " proto_id = fc_get_fabric_proto_ident(se_tpg);\n" - buf += " break;\n" - elif proto_ident == "SAS": - buf += " case SCSI_PROTOCOL_SAS:\n" - buf += " default:\n" - buf += " proto_id = sas_get_fabric_proto_ident(se_tpg);\n" - buf += " break;\n" - elif proto_ident == "iSCSI": - buf += " case SCSI_PROTOCOL_ISCSI:\n" - buf += " default:\n" - buf += " proto_id = iscsi_get_fabric_proto_ident(se_tpg);\n" - buf += " break;\n" - - buf += " }\n\n" - buf += " return proto_id;\n" - buf += "}\n\n" - bufi += "u8 " + fabric_mod_name + "_get_fabric_proto_ident(struct se_portal_group *);\n" - if re.search('get_wwn', fo): buf += "char *" + fabric_mod_name + "_get_fabric_wwn(struct se_portal_group *se_tpg)\n" buf += "{\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 8eed6089c5d7..9213c2de28fc 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -3394,11 +3394,6 @@ static char *srpt_get_fabric_name(void) return "srpt"; } -static u8 srpt_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - return SCSI_TRANSPORTID_PROTOCOLID_SRP; -} - static char *srpt_get_fabric_wwn(struct se_portal_group *tpg) { struct srpt_port *sport = container_of(tpg, struct srpt_port, port_tpg_1); @@ -3863,7 +3858,6 @@ static const struct target_core_fabric_ops srpt_template = { .name = "srpt", .node_acl_size = sizeof(struct srpt_node_acl), .get_fabric_name = srpt_get_fabric_name, - .get_fabric_proto_ident = srpt_get_fabric_proto_ident, .tpg_get_wwn = srpt_get_fabric_wwn, .tpg_get_tag = srpt_get_tag, .tpg_get_pr_transport_id = srpt_get_pr_transport_id, diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index 30cbfa6dc3e6..4566c4649751 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -190,23 +190,6 @@ static char *tcm_qla2xxx_npiv_get_fabric_name(void) return "qla2xxx_npiv"; } -static u8 tcm_qla2xxx_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, - struct tcm_qla2xxx_tpg, se_tpg); - struct tcm_qla2xxx_lport *lport = tpg->lport; - u8 proto_id; - - switch (lport->lport_proto_id) { - case SCSI_PROTOCOL_FCP: - default: - proto_id = fc_get_fabric_proto_ident(se_tpg); - break; - } - - return proto_id; -} - static char *tcm_qla2xxx_get_fabric_wwn(struct se_portal_group *se_tpg) { struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, @@ -1928,7 +1911,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { .name = "qla2xxx", .node_acl_size = sizeof(struct tcm_qla2xxx_nacl), .get_fabric_name = tcm_qla2xxx_get_fabric_name, - .get_fabric_proto_ident = tcm_qla2xxx_get_fabric_proto_ident, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, .tpg_get_tag = tcm_qla2xxx_get_tag, .tpg_get_pr_transport_id = tcm_qla2xxx_get_pr_transport_id, @@ -1979,7 +1961,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .name = "qla2xxx_npiv", .node_acl_size = sizeof(struct tcm_qla2xxx_nacl), .get_fabric_name = tcm_qla2xxx_npiv_get_fabric_name, - .get_fabric_proto_ident = tcm_qla2xxx_get_fabric_proto_ident, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, .tpg_get_tag = tcm_qla2xxx_get_tag, .tpg_get_pr_transport_id = tcm_qla2xxx_get_pr_transport_id, diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index 0d5d88817a47..9dec9f39139f 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -1918,7 +1918,6 @@ const struct target_core_fabric_ops iscsi_ops = { .name = "iscsi", .node_acl_size = sizeof(struct iscsi_node_acl), .get_fabric_name = iscsi_get_fabric_name, - .get_fabric_proto_ident = iscsi_get_fabric_proto_ident, .tpg_get_wwn = lio_tpg_get_endpoint_wwn, .tpg_get_tag = lio_tpg_get_tag, .tpg_get_default_depth = lio_tpg_get_default_depth, diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index 3f264d436737..0eed0209a7f4 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -525,32 +525,6 @@ static inline struct tcm_loop_tpg *tl_tpg(struct se_portal_group *se_tpg) return container_of(se_tpg, struct tcm_loop_tpg, tl_se_tpg); } -static u8 tcm_loop_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - struct tcm_loop_hba *tl_hba = tl_tpg(se_tpg)->tl_hba; - /* - * tl_proto_id is set at tcm_loop_configfs.c:tcm_loop_make_scsi_hba() - * time based on the protocol dependent prefix of the passed configfs group. - * - * Based upon tl_proto_id, TCM_Loop emulates the requested fabric - * ProtocolID using target_core_fabric_lib.c symbols. - */ - switch (tl_hba->tl_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_fabric_proto_ident(se_tpg); - case SCSI_PROTOCOL_FCP: - return fc_get_fabric_proto_ident(se_tpg); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_fabric_proto_ident(se_tpg); - default: - pr_err("Unknown tl_proto_id: 0x%02x, using" - " SAS emulation\n", tl_hba->tl_proto_id); - break; - } - - return sas_get_fabric_proto_ident(se_tpg); -} - static char *tcm_loop_get_endpoint_wwn(struct se_portal_group *se_tpg) { /* @@ -1356,7 +1330,6 @@ static const struct target_core_fabric_ops loop_ops = { .module = THIS_MODULE, .name = "loopback", .get_fabric_name = tcm_loop_get_fabric_name, - .get_fabric_proto_ident = tcm_loop_get_fabric_proto_ident, .tpg_get_wwn = tcm_loop_get_endpoint_wwn, .tpg_get_tag = tcm_loop_get_tag, .tpg_get_pr_transport_id = tcm_loop_get_pr_transport_id, diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 40b9f516cf9b..8acb37fd9ebc 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -1832,18 +1832,6 @@ static int sbp_check_stop_free(struct se_cmd *se_cmd) return 1; } -/* - * Handlers for Serial Bus Protocol 2/3 (SBP-2 / SBP-3) - */ -static u8 sbp_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - /* - * Return a IEEE 1394 SCSI Protocol identifier for loopback operations - * This is defined in section 7.5.1 Table 362 in spc4r17 - */ - return SCSI_PROTOCOL_SBP; -} - static u32 sbp_get_pr_transport_id( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -2442,7 +2430,6 @@ static const struct target_core_fabric_ops sbp_ops = { .module = THIS_MODULE, .name = "sbp", .get_fabric_name = sbp_get_fabric_name, - .get_fabric_proto_ident = sbp_get_fabric_proto_ident, .tpg_get_wwn = sbp_get_fabric_wwn, .tpg_get_tag = sbp_get_tag, .tpg_get_pr_transport_id = sbp_get_pr_transport_id, diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c index 2b10499264d3..21c9f7d79d5e 100644 --- a/drivers/target/target_core_configfs.c +++ b/drivers/target/target_core_configfs.c @@ -318,10 +318,6 @@ static int target_fabric_tf_ops_check(const struct target_core_fabric_ops *tfo) pr_err("Missing tfo->get_fabric_name()\n"); return -EINVAL; } - if (!tfo->get_fabric_proto_ident) { - pr_err("Missing tfo->get_fabric_proto_ident()\n"); - return -EINVAL; - } if (!tfo->tpg_get_wwn) { pr_err("Missing tfo->tpg_get_wwn()\n"); return -EINVAL; diff --git a/drivers/target/target_core_fabric_lib.c b/drivers/target/target_core_fabric_lib.c index 35bfe77160d8..6fed14adbe61 100644 --- a/drivers/target/target_core_fabric_lib.c +++ b/drivers/target/target_core_fabric_lib.c @@ -42,16 +42,6 @@ /* * Handlers for Serial Attached SCSI (SAS) */ -u8 sas_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - /* - * Return a SAS Serial SCSI Protocol identifier for loopback operations - * This is defined in section 7.5.1 Table 362 in spc4r17 - */ - return 0x6; -} -EXPORT_SYMBOL(sas_get_fabric_proto_ident); - u32 sas_get_pr_transport_id( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -128,12 +118,6 @@ EXPORT_SYMBOL(sas_parse_pr_out_transport_id); /* * Handlers for Fibre Channel Protocol (FCP) */ -u8 fc_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - return 0x0; /* 0 = fcp-2 per SPC4 section 7.5.1 */ -} -EXPORT_SYMBOL(fc_get_fabric_proto_ident); - u32 fc_get_pr_transport_id_len( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, @@ -208,17 +192,6 @@ EXPORT_SYMBOL(fc_parse_pr_out_transport_id); /* * Handlers for Internet Small Computer Systems Interface (iSCSI) */ - -u8 iscsi_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - /* - * This value is defined for "Internet SCSI (iSCSI)" - * in spc4r17 section 7.5.1 Table 362 - */ - return 0x5; -} -EXPORT_SYMBOL(iscsi_get_fabric_proto_ident); - u32 iscsi_get_pr_transport_id( struct se_portal_group *se_tpg, struct se_node_acl *se_nacl, diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c index a15411c79ae9..23c065f83a56 100644 --- a/drivers/target/target_core_pr.c +++ b/drivers/target/target_core_pr.c @@ -1447,7 +1447,7 @@ core_scsi3_decode_spec_i_port( struct pr_transport_id_holder *tidh_new, *tidh, *tidh_tmp; const struct target_core_fabric_ops *tmp_tf_ops; unsigned char *buf; - unsigned char *ptr, *i_str = NULL, proto_ident, tmp_proto_ident; + unsigned char *ptr, *i_str = NULL, proto_ident; char *iport_ptr = NULL, i_buf[PR_REG_ISID_ID_LEN]; sense_reason_t ret; u32 tpdl, tid_len = 0; @@ -1536,15 +1536,13 @@ core_scsi3_decode_spec_i_port( tmp_tf_ops = tmp_tpg->se_tpg_tfo; if (!tmp_tf_ops) continue; - if (!tmp_tf_ops->get_fabric_proto_ident || - !tmp_tf_ops->tpg_parse_pr_out_transport_id) + if (!tmp_tf_ops->tpg_parse_pr_out_transport_id) continue; /* * Look for the matching proto_ident provided by * the received TransportID */ - tmp_proto_ident = tmp_tf_ops->get_fabric_proto_ident(tmp_tpg); - if (tmp_proto_ident != proto_ident) + if (tmp_tpg->proto_id != proto_ident) continue; dest_rtpi = tmp_port->sep_rtpi; @@ -3230,11 +3228,11 @@ core_scsi3_emulate_pro_register_and_move(struct se_cmd *cmd, u64 res_key, pr_debug("SPC-3 PR REGISTER_AND_MOVE: Extracted Protocol Identifier:" " 0x%02x\n", proto_ident); - if (proto_ident != dest_tf_ops->get_fabric_proto_ident(dest_se_tpg)) { + if (proto_ident != dest_se_tpg->proto_id) { pr_err("SPC-3 PR REGISTER_AND_MOVE: Received" " proto_ident: 0x%02x does not match ident: 0x%02x" " from fabric: %s\n", proto_ident, - dest_tf_ops->get_fabric_proto_ident(dest_se_tpg), + dest_se_tpg->proto_id, dest_tf_ops->get_fabric_name()); ret = TCM_INVALID_PARAMETER_LIST; goto out; diff --git a/drivers/target/target_core_spc.c b/drivers/target/target_core_spc.c index 988c158cf65d..78c0b40fa5c0 100644 --- a/drivers/target/target_core_spc.c +++ b/drivers/target/target_core_spc.c @@ -286,8 +286,7 @@ check_t10_vend_desc: * Get the PROTOCOL IDENTIFIER as defined by spc4r17 * section 7.5.1 Table 362 */ - buf[off] = - (tpg->se_tpg_tfo->get_fabric_proto_ident(tpg) << 4); + buf[off] = tpg->proto_id << 4; buf[off++] |= 0x1; /* CODE SET == Binary */ buf[off] = 0x80; /* Set PIV=1 */ /* Set ASSOCIATION == target port: 01b */ @@ -322,8 +321,7 @@ check_t10_vend_desc: tg_pt_gp_id = tg_pt_gp->tg_pt_gp_id; spin_unlock(&tg_pt_gp_mem->tg_pt_gp_mem_lock); - buf[off] = - (tpg->se_tpg_tfo->get_fabric_proto_ident(tpg) << 4); + buf[off] = tpg->proto_id << 4; buf[off++] |= 0x1; /* CODE SET == Binary */ buf[off] = 0x80; /* Set PIV=1 */ /* Set ASSOCIATION == target port: 01b */ @@ -371,8 +369,7 @@ check_lu_gp: * section 7.5.1 Table 362 */ check_scsi_name: - buf[off] = - (tpg->se_tpg_tfo->get_fabric_proto_ident(tpg) << 4); + buf[off] = tpg->proto_id << 4; buf[off++] |= 0x3; /* CODE SET == UTF-8 */ buf[off] = 0x80; /* Set PIV=1 */ /* Set ASSOCIATION == target port: 01b */ @@ -412,8 +409,7 @@ check_scsi_name: /* * Target device designator */ - buf[off] = - (tpg->se_tpg_tfo->get_fabric_proto_ident(tpg) << 4); + buf[off] = tpg->proto_id << 4; buf[off++] |= 0x3; /* CODE SET == UTF-8 */ buf[off] = 0x80; /* Set PIV=1 */ /* Set ASSOCIATION == target device: 10b */ diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index 8309c3d91387..fabc7bacf693 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -452,7 +452,6 @@ static const struct target_core_fabric_ops ft_fabric_ops = { .name = "fc", .node_acl_size = sizeof(struct ft_node_acl), .get_fabric_name = ft_get_fabric_name, - .get_fabric_proto_ident = fc_get_fabric_proto_ident, .tpg_get_wwn = ft_get_fabric_wwn, .tpg_get_tag = ft_get_tag, .tpg_get_pr_transport_id = fc_get_pr_transport_id, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index 08b4f48aa49e..d6b03178262f 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1274,23 +1274,6 @@ static char *usbg_get_fabric_name(void) return "usb_gadget"; } -static u8 usbg_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - struct usbg_tpg *tpg = container_of(se_tpg, - struct usbg_tpg, se_tpg); - struct usbg_tport *tport = tpg->tport; - u8 proto_id; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - default: - proto_id = sas_get_fabric_proto_ident(se_tpg); - break; - } - - return proto_id; -} - static char *usbg_get_fabric_wwn(struct se_portal_group *se_tpg) { struct usbg_tpg *tpg = container_of(se_tpg, @@ -1803,7 +1786,6 @@ static const struct target_core_fabric_ops usbg_ops = { .module = THIS_MODULE, .name = "usb_gadget", .get_fabric_name = usbg_get_fabric_name, - .get_fabric_proto_ident = usbg_get_fabric_proto_ident, .tpg_get_wwn = usbg_get_fabric_wwn, .tpg_get_tag = usbg_get_tag, .tpg_get_pr_transport_id = usbg_get_pr_transport_id, diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 8295e7be0fcb..022860ccd008 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -288,28 +288,6 @@ static char *vhost_scsi_get_fabric_name(void) return "vhost"; } -static u8 vhost_scsi_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - struct vhost_scsi_tpg *tpg = container_of(se_tpg, - struct vhost_scsi_tpg, se_tpg); - struct vhost_scsi_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_fabric_proto_ident(se_tpg); - case SCSI_PROTOCOL_FCP: - return fc_get_fabric_proto_ident(se_tpg); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_fabric_proto_ident(se_tpg); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using" - " SAS emulation\n", tport->tport_proto_id); - break; - } - - return sas_get_fabric_proto_ident(se_tpg); -} - static char *vhost_scsi_get_fabric_wwn(struct se_portal_group *se_tpg) { struct vhost_scsi_tpg *tpg = container_of(se_tpg, @@ -2244,7 +2222,6 @@ static struct target_core_fabric_ops vhost_scsi_ops = { .module = THIS_MODULE, .name = "vhost", .get_fabric_name = vhost_scsi_get_fabric_name, - .get_fabric_proto_ident = vhost_scsi_get_fabric_proto_ident, .tpg_get_wwn = vhost_scsi_get_fabric_wwn, .tpg_get_tag = vhost_scsi_get_tpgt, .tpg_get_pr_transport_id = vhost_scsi_get_pr_transport_id, diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index 223d493878eb..8bf9448bd7fd 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -1254,28 +1254,6 @@ static char *scsiback_dump_proto_id(struct scsiback_tport *tport) return "Unknown"; } -static u8 scsiback_get_fabric_proto_ident(struct se_portal_group *se_tpg) -{ - struct scsiback_tpg *tpg = container_of(se_tpg, - struct scsiback_tpg, se_tpg); - struct scsiback_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_fabric_proto_ident(se_tpg); - case SCSI_PROTOCOL_FCP: - return fc_get_fabric_proto_ident(se_tpg); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_fabric_proto_ident(se_tpg); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using SAS emulation\n", - tport->tport_proto_id); - break; - } - - return sas_get_fabric_proto_ident(se_tpg); -} - static char *scsiback_get_fabric_wwn(struct se_portal_group *se_tpg) { struct scsiback_tpg *tpg = container_of(se_tpg, @@ -1929,7 +1907,6 @@ static const struct target_core_fabric_ops scsiback_ops = { .module = THIS_MODULE, .name = "xen-pvscsi", .get_fabric_name = scsiback_get_fabric_name, - .get_fabric_proto_ident = scsiback_get_fabric_proto_ident, .tpg_get_wwn = scsiback_get_fabric_wwn, .tpg_get_tag = scsiback_get_tag, .tpg_get_pr_transport_id = scsiback_get_pr_transport_id, diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h index e0adc141de07..495606382546 100644 --- a/include/target/target_core_fabric.h +++ b/include/target/target_core_fabric.h @@ -6,7 +6,6 @@ struct target_core_fabric_ops { const char *name; size_t node_acl_size; char *(*get_fabric_name)(void); - u8 (*get_fabric_proto_ident)(struct se_portal_group *); char *(*tpg_get_wwn)(struct se_portal_group *); u16 (*tpg_get_tag)(struct se_portal_group *); u32 (*tpg_get_default_depth)(struct se_portal_group *); @@ -179,7 +178,6 @@ int core_tpg_register(const struct target_core_fabric_ops *, int core_tpg_deregister(struct se_portal_group *); /* SAS helpers */ -u8 sas_get_fabric_proto_ident(struct se_portal_group *); u32 sas_get_pr_transport_id(struct se_portal_group *, struct se_node_acl *, struct t10_pr_registration *, int *, unsigned char *); u32 sas_get_pr_transport_id_len(struct se_portal_group *, struct se_node_acl *, @@ -188,7 +186,6 @@ char *sas_parse_pr_out_transport_id(struct se_portal_group *, const char *, u32 *, char **); /* FC helpers */ -u8 fc_get_fabric_proto_ident(struct se_portal_group *); u32 fc_get_pr_transport_id(struct se_portal_group *, struct se_node_acl *, struct t10_pr_registration *, int *, unsigned char *); u32 fc_get_pr_transport_id_len(struct se_portal_group *, struct se_node_acl *, @@ -197,7 +194,6 @@ char *fc_parse_pr_out_transport_id(struct se_portal_group *, const char *, u32 *, char **); /* iSCSI helpers */ -u8 iscsi_get_fabric_proto_ident(struct se_portal_group *); u32 iscsi_get_pr_transport_id(struct se_portal_group *, struct se_node_acl *, struct t10_pr_registration *, int *, unsigned char *); u32 iscsi_get_pr_transport_id_len(struct se_portal_group *, struct se_node_acl *, -- cgit v1.2.3 From 2650d71e244fb3637b5f58a0080682a8bf9c7091 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 1 May 2015 17:47:58 +0200 Subject: target: move transport ID handling to the core Now that struct se_portal_group contains a protocol identifier field we can take all the code to format an parse protocol identifiers in CDBs into common code instead of leaving this to low-level drivers. Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 121 ------------ drivers/infiniband/ulp/srpt/ib_srpt.c | 39 ---- drivers/infiniband/ulp/srpt/ib_srpt.h | 18 -- drivers/scsi/qla2xxx/tcm_qla2xxx.c | 73 -------- drivers/scsi/qla2xxx/tcm_qla2xxx.h | 2 - drivers/target/iscsi/iscsi_target_configfs.c | 3 - drivers/target/loopback/tcm_loop.c | 92 ---------- drivers/target/sbp/sbp_target.c | 70 ------- drivers/target/target_core_configfs.c | 8 - drivers/target/target_core_fabric_lib.c | 263 ++++++++++++++------------- drivers/target/target_core_internal.h | 9 + drivers/target/target_core_pr.c | 49 +++-- drivers/target/tcm_fc/tfc_conf.c | 3 - drivers/usb/gadget/legacy/tcm_usb_gadget.c | 75 +------- drivers/usb/gadget/legacy/tcm_usb_gadget.h | 2 - drivers/vhost/scsi.c | 94 ---------- drivers/xen/xen-scsiback.c | 94 ---------- include/target/target_core_fabric.h | 33 ---- 18 files changed, 173 insertions(+), 875 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 29176c29537c..0dbd70cccde1 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -60,8 +60,6 @@ def tcm_mod_build_FC_include(fabric_mod_dir_var, fabric_mod_name): buf += "};\n" buf += "\n" buf += "struct " + fabric_mod_name + "_lport {\n" - buf += " /* SCSI protocol the lport is providing */\n" - buf += " u8 lport_proto_id;\n" buf += " /* Binary World Wide unique Port Name for FC Target Lport */\n" buf += " u64 lport_wwpn;\n" buf += " /* ASCII formatted WWPN for FC Target Lport */\n" @@ -105,8 +103,6 @@ def tcm_mod_build_SAS_include(fabric_mod_dir_var, fabric_mod_name): buf += " struct se_portal_group se_tpg;\n" buf += "};\n\n" buf += "struct " + fabric_mod_name + "_tport {\n" - buf += " /* SCSI protocol the tport is providing */\n" - buf += " u8 tport_proto_id;\n" buf += " /* Binary World Wide unique Port Name for SAS Target port */\n" buf += " u64 tport_wwpn;\n" buf += " /* ASCII formatted WWPN for SAS Target port */\n" @@ -150,8 +146,6 @@ def tcm_mod_build_iSCSI_include(fabric_mod_dir_var, fabric_mod_name): buf += " struct se_portal_group se_tpg;\n" buf += "};\n\n" buf += "struct " + fabric_mod_name + "_tport {\n" - buf += " /* SCSI protocol the tport is providing */\n" - buf += " u8 tport_proto_id;\n" buf += " /* ASCII formatted TargetName for IQN */\n" buf += " char tport_name[" + fabric_mod_name.upper() + "_NAMELEN];\n" buf += " /* Returned by " + fabric_mod_name + "_make_tport() */\n" @@ -303,9 +297,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .get_fabric_name = " + fabric_mod_name + "_get_fabric_name,\n" buf += " .tpg_get_wwn = " + fabric_mod_name + "_get_fabric_wwn,\n" buf += " .tpg_get_tag = " + fabric_mod_name + "_get_tag,\n" - buf += " .tpg_get_pr_transport_id = " + fabric_mod_name + "_get_pr_transport_id,\n" - buf += " .tpg_get_pr_transport_id_len = " + fabric_mod_name + "_get_pr_transport_id_len,\n" - buf += " .tpg_parse_pr_out_transport_id = " + fabric_mod_name + "_parse_pr_out_transport_id,\n" buf += " .tpg_check_demo_mode = " + fabric_mod_name + "_check_false,\n" buf += " .tpg_check_demo_mode_cache = " + fabric_mod_name + "_check_true,\n" buf += " .tpg_check_demo_mode_write_protect = " + fabric_mod_name + "_check_true,\n" @@ -478,118 +469,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "}\n\n" bufi += "u16 " + fabric_mod_name + "_get_tag(struct se_portal_group *);\n" - if re.search('get_pr_transport_id\)\(', fo): - buf += "u32 " + fabric_mod_name + "_get_pr_transport_id(\n" - buf += " struct se_portal_group *se_tpg,\n" - buf += " struct se_node_acl *se_nacl,\n" - buf += " struct t10_pr_registration *pr_reg,\n" - buf += " int *format_code,\n" - buf += " unsigned char *buf)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_tpg *tpg = container_of(se_tpg,\n" - buf += " struct " + fabric_mod_name + "_tpg, se_tpg);\n" - buf += " struct " + fabric_mod_name + "_" + fabric_mod_port + " *" + fabric_mod_port + " = tpg->" + fabric_mod_port + ";\n" - buf += " int ret = 0;\n\n" - buf += " switch (" + fabric_mod_port + "->" + fabric_mod_port + "_proto_id) {\n" - if proto_ident == "FC": - buf += " case SCSI_PROTOCOL_FCP:\n" - buf += " default:\n" - buf += " ret = fc_get_pr_transport_id(se_tpg, se_nacl, pr_reg,\n" - buf += " format_code, buf);\n" - buf += " break;\n" - elif proto_ident == "SAS": - buf += " case SCSI_PROTOCOL_SAS:\n" - buf += " default:\n" - buf += " ret = sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg,\n" - buf += " format_code, buf);\n" - buf += " break;\n" - elif proto_ident == "iSCSI": - buf += " case SCSI_PROTOCOL_ISCSI:\n" - buf += " default:\n" - buf += " ret = iscsi_get_pr_transport_id(se_tpg, se_nacl, pr_reg,\n" - buf += " format_code, buf);\n" - buf += " break;\n" - - buf += " }\n\n" - buf += " return ret;\n" - buf += "}\n\n" - bufi += "u32 " + fabric_mod_name + "_get_pr_transport_id(struct se_portal_group *,\n" - bufi += " struct se_node_acl *, struct t10_pr_registration *,\n" - bufi += " int *, unsigned char *);\n" - - if re.search('get_pr_transport_id_len\)\(', fo): - buf += "u32 " + fabric_mod_name + "_get_pr_transport_id_len(\n" - buf += " struct se_portal_group *se_tpg,\n" - buf += " struct se_node_acl *se_nacl,\n" - buf += " struct t10_pr_registration *pr_reg,\n" - buf += " int *format_code)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_tpg *tpg = container_of(se_tpg,\n" - buf += " struct " + fabric_mod_name + "_tpg, se_tpg);\n" - buf += " struct " + fabric_mod_name + "_" + fabric_mod_port + " *" + fabric_mod_port + " = tpg->" + fabric_mod_port + ";\n" - buf += " int ret = 0;\n\n" - buf += " switch (" + fabric_mod_port + "->" + fabric_mod_port + "_proto_id) {\n" - if proto_ident == "FC": - buf += " case SCSI_PROTOCOL_FCP:\n" - buf += " default:\n" - buf += " ret = fc_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg,\n" - buf += " format_code);\n" - buf += " break;\n" - elif proto_ident == "SAS": - buf += " case SCSI_PROTOCOL_SAS:\n" - buf += " default:\n" - buf += " ret = sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg,\n" - buf += " format_code);\n" - buf += " break;\n" - elif proto_ident == "iSCSI": - buf += " case SCSI_PROTOCOL_ISCSI:\n" - buf += " default:\n" - buf += " ret = iscsi_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg,\n" - buf += " format_code);\n" - buf += " break;\n" - - - buf += " }\n\n" - buf += " return ret;\n" - buf += "}\n\n" - bufi += "u32 " + fabric_mod_name + "_get_pr_transport_id_len(struct se_portal_group *,\n" - bufi += " struct se_node_acl *, struct t10_pr_registration *,\n" - bufi += " int *);\n" - - if re.search('parse_pr_out_transport_id\)\(', fo): - buf += "char *" + fabric_mod_name + "_parse_pr_out_transport_id(\n" - buf += " struct se_portal_group *se_tpg,\n" - buf += " const char *buf,\n" - buf += " u32 *out_tid_len,\n" - buf += " char **port_nexus_ptr)\n" - buf += "{\n" - buf += " struct " + fabric_mod_name + "_tpg *tpg = container_of(se_tpg,\n" - buf += " struct " + fabric_mod_name + "_tpg, se_tpg);\n" - buf += " struct " + fabric_mod_name + "_" + fabric_mod_port + " *" + fabric_mod_port + " = tpg->" + fabric_mod_port + ";\n" - buf += " char *tid = NULL;\n\n" - buf += " switch (" + fabric_mod_port + "->" + fabric_mod_port + "_proto_id) {\n" - if proto_ident == "FC": - buf += " case SCSI_PROTOCOL_FCP:\n" - buf += " default:\n" - buf += " tid = fc_parse_pr_out_transport_id(se_tpg, buf, out_tid_len,\n" - buf += " port_nexus_ptr);\n" - elif proto_ident == "SAS": - buf += " case SCSI_PROTOCOL_SAS:\n" - buf += " default:\n" - buf += " tid = sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len,\n" - buf += " port_nexus_ptr);\n" - elif proto_ident == "iSCSI": - buf += " case SCSI_PROTOCOL_ISCSI:\n" - buf += " default:\n" - buf += " tid = iscsi_parse_pr_out_transport_id(se_tpg, buf, out_tid_len,\n" - buf += " port_nexus_ptr);\n" - - buf += " }\n\n" - buf += " return tid;\n" - buf += "}\n\n" - bufi += "char *" + fabric_mod_name + "_parse_pr_out_transport_id(struct se_portal_group *,\n" - bufi += " const char *, u32 *, char **);\n" - if re.search('tpg_get_inst_index\)\(', fo): buf += "u32 " + fabric_mod_name + "_tpg_get_inst_index(struct se_portal_group *se_tpg)\n" buf += "{\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 9213c2de28fc..98e00360f97e 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -3406,42 +3406,6 @@ static u16 srpt_get_tag(struct se_portal_group *tpg) return 1; } -static u32 srpt_get_pr_transport_id(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, unsigned char *buf) -{ - struct srpt_node_acl *nacl; - struct spc_rdma_transport_id *tr_id; - - nacl = container_of(se_nacl, struct srpt_node_acl, nacl); - tr_id = (void *)buf; - tr_id->protocol_identifier = SCSI_TRANSPORTID_PROTOCOLID_SRP; - memcpy(tr_id->i_port_id, nacl->i_port_id, sizeof(tr_id->i_port_id)); - return sizeof(*tr_id); -} - -static u32 srpt_get_pr_transport_id_len(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - *format_code = 0; - return sizeof(struct spc_rdma_transport_id); -} - -static char *srpt_parse_pr_out_transport_id(struct se_portal_group *se_tpg, - const char *buf, u32 *out_tid_len, - char **port_nexus_ptr) -{ - struct spc_rdma_transport_id *tr_id; - - *port_nexus_ptr = NULL; - *out_tid_len = sizeof(struct spc_rdma_transport_id); - tr_id = (void *)buf; - return (char *)tr_id->i_port_id; -} - static u32 srpt_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -3860,9 +3824,6 @@ static const struct target_core_fabric_ops srpt_template = { .get_fabric_name = srpt_get_fabric_name, .tpg_get_wwn = srpt_get_fabric_wwn, .tpg_get_tag = srpt_get_tag, - .tpg_get_pr_transport_id = srpt_get_pr_transport_id, - .tpg_get_pr_transport_id_len = srpt_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = srpt_parse_pr_out_transport_id, .tpg_check_demo_mode = srpt_check_false, .tpg_check_demo_mode_cache = srpt_check_true, .tpg_check_demo_mode_write_protect = srpt_check_true, diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h index 355f6f5ce8b2..33b2c88b73ba 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.h +++ b/drivers/infiniband/ulp/srpt/ib_srpt.h @@ -422,22 +422,4 @@ struct srpt_node_acl { struct list_head list; }; -/* - * SRP-releated SCSI persistent reservation definitions. - * - * See also SPC4r28, section 7.6.1 (Protocol specific parameters introduction). - * See also SPC4r28, section 7.6.4.5 (TransportID for initiator ports using - * SCSI over an RDMA interface). - */ - -enum { - SCSI_TRANSPORTID_PROTOCOLID_SRP = 4, -}; - -struct spc_rdma_transport_id { - uint8_t protocol_identifier; - uint8_t reserved[7]; - uint8_t i_port_id[16]; -}; - #endif /* IB_SRPT_H */ diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index 4566c4649751..bd0f9eb67901 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -206,73 +206,6 @@ static u16 tcm_qla2xxx_get_tag(struct se_portal_group *se_tpg) return tpg->lport_tpgt; } -static u32 tcm_qla2xxx_get_pr_transport_id( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, - unsigned char *buf) -{ - struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, - struct tcm_qla2xxx_tpg, se_tpg); - struct tcm_qla2xxx_lport *lport = tpg->lport; - int ret = 0; - - switch (lport->lport_proto_id) { - case SCSI_PROTOCOL_FCP: - default: - ret = fc_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - break; - } - - return ret; -} - -static u32 tcm_qla2xxx_get_pr_transport_id_len( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, - struct tcm_qla2xxx_tpg, se_tpg); - struct tcm_qla2xxx_lport *lport = tpg->lport; - int ret = 0; - - switch (lport->lport_proto_id) { - case SCSI_PROTOCOL_FCP: - default: - ret = fc_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - break; - } - - return ret; -} - -static char *tcm_qla2xxx_parse_pr_out_transport_id( - struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, - struct tcm_qla2xxx_tpg, se_tpg); - struct tcm_qla2xxx_lport *lport = tpg->lport; - char *tid = NULL; - - switch (lport->lport_proto_id) { - case SCSI_PROTOCOL_FCP: - default: - tid = fc_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - break; - } - - return tid; -} - static int tcm_qla2xxx_check_demo_mode(struct se_portal_group *se_tpg) { struct tcm_qla2xxx_tpg *tpg = container_of(se_tpg, @@ -1913,9 +1846,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { .get_fabric_name = tcm_qla2xxx_get_fabric_name, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, .tpg_get_tag = tcm_qla2xxx_get_tag, - .tpg_get_pr_transport_id = tcm_qla2xxx_get_pr_transport_id, - .tpg_get_pr_transport_id_len = tcm_qla2xxx_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = tcm_qla2xxx_parse_pr_out_transport_id, .tpg_check_demo_mode = tcm_qla2xxx_check_demo_mode, .tpg_check_demo_mode_cache = tcm_qla2xxx_check_demo_mode_cache, .tpg_check_demo_mode_write_protect = @@ -1963,9 +1893,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .get_fabric_name = tcm_qla2xxx_npiv_get_fabric_name, .tpg_get_wwn = tcm_qla2xxx_get_fabric_wwn, .tpg_get_tag = tcm_qla2xxx_get_tag, - .tpg_get_pr_transport_id = tcm_qla2xxx_get_pr_transport_id, - .tpg_get_pr_transport_id_len = tcm_qla2xxx_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = tcm_qla2xxx_parse_pr_out_transport_id, .tpg_check_demo_mode = tcm_qla2xxx_check_demo_mode, .tpg_check_demo_mode_cache = tcm_qla2xxx_check_demo_mode_cache, .tpg_check_demo_mode_write_protect = tcm_qla2xxx_check_demo_mode, diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.h b/drivers/scsi/qla2xxx/tcm_qla2xxx.h index 3d805a07061c..3bbf4cb6fd97 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.h +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.h @@ -57,8 +57,6 @@ struct tcm_qla2xxx_fc_loopid { }; struct tcm_qla2xxx_lport { - /* SCSI protocol the lport is providing */ - u8 lport_proto_id; /* Binary World Wide unique Port Name for FC Target Lport */ u64 lport_wwpn; /* Binary World Wide unique Port Name for FC NPIV Target Lport */ diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index 9dec9f39139f..bd8af8764f4b 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -1921,9 +1921,6 @@ const struct target_core_fabric_ops iscsi_ops = { .tpg_get_wwn = lio_tpg_get_endpoint_wwn, .tpg_get_tag = lio_tpg_get_tag, .tpg_get_default_depth = lio_tpg_get_default_depth, - .tpg_get_pr_transport_id = iscsi_get_pr_transport_id, - .tpg_get_pr_transport_id_len = iscsi_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = iscsi_parse_pr_out_transport_id, .tpg_check_demo_mode = lio_tpg_check_demo_mode, .tpg_check_demo_mode_cache = lio_tpg_check_demo_mode_cache, .tpg_check_demo_mode_write_protect = diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index 0eed0209a7f4..b788406977f6 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -542,95 +542,6 @@ static u16 tcm_loop_get_tag(struct se_portal_group *se_tpg) return tl_tpg(se_tpg)->tl_tpgt; } -static u32 tcm_loop_get_pr_transport_id( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, - unsigned char *buf) -{ - struct tcm_loop_hba *tl_hba = tl_tpg(se_tpg)->tl_hba; - - switch (tl_hba->tl_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - case SCSI_PROTOCOL_FCP: - return fc_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - default: - pr_err("Unknown tl_proto_id: 0x%02x, using" - " SAS emulation\n", tl_hba->tl_proto_id); - break; - } - - return sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); -} - -static u32 tcm_loop_get_pr_transport_id_len( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - struct tcm_loop_hba *tl_hba = tl_tpg(se_tpg)->tl_hba; - - switch (tl_hba->tl_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - case SCSI_PROTOCOL_FCP: - return fc_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - default: - pr_err("Unknown tl_proto_id: 0x%02x, using" - " SAS emulation\n", tl_hba->tl_proto_id); - break; - } - - return sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); -} - -/* - * Used for handling SCSI fabric dependent TransportIDs in SPC-3 and above - * Persistent Reservation SPEC_I_PT=1 and PROUT REGISTER_AND_MOVE operations. - */ -static char *tcm_loop_parse_pr_out_transport_id( - struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - struct tcm_loop_hba *tl_hba = tl_tpg(se_tpg)->tl_hba; - - switch (tl_hba->tl_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - case SCSI_PROTOCOL_FCP: - return fc_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - case SCSI_PROTOCOL_ISCSI: - return iscsi_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - default: - pr_err("Unknown tl_proto_id: 0x%02x, using" - " SAS emulation\n", tl_hba->tl_proto_id); - break; - } - - return sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); -} - /* * Returning (1) here allows for target_core_mod struct se_node_acl to be generated * based upon the incoming fabric dependent SCSI Initiator Port @@ -1332,9 +1243,6 @@ static const struct target_core_fabric_ops loop_ops = { .get_fabric_name = tcm_loop_get_fabric_name, .tpg_get_wwn = tcm_loop_get_endpoint_wwn, .tpg_get_tag = tcm_loop_get_tag, - .tpg_get_pr_transport_id = tcm_loop_get_pr_transport_id, - .tpg_get_pr_transport_id_len = tcm_loop_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = tcm_loop_parse_pr_out_transport_id, .tpg_check_demo_mode = tcm_loop_check_demo_mode, .tpg_check_demo_mode_cache = tcm_loop_check_demo_mode_cache, .tpg_check_demo_mode_write_protect = diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 8acb37fd9ebc..89f172dc8678 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -1832,73 +1832,6 @@ static int sbp_check_stop_free(struct se_cmd *se_cmd) return 1; } -static u32 sbp_get_pr_transport_id( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, - unsigned char *buf) -{ - int ret; - - /* - * Set PROTOCOL IDENTIFIER to 3h for SBP - */ - buf[0] = SCSI_PROTOCOL_SBP; - /* - * From spc4r17, 7.5.4.4 TransportID for initiator ports using SCSI - * over IEEE 1394 - */ - ret = hex2bin(&buf[8], se_nacl->initiatorname, 8); - if (ret < 0) - pr_debug("sbp transport_id: invalid hex string\n"); - - /* - * The IEEE 1394 Transport ID is a hardcoded 24-byte length - */ - return 24; -} - -static u32 sbp_get_pr_transport_id_len( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - *format_code = 0; - /* - * From spc4r17, 7.5.4.4 TransportID for initiator ports using SCSI - * over IEEE 1394 - * - * The SBP Transport ID is a hardcoded 24-byte length - */ - return 24; -} - -/* - * Used for handling SCSI fabric dependent TransportIDs in SPC-3 and above - * Persistent Reservation SPEC_I_PT=1 and PROUT REGISTER_AND_MOVE operations. - */ -static char *sbp_parse_pr_out_transport_id( - struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - /* - * Assume the FORMAT CODE 00b from spc4r17, 7.5.4.4 TransportID - * for initiator ports using SCSI over SBP Serial SCSI Protocol - * - * The TransportID for a IEEE 1394 Initiator Port is of fixed size of - * 24 bytes, and IEEE 1394 does not contain a I_T nexus identifier, - * so we return the **port_nexus_ptr set to NULL. - */ - *port_nexus_ptr = NULL; - *out_tid_len = 24; - - return (char *)&buf[8]; -} - static int sbp_count_se_tpg_luns(struct se_portal_group *tpg) { int i, count = 0; @@ -2432,9 +2365,6 @@ static const struct target_core_fabric_ops sbp_ops = { .get_fabric_name = sbp_get_fabric_name, .tpg_get_wwn = sbp_get_fabric_wwn, .tpg_get_tag = sbp_get_tag, - .tpg_get_pr_transport_id = sbp_get_pr_transport_id, - .tpg_get_pr_transport_id_len = sbp_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = sbp_parse_pr_out_transport_id, .tpg_check_demo_mode = sbp_check_true, .tpg_check_demo_mode_cache = sbp_check_true, .tpg_check_demo_mode_write_protect = sbp_check_false, diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c index 21c9f7d79d5e..5e2649fc6919 100644 --- a/drivers/target/target_core_configfs.c +++ b/drivers/target/target_core_configfs.c @@ -326,14 +326,6 @@ static int target_fabric_tf_ops_check(const struct target_core_fabric_ops *tfo) pr_err("Missing tfo->tpg_get_tag()\n"); return -EINVAL; } - if (!tfo->tpg_get_pr_transport_id) { - pr_err("Missing tfo->tpg_get_pr_transport_id()\n"); - return -EINVAL; - } - if (!tfo->tpg_get_pr_transport_id_len) { - pr_err("Missing tfo->tpg_get_pr_transport_id_len()\n"); - return -EINVAL; - } if (!tfo->tpg_check_demo_mode) { pr_err("Missing tfo->tpg_check_demo_mode()\n"); return -EINVAL; diff --git a/drivers/target/target_core_fabric_lib.c b/drivers/target/target_core_fabric_lib.c index 6fed14adbe61..89720b2f37c2 100644 --- a/drivers/target/target_core_fabric_lib.c +++ b/drivers/target/target_core_fabric_lib.c @@ -24,6 +24,11 @@ * ******************************************************************************/ +/* + * See SPC4, section 7.5 "Protocol specific parameters" for details + * on the formats implemented in this file. + */ + #include #include #include @@ -39,103 +44,26 @@ #include "target_core_internal.h" #include "target_core_pr.h" -/* - * Handlers for Serial Attached SCSI (SAS) - */ -u32 sas_get_pr_transport_id( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, + +static int sas_get_pr_transport_id( + struct se_node_acl *nacl, int *format_code, unsigned char *buf) { - unsigned char *ptr; int ret; - /* - * Set PROTOCOL IDENTIFIER to 6h for SAS - */ - buf[0] = 0x06; - /* - * From spc4r17, 7.5.4.7 TransportID for initiator ports using SCSI - * over SAS Serial SCSI Protocol - */ - ptr = &se_nacl->initiatorname[4]; /* Skip over 'naa. prefix */ - - ret = hex2bin(&buf[4], ptr, 8); - if (ret < 0) - pr_debug("sas transport_id: invalid hex string\n"); - - /* - * The SAS Transport ID is a hardcoded 24-byte length - */ - return 24; -} -EXPORT_SYMBOL(sas_get_pr_transport_id); - -u32 sas_get_pr_transport_id_len( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - *format_code = 0; - /* - * From spc4r17, 7.5.4.7 TransportID for initiator ports using SCSI - * over SAS Serial SCSI Protocol - * - * The SAS Transport ID is a hardcoded 24-byte length - */ - return 24; -} -EXPORT_SYMBOL(sas_get_pr_transport_id_len); - -/* - * Used for handling SCSI fabric dependent TransportIDs in SPC-3 and above - * Persistent Reservation SPEC_I_PT=1 and PROUT REGISTER_AND_MOVE operations. - */ -char *sas_parse_pr_out_transport_id( - struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - /* - * Assume the FORMAT CODE 00b from spc4r17, 7.5.4.7 TransportID - * for initiator ports using SCSI over SAS Serial SCSI Protocol - * - * The TransportID for a SAS Initiator Port is of fixed size of - * 24 bytes, and SAS does not contain a I_T nexus identifier, - * so we return the **port_nexus_ptr set to NULL. - */ - *port_nexus_ptr = NULL; - *out_tid_len = 24; - - return (char *)&buf[4]; -} -EXPORT_SYMBOL(sas_parse_pr_out_transport_id); + /* Skip over 'naa. prefix */ + ret = hex2bin(&buf[4], &nacl->initiatorname[4], 8); + if (ret) { + pr_debug("%s: invalid hex string\n", __func__); + return ret; + } -/* - * Handlers for Fibre Channel Protocol (FCP) - */ -u32 fc_get_pr_transport_id_len( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - *format_code = 0; - /* - * The FC Transport ID is a hardcoded 24-byte length - */ return 24; } -EXPORT_SYMBOL(fc_get_pr_transport_id_len); -u32 fc_get_pr_transport_id( - struct se_portal_group *se_tpg, +static int fc_get_pr_transport_id( struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, int *format_code, unsigned char *buf) { @@ -144,24 +72,20 @@ u32 fc_get_pr_transport_id( u32 off = 8; /* - * PROTOCOL IDENTIFIER is 0h for FCP-2 - * - * From spc4r17, 7.5.4.2 TransportID for initiator ports using - * SCSI over Fibre Channel - * * We convert the ASCII formatted N Port name into a binary * encoded TransportID. */ ptr = &se_nacl->initiatorname[0]; - for (i = 0; i < 24; ) { if (!strncmp(&ptr[i], ":", 1)) { i++; continue; } ret = hex2bin(&buf[off++], &ptr[i], 1); - if (ret < 0) - pr_debug("fc transport_id: invalid hex string\n"); + if (ret < 0) { + pr_debug("%s: invalid hex string\n", __func__); + return ret; + } i += 2; } /* @@ -169,31 +93,52 @@ u32 fc_get_pr_transport_id( */ return 24; } -EXPORT_SYMBOL(fc_get_pr_transport_id); -char *fc_parse_pr_out_transport_id( - struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) +static int sbp_get_pr_transport_id( + struct se_node_acl *nacl, + int *format_code, + unsigned char *buf) { - /* - * The TransportID for a FC N Port is of fixed size of - * 24 bytes, and FC does not contain a I_T nexus identifier, - * so we return the **port_nexus_ptr set to NULL. - */ - *port_nexus_ptr = NULL; - *out_tid_len = 24; + int ret; + + ret = hex2bin(&buf[8], nacl->initiatorname, 8); + if (ret) { + pr_debug("%s: invalid hex string\n", __func__); + return ret; + } - return (char *)&buf[8]; + return 24; } -EXPORT_SYMBOL(fc_parse_pr_out_transport_id); -/* - * Handlers for Internet Small Computer Systems Interface (iSCSI) - */ -u32 iscsi_get_pr_transport_id( - struct se_portal_group *se_tpg, +static int srp_get_pr_transport_id( + struct se_node_acl *nacl, + int *format_code, + unsigned char *buf) +{ + const char *p; + unsigned len, count, leading_zero_bytes; + int rc; + + p = nacl->initiatorname; + if (strncasecmp(p, "0x", 2) == 0) + p += 2; + len = strlen(p); + if (len % 2) + return -EINVAL; + + count = min(len / 2, 16U); + leading_zero_bytes = 16 - count; + memset(buf + 8, 0, leading_zero_bytes); + rc = hex2bin(buf + 8 + leading_zero_bytes, p, count); + if (rc < 0) { + pr_debug("hex2bin failed for %s: %d\n", __func__, rc); + return rc; + } + + return 24; +} + +static int iscsi_get_pr_transport_id( struct se_node_acl *se_nacl, struct t10_pr_registration *pr_reg, int *format_code, @@ -203,10 +148,6 @@ u32 iscsi_get_pr_transport_id( u16 len = 0; spin_lock_irq(&se_nacl->nacl_sess_lock); - /* - * Set PROTOCOL IDENTIFIER to 5h for iSCSI - */ - buf[0] = 0x05; /* * From spc4r17 Section 7.5.4.6: TransportID for initiator * ports using SCSI over iSCSI. @@ -286,10 +227,8 @@ u32 iscsi_get_pr_transport_id( return len; } -EXPORT_SYMBOL(iscsi_get_pr_transport_id); -u32 iscsi_get_pr_transport_id_len( - struct se_portal_group *se_tpg, +static int iscsi_get_pr_transport_id_len( struct se_node_acl *se_nacl, struct t10_pr_registration *pr_reg, int *format_code) @@ -332,9 +271,8 @@ u32 iscsi_get_pr_transport_id_len( return len; } -EXPORT_SYMBOL(iscsi_get_pr_transport_id_len); -char *iscsi_parse_pr_out_transport_id( +static char *iscsi_parse_pr_out_transport_id( struct se_portal_group *se_tpg, const char *buf, u32 *out_tid_len, @@ -421,4 +359,79 @@ char *iscsi_parse_pr_out_transport_id( return (char *)&buf[4]; } -EXPORT_SYMBOL(iscsi_parse_pr_out_transport_id); + +int target_get_pr_transport_id_len(struct se_node_acl *nacl, + struct t10_pr_registration *pr_reg, int *format_code) +{ + switch (nacl->se_tpg->proto_id) { + case SCSI_PROTOCOL_FCP: + case SCSI_PROTOCOL_SBP: + case SCSI_PROTOCOL_SRP: + case SCSI_PROTOCOL_SAS: + break; + case SCSI_PROTOCOL_ISCSI: + return iscsi_get_pr_transport_id_len(nacl, pr_reg, format_code); + default: + pr_err("Unknown proto_id: 0x%02x\n", nacl->se_tpg->proto_id); + return -EINVAL; + } + + /* + * Most transports use a fixed length 24 byte identifier. + */ + *format_code = 0; + return 24; +} + +int target_get_pr_transport_id(struct se_node_acl *nacl, + struct t10_pr_registration *pr_reg, int *format_code, + unsigned char *buf) +{ + switch (nacl->se_tpg->proto_id) { + case SCSI_PROTOCOL_SAS: + return sas_get_pr_transport_id(nacl, format_code, buf); + case SCSI_PROTOCOL_SBP: + return sbp_get_pr_transport_id(nacl, format_code, buf); + case SCSI_PROTOCOL_SRP: + return srp_get_pr_transport_id(nacl, format_code, buf); + case SCSI_PROTOCOL_FCP: + return fc_get_pr_transport_id(nacl, format_code, buf); + case SCSI_PROTOCOL_ISCSI: + return iscsi_get_pr_transport_id(nacl, pr_reg, format_code, + buf); + default: + pr_err("Unknown proto_id: 0x%02x\n", nacl->se_tpg->proto_id); + return -EINVAL; + } +} + +const char *target_parse_pr_out_transport_id(struct se_portal_group *tpg, + const char *buf, u32 *out_tid_len, char **port_nexus_ptr) +{ + u32 offset; + + switch (tpg->proto_id) { + case SCSI_PROTOCOL_SAS: + /* + * Assume the FORMAT CODE 00b from spc4r17, 7.5.4.7 TransportID + * for initiator ports using SCSI over SAS Serial SCSI Protocol. + */ + offset = 4; + break; + case SCSI_PROTOCOL_SBP: + case SCSI_PROTOCOL_SRP: + case SCSI_PROTOCOL_FCP: + offset = 8; + break; + case SCSI_PROTOCOL_ISCSI: + return iscsi_parse_pr_out_transport_id(tpg, buf, out_tid_len, + port_nexus_ptr); + default: + pr_err("Unknown proto_id: 0x%02x\n", tpg->proto_id); + return NULL; + } + + *port_nexus_ptr = NULL; + *out_tid_len = 24; + return buf + offset; +} diff --git a/drivers/target/target_core_internal.h b/drivers/target/target_core_internal.h index 058ca71cda81..d0344ad9b0d8 100644 --- a/drivers/target/target_core_internal.h +++ b/drivers/target/target_core_internal.h @@ -38,6 +38,15 @@ struct se_device *target_alloc_device(struct se_hba *hba, const char *name); int target_configure_device(struct se_device *dev); void target_free_device(struct se_device *); +/* target_core_fabric_lib.c */ +int target_get_pr_transport_id_len(struct se_node_acl *nacl, + struct t10_pr_registration *pr_reg, int *format_code); +int target_get_pr_transport_id(struct se_node_acl *nacl, + struct t10_pr_registration *pr_reg, int *format_code, + unsigned char *buf); +const char *target_parse_pr_out_transport_id(struct se_portal_group *tpg, + const char *buf, u32 *out_tid_len, char **port_nexus_ptr); + /* target_core_hba.c */ struct se_hba *core_alloc_hba(const char *, u32, u32); int core_delete_hba(struct se_hba *); diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c index 23c065f83a56..d396b3b87025 100644 --- a/drivers/target/target_core_pr.c +++ b/drivers/target/target_core_pr.c @@ -1445,9 +1445,8 @@ core_scsi3_decode_spec_i_port( struct t10_pr_registration *pr_reg_tmp, *pr_reg_tmp_safe; LIST_HEAD(tid_dest_list); struct pr_transport_id_holder *tidh_new, *tidh, *tidh_tmp; - const struct target_core_fabric_ops *tmp_tf_ops; - unsigned char *buf; - unsigned char *ptr, *i_str = NULL, proto_ident; + unsigned char *buf, *ptr, proto_ident; + const unsigned char *i_str; char *iport_ptr = NULL, i_buf[PR_REG_ISID_ID_LEN]; sense_reason_t ret; u32 tpdl, tid_len = 0; @@ -1533,11 +1532,7 @@ core_scsi3_decode_spec_i_port( tmp_tpg = tmp_port->sep_tpg; if (!tmp_tpg) continue; - tmp_tf_ops = tmp_tpg->se_tpg_tfo; - if (!tmp_tf_ops) - continue; - if (!tmp_tf_ops->tpg_parse_pr_out_transport_id) - continue; + /* * Look for the matching proto_ident provided by * the received TransportID @@ -1546,9 +1541,8 @@ core_scsi3_decode_spec_i_port( continue; dest_rtpi = tmp_port->sep_rtpi; - i_str = tmp_tf_ops->tpg_parse_pr_out_transport_id( - tmp_tpg, (const char *)ptr, &tid_len, - &iport_ptr); + i_str = target_parse_pr_out_transport_id(tmp_tpg, + (const char *)ptr, &tid_len, &iport_ptr); if (!i_str) continue; @@ -3105,7 +3099,7 @@ core_scsi3_emulate_pro_register_and_move(struct se_cmd *cmd, u64 res_key, struct t10_pr_registration *pr_reg, *pr_res_holder, *dest_pr_reg; struct t10_reservation *pr_tmpl = &dev->t10_pr; unsigned char *buf; - unsigned char *initiator_str; + const unsigned char *initiator_str; char *iport_ptr = NULL, i_buf[PR_REG_ISID_ID_LEN]; u32 tid_len, tmp_tid_len; int new_reg = 0, type, scope, matching_iname; @@ -3237,14 +3231,7 @@ core_scsi3_emulate_pro_register_and_move(struct se_cmd *cmd, u64 res_key, ret = TCM_INVALID_PARAMETER_LIST; goto out; } - if (dest_tf_ops->tpg_parse_pr_out_transport_id == NULL) { - pr_err("SPC-3 PR REGISTER_AND_MOVE: Fabric does not" - " containg a valid tpg_parse_pr_out_transport_id" - " function pointer\n"); - ret = TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE; - goto out; - } - initiator_str = dest_tf_ops->tpg_parse_pr_out_transport_id(dest_se_tpg, + initiator_str = target_parse_pr_out_transport_id(dest_se_tpg, (const char *)&buf[24], &tmp_tid_len, &iport_ptr); if (!initiator_str) { pr_err("SPC-3 PR REGISTER_AND_MOVE: Unable to locate" @@ -3881,9 +3868,10 @@ core_scsi3_pri_read_full_status(struct se_cmd *cmd) struct t10_pr_registration *pr_reg, *pr_reg_tmp; struct t10_reservation *pr_tmpl = &dev->t10_pr; unsigned char *buf; - u32 add_desc_len = 0, add_len = 0, desc_len, exp_desc_len; + u32 add_desc_len = 0, add_len = 0; u32 off = 8; /* off into first Full Status descriptor */ int format_code = 0, pr_res_type = 0, pr_res_scope = 0; + int exp_desc_len, desc_len; bool all_reg = false; if (cmd->data_length < 8) { @@ -3928,10 +3916,10 @@ core_scsi3_pri_read_full_status(struct se_cmd *cmd) * Determine expected length of $FABRIC_MOD specific * TransportID full status descriptor.. */ - exp_desc_len = se_tpg->se_tpg_tfo->tpg_get_pr_transport_id_len( - se_tpg, se_nacl, pr_reg, &format_code); - - if ((exp_desc_len + add_len) > cmd->data_length) { + exp_desc_len = target_get_pr_transport_id_len(se_nacl, pr_reg, + &format_code); + if (exp_desc_len < 0 || + exp_desc_len + add_len > cmd->data_length) { pr_warn("SPC-3 PRIN READ_FULL_STATUS ran" " out of buffer: %d\n", cmd->data_length); spin_lock(&pr_tmpl->registration_lock); @@ -3995,14 +3983,19 @@ core_scsi3_pri_read_full_status(struct se_cmd *cmd) } else off += 2; /* Skip over RELATIVE TARGET PORT IDENTIFIER */ + buf[off+4] = se_tpg->proto_id; + /* - * Now, have the $FABRIC_MOD fill in the protocol identifier + * Now, have the $FABRIC_MOD fill in the transport ID. */ - desc_len = se_tpg->se_tpg_tfo->tpg_get_pr_transport_id(se_tpg, - se_nacl, pr_reg, &format_code, &buf[off+4]); + desc_len = target_get_pr_transport_id(se_nacl, pr_reg, + &format_code, &buf[off+4]); spin_lock(&pr_tmpl->registration_lock); atomic_dec_mb(&pr_reg->pr_res_holders); + + if (desc_len < 0) + break; /* * Set the ADDITIONAL DESCRIPTOR LENGTH */ diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index fabc7bacf693..6ad7404b7dd1 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -454,9 +454,6 @@ static const struct target_core_fabric_ops ft_fabric_ops = { .get_fabric_name = ft_get_fabric_name, .tpg_get_wwn = ft_get_fabric_wwn, .tpg_get_tag = ft_get_tag, - .tpg_get_pr_transport_id = fc_get_pr_transport_id, - .tpg_get_pr_transport_id_len = fc_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = fc_parse_pr_out_transport_id, .tpg_check_demo_mode = ft_check_false, .tpg_check_demo_mode_cache = ft_check_false, .tpg_check_demo_mode_write_protect = ft_check_false, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index d6b03178262f..77cdbb56e1d5 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1290,72 +1290,6 @@ static u16 usbg_get_tag(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 usbg_get_pr_transport_id( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, - unsigned char *buf) -{ - struct usbg_tpg *tpg = container_of(se_tpg, - struct usbg_tpg, se_tpg); - struct usbg_tport *tport = tpg->tport; - int ret = 0; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - default: - ret = sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - break; - } - - return ret; -} - -static u32 usbg_get_pr_transport_id_len( - struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - struct usbg_tpg *tpg = container_of(se_tpg, - struct usbg_tpg, se_tpg); - struct usbg_tport *tport = tpg->tport; - int ret = 0; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - default: - ret = sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - break; - } - - return ret; -} - -static char *usbg_parse_pr_out_transport_id( - struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - struct usbg_tpg *tpg = container_of(se_tpg, - struct usbg_tpg, se_tpg); - struct usbg_tport *tport = tpg->tport; - char *tid = NULL; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - default: - tid = sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - } - - return tid; -} - static u32 usbg_tpg_get_inst_index(struct se_portal_group *se_tpg) { return 1; @@ -1491,8 +1425,12 @@ static struct se_portal_group *usbg_make_tpg( tpg->tport = tport; tpg->tport_tpgt = tpgt; + /* + * SPC doesn't assign a protocol identifier for USB-SCSI, so we + * pretend to be SAS.. + */ ret = core_tpg_register(&usbg_ops, wwn, &tpg->se_tpg, - tport->tport_proto_id); + SCSI_PROTOCOL_SAS); if (ret < 0) { destroy_workqueue(tpg->workqueue); kfree(tpg); @@ -1788,9 +1726,6 @@ static const struct target_core_fabric_ops usbg_ops = { .get_fabric_name = usbg_get_fabric_name, .tpg_get_wwn = usbg_get_fabric_wwn, .tpg_get_tag = usbg_get_tag, - .tpg_get_pr_transport_id = usbg_get_pr_transport_id, - .tpg_get_pr_transport_id_len = usbg_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = usbg_parse_pr_out_transport_id, .tpg_check_demo_mode = usbg_check_true, .tpg_check_demo_mode_cache = usbg_check_false, .tpg_check_demo_mode_write_protect = usbg_check_false, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.h b/drivers/usb/gadget/legacy/tcm_usb_gadget.h index b254aec521da..4c1c22a964b4 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.h +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.h @@ -44,8 +44,6 @@ struct usbg_tpg { }; struct usbg_tport { - /* SCSI protocol the tport is providing */ - u8 tport_proto_id; /* Binary World Wide unique Port Name for SAS Target port */ u64 tport_wwpn; /* ASCII formatted WWPN for SAS Target port */ diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 022860ccd008..db9f4b474214 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -304,97 +304,6 @@ static u16 vhost_scsi_get_tpgt(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 -vhost_scsi_get_pr_transport_id(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, - unsigned char *buf) -{ - struct vhost_scsi_tpg *tpg = container_of(se_tpg, - struct vhost_scsi_tpg, se_tpg); - struct vhost_scsi_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - case SCSI_PROTOCOL_FCP: - return fc_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using" - " SAS emulation\n", tport->tport_proto_id); - break; - } - - return sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); -} - -static u32 -vhost_scsi_get_pr_transport_id_len(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - struct vhost_scsi_tpg *tpg = container_of(se_tpg, - struct vhost_scsi_tpg, se_tpg); - struct vhost_scsi_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - case SCSI_PROTOCOL_FCP: - return fc_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using" - " SAS emulation\n", tport->tport_proto_id); - break; - } - - return sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); -} - -static char * -vhost_scsi_parse_pr_out_transport_id(struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - struct vhost_scsi_tpg *tpg = container_of(se_tpg, - struct vhost_scsi_tpg, se_tpg); - struct vhost_scsi_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - case SCSI_PROTOCOL_FCP: - return fc_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - case SCSI_PROTOCOL_ISCSI: - return iscsi_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using" - " SAS emulation\n", tport->tport_proto_id); - break; - } - - return sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); -} - static int vhost_scsi_check_prot_fabric_only(struct se_portal_group *se_tpg) { struct vhost_scsi_tpg *tpg = container_of(se_tpg, @@ -2224,9 +2133,6 @@ static struct target_core_fabric_ops vhost_scsi_ops = { .get_fabric_name = vhost_scsi_get_fabric_name, .tpg_get_wwn = vhost_scsi_get_fabric_wwn, .tpg_get_tag = vhost_scsi_get_tpgt, - .tpg_get_pr_transport_id = vhost_scsi_get_pr_transport_id, - .tpg_get_pr_transport_id_len = vhost_scsi_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = vhost_scsi_parse_pr_out_transport_id, .tpg_check_demo_mode = vhost_scsi_check_true, .tpg_check_demo_mode_cache = vhost_scsi_check_true, .tpg_check_demo_mode_write_protect = vhost_scsi_check_false, diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index 8bf9448bd7fd..10c71a5616fa 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -1270,97 +1270,6 @@ static u16 scsiback_get_tag(struct se_portal_group *se_tpg) return tpg->tport_tpgt; } -static u32 -scsiback_get_pr_transport_id(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code, - unsigned char *buf) -{ - struct scsiback_tpg *tpg = container_of(se_tpg, - struct scsiback_tpg, se_tpg); - struct scsiback_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - case SCSI_PROTOCOL_FCP: - return fc_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using SAS emulation\n", - tport->tport_proto_id); - break; - } - - return sas_get_pr_transport_id(se_tpg, se_nacl, pr_reg, - format_code, buf); -} - -static u32 -scsiback_get_pr_transport_id_len(struct se_portal_group *se_tpg, - struct se_node_acl *se_nacl, - struct t10_pr_registration *pr_reg, - int *format_code) -{ - struct scsiback_tpg *tpg = container_of(se_tpg, - struct scsiback_tpg, se_tpg); - struct scsiback_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - case SCSI_PROTOCOL_FCP: - return fc_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - case SCSI_PROTOCOL_ISCSI: - return iscsi_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using SAS emulation\n", - tport->tport_proto_id); - break; - } - - return sas_get_pr_transport_id_len(se_tpg, se_nacl, pr_reg, - format_code); -} - -static char * -scsiback_parse_pr_out_transport_id(struct se_portal_group *se_tpg, - const char *buf, - u32 *out_tid_len, - char **port_nexus_ptr) -{ - struct scsiback_tpg *tpg = container_of(se_tpg, - struct scsiback_tpg, se_tpg); - struct scsiback_tport *tport = tpg->tport; - - switch (tport->tport_proto_id) { - case SCSI_PROTOCOL_SAS: - return sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - case SCSI_PROTOCOL_FCP: - return fc_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - case SCSI_PROTOCOL_ISCSI: - return iscsi_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); - default: - pr_err("Unknown tport_proto_id: 0x%02x, using SAS emulation\n", - tport->tport_proto_id); - break; - } - - return sas_parse_pr_out_transport_id(se_tpg, buf, out_tid_len, - port_nexus_ptr); -} - static struct se_wwn * scsiback_make_tport(struct target_fabric_configfs *tf, struct config_group *group, @@ -1909,9 +1818,6 @@ static const struct target_core_fabric_ops scsiback_ops = { .get_fabric_name = scsiback_get_fabric_name, .tpg_get_wwn = scsiback_get_fabric_wwn, .tpg_get_tag = scsiback_get_tag, - .tpg_get_pr_transport_id = scsiback_get_pr_transport_id, - .tpg_get_pr_transport_id_len = scsiback_get_pr_transport_id_len, - .tpg_parse_pr_out_transport_id = scsiback_parse_pr_out_transport_id, .tpg_check_demo_mode = scsiback_check_true, .tpg_check_demo_mode_cache = scsiback_check_true, .tpg_check_demo_mode_write_protect = scsiback_check_false, diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h index 495606382546..a420f434c6c5 100644 --- a/include/target/target_core_fabric.h +++ b/include/target/target_core_fabric.h @@ -9,15 +9,6 @@ struct target_core_fabric_ops { char *(*tpg_get_wwn)(struct se_portal_group *); u16 (*tpg_get_tag)(struct se_portal_group *); u32 (*tpg_get_default_depth)(struct se_portal_group *); - u32 (*tpg_get_pr_transport_id)(struct se_portal_group *, - struct se_node_acl *, - struct t10_pr_registration *, int *, - unsigned char *); - u32 (*tpg_get_pr_transport_id_len)(struct se_portal_group *, - struct se_node_acl *, - struct t10_pr_registration *, int *); - char *(*tpg_parse_pr_out_transport_id)(struct se_portal_group *, - const char *, u32 *, char **); int (*tpg_check_demo_mode)(struct se_portal_group *); int (*tpg_check_demo_mode_cache)(struct se_portal_group *); int (*tpg_check_demo_mode_write_protect)(struct se_portal_group *); @@ -177,30 +168,6 @@ int core_tpg_register(const struct target_core_fabric_ops *, struct se_wwn *, struct se_portal_group *, int); int core_tpg_deregister(struct se_portal_group *); -/* SAS helpers */ -u32 sas_get_pr_transport_id(struct se_portal_group *, struct se_node_acl *, - struct t10_pr_registration *, int *, unsigned char *); -u32 sas_get_pr_transport_id_len(struct se_portal_group *, struct se_node_acl *, - struct t10_pr_registration *, int *); -char *sas_parse_pr_out_transport_id(struct se_portal_group *, const char *, - u32 *, char **); - -/* FC helpers */ -u32 fc_get_pr_transport_id(struct se_portal_group *, struct se_node_acl *, - struct t10_pr_registration *, int *, unsigned char *); -u32 fc_get_pr_transport_id_len(struct se_portal_group *, struct se_node_acl *, - struct t10_pr_registration *, int *); -char *fc_parse_pr_out_transport_id(struct se_portal_group *, const char *, - u32 *, char **); - -/* iSCSI helpers */ -u32 iscsi_get_pr_transport_id(struct se_portal_group *, struct se_node_acl *, - struct t10_pr_registration *, int *, unsigned char *); -u32 iscsi_get_pr_transport_id_len(struct se_portal_group *, struct se_node_acl *, - struct t10_pr_registration *, int *); -char *iscsi_parse_pr_out_transport_id(struct se_portal_group *, const char *, - u32 *, char **); - /* * The LIO target core uses DMA_TO_DEVICE to mean that data is going * to the target (eg handling a WRITE) and DMA_FROM_DEVICE to mean -- cgit v1.2.3 From 649ee05499d1257a3af0e10d961a1c52d9ef95b7 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Tue, 14 Apr 2015 13:26:44 +0200 Subject: target: Move task tag into struct se_cmd + support 64-bit tags Simplify target core and target drivers by storing the task tag a.k.a. command identifier inside struct se_cmd. For several transports (e.g. SRP) tags are 64 bits wide. Hence add support for 64-bit tags. (Fix core_tmr_abort_task conversion spec warnings - nab) (Fix up usb-gadget to use 16-bit tags - HCH + bart) Signed-off-by: Bart Van Assche Cc: Christoph Hellwig Cc: Andy Grover Cc: Sagi Grimberg Cc: Cc: Felipe Balbi Cc: Michael S. Tsirkin Cc: Juergen Gross Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 8 ----- drivers/infiniband/ulp/srpt/ib_srpt.c | 27 +++++---------- drivers/infiniband/ulp/srpt/ib_srpt.h | 1 - drivers/scsi/qla2xxx/qla_target.c | 52 ++++++++++++---------------- drivers/scsi/qla2xxx/qla_target.h | 1 - drivers/scsi/qla2xxx/tcm_qla2xxx.c | 15 -------- drivers/target/iscsi/iscsi_target.c | 2 ++ drivers/target/iscsi/iscsi_target_configfs.c | 9 ----- drivers/target/loopback/tcm_loop.c | 10 +----- drivers/target/sbp/sbp_target.c | 12 ++----- drivers/target/target_core_configfs.c | 4 --- drivers/target/target_core_tmr.c | 21 +++++------ drivers/target/target_core_transport.c | 41 +++++++++++----------- drivers/target/target_core_xcopy.c | 7 +--- drivers/target/tcm_fc/tcm_fc.h | 1 - drivers/target/tcm_fc/tfc_cmd.c | 10 +----- drivers/target/tcm_fc/tfc_conf.c | 1 - drivers/usb/gadget/legacy/tcm_usb_gadget.c | 15 ++------ drivers/vhost/scsi.c | 7 +--- drivers/xen/xen-scsiback.c | 10 +----- include/target/target_core_base.h | 3 +- include/target/target_core_fabric.h | 1 - 22 files changed, 76 insertions(+), 182 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 0dbd70cccde1..71e1f5863310 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -310,7 +310,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += " .write_pending = " + fabric_mod_name + "_write_pending,\n" buf += " .write_pending_status = " + fabric_mod_name + "_write_pending_status,\n" buf += " .set_default_node_attributes = " + fabric_mod_name + "_set_default_node_attrs,\n" - buf += " .get_task_tag = " + fabric_mod_name + "_get_task_tag,\n" buf += " .get_cmd_state = " + fabric_mod_name + "_get_cmd_state,\n" buf += " .queue_data_in = " + fabric_mod_name + "_queue_data_in,\n" buf += " .queue_status = " + fabric_mod_name + "_queue_status,\n" @@ -525,13 +524,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "}\n\n" bufi += "void " + fabric_mod_name + "_set_default_node_attrs(struct se_node_acl *);\n" - if re.search('get_task_tag\)\(', fo): - buf += "u32 " + fabric_mod_name + "_get_task_tag(struct se_cmd *se_cmd)\n" - buf += "{\n" - buf += " return 0;\n" - buf += "}\n\n" - bufi += "u32 " + fabric_mod_name + "_get_task_tag(struct se_cmd *);\n" - if re.search('get_cmd_state\)\(', fo): buf += "int " + fabric_mod_name + "_get_cmd_state(struct se_cmd *se_cmd)\n" buf += "{\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 98e00360f97e..56df5cd918c5 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -1339,7 +1339,7 @@ static int srpt_abort_cmd(struct srpt_send_ioctx *ioctx) } pr_debug("Aborting cmd with state %d and tag %lld\n", state, - ioctx->tag); + ioctx->cmd.tag); switch (state) { case SRPT_STATE_NEW: @@ -1701,7 +1701,7 @@ static int srpt_handle_cmd(struct srpt_rdma_ch *ch, srp_cmd = recv_ioctx->ioctx.buf; cmd = &send_ioctx->cmd; - send_ioctx->tag = srp_cmd->tag; + cmd->tag = srp_cmd->tag; switch (srp_cmd->task_attr) { case SRP_CMD_SIMPLE_Q: @@ -1772,7 +1772,7 @@ static int srpt_rx_mgmt_fn_tag(struct srpt_send_ioctx *ioctx, u64 tag) for (i = 0; i < ch->rq_size; ++i) { target = ch->ioctx_ring[i]; if (target->cmd.se_lun == ioctx->cmd.se_lun && - target->tag == tag && + target->cmd.tag == tag && srpt_get_cmd_state(target) != SRPT_STATE_DONE) { ret = 0; /* now let the target core abort &target->cmd; */ @@ -1831,7 +1831,7 @@ static void srpt_handle_tsk_mgmt(struct srpt_rdma_ch *ch, srp_tsk->task_tag, srp_tsk->tag, ch->cm_id, ch->sess); srpt_set_cmd_state(send_ioctx, SRPT_STATE_MGMT); - send_ioctx->tag = srp_tsk->tag; + send_ioctx->cmd.tag = srp_tsk->tag; tcm_tmr = srp_tmr_to_tcm(srp_tsk->tsk_mgmt_func); if (tcm_tmr < 0) { send_ioctx->cmd.se_tmr_req->response = @@ -2979,7 +2979,7 @@ static int srpt_write_pending(struct se_cmd *se_cmd) case CH_DRAINING: case CH_RELEASING: pr_debug("cmd with tag %lld: channel disconnecting\n", - ioctx->tag); + ioctx->cmd.tag); srpt_set_cmd_state(ioctx, SRPT_STATE_DATA_IN); ret = -EINVAL; goto out; @@ -3054,24 +3054,24 @@ static void srpt_queue_response(struct se_cmd *cmd) ret = srpt_xfer_data(ch, ioctx); if (ret) { pr_err("xfer_data failed for tag %llu\n", - ioctx->tag); + ioctx->cmd.tag); return; } } if (state != SRPT_STATE_MGMT) - resp_len = srpt_build_cmd_rsp(ch, ioctx, ioctx->tag, + resp_len = srpt_build_cmd_rsp(ch, ioctx, ioctx->cmd.tag, cmd->scsi_status); else { srp_tm_status = tcm_to_srp_tsk_mgmt_status(cmd->se_tmr_req->response); resp_len = srpt_build_tskmgmt_rsp(ch, ioctx, srp_tm_status, - ioctx->tag); + ioctx->cmd.tag); } ret = srpt_post_send(ch, ioctx, resp_len); if (ret) { pr_err("sending cmd response failed for tag %llu\n", - ioctx->tag); + ioctx->cmd.tag); srpt_unmap_sg_to_ib_sge(ch, ioctx); srpt_set_cmd_state(ioctx, SRPT_STATE_DONE); target_put_sess_cmd(&ioctx->cmd); @@ -3479,14 +3479,6 @@ static void srpt_set_default_node_attrs(struct se_node_acl *nacl) { } -static u32 srpt_get_task_tag(struct se_cmd *se_cmd) -{ - struct srpt_send_ioctx *ioctx; - - ioctx = container_of(se_cmd, struct srpt_send_ioctx, cmd); - return ioctx->tag; -} - /* Note: only used from inside debug printk's by the TCM core. */ static int srpt_get_tcm_cmd_state(struct se_cmd *se_cmd) { @@ -3838,7 +3830,6 @@ static const struct target_core_fabric_ops srpt_template = { .write_pending = srpt_write_pending, .write_pending_status = srpt_write_pending_status, .set_default_node_attributes = srpt_set_default_node_attrs, - .get_task_tag = srpt_get_task_tag, .get_cmd_state = srpt_get_tcm_cmd_state, .queue_data_in = srpt_queue_data_in, .queue_status = srpt_queue_status, diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h index 33b2c88b73ba..6fec740742bd 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.h +++ b/drivers/infiniband/ulp/srpt/ib_srpt.h @@ -238,7 +238,6 @@ struct srpt_send_ioctx { bool rdma_aborted; struct se_cmd cmd; struct completion tx_done; - u64 tag; int sg_cnt; int mapped_sg_count; u16 n_rdma_ius; diff --git a/drivers/scsi/qla2xxx/qla_target.c b/drivers/scsi/qla2xxx/qla_target.c index fe8a8d157e22..e7515069e1ce 100644 --- a/drivers/scsi/qla2xxx/qla_target.c +++ b/drivers/scsi/qla2xxx/qla_target.c @@ -1191,7 +1191,7 @@ static int __qlt_24xx_handle_abts(struct scsi_qla_host *vha, list_for_each_entry(se_cmd, &se_sess->sess_cmd_list, se_cmd_list) { struct qla_tgt_cmd *cmd = container_of(se_cmd, struct qla_tgt_cmd, se_cmd); - if (cmd->tag == abts->exchange_addr_to_abort) { + if (se_cmd->tag == abts->exchange_addr_to_abort) { lun = cmd->unpacked_lun; found_lun = true; break; @@ -1728,9 +1728,8 @@ static int qlt_pre_xmit_response(struct qla_tgt_cmd *cmd, if (unlikely(cmd->aborted)) { ql_dbg(ql_dbg_tgt_mgt, vha, 0xf014, - "qla_target(%d): terminating exchange " - "for aborted cmd=%p (se_cmd=%p, tag=%d)", vha->vp_idx, cmd, - se_cmd, cmd->tag); + "qla_target(%d): terminating exchange for aborted cmd=%p (se_cmd=%p, tag=%lld)", + vha->vp_idx, cmd, se_cmd, se_cmd->tag); cmd->state = QLA_TGT_STATE_ABORTED; cmd->cmd_flags |= BIT_6; @@ -1765,18 +1764,17 @@ static int qlt_pre_xmit_response(struct qla_tgt_cmd *cmd, if (se_cmd->se_cmd_flags & SCF_UNDERFLOW_BIT) { prm->residual = se_cmd->residual_count; ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x305c, - "Residual underflow: %d (tag %d, " - "op %x, bufflen %d, rq_result %x)\n", prm->residual, - cmd->tag, se_cmd->t_task_cdb ? se_cmd->t_task_cdb[0] : 0, - cmd->bufflen, prm->rq_result); + "Residual underflow: %d (tag %lld, op %x, bufflen %d, rq_result %x)\n", + prm->residual, se_cmd->tag, + se_cmd->t_task_cdb ? se_cmd->t_task_cdb[0] : 0, + cmd->bufflen, prm->rq_result); prm->rq_result |= SS_RESIDUAL_UNDER; } else if (se_cmd->se_cmd_flags & SCF_OVERFLOW_BIT) { prm->residual = se_cmd->residual_count; ql_dbg(ql_dbg_io, vha, 0x305d, - "Residual overflow: %d (tag %d, " - "op %x, bufflen %d, rq_result %x)\n", prm->residual, - cmd->tag, se_cmd->t_task_cdb ? se_cmd->t_task_cdb[0] : 0, - cmd->bufflen, prm->rq_result); + "Residual overflow: %d (tag %lld, op %x, bufflen %d, rq_result %x)\n", + prm->residual, se_cmd->tag, se_cmd->t_task_cdb ? + se_cmd->t_task_cdb[0] : 0, cmd->bufflen, prm->rq_result); prm->rq_result |= SS_RESIDUAL_OVER; } @@ -1849,7 +1847,7 @@ static void qlt_check_srr_debug(struct qla_tgt_cmd *cmd, int *xmit_type) == 50) { *xmit_type &= ~QLA_TGT_XMIT_STATUS; ql_dbg(ql_dbg_tgt_mgt, cmd->vha, 0xf015, - "Dropping cmd %p (tag %d) status", cmd, cmd->tag); + "Dropping cmd %p (tag %d) status", cmd, se_cmd->tag); } #endif /* @@ -1873,7 +1871,7 @@ static void qlt_check_srr_debug(struct qla_tgt_cmd *cmd, int *xmit_type) ql_dbg(ql_dbg_tgt_mgt, cmd->vha, 0xf016, "Cutting cmd %p (tag %d) buffer" " tail to len %d, sg_cnt %d (cmd->bufflen %d," - " cmd->sg_cnt %d)", cmd, cmd->tag, tot_len, leave, + " cmd->sg_cnt %d)", cmd, se_cmd->tag, tot_len, leave, cmd->bufflen, cmd->sg_cnt); cmd->bufflen = tot_len; @@ -1885,13 +1883,13 @@ static void qlt_check_srr_debug(struct qla_tgt_cmd *cmd, int *xmit_type) ql_dbg(ql_dbg_tgt_mgt, cmd->vha, 0xf017, "Cutting cmd %p (tag %d) buffer head " - "to offset %d (cmd->bufflen %d)", cmd, cmd->tag, offset, + "to offset %d (cmd->bufflen %d)", cmd, se_cmd->tag, offset, cmd->bufflen); if (offset == 0) *xmit_type &= ~QLA_TGT_XMIT_DATA; else if (qlt_set_data_offset(cmd, offset)) { ql_dbg(ql_dbg_tgt_mgt, cmd->vha, 0xf018, - "qlt_set_data_offset() failed (tag %d)", cmd->tag); + "qlt_set_data_offset() failed (tag %d)", se_cmd->tag); } } } @@ -3194,7 +3192,7 @@ skip_term: return; } else if (cmd->state == QLA_TGT_STATE_ABORTED) { ql_dbg(ql_dbg_tgt_mgt, vha, 0xf01e, - "Aborted command %p (tag %d) finished\n", cmd, cmd->tag); + "Aborted command %p (tag %lld) finished\n", cmd, se_cmd->tag); } else { ql_dbg(ql_dbg_tgt_mgt, vha, 0xf05c, "qla_target(%d): A command in state (%d) should " @@ -3266,7 +3264,7 @@ static void __qlt_do_work(struct qla_tgt_cmd *cmd) goto out_term; cdb = &atio->u.isp24.fcp_cmnd.cdb[0]; - cmd->tag = atio->u.isp24.exchange_addr; + cmd->se_cmd.tag = atio->u.isp24.exchange_addr; cmd->unpacked_lun = scsilun_to_int( (struct scsi_lun *)&atio->u.isp24.fcp_cmnd.lun); @@ -3891,9 +3889,8 @@ static void qlt_handle_srr(struct scsi_qla_host *vha, resp = 1; } else { ql_dbg(ql_dbg_tgt_mgt, vha, 0xf064, - "qla_target(%d): SRR for in data for cmd " - "without them (tag %d, SCSI status %d), " - "reject", vha->vp_idx, cmd->tag, + "qla_target(%d): SRR for in data for cmd without them (tag %lld, SCSI status %d), reject", + vha->vp_idx, se_cmd->tag, cmd->se_cmd.scsi_status); goto out_reject; } @@ -3927,10 +3924,8 @@ static void qlt_handle_srr(struct scsi_qla_host *vha, } } else { ql_dbg(ql_dbg_tgt_mgt, vha, 0xf066, - "qla_target(%d): SRR for out data for cmd " - "without them (tag %d, SCSI status %d), " - "reject", vha->vp_idx, cmd->tag, - cmd->se_cmd.scsi_status); + "qla_target(%d): SRR for out data for cmd without them (tag %lld, SCSI status %d), reject", + vha->vp_idx, se_cmd->tag, cmd->se_cmd.scsi_status); goto out_reject; } break; @@ -4051,10 +4046,9 @@ restart: cmd->sg = se_cmd->t_data_sg; ql_dbg(ql_dbg_tgt_mgt, vha, 0xf02c, - "SRR cmd %p (se_cmd %p, tag %d, op %x), " - "sg_cnt=%d, offset=%d", cmd, &cmd->se_cmd, cmd->tag, - se_cmd->t_task_cdb ? se_cmd->t_task_cdb[0] : 0, - cmd->sg_cnt, cmd->offset); + "SRR cmd %p (se_cmd %p, tag %lld, op %x), sg_cnt=%d, offset=%d", + cmd, &cmd->se_cmd, se_cmd->tag, se_cmd->t_task_cdb ? + se_cmd->t_task_cdb[0] : 0, cmd->sg_cnt, cmd->offset); qlt_handle_srr(vha, sctio, imm); diff --git a/drivers/scsi/qla2xxx/qla_target.h b/drivers/scsi/qla2xxx/qla_target.h index 332086776dfe..985d76dd706b 100644 --- a/drivers/scsi/qla2xxx/qla_target.h +++ b/drivers/scsi/qla2xxx/qla_target.h @@ -924,7 +924,6 @@ struct qla_tgt_cmd { int sg_cnt; /* SG segments count */ int bufflen; /* cmd buffer length */ int offset; - uint32_t tag; uint32_t unpacked_lun; enum dma_data_direction dma_data_direction; uint32_t reset_count; diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index bd0f9eb67901..8e331220adda 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -421,19 +421,6 @@ static void tcm_qla2xxx_set_default_node_attrs(struct se_node_acl *nacl) return; } -static u32 tcm_qla2xxx_get_task_tag(struct se_cmd *se_cmd) -{ - struct qla_tgt_cmd *cmd; - - /* check for task mgmt cmd */ - if (se_cmd->se_cmd_flags & SCF_SCSI_TMR_CDB) - return 0xffffffff; - - cmd = container_of(se_cmd, struct qla_tgt_cmd, se_cmd); - - return cmd->tag; -} - static int tcm_qla2xxx_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -1865,7 +1852,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_ops = { .write_pending = tcm_qla2xxx_write_pending, .write_pending_status = tcm_qla2xxx_write_pending_status, .set_default_node_attributes = tcm_qla2xxx_set_default_node_attrs, - .get_task_tag = tcm_qla2xxx_get_task_tag, .get_cmd_state = tcm_qla2xxx_get_cmd_state, .queue_data_in = tcm_qla2xxx_queue_data_in, .queue_status = tcm_qla2xxx_queue_status, @@ -1910,7 +1896,6 @@ static const struct target_core_fabric_ops tcm_qla2xxx_npiv_ops = { .write_pending = tcm_qla2xxx_write_pending, .write_pending_status = tcm_qla2xxx_write_pending_status, .set_default_node_attributes = tcm_qla2xxx_set_default_node_attrs, - .get_task_tag = tcm_qla2xxx_get_task_tag, .get_cmd_state = tcm_qla2xxx_get_cmd_state, .queue_data_in = tcm_qla2xxx_queue_data_in, .queue_status = tcm_qla2xxx_queue_status, diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c index 866c167c0986..3c4431f71158 100644 --- a/drivers/target/iscsi/iscsi_target.c +++ b/drivers/target/iscsi/iscsi_target.c @@ -1008,6 +1008,8 @@ int iscsit_setup_scsi_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd, if (cmd->sense_reason) goto attach_cmd; + /* only used for printks or comparing with ->ref_task_tag */ + cmd->se_cmd.tag = (__force u32)cmd->init_task_tag; cmd->sense_reason = target_setup_cmd_from_cdb(&cmd->se_cmd, hdr->cdb); if (cmd->sense_reason) { if (cmd->sense_reason == TCM_OUT_OF_RESOURCES) { diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index bd8af8764f4b..aa4fc4d8e176 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -1692,14 +1692,6 @@ static char *iscsi_get_fabric_name(void) return "iSCSI"; } -static u32 iscsi_get_task_tag(struct se_cmd *se_cmd) -{ - struct iscsi_cmd *cmd = container_of(se_cmd, struct iscsi_cmd, se_cmd); - - /* only used for printks or comparism with ->ref_task_tag */ - return (__force u32)cmd->init_task_tag; -} - static int iscsi_get_cmd_state(struct se_cmd *se_cmd) { struct iscsi_cmd *cmd = container_of(se_cmd, struct iscsi_cmd, se_cmd); @@ -1938,7 +1930,6 @@ const struct target_core_fabric_ops iscsi_ops = { .write_pending = lio_write_pending, .write_pending_status = lio_write_pending_status, .set_default_node_attributes = lio_set_default_node_attributes, - .get_task_tag = iscsi_get_task_tag, .get_cmd_state = iscsi_get_cmd_state, .queue_data_in = lio_queue_data_in, .queue_status = lio_queue_status, diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index b788406977f6..07d3b52c88eb 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -165,6 +165,7 @@ static void tcm_loop_submission_work(struct work_struct *work) transfer_length = scsi_bufflen(sc); } + se_cmd->tag = tl_cmd->sc_cmd_tag; rc = target_submit_cmd_map_sgls(se_cmd, tl_nexus->se_sess, sc->cmnd, &tl_cmd->tl_sense_buf[0], tl_cmd->sc->device->lun, transfer_length, TCM_SIMPLE_TAG, @@ -597,14 +598,6 @@ static void tcm_loop_set_default_node_attributes(struct se_node_acl *se_acl) return; } -static u32 tcm_loop_get_task_tag(struct se_cmd *se_cmd) -{ - struct tcm_loop_cmd *tl_cmd = container_of(se_cmd, - struct tcm_loop_cmd, tl_se_cmd); - - return tl_cmd->sc_cmd_tag; -} - static int tcm_loop_get_cmd_state(struct se_cmd *se_cmd) { struct tcm_loop_cmd *tl_cmd = container_of(se_cmd, @@ -1259,7 +1252,6 @@ static const struct target_core_fabric_ops loop_ops = { .write_pending = tcm_loop_write_pending, .write_pending_status = tcm_loop_write_pending_status, .set_default_node_attributes = tcm_loop_set_default_node_attributes, - .get_task_tag = tcm_loop_get_task_tag, .get_cmd_state = tcm_loop_get_cmd_state, .queue_data_in = tcm_loop_queue_data_in, .queue_status = tcm_loop_queue_status, diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 89f172dc8678..2916a4023e71 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -1234,6 +1234,8 @@ static void sbp_handle_command(struct sbp_target_request *req) pr_debug("sbp_handle_command ORB:0x%llx unpacked_lun:%d data_len:%d data_dir:%d\n", req->orb_pointer, unpacked_lun, data_length, data_dir); + /* only used for printk until we do TMRs */ + req->se_cmd.tag = req->orb_pointer; if (target_submit_cmd(&req->se_cmd, sess->se_sess, req->cmd_buf, req->sense_buf, unpacked_lun, data_length, TCM_SIMPLE_TAG, data_dir, 0)) @@ -1768,15 +1770,6 @@ static void sbp_set_default_node_attrs(struct se_node_acl *nacl) return; } -static u32 sbp_get_task_tag(struct se_cmd *se_cmd) -{ - struct sbp_target_request *req = container_of(se_cmd, - struct sbp_target_request, se_cmd); - - /* only used for printk until we do TMRs */ - return (u32)req->orb_pointer; -} - static int sbp_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -2377,7 +2370,6 @@ static const struct target_core_fabric_ops sbp_ops = { .write_pending = sbp_write_pending, .write_pending_status = sbp_write_pending_status, .set_default_node_attributes = sbp_set_default_node_attrs, - .get_task_tag = sbp_get_task_tag, .get_cmd_state = sbp_get_cmd_state, .queue_data_in = sbp_queue_data_in, .queue_status = sbp_queue_status, diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c index 5e2649fc6919..fc598c084523 100644 --- a/drivers/target/target_core_configfs.c +++ b/drivers/target/target_core_configfs.c @@ -374,10 +374,6 @@ static int target_fabric_tf_ops_check(const struct target_core_fabric_ops *tfo) pr_err("Missing tfo->set_default_node_attributes()\n"); return -EINVAL; } - if (!tfo->get_task_tag) { - pr_err("Missing tfo->get_task_tag()\n"); - return -EINVAL; - } if (!tfo->get_cmd_state) { pr_err("Missing tfo->get_cmd_state()\n"); return -EINVAL; diff --git a/drivers/target/target_core_tmr.c b/drivers/target/target_core_tmr.c index b2e169fba3c6..393aca8bb3eb 100644 --- a/drivers/target/target_core_tmr.c +++ b/drivers/target/target_core_tmr.c @@ -117,7 +117,7 @@ void core_tmr_abort_task( { struct se_cmd *se_cmd; unsigned long flags; - int ref_tag; + u64 ref_tag; spin_lock_irqsave(&se_sess->sess_cmd_lock, flags); list_for_each_entry(se_cmd, &se_sess->sess_cmd_list, se_cmd_list) { @@ -129,16 +129,17 @@ void core_tmr_abort_task( if (se_cmd->se_cmd_flags & SCF_SCSI_TMR_CDB) continue; - ref_tag = se_cmd->se_tfo->get_task_tag(se_cmd); + ref_tag = se_cmd->tag; if (tmr->ref_task_tag != ref_tag) continue; - printk("ABORT_TASK: Found referenced %s task_tag: %u\n", + printk("ABORT_TASK: Found referenced %s task_tag: %llu\n", se_cmd->se_tfo->get_fabric_name(), ref_tag); spin_lock(&se_cmd->t_state_lock); if (se_cmd->transport_state & CMD_T_COMPLETE) { - printk("ABORT_TASK: ref_tag: %u already complete, skipping\n", ref_tag); + printk("ABORT_TASK: ref_tag: %llu already complete," + " skipping\n", ref_tag); spin_unlock(&se_cmd->t_state_lock); spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags); goto out; @@ -157,14 +158,14 @@ void core_tmr_abort_task( transport_cmd_finish_abort(se_cmd, true); printk("ABORT_TASK: Sending TMR_FUNCTION_COMPLETE for" - " ref_tag: %d\n", ref_tag); + " ref_tag: %llu\n", ref_tag); tmr->response = TMR_FUNCTION_COMPLETE; return; } spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags); out: - printk("ABORT_TASK: Sending TMR_TASK_DOES_NOT_EXIST for ref_tag: %d\n", + printk("ABORT_TASK: Sending TMR_TASK_DOES_NOT_EXIST for ref_tag: %lld\n", tmr->ref_task_tag); tmr->response = TMR_TASK_DOES_NOT_EXIST; } @@ -289,16 +290,16 @@ static void core_tmr_drain_state_list( list_del(&cmd->state_list); pr_debug("LUN_RESET: %s cmd: %p" - " ITT/CmdSN: 0x%08x/0x%08x, i_state: %d, t_state: %d" + " ITT/CmdSN: 0x%08llx/0x%08x, i_state: %d, t_state: %d" "cdb: 0x%02x\n", (preempt_and_abort_list) ? "Preempt" : "", cmd, - cmd->se_tfo->get_task_tag(cmd), 0, + cmd->tag, 0, cmd->se_tfo->get_cmd_state(cmd), cmd->t_state, cmd->t_task_cdb[0]); - pr_debug("LUN_RESET: ITT[0x%08x] - pr_res_key: 0x%016Lx" + pr_debug("LUN_RESET: ITT[0x%08llx] - pr_res_key: 0x%016Lx" " -- CMD_T_ACTIVE: %d" " CMD_T_STOP: %d CMD_T_SENT: %d\n", - cmd->se_tfo->get_task_tag(cmd), cmd->pr_res_key, + cmd->tag, cmd->pr_res_key, (cmd->transport_state & CMD_T_ACTIVE) != 0, (cmd->transport_state & CMD_T_STOP) != 0, (cmd->transport_state & CMD_T_SENT) != 0); diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c index 85b021e749e6..0d8662bb470e 100644 --- a/drivers/target/target_core_transport.c +++ b/drivers/target/target_core_transport.c @@ -600,9 +600,8 @@ static int transport_cmd_check_stop(struct se_cmd *cmd, bool remove_from_lists, * this command for frontend exceptions. */ if (cmd->transport_state & CMD_T_STOP) { - pr_debug("%s:%d CMD_T_STOP for ITT: 0x%08x\n", - __func__, __LINE__, - cmd->se_tfo->get_task_tag(cmd)); + pr_debug("%s:%d CMD_T_STOP for ITT: 0x%08llx\n", + __func__, __LINE__, cmd->tag); spin_unlock_irqrestore(&cmd->t_state_lock, flags); @@ -1155,6 +1154,8 @@ target_cmd_size_check(struct se_cmd *cmd, unsigned int size) /* * Used by fabric modules containing a local struct se_cmd within their * fabric dependent per I/O descriptor. + * + * Preserves the value of @cmd->tag. */ void transport_init_se_cmd( struct se_cmd *cmd, @@ -1380,6 +1381,8 @@ transport_generic_map_mem_to_cmd(struct se_cmd *cmd, struct scatterlist *sgl, * @sgl_prot: struct scatterlist memory protection information * @sgl_prot_count: scatterlist count for protection information * + * Task tags are supported if the caller has set @se_cmd->tag. + * * Returns non zero to signal active I/O shutdown failure. All other * setup exceptions will be returned as a SCSI CHECK_CONDITION response, * but still return zero here. @@ -1512,6 +1515,8 @@ EXPORT_SYMBOL(target_submit_cmd_map_sgls); * @data_dir: DMA data direction * @flags: flags for command submission from target_sc_flags_tables * + * Task tags are supported if the caller has set @se_cmd->tag. + * * Returns non zero to signal active I/O shutdown failure. All other * setup exceptions will be returned as a SCSI CHECK_CONDITION response, * but still return zero here. @@ -1639,9 +1644,8 @@ void transport_generic_request_failure(struct se_cmd *cmd, { int ret = 0; - pr_debug("-----[ Storage Engine Exception for cmd: %p ITT: 0x%08x" - " CDB: 0x%02x\n", cmd, cmd->se_tfo->get_task_tag(cmd), - cmd->t_task_cdb[0]); + pr_debug("-----[ Storage Engine Exception for cmd: %p ITT: 0x%08llx" + " CDB: 0x%02x\n", cmd, cmd->tag, cmd->t_task_cdb[0]); pr_debug("-----[ i_state: %d t_state: %d sense_reason: %d\n", cmd->se_tfo->get_cmd_state(cmd), cmd->t_state, sense_reason); @@ -1849,9 +1853,8 @@ void target_execute_cmd(struct se_cmd *cmd) */ spin_lock_irq(&cmd->t_state_lock); if (cmd->transport_state & CMD_T_STOP) { - pr_debug("%s:%d CMD_T_STOP for ITT: 0x%08x\n", - __func__, __LINE__, - cmd->se_tfo->get_task_tag(cmd)); + pr_debug("%s:%d CMD_T_STOP for ITT: 0x%08llx\n", + __func__, __LINE__, cmd->tag); spin_unlock_irq(&cmd->t_state_lock); complete_all(&cmd->t_transport_stop_comp); @@ -2658,10 +2661,8 @@ bool transport_wait_for_tasks(struct se_cmd *cmd) cmd->transport_state |= CMD_T_STOP; - pr_debug("wait_for_tasks: Stopping %p ITT: 0x%08x" - " i_state: %d, t_state: %d, CMD_T_STOP\n", - cmd, cmd->se_tfo->get_task_tag(cmd), - cmd->se_tfo->get_cmd_state(cmd), cmd->t_state); + pr_debug("wait_for_tasks: Stopping %p ITT: 0x%08llx i_state: %d, t_state: %d, CMD_T_STOP\n", + cmd, cmd->tag, cmd->se_tfo->get_cmd_state(cmd), cmd->t_state); spin_unlock_irqrestore(&cmd->t_state_lock, flags); @@ -2670,9 +2671,8 @@ bool transport_wait_for_tasks(struct se_cmd *cmd) spin_lock_irqsave(&cmd->t_state_lock, flags); cmd->transport_state &= ~(CMD_T_ACTIVE | CMD_T_STOP); - pr_debug("wait_for_tasks: Stopped wait_for_completion(" - "&cmd->t_transport_stop_comp) for ITT: 0x%08x\n", - cmd->se_tfo->get_task_tag(cmd)); + pr_debug("wait_for_tasks: Stopped wait_for_completion(&cmd->t_transport_stop_comp) for ITT: 0x%08llx\n", + cmd->tag); spin_unlock_irqrestore(&cmd->t_state_lock, flags); @@ -2974,8 +2974,8 @@ int transport_check_aborted_status(struct se_cmd *cmd, int send_status) if (!send_status || !(cmd->se_cmd_flags & SCF_SEND_DELAYED_TAS)) return 1; - pr_debug("Sending delayed SAM_STAT_TASK_ABORTED status for CDB: 0x%02x ITT: 0x%08x\n", - cmd->t_task_cdb[0], cmd->se_tfo->get_task_tag(cmd)); + pr_debug("Sending delayed SAM_STAT_TASK_ABORTED status for CDB: 0x%02x ITT: 0x%08llx\n", + cmd->t_task_cdb[0], cmd->tag); cmd->se_cmd_flags &= ~SCF_SEND_DELAYED_TAS; cmd->scsi_status = SAM_STAT_TASK_ABORTED; @@ -3014,9 +3014,8 @@ void transport_send_task_abort(struct se_cmd *cmd) transport_lun_remove_cmd(cmd); - pr_debug("Setting SAM_STAT_TASK_ABORTED status for CDB: 0x%02x," - " ITT: 0x%08x\n", cmd->t_task_cdb[0], - cmd->se_tfo->get_task_tag(cmd)); + pr_debug("Setting SAM_STAT_TASK_ABORTED status for CDB: 0x%02x, ITT: 0x%08llx\n", + cmd->t_task_cdb[0], cmd->tag); trace_target_cmd_complete(cmd); cmd->se_tfo->queue_status(cmd); diff --git a/drivers/target/target_core_xcopy.c b/drivers/target/target_core_xcopy.c index 8fd680ac941b..5545619d3045 100644 --- a/drivers/target/target_core_xcopy.c +++ b/drivers/target/target_core_xcopy.c @@ -359,11 +359,6 @@ static char *xcopy_pt_get_fabric_name(void) return "xcopy-pt"; } -static u32 xcopy_pt_get_tag(struct se_cmd *se_cmd) -{ - return 0; -} - static int xcopy_pt_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -424,7 +419,6 @@ static int xcopy_pt_queue_status(struct se_cmd *se_cmd) static const struct target_core_fabric_ops xcopy_pt_tfo = { .get_fabric_name = xcopy_pt_get_fabric_name, - .get_task_tag = xcopy_pt_get_tag, .get_cmd_state = xcopy_pt_get_cmd_state, .release_cmd = xcopy_pt_release_cmd, .check_stop_free = xcopy_pt_check_stop_free, @@ -575,6 +569,7 @@ static int target_xcopy_setup_pt_cmd( xpt_cmd->xcopy_op = xop; target_xcopy_setup_pt_port(xpt_cmd, xop, remote_port); + cmd->tag = 0; sense_rc = target_setup_cmd_from_cdb(cmd, cdb); if (sense_rc) { ret = -EINVAL; diff --git a/drivers/target/tcm_fc/tcm_fc.h b/drivers/target/tcm_fc/tcm_fc.h index 4ceaeb9a4b93..39909dadef3e 100644 --- a/drivers/target/tcm_fc/tcm_fc.h +++ b/drivers/target/tcm_fc/tcm_fc.h @@ -157,7 +157,6 @@ int ft_queue_status(struct se_cmd *); int ft_queue_data_in(struct se_cmd *); int ft_write_pending(struct se_cmd *); int ft_write_pending_status(struct se_cmd *); -u32 ft_get_task_tag(struct se_cmd *); int ft_get_cmd_state(struct se_cmd *); void ft_queue_tm_resp(struct se_cmd *); void ft_aborted_task(struct se_cmd *); diff --git a/drivers/target/tcm_fc/tfc_cmd.c b/drivers/target/tcm_fc/tfc_cmd.c index edcafa4490c0..a8fe6ed5262f 100644 --- a/drivers/target/tcm_fc/tfc_cmd.c +++ b/drivers/target/tcm_fc/tfc_cmd.c @@ -247,15 +247,6 @@ int ft_write_pending(struct se_cmd *se_cmd) return 0; } -u32 ft_get_task_tag(struct se_cmd *se_cmd) -{ - struct ft_cmd *cmd = container_of(se_cmd, struct ft_cmd, se_cmd); - - if (cmd->aborted) - return ~0; - return fc_seq_exch(cmd->seq)->rxid; -} - int ft_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -568,6 +559,7 @@ static void ft_send_work(struct work_struct *work) } fc_seq_exch(cmd->seq)->lp->tt.seq_set_resp(cmd->seq, ft_recv_seq, cmd); + cmd->se_cmd.tag = fc_seq_exch(cmd->seq)->rxid; /* * Use a single se_cmd->cmd_kref as we expect to release se_cmd * directly from ft_check_stop_free callback in response path. diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index 6ad7404b7dd1..f0821967f0a1 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -468,7 +468,6 @@ static const struct target_core_fabric_ops ft_fabric_ops = { .write_pending = ft_write_pending, .write_pending_status = ft_write_pending_status, .set_default_node_attributes = ft_set_default_node_attr, - .get_task_tag = ft_get_task_tag, .get_cmd_state = ft_get_cmd_state, .queue_data_in = ft_queue_data_in, .queue_status = ft_queue_status, diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index 77cdbb56e1d5..a000d89dc78a 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -1112,6 +1112,7 @@ static int usbg_submit_command(struct f_uas *fu, memcpy(cmd->cmd_buf, cmd_iu->cdb, cmd_len); cmd->tag = be16_to_cpup(&cmd_iu->tag); + cmd->se_cmd.tag = cmd->tag; if (fu->flags & USBG_USE_STREAMS) { if (cmd->tag > UASP_SS_EP_COMP_NUM_STREAMS) goto err; @@ -1245,6 +1246,7 @@ static int bot_submit_command(struct f_uas *fu, cmd->unpacked_lun = cbw->Lun; cmd->is_read = cbw->Flags & US_BULK_FLAG_IN ? 1 : 0; cmd->data_len = le32_to_cpu(cbw->DataTransferLength); + cmd->se_cmd.tag = le32_to_cpu(cmd->bot_tag); INIT_WORK(&cmd->work, bot_cmd_work); ret = queue_work(tpg->workqueue, &cmd->work); @@ -1340,18 +1342,6 @@ static void usbg_set_default_node_attrs(struct se_node_acl *nacl) return; } -static u32 usbg_get_task_tag(struct se_cmd *se_cmd) -{ - struct usbg_cmd *cmd = container_of(se_cmd, struct usbg_cmd, - se_cmd); - struct f_uas *fu = cmd->fu; - - if (fu->flags & USBG_IS_BOT) - return le32_to_cpu(cmd->bot_tag); - else - return cmd->tag; -} - static int usbg_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -1739,7 +1729,6 @@ static const struct target_core_fabric_ops usbg_ops = { .write_pending = usbg_send_write_request, .write_pending_status = usbg_write_pending_status, .set_default_node_attributes = usbg_set_default_node_attrs, - .get_task_tag = usbg_get_task_tag, .get_cmd_state = usbg_get_cmd_state, .queue_data_in = usbg_send_read_response, .queue_status = usbg_send_status_response, diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index db9f4b474214..4a003948b07f 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -369,11 +369,6 @@ static void vhost_scsi_set_default_node_attrs(struct se_node_acl *nacl) return; } -static u32 vhost_scsi_get_task_tag(struct se_cmd *se_cmd) -{ - return 0; -} - static int vhost_scsi_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -818,6 +813,7 @@ static void vhost_scsi_submission_work(struct work_struct *work) } tv_nexus = cmd->tvc_nexus; + se_cmd->tag = 0; rc = target_submit_cmd_map_sgls(se_cmd, tv_nexus->tvn_se_sess, cmd->tvc_cdb, &cmd->tvc_sense_buf[0], cmd->tvc_lun, cmd->tvc_exp_data_len, @@ -2148,7 +2144,6 @@ static struct target_core_fabric_ops vhost_scsi_ops = { .write_pending = vhost_scsi_write_pending, .write_pending_status = vhost_scsi_write_pending_status, .set_default_node_attributes = vhost_scsi_set_default_node_attrs, - .get_task_tag = vhost_scsi_get_task_tag, .get_cmd_state = vhost_scsi_get_cmd_state, .queue_data_in = vhost_scsi_queue_data_in, .queue_status = vhost_scsi_queue_status, diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index 10c71a5616fa..ea929baf7ad0 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -400,6 +400,7 @@ static void scsiback_cmd_exec(struct vscsibk_pend *pending_req) memset(se_cmd, 0, sizeof(*se_cmd)); scsiback_get(pending_req->info); + se_cmd->tag = pending_req->rqid; rc = target_submit_cmd_map_sgls(se_cmd, sess, pending_req->cmnd, pending_req->sense_buffer, pending_req->v2p->lun, pending_req->data_len, 0, @@ -1394,14 +1395,6 @@ static void scsiback_set_default_node_attrs(struct se_node_acl *nacl) { } -static u32 scsiback_get_task_tag(struct se_cmd *se_cmd) -{ - struct vscsibk_pend *pending_req = container_of(se_cmd, - struct vscsibk_pend, se_cmd); - - return pending_req->rqid; -} - static int scsiback_get_cmd_state(struct se_cmd *se_cmd) { return 0; @@ -1833,7 +1826,6 @@ static const struct target_core_fabric_ops scsiback_ops = { .write_pending = scsiback_write_pending, .write_pending_status = scsiback_write_pending_status, .set_default_node_attributes = scsiback_set_default_node_attrs, - .get_task_tag = scsiback_get_task_tag, .get_cmd_state = scsiback_get_cmd_state, .queue_data_in = scsiback_queue_data_in, .queue_status = scsiback_queue_status, diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h index c462fb0a47f4..042a73464966 100644 --- a/include/target/target_core_base.h +++ b/include/target/target_core_base.h @@ -420,7 +420,7 @@ struct se_tmr_req { u8 response; int call_transport; /* Reference to ITT that Task Mgmt should be performed */ - u32 ref_task_tag; + u64 ref_task_tag; void *fabric_tmr_ptr; struct se_cmd *task_cmd; struct se_device *tmr_dev; @@ -473,6 +473,7 @@ struct se_cmd { u8 scsi_asc; u8 scsi_ascq; u16 scsi_sense_length; + u64 tag; /* SAM command identifier aka task tag */ /* Delay for ALUA Active/NonOptimized state access in milliseconds */ int alua_nonop_delay; /* See include/linux/dma-mapping.h */ diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h index a420f434c6c5..f64d493f888b 100644 --- a/include/target/target_core_fabric.h +++ b/include/target/target_core_fabric.h @@ -53,7 +53,6 @@ struct target_core_fabric_ops { int (*write_pending)(struct se_cmd *); int (*write_pending_status)(struct se_cmd *); void (*set_default_node_attributes)(struct se_node_acl *); - u32 (*get_task_tag)(struct se_cmd *); int (*get_cmd_state)(struct se_cmd *); int (*queue_data_in)(struct se_cmd *); int (*queue_status)(struct se_cmd *); -- cgit v1.2.3 From 7ad34a93675e9c5a65711f83c518871317adc2ee Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Sun, 3 May 2015 08:50:56 +0200 Subject: target: target_core_configfs.h is not needed in fabric drivers Signed-off-by: Christoph Hellwig Signed-off-by: Nicholas Bellinger --- Documentation/target/tcm_mod_builder.py | 2 -- drivers/infiniband/ulp/srpt/ib_srpt.c | 1 - drivers/scsi/qla2xxx/tcm_qla2xxx.c | 1 - drivers/target/iscsi/iscsi_target.c | 1 - drivers/target/iscsi/iscsi_target_configfs.c | 1 - drivers/target/iscsi/iscsi_target_tpg.c | 1 - drivers/target/iscsi/iscsi_target_util.c | 1 - drivers/target/loopback/tcm_loop.c | 1 - drivers/target/sbp/sbp_target.c | 1 - drivers/target/target_core_alua.c | 1 - drivers/target/target_core_fabric_lib.c | 1 - drivers/target/target_core_hba.c | 1 - drivers/target/target_core_pr.c | 1 - drivers/target/target_core_stat.c | 1 - drivers/target/target_core_tmr.c | 1 - drivers/target/target_core_transport.c | 1 - drivers/target/target_core_ua.c | 1 - drivers/target/target_core_xcopy.c | 1 - drivers/target/tcm_fc/tfc_cmd.c | 1 - drivers/target/tcm_fc/tfc_conf.c | 1 - drivers/target/tcm_fc/tfc_io.c | 1 - drivers/target/tcm_fc/tfc_sess.c | 1 - drivers/usb/gadget/legacy/tcm_usb_gadget.c | 1 - drivers/vhost/scsi.c | 1 - drivers/xen/xen-scsiback.c | 1 - 25 files changed, 26 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 71e1f5863310..c70b193ec110 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -203,7 +203,6 @@ def tcm_mod_build_configfs(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "#include \n" buf += "#include \n" buf += "#include \n" - buf += "#include \n" buf += "#include \n\n" buf += "#include \"" + fabric_mod_name + "_base.h\"\n" buf += "#include \"" + fabric_mod_name + "_fabric.h\"\n\n" @@ -417,7 +416,6 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "#include \n\n" buf += "#include \n" buf += "#include \n" - buf += "#include \n\n" buf += "#include \"" + fabric_mod_name + "_base.h\"\n" buf += "#include \"" + fabric_mod_name + "_fabric.h\"\n\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index f21a5f6bf858..dbad5c67a294 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -46,7 +46,6 @@ #include #include #include -#include #include "ib_srpt.h" /* Name of this kernel module. */ diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c index 8e331220adda..b505e5e7c987 100644 --- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c +++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c @@ -43,7 +43,6 @@ #include #include #include -#include #include #include "qla_def.h" diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c index 3c4431f71158..1817922fe0f1 100644 --- a/drivers/target/iscsi/iscsi_target.c +++ b/drivers/target/iscsi/iscsi_target.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "iscsi_target_parameters.h" diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index aa4fc4d8e176..523ae556e22c 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/drivers/target/iscsi/iscsi_target_tpg.c b/drivers/target/iscsi/iscsi_target_tpg.c index dcb7ede1d4aa..d4ac31fc2acd 100644 --- a/drivers/target/iscsi/iscsi_target_tpg.c +++ b/drivers/target/iscsi/iscsi_target_tpg.c @@ -18,7 +18,6 @@ #include #include -#include #include #include "iscsi_target_erl0.h" diff --git a/drivers/target/iscsi/iscsi_target_util.c b/drivers/target/iscsi/iscsi_target_util.c index c1582e88191e..a2bff0702eb2 100644 --- a/drivers/target/iscsi/iscsi_target_util.c +++ b/drivers/target/iscsi/iscsi_target_util.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index 07d3b52c88eb..b0c17614493e 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -35,7 +35,6 @@ #include #include #include -#include #include "tcm_loop.h" diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 2916a4023e71..5d7755edc668 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include diff --git a/drivers/target/target_core_alua.c b/drivers/target/target_core_alua.c index 4f8d4d459aa4..b590f153a7b6 100644 --- a/drivers/target/target_core_alua.c +++ b/drivers/target/target_core_alua.c @@ -35,7 +35,6 @@ #include #include #include -#include #include "target_core_internal.h" #include "target_core_alua.h" diff --git a/drivers/target/target_core_fabric_lib.c b/drivers/target/target_core_fabric_lib.c index 89720b2f37c2..92346f23ab45 100644 --- a/drivers/target/target_core_fabric_lib.c +++ b/drivers/target/target_core_fabric_lib.c @@ -39,7 +39,6 @@ #include #include -#include #include "target_core_internal.h" #include "target_core_pr.h" diff --git a/drivers/target/target_core_hba.c b/drivers/target/target_core_hba.c index ff95f95dcd13..e6e496ff9546 100644 --- a/drivers/target/target_core_hba.c +++ b/drivers/target/target_core_hba.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "target_core_internal.h" diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c index d396b3b87025..a4b9a0dd50cd 100644 --- a/drivers/target/target_core_pr.c +++ b/drivers/target/target_core_pr.c @@ -35,7 +35,6 @@ #include #include #include -#include #include "target_core_internal.h" #include "target_core_pr.h" diff --git a/drivers/target/target_core_stat.c b/drivers/target/target_core_stat.c index 03538994d2f7..64efee2fba52 100644 --- a/drivers/target/target_core_stat.c +++ b/drivers/target/target_core_stat.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include "target_core_internal.h" diff --git a/drivers/target/target_core_tmr.c b/drivers/target/target_core_tmr.c index 393aca8bb3eb..60ef1043242e 100644 --- a/drivers/target/target_core_tmr.c +++ b/drivers/target/target_core_tmr.c @@ -33,7 +33,6 @@ #include #include #include -#include #include "target_core_internal.h" #include "target_core_alua.h" diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c index 0d8662bb470e..fc460f1b0b75 100644 --- a/drivers/target/target_core_transport.c +++ b/drivers/target/target_core_transport.c @@ -44,7 +44,6 @@ #include #include #include -#include #include "target_core_internal.h" #include "target_core_alua.h" diff --git a/drivers/target/target_core_ua.c b/drivers/target/target_core_ua.c index 1738b1646988..a0bf0d1a3df7 100644 --- a/drivers/target/target_core_ua.c +++ b/drivers/target/target_core_ua.c @@ -30,7 +30,6 @@ #include #include -#include #include "target_core_internal.h" #include "target_core_alua.h" diff --git a/drivers/target/target_core_xcopy.c b/drivers/target/target_core_xcopy.c index 5545619d3045..3556a9dcee46 100644 --- a/drivers/target/target_core_xcopy.c +++ b/drivers/target/target_core_xcopy.c @@ -32,7 +32,6 @@ #include #include #include -#include #include "target_core_internal.h" #include "target_core_pr.h" diff --git a/drivers/target/tcm_fc/tfc_cmd.c b/drivers/target/tcm_fc/tfc_cmd.c index a8fe6ed5262f..d62282fb2b5b 100644 --- a/drivers/target/tcm_fc/tfc_cmd.c +++ b/drivers/target/tcm_fc/tfc_cmd.c @@ -40,7 +40,6 @@ #include #include -#include #include #include "tcm_fc.h" diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index f0821967f0a1..ee5653139417 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -43,7 +43,6 @@ #include #include #include -#include #include #include "tcm_fc.h" diff --git a/drivers/target/tcm_fc/tfc_io.c b/drivers/target/tcm_fc/tfc_io.c index 583e755d8091..401ce7f27863 100644 --- a/drivers/target/tcm_fc/tfc_io.c +++ b/drivers/target/tcm_fc/tfc_io.c @@ -48,7 +48,6 @@ #include #include -#include #include #include "tcm_fc.h" diff --git a/drivers/target/tcm_fc/tfc_sess.c b/drivers/target/tcm_fc/tfc_sess.c index ccee7e332a4d..96a2273667ce 100644 --- a/drivers/target/tcm_fc/tfc_sess.c +++ b/drivers/target/tcm_fc/tfc_sess.c @@ -40,7 +40,6 @@ #include #include -#include #include #include "tcm_fc.h" diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index a000d89dc78a..16b9a16678fe 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 4a003948b07f..dcd228b59ded 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index ea929baf7ad0..edd0379c06b9 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -56,7 +56,6 @@ #include #include -#include #include #include -- cgit v1.2.3 From 4d66ea091a4dcc39bae70f1bb2148890da2c8ce9 Mon Sep 17 00:00:00 2001 From: Fanael Linithien Date: Mon, 1 Jun 2015 07:15:38 +1000 Subject: xfs: fix kernel version in docs Linux v3.20 was released as v4.0. Signed-off-by: Fanael Linithien Reviewed-by: Dave Chinner Signed-off-by: Dave Chinner --- Documentation/filesystems/xfs.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/xfs.txt b/Documentation/filesystems/xfs.txt index 5a5a05582b58..8146e9fd5ffc 100644 --- a/Documentation/filesystems/xfs.txt +++ b/Documentation/filesystems/xfs.txt @@ -236,10 +236,10 @@ Removed Mount Options Name Removed ---- ------- - delaylog/nodelaylog v3.20 - ihashsize v3.20 - irixsgid v3.20 - osyncisdsync/osyncisosync v3.20 + delaylog/nodelaylog v4.0 + ihashsize v4.0 + irixsgid v4.0 + osyncisdsync/osyncisosync v4.0 sysctls @@ -346,5 +346,5 @@ Removed Sysctls Name Removed ---- ------- - fs.xfs.xfsbufd_centisec v3.20 - fs.xfs.age_buffer_centisecs v3.20 + fs.xfs.xfsbufd_centisec v4.0 + fs.xfs.age_buffer_centisecs v4.0 -- cgit v1.2.3 From 8f4a91202203624cbd8fe565cbdd5c876b652a5d Mon Sep 17 00:00:00 2001 From: Rama Kiran Kumar Indrakanti Date: Mon, 25 May 2015 11:51:10 +0530 Subject: sc16is7xx: spi interface documentation Updated the documentation for spi interface. Signed-off-by: Rama Kiran Kumar Indrakanti Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/nxp,sc16is7xx.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt index 246c795668dc..fbfe53635a3a 100644 --- a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt +++ b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt @@ -1,4 +1,5 @@ * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART) +* i2c as bus Required properties: - compatible: Should be one of the following: @@ -31,3 +32,39 @@ Example: gpio-controller; #gpio-cells = <2>; }; + +* spi as bus + +Required properties: +- compatible: Should be one of the following: + - "nxp,sc16is740" for NXP SC16IS740, + - "nxp,sc16is741" for NXP SC16IS741, + - "nxp,sc16is750" for NXP SC16IS750, + - "nxp,sc16is752" for NXP SC16IS752, + - "nxp,sc16is760" for NXP SC16IS760, + - "nxp,sc16is762" for NXP SC16IS762. +- reg: SPI chip select number. +- interrupt-parent: The phandle for the interrupt controller that + services interrupts for this IC. +- interrupts: Specifies the interrupt source of the parent interrupt + controller. The format of the interrupt specifier depends on the + parent interrupt controller. +- clocks: phandle to the IC source clock. + +Optional properties: +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be two. The first cell is the GPIO number and + the second cell is used to specify the GPIO polarity: + 0 = active high, + 1 = active low. + +Example: + sc16is750: sc16is750@0 { + compatible = "nxp,sc16is750"; + reg = <0>; + clocks = <&clk20m>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; -- cgit v1.2.3 From 6e63be3fee141cc6d122f648b524a66160dbe6aa Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Mon, 25 May 2015 06:54:28 +0300 Subject: serial: earlycon: Add support for big-endian MMIO accesses Support command line parameters of the form: earlycon=,io|mmio|mmio32|mmio32be,, This commit seem to be needed even after commit: serial: 8250: Add support for big-endian MMIO accesses c627f2ceb692e8a9358b64ac2d139314e7bb0d17 Signed-off-by: Noam Camus Signed-off-by: Greg Kroah-Hartman --- Documentation/kernel-parameters.txt | 9 +++++---- drivers/tty/serial/earlycon.c | 9 ++++++--- drivers/tty/serial/serial_core.c | 7 +++++-- 3 files changed, 16 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..55bb093a08a3 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -959,14 +959,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. uart[8250],io,[,options] uart[8250],mmio,[,options] uart[8250],mmio32,[,options] + uart[8250],mmio32be,[,options] uart[8250],0x[,options] Start an early, polled-mode console on the 8250/16550 UART at the specified I/O port or MMIO address. MMIO inter-register address stride is either 8-bit - (mmio) or 32-bit (mmio32). - If none of [io|mmio|mmio32], is assumed to be - equivalent to 'mmio'. 'options' are specified in the - same format described for "console=ttyS"; if + (mmio) or 32-bit (mmio32 or mmio32be). + If none of [io|mmio|mmio32|mmio32be], is assumed + to be equivalent to 'mmio'. 'options' are specified + in the same format described for "console=ttyS"; if unspecified, the h/w is not initialized. pl011, diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c index 6dc471e30e79..f09636083426 100644 --- a/drivers/tty/serial/earlycon.c +++ b/drivers/tty/serial/earlycon.c @@ -72,6 +72,7 @@ static int __init parse_options(struct earlycon_device *device, char *options) switch (port->iotype) { case UPIO_MEM32: + case UPIO_MEM32BE: port->regshift = 2; /* fall-through */ case UPIO_MEM: port->mapbase = addr; @@ -90,9 +91,11 @@ static int __init parse_options(struct earlycon_device *device, char *options) strlcpy(device->options, options, length); } - if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM32) + if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM32 || + port->iotype == UPIO_MEM32BE) pr_info("Early serial console at MMIO%s 0x%llx (options '%s')\n", - (port->iotype == UPIO_MEM32) ? "32" : "", + (port->iotype == UPIO_MEM) ? "" : + (port->iotype == UPIO_MEM32) ? "32" : "32be", (unsigned long long)port->mapbase, device->options); else @@ -133,7 +136,7 @@ static int __init register_earlycon(char *buf, const struct earlycon_id *match) * * Registers the earlycon console matching the earlycon specified * in the param string @buf. Acceptable param strings are of the form - * ,io|mmio|mmio32,, + * ,io|mmio|mmio32|mmio32be,, * ,0x, * , * diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index eec067d8eedb..860e59fd6ef4 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c @@ -1814,8 +1814,8 @@ uart_get_console(struct uart_port *ports, int nr, struct console *co) * @options: ptr for field; NULL if not present (out) * * Decodes earlycon kernel command line parameters of the form - * earlycon=,io|mmio|mmio32,, - * console=,io|mmio|mmio32,, + * earlycon=,io|mmio|mmio32|mmio32be,, + * console=,io|mmio|mmio32|mmio32be,, * * The optional form * earlycon=,0x, @@ -1833,6 +1833,9 @@ int uart_parse_earlycon(char *p, unsigned char *iotype, unsigned long *addr, } else if (strncmp(p, "mmio32,", 7) == 0) { *iotype = UPIO_MEM32; p += 7; + } else if (strncmp(p, "mmio32be,", 9) == 0) { + *iotype = UPIO_MEM32BE; + p += 9; } else if (strncmp(p, "io,", 3) == 0) { *iotype = UPIO_PORT; p += 3; -- cgit v1.2.3 From a7a215283703231bcde0740710569f6c0e39ac53 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Sat, 30 May 2015 23:14:45 +0200 Subject: doc: dt: add documentation for nxp,lpc1850-uart Add device tree binding documentation for nxp,lpc1850-uart. Signed-off-by: Joachim Eastwood Signed-off-by: Greg Kroah-Hartman --- .../bindings/serial/nxp,lpc1850-uart.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt b/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt new file mode 100644 index 000000000000..04e23e63ee4f --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt @@ -0,0 +1,28 @@ +* NXP LPC1850 UART + +Required properties: +- compatible : "nxp,lpc1850-uart", "ns16550a". +- reg : offset and length of the register set for the device. +- interrupts : should contain uart interrupt. +- clocks : phandle to the input clocks. +- clock-names : required elements: "uartclk", "reg". + +Optional properties: +- dmas : Two or more DMA channel specifiers following the + convention outlined in bindings/dma/dma.txt +- dma-names : Names for the dma channels, if present. There must + be at least one channel named "tx" for transmit + and named "rx" for receive. + +Since it's also possible to also use the of_serial.c driver all +parameters from 8250.txt also apply but are optional. + +Example: +uart0: serial@40081000 { + compatible = "nxp,lpc1850-uart", "ns16550a"; + reg = <0x40081000 0x1000>; + reg-shift = <2>; + interrupts = <24>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; + clock-names = "uartclk", "reg"; +}; -- cgit v1.2.3 From 976cf2056ccf1be1759f8c122d194c117c879e11 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 14 May 2015 14:40:04 +0200 Subject: i2c: slave: docs: be more precise about the prerequsites There was some confusion what was needed to utilize the slave support, so let's be more precise about this. Add an introductory paragraph to the development section while we are here. Signed-off-by: Wolfram Sang Acked-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang --- Documentation/i2c/slave-interface | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/i2c/slave-interface b/Documentation/i2c/slave-interface index 389bb5d61854..02b086510b6c 100644 --- a/Documentation/i2c/slave-interface +++ b/Documentation/i2c/slave-interface @@ -3,16 +3,16 @@ Linux I2C slave interface description by Wolfram Sang in 2014-15 -Linux can also be an I2C slave in case I2C controllers have slave support. -Besides this HW requirement, one also needs a software backend providing the -actual functionality. An example for this is the slave-eeprom driver, which -acts as a dual memory driver. While another I2C master on the bus can access it -like a regular EEPROM, the Linux I2C slave can access the content via sysfs and -retrieve/provide information as needed. The software backend driver and the I2C -bus driver communicate via events. Here is a small graph visualizing the data -flow and the means by which data is transported. The dotted line marks only one -example. The backend could also use e.g. a character device, be in-kernel -only, or something completely different: +Linux can also be an I2C slave if the I2C controller in use has slave +functionality. For that to work, one needs slave support in the bus driver plus +a hardware independent software backend providing the actual functionality. An +example for the latter is the slave-eeprom driver, which acts as a dual memory +driver. While another I2C master on the bus can access it like a regular +EEPROM, the Linux I2C slave can access the content via sysfs and handle data as +needed. The backend driver and the I2C bus driver communicate via events. Here +is a small graph visualizing the data flow and the means by which data is +transported. The dotted line marks only one example. The backend could also +use a character device, be in-kernel only, or something completely different: e.g. sysfs I2C slave events I/O registers @@ -43,6 +43,11 @@ behaviour and setup. Developer manual ================ +First, the events which are used by the bus driver and the backend will be +described in detail. After that, some implementation hints for extending bus +drivers and writing backends will be given. + + I2C slave events ---------------- -- cgit v1.2.3 From ce38815d39eac9c73d37dd4b0039c87f15dcbe18 Mon Sep 17 00:00:00 2001 From: Xudong Chen Date: Thu, 21 May 2015 16:53:28 +0800 Subject: I2C: mediatek: Add driver for MediaTek I2C controller The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by: Xudong Chen Signed-off-by: Liguo Zhang Signed-off-by: Eddie Huang Acked-by: Sascha Hauer Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++ drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-mt65xx.c | 686 +++++++++++++++++++++ 4 files changed, 737 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt create mode 100644 drivers/i2c/busses/i2c-mt65xx.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt new file mode 100644 index 000000000000..0ce6fa3242f0 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt @@ -0,0 +1,41 @@ +* Mediatek's I2C controller + +The Mediatek's I2C controller is used to interface with I2C devices. + +Required properties: + - compatible: value should be either of the following. + (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c. + (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c. + (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c. + (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c. + (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c. + - reg: physical base address of the controller and dma base, length of memory + mapped region. + - interrupts: interrupt number to the cpu. + - clock-div: the fixed value for frequency divider of clock source in i2c + module. Each IC may be different. + - clocks: clock name from clock manager + - clock-names: Must include "main" and "dma", if enable have-pmic need include + "pmic" extra. + +Optional properties: + - clock-frequency: Frequency in Hz of the bus when transfer, the default value + is 100000. + - mediatek,have-pmic: platform can control i2c form special pmic side. + Only mt6589 and mt8135 support this feature. + - mediatek,use-push-pull: IO config use push-pull mode. + +Example: + + i2c0: i2c@1100d000 { + compatible = "mediatek,mt6577-i2c"; + reg = <0x1100d000 0x70>, + <0x11000300 0x80>; + interrupts = ; + clock-frequency = <400000>; + mediatek,have-pmic; + clock-div = <16>; + clocks = <&i2c0_ck>, <&ap_dma_ck>; + clock-names = "main", "dma"; + }; + diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 1d759c3767e7..8a639dce5173 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -620,6 +620,15 @@ config I2C_MPC This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MT65XX + tristate "MediaTek I2C adapter" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + This selects the MediaTek(R) Integrated Inter Circuit bus driver + for MT65xx and MT81xx. + If you want to use MediaTek(R) I2C interface, say Y or M here. + If unsure, say N. + config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" depends on MV64X60 || PLAT_ORION || ARCH_SUNXI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index d8093022ee4c..65995423c680 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o obj-$(CONFIG_I2C_MESON) += i2c-meson.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c new file mode 100644 index 000000000000..b1d2d7cc6db0 --- /dev/null +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -0,0 +1,686 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Xudong Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define I2C_HS_NACKERR (1 << 2) +#define I2C_ACKERR (1 << 1) +#define I2C_TRANSAC_COMP (1 << 0) +#define I2C_TRANSAC_START (1 << 0) +#define I2C_DCM_DISABLE 0x0000 +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 +#define I2C_IO_CONFIG_PUSH_PULL 0x0000 +#define I2C_SOFT_RST 0x0001 +#define I2C_FIFO_ADDR_CLR 0x0001 +#define I2C_DELAY_LEN 0x0002 +#define I2C_ST_START_CON 0x8001 +#define I2C_FS_START_CON 0x1800 +#define I2C_TIME_CLR_VALUE 0x0000 +#define I2C_TIME_DEFAULT_VALUE 0x0003 +#define I2C_FS_TIME_INIT_VALUE 0x1303 +#define I2C_WRRD_TRANAC_VALUE 0x0002 +#define I2C_RD_TRANAC_VALUE 0x0001 + +#define I2C_DMA_CON_TX 0x0000 +#define I2C_DMA_CON_RX 0x0001 +#define I2C_DMA_START_EN 0x0001 +#define I2C_DMA_INT_FLAG_NONE 0x0000 +#define I2C_DMA_CLR_FLAG 0x0000 + +#define I2C_DEFAULT_SPEED 100000 /* hz */ +#define MAX_FS_MODE_SPEED 400000 +#define MAX_HS_MODE_SPEED 3400000 +#define MAX_SAMPLE_CNT_DIV 8 +#define MAX_STEP_CNT_DIV 64 +#define MAX_HS_STEP_CNT_DIV 8 + +#define I2C_CONTROL_RS (0x1 << 1) +#define I2C_CONTROL_DMA_EN (0x1 << 2) +#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) +#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) +#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) +#define I2C_CONTROL_WRAPPER (0x1 << 0) + +#define I2C_DRV_NAME "i2c-mt65xx" + +enum DMA_REGS_OFFSET { + OFFSET_INT_FLAG = 0x0, + OFFSET_INT_EN = 0x04, + OFFSET_EN = 0x08, + OFFSET_CON = 0x18, + OFFSET_TX_MEM_ADDR = 0x1c, + OFFSET_RX_MEM_ADDR = 0x20, + OFFSET_TX_LEN = 0x24, + OFFSET_RX_LEN = 0x28, +}; + +enum i2c_trans_st_rs { + I2C_TRANS_STOP = 0, + I2C_TRANS_REPEATED_START, +}; + +enum mtk_trans_op { + I2C_MASTER_WR = 1, + I2C_MASTER_RD, + I2C_MASTER_WRRD, +}; + +enum I2C_REGS_OFFSET { + OFFSET_DATA_PORT = 0x0, + OFFSET_SLAVE_ADDR = 0x04, + OFFSET_INTR_MASK = 0x08, + OFFSET_INTR_STAT = 0x0c, + OFFSET_CONTROL = 0x10, + OFFSET_TRANSFER_LEN = 0x14, + OFFSET_TRANSAC_LEN = 0x18, + OFFSET_DELAY_LEN = 0x1c, + OFFSET_TIMING = 0x20, + OFFSET_START = 0x24, + OFFSET_EXT_CONF = 0x28, + OFFSET_FIFO_STAT = 0x30, + OFFSET_FIFO_THRESH = 0x34, + OFFSET_FIFO_ADDR_CLR = 0x38, + OFFSET_IO_CONFIG = 0x40, + OFFSET_RSV_DEBUG = 0x44, + OFFSET_HS = 0x48, + OFFSET_SOFTRESET = 0x50, + OFFSET_DCM_EN = 0x54, + OFFSET_PATH_DIR = 0x60, + OFFSET_DEBUGSTAT = 0x64, + OFFSET_DEBUGCTRL = 0x68, + OFFSET_TRANSFER_LEN_AUX = 0x6c, +}; + +struct mtk_i2c_compatible { + const struct i2c_adapter_quirks *quirks; + unsigned char pmic_i2c: 1; + unsigned char dcm: 1; +}; + +struct mtk_i2c { + struct i2c_adapter adap; /* i2c host adapter */ + struct device *dev; + struct completion msg_complete; + + /* set in i2c probe */ + void __iomem *base; /* i2c base addr */ + void __iomem *pdmabase; /* dma base address*/ + struct clk *clk_main; /* main clock for i2c bus */ + struct clk *clk_dma; /* DMA clock for i2c via DMA */ + struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ + bool have_pmic; /* can use i2c pins from PMIC */ + bool use_push_pull; /* IO config push-pull mode */ + + u16 irq_stat; /* interrupt status */ + unsigned int speed_hz; /* The speed in transfer */ + enum mtk_trans_op op; + u16 timing_reg; + u16 high_speed_reg; + const struct mtk_i2c_compatible *dev_comp; +}; + +static const struct i2c_adapter_quirks mt6577_i2c_quirks = { + .flags = I2C_AQ_COMB_WRITE_THEN_READ, + .max_num_msgs = 1, + .max_write_len = 255, + .max_read_len = 255, + .max_comb_1st_msg_len = 255, + .max_comb_2nd_msg_len = 31, +}; + +static const struct mtk_i2c_compatible mt6577_compat = { + .quirks = &mt6577_i2c_quirks, + .pmic_i2c = 0, + .dcm = 1, +}; + +static const struct mtk_i2c_compatible mt6589_compat = { + .quirks = &mt6577_i2c_quirks, + .pmic_i2c = 1, + .dcm = 0, +}; + +static const struct of_device_id mtk_i2c_of_match[] = { + { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, + {} +}; +MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); + +static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) +{ + int ret; + + ret = clk_prepare_enable(i2c->clk_dma); + if (ret) + return ret; + + ret = clk_prepare_enable(i2c->clk_main); + if (ret) + goto err_main; + + if (i2c->have_pmic) { + ret = clk_prepare_enable(i2c->clk_pmic); + if (ret) + goto err_pmic; + } + return 0; + +err_pmic: + clk_disable_unprepare(i2c->clk_main); +err_main: + clk_disable_unprepare(i2c->clk_dma); + + return ret; +} + +static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) +{ + if (i2c->have_pmic) + clk_disable_unprepare(i2c->clk_pmic); + + clk_disable_unprepare(i2c->clk_main); + clk_disable_unprepare(i2c->clk_dma); +} + +static void mtk_i2c_init_hw(struct mtk_i2c *i2c) +{ + u16 control_reg; + + writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET); + + /* Set ioconfig */ + if (i2c->use_push_pull) + writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG); + else + writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG); + + if (i2c->dev_comp->dcm) + writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN); + + writew(i2c->timing_reg, i2c->base + OFFSET_TIMING); + writew(i2c->high_speed_reg, i2c->base + OFFSET_HS); + + /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ + if (i2c->have_pmic) + writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR); + + control_reg = I2C_CONTROL_ACKERR_DET_EN | + I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; + writew(control_reg, i2c->base + OFFSET_CONTROL); + writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN); +} + +/* + * Calculate i2c port speed + * + * Hardware design: + * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) + * clock_div: fixed in hardware, but may be various in different SoCs + * + * The calculation want to pick the highest bus frequency that is still + * less than or equal to i2c->speed_hz. The calculation try to get + * sample_cnt and step_cn + */ +static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk, + unsigned int clock_div) +{ + unsigned int clk_src; + unsigned int step_cnt; + unsigned int sample_cnt; + unsigned int max_step_cnt; + unsigned int target_speed; + unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; + unsigned int base_step_cnt; + unsigned int opt_div; + unsigned int best_mul; + unsigned int cnt_mul; + + clk_src = parent_clk / clock_div; + target_speed = i2c->speed_hz; + + if (target_speed > MAX_HS_MODE_SPEED) + target_speed = MAX_HS_MODE_SPEED; + + if (target_speed > MAX_FS_MODE_SPEED) + max_step_cnt = MAX_HS_STEP_CNT_DIV; + else + max_step_cnt = MAX_STEP_CNT_DIV; + + base_step_cnt = max_step_cnt; + /* Find the best combination */ + opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); + best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; + + /* Search for the best pair (sample_cnt, step_cnt) with + * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV + * 0 < step_cnt < max_step_cnt + * sample_cnt * step_cnt >= opt_div + * optimizing for sample_cnt * step_cnt being minimal + */ + for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { + step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); + cnt_mul = step_cnt * sample_cnt; + if (step_cnt > max_step_cnt) + continue; + + if (cnt_mul < best_mul) { + best_mul = cnt_mul; + base_sample_cnt = sample_cnt; + base_step_cnt = step_cnt; + if (best_mul == opt_div) + break; + } + } + + sample_cnt = base_sample_cnt; + step_cnt = base_step_cnt; + + if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { + /* In this case, hardware can't support such + * low i2c_bus_freq + */ + dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); + return -EINVAL; + } + + step_cnt--; + sample_cnt--; + + if (target_speed > MAX_FS_MODE_SPEED) { + /* Set the high speed mode register */ + i2c->timing_reg = I2C_FS_TIME_INIT_VALUE; + i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | + (sample_cnt << 12) | (step_cnt << 8); + } else { + i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0); + /* Disable the high speed transaction */ + i2c->high_speed_reg = I2C_TIME_CLR_VALUE; + } + + return 0; +} + +static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) +{ + u16 addr_reg; + u16 control_reg; + dma_addr_t rpaddr = 0; + dma_addr_t wpaddr = 0; + int ret; + + i2c->irq_stat = 0; + + reinit_completion(&i2c->msg_complete); + + control_reg = readw(i2c->base + OFFSET_CONTROL) & + ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); + if (i2c->speed_hz > 400000) + control_reg |= I2C_CONTROL_RS; + + if (i2c->op == I2C_MASTER_WRRD) + control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; + + writew(control_reg, i2c->base + OFFSET_CONTROL); + + /* set start condition */ + if (i2c->speed_hz <= 100000) + writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF); + else + writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF); + + addr_reg = msgs->addr << 1; + if (i2c->op == I2C_MASTER_RD) + addr_reg |= 0x1; + + writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR); + + /* Clear interrupt status */ + writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, + i2c->base + OFFSET_INTR_STAT); + writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR); + + /* Enable interrupt */ + writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, + i2c->base + OFFSET_INTR_MASK); + + /* Set transfer and transaction len */ + if (i2c->op == I2C_MASTER_WRRD) { + writew(msgs->len | ((msgs + 1)->len) << 8, + i2c->base + OFFSET_TRANSFER_LEN); + writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN); + } else { + writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN); + writew(I2C_RD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN); + } + + /* Prepare buffer data to start transfer */ + if (i2c->op == I2C_MASTER_RD) { + writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); + writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON); + rpaddr = dma_map_single(i2c->dev, msgs->buf, + msgs->len, DMA_FROM_DEVICE); + if (dma_mapping_error(i2c->dev, rpaddr)) + return -ENOMEM; + writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); + writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); + } else if (i2c->op == I2C_MASTER_WR) { + writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); + writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); + wpaddr = dma_map_single(i2c->dev, msgs->buf, + msgs->len, DMA_TO_DEVICE); + if (dma_mapping_error(i2c->dev, wpaddr)) + return -ENOMEM; + writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); + writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); + } else { + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON); + wpaddr = dma_map_single(i2c->dev, msgs->buf, + msgs->len, DMA_TO_DEVICE); + if (dma_mapping_error(i2c->dev, wpaddr)) + return -ENOMEM; + rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf, + (msgs + 1)->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(i2c->dev, rpaddr)) { + dma_unmap_single(i2c->dev, wpaddr, + msgs->len, DMA_TO_DEVICE); + return -ENOMEM; + } + writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); + writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); + writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); + writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); + } + + writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); + writew(I2C_TRANSAC_START, i2c->base + OFFSET_START); + + ret = wait_for_completion_timeout(&i2c->msg_complete, + i2c->adap.timeout); + + /* Clear interrupt mask */ + writew(~(I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK); + + if (i2c->op == I2C_MASTER_WR) { + dma_unmap_single(i2c->dev, wpaddr, + msgs->len, DMA_TO_DEVICE); + } else if (i2c->op == I2C_MASTER_RD) { + dma_unmap_single(i2c->dev, rpaddr, + msgs->len, DMA_FROM_DEVICE); + } else { + dma_unmap_single(i2c->dev, wpaddr, msgs->len, + DMA_TO_DEVICE); + dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, + DMA_FROM_DEVICE); + } + + if (ret == 0) { + dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); + mtk_i2c_init_hw(i2c); + return -ETIMEDOUT; + } + + completion_done(&i2c->msg_complete); + + if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { + dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); + mtk_i2c_init_hw(i2c); + return -ENXIO; + } + + return 0; +} + +static int mtk_i2c_transfer(struct i2c_adapter *adap, + struct i2c_msg msgs[], int num) +{ + int ret; + int left_num = num; + struct mtk_i2c *i2c = i2c_get_adapdata(adap); + + ret = mtk_i2c_clock_enable(i2c); + if (ret) + return ret; + + if (!msgs->buf) { + dev_dbg(i2c->dev, "data buffer is NULL.\n"); + ret = -EINVAL; + goto err_exit; + } + + if (msgs->flags & I2C_M_RD) + i2c->op = I2C_MASTER_RD; + else + i2c->op = I2C_MASTER_WR; + + if (num > 1) { + /* combined two messages into one transaction */ + i2c->op = I2C_MASTER_WRRD; + left_num--; + } + + /* always use DMA mode. */ + ret = mtk_i2c_do_transfer(i2c, msgs); + if (ret < 0) + goto err_exit; + + /* the return value is number of executed messages */ + ret = num; + +err_exit: + mtk_i2c_clock_disable(i2c); + return ret; +} + +static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) +{ + struct mtk_i2c *i2c = dev_id; + + i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT); + writew(I2C_HS_NACKERR | I2C_ACKERR + | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT); + + complete(&i2c->msg_complete); + + return IRQ_HANDLED; +} + +static u32 mtk_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm mtk_i2c_algorithm = { + .master_xfer = mtk_i2c_transfer, + .functionality = mtk_i2c_functionality, +}; + +static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c, + unsigned int *clk_src_div) +{ + int ret; + + ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); + if (ret < 0) + i2c->speed_hz = I2C_DEFAULT_SPEED; + + ret = of_property_read_u32(np, "clock-div", clk_src_div); + if (ret < 0) + return ret; + + if (*clk_src_div == 0) + return -EINVAL; + + i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); + i2c->use_push_pull = + of_property_read_bool(np, "mediatek,use-push-pull"); + + return 0; +} + +static int mtk_i2c_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + int ret = 0; + struct mtk_i2c *i2c; + struct clk *clk; + unsigned int clk_src_div; + struct resource *res; + int irq; + + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div); + if (ret) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2c->base)) + return PTR_ERR(i2c->base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2c->pdmabase)) + return PTR_ERR(i2c->pdmabase); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return irq; + + init_completion(&i2c->msg_complete); + + of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node); + if (!of_id) + return -EINVAL; + + i2c->dev_comp = of_id->data; + i2c->adap.dev.of_node = pdev->dev.of_node; + i2c->dev = &pdev->dev; + i2c->adap.dev.parent = &pdev->dev; + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &mtk_i2c_algorithm; + i2c->adap.quirks = i2c->dev_comp->quirks; + i2c->adap.timeout = 2 * HZ; + i2c->adap.retries = 1; + + if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) + return -EINVAL; + + i2c->clk_main = devm_clk_get(&pdev->dev, "main"); + if (IS_ERR(i2c->clk_main)) { + dev_err(&pdev->dev, "cannot get main clock\n"); + return PTR_ERR(i2c->clk_main); + } + + i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); + if (IS_ERR(i2c->clk_dma)) { + dev_err(&pdev->dev, "cannot get dma clock\n"); + return PTR_ERR(i2c->clk_dma); + } + + clk = i2c->clk_main; + if (i2c->have_pmic) { + i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); + if (IS_ERR(i2c->clk_pmic)) { + dev_err(&pdev->dev, "cannot get pmic clock\n"); + return PTR_ERR(i2c->clk_pmic); + } + clk = i2c->clk_pmic; + } + + strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); + + ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div); + if (ret) { + dev_err(&pdev->dev, "Failed to set the speed.\n"); + return -EINVAL; + } + + ret = mtk_i2c_clock_enable(i2c); + if (ret) { + dev_err(&pdev->dev, "clock enable failed!\n"); + return ret; + } + mtk_i2c_init_hw(i2c); + mtk_i2c_clock_disable(i2c); + + ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, + IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); + if (ret < 0) { + dev_err(&pdev->dev, + "Request I2C IRQ %d fail\n", irq); + return ret; + } + + i2c_set_adapdata(&i2c->adap, i2c); + ret = i2c_add_adapter(&i2c->adap); + if (ret) { + dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n"); + return ret; + } + + platform_set_drvdata(pdev, i2c); + + return 0; +} + +static int mtk_i2c_remove(struct platform_device *pdev) +{ + struct mtk_i2c *i2c = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c->adap); + + return 0; +} + +static struct platform_driver mtk_i2c_driver = { + .probe = mtk_i2c_probe, + .remove = mtk_i2c_remove, + .driver = { + .name = I2C_DRV_NAME, + .of_match_table = of_match_ptr(mtk_i2c_of_match), + }, +}; + +module_platform_driver(mtk_i2c_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); +MODULE_AUTHOR("Xudong Chen "); -- cgit v1.2.3 From 887ee43477e4e327dbcd2aabc2d78a5116ed8a33 Mon Sep 17 00:00:00 2001 From: Beomho Seo Date: Thu, 30 Apr 2015 13:07:43 +0900 Subject: hwmon: (ntc_thermistor) Add support for ncpXXwf104 This patch adds support for the ntc thermistor NCPXXWF104 series. Cc: Jean Delvare Cc: Guenter Roeck Signed-off-by: Beomho Seo Signed-off-by: Guenter Roeck --- .../devicetree/bindings/hwmon/ntc_thermistor.txt | 1 + Documentation/hwmon/ntc_thermistor | 6 ++- drivers/hwmon/Kconfig | 4 +- drivers/hwmon/ntc_thermistor.c | 44 ++++++++++++++++++++++ include/linux/platform_data/ntc_thermistor.h | 1 + 5 files changed, 52 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt index fcca8e744f41..a04a80f9cc70 100644 --- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt +++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt @@ -9,6 +9,7 @@ Requires node properties: "murata,ncp21wb473" "murata,ncp03wb473" "murata,ncp15wl333" + "murata,ncp03wf104" /* Usage of vendor name "ntc" is deprecated */ "ntc,ncp15wb473" diff --git a/Documentation/hwmon/ntc_thermistor b/Documentation/hwmon/ntc_thermistor index c5e05e2900a3..1d4cc847c6fe 100644 --- a/Documentation/hwmon/ntc_thermistor +++ b/Documentation/hwmon/ntc_thermistor @@ -2,8 +2,10 @@ Kernel driver ntc_thermistor ================= Supported thermistors from Murata: -* Murata NTC Thermistors NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, NCP15WL333 - Prefixes: 'ncp15wb473', 'ncp18wb473', 'ncp21wb473', 'ncp03wb473', 'ncp15wl333' +* Murata NTC Thermistors NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, + NCP15WL333, NCP03WF104 + Prefixes: 'ncp15wb473', 'ncp18wb473', 'ncp21wb473', 'ncp03wb473', + 'ncp15wl333', 'ncp03wf104' Datasheet: Publicly available at Murata Supported thermistors from EPCOS: diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 25d9e72627e9..4542ffc5468a 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1106,8 +1106,8 @@ config SENSORS_NTC_THERMISTOR send notifications about the temperature. Currently, this driver supports - NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, and NCP15WL333 - from Murata and B57330V2103 from EPCOS. + NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, NCP15WL333, + and NCP03WF104 from Murata and B57330V2103 from EPCOS. This driver can also be built as a module. If so, the module will be called ntc-thermistor. diff --git a/drivers/hwmon/ntc_thermistor.c b/drivers/hwmon/ntc_thermistor.c index 68800115876b..fca92912269e 100644 --- a/drivers/hwmon/ntc_thermistor.c +++ b/drivers/hwmon/ntc_thermistor.c @@ -53,6 +53,7 @@ static const struct platform_device_id ntc_thermistor_id[] = { { "ncp03wb473", TYPE_NCPXXWB473 }, { "ncp15wl333", TYPE_NCPXXWL333 }, { "b57330v2103", TYPE_B57330V2103}, + { "ncp03wf104", TYPE_NCPXXWF104 }, { }, }; @@ -135,6 +136,43 @@ static const struct ntc_compensation ncpXXwl333[] = { { .temp_c = 125, .ohm = 707 }, }; +static const struct ntc_compensation ncpXXwf104[] = { + { .temp_c = -40, .ohm = 4397119 }, + { .temp_c = -35, .ohm = 3088599 }, + { .temp_c = -30, .ohm = 2197225 }, + { .temp_c = -25, .ohm = 1581881 }, + { .temp_c = -20, .ohm = 1151037 }, + { .temp_c = -15, .ohm = 846579 }, + { .temp_c = -10, .ohm = 628988 }, + { .temp_c = -5, .ohm = 471632 }, + { .temp_c = 0, .ohm = 357012 }, + { .temp_c = 5, .ohm = 272500 }, + { .temp_c = 10, .ohm = 209710 }, + { .temp_c = 15, .ohm = 162651 }, + { .temp_c = 20, .ohm = 127080 }, + { .temp_c = 25, .ohm = 100000 }, + { .temp_c = 30, .ohm = 79222 }, + { .temp_c = 35, .ohm = 63167 }, + { .temp_c = 40, .ohm = 50677 }, + { .temp_c = 45, .ohm = 40904 }, + { .temp_c = 50, .ohm = 33195 }, + { .temp_c = 55, .ohm = 27091 }, + { .temp_c = 60, .ohm = 22224 }, + { .temp_c = 65, .ohm = 18323 }, + { .temp_c = 70, .ohm = 15184 }, + { .temp_c = 75, .ohm = 12635 }, + { .temp_c = 80, .ohm = 10566 }, + { .temp_c = 85, .ohm = 8873 }, + { .temp_c = 90, .ohm = 7481 }, + { .temp_c = 95, .ohm = 6337 }, + { .temp_c = 100, .ohm = 5384 }, + { .temp_c = 105, .ohm = 4594 }, + { .temp_c = 110, .ohm = 3934 }, + { .temp_c = 115, .ohm = 3380 }, + { .temp_c = 120, .ohm = 2916 }, + { .temp_c = 125, .ohm = 2522 }, +}; + /* * The following compensation table is from the specification of EPCOS NTC * Thermistors Datasheet @@ -219,6 +257,8 @@ static const struct of_device_id ntc_match[] = { .data = &ntc_thermistor_id[4] }, { .compatible = "epcos,b57330v2103", .data = &ntc_thermistor_id[5]}, + { .compatible = "murata,ncp03wf104", + .data = &ntc_thermistor_id[6] }, /* Usage of vendor name "ntc" is deprecated */ { .compatible = "ntc,ncp15wb473", @@ -567,6 +607,10 @@ static int ntc_thermistor_probe(struct platform_device *pdev) data->comp = b57330v2103; data->n_comp = ARRAY_SIZE(b57330v2103); break; + case TYPE_NCPXXWF104: + data->comp = ncpXXwf104; + data->n_comp = ARRAY_SIZE(ncpXXwf104); + break; default: dev_err(&pdev->dev, "Unknown device type: %lu(%s)\n", pdev_id->driver_data, pdev_id->name); diff --git a/include/linux/platform_data/ntc_thermistor.h b/include/linux/platform_data/ntc_thermistor.h index 0a6de4ca4930..aed170588b74 100644 --- a/include/linux/platform_data/ntc_thermistor.h +++ b/include/linux/platform_data/ntc_thermistor.h @@ -27,6 +27,7 @@ enum ntc_thermistor_type { TYPE_NCPXXWB473, TYPE_NCPXXWL333, TYPE_B57330V2103, + TYPE_NCPXXWF104, }; struct ntc_thermistor_platform_data { -- cgit v1.2.3 From 308f3f8d8112ea9af6e10564f4012f2d1f94f062 Mon Sep 17 00:00:00 2001 From: Suman Tripathi Date: Mon, 4 May 2015 19:09:51 +0530 Subject: mmc: sdhci-of-arasan: Add the support for sdhci-arasan4.9a This patch adds the quirks and compatible string in sdhci-of-arasan.c to support sdhci-arasan4.9a version of controller. Signed-off-by: Suman Tripathi Reviewed-by: Michal Simek Acked-by: Arnd Bergmann Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 3 ++- drivers/mmc/host/sdhci-of-arasan.c | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 98ee2abbe138..7e9490313d5a 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -8,7 +8,8 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or + 'arasan,sdhci-4.9a' - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 6287d426c96b..21c0c08dfe54 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -20,6 +20,7 @@ */ #include +#include #include "sdhci-pltfm.h" #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c @@ -168,6 +169,11 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto clk_disable_all; } + if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) { + host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; + } + sdhci_get_of_property(pdev); pltfm_host = sdhci_priv(host); pltfm_host->priv = sdhci_arasan; @@ -208,6 +214,7 @@ static int sdhci_arasan_remove(struct platform_device *pdev) static const struct of_device_id sdhci_arasan_of_match[] = { { .compatible = "arasan,sdhci-8.9a" }, + { .compatible = "arasan,sdhci-4.9a" }, { } }; MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); -- cgit v1.2.3 From 19f4424677455a01b93163975cfbcffa9adb3336 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 6 May 2015 20:31:20 +0200 Subject: mmc: dt: Allow to specify that no write protect signal is present Allow to specify in the device-tree that no physical write-protect signal is connected to a particular instance of a MMC controller. Setting the property will cause the core will assume that the SD card is always read-write. The name for the new property is 'disable-wp' and was chosen based on the property with the same function from the Synopsys designware mobile storage host controller DT bindings specification. Signed-off-by: Lars-Peter Clausen Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc.txt | 5 +++++ drivers/mmc/core/host.c | 3 +++ 2 files changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 438899e8829b..0384fc3f64e8 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -21,6 +21,11 @@ Optional properties: below for the case, when a GPIO is used for the CD line - wp-inverted: when present, polarity on the WP line is inverted. See the note below for the case, when a GPIO is used for the WP line +- disable-wp: When set no physical WP line is present. This property should + only be specified when the controller has a dedicated write-protect + detection logic. If a GPIO is always used for the write-protect detection + logic it is sufficient to not specify wp-gpios property in the absence of a WP + line. - max-frequency: maximum operating clock frequency - no-1-8-v: when present, denotes that 1.8v card voltage is not supported on this system, even if the controller claims it is. diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 86c495b7a335..99a9c9011c50 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -484,6 +484,9 @@ int mmc_of_parse(struct mmc_host *host) else if (ret != -ENOENT) return ret; + if (of_property_read_bool(np, "disable-wp")) + host->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; + /* See the comment on CD inversion above */ if (ro_cap_invert ^ ro_gpio_invert) host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; -- cgit v1.2.3 From d9c7eb3895f755ab0e458a216961964ebffd9edb Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Thu, 14 May 2015 16:45:17 +0800 Subject: Document: dw_mmc-k3: add document of hi6220 mmc Add bindings for hi6220 mmc support Signed-off-by: Zhangfei Gao Signed-off-by: Jaehoon Chung Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/k3-dw-mshc.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt index 3b3544931437..df370585cbcc 100644 --- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt @@ -13,6 +13,10 @@ Required Properties: * compatible: should be one of the following. - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions. + - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions. + +Optional Properties: +- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral. Example: @@ -42,3 +46,27 @@ Example: cap-mmc-highspeed; cap-sd-highspeed; }; + + /* for Hi6220 */ + + dwmmc_1: dwmmc1@f723e000 { + compatible = "hisilicon,hi6220-dw-mshc"; + num-slots = <0x1>; + bus-width = <0x4>; + disable-wp; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + card-detect-delay = <200>; + hisilicon,peripheral-syscon = <&ao_ctrl>; + reg = <0x0 0xf723e000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>; + clock-names = "ciu", "biu"; + cd-gpios = <&gpio1 0 1>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; + pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; + vqmmc-supply = <&ldo7>; + vmmc-supply = <&ldo10>; + }; -- cgit v1.2.3 From 89d49a706ca417c55c046d2580403be578cadaab Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 14 May 2015 07:22:46 +0000 Subject: mmc: sh_mmcif: calculate best clock with parent clock MMCIF IP on R-Car series has parent clock which can be set several rate, and it was not implemented on old SH-Mobile series (= SH-Mobile series parent clock was fixed rate) R-Car series MMCIF can use more high speed access if it setups parent clock. This patch adds parent clock setup method. It will be used if DT has "max-frequency", and then, this driver assumes it is booted on R-Car Gen2 or later SoC. Because SH-Mobile series (which doesn't boot from DT) and R-Car series (which boots from DT) have different divider. Signed-off-by: Kuninori Morimoto Tested-by: Keita Kobayashi Signed-off-by: Ulf Hansson [Ulf: Silence compiler warning] --- .../devicetree/bindings/mmc/renesas,mmcif.txt | 3 + drivers/mmc/host/sh_mmcif.c | 84 +++++++++++++++++++--- 2 files changed, 78 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt index 299081f94abd..d38942f6c5ae 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt @@ -18,6 +18,8 @@ Required properties: dma-names property. - dma-names: must contain "tx" for the transmit DMA channel and "rx" for the receive DMA channel. +- max-frequency: Maximum operating clock frequency, driver uses default clock + frequency if it is not set. Example: R8A7790 (R-Car H2) MMCIF0 @@ -29,4 +31,5 @@ Example: R8A7790 (R-Car H2) MMCIF0 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; dma-names = "tx", "rx"; + max-frequency = <97500000>; }; diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index e13c5f41fac4..5a1fdd405b1a 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -224,6 +225,9 @@ enum sh_mmcif_wait_for { MMCIF_WAIT_FOR_STOP, }; +/* + * difference for each SoC + */ struct sh_mmcif_host { struct mmc_host *mmc; struct mmc_request *mrq; @@ -248,6 +252,7 @@ struct sh_mmcif_host { bool ccs_enable; /* Command Completion Signal support */ bool clk_ctrl2_enable; struct mutex thread_lock; + u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ /* DMA support */ struct dma_chan *chan_rx; @@ -492,19 +497,55 @@ static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) struct sh_mmcif_plat_data *p = dev->platform_data; bool sup_pclk = p ? p->sup_pclk : false; unsigned int current_clk = clk_get_rate(host->clk); + unsigned int clkdiv; sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); if (!clk) return; - if (sup_pclk && clk == current_clk) - sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); - else - sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & - ((fls(DIV_ROUND_UP(current_clk, - clk) - 1) - 1) << 16)); + if (host->clkdiv_map) { + unsigned int freq, best_freq, myclk, div, diff_min, diff; + int i; + + clkdiv = 0; + diff_min = ~0; + best_freq = 0; + for (i = 31; i >= 0; i--) { + if (!((1 << i) & host->clkdiv_map)) + continue; + + /* + * clk = parent_freq / div + * -> parent_freq = clk x div + */ + + div = 1 << (i + 1); + freq = clk_round_rate(host->clk, clk * div); + myclk = freq / div; + diff = (myclk > clk) ? myclk - clk : clk - myclk; + + if (diff <= diff_min) { + best_freq = freq; + clkdiv = i; + diff_min = diff; + } + } + + dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", + (best_freq / (1 << (clkdiv + 1))), clk, + best_freq, clkdiv); + + clk_set_rate(host->clk, best_freq); + clkdiv = clkdiv << 16; + } else if (sup_pclk && clk == current_clk) { + clkdiv = CLK_SUP_PCLK; + } else { + clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; + } + + sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); } @@ -1000,10 +1041,35 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) { - unsigned int clk = clk_get_rate(host->clk); + struct device *dev = sh_mmcif_host_to_dev(host); + + if (host->mmc->f_max) { + unsigned int f_max, f_min = 0, f_min_old; + + f_max = host->mmc->f_max; + for (f_min_old = f_max; f_min_old > 2;) { + f_min = clk_round_rate(host->clk, f_min_old / 2); + if (f_min == f_min_old) + break; + f_min_old = f_min; + } + + /* + * This driver assumes this SoC is R-Car Gen2 or later + */ + host->clkdiv_map = 0x3ff; + + host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); + host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); + } else { + unsigned int clk = clk_get_rate(host->clk); + + host->mmc->f_max = clk / 2; + host->mmc->f_min = clk / 512; + } - host->mmc->f_max = clk / 2; - host->mmc->f_min = clk / 512; + dev_dbg(dev, "clk max/min = %d/%d\n", + host->mmc->f_max, host->mmc->f_min); } static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) -- cgit v1.2.3 From e4a51cebf4dcae47a1312956fa8a237dc8efcb48 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 27 May 2015 18:13:29 +0800 Subject: mmc: sdhci-esdhc-imx: using specific compatible string in binding doc Using specific compatible string in binding doc to make the binding more clear. It's also used to avoid checkpatch warning in the future like follows: WARNING: DT compatible string "fsl,imx6sx-usdhc" appears un-documented -- check ./Documentation/devicetree/bindings/ + { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, total: 0 errors, 1 warnings, 18 lines checked Signed-off-by: Dong Aisheng Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 415c5575cbf7..5d0376b8f202 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -7,7 +7,14 @@ This file documents differences between the core properties described by mmc.txt and the properties used by the sdhci-esdhc-imx driver. Required properties: -- compatible : Should be "fsl,-esdhc" +- compatible : Should be "fsl,-esdhc", the supported chips include + "fsl,imx25-esdhc" + "fsl,imx35-esdhc" + "fsl,imx51-esdhc" + "fsl,imx53-esdhc" + "fsl,imx6q-usdhc" + "fsl,imx6sl-usdhc" + "fsl,imx6sx-usdhc" Optional properties: - fsl,cd-controller : Indicate to use controller internal card detection -- cgit v1.2.3 From 6fc1cb2ef495df7a505b71dbc660c743043ae7b8 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 31 May 2015 09:59:10 -0300 Subject: [media] DocBook media: fix typos satellital -> satellite antena -> antenna Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 8 ++++---- Documentation/DocBook/media/dvb/fe-set-tone.xml | 2 +- Documentation/DocBook/media/dvb/fe-set-voltage.xml | 2 +- Documentation/DocBook/media/dvb/frontend.xml | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index a5d0a209d3f3..00bf3edc91c7 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -3,7 +3,7 @@ Tuning into a Digital TV physical channel and starting decoding it requires to change a set of parameters, in order to control the tuner, the demodulator, the Linear Low-noise Amplifier (LNA) and to set the - antena subsystem via Satellite Equipment Control (SEC), on satellital + antenna subsystem via Satellite Equipment Control (SEC), on satellite systems. The actual parameters are specific to each particular digital TV standards, and may change as the digital TV specs evolutes. In the past, the strategy used were to have an union with the parameters @@ -171,7 +171,7 @@ get/set up to 64 properties. The actual meaning of each property is described on Central frequency of the channel. Notes: - 1)For satellital delivery systems, it is measured in kHz. + 1)For satellite delivery systems, it is measured in kHz. For the other ones, it is measured in Hz. 2)For ISDB-T, the channels are usually transmitted with an offset of 143kHz. E.g. a valid frequency could be 474143 kHz. The stepping is bound to the bandwidth of @@ -1434,8 +1434,8 @@ enum fe_interleaving { In addition, the DTV QoS statistics are also valid.
-
- Properties used on satellital delivery systems +
+ Properties used on satellite delivery systems
DVB-S delivery system The following parameters are valid for DVB-S: diff --git a/Documentation/DocBook/media/dvb/fe-set-tone.xml b/Documentation/DocBook/media/dvb/fe-set-tone.xml index f3d965503c25..4ef6c74601ee 100644 --- a/Documentation/DocBook/media/dvb/fe-set-tone.xml +++ b/Documentation/DocBook/media/dvb/fe-set-tone.xml @@ -49,7 +49,7 @@ This ioctl is used to set the generation of the continuous 22kHz tone. This call requires read/write permissions. -Usually, satellital antenna subsystems require that the digital TV +Usually, satellite antenna subsystems require that the digital TV device to send a 22kHz tone in order to select between high/low band on some dual-band LNBf. It is also used to send signals to DiSEqC equipment, but this is done using the DiSEqC ioctls. diff --git a/Documentation/DocBook/media/dvb/fe-set-voltage.xml b/Documentation/DocBook/media/dvb/fe-set-voltage.xml index d43d51ab8a2d..688fbc2c5937 100644 --- a/Documentation/DocBook/media/dvb/fe-set-voltage.xml +++ b/Documentation/DocBook/media/dvb/fe-set-voltage.xml @@ -49,7 +49,7 @@ This ioctl allows to set the DC voltage level sent through the antenna cable to 13V, 18V or off. -Usually, a satellital antenna subsystems require that the digital TV +Usually, a satellite antenna subsystems require that the digital TV device to send a DC voltage to feed power to the LNBf. Depending on the LNBf type, the polarization or the intermediate frequency (IF) of the LNBf can controlled by the voltage level. Other devices (for example, the ones diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index d81b3ff33295..9eda6c0997d0 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -4,7 +4,7 @@ Terrestrial systems: DVB-T, DVB-T2, ATSC, ATSC M/H, ISDB-T, DVB-H, DTMB, CMMB Cable systems: DVB-C Annex A/C, ClearQAM (DVB-C Annex B), ISDB-C - Satellital systems: DVB-S, DVB-S2, DVB Turbo, ISDB-S, DSS + Satellite systems: DVB-S, DVB-S2, DVB Turbo, ISDB-S, DSS The DVB frontend controls several sub-devices including: @@ -21,7 +21,7 @@ NOTE: Transmission via the internet (DVB-IP) is not yet handled by this API but a future extension is possible. -On Satellital systems, the API support for the Satellite Equipment Control +On Satellite systems, the API support for the Satellite Equipment Control (SEC) allows to power control and to send/receive signals to control the antenna subsystem, selecting the polarization and choosing the Intermediate Frequency IF) of the Low Noise Block Converter Feed Horn (LNBf). It -- cgit v1.2.3 From 595d041a18ec80702b6d4e01ebb2e47f1a0d3781 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 31 May 2015 09:59:11 -0300 Subject: [media] DocBook media: xmllint fixes Fixes a large number of xmllint errors. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 20 ++++++++--------- .../media/dvb/fe-diseqc-recv-slave-reply.xml | 2 +- .../DocBook/media/dvb/fe-diseqc-send-burst.xml | 8 +++---- .../media/dvb/fe-diseqc-send-master-cmd.xml | 2 +- .../media/dvb/fe-enable-high-lnb-voltage.xml | 6 ++--- Documentation/DocBook/media/dvb/fe-get-info.xml | 8 +++---- .../DocBook/media/dvb/fe-get-property.xml | 26 +++++++++++----------- Documentation/DocBook/media/dvb/fe-read-status.xml | 4 ++-- .../media/dvb/fe-set-frontend-tune-mode.xml | 6 ++--- Documentation/DocBook/media/dvb/fe-set-tone.xml | 8 +++---- Documentation/DocBook/media/dvb/fe-set-voltage.xml | 6 ++--- Documentation/DocBook/media/dvb/frontend.xml | 16 ++++++------- .../DocBook/media/dvb/frontend_legacy_api.xml | 3 +-- 13 files changed, 56 insertions(+), 59 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 00bf3edc91c7..5dfde521e9fe 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -27,13 +27,13 @@ rate of 5.217 Mbauds, those properties should be sent to FE_SET_PROPERTY ioctl: - &DTV-DELIVERY-SYSTEM; = SYS_DVBC_ANNEX_A - &DTV-FREQUENCY; = 651000000 - &DTV-MODULATION; = QAM_256 - &DTV-INVERSION; = INVERSION_AUTO - &DTV-SYMBOL-RATE; = 5217000 - &DTV-INNER-FEC; = FEC_3_4 - &DTV-TUNE; + &DTV-DELIVERY-SYSTEM; = SYS_DVBC_ANNEX_A + &DTV-FREQUENCY; = 651000000 + &DTV-MODULATION; = QAM_256 + &DTV-INVERSION; = INVERSION_AUTO + &DTV-SYMBOL-RATE; = 5217000 + &DTV-INNER-FEC; = FEC_3_4 + &DTV-TUNE; The code that would do the above is: @@ -394,7 +394,6 @@ get/set up to 64 properties. The actual meaning of each property is described on FEC_3_5 Forward Error Correction Code 3/5 - @@ -916,7 +915,6 @@ typedef enum atscmh_sccc_code_mode { -
Notes: 1) If DTV_GUARD_INTERVAL is set the GUARD_INTERVAL_AUTO the hardware will @@ -924,6 +922,7 @@ typedef enum atscmh_sccc_code_mode { in the missing parameters. 2) Intervals 1/128, 19/128 and 19/256 are used only for DVB-T2 at present 3) DTMB specifies PN420, PN595 and PN945. +
<constant>DTV_TRANSMISSION_MODE</constant> @@ -975,12 +974,10 @@ typedef enum atscmh_sccc_code_mode { TRANSMISSION_MODE_C3780 Multi Carrier (C=3780) transmission mode (DTMB) - -
Notes: @@ -993,6 +990,7 @@ typedef enum atscmh_sccc_code_mode { 3) DVB-T specifies 2K and 8K as valid sizes. 4) DVB-T2 specifies 1K, 2K, 4K, 8K, 16K and 32K. 5) DTMB specifies C1 and C3780. +
<constant>DTV_HIERARCHY</constant> diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml b/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml index de68b5b57476..4595dbfff208 100644 --- a/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml +++ b/Documentation/DocBook/media/dvb/fe-diseqc-recv-slave-reply.xml @@ -15,7 +15,7 @@ int ioctl int fd int request - &dvb-diseqc-slave-reply; *argp + struct dvb_diseqc_slave_reply *argp diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml index f79c3f21323d..91dd2078a0f4 100644 --- a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml +++ b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml @@ -15,7 +15,7 @@ int ioctl int fd int request - &fe-sec-mini-cmd; *tone + enum fe_sec_mini_cmd *tone @@ -58,11 +58,11 @@ &return-value-dvb; -
+ enum fe_sec_mini_cmd - enum fe_sec_tone_mode + enum fe_sec_mini_cmd &cs-def; @@ -84,6 +84,6 @@
-
+ diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml b/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml index d4d6cd8dfc6c..38cf313e121b 100644 --- a/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml +++ b/Documentation/DocBook/media/dvb/fe-diseqc-send-master-cmd.xml @@ -15,7 +15,7 @@ int ioctl int fd int request - &dvb-diseqc-master-cmd; *argp + struct dvb_diseqc_master_cmd *argp diff --git a/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml b/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml index 3ee08a82cc7c..c11890b184ad 100644 --- a/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml +++ b/Documentation/DocBook/media/dvb/fe-enable-high-lnb-voltage.xml @@ -41,9 +41,9 @@ Valid flags: - 0 - normal 13V and 18V. - >0 - enables slightly higher voltages instead of - 13/18V, in order to compensate for long antena cables. + 0 - normal 13V and 18V. + >0 - enables slightly higher voltages instead of + 13/18V, in order to compensate for long antenna cables. diff --git a/Documentation/DocBook/media/dvb/fe-get-info.xml b/Documentation/DocBook/media/dvb/fe-get-info.xml index 4400790b4565..0e0245e45d26 100644 --- a/Documentation/DocBook/media/dvb/fe-get-info.xml +++ b/Documentation/DocBook/media/dvb/fe-get-info.xml @@ -16,7 +16,7 @@ int ioctl int fd int request - &dvb-frontend-info; *argp + struct dvb_frontend_info *argp @@ -112,12 +112,12 @@ driver is not compatible with this specification the ioctl returns an error. - NOTE: The frequencies are specified in Hz for Terrestrial and Cable systems. They're specified in kHz for Satellite systems + -
+ frontend capabilities Capabilities describe what a frontend can do. Some capabilities are @@ -262,5 +262,5 @@ driver is not compatible with this specification the ioctl returns an error. -
+ diff --git a/Documentation/DocBook/media/dvb/fe-get-property.xml b/Documentation/DocBook/media/dvb/fe-get-property.xml index 456ed92133f1..7d0bd78f5a24 100644 --- a/Documentation/DocBook/media/dvb/fe-get-property.xml +++ b/Documentation/DocBook/media/dvb/fe-get-property.xml @@ -17,7 +17,7 @@ int ioctl int fd int request - &dtv-properties; *argp + struct dtv_property *argp @@ -57,25 +57,25 @@ and on the device: FE_SET_PROPERTY: -This ioctl is used to set one or more - frontend properties. -This is the basic command to request the frontend to tune into some - frequency and to start decoding the digital TV signal. -This call requires read/write access to the device. -At return, the values are updated to reflect the - actual parameters used. +This ioctl is used to set one or more + frontend properties. +This is the basic command to request the frontend to tune into some + frequency and to start decoding the digital TV signal. +This call requires read/write access to the device. +At return, the values are updated to reflect the + actual parameters used. FE_GET_PROPERTY: -This ioctl is used to get properties and -statistics from the frontend. -No properties are changed, and statistics aren't reset. -This call only requires read-only access to the device. +This ioctl is used to get properties and +statistics from the frontend. +No properties are changed, and statistics aren't reset. +This call only requires read-only access to the device. -&return-value-dvb;. +&return-value-dvb; diff --git a/Documentation/DocBook/media/dvb/fe-read-status.xml b/Documentation/DocBook/media/dvb/fe-read-status.xml index bbd0b5bb6b12..3e4c794ceac3 100644 --- a/Documentation/DocBook/media/dvb/fe-read-status.xml +++ b/Documentation/DocBook/media/dvb/fe-read-status.xml @@ -59,7 +59,7 @@ pointer to an integer where the status will be written. &return-value-dvb; -
+ int fe_status The fe_status parameter is used to indicate the current state @@ -103,5 +103,5 @@ pointer to an integer where the status will be written. -
+ diff --git a/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml b/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml index 30bc99dc4c1c..99fa8a015c7a 100644 --- a/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml +++ b/Documentation/DocBook/media/dvb/fe-set-frontend-tune-mode.xml @@ -40,14 +40,14 @@ Valid flags: - 0 - normal tune mode - FE_TUNE_MODE_ONESHOT - When set, this flag will + 0 - normal tune mode + FE_TUNE_MODE_ONESHOT - When set, this flag will disable any zigzagging or other "normal" tuning behaviour. Additionally, there will be no automatic monitoring of the lock status, and hence no frontend events will be generated. If a frontend device is closed, this flag will be automatically turned off when the device is reopened - read-write. + read-write. diff --git a/Documentation/DocBook/media/dvb/fe-set-tone.xml b/Documentation/DocBook/media/dvb/fe-set-tone.xml index 4ef6c74601ee..12cd4dd3a6ef 100644 --- a/Documentation/DocBook/media/dvb/fe-set-tone.xml +++ b/Documentation/DocBook/media/dvb/fe-set-tone.xml @@ -15,7 +15,7 @@ int ioctl int fd int request - &fe-sec-tone-mode; *tone + enum fe_sec_tone_mode *tone @@ -61,8 +61,8 @@ &return-value-dvb; -
-enum fe_sec_voltage + +enum fe_sec_tone_mode enum fe_sec_tone_mode @@ -86,6 +86,6 @@
-
+ diff --git a/Documentation/DocBook/media/dvb/fe-set-voltage.xml b/Documentation/DocBook/media/dvb/fe-set-voltage.xml index 688fbc2c5937..73710f89ff1e 100644 --- a/Documentation/DocBook/media/dvb/fe-set-voltage.xml +++ b/Documentation/DocBook/media/dvb/fe-set-voltage.xml @@ -15,7 +15,7 @@ int ioctl int fd int request - &fe-sec-voltage; *voltage + enum fe_sec_voltage *voltage @@ -65,7 +65,7 @@ &return-value-dvb; -
+ enum fe_sec_voltage @@ -92,6 +92,6 @@
-
+ diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 9eda6c0997d0..ab42d8c6d11a 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -2,16 +2,16 @@ The DVB frontend API was designed to support three types of delivery systems: - Terrestrial systems: DVB-T, DVB-T2, ATSC, ATSC M/H, ISDB-T, DVB-H, DTMB, CMMB - Cable systems: DVB-C Annex A/C, ClearQAM (DVB-C Annex B), ISDB-C - Satellite systems: DVB-S, DVB-S2, DVB Turbo, ISDB-S, DSS + Terrestrial systems: DVB-T, DVB-T2, ATSC, ATSC M/H, ISDB-T, DVB-H, DTMB, CMMB + Cable systems: DVB-C Annex A/C, ClearQAM (DVB-C Annex B), ISDB-C + Satellite systems: DVB-S, DVB-S2, DVB Turbo, ISDB-S, DSS The DVB frontend controls several sub-devices including: - Tuner, - Digital TV demodulator - Low noise amplifier (LNA) - Satellite Equipment Control (SEC) hardware (only for Satellite). + Tuner + Digital TV demodulator + Low noise amplifier (LNA) + Satellite Equipment Control (SEC) hardware (only for Satellite). The frontend can be accessed through /dev/dvb/adapter?/frontend?. Data types and @@ -50,7 +50,7 @@ specification is available at Signal statistics are provided via FE_GET_PROPERTY. Please notice that several statistics require the demodulator to be fully locked (e. g. with FE_HAS_LOCK bit set). See - Frontend statistics indicators + Frontend statistics indicators for more details.
diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index cb2e18381305..3005cec58eb0 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -95,7 +95,6 @@ supported via the new FE_GET_PROPERTY/FE_GET_SET BANDWIDTH_10_MHZ 10 MHz - @@ -200,7 +199,7 @@ struct dvb_vsb_parameters {
-
+
Frontend Legacy Function Calls Those functions are defined at DVB version 3. The support is kept in -- cgit v1.2.3 From dc9ef7d11207a04514ca195f0c9f4d2ac56696e1 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 31 May 2015 09:59:12 -0300 Subject: [media] DocBook media: rewrite frontend open/close To fix the last xmllint errors the open and close function reference description was rewritten based on the v4l2 open and close functions. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 281 +++++++++++++++------------ 1 file changed, 159 insertions(+), 122 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index ab42d8c6d11a..c7fa3d8bff5c 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -59,11 +59,54 @@ specification is available at
Frontend Function Calls -
-open() -DESCRIPTION - - + + + open() + &manvol; + + + + fe-open + Open a frontend device + + + + + #include <fcntl.h> + + int open + const char *device_name + int flags + + + + + + Arguments + + + + device_name + + Device to be opened. + + + + flags + + Open flags. Access mode must be +O_RDWR. This is just a technicality, input devices +still support only reading and output devices only writing. + When the O_NONBLOCK flag is +given, the read() function will return the &EAGAIN; when no data is available, +otherwise these functions block until data becomes +available. Other flags have no effect. + + + + + + Description This system call opens a named frontend device (/dev/dvb/adapter0/frontend0) for subsequent use. Usually the first thing to do after a successful open is to find out the frontend type with FE_GET_INFO. @@ -82,127 +125,121 @@ specification is available at for use in the specified mode. This implies that the corresponding hardware is powered up, and that other front-ends may have been powered down to make that possible. - - - -SYNOPSIS - -int open(const char ⋆deviceName, int flags); - - -PARAMETERS - - -const char - *deviceName - -Name of specific video device. - - -int flags - -A bit-wise OR of the following flags: - - - -O_RDONLY read-only access - - - -O_RDWR read/write access - - - -O_NONBLOCK open in non-blocking mode - - - -(blocking mode is the default) - - -RETURN VALUE - -ENODEV - -Device driver not loaded/available. - - -EINTERNAL - -Internal error. - - -EBUSY - -Device or resource busy. - - -EINVAL - -Invalid argument. - - -
+ -
-close() -DESCRIPTION - - + + Return Value + + On success open returns the new file +descriptor. On error -1 is returned, and the errno +variable is set appropriately. Possible error codes are: + + + + EACCES + + The caller has no permission to access the +device. + + + + EBUSY + + The driver does not support multiple opens and the +device is already in use. + + + + ENXIO + + No device corresponding to this device special file +exists. + + + + ENOMEM + + Not enough kernel memory was available to complete the +request. + + + + EMFILE + + The process already has the maximum number of +files open. + + + + ENFILE + + The limit on the total number of files open on the +system has been reached. + + + + + + + + + close() + &manvol; + + + + fe-close + Close a frontend device + + + + + #include <unistd.h> + + int close + int fd + + + + + + Arguments + + + + fd + + &fd; + + + + + + + Description This system call closes a previously opened front-end device. After closing a front-end device, its corresponding hardware might be powered down automatically. - - -SYNOPSIS - - -int close(int fd); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -RETURN VALUE - -EBADF - -fd is not a valid open file descriptor. - - -
+ + + Return Value + + The function returns 0 on +success, -1 on failure and the +errno is set appropriately. Possible error +codes: + + + + EBADF + + fd is not a valid open file +descriptor. + + + + + &sub-fe-get-info; &sub-fe-read-status; -- cgit v1.2.3 From 6fd877748a9c4133e37417061e426188fcb00fea Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 1 Jun 2015 05:54:20 -0300 Subject: [media] DocBook: some fixes for DVB FE open() The changeset dc9ef7d11207 change the open() ioctl documentation to match the V4L2 open(). However, some cut-and-pasted stuff doesn't match what actually happens at the DVB core. So, fix the documentation entry to be more accurate with the DVB frontend open() specifics. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend.xml | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index c7fa3d8bff5c..9d8e95cd9694 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -61,7 +61,7 @@ specification is available at - open() + DVB frontend open() &manvol; @@ -94,20 +94,19 @@ specification is available at flags - Open flags. Access mode must be -O_RDWR. This is just a technicality, input devices -still support only reading and output devices only writing. - When the O_NONBLOCK flag is -given, the read() function will return the &EAGAIN; when no data is available, -otherwise these functions block until data becomes -available. Other flags have no effect. + Open flags. Access can either be + O_RDWR or O_RDONLY. + Multiple opens are allowed with O_RDONLY. In this mode, only query and read ioctls are allowed. + Only one open is allowed in O_RDWR. In this mode, all ioctls are allowed. + When the O_NONBLOCK flag is given, the system calls may return &EAGAIN; when no data is available or when the device driver is temporarily busy. + Other flags have no effect. Description -This system call opens a named frontend device (/dev/dvb/adapter0/frontend0) + This system call opens a named frontend device (/dev/dvb/adapter?/frontend?) for subsequent use. Usually the first thing to do after a successful open is to find out the frontend type with FE_GET_INFO. The device can be opened in read-only mode, which only allows monitoring of @@ -145,8 +144,7 @@ device. EBUSY - The driver does not support multiple opens and the -device is already in use. + The the device driver is already in use. @@ -177,13 +175,19 @@ files open. system has been reached. + + ENODEV + + The device got removed. + + - close() + DVB frontend close() &manvol; -- cgit v1.2.3 From c1c3c85ddf60a6d97c122d57d385b4929fcec4b3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 1 Jun 2015 06:10:15 -0300 Subject: [media] DocBook: fix FE_SET_PROPERTY ioctl arguments FE_SET_PROPERTY/FE_GET_PROPERTY actually expects a struct dtv_properties argument. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-get-property.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-get-property.xml b/Documentation/DocBook/media/dvb/fe-get-property.xml index 7d0bd78f5a24..53a170ed3bd1 100644 --- a/Documentation/DocBook/media/dvb/fe-get-property.xml +++ b/Documentation/DocBook/media/dvb/fe-get-property.xml @@ -17,7 +17,7 @@ int ioctl int fd int request - struct dtv_property *argp + struct dtv_properties *argp -- cgit v1.2.3 From 31a0b5373c7562d5a24f973a2afec1785d72d9c4 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 26 Feb 2015 17:42:06 +0100 Subject: clk: shmobile: Add r8a7778 SoC to MSTP bindings Signed-off-by: Ulrich Hecht Acked-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 0a80fa70ca26..e163092348bf 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks + - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks -- cgit v1.2.3 From b5405db9df8ea71435336bea8295cc4aa84ee3fa Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 28 May 2015 17:17:00 +0200 Subject: clk: shmobile: Add r8a7793 SoC to MSTP bindings Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion. Signed-off-by: Ulrich Hecht Acked-by: Simon Horman Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index e163092348bf..c95f7d2db6bd 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -16,7 +16,8 @@ Required Properties: - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks + - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks + - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - "renesas,cpg-mstp-clock" for generic MSTP gate clocks -- cgit v1.2.3 From 0e0d8b7050372e5b55f5067be8a15bb7577c9b00 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 28 May 2015 17:17:01 +0200 Subject: clk: shmobile: r8a7793: Document DIV6 clock bindings Signed-off-by: Ulrich Hecht Acked-by: Simon Horman Cc: devicetree@vger.kernel.org Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 054f65f9319c..b0a3a1147d62 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -10,7 +10,8 @@ Required Properties: - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks + - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - "renesas,cpg-div6-clock" for generic DIV6 clocks - reg: Base address and length of the memory resource used by the DIV6 clock -- cgit v1.2.3 From 0c933f3a45be471160bcf3428c1ee8f75f9cd75d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 1 Jun 2015 11:57:48 +0200 Subject: clk: shmobile: r8a7794: Document DIV6 clock bindings Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index b0a3a1147d62..3e40c41b0565 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -12,6 +12,7 @@ Required Properties: - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks + - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - "renesas,cpg-div6-clock" for generic DIV6 clocks - reg: Base address and length of the memory resource used by the DIV6 clock -- cgit v1.2.3 From 370626288f1a5992951abf825c4b662ba55774c0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 1 Jun 2015 12:00:08 +0200 Subject: clk: shmobile: div6: Document mandatory compatible fallback The generic CPG DIV6 clock compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 3e40c41b0565..5ddb68418655 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt @@ -14,7 +14,7 @@ Required Properties: - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - - "renesas,cpg-div6-clock" for generic DIV6 clocks + and "renesas,cpg-div6-clock" as a fallback. - reg: Base address and length of the memory resource used by the DIV6 clock - clocks: Reference to the parent clock(s); either one, four, or eight clocks must be specified. For clocks with multiple parents, invalid -- cgit v1.2.3 From 17df1fb2e502371b63ea1b2110584e8a712d6c20 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 May 2015 11:28:10 +0200 Subject: clk: shmobile: mstp: Document mandatory compatible fallback The generic MSTP gate clocks compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Also fix a typo (missing plural "s") in the compatible value. Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index c95f7d2db6bd..16ed18155160 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -20,7 +20,7 @@ Required Properties: - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + and "renesas,cpg-mstp-clocks" as a fallback. - reg: Base address and length of the I/O mapped registers used by the MSTP clocks. The first register is the clock control register and is mandatory. The second register is the clock status register and is optional when not -- cgit v1.2.3 From dd734a7e773c6b9d764d2879e715aaf579a99506 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 May 2015 11:31:17 +0200 Subject: clk: shmobile: rcar-gen2: Document mandatory compatible fallback The generic R-Car Gen2 CPG compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index b02944fba9de..56f111bd3e45 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt @@ -10,7 +10,7 @@ Required Properties: - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG - - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG + and "renesas,rcar-gen2-cpg-clocks" as a fallback. - reg: Base address and length of the memory resource used by the CPG -- cgit v1.2.3 From a431c1fa01ff020ecb146c04fbbea974e3eb910f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 28 May 2015 11:33:33 +0200 Subject: clk: shmobile: rz: Document mandatory compatible fallback The generic RZ CPG compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt index 98a257492522..b0f7ddb8cdb1 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt @@ -7,7 +7,7 @@ Required Properties: - compatible: Must be one of - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG - - "renesas,rz-cpg-clocks" for the generic RZ CPG + and "renesas,rz-cpg-clocks" as a fallback. - reg: Base address and length of the memory resource used by the CPG - clocks: References to possible parent clocks. Order must match clock modes in the datasheet. For the r7s72100, this is extal, usb_x1. -- cgit v1.2.3 From 692fbb89fa0b8028f402e33eb912474e11b5f435 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Thu, 16 Apr 2015 18:03:04 +1000 Subject: phy: twl4030-usb: add ABI documentation This driver device one local attribute: vbus. Describe that in Documentation/ABI/testing/sysfs-platform/twl4030-usb. Signed-off-by: NeilBrown Signed-off-by: Kishon Vijay Abraham I --- Documentation/ABI/testing/sysfs-platform-twl4030-usb | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-twl4030-usb (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-platform-twl4030-usb b/Documentation/ABI/testing/sysfs-platform-twl4030-usb new file mode 100644 index 000000000000..512c51be64ae --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-twl4030-usb @@ -0,0 +1,8 @@ +What: /sys/bus/platform/devices/*twl4030-usb/vbus +Description: + Read-only status reporting if VBUS (approx 5V) + is being supplied by the USB bus. + + Possible values: "on", "off". + + Changes are notified via select/poll. -- cgit v1.2.3 From 4af34b572a85c44c55491a10693535a79627c478 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 1 Jun 2015 11:04:26 +0200 Subject: drivers: soc: sunxi: Introduce SoC driver to map SRAMs The Allwinner SoCs have a handful of SRAM that can be either mapped to be accessible by devices or the CPU. That mapping is controlled by an SRAM controller, and that mapping might not be set by the bootloader, for example if the device wasn't used at all, or if we're using solutions like the U-Boot's Falcon Boot. We could also imagine changing this at runtime for example to change the mapping of these SRAMs to use them for suspend/resume or runtime memory rate change, if that ever happens. These use cases require some API in the kernel to control that mapping, exported through a drivers/soc driver. This driver also implement a debugfs file that shows the SRAM found in the system, the current mapping and the SRAM that have been claimed by some drivers in the kernel. Signed-off-by: Maxime Ripard Acked-by: Arnd Bergmann Acked-by: Hans de Goede Tested-by: Hans de Goede Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/soc/sunxi/sram.txt | 72 ++++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/sunxi/Kconfig | 10 + drivers/soc/sunxi/Makefile | 1 + drivers/soc/sunxi/sunxi_sram.c | 284 +++++++++++++++++++++ include/linux/soc/sunxi/sunxi_sram.h | 19 ++ 7 files changed, 388 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/sunxi/sram.txt create mode 100644 drivers/soc/sunxi/Kconfig create mode 100644 drivers/soc/sunxi/Makefile create mode 100644 drivers/soc/sunxi/sunxi_sram.c create mode 100644 include/linux/soc/sunxi/sunxi_sram.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/sunxi/sram.txt b/Documentation/devicetree/bindings/soc/sunxi/sram.txt new file mode 100644 index 000000000000..067698112f5f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sunxi/sram.txt @@ -0,0 +1,72 @@ +Allwinnner SoC SRAM controllers +----------------------------------------------------- + +The SRAM controller found on most Allwinner devices is represented by +a regular node for the SRAM controller itself, with sub-nodes +reprensenting the SRAM handled by the SRAM controller. + +Controller Node +--------------- + +Required properties: +- compatible : "allwinner,sun4i-a10-sram-controller" +- reg : sram controller register offset + length + +SRAM nodes +---------- + +Each SRAM is described using the mmio-sram bindings documented in +Documentation/devicetree/bindings/misc/sram.txt + +Each SRAM will have SRAM sections that are going to be handled by the +SRAM controller as subnodes. These sections are represented following +once again the representation described in the mmio-sram binding. + +The valid sections compatible are: + - allwinner,sun4i-a10-sram-a3-a4 + - allwinner,sun4i-a10-sram-d + +Devices using SRAM sections +--------------------------- + +Some devices need to request to the SRAM controller to map an SRAM for +their exclusive use. + +The relationship between such a device and an SRAM section is +expressed through the allwinner,sram property, that will take a +phandle and an argument. + +This valid values for this argument are: + - 0: CPU + - 1: Device + +Example +------- +sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; +}; + +emac: ethernet@01c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + ... + + allwinner,sram = <&emac_sram 1>; +}; diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d8bde82f0370..96ddecb92254 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" +source "drivers/soc/sunxi/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/versatile/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 70042b259744..7dc7c0d8a2c1 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/ diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig new file mode 100644 index 000000000000..353b07e40176 --- /dev/null +++ b/drivers/soc/sunxi/Kconfig @@ -0,0 +1,10 @@ +# +# Allwinner sunXi SoC drivers +# +config SUNXI_SRAM + bool + default ARCH_SUNXI + help + Say y here to enable the SRAM controller support. This + device is responsible on mapping the SRAM in the sunXi SoCs + whether to the CPU/DMA, or to the devices. diff --git a/drivers/soc/sunxi/Makefile b/drivers/soc/sunxi/Makefile new file mode 100644 index 000000000000..4cf9dbdf346e --- /dev/null +++ b/drivers/soc/sunxi/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c new file mode 100644 index 000000000000..bc52670c8f4b --- /dev/null +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -0,0 +1,284 @@ +/* + * Allwinner SoCs SRAM Controller Driver + * + * Copyright (C) 2015 Maxime Ripard + * + * Author: Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct sunxi_sram_func { + char *func; + u8 val; +}; + +struct sunxi_sram_data { + char *name; + u8 reg; + u8 offset; + u8 width; + struct sunxi_sram_func *func; + struct list_head list; +}; + +struct sunxi_sram_desc { + struct sunxi_sram_data data; + bool claimed; +}; + +#define SUNXI_SRAM_MAP(_val, _func) \ + { \ + .func = _func, \ + .val = _val, \ + } + +#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ + { \ + .name = _name, \ + .reg = _reg, \ + .offset = _off, \ + .width = _width, \ + .func = (struct sunxi_sram_func[]){ \ + __VA_ARGS__, { } }, \ + } + +static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = { + .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2, + SUNXI_SRAM_MAP(0, "cpu"), + SUNXI_SRAM_MAP(1, "emac")), +}; + +static struct sunxi_sram_desc sun4i_a10_sram_d = { + .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1, + SUNXI_SRAM_MAP(0, "cpu"), + SUNXI_SRAM_MAP(1, "usb-otg")), +}; + +static const struct of_device_id sunxi_sram_dt_ids[] = { + { + .compatible = "allwinner,sun4i-a10-sram-a3-a4", + .data = &sun4i_a10_sram_a3_a4.data, + }, + { + .compatible = "allwinner,sun4i-a10-sram-d", + .data = &sun4i_a10_sram_d.data, + }, + {} +}; + +static struct device *sram_dev; +static LIST_HEAD(claimed_sram); +static DEFINE_SPINLOCK(sram_lock); +static void __iomem *base; + +static int sunxi_sram_show(struct seq_file *s, void *data) +{ + struct device_node *sram_node, *section_node; + const struct sunxi_sram_data *sram_data; + const struct of_device_id *match; + struct sunxi_sram_func *func; + const __be32 *sram_addr_p, *section_addr_p; + u32 val; + + seq_puts(s, "Allwinner sunXi SRAM\n"); + seq_puts(s, "--------------------\n\n"); + + for_each_child_of_node(sram_dev->of_node, sram_node) { + sram_addr_p = of_get_address(sram_node, 0, NULL, NULL); + + seq_printf(s, "sram@%08x\n", + be32_to_cpu(*sram_addr_p)); + + for_each_child_of_node(sram_node, section_node) { + match = of_match_node(sunxi_sram_dt_ids, section_node); + if (!match) + continue; + sram_data = match->data; + + section_addr_p = of_get_address(section_node, 0, + NULL, NULL); + + seq_printf(s, "\tsection@%04x\t(%s)\n", + be32_to_cpu(*section_addr_p), + sram_data->name); + + val = readl(base + sram_data->reg); + val >>= sram_data->offset; + val &= sram_data->width; + + for (func = sram_data->func; func->func; func++) { + seq_printf(s, "\t\t%s%c\n", func->func, + func->val == val ? '*' : ' '); + } + } + + seq_puts(s, "\n"); + } + + return 0; +} + +static int sunxi_sram_open(struct inode *inode, struct file *file) +{ + return single_open(file, sunxi_sram_show, inode->i_private); +} + +static const struct file_operations sunxi_sram_fops = { + .open = sunxi_sram_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data) +{ + return container_of(data, struct sunxi_sram_desc, data); +} + +static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node, + unsigned int *value) +{ + const struct of_device_id *match; + struct of_phandle_args args; + int ret; + + ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0, + &args); + if (ret) + return ERR_PTR(ret); + + if (!of_device_is_available(args.np)) { + ret = -EBUSY; + goto err; + } + + if (value) + *value = args.args[0]; + + match = of_match_node(sunxi_sram_dt_ids, args.np); + if (!match) { + ret = -EINVAL; + goto err; + } + + of_node_put(args.np); + return match->data; + +err: + of_node_put(args.np); + return ERR_PTR(ret); +} + +int sunxi_sram_claim(struct device *dev) +{ + const struct sunxi_sram_data *sram_data; + struct sunxi_sram_desc *sram_desc; + unsigned int device; + u32 val, mask; + + if (IS_ERR(base)) + return -EPROBE_DEFER; + + if (!dev || !dev->of_node) + return -EINVAL; + + sram_data = sunxi_sram_of_parse(dev->of_node, &device); + if (IS_ERR(sram_data)) + return PTR_ERR(sram_data); + + sram_desc = to_sram_desc(sram_data); + + spin_lock(&sram_lock); + + if (sram_desc->claimed) { + spin_unlock(&sram_lock); + return -EBUSY; + } + + mask = GENMASK(sram_data->offset + sram_data->width, sram_data->offset); + val = readl(base + sram_data->reg); + val &= ~mask; + writel(val | ((device << sram_data->offset) & mask), + base + sram_data->reg); + + spin_unlock(&sram_lock); + + return 0; +} +EXPORT_SYMBOL(sunxi_sram_claim); + +int sunxi_sram_release(struct device *dev) +{ + const struct sunxi_sram_data *sram_data; + struct sunxi_sram_desc *sram_desc; + + if (!dev || !dev->of_node) + return -EINVAL; + + sram_data = sunxi_sram_of_parse(dev->of_node, NULL); + if (IS_ERR(sram_data)) + return -EINVAL; + + sram_desc = to_sram_desc(sram_data); + + spin_lock(&sram_lock); + sram_desc->claimed = false; + spin_unlock(&sram_lock); + + return 0; +} +EXPORT_SYMBOL(sunxi_sram_release); + +static int sunxi_sram_probe(struct platform_device *pdev) +{ + struct resource *res; + struct dentry *d; + + sram_dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + + d = debugfs_create_file("sram", S_IRUGO, NULL, NULL, + &sunxi_sram_fops); + if (!d) + return -ENOMEM; + + return 0; +} + +static const struct of_device_id sunxi_sram_dt_match[] = { + { .compatible = "allwinner,sun4i-a10-sram-controller" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); + +static struct platform_driver sunxi_sram_driver = { + .driver = { + .name = "sunxi-sram", + .of_match_table = sunxi_sram_dt_match, + }, + .probe = sunxi_sram_probe, +}; +module_platform_driver(sunxi_sram_driver); + +MODULE_AUTHOR("Maxime Ripard "); +MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/soc/sunxi/sunxi_sram.h b/include/linux/soc/sunxi/sunxi_sram.h new file mode 100644 index 000000000000..c5f663bba9c2 --- /dev/null +++ b/include/linux/soc/sunxi/sunxi_sram.h @@ -0,0 +1,19 @@ +/* + * Allwinner SoCs SRAM Controller Driver + * + * Copyright (C) 2015 Maxime Ripard + * + * Author: Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _SUNXI_SRAM_H_ +#define _SUNXI_SRAM_H_ + +int sunxi_sram_claim(struct device *dev); +int sunxi_sram_release(struct device *dev); + +#endif /* _SUNXI_SRAM_H_ */ -- cgit v1.2.3 From 7667f716e502f2b3e42085738b205ddc9abcff25 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 1 Jun 2015 12:44:15 +0200 Subject: ASoC: rsnd: Document r8a7778-specific binding Add the missing r8a7778-specific compatible value, which is already in use since v4.1-rc1. Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index f316ce1f214a..14f467345994 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -5,6 +5,7 @@ Required properties: "renesas,rcar_sound-gen1" if generation1, and "renesas,rcar_sound-gen2" if generation2 Examples with soctypes are: + - "renesas,rcar_sound-r8a7778" (R-Car M1A) - "renesas,rcar_sound-r8a7790" (R-Car H2) - "renesas,rcar_sound-r8a7791" (R-Car M2-W) - reg : Should contain the register physical address. -- cgit v1.2.3 From ec80749dfd859b560e8864d665d38d7a63e6a7f2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 1 Jun 2015 20:23:27 +0200 Subject: clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCs The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic interface which gets enabled by almost the same bits as used on the a31 for the 3rd phy, but not exactly the same bits so we need a new compatible for this. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-usb.c | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 4fa11af3d378..8a47b77abfca 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -67,6 +67,7 @@ Required properties: "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 + "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c index a86ed2f8d7af..3a25f9588e67 100644 --- a/drivers/clk/sunxi/clk-usb.c +++ b/drivers/clk/sunxi/clk-usb.c @@ -204,6 +204,17 @@ static void __init sun6i_a31_usb_setup(struct device_node *node) } CLK_OF_DECLARE(sun6i_a31_usb, "allwinner,sun6i-a31-usb-clk", sun6i_a31_usb_setup); +static const struct usb_clk_data sun8i_a23_usb_clk_data __initconst = { + .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8), + .reset_mask = BIT(2) | BIT(1) | BIT(0), +}; + +static void __init sun8i_a23_usb_setup(struct device_node *node) +{ + sunxi_usb_clk_setup(node, &sun8i_a23_usb_clk_data, &sun4i_a10_usb_lock); +} +CLK_OF_DECLARE(sun8i_a23_usb, "allwinner,sun8i-a23-usb-clk", sun8i_a23_usb_setup); + static const struct usb_clk_data sun9i_a80_usb_mod_data __initconst = { .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1), .reset_mask = BIT(19) | BIT(18) | BIT(17), -- cgit v1.2.3 From 5fc9b49deadc16d088e8fc6ca4fee85644380497 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Tue, 12 May 2015 00:00:49 +0200 Subject: doc: dt: Add documentation for lpc3220-timer Add DT bindings documentation for lpc3220-timer. This timer is used as clocksource on many NXP platforms. Signed-off-by: Joachim Eastwood Signed-off-by: Daniel Lezcano Acked-by: Arnd Bergmann --- .../bindings/timer/nxp,lpc3220-timer.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt b/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt new file mode 100644 index 000000000000..51b05a0e70d1 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt @@ -0,0 +1,26 @@ +* NXP LPC3220 timer + +The NXP LPC3220 timer is used on a wide range of NXP SoCs. This +includes LPC32xx, LPC178x, LPC18xx and LPC43xx parts. + +Required properties: +- compatible: + Should be "nxp,lpc3220-timer". +- reg: + Address and length of the register set. +- interrupts: + Reference to the timer interrupt +- clocks: + Should contain a reference to timer clock. +- clock-names: + Should contain "timerclk". + +Example: + +timer1: timer@40085000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40085000 0x1000>; + interrupts = <13>; + clocks = <&ccu1 CLK_CPU_TIMER1>; + clock-names = "timerclk"; +}; -- cgit v1.2.3 From 571fc8e836a1537b87804358c7baa9882d25b754 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Sat, 9 May 2015 09:53:45 +0200 Subject: dt-bindings: Document the ARM System timer bindings This adds documentation of device tree bindings for the ARM System timer. Tested-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Maxime Coquelin Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/arm/armv7m_systick.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/armv7m_systick.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/armv7m_systick.txt b/Documentation/devicetree/bindings/arm/armv7m_systick.txt new file mode 100644 index 000000000000..7cf4a24601eb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armv7m_systick.txt @@ -0,0 +1,26 @@ +* ARMv7M System Timer + +ARMv7-M includes a system timer, known as SysTick. Current driver only +implements the clocksource feature. + +Required properties: +- compatible : Should be "arm,armv7m-systick" +- reg : The address range of the timer + +Required clocking property, have to be one of: +- clocks : The input clock of the timer +- clock-frequency : The rate in HZ in input of the ARM SysTick + +Examples: + +systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + clocks = <&clk_systick>; +}; + +systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + clock-frequency = <90000000>; +}; -- cgit v1.2.3 From 4853914ffcea925ded0ac2be205f55688f302caa Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 22 May 2015 23:03:32 +0200 Subject: dt-bindings: Document the STM32 timer bindings This adds documentation of device tree bindings for the STM32 timer. Tested-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Maxime Coquelin Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/st,stm32-timer.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/st,stm32-timer.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt new file mode 100644 index 000000000000..8ef28e70d6e8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt @@ -0,0 +1,22 @@ +. STMicroelectronics STM32 timer + +The STM32 MCUs family has several general-purpose 16 and 32 bits timers. + +Required properties: +- compatible : Should be "st,stm32-timer" +- reg : Address and length of the register set +- clocks : Reference on the timer input clock +- interrupts : Reference to the timer interrupt + +Optional properties: +- resets: Reference to a reset controller asserting the timer + +Example: + +timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&rrc 259>; + clocks = <&clk_pmtr1>; +}; -- cgit v1.2.3 From c4843a7593a9df3ff5b1806084cefdfa81dd7c79 Mon Sep 17 00:00:00 2001 From: Greg Thelen Date: Fri, 22 May 2015 17:13:16 -0400 Subject: memcg: add per cgroup dirty page accounting When modifying PG_Dirty on cached file pages, update the new MEM_CGROUP_STAT_DIRTY counter. This is done in the same places where global NR_FILE_DIRTY is managed. The new memcg stat is visible in the per memcg memory.stat cgroupfs file. The most recent past attempt at this was http://thread.gmane.org/gmane.linux.kernel.cgroups/8632 The new accounting supports future efforts to add per cgroup dirty page throttling and writeback. It also helps an administrator break down a container's memory usage and provides evidence to understand memcg oom kills (the new dirty count is included in memcg oom kill messages). The ability to move page accounting between memcg (memory.move_charge_at_immigrate) makes this accounting more complicated than the global counter. The existing mem_cgroup_{begin,end}_page_stat() lock is used to serialize move accounting with stat updates. Typical update operation: memcg = mem_cgroup_begin_page_stat(page) if (TestSetPageDirty()) { [...] mem_cgroup_update_page_stat(memcg) } mem_cgroup_end_page_stat(memcg) Summary of mem_cgroup_end_page_stat() overhead: - Without CONFIG_MEMCG it's a no-op - With CONFIG_MEMCG and no inter memcg task movement, it's just rcu_read_lock() - With CONFIG_MEMCG and inter memcg task movement, it's rcu_read_lock() + spin_lock_irqsave() A memcg parameter is added to several routines because their callers now grab mem_cgroup_begin_page_stat() which returns the memcg later needed by for mem_cgroup_update_page_stat(). Because mem_cgroup_begin_page_stat() may disable interrupts, some adjustments are needed: - move __mark_inode_dirty() from __set_page_dirty() to its caller. __mark_inode_dirty() locking does not want interrupts disabled. - use spin_lock_irqsave(tree_lock) rather than spin_lock_irq() in __delete_from_page_cache(), replace_page_cache_page(), invalidate_complete_page2(), and __remove_mapping(). text data bss dec hex filename 8925147 1774832 1785856 12485835 be84cb vmlinux-!CONFIG_MEMCG-before 8925339 1774832 1785856 12486027 be858b vmlinux-!CONFIG_MEMCG-after +192 text bytes 8965977 1784992 1785856 12536825 bf4bf9 vmlinux-CONFIG_MEMCG-before 8966750 1784992 1785856 12537598 bf4efe vmlinux-CONFIG_MEMCG-after +773 text bytes Performance tests run on v4.0-rc1-36-g4f671fe2f952. Lower is better for all metrics, they're all wall clock or cycle counts. The read and write fault benchmarks just measure fault time, they do not include I/O time. * CONFIG_MEMCG not set: baseline patched kbuild 1m25.030000(+-0.088% 3 samples) 1m25.426667(+-0.120% 3 samples) dd write 100 MiB 0.859211561 +-15.10% 0.874162885 +-15.03% dd write 200 MiB 1.670653105 +-17.87% 1.669384764 +-11.99% dd write 1000 MiB 8.434691190 +-14.15% 8.474733215 +-14.77% read fault cycles 254.0(+-0.000% 10 samples) 253.0(+-0.000% 10 samples) write fault cycles 2021.2(+-3.070% 10 samples) 1984.5(+-1.036% 10 samples) * CONFIG_MEMCG=y root_memcg: baseline patched kbuild 1m25.716667(+-0.105% 3 samples) 1m25.686667(+-0.153% 3 samples) dd write 100 MiB 0.855650830 +-14.90% 0.887557919 +-14.90% dd write 200 MiB 1.688322953 +-12.72% 1.667682724 +-13.33% dd write 1000 MiB 8.418601605 +-14.30% 8.673532299 +-15.00% read fault cycles 266.0(+-0.000% 10 samples) 266.0(+-0.000% 10 samples) write fault cycles 2051.7(+-1.349% 10 samples) 2049.6(+-1.686% 10 samples) * CONFIG_MEMCG=y non-root_memcg: baseline patched kbuild 1m26.120000(+-0.273% 3 samples) 1m25.763333(+-0.127% 3 samples) dd write 100 MiB 0.861723964 +-15.25% 0.818129350 +-14.82% dd write 200 MiB 1.669887569 +-13.30% 1.698645885 +-13.27% dd write 1000 MiB 8.383191730 +-14.65% 8.351742280 +-14.52% read fault cycles 265.7(+-0.172% 10 samples) 267.0(+-0.000% 10 samples) write fault cycles 2070.6(+-1.512% 10 samples) 2084.4(+-2.148% 10 samples) As expected anon page faults are not affected by this patch. tj: Updated to apply on top of the recent cancel_dirty_page() changes. Signed-off-by: Sha Zhengju Signed-off-by: Greg Thelen Signed-off-by: Tejun Heo Signed-off-by: Jens Axboe --- Documentation/cgroups/memory.txt | 1 + fs/buffer.c | 34 +++++++++++++++++++++------ fs/xfs/xfs_aops.c | 12 ++++++++-- include/linux/memcontrol.h | 1 + include/linux/mm.h | 6 +++-- include/linux/pagemap.h | 3 ++- mm/filemap.c | 31 +++++++++++++++++-------- mm/memcontrol.c | 24 ++++++++++++++++++- mm/page-writeback.c | 50 +++++++++++++++++++++++++++++++++------- mm/rmap.c | 2 ++ mm/truncate.c | 14 +++++++---- mm/vmscan.c | 17 ++++++++++---- 12 files changed, 156 insertions(+), 39 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cgroups/memory.txt b/Documentation/cgroups/memory.txt index f456b4315e86..ff71e16cc752 100644 --- a/Documentation/cgroups/memory.txt +++ b/Documentation/cgroups/memory.txt @@ -493,6 +493,7 @@ pgpgin - # of charging events to the memory cgroup. The charging pgpgout - # of uncharging events to the memory cgroup. The uncharging event happens each time a page is unaccounted from the cgroup. swap - # of bytes of swap usage +dirty - # of bytes that are waiting to get written back to the disk. writeback - # of bytes of file/anon cache that are queued for syncing to disk. inactive_anon - # of bytes of anonymous and swap cache memory on inactive diff --git a/fs/buffer.c b/fs/buffer.c index f21327d1f673..23b640d5d6e9 100644 --- a/fs/buffer.c +++ b/fs/buffer.c @@ -623,21 +623,22 @@ EXPORT_SYMBOL(mark_buffer_dirty_inode); * * If warn is true, then emit a warning if the page is not uptodate and has * not been truncated. + * + * The caller must hold mem_cgroup_begin_page_stat() lock. */ -static void __set_page_dirty(struct page *page, - struct address_space *mapping, int warn) +static void __set_page_dirty(struct page *page, struct address_space *mapping, + struct mem_cgroup *memcg, int warn) { unsigned long flags; spin_lock_irqsave(&mapping->tree_lock, flags); if (page->mapping) { /* Race with truncate? */ WARN_ON_ONCE(warn && !PageUptodate(page)); - account_page_dirtied(page, mapping); + account_page_dirtied(page, mapping, memcg); radix_tree_tag_set(&mapping->page_tree, page_index(page), PAGECACHE_TAG_DIRTY); } spin_unlock_irqrestore(&mapping->tree_lock, flags); - __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); } /* @@ -668,6 +669,7 @@ static void __set_page_dirty(struct page *page, int __set_page_dirty_buffers(struct page *page) { int newly_dirty; + struct mem_cgroup *memcg; struct address_space *mapping = page_mapping(page); if (unlikely(!mapping)) @@ -683,11 +685,22 @@ int __set_page_dirty_buffers(struct page *page) bh = bh->b_this_page; } while (bh != head); } + /* + * Use mem_group_begin_page_stat() to keep PageDirty synchronized with + * per-memcg dirty page counters. + */ + memcg = mem_cgroup_begin_page_stat(page); newly_dirty = !TestSetPageDirty(page); spin_unlock(&mapping->private_lock); if (newly_dirty) - __set_page_dirty(page, mapping, 1); + __set_page_dirty(page, mapping, memcg, 1); + + mem_cgroup_end_page_stat(memcg); + + if (newly_dirty) + __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); + return newly_dirty; } EXPORT_SYMBOL(__set_page_dirty_buffers); @@ -1158,11 +1171,18 @@ void mark_buffer_dirty(struct buffer_head *bh) if (!test_set_buffer_dirty(bh)) { struct page *page = bh->b_page; + struct address_space *mapping = NULL; + struct mem_cgroup *memcg; + + memcg = mem_cgroup_begin_page_stat(page); if (!TestSetPageDirty(page)) { - struct address_space *mapping = page_mapping(page); + mapping = page_mapping(page); if (mapping) - __set_page_dirty(page, mapping, 0); + __set_page_dirty(page, mapping, memcg, 0); } + mem_cgroup_end_page_stat(memcg); + if (mapping) + __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); } } EXPORT_SYMBOL(mark_buffer_dirty); diff --git a/fs/xfs/xfs_aops.c b/fs/xfs/xfs_aops.c index 095f94c2d8b5..e5099f268032 100644 --- a/fs/xfs/xfs_aops.c +++ b/fs/xfs/xfs_aops.c @@ -1873,6 +1873,7 @@ xfs_vm_set_page_dirty( loff_t end_offset; loff_t offset; int newly_dirty; + struct mem_cgroup *memcg; if (unlikely(!mapping)) return !TestSetPageDirty(page); @@ -1892,6 +1893,11 @@ xfs_vm_set_page_dirty( offset += 1 << inode->i_blkbits; } while (bh != head); } + /* + * Use mem_group_begin_page_stat() to keep PageDirty synchronized with + * per-memcg dirty page counters. + */ + memcg = mem_cgroup_begin_page_stat(page); newly_dirty = !TestSetPageDirty(page); spin_unlock(&mapping->private_lock); @@ -1902,13 +1908,15 @@ xfs_vm_set_page_dirty( spin_lock_irqsave(&mapping->tree_lock, flags); if (page->mapping) { /* Race with truncate? */ WARN_ON_ONCE(!PageUptodate(page)); - account_page_dirtied(page, mapping); + account_page_dirtied(page, mapping, memcg); radix_tree_tag_set(&mapping->page_tree, page_index(page), PAGECACHE_TAG_DIRTY); } spin_unlock_irqrestore(&mapping->tree_lock, flags); - __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); } + mem_cgroup_end_page_stat(memcg); + if (newly_dirty) + __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); return newly_dirty; } diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h index 72dff5fb0d0c..5fe6411b5e54 100644 --- a/include/linux/memcontrol.h +++ b/include/linux/memcontrol.h @@ -41,6 +41,7 @@ enum mem_cgroup_stat_index { MEM_CGROUP_STAT_RSS, /* # of pages charged as anon rss */ MEM_CGROUP_STAT_RSS_HUGE, /* # of pages charged as anon huge */ MEM_CGROUP_STAT_FILE_MAPPED, /* # of pages charged as file rss */ + MEM_CGROUP_STAT_DIRTY, /* # of dirty pages in page cache */ MEM_CGROUP_STAT_WRITEBACK, /* # of pages under writeback */ MEM_CGROUP_STAT_SWAP, /* # of pages, swapped out */ MEM_CGROUP_STAT_NSTATS, diff --git a/include/linux/mm.h b/include/linux/mm.h index a83cf3a6f78e..f48d979ced4b 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1211,8 +1211,10 @@ int __set_page_dirty_nobuffers(struct page *page); int __set_page_dirty_no_writeback(struct page *page); int redirty_page_for_writepage(struct writeback_control *wbc, struct page *page); -void account_page_dirtied(struct page *page, struct address_space *mapping); -void account_page_cleaned(struct page *page, struct address_space *mapping); +void account_page_dirtied(struct page *page, struct address_space *mapping, + struct mem_cgroup *memcg); +void account_page_cleaned(struct page *page, struct address_space *mapping, + struct mem_cgroup *memcg); int set_page_dirty(struct page *page); int set_page_dirty_lock(struct page *page); void cancel_dirty_page(struct page *page); diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h index 4b3736f7065c..fb0814ca65c7 100644 --- a/include/linux/pagemap.h +++ b/include/linux/pagemap.h @@ -651,7 +651,8 @@ int add_to_page_cache_locked(struct page *page, struct address_space *mapping, int add_to_page_cache_lru(struct page *page, struct address_space *mapping, pgoff_t index, gfp_t gfp_mask); extern void delete_from_page_cache(struct page *page); -extern void __delete_from_page_cache(struct page *page, void *shadow); +extern void __delete_from_page_cache(struct page *page, void *shadow, + struct mem_cgroup *memcg); int replace_page_cache_page(struct page *old, struct page *new, gfp_t gfp_mask); /* diff --git a/mm/filemap.c b/mm/filemap.c index 6bf5e42d560a..7b1443dc3ad0 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -100,6 +100,7 @@ * ->tree_lock (page_remove_rmap->set_page_dirty) * bdi.wb->list_lock (page_remove_rmap->set_page_dirty) * ->inode->i_lock (page_remove_rmap->set_page_dirty) + * ->memcg->move_lock (page_remove_rmap->mem_cgroup_begin_page_stat) * bdi.wb->list_lock (zap_pte_range->set_page_dirty) * ->inode->i_lock (zap_pte_range->set_page_dirty) * ->private_lock (zap_pte_range->__set_page_dirty_buffers) @@ -174,9 +175,11 @@ static void page_cache_tree_delete(struct address_space *mapping, /* * Delete a page from the page cache and free it. Caller has to make * sure the page is locked and that nobody else uses it - or that usage - * is safe. The caller must hold the mapping's tree_lock. + * is safe. The caller must hold the mapping's tree_lock and + * mem_cgroup_begin_page_stat(). */ -void __delete_from_page_cache(struct page *page, void *shadow) +void __delete_from_page_cache(struct page *page, void *shadow, + struct mem_cgroup *memcg) { struct address_space *mapping = page->mapping; @@ -210,7 +213,7 @@ void __delete_from_page_cache(struct page *page, void *shadow) * anyway will be cleared before returning page into buddy allocator. */ if (WARN_ON_ONCE(PageDirty(page))) - account_page_cleaned(page, mapping); + account_page_cleaned(page, mapping, memcg); } /** @@ -224,14 +227,20 @@ void __delete_from_page_cache(struct page *page, void *shadow) void delete_from_page_cache(struct page *page) { struct address_space *mapping = page->mapping; + struct mem_cgroup *memcg; + unsigned long flags; + void (*freepage)(struct page *); BUG_ON(!PageLocked(page)); freepage = mapping->a_ops->freepage; - spin_lock_irq(&mapping->tree_lock); - __delete_from_page_cache(page, NULL); - spin_unlock_irq(&mapping->tree_lock); + + memcg = mem_cgroup_begin_page_stat(page); + spin_lock_irqsave(&mapping->tree_lock, flags); + __delete_from_page_cache(page, NULL, memcg); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); if (freepage) freepage(page); @@ -470,6 +479,8 @@ int replace_page_cache_page(struct page *old, struct page *new, gfp_t gfp_mask) if (!error) { struct address_space *mapping = old->mapping; void (*freepage)(struct page *); + struct mem_cgroup *memcg; + unsigned long flags; pgoff_t offset = old->index; freepage = mapping->a_ops->freepage; @@ -478,15 +489,17 @@ int replace_page_cache_page(struct page *old, struct page *new, gfp_t gfp_mask) new->mapping = mapping; new->index = offset; - spin_lock_irq(&mapping->tree_lock); - __delete_from_page_cache(old, NULL); + memcg = mem_cgroup_begin_page_stat(old); + spin_lock_irqsave(&mapping->tree_lock, flags); + __delete_from_page_cache(old, NULL, memcg); error = radix_tree_insert(&mapping->page_tree, offset, new); BUG_ON(error); mapping->nrpages++; __inc_zone_page_state(new, NR_FILE_PAGES); if (PageSwapBacked(new)) __inc_zone_page_state(new, NR_SHMEM); - spin_unlock_irq(&mapping->tree_lock); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); mem_cgroup_migrate(old, new, true); radix_tree_preload_end(); if (freepage) diff --git a/mm/memcontrol.c b/mm/memcontrol.c index 14c2f2017e37..c23c1a3e8e16 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -90,6 +90,7 @@ static const char * const mem_cgroup_stat_names[] = { "rss", "rss_huge", "mapped_file", + "dirty", "writeback", "swap", }; @@ -2011,6 +2012,7 @@ again: return memcg; } +EXPORT_SYMBOL(mem_cgroup_begin_page_stat); /** * mem_cgroup_end_page_stat - finish a page state statistics transaction @@ -2029,6 +2031,7 @@ void mem_cgroup_end_page_stat(struct mem_cgroup *memcg) rcu_read_unlock(); } +EXPORT_SYMBOL(mem_cgroup_end_page_stat); /** * mem_cgroup_update_page_stat - update page state statistics @@ -4746,6 +4749,7 @@ static int mem_cgroup_move_account(struct page *page, { unsigned long flags; int ret; + bool anon; VM_BUG_ON(from == to); VM_BUG_ON_PAGE(PageLRU(page), page); @@ -4771,15 +4775,33 @@ static int mem_cgroup_move_account(struct page *page, if (page->mem_cgroup != from) goto out_unlock; + anon = PageAnon(page); + spin_lock_irqsave(&from->move_lock, flags); - if (!PageAnon(page) && page_mapped(page)) { + if (!anon && page_mapped(page)) { __this_cpu_sub(from->stat->count[MEM_CGROUP_STAT_FILE_MAPPED], nr_pages); __this_cpu_add(to->stat->count[MEM_CGROUP_STAT_FILE_MAPPED], nr_pages); } + /* + * move_lock grabbed above and caller set from->moving_account, so + * mem_cgroup_update_page_stat() will serialize updates to PageDirty. + * So mapping should be stable for dirty pages. + */ + if (!anon && PageDirty(page)) { + struct address_space *mapping = page_mapping(page); + + if (mapping_cap_account_dirty(mapping)) { + __this_cpu_sub(from->stat->count[MEM_CGROUP_STAT_DIRTY], + nr_pages); + __this_cpu_add(to->stat->count[MEM_CGROUP_STAT_DIRTY], + nr_pages); + } + } + if (PageWriteback(page)) { __this_cpu_sub(from->stat->count[MEM_CGROUP_STAT_WRITEBACK], nr_pages); diff --git a/mm/page-writeback.c b/mm/page-writeback.c index 227b867598e1..bdeecad00489 100644 --- a/mm/page-writeback.c +++ b/mm/page-writeback.c @@ -2090,15 +2090,20 @@ int __set_page_dirty_no_writeback(struct page *page) /* * Helper function for set_page_dirty family. + * + * Caller must hold mem_cgroup_begin_page_stat(). + * * NOTE: This relies on being atomic wrt interrupts. */ -void account_page_dirtied(struct page *page, struct address_space *mapping) +void account_page_dirtied(struct page *page, struct address_space *mapping, + struct mem_cgroup *memcg) { trace_writeback_dirty_page(page, mapping); if (mapping_cap_account_dirty(mapping)) { struct backing_dev_info *bdi = inode_to_bdi(mapping->host); + mem_cgroup_inc_page_stat(memcg, MEM_CGROUP_STAT_DIRTY); __inc_zone_page_state(page, NR_FILE_DIRTY); __inc_zone_page_state(page, NR_DIRTIED); __inc_bdi_stat(bdi, BDI_RECLAIMABLE); @@ -2112,10 +2117,14 @@ EXPORT_SYMBOL(account_page_dirtied); /* * Helper function for deaccounting dirty page without writeback. + * + * Caller must hold mem_cgroup_begin_page_stat(). */ -void account_page_cleaned(struct page *page, struct address_space *mapping) +void account_page_cleaned(struct page *page, struct address_space *mapping, + struct mem_cgroup *memcg) { if (mapping_cap_account_dirty(mapping)) { + mem_cgroup_dec_page_stat(memcg, MEM_CGROUP_STAT_DIRTY); dec_zone_page_state(page, NR_FILE_DIRTY); dec_bdi_stat(inode_to_bdi(mapping->host), BDI_RECLAIMABLE); task_io_account_cancelled_write(PAGE_CACHE_SIZE); @@ -2136,26 +2145,34 @@ void account_page_cleaned(struct page *page, struct address_space *mapping) */ int __set_page_dirty_nobuffers(struct page *page) { + struct mem_cgroup *memcg; + + memcg = mem_cgroup_begin_page_stat(page); if (!TestSetPageDirty(page)) { struct address_space *mapping = page_mapping(page); unsigned long flags; - if (!mapping) + if (!mapping) { + mem_cgroup_end_page_stat(memcg); return 1; + } spin_lock_irqsave(&mapping->tree_lock, flags); BUG_ON(page_mapping(page) != mapping); WARN_ON_ONCE(!PagePrivate(page) && !PageUptodate(page)); - account_page_dirtied(page, mapping); + account_page_dirtied(page, mapping, memcg); radix_tree_tag_set(&mapping->page_tree, page_index(page), PAGECACHE_TAG_DIRTY); spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); + if (mapping->host) { /* !PageAnon && !swapper_space */ __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); } return 1; } + mem_cgroup_end_page_stat(memcg); return 0; } EXPORT_SYMBOL(__set_page_dirty_nobuffers); @@ -2273,8 +2290,20 @@ EXPORT_SYMBOL(set_page_dirty_lock); */ void cancel_dirty_page(struct page *page) { - if (TestClearPageDirty(page)) - account_page_cleaned(page, page_mapping(page)); + struct address_space *mapping = page_mapping(page); + + if (mapping_cap_account_dirty(mapping)) { + struct mem_cgroup *memcg; + + memcg = mem_cgroup_begin_page_stat(page); + + if (TestClearPageDirty(page)) + account_page_cleaned(page, mapping, memcg); + + mem_cgroup_end_page_stat(memcg); + } else { + ClearPageDirty(page); + } } EXPORT_SYMBOL(cancel_dirty_page); @@ -2295,6 +2324,8 @@ EXPORT_SYMBOL(cancel_dirty_page); int clear_page_dirty_for_io(struct page *page) { struct address_space *mapping = page_mapping(page); + struct mem_cgroup *memcg; + int ret = 0; BUG_ON(!PageLocked(page)); @@ -2334,13 +2365,16 @@ int clear_page_dirty_for_io(struct page *page) * always locked coming in here, so we get the desired * exclusion. */ + memcg = mem_cgroup_begin_page_stat(page); if (TestClearPageDirty(page)) { + mem_cgroup_dec_page_stat(memcg, MEM_CGROUP_STAT_DIRTY); dec_zone_page_state(page, NR_FILE_DIRTY); dec_bdi_stat(inode_to_bdi(mapping->host), BDI_RECLAIMABLE); - return 1; + ret = 1; } - return 0; + mem_cgroup_end_page_stat(memcg); + return ret; } return TestClearPageDirty(page); } diff --git a/mm/rmap.c b/mm/rmap.c index 24dd3f9fee27..8fc556ce2dcb 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -30,6 +30,8 @@ * swap_lock (in swap_duplicate, swap_info_get) * mmlist_lock (in mmput, drain_mmlist and others) * mapping->private_lock (in __set_page_dirty_buffers) + * mem_cgroup_{begin,end}_page_stat (memcg->move_lock) + * mapping->tree_lock (widely used) * inode->i_lock (in set_page_dirty's __mark_inode_dirty) * bdi.wb->list_lock (in set_page_dirty's __mark_inode_dirty) * sb_lock (within inode_lock in fs/fs-writeback.c) diff --git a/mm/truncate.c b/mm/truncate.c index 0c360259c085..76e35ad97102 100644 --- a/mm/truncate.c +++ b/mm/truncate.c @@ -510,19 +510,24 @@ EXPORT_SYMBOL(invalidate_mapping_pages); static int invalidate_complete_page2(struct address_space *mapping, struct page *page) { + struct mem_cgroup *memcg; + unsigned long flags; + if (page->mapping != mapping) return 0; if (page_has_private(page) && !try_to_release_page(page, GFP_KERNEL)) return 0; - spin_lock_irq(&mapping->tree_lock); + memcg = mem_cgroup_begin_page_stat(page); + spin_lock_irqsave(&mapping->tree_lock, flags); if (PageDirty(page)) goto failed; BUG_ON(page_has_private(page)); - __delete_from_page_cache(page, NULL); - spin_unlock_irq(&mapping->tree_lock); + __delete_from_page_cache(page, NULL, memcg); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); if (mapping->a_ops->freepage) mapping->a_ops->freepage(page); @@ -530,7 +535,8 @@ invalidate_complete_page2(struct address_space *mapping, struct page *page) page_cache_release(page); /* pagecache ref */ return 1; failed: - spin_unlock_irq(&mapping->tree_lock); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); return 0; } diff --git a/mm/vmscan.c b/mm/vmscan.c index 5e8eadd71bac..7582f9fcda92 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -579,10 +579,14 @@ static pageout_t pageout(struct page *page, struct address_space *mapping, static int __remove_mapping(struct address_space *mapping, struct page *page, bool reclaimed) { + unsigned long flags; + struct mem_cgroup *memcg; + BUG_ON(!PageLocked(page)); BUG_ON(mapping != page_mapping(page)); - spin_lock_irq(&mapping->tree_lock); + memcg = mem_cgroup_begin_page_stat(page); + spin_lock_irqsave(&mapping->tree_lock, flags); /* * The non racy check for a busy page. * @@ -620,7 +624,8 @@ static int __remove_mapping(struct address_space *mapping, struct page *page, swp_entry_t swap = { .val = page_private(page) }; mem_cgroup_swapout(page, swap); __delete_from_swap_cache(page); - spin_unlock_irq(&mapping->tree_lock); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); swapcache_free(swap); } else { void (*freepage)(struct page *); @@ -640,8 +645,9 @@ static int __remove_mapping(struct address_space *mapping, struct page *page, if (reclaimed && page_is_file_cache(page) && !mapping_exiting(mapping)) shadow = workingset_eviction(mapping, page); - __delete_from_page_cache(page, shadow); - spin_unlock_irq(&mapping->tree_lock); + __delete_from_page_cache(page, shadow, memcg); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); if (freepage != NULL) freepage(page); @@ -650,7 +656,8 @@ static int __remove_mapping(struct address_space *mapping, struct page *page, return 1; cannot_free: - spin_unlock_irq(&mapping->tree_lock); + spin_unlock_irqrestore(&mapping->tree_lock, flags); + mem_cgroup_end_page_stat(memcg); return 0; } -- cgit v1.2.3 From ba929992522b6d1f866b7021bc50da66f8fdd743 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Fri, 8 May 2015 10:11:12 +0200 Subject: target: Minimize SCSI header #include directives Only include SCSI initiator header files in target code that needs these header files, namely the SCSI pass-through code and the tcm_loop driver. Change SCSI_SENSE_BUFFERSIZE into TRANSPORT_SENSE_BUFFER in target code because the former is intended for initiator code and the latter for target code. With this patch the only initiator include directives in target code that remain are as follows: $ git grep -nHE 'include .scsi/(scsi.h|scsi_host.h|scsi_device.h|scsi_cmnd.h)' drivers/target drivers/infiniband/ulp/{isert,srpt} drivers/usb/gadget/legacy/tcm_*.[ch] drivers/{vhost,xen} include/{target,trace/events/target.h} drivers/target/loopback/tcm_loop.c:29:#include drivers/target/loopback/tcm_loop.c:31:#include drivers/target/loopback/tcm_loop.c:32:#include drivers/target/loopback/tcm_loop.c:33:#include drivers/target/target_core_pscsi.c:39:#include drivers/target/target_core_pscsi.c:40:#include drivers/xen/xen-scsiback.c:52:#include /* SG_ALL */ Signed-off-by: Bart Van Assche Reviewed-by: Christoph Hellwig Signed-off-by: James Bottomley --- Documentation/target/tcm_mod_builder.py | 7 ++----- drivers/infiniband/ulp/srpt/ib_srpt.c | 1 + drivers/infiniband/ulp/srpt/ib_srpt.h | 2 +- drivers/target/iscsi/iscsi_target.c | 2 +- drivers/target/iscsi/iscsi_target_device.c | 1 - drivers/target/iscsi/iscsi_target_tmr.c | 2 +- drivers/target/sbp/sbp_target.c | 2 +- drivers/target/target_core_alua.c | 3 +-- drivers/target/target_core_device.c | 4 ++-- drivers/target/target_core_fabric_lib.c | 2 -- drivers/target/target_core_file.c | 3 +-- drivers/target/target_core_iblock.c | 3 +-- drivers/target/target_core_pr.c | 3 +-- drivers/target/target_core_pscsi.c | 2 -- drivers/target/target_core_pscsi.h | 6 +++--- drivers/target/target_core_rd.c | 3 +-- drivers/target/target_core_sbc.c | 2 +- drivers/target/target_core_spc.c | 3 ++- drivers/target/target_core_stat.c | 3 --- drivers/target/target_core_tmr.c | 2 -- drivers/target/target_core_tpg.c | 3 +-- drivers/target/target_core_transport.c | 4 +--- drivers/target/target_core_ua.c | 3 +-- drivers/target/target_core_user.c | 5 +++-- drivers/target/target_core_xcopy.c | 3 +-- drivers/target/tcm_fc/tfc_cmd.c | 4 ---- drivers/target/tcm_fc/tfc_conf.c | 4 ---- drivers/target/tcm_fc/tfc_io.c | 4 ---- drivers/target/tcm_fc/tfc_sess.c | 4 ---- drivers/usb/gadget/legacy/tcm_usb_gadget.c | 1 - drivers/usb/gadget/legacy/tcm_usb_gadget.h | 1 - drivers/vhost/scsi.c | 3 ++- drivers/xen/xen-scsiback.c | 5 +---- include/target/iscsi/iscsi_target_core.h | 1 - include/target/target_core_base.h | 3 +-- include/trace/events/target.h | 2 +- 36 files changed, 32 insertions(+), 74 deletions(-) (limited to 'Documentation') diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py index 2ba71cea0172..6085e1f19c9d 100755 --- a/Documentation/target/tcm_mod_builder.py +++ b/Documentation/target/tcm_mod_builder.py @@ -503,11 +503,8 @@ def tcm_mod_dump_fabric_ops(proto_ident, fabric_mod_dir_var, fabric_mod_name): buf += "#include \n" buf += "#include \n" buf += "#include \n" - buf += "#include \n" - buf += "#include \n" - buf += "#include \n" - buf += "#include \n" - buf += "#include \n\n" + buf += "#include \n" + buf += "#include \n" buf += "#include \n" buf += "#include \n" buf += "#include \n\n" diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c index 9b84b4c0a000..af70d39361ec 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.c +++ b/drivers/infiniband/ulp/srpt/ib_srpt.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h index 3dae156905de..d85c0c205625 100644 --- a/drivers/infiniband/ulp/srpt/ib_srpt.h +++ b/drivers/infiniband/ulp/srpt/ib_srpt.h @@ -245,7 +245,7 @@ struct srpt_send_ioctx { u8 n_rdma; u8 n_rbuf; bool queue_status_only; - u8 sense_data[SCSI_SENSE_BUFFERSIZE]; + u8 sense_data[TRANSPORT_SENSE_BUFFER]; }; /** diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c index 34871a628b11..e0836c6e5d9e 100644 --- a/drivers/target/iscsi/iscsi_target.c +++ b/drivers/target/iscsi/iscsi_target.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/target/iscsi/iscsi_target_device.c b/drivers/target/iscsi/iscsi_target_device.c index 34c3cd1b05ce..5fabcd3d623f 100644 --- a/drivers/target/iscsi/iscsi_target_device.c +++ b/drivers/target/iscsi/iscsi_target_device.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. ******************************************************************************/ -#include #include #include diff --git a/drivers/target/iscsi/iscsi_target_tmr.c b/drivers/target/iscsi/iscsi_target_tmr.c index b0224a77e26d..fe9a582ca6af 100644 --- a/drivers/target/iscsi/iscsi_target_tmr.c +++ b/drivers/target/iscsi/iscsi_target_tmr.c @@ -17,7 +17,7 @@ ******************************************************************************/ #include -#include +#include #include #include #include diff --git a/drivers/target/sbp/sbp_target.c b/drivers/target/sbp/sbp_target.c index 18b0f9703ff2..ce81f17ad1ba 100644 --- a/drivers/target/sbp/sbp_target.c +++ b/drivers/target/sbp/sbp_target.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/target/target_core_alua.c b/drivers/target/target_core_alua.c index 75cbde1f7c5b..29904a9667a9 100644 --- a/drivers/target/target_core_alua.c +++ b/drivers/target/target_core_alua.c @@ -28,8 +28,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c index 7faa6aef9a4d..2dd7ea373c58 100644 --- a/drivers/target/target_core_device.c +++ b/drivers/target/target_core_device.c @@ -35,8 +35,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/drivers/target/target_core_fabric_lib.c b/drivers/target/target_core_fabric_lib.c index 35bfe77160d8..fdf31ef02f8a 100644 --- a/drivers/target/target_core_fabric_lib.c +++ b/drivers/target/target_core_fabric_lib.c @@ -29,8 +29,6 @@ #include #include #include -#include -#include #include #include diff --git a/drivers/target/target_core_file.c b/drivers/target/target_core_file.c index f7e6e51aed36..169f33c58102 100644 --- a/drivers/target/target_core_file.c +++ b/drivers/target/target_core_file.c @@ -31,8 +31,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_iblock.c b/drivers/target/target_core_iblock.c index 1b7947c2510f..31ed331a75dc 100644 --- a/drivers/target/target_core_iblock.c +++ b/drivers/target/target_core_iblock.c @@ -35,8 +35,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c index c1aa9655e96e..83d50b3f3e21 100644 --- a/drivers/target/target_core_pr.c +++ b/drivers/target/target_core_pr.c @@ -28,8 +28,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_pscsi.c b/drivers/target/target_core_pscsi.c index f6c954c4635f..0a3ed787b824 100644 --- a/drivers/target/target_core_pscsi.c +++ b/drivers/target/target_core_pscsi.c @@ -36,9 +36,7 @@ #include #include -#include #include -#include #include #include diff --git a/drivers/target/target_core_pscsi.h b/drivers/target/target_core_pscsi.h index 1bd757dff8ee..8fee9b0a88e2 100644 --- a/drivers/target/target_core_pscsi.h +++ b/drivers/target/target_core_pscsi.h @@ -16,13 +16,13 @@ #define PS_TIMEOUT_OTHER (500*HZ) #include -#include -#include #include #include +struct scsi_device; + struct pscsi_plugin_task { - unsigned char pscsi_sense[SCSI_SENSE_BUFFERSIZE]; + unsigned char pscsi_sense[TRANSPORT_SENSE_BUFFER]; int pscsi_direction; int pscsi_result; u32 pscsi_resid; diff --git a/drivers/target/target_core_rd.c b/drivers/target/target_core_rd.c index a263bf5fab8d..8882686a12c0 100644 --- a/drivers/target/target_core_rd.c +++ b/drivers/target/target_core_rd.c @@ -29,8 +29,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_sbc.c b/drivers/target/target_core_sbc.c index 8855781ac653..39a95ada371b 100644 --- a/drivers/target/target_core_sbc.c +++ b/drivers/target/target_core_sbc.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/target/target_core_spc.c b/drivers/target/target_core_spc.c index 7912aa124385..52ea640274f4 100644 --- a/drivers/target/target_core_spc.c +++ b/drivers/target/target_core_spc.c @@ -24,7 +24,8 @@ #include #include -#include +#include +#include #include #include diff --git a/drivers/target/target_core_stat.c b/drivers/target/target_core_stat.c index 03538994d2f7..40f6c1378041 100644 --- a/drivers/target/target_core_stat.c +++ b/drivers/target/target_core_stat.c @@ -33,9 +33,6 @@ #include #include #include -#include -#include -#include #include #include diff --git a/drivers/target/target_core_tmr.c b/drivers/target/target_core_tmr.c index 315ec3458eeb..a5bb0c46e57e 100644 --- a/drivers/target/target_core_tmr.c +++ b/drivers/target/target_core_tmr.c @@ -27,8 +27,6 @@ #include #include #include -#include -#include #include #include diff --git a/drivers/target/target_core_tpg.c b/drivers/target/target_core_tpg.c index 47f064415bf6..84de757bd458 100644 --- a/drivers/target/target_core_tpg.c +++ b/drivers/target/target_core_tpg.c @@ -32,8 +32,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c index 3fe5cb240b6f..d89793a377f7 100644 --- a/drivers/target/target_core_transport.c +++ b/drivers/target/target_core_transport.c @@ -37,9 +37,7 @@ #include #include #include -#include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_ua.c b/drivers/target/target_core_ua.c index 1738b1646988..e44cc94b12cb 100644 --- a/drivers/target/target_core_ua.c +++ b/drivers/target/target_core_ua.c @@ -25,8 +25,7 @@ #include #include -#include -#include +#include #include #include diff --git a/drivers/target/target_core_user.c b/drivers/target/target_core_user.c index dbc872a6c981..21b438ec4700 100644 --- a/drivers/target/target_core_user.c +++ b/drivers/target/target_core_user.c @@ -19,12 +19,13 @@ #include #include #include +#include #include #include -#include -#include #include #include +#include +#include #include #include #include diff --git a/drivers/target/target_core_xcopy.c b/drivers/target/target_core_xcopy.c index a600ff15dcfd..7a4486a054fc 100644 --- a/drivers/target/target_core_xcopy.c +++ b/drivers/target/target_core_xcopy.c @@ -25,8 +25,7 @@ #include #include #include -#include -#include +#include #include #include diff --git a/drivers/target/tcm_fc/tfc_cmd.c b/drivers/target/tcm_fc/tfc_cmd.c index edcafa4490c0..1bf78e7c994c 100644 --- a/drivers/target/tcm_fc/tfc_cmd.c +++ b/drivers/target/tcm_fc/tfc_cmd.c @@ -30,10 +30,6 @@ #include #include #include -#include -#include -#include -#include #include #include #include diff --git a/drivers/target/tcm_fc/tfc_conf.c b/drivers/target/tcm_fc/tfc_conf.c index 65dce1345966..86b699b94c7b 100644 --- a/drivers/target/tcm_fc/tfc_conf.c +++ b/drivers/target/tcm_fc/tfc_conf.c @@ -34,10 +34,6 @@ #include #include #include -#include -#include -#include -#include #include #include diff --git a/drivers/target/tcm_fc/tfc_io.c b/drivers/target/tcm_fc/tfc_io.c index 583e755d8091..fe585d1cce23 100644 --- a/drivers/target/tcm_fc/tfc_io.c +++ b/drivers/target/tcm_fc/tfc_io.c @@ -39,10 +39,6 @@ #include #include #include -#include -#include -#include -#include #include #include diff --git a/drivers/target/tcm_fc/tfc_sess.c b/drivers/target/tcm_fc/tfc_sess.c index ccee7e332a4d..f2a616d4f2c4 100644 --- a/drivers/target/tcm_fc/tfc_sess.c +++ b/drivers/target/tcm_fc/tfc_sess.c @@ -32,10 +32,6 @@ #include #include #include -#include -#include -#include -#include #include #include diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index 8b80addc4ce6..789b047a18ab 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.h b/drivers/usb/gadget/legacy/tcm_usb_gadget.h index 8289219925b8..9fb3544cc80f 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.h +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.h @@ -6,7 +6,6 @@ #include #include #include -#include #include #include diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c index 5e19bb53b3a9..08419756e98b 100644 --- a/drivers/vhost/scsi.c +++ b/drivers/vhost/scsi.c @@ -37,7 +37,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c index b7f51504f85a..39223c3e99ad 100644 --- a/drivers/xen/xen-scsiback.c +++ b/drivers/xen/xen-scsiback.c @@ -49,10 +49,7 @@ #include -#include -#include -#include -#include +#include /* SG_ALL */ #include #include diff --git a/include/target/iscsi/iscsi_target_core.h b/include/target/iscsi/iscsi_target_core.h index 54e7af301888..006983b296dd 100644 --- a/include/target/iscsi/iscsi_target_core.h +++ b/include/target/iscsi/iscsi_target_core.h @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h index 020377429043..aec6f6a4477c 100644 --- a/include/target/target_core_base.h +++ b/include/target/target_core_base.h @@ -6,7 +6,6 @@ #include #include #include -#include #include #include @@ -25,7 +24,7 @@ * From include/scsi/scsi_cmnd.h:SCSI_SENSE_BUFFERSIZE, currently * defined 96, but the real limit is 252 (or 260 including the header) */ -#define TRANSPORT_SENSE_BUFFER SCSI_SENSE_BUFFERSIZE +#define TRANSPORT_SENSE_BUFFER 96 /* Used by transport_send_check_condition_and_sense() */ #define SPC_SENSE_KEY_OFFSET 2 #define SPC_ADD_SENSE_LEN_OFFSET 7 diff --git a/include/trace/events/target.h b/include/trace/events/target.h index 04c3c6efdcc2..50fea660c0f8 100644 --- a/include/trace/events/target.h +++ b/include/trace/events/target.h @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include -- cgit v1.2.3 From 05545c92db9637318a98d3d59d400beb819decc7 Mon Sep 17 00:00:00 2001 From: "Seymour, Shane M" Date: Wed, 6 May 2015 01:37:20 +0000 Subject: st: implement tape statistics This patch implements tape statistics in the st module via sysfs. Current no statistics are available for tape I/O and there is no easy way to reuse the block layer statistics for tape as tape is a character device and does not have perform I/O in sector sized chunks (the size of the data written to tape can change). For tapes we also need extra stats related to things like tape movement (via other I/O). There have been multiple end users requesting statistics including AT&T (and some HP customers who have not given permission to be named). It is impossible for them to investigate any issues related to tape performance in a non-invasive way. [jejb: eliminate PRId64] Signed-off-by: Shane Seymour Tested-by: Shane Seymour Reviewed-by: Christoph Hellwig Signed-off-by: James Bottomley --- Documentation/ABI/testing/sysfs-class-scsi_tape | 109 ++++++++++ Documentation/scsi/st.txt | 59 +++++ drivers/scsi/st.c | 272 +++++++++++++++++++++++- drivers/scsi/st.h | 22 ++ 4 files changed, 461 insertions(+), 1 deletion(-) create mode 100644 Documentation/ABI/testing/sysfs-class-scsi_tape (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-scsi_tape b/Documentation/ABI/testing/sysfs-class-scsi_tape new file mode 100644 index 000000000000..9be398b87ee9 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-scsi_tape @@ -0,0 +1,109 @@ +What: /sys/class/scsi_tape/*/stats/in_flight +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Show the number of I/Os currently in-flight between the st + module and the SCSI mid-layer. +Users: + + +What: /sys/class/scsi_tape/*/stats/io_ns +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total amount of time spent waiting for all I/O + to and from the tape drive to complete. This includes all + reads, writes, and other SCSI commands issued to the tape + drive. An example of other SCSI commands would be tape + movement such as a rewind when a rewind tape device is + closed. This item is measured in nanoseconds. + + To determine the amount of time spent waiting for other I/O + to complete subtract read_ns and write_ns from this value. +Users: + + +What: /sys/class/scsi_tape/*/stats/other_cnt +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + The number of I/O requests issued to the tape drive other + than SCSI read/write requests. +Users: + + +What: /sys/class/scsi_tape/*/stats/read_byte_cnt +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total number of bytes requested from the tape drive. + This value is presented in bytes because tape drives support + variable length block sizes. +Users: + + +What: /sys/class/scsi_tape/*/stats/read_cnt +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total number of read requests issued to the tape + drive. +Users: + + +What: /sys/class/scsi_tape/*/stats/read_ns +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total amount of time in nanoseconds waiting for + read I/O requests to complete. +Users: + + +What: /sys/class/scsi_tape/*/stats/write_byte_cnt +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total number of bytes written to the tape drive. + This value is presented in bytes because tape drives support + variable length block sizes. +Users: + + +What: /sys/class/scsi_tape/*/stats/write_cnt +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total number of write requests issued to the tape + drive. +Users: + + +What: /sys/class/scsi_tape/*/stats/write_ms +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the total amount of time in nanoseconds waiting for + write I/O requests to complete. +Users: + + +What: /sys/class/scsi_tape/*/stats/resid_cnt +Date: Apr 2015 +KernelVersion: 4.2 +Contact: Shane Seymour +Description: + Shows the number of times we found that a residual >0 + was found when the SCSI midlayer indicated that there was + an error. For reads this may be a case of someone issuing + reads greater than the block size. +Users: diff --git a/Documentation/scsi/st.txt b/Documentation/scsi/st.txt index 0d5bdb153d3b..f29fa550665a 100644 --- a/Documentation/scsi/st.txt +++ b/Documentation/scsi/st.txt @@ -151,6 +151,65 @@ A link named 'tape' is made from the SCSI device directory to the class directory corresponding to the mode 0 auto-rewind device (e.g., st0). +SYSFS AND STATISTICS FOR TAPE DEVICES + +The st driver maintains statistics for tape drives inside the sysfs filesystem. +The following method can be used to locate the statistics that are +available (assuming that sysfs is mounted at /sys): + +1. Use opendir(3) on the directory /sys/class/scsi_tape +2. Use readdir(3) to read the directory contents +3. Use regcomp(3)/regexec(3) to match directory entries to the extended + regular expression "^st[0-9]+$" +4. Access the statistics from the /sys/class/scsi_tape//stats + directory (where is a directory entry from /sys/class/scsi_tape + that matched the extended regular expression) + +The reason for using this approach is that all the character devices +pointing to the same tape drive use the same statistics. That means +that st0 would have the same statistics as nst0. + +The directory contains the following statistics files: + +1. in_flight - The number of I/Os currently outstanding to this device. +2. io_ns - The amount of time spent waiting (in nanoseconds) for all I/O + to complete (including read and write). This includes tape movement + commands such as seeking between file or set marks and implicit tape + movement such as when rewind on close tape devices are used. +3. other_cnt - The number of I/Os issued to the tape drive other than read or + write commands. The time taken to complete these commands uses the + following calculation io_ms-read_ms-write_ms. +4. read_byte_cnt - The number of bytes read from the tape drive. +5. read_cnt - The number of read requests issued to the tape drive. +6. read_ns - The amount of time (in nanoseconds) spent waiting for read + requests to complete. +7. write_byte_cnt - The number of bytes written to the tape drive. +8. write_cnt - The number of write requests issued to the tape drive. +9. write_ns - The amount of time (in nanoseconds) spent waiting for write + requests to complete. +10. resid_cnt - The number of times during a read or write we found + the residual amount to be non-zero. This should mean that a program + is issuing a read larger thean the block size on tape. For write + not all data made it to tape. + +Note: The in_flight value is incremented when an I/O starts the I/O +itself is not added to the statistics until it completes. + +The total of read_cnt, write_cnt, and other_cnt may not total to the same +value as iodone_cnt at the device level. The tape statistics only count +I/O issued via the st module. + +When read the statistics may not be temporally consistent while I/O is in +progress. The individual values are read and written to atomically however +when reading them back via sysfs they may be in the process of being +updated when starting an I/O or when it is completed. + +The value shown in in_flight is incremented before any statstics are +updated and decremented when an I/O completes after updating statistics. +The value of in_flight is 0 when there are no I/Os outstanding that are +issued by the st driver. Tape statistics do not take into account any +I/O performed via the sg device. + BSD AND SYS V SEMANTICS The user can choose between these two behaviours of the tape driver by diff --git a/drivers/scsi/st.c b/drivers/scsi/st.c index 9a1c34205254..3f25b8fa921d 100644 --- a/drivers/scsi/st.c +++ b/drivers/scsi/st.c @@ -471,6 +471,47 @@ static void st_release_request(struct st_request *streq) kfree(streq); } +static void st_do_stats(struct scsi_tape *STp, struct request *req) +{ + ktime_t now; + + now = ktime_get(); + if (req->cmd[0] == WRITE_6) { + now = ktime_sub(now, STp->stats->write_time); + atomic64_add(ktime_to_ns(now), &STp->stats->tot_write_time); + atomic64_add(ktime_to_ns(now), &STp->stats->tot_io_time); + atomic64_inc(&STp->stats->write_cnt); + if (req->errors) { + atomic64_add(atomic_read(&STp->stats->last_write_size) + - STp->buffer->cmdstat.residual, + &STp->stats->write_byte_cnt); + if (STp->buffer->cmdstat.residual > 0) + atomic64_inc(&STp->stats->resid_cnt); + } else + atomic64_add(atomic_read(&STp->stats->last_write_size), + &STp->stats->write_byte_cnt); + } else if (req->cmd[0] == READ_6) { + now = ktime_sub(now, STp->stats->read_time); + atomic64_add(ktime_to_ns(now), &STp->stats->tot_read_time); + atomic64_add(ktime_to_ns(now), &STp->stats->tot_io_time); + atomic64_inc(&STp->stats->read_cnt); + if (req->errors) { + atomic64_add(atomic_read(&STp->stats->last_read_size) + - STp->buffer->cmdstat.residual, + &STp->stats->read_byte_cnt); + if (STp->buffer->cmdstat.residual > 0) + atomic64_inc(&STp->stats->resid_cnt); + } else + atomic64_add(atomic_read(&STp->stats->last_read_size), + &STp->stats->read_byte_cnt); + } else { + now = ktime_sub(now, STp->stats->other_time); + atomic64_add(ktime_to_ns(now), &STp->stats->tot_io_time); + atomic64_inc(&STp->stats->other_cnt); + } + atomic64_dec(&STp->stats->in_flight); +} + static void st_scsi_execute_end(struct request *req, int uptodate) { struct st_request *SRpnt = req->end_io_data; @@ -480,6 +521,8 @@ static void st_scsi_execute_end(struct request *req, int uptodate) STp->buffer->cmdstat.midlevel_result = SRpnt->result = req->errors; STp->buffer->cmdstat.residual = req->resid_len; + st_do_stats(STp, req); + tmp = SRpnt->bio; if (SRpnt->waiting) complete(SRpnt->waiting); @@ -496,6 +539,7 @@ static int st_scsi_execute(struct st_request *SRpnt, const unsigned char *cmd, struct rq_map_data *mdata = &SRpnt->stp->buffer->map_data; int err = 0; int write = (data_direction == DMA_TO_DEVICE); + struct scsi_tape *STp = SRpnt->stp; req = blk_get_request(SRpnt->stp->device->request_queue, write, GFP_KERNEL); @@ -516,6 +560,17 @@ static int st_scsi_execute(struct st_request *SRpnt, const unsigned char *cmd, } } + atomic64_inc(&STp->stats->in_flight); + if (cmd[0] == WRITE_6) { + atomic_set(&STp->stats->last_write_size, bufflen); + STp->stats->write_time = ktime_get(); + } else if (cmd[0] == READ_6) { + atomic_set(&STp->stats->last_read_size, bufflen); + STp->stats->read_time = ktime_get(); + } else { + STp->stats->other_time = ktime_get(); + } + SRpnt->bio = req->bio; req->cmd_len = COMMAND_SIZE(cmd[0]); memset(req->cmd, 0, BLK_MAX_CDB); @@ -4222,6 +4277,12 @@ static int st_probe(struct device *dev) } tpnt->index = error; sprintf(disk->disk_name, "st%d", tpnt->index); + tpnt->stats = kzalloc(sizeof(struct scsi_tape_stats), GFP_KERNEL); + if (tpnt->stats == NULL) { + sdev_printk(KERN_ERR, SDp, + "st: Can't allocate statistics.\n"); + goto out_idr_remove; + } dev_set_drvdata(dev, tpnt); @@ -4241,6 +4302,8 @@ static int st_probe(struct device *dev) out_remove_devs: remove_cdevs(tpnt); + kfree(tpnt->stats); +out_idr_remove: spin_lock(&st_index_lock); idr_remove(&st_index_idr, tpnt->index); spin_unlock(&st_index_lock); @@ -4298,6 +4361,7 @@ static void scsi_tape_release(struct kref *kref) disk->private_data = NULL; put_disk(disk); + kfree(tpnt->stats); kfree(tpnt); return; } @@ -4513,6 +4577,184 @@ options_show(struct device *dev, struct device_attribute *attr, char *buf) } static DEVICE_ATTR_RO(options); +/* Support for tape stats */ + +/** + * read_cnt_show - return read count - count of reads made from tape drive + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t read_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->read_cnt)); +} +static DEVICE_ATTR_RO(read_cnt); + +/** + * read_byte_cnt_show - return read byte count - tape drives + * may use blocks less than 512 bytes this gives the raw byte count of + * of data read from the tape drive. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t read_byte_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->read_byte_cnt)); +} +static DEVICE_ATTR_RO(read_byte_cnt); + +/** + * read_us_show - return read us - overall time spent waiting on reads in ns. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t read_ns_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->tot_read_time)); +} +static DEVICE_ATTR_RO(read_ns); + +/** + * write_cnt_show - write count - number of user calls + * to write(2) that have written data to tape. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t write_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->write_cnt)); +} +static DEVICE_ATTR_RO(write_cnt); + +/** + * write_byte_cnt_show - write byte count - raw count of + * bytes written to tape. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t write_byte_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->write_byte_cnt)); +} +static DEVICE_ATTR_RO(write_byte_cnt); + +/** + * write_ns_show - write ns - number of nanoseconds waiting on write + * requests to complete. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t write_ns_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->tot_write_time)); +} +static DEVICE_ATTR_RO(write_ns); + +/** + * in_flight_show - number of I/Os currently in flight - + * in most cases this will be either 0 or 1. It may be higher if someone + * has also issued other SCSI commands such as via an ioctl. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t in_flight_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->in_flight)); +} +static DEVICE_ATTR_RO(in_flight); + +/** + * io_ns_show - io wait ns - this is the number of ns spent + * waiting on all I/O to complete. This includes tape movement commands + * such as rewinding, seeking to end of file or tape, it also includes + * read and write. To determine the time spent on tape movement + * subtract the read and write ns from this value. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t io_ns_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->tot_io_time)); +} +static DEVICE_ATTR_RO(io_ns); + +/** + * other_cnt_show - other io count - this is the number of + * I/O requests other than read and write requests. + * Typically these are tape movement requests but will include driver + * tape movement. This includes only requests issued by the st driver. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t other_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->other_cnt)); +} +static DEVICE_ATTR_RO(other_cnt); + +/** + * resid_cnt_show - A count of the number of times we get a residual + * count - this should indicate someone issuing reads larger than the + * block size on tape. + * @dev: struct device + * @attr: attribute structure + * @buf: buffer to return formatted data in + */ +static ssize_t resid_cnt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct st_modedef *STm = dev_get_drvdata(dev); + + return sprintf(buf, "%lld", + (long long)atomic64_read(&STm->tape->stats->resid_cnt)); +} +static DEVICE_ATTR_RO(resid_cnt); + static struct attribute *st_dev_attrs[] = { &dev_attr_defined.attr, &dev_attr_default_blksize.attr, @@ -4521,7 +4763,35 @@ static struct attribute *st_dev_attrs[] = { &dev_attr_options.attr, NULL, }; -ATTRIBUTE_GROUPS(st_dev); + +static struct attribute *st_stats_attrs[] = { + &dev_attr_read_cnt.attr, + &dev_attr_read_byte_cnt.attr, + &dev_attr_read_ns.attr, + &dev_attr_write_cnt.attr, + &dev_attr_write_byte_cnt.attr, + &dev_attr_write_ns.attr, + &dev_attr_in_flight.attr, + &dev_attr_io_ns.attr, + &dev_attr_other_cnt.attr, + &dev_attr_resid_cnt.attr, + NULL, +}; + +static struct attribute_group stats_group = { + .name = "stats", + .attrs = st_stats_attrs, +}; + +static struct attribute_group st_group = { + .attrs = st_dev_attrs, +}; + +static const struct attribute_group *st_dev_groups[] = { + &st_group, + &stats_group, + NULL, +}; /* The following functions may be useful for a larger audience. */ static int sgl_map_user_pages(struct st_buffer *STbp, diff --git a/drivers/scsi/st.h b/drivers/scsi/st.h index f3eee0f9f40c..b6486b5d8681 100644 --- a/drivers/scsi/st.h +++ b/drivers/scsi/st.h @@ -92,6 +92,27 @@ struct st_partstat { int drv_file; }; +/* Tape statistics */ +struct scsi_tape_stats { + atomic64_t read_byte_cnt; /* bytes read */ + atomic64_t write_byte_cnt; /* bytes written */ + atomic64_t in_flight; /* Number of I/Os in flight */ + atomic64_t read_cnt; /* Count of read requests */ + atomic64_t write_cnt; /* Count of write requests */ + atomic64_t other_cnt; /* Count of other requests either + * implicit or from user space + * ioctl. */ + atomic64_t resid_cnt; /* Count of resid_len > 0 */ + atomic64_t tot_read_time; /* ktime spent completing reads */ + atomic64_t tot_write_time; /* ktime spent completing writes */ + atomic64_t tot_io_time; /* ktime spent doing any I/O */ + ktime_t read_time; /* holds ktime request was queued */ + ktime_t write_time; /* holds ktime request was queued */ + ktime_t other_time; /* holds ktime request was queued */ + atomic_t last_read_size; /* Number of bytes issued for last read */ + atomic_t last_write_size; /* Number of bytes issued for last write */ +}; + #define ST_NBR_PARTITIONS 4 /* The tape drive descriptor */ @@ -171,6 +192,7 @@ struct scsi_tape { #endif struct gendisk *disk; struct kref kref; + struct scsi_tape_stats *stats; }; /* Bit masks for use_pf */ -- cgit v1.2.3 From 61bd93ce801bb6df36eda257a9d2d16c02863cdd Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 1 Jun 2015 13:40:32 +0200 Subject: arm64: use fixmap region for permanent FDT mapping Currently, the FDT blob needs to be in the same 512 MB region as the kernel, so that it can be mapped into the kernel virtual memory space very early on using a minimal set of statically allocated translation tables. Now that we have early fixmap support, we can relax this restriction, by moving the permanent FDT mapping to the fixmap region instead. This way, the FDT blob may be anywhere in memory. This also moves the vetting of the FDT to mmu.c, since the early init code in head.S does not handle mapping of the FDT anymore. At the same time, fix up some comments in head.S that have gone stale. Reviewed-by: Mark Rutland Tested-by: Mark Rutland Signed-off-by: Ard Biesheuvel Signed-off-by: Catalin Marinas --- Documentation/arm64/booting.txt | 10 ++++--- arch/arm64/include/asm/boot.h | 14 +++++++++ arch/arm64/include/asm/fixmap.h | 15 ++++++++++ arch/arm64/include/asm/mmu.h | 1 + arch/arm64/kernel/head.S | 39 +----------------------- arch/arm64/kernel/setup.c | 30 +++++++------------ arch/arm64/mm/Makefile | 2 ++ arch/arm64/mm/init.c | 1 - arch/arm64/mm/mmu.c | 66 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 115 insertions(+), 63 deletions(-) create mode 100644 arch/arm64/include/asm/boot.h (limited to 'Documentation') diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index f3c05b5f9f08..1690350f16e7 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -45,11 +45,13 @@ sees fit.) Requirement: MANDATORY -The device tree blob (dtb) must be placed on an 8-byte boundary within -the first 512 megabytes from the start of the kernel image and must not -cross a 2-megabyte boundary. This is to allow the kernel to map the -blob using a single section mapping in the initial page tables. +The device tree blob (dtb) must be placed on an 8-byte boundary and must +not exceed 2 megabytes in size. Since the dtb will be mapped cacheable +using blocks of up to 2 megabytes in size, it must not be placed within +any 2M region which must be mapped with any specific attributes. +NOTE: versions prior to v4.2 also require that the DTB be placed within +the 512 MB region starting at text_offset bytes below the kernel Image. 3. Decompress the kernel image ------------------------------ diff --git a/arch/arm64/include/asm/boot.h b/arch/arm64/include/asm/boot.h new file mode 100644 index 000000000000..81151b67b26b --- /dev/null +++ b/arch/arm64/include/asm/boot.h @@ -0,0 +1,14 @@ + +#ifndef __ASM_BOOT_H +#define __ASM_BOOT_H + +#include + +/* + * arm64 requires the DTB to be 8 byte aligned and + * not exceed 2MB in size. + */ +#define MIN_FDT_ALIGN 8 +#define MAX_FDT_SIZE SZ_2M + +#endif diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h index 95e6b6dcbe37..c0739187a920 100644 --- a/arch/arm64/include/asm/fixmap.h +++ b/arch/arm64/include/asm/fixmap.h @@ -17,6 +17,7 @@ #ifndef __ASSEMBLY__ #include +#include #include /* @@ -32,6 +33,20 @@ */ enum fixed_addresses { FIX_HOLE, + + /* + * Reserve a virtual window for the FDT that is 2 MB larger than the + * maximum supported size, and put it at the top of the fixmap region. + * The additional space ensures that any FDT that does not exceed + * MAX_FDT_SIZE can be mapped regardless of whether it crosses any + * 2 MB alignment boundaries. + * + * Keep this at the top so it remains 2 MB aligned. + */ +#define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) + FIX_FDT_END, + FIX_FDT = FIX_FDT_END + FIX_FDT_SIZE / PAGE_SIZE - 1, + FIX_EARLYCON_MEM_BASE, FIX_TEXT_POKE0, __end_of_permanent_fixed_addresses, diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 3d311761e3c2..79fcfb048884 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -34,5 +34,6 @@ extern void init_mem_pgprot(void); extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, unsigned long virt, phys_addr_t size, pgprot_t prot); +extern void *fixmap_remap_fdt(phys_addr_t dt_phys); #endif diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 19f915e8f6e0..30cffc5e7402 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -237,8 +237,6 @@ ENTRY(stext) bl el2_setup // Drop to EL1, w20=cpu_boot_mode adrp x24, __PHYS_OFFSET bl set_cpu_boot_mode_flag - - bl __vet_fdt bl __create_page_tables // x25=TTBR0, x26=TTBR1 /* * The following calls CPU setup code, see arch/arm64/mm/proc.S for @@ -269,24 +267,6 @@ preserve_boot_args: b __inval_cache_range // tail call ENDPROC(preserve_boot_args) -/* - * Determine validity of the x21 FDT pointer. - * The dtb must be 8-byte aligned and live in the first 512M of memory. - */ -__vet_fdt: - tst x21, #0x7 - b.ne 1f - cmp x21, x24 - b.lt 1f - mov x0, #(1 << 29) - add x0, x0, x24 - cmp x21, x0 - b.ge 1f - ret -1: - mov x21, #0 - ret -ENDPROC(__vet_fdt) /* * Macro to create a table entry to the next page. * @@ -348,8 +328,7 @@ ENDPROC(__vet_fdt) * required to get the kernel running. The following sections are required: * - identity mapping to enable the MMU (low address, TTBR0) * - first few MB of the kernel linear mapping to jump to once the MMU has - * been enabled, including the FDT blob (TTBR1) - * - pgd entry for fixed mappings (TTBR1) + * been enabled */ __create_page_tables: adrp x25, idmap_pg_dir @@ -438,22 +417,6 @@ __create_page_tables: mov x3, x24 // phys offset create_block_map x0, x7, x3, x5, x6 - /* - * Map the FDT blob (maximum 2MB; must be within 512MB of - * PHYS_OFFSET). - */ - mov x3, x21 // FDT phys address - and x3, x3, #~((1 << 21) - 1) // 2MB aligned - mov x6, #PAGE_OFFSET - sub x5, x3, x24 // subtract PHYS_OFFSET - tst x5, #~((1 << 29) - 1) // within 512MB? - csel x21, xzr, x21, ne // zero the FDT pointer - b.ne 1f - add x5, x5, x6 // __va(FDT blob) - add x6, x5, #1 << 21 // 2MB for the FDT blob - sub x6, x6, #1 // inclusive range - create_block_map x0, x7, x3, x5, x6 -1: /* * Since the page tables have been populated with non-cacheable * accesses (MMU disabled), invalidate the idmap and swapper page diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 508cca1f8dce..ffd3970721bf 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -105,18 +105,6 @@ static struct resource mem_res[] = { #define kernel_code mem_res[0] #define kernel_data mem_res[1] -void __init early_print(const char *str, ...) -{ - char buf[256]; - va_list ap; - - va_start(ap, str); - vsnprintf(buf, sizeof(buf), str, ap); - va_end(ap); - - printk("%s", buf); -} - /* * The recorded values of x0 .. x3 upon kernel entry. */ @@ -326,12 +314,14 @@ static void __init setup_processor(void) static void __init setup_machine_fdt(phys_addr_t dt_phys) { - if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { - early_print("\n" - "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" - "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" - "\nPlease check your bootloader.\n", - dt_phys, phys_to_virt(dt_phys)); + void *dt_virt = fixmap_remap_fdt(dt_phys); + + if (!dt_virt || !early_init_dt_scan(dt_virt)) { + pr_crit("\n" + "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" + "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" + "\nPlease check your bootloader.", + &dt_phys, dt_virt); while (true) cpu_relax(); @@ -374,8 +364,6 @@ void __init setup_arch(char **cmdline_p) { setup_processor(); - setup_machine_fdt(__fdt_pointer); - init_mm.start_code = (unsigned long) _text; init_mm.end_code = (unsigned long) _etext; init_mm.end_data = (unsigned long) _edata; @@ -386,6 +374,8 @@ void __init setup_arch(char **cmdline_p) early_fixmap_init(); early_ioremap_init(); + setup_machine_fdt(__fdt_pointer); + parse_early_param(); /* diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile index 773d37a14039..9d84feb41a16 100644 --- a/arch/arm64/mm/Makefile +++ b/arch/arm64/mm/Makefile @@ -4,3 +4,5 @@ obj-y := dma-mapping.o extable.o fault.o init.o \ context.o proc.o pageattr.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_ARM64_PTDUMP) += dump.o + +CFLAGS_mmu.o := -I$(srctree)/scripts/dtc/libfdt/ diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 89a05f467ffb..597831bdddf3 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -170,7 +170,6 @@ void __init arm64_memblock_init(void) memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start); #endif - early_init_fdt_reserve_self(); early_init_fdt_scan_reserved_mem(); /* 4GB maximum for 32-bit only capable devices */ diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 5b8b664422d3..82d3435bf14f 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -643,3 +644,68 @@ void __set_fixmap(enum fixed_addresses idx, flush_tlb_kernel_range(addr, addr+PAGE_SIZE); } } + +void *__init fixmap_remap_fdt(phys_addr_t dt_phys) +{ + const u64 dt_virt_base = __fix_to_virt(FIX_FDT); + pgprot_t prot = PAGE_KERNEL | PTE_RDONLY; + int granularity, size, offset; + void *dt_virt; + + /* + * Check whether the physical FDT address is set and meets the minimum + * alignment requirement. Since we are relying on MIN_FDT_ALIGN to be + * at least 8 bytes so that we can always access the size field of the + * FDT header after mapping the first chunk, double check here if that + * is indeed the case. + */ + BUILD_BUG_ON(MIN_FDT_ALIGN < 8); + if (!dt_phys || dt_phys % MIN_FDT_ALIGN) + return NULL; + + /* + * Make sure that the FDT region can be mapped without the need to + * allocate additional translation table pages, so that it is safe + * to call create_mapping() this early. + * + * On 64k pages, the FDT will be mapped using PTEs, so we need to + * be in the same PMD as the rest of the fixmap. + * On 4k pages, we'll use section mappings for the FDT so we only + * have to be in the same PUD. + */ + BUILD_BUG_ON(dt_virt_base % SZ_2M); + + if (IS_ENABLED(CONFIG_ARM64_64K_PAGES)) { + BUILD_BUG_ON(__fix_to_virt(FIX_FDT_END) >> PMD_SHIFT != + __fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT); + + granularity = PAGE_SIZE; + } else { + BUILD_BUG_ON(__fix_to_virt(FIX_FDT_END) >> PUD_SHIFT != + __fix_to_virt(FIX_BTMAP_BEGIN) >> PUD_SHIFT); + + granularity = PMD_SIZE; + } + + offset = dt_phys % granularity; + dt_virt = (void *)dt_virt_base + offset; + + /* map the first chunk so we can read the size from the header */ + create_mapping(round_down(dt_phys, granularity), dt_virt_base, + granularity, prot); + + if (fdt_check_header(dt_virt) != 0) + return NULL; + + size = fdt_totalsize(dt_virt); + if (size > MAX_FDT_SIZE) + return NULL; + + if (offset + size > granularity) + create_mapping(round_down(dt_phys, granularity), dt_virt_base, + round_up(offset + size, granularity), prot); + + memblock_reserve(dt_phys, size); + + return dt_virt; +} -- cgit v1.2.3 From 451bb7fbccdc0f5d942227913afa5dea3afd12f7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 1 Jun 2015 16:09:35 -0600 Subject: EDAC, xgene: Fix cpuid abuse The new x-gene EDAC driver incorrectly tried to figure out the version of one of its IP blocks by looking at the version of the CPU core, which is only vagely related. This removes the incorrect code and instead uses the version of the IP block in the compatible string where it belongs. Found using build testing on x86, which does not provide the arm64 cpuid interface. Signed-off-by: Arnd Bergmann [ Changed subnode to "apm,xgene-edac-pmd-v2", adjusted check. ] Signed-off-by: Loc Ho Cc: devicetree@vger.kernel.org Cc: dougthompson@xmission.com Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac Cc: mark.rutland@arm.com Cc: mchehab@osg.samsung.com Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/3195065.IK73o60xya@wuerfel Signed-off-by: Borislav Petkov --- .../devicetree/bindings/edac/apm-xgene-edac.txt | 3 +- drivers/edac/xgene_edac.c | 55 ++++------------------ 2 files changed, 10 insertions(+), 48 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt index 480911c38ff9..78edb80002c8 100644 --- a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt +++ b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt @@ -25,7 +25,8 @@ Required properties for memory controller subnode: - memory-controller : Instance number of the memory controller. Required properties for PMD subnode: -- compatible : Shall be "apm,xgene-edac-pmd". +- compatible : Shall be "apm,xgene-edac-pmd" or + "apm,xgene-edac-pmd-v2". - reg : First resource shall be the PMD resource. - pmd-controller : Instance number of the PMD controller. diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c index b5158572f6ab..14636e4b6a08 100644 --- a/drivers/edac/xgene_edac.c +++ b/drivers/edac/xgene_edac.c @@ -523,6 +523,7 @@ struct xgene_edac_pmd_ctx { struct edac_device_ctl_info *edac_dev; void __iomem *pmd_csr; u32 pmd; + int version; }; static void xgene_edac_pmd_l1_check(struct edac_device_ctl_info *edac_dev, @@ -784,50 +785,6 @@ static void xgene_edac_pmd_cpu_hw_cfg(struct edac_device_ctl_info *edac_dev, writel(0x00000101, pg_f + MEMERR_CPU_MMUECR_PAGE_OFFSET); } -static bool xgene_edac_pmd_l2c_version1(void) -{ - /* Check all chips with PMD L2C version 1 HW */ - #define REVIDR_MINOR_REV(revidr) ((revidr) & 0x00000007) - - switch (MIDR_VARIANT(read_cpuid_id())) { - case 0: - switch (MIDR_REVISION(read_cpuid_id())) { - case 0: - - switch (REVIDR_MINOR_REV(read_cpuid(REVIDR_EL1))) { - case 1: - case 2: - return true; - }; - break; - case 1: - if (REVIDR_MINOR_REV(read_cpuid(REVIDR_EL1)) == 1) - return true; - break; - } - break; - case 1: - switch (MIDR_REVISION(read_cpuid_id())) { - case 0: - switch (REVIDR_MINOR_REV(read_cpuid(REVIDR_EL1))) { - case 1: - return true; - }; - break; - case 1: - switch (REVIDR_MINOR_REV(read_cpuid(REVIDR_EL1))) { - case 1: - case 0: - return true; - }; - break; - } - break; - } - - return false; -} - static void xgene_edac_pmd_hw_cfg(struct edac_device_ctl_info *edac_dev) { struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; @@ -837,7 +794,7 @@ static void xgene_edac_pmd_hw_cfg(struct edac_device_ctl_info *edac_dev) /* Enable PMD memory error - MEMERR_L2C_L2ECR and L2C_L2RTOCR */ writel(0x00000703, pg_e + MEMERR_L2C_L2ECR_PAGE_OFFSET); /* Configure L2C HW request time out feature if supported */ - if (!xgene_edac_pmd_l2c_version1()) + if (ctx->version > 1) writel(0x00000119, pg_d + CPUX_L2C_L2RTOCR_PAGE_OFFSET); } @@ -956,7 +913,8 @@ static int xgene_edac_pmd_available(u32 efuse, int pmd) return (efuse & (1 << pmd)) ? 0 : 1; } -static int xgene_edac_pmd_add(struct xgene_edac *edac, struct device_node *np) +static int xgene_edac_pmd_add(struct xgene_edac *edac, struct device_node *np, + int version) { struct edac_device_ctl_info *edac_dev; struct xgene_edac_pmd_ctx *ctx; @@ -998,6 +956,7 @@ static int xgene_edac_pmd_add(struct xgene_edac *edac, struct device_node *np) ctx->edac = edac; ctx->edac_dev = edac_dev; ctx->ddev = *edac->dev; + ctx->version = version; edac_dev->dev = &ctx->ddev; edac_dev->ctl_name = ctx->name; edac_dev->dev_name = ctx->name; @@ -1169,7 +1128,9 @@ static int xgene_edac_probe(struct platform_device *pdev) if (of_device_is_compatible(child, "apm,xgene-edac-mc")) xgene_edac_mc_add(edac, child); if (of_device_is_compatible(child, "apm,xgene-edac-pmd")) - xgene_edac_pmd_add(edac, child); + xgene_edac_pmd_add(edac, child, 1); + if (of_device_is_compatible(child, "apm,xgene-edac-pmd-v2")) + xgene_edac_pmd_add(edac, child, 2); } return 0; -- cgit v1.2.3 From bb13f0e08d16a6a303aab786b2aaf2ca76747cfb Mon Sep 17 00:00:00 2001 From: "Fang, Yang A" Date: Fri, 29 May 2015 11:56:10 -0700 Subject: ASoC: max98090: read micbias from device property This patch reads max98090 micbias from acpi or dt Signed-off-by: Fang, Yang A Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/max98090.txt | 6 ++++++ sound/soc/codecs/max98090.c | 13 ++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/max98090.txt b/Documentation/devicetree/bindings/sound/max98090.txt index aa802a274520..4e3be6682c98 100644 --- a/Documentation/devicetree/bindings/sound/max98090.txt +++ b/Documentation/devicetree/bindings/sound/max98090.txt @@ -18,6 +18,12 @@ Optional properties: - maxim,dmic-freq: Frequency at which to clock DMIC +- maxim,micbias: Micbias voltage applies to the analog mic, valid voltages value are: + 0 - 2.2v + 1 - 2.55v + 2 - 2.4v + 3 - 2.8v + Pins on the device (for linking into audio routes): * MIC1 diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index 3e33ef2acf3c..9d80c68abdd5 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -2422,6 +2422,8 @@ static int max98090_probe(struct snd_soc_codec *codec) struct max98090_cdata *cdata; enum max98090_type devtype; int ret = 0; + int err; + unsigned int micbias; dev_dbg(codec->dev, "max98090_probe\n"); @@ -2506,8 +2508,17 @@ static int max98090_probe(struct snd_soc_codec *codec) snd_soc_write(codec, M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_MASK); + err = device_property_read_u32(codec->dev, "maxim,micbias", &micbias); + if (err) { + micbias = M98090_MBVSEL_2V8; + dev_info(codec->dev, "use default 2.8v micbias\n"); + } else if (micbias < M98090_MBVSEL_2V2 || micbias > M98090_MBVSEL_2V8) { + dev_err(codec->dev, "micbias out of range 0x%x\n", micbias); + micbias = M98090_MBVSEL_2V8; + } + snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, - M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); + M98090_MBVSEL_MASK, micbias); max98090_add_widgets(codec); -- cgit v1.2.3 From c0d77c884461fc0dec0411e49797dc3f3651c31b Mon Sep 17 00:00:00 2001 From: Rafal Krypa Date: Tue, 2 Jun 2015 11:23:48 +0200 Subject: Smack: allow multiple labels in onlycap Smack onlycap allows limiting of CAP_MAC_ADMIN and CAP_MAC_OVERRIDE to processes running with the configured label. But having single privileged label is not enough in some real use cases. On a complex system like Tizen, there maybe few programs that need to configure Smack policy in run-time and running them all with a single label is not always practical. This patch extends onlycap feature for multiple labels. They are configured in the same smackfs "onlycap" interface, separated by spaces. Signed-off-by: Rafal Krypa --- Documentation/security/Smack.txt | 6 +- security/smack/smack.h | 25 +++--- security/smack/smack_access.c | 41 ++++++++++ security/smack/smackfs.c | 163 ++++++++++++++++++++++++++------------- 4 files changed, 163 insertions(+), 72 deletions(-) (limited to 'Documentation') diff --git a/Documentation/security/Smack.txt b/Documentation/security/Smack.txt index abc82f85215b..de5e1aeca7fb 100644 --- a/Documentation/security/Smack.txt +++ b/Documentation/security/Smack.txt @@ -206,11 +206,11 @@ netlabel label. The format accepted on write is: "%d.%d.%d.%d label" or "%d.%d.%d.%d/%d label". onlycap - This contains the label processes must have for CAP_MAC_ADMIN + This contains labels processes must have for CAP_MAC_ADMIN and CAP_MAC_OVERRIDE to be effective. If this file is empty these capabilities are effective at for processes with any - label. The value is set by writing the desired label to the - file or cleared by writing "-" to the file. + label. The values are set by writing the desired labels, separated + by spaces, to the file or cleared by writing "-" to the file. ptrace This is used to define the current ptrace policy 0 - default: this is the policy that relies on Smack access rules. diff --git a/security/smack/smack.h b/security/smack/smack.h index b8c1a869d85e..244e035e5a99 100644 --- a/security/smack/smack.h +++ b/security/smack/smack.h @@ -138,6 +138,11 @@ struct smk_port_label { struct smack_known *smk_out; /* outgoing label */ }; +struct smack_onlycap { + struct list_head list; + struct smack_known *smk_label; +}; + /* * Mount options */ @@ -249,6 +254,7 @@ int smk_netlbl_mls(int, char *, struct netlbl_lsm_secattr *, int); struct smack_known *smk_import_entry(const char *, int); void smk_insert_entry(struct smack_known *skp); struct smack_known *smk_find_entry(const char *); +int smack_privileged(int cap); /* * Shared data. @@ -257,7 +263,6 @@ extern int smack_enabled; extern int smack_cipso_direct; extern int smack_cipso_mapped; extern struct smack_known *smack_net_ambient; -extern struct smack_known *smack_onlycap; extern struct smack_known *smack_syslog_label; #ifdef CONFIG_SECURITY_SMACK_BRINGUP extern struct smack_known *smack_unconfined; @@ -276,6 +281,9 @@ extern struct mutex smack_known_lock; extern struct list_head smack_known_list; extern struct list_head smk_netlbladdr_list; +extern struct mutex smack_onlycap_lock; +extern struct list_head smack_onlycap_list; + #define SMACK_HASH_SLOTS 16 extern struct hlist_head smack_known_hash[SMACK_HASH_SLOTS]; @@ -331,21 +339,6 @@ static inline struct smack_known *smk_of_current(void) return smk_of_task(current_security()); } -/* - * Is the task privileged and allowed to be privileged - * by the onlycap rule. - */ -static inline int smack_privileged(int cap) -{ - struct smack_known *skp = smk_of_current(); - - if (!capable(cap)) - return 0; - if (smack_onlycap == NULL || smack_onlycap == skp) - return 1; - return 0; -} - /* * logging functions */ diff --git a/security/smack/smack_access.c b/security/smack/smack_access.c index 408e20be1ad7..00f6b38bffbd 100644 --- a/security/smack/smack_access.c +++ b/security/smack/smack_access.c @@ -617,3 +617,44 @@ struct smack_known *smack_from_secid(const u32 secid) rcu_read_unlock(); return &smack_known_invalid; } + +/* + * Unless a process is running with one of these labels + * even having CAP_MAC_OVERRIDE isn't enough to grant + * privilege to violate MAC policy. If no labels are + * designated (the empty list case) capabilities apply to + * everyone. + */ +LIST_HEAD(smack_onlycap_list); +DEFINE_MUTEX(smack_onlycap_lock); + +/* + * Is the task privileged and allowed to be privileged + * by the onlycap rule. + * + * Returns 1 if the task is allowed to be privileged, 0 if it's not. + */ +int smack_privileged(int cap) +{ + struct smack_known *skp = smk_of_current(); + struct smack_onlycap *sop; + + if (!capable(cap)) + return 0; + + rcu_read_lock(); + if (list_empty(&smack_onlycap_list)) { + rcu_read_unlock(); + return 1; + } + + list_for_each_entry_rcu(sop, &smack_onlycap_list, list) { + if (sop->smk_label == skp) { + rcu_read_unlock(); + return 1; + } + } + rcu_read_unlock(); + + return 0; +} diff --git a/security/smack/smackfs.c b/security/smack/smackfs.c index e40dc48737ff..f1c22a891b1a 100644 --- a/security/smack/smackfs.c +++ b/security/smack/smackfs.c @@ -87,16 +87,6 @@ int smack_cipso_direct = SMACK_CIPSO_DIRECT_DEFAULT; */ int smack_cipso_mapped = SMACK_CIPSO_MAPPED_DEFAULT; -/* - * Unless a process is running with this label even - * having CAP_MAC_OVERRIDE isn't enough to grant - * privilege to violate MAC policy. If no label is - * designated (the NULL case) capabilities apply to - * everyone. It is expected that the hat (^) label - * will be used if any label is used. - */ -struct smack_known *smack_onlycap; - #ifdef CONFIG_SECURITY_SMACK_BRINGUP /* * Allow one label to be unconfined. This is for @@ -1636,34 +1626,79 @@ static const struct file_operations smk_ambient_ops = { .llseek = default_llseek, }; -/** - * smk_read_onlycap - read() for smackfs/onlycap - * @filp: file pointer, not actually used - * @buf: where to put the result - * @cn: maximum to send along - * @ppos: where to start - * - * Returns number of bytes read or error code, as appropriate +/* + * Seq_file operations for /smack/onlycap */ -static ssize_t smk_read_onlycap(struct file *filp, char __user *buf, - size_t cn, loff_t *ppos) +static void *onlycap_seq_start(struct seq_file *s, loff_t *pos) { - char *smack = ""; - ssize_t rc = -EINVAL; - int asize; + return smk_seq_start(s, pos, &smack_onlycap_list); +} - if (*ppos != 0) - return 0; +static void *onlycap_seq_next(struct seq_file *s, void *v, loff_t *pos) +{ + return smk_seq_next(s, v, pos, &smack_onlycap_list); +} - if (smack_onlycap != NULL) - smack = smack_onlycap->smk_known; +static int onlycap_seq_show(struct seq_file *s, void *v) +{ + struct list_head *list = v; + struct smack_onlycap *sop = + list_entry_rcu(list, struct smack_onlycap, list); - asize = strlen(smack) + 1; + seq_puts(s, sop->smk_label->smk_known); + seq_putc(s, ' '); - if (cn >= asize) - rc = simple_read_from_buffer(buf, cn, ppos, smack, asize); + return 0; +} - return rc; +static const struct seq_operations onlycap_seq_ops = { + .start = onlycap_seq_start, + .next = onlycap_seq_next, + .show = onlycap_seq_show, + .stop = smk_seq_stop, +}; + +static int smk_open_onlycap(struct inode *inode, struct file *file) +{ + return seq_open(file, &onlycap_seq_ops); +} + +/** + * smk_list_swap_rcu - swap public list with a private one in RCU-safe way + * The caller must hold appropriate mutex to prevent concurrent modifications + * to the public list. + * Private list is assumed to be not accessible to other threads yet. + * + * @public: public list + * @private: private list + */ +static void smk_list_swap_rcu(struct list_head *public, + struct list_head *private) +{ + struct list_head *first, *last; + + if (list_empty(public)) { + list_splice_init_rcu(private, public, synchronize_rcu); + } else { + /* Remember public list before replacing it */ + first = public->next; + last = public->prev; + + /* Publish private list in place of public in RCU-safe way */ + private->prev->next = public; + private->next->prev = public; + rcu_assign_pointer(public->next, private->next); + public->prev = private->prev; + + synchronize_rcu(); + + /* When all readers are done with the old public list, + * attach it in place of private */ + private->next = first; + private->prev = last; + first->prev = private; + last->next = private; + } } /** @@ -1679,28 +1714,47 @@ static ssize_t smk_write_onlycap(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { char *data; - struct smack_known *skp = smk_of_task(current->cred->security); + char *data_parse; + char *tok; + struct smack_known *skp; + struct smack_onlycap *sop; + struct smack_onlycap *sop2; + LIST_HEAD(list_tmp); int rc = count; if (!smack_privileged(CAP_MAC_ADMIN)) return -EPERM; - /* - * This can be done using smk_access() but is done - * explicitly for clarity. The smk_access() implementation - * would use smk_access(smack_onlycap, MAY_WRITE) - */ - if (smack_onlycap != NULL && smack_onlycap != skp) - return -EPERM; - data = kzalloc(count + 1, GFP_KERNEL); if (data == NULL) return -ENOMEM; if (copy_from_user(data, buf, count) != 0) { - rc = -EFAULT; - goto freeout; + kfree(data); + return -EFAULT; + } + + data_parse = data; + while ((tok = strsep(&data_parse, " ")) != NULL) { + if (!*tok) + continue; + + skp = smk_import_entry(tok, 0); + if (IS_ERR(skp)) { + rc = PTR_ERR(skp); + break; + } + + sop = kzalloc(sizeof(*sop), GFP_KERNEL); + if (sop == NULL) { + rc = -ENOMEM; + break; + } + + sop->smk_label = skp; + list_add_rcu(&sop->list, &list_tmp); } + kfree(data); /* * Clear the smack_onlycap on invalid label errors. This means @@ -1710,26 +1764,29 @@ static ssize_t smk_write_onlycap(struct file *file, const char __user *buf, * so "-usecapabilities" will also work. * * But do so only on invalid label, not on system errors. + * The invalid label must be first to count as clearing attempt. */ - skp = smk_import_entry(data, count); - if (PTR_ERR(skp) == -EINVAL) - skp = NULL; - else if (IS_ERR(skp)) { - rc = PTR_ERR(skp); - goto freeout; + if (rc == -EINVAL && list_empty(&list_tmp)) + rc = count; + + if (rc >= 0) { + mutex_lock(&smack_onlycap_lock); + smk_list_swap_rcu(&smack_onlycap_list, &list_tmp); + mutex_unlock(&smack_onlycap_lock); } - smack_onlycap = skp; + list_for_each_entry_safe(sop, sop2, &list_tmp, list) + kfree(sop); -freeout: - kfree(data); return rc; } static const struct file_operations smk_onlycap_ops = { - .read = smk_read_onlycap, + .open = smk_open_onlycap, + .read = seq_read, .write = smk_write_onlycap, - .llseek = default_llseek, + .llseek = seq_lseek, + .release = seq_release, }; #ifdef CONFIG_SECURITY_SMACK_BRINGUP -- cgit v1.2.3 From 4c060b89c1af20b3a9d6393072ac85b4a3ccc300 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Tue, 2 Jun 2015 18:35:39 +0000 Subject: ARM: socfpga: dts: add sdram controller dt binding doc Add binding doc for Altera SOCFPGA SDRAM controller. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- .../bindings/arm/altera/socfpga-sdram-controller.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt new file mode 100644 index 000000000000..77ca635765e1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt @@ -0,0 +1,12 @@ +Altera SOCFPGA SDRAM Controller + +Required properties: +- compatible : Should contain "altr,sdr-ctl" and "syscon". + syscon is required by the Altera SOCFPGA SDRAM EDAC. +- reg : Should contain 1 register range (address and length) + +Example: + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; -- cgit v1.2.3 From 6bebe8daa6cc35853d7a3c42709594f7e225015f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 May 2015 21:20:59 +0900 Subject: of: Add vendor prefix for Hardkernel Add Hardkernel Co., Ltd. to the list of device tree vendor prefixes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..e8a00b74d8fe 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -90,6 +90,7 @@ gumstix Gumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. +hardkernel Hardkernel Co., Ltd himax Himax Technologies, Inc. hisilicon Hisilicon Limited. hit Hitachi Ltd. -- cgit v1.2.3 From 791b0bfae8408a5b7b9db621ce81bc7b3568981a Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Thu, 16 Apr 2015 14:41:11 +0300 Subject: dt/bindings: fsl/guts: Added global-utilities compatibles v3 - Addressed Scott's feedback: Added "fsl,-guts" v2 - Addressed Scott's feedback Signed-off-by: Igal Liberman Signed-off-by: Scott Wood --- Documentation/devicetree/bindings/powerpc/fsl/guts.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt index 7f150b5012cc..b71b2039e112 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt @@ -9,6 +9,11 @@ Required properties: - compatible : Should define the compatible device type for global-utilities. + Possible compatibles: + "fsl,qoriq-device-config-1.0" + "fsl,qoriq-device-config-2.0" + "fsl,-device-config" + "fsl,-guts" - reg : Offset and length of the register set for the device. Recommended properties: -- cgit v1.2.3 From e9326dea3fe76f38493d1b74999c45707fdc906d Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 17 Apr 2015 17:53:06 -0500 Subject: powerpc/qman: Change fsl,qman-channel-id to cell-index It turns out that existing U-Boots will dereference NULL pointers if the device tree does not have cell-index in the portal nodes. No patch has yet been merged adding device tree nodes for this binding (except a dtsi that has not yet been referenced), nor has any driver yet been merged making use of the binding, so it's not too late to change the binding in order to keep compatibility with existing U-Boots. Signed-off-by: Scott Wood Cc: Madalin-Cristian Bucur --- Documentation/devicetree/bindings/soc/fsl/qman-portals.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt index 48c4dae5d6f9..47e46ccbc170 100644 --- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt +++ b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt @@ -47,7 +47,7 @@ PROPERTIES For additional details about the PAMU/LIODN binding(s) see pamu.txt -- fsl,qman-channel-id +- cell-index Usage: Required Value type: Definition: The hardware index of the channel. This can also be @@ -136,7 +136,7 @@ The example below shows a (P4080) QMan portals container/bus node with two porta reg = <0x4000 0x4000>, <0x101000 0x1000>; interrupts = <106 2 0 0>; fsl,liodn = <3 4>; - fsl,qman-channel-id = <1>; + cell-index = <1>; fman0 { fsl,liodn = <0x22>; -- cgit v1.2.3 From addfda2fc2ed2fcd7896ef689aa75a7d35a7579b Mon Sep 17 00:00:00 2001 From: Stephan Mueller Date: Thu, 28 May 2015 08:52:42 +0200 Subject: crypto: doc - cover new AEAD interface The patch updates the DocBook to cover the new AEAD interface implementation. Signed-off-by: Stephan Mueller Signed-off-by: Herbert Xu --- Documentation/DocBook/crypto-API.tmpl | 23 +++++++++++++++++------ include/crypto/aead.h | 5 ++++- 2 files changed, 21 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/crypto-API.tmpl b/Documentation/DocBook/crypto-API.tmpl index 5b0551034aa1..f3fc07795620 100644 --- a/Documentation/DocBook/crypto-API.tmpl +++ b/Documentation/DocBook/crypto-API.tmpl @@ -536,8 +536,8 @@ For other use cases of AEAD ciphers, the ASCII art applies as - well, but the caller may not use the GIVCIPHER interface. In - this case, the caller must generate the IV. + well, but the caller may not use the AEAD cipher with a separate + IV generator. In this case, the caller must generate the IV. @@ -584,8 +584,8 @@ kernel crypto API | IPSEC Layer | +-----------+ | | | (1) -| givcipher | <----------------------------------- esp_output -| (seqiv) | ---+ +| aead | <----------------------------------- esp_output +| (seqniv) | ---+ +-----------+ | | (2) +-----------+ | @@ -620,8 +620,8 @@ kernel crypto API | IPSEC Layer - esp_output() invokes crypto_aead_givencrypt() to trigger an encryption - operation of the GIVCIPHER implementation. + esp_output() invokes crypto_aead_encrypt() to trigger an encryption + operation of the AEAD cipher with IV generator. @@ -1669,6 +1669,16 @@ read(opfd, out, outlen); Programming Interface + + Please note that the kernel crypto API contains the AEAD givcrypt + API (crypto_aead_giv* and aead_givcrypt_* function calls in + include/crypto/aead.h). This API is obsolete and will be removed + in the future. To obtain the functionality of an AEAD cipher with + internal IV generation, use the IV generator as a regular cipher. + For example, rfc4106(gcm(aes)) is the AEAD cipher with external + IV generation and seqniv(rfc4106(gcm(aes))) implies that the kernel + crypto API generates the IV. Different IV generators are available. + Block Cipher Context Data Structures !Pinclude/linux/crypto.h Block Cipher Context Data Structures !Finclude/crypto/aead.h aead_request @@ -1724,6 +1734,7 @@ read(opfd, out, outlen); !Finclude/crypto/aead.h aead_request_set_callback !Finclude/crypto/aead.h aead_request_set_crypt !Finclude/crypto/aead.h aead_request_set_assoc +!Finclude/crypto/aead.h aead_request_set_ad Synchronous Block Cipher API !Pinclude/linux/crypto.h Synchronous Block Cipher API diff --git a/include/crypto/aead.h b/include/crypto/aead.h index 61306ed81b8f..1a273bc5656c 100644 --- a/include/crypto/aead.h +++ b/include/crypto/aead.h @@ -50,6 +50,7 @@ /** * struct aead_request - AEAD request * @base: Common attributes for async crypto requests + * @old: Boolean whether the old or new AEAD API is used * @assoclen: Length in bytes of associated data for authentication * @cryptlen: Length of data to be encrypted or decrypted * @iv: Initialisation vector @@ -467,7 +468,9 @@ static inline void aead_request_set_callback(struct aead_request *req, * @iv: IV for the cipher operation which must comply with the IV size defined * by crypto_aead_ivsize() * - * Setting the source data and destination data scatter / gather lists. + * Setting the source data and destination data scatter / gather lists which + * hold the associated data concatenated with the plaintext or ciphertext. See + * below for the authentication tag. * * For encryption, the source is treated as the plaintext and the * destination is the ciphertext. For a decryption operation, the use is -- cgit v1.2.3 From e36f6fe1f7aa4238478d4b253aac7d3fcfff6ee0 Mon Sep 17 00:00:00 2001 From: Vaibhav Jain Date: Fri, 22 May 2015 10:56:05 +0530 Subject: cxl: Export AFU error buffer via sysfs Export the "AFU Error Buffer" via sysfs attribute (afu_err_buf). AFU error buffer is used by the AFU to report application specific errors. The contents of this buffer are AFU specific and are intended to be interpreted by the application interacting with the afu. Suggested-by: Michael Neuling Signed-off-by: Vaibhav Jain Signed-off-by: Michael Ellerman --- Documentation/ABI/testing/sysfs-class-cxl | 11 ++++++ drivers/misc/cxl/cxl.h | 7 ++++ drivers/misc/cxl/pci.c | 60 +++++++++++++++++++++++++++++++ drivers/misc/cxl/sysfs.c | 33 +++++++++++++++++ 4 files changed, 111 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl index d46bba801aac..45e9ce3075b2 100644 --- a/Documentation/ABI/testing/sysfs-class-cxl +++ b/Documentation/ABI/testing/sysfs-class-cxl @@ -6,6 +6,17 @@ Example: The real path of the attribute /sys/class/cxl/afu0.0s/irqs_max is Slave contexts (eg. /sys/class/cxl/afu0.0s): +What: /sys/class/cxl//afu_err_buf +Date: September 2014 +Contact: linuxppc-dev@lists.ozlabs.org +Description: read only + AFU Error Buffer contents. The contents of this file are + application specific and depends on the AFU being used. + Applications interacting with the AFU can use this attribute + to know about the current error condition and take appropriate + action like logging the event etc. + + What: /sys/class/cxl//irqs_max Date: September 2014 Contact: linuxppc-dev@lists.ozlabs.org diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h index 9f280e3e742e..cfee819bf5d4 100644 --- a/drivers/misc/cxl/cxl.h +++ b/drivers/misc/cxl/cxl.h @@ -360,6 +360,10 @@ struct cxl_afu { struct mutex spa_mutex; spinlock_t afu_cntl_lock; + /* AFU error buffer fields and bin attribute for sysfs */ + u64 eb_len, eb_offset; + struct bin_attribute attr_eb; + /* * Only the first part of the SPA is used for the process element * linked list. The only other part that software needs to worry about @@ -561,6 +565,9 @@ static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off); u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off); +ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf, + loff_t off, size_t count); + struct cxl_calls { void (*cxl_slbia)(struct mm_struct *mm); diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c index 1ef01647265f..c3671b3c4dcd 100644 --- a/drivers/misc/cxl/pci.c +++ b/drivers/misc/cxl/pci.c @@ -593,6 +593,22 @@ static int cxl_read_afu_descriptor(struct cxl_afu *afu) afu->crs_len = AFUD_CR_LEN(val) * 256; afu->crs_offset = AFUD_READ_CR_OFF(afu); + + /* eb_len is in multiple of 4K */ + afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; + afu->eb_offset = AFUD_READ_EB_OFF(afu); + + /* eb_off is 4K aligned so lower 12 bits are always zero */ + if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { + dev_warn(&afu->dev, + "Invalid AFU error buffer offset %Lx\n", + afu->eb_offset); + dev_info(&afu->dev, + "Ignoring AFU error buffer in the descriptor\n"); + /* indicate that no afu buffer exists */ + afu->eb_len = 0; + } + return 0; } @@ -672,6 +688,50 @@ static int sanitise_afu_regs(struct cxl_afu *afu) return 0; } +#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE +/* + * afu_eb_read: + * Called from sysfs and reads the afu error info buffer. The h/w only supports + * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte + * aligned the function uses a bounce buffer which can be max PAGE_SIZE. + */ +ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf, + loff_t off, size_t count) +{ + loff_t aligned_start, aligned_end; + size_t aligned_length; + void *tbuf; + const void __iomem *ebuf = afu->afu_desc_mmio + afu->eb_offset; + + if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) + return 0; + + /* calculate aligned read window */ + count = min((size_t)(afu->eb_len - off), count); + aligned_start = round_down(off, 8); + aligned_end = round_up(off + count, 8); + aligned_length = aligned_end - aligned_start; + + /* max we can copy in one read is PAGE_SIZE */ + if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { + aligned_length = ERR_BUFF_MAX_COPY_SIZE; + count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); + } + + /* use bounce buffer for copy */ + tbuf = (void *)__get_free_page(GFP_TEMPORARY); + if (!tbuf) + return -ENOMEM; + + /* perform aligned read from the mmio region */ + memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); + memcpy(buf, tbuf + (off & 0x7), count); + + free_page((unsigned long)tbuf); + + return count; +} + static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) { struct cxl_afu *afu; diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c index d0c38c7bc0c4..4942d55ba77f 100644 --- a/drivers/misc/cxl/sysfs.c +++ b/drivers/misc/cxl/sysfs.c @@ -356,6 +356,16 @@ static ssize_t api_version_compatible_show(struct device *device, return scnprintf(buf, PAGE_SIZE, "%i\n", CXL_API_VERSION_COMPATIBLE); } +static ssize_t afu_eb_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t off, size_t count) +{ + struct cxl_afu *afu = to_cxl_afu(container_of(kobj, + struct device, kobj)); + + return cxl_afu_read_err_buffer(afu, buf, off, count); +} + static struct device_attribute afu_attrs[] = { __ATTR_RO(mmio_size), __ATTR_RO(irqs_min), @@ -534,6 +544,10 @@ void cxl_sysfs_afu_remove(struct cxl_afu *afu) struct afu_config_record *cr, *tmp; int i; + /* remove the err buffer bin attribute */ + if (afu->eb_len) + device_remove_bin_file(&afu->dev, &afu->attr_eb); + for (i = 0; i < ARRAY_SIZE(afu_attrs); i++) device_remove_file(&afu->dev, &afu_attrs[i]); @@ -555,6 +569,22 @@ int cxl_sysfs_afu_add(struct cxl_afu *afu) goto err; } + /* conditionally create the add the binary file for error info buffer */ + if (afu->eb_len) { + afu->attr_eb.attr.name = "afu_err_buff"; + afu->attr_eb.attr.mode = S_IRUGO; + afu->attr_eb.size = afu->eb_len; + afu->attr_eb.read = afu_eb_read; + + rc = device_create_bin_file(&afu->dev, &afu->attr_eb); + if (rc) { + dev_err(&afu->dev, + "Unable to create eb attr for the afu. Err(%d)\n", + rc); + goto err; + } + } + for (i = 0; i < afu->crs_num; i++) { cr = cxl_sysfs_afu_new_cr(afu, i); if (IS_ERR(cr)) { @@ -570,6 +600,9 @@ err1: cxl_sysfs_afu_remove(afu); return rc; err: + /* reset the eb_len as we havent created the bin attr */ + afu->eb_len = 0; + for (i--; i >= 0; i--) device_remove_file(&afu->dev, &afu_attrs[i]); return rc; -- cgit v1.2.3 From aee85fb6ba766dc813ec0211a7340334b27b8f47 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 27 May 2015 16:07:01 +1000 Subject: cxl: Document external user of existing API Now that libcxl is public, let's document it. Signed-off-by: Michael Neuling Acked-by: Ian Munsie Signed-off-by: Michael Ellerman --- Documentation/ABI/testing/sysfs-class-cxl | 22 ++++++++++++++++++++++ Documentation/powerpc/cxl.txt | 4 ++++ 2 files changed, 26 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl index 45e9ce3075b2..acfe9df83139 100644 --- a/Documentation/ABI/testing/sysfs-class-cxl +++ b/Documentation/ABI/testing/sysfs-class-cxl @@ -26,6 +26,7 @@ Description: read/write that hardware can support (eg. 2037). Write values will limit userspace applications to that many userspace interrupts. Must be >= irqs_min. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//irqs_min Date: September 2014 @@ -35,6 +36,7 @@ Description: read only userspace must request on a CXL_START_WORK ioctl. Userspace may omit the num_interrupts field in the START_WORK IOCTL to get this minimum automatically. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//mmio_size Date: September 2014 @@ -42,6 +44,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Decimal value of the size of the MMIO space that may be mmaped by userspace. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//modes_supported Date: September 2014 @@ -49,6 +52,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only List of the modes this AFU supports. One per line. Valid entries are: "dedicated_process" and "afu_directed" +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//mode Date: September 2014 @@ -57,6 +61,7 @@ Description: read/write The current mode the AFU is using. Will be one of the modes given in modes_supported. Writing will change the mode provided that no user contexts are attached. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//prefault_mode @@ -70,6 +75,7 @@ Description: read/write descriptor as an effective address and prefault what it points to. all: all segments process calling START_WORK maps. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//reset Date: September 2014 @@ -77,12 +83,14 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: write only Writing 1 here will reset the AFU provided there are not contexts active on the AFU. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//api_version Date: September 2014 Contact: linuxppc-dev@lists.ozlabs.org Description: read only Decimal value of the current version of the kernel/user API. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//api_version_compatible Date: September 2014 @@ -90,6 +98,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Decimal value of the the lowest version of the userspace API this this kernel supports. +Users: https://github.com/ibm-capi/libcxl AFU configuration records (eg. /sys/class/cxl/afu0.0/cr0): @@ -103,6 +112,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Hexadecimal value of the vendor ID found in this AFU configuration record. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//cr/device Date: February 2015 @@ -110,6 +120,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Hexadecimal value of the device ID found in this AFU configuration record. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//cr/class Date: February 2015 @@ -117,6 +128,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Hexadecimal value of the class code found in this AFU configuration record. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//cr/config Date: February 2015 @@ -126,6 +138,7 @@ Description: read only record. The format is expected to match the either the standard or extended configuration space defined by the PCIe specification. +Users: https://github.com/ibm-capi/libcxl @@ -137,18 +150,21 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Decimal value of the size of the MMIO space that may be mmaped by userspace. This includes all slave contexts space also. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl/m/pp_mmio_len Date: September 2014 Contact: linuxppc-dev@lists.ozlabs.org Description: read only Decimal value of the Per Process MMIO space length. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl/m/pp_mmio_off Date: September 2014 Contact: linuxppc-dev@lists.ozlabs.org Description: read only Decimal value of the Per Process MMIO space offset. +Users: https://github.com/ibm-capi/libcxl Card info (eg. /sys/class/cxl/card0) @@ -158,12 +174,14 @@ Date: September 2014 Contact: linuxppc-dev@lists.ozlabs.org Description: read only Identifies the CAIA Version the card implements. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//psl_revision Date: September 2014 Contact: linuxppc-dev@lists.ozlabs.org Description: read only Identifies the revision level of the PSL. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//base_image Date: September 2014 @@ -173,6 +191,7 @@ Description: read only that support loadable PSLs. For FPGAs this field identifies the image contained in the on-adapter flash which is loaded during the initial program load. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//image_loaded Date: September 2014 @@ -180,6 +199,7 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: read only Will return "user" or "factory" depending on the image loaded onto the card. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//load_image_on_perst Date: December 2014 @@ -194,6 +214,7 @@ Description: read/write user or factory image to be loaded. Default is to reload on PERST whichever image the card has loaded. +Users: https://github.com/ibm-capi/libcxl What: /sys/class/cxl//reset Date: October 2014 @@ -201,3 +222,4 @@ Contact: linuxppc-dev@lists.ozlabs.org Description: write only Writing 1 will issue a PERST to card which may cause the card to reload the FPGA depending on load_image_on_perst. +Users: https://github.com/ibm-capi/libcxl diff --git a/Documentation/powerpc/cxl.txt b/Documentation/powerpc/cxl.txt index 2c71ecc519d9..2a230d01cd8c 100644 --- a/Documentation/powerpc/cxl.txt +++ b/Documentation/powerpc/cxl.txt @@ -133,6 +133,9 @@ User API The following file operations are supported on both slave and master devices. + A userspace library libcxl is avaliable here: + https://github.com/ibm-capi/libcxl + This provides a C interface to this kernel API. open ---- @@ -366,6 +369,7 @@ Sysfs Class enumeration and tuning of the accelerators. Its layout is described in Documentation/ABI/testing/sysfs-class-cxl + Udev rules ========== -- cgit v1.2.3 From ef69728f2fe52ec5786c28b1b4fa68689942ad19 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 8 May 2015 01:35:53 +0800 Subject: Document: dt: binding: imx: update document for imx7d support This part just add necessary change to boot imx7d. Update clock, pinctrl and gpt for imx7d Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../devicetree/bindings/clock/imx7d-clock.txt | 13 +++++++++++ .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 27 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx7d-clock.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.txt b/Documentation/devicetree/bindings/clock/imx7d-clock.txt new file mode 100644 index 000000000000..9d3026d81a68 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.txt @@ -0,0 +1,13 @@ +* Clock bindings for Freescale i.MX7 Dual + +Required properties: +- compatible: Should be "fsl,imx7d-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include entries "ckil", "osc" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h +for the full list of i.MX7 Dual clock IDs. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt new file mode 100644 index 000000000000..8bbf25d58656 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -0,0 +1,27 @@ +* Freescale i.MX7 Dual IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7d-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_PUS_100K_DOWN (0 << 5) +PAD_CTL_PUS_5K_UP (1 << 5) +PAD_CTL_PUS_47K_UP (2 << 5) +PAD_CTL_PUS_100K_UP (3 << 5) +PAD_CTL_PUE (1 << 4) +PAD_CTL_HYS (1 << 3) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_FAST (0 << 2) +PAD_CTL_DSE_X1 (0 << 0) +PAD_CTL_DSE_X2 (1 << 0) +PAD_CTL_DSE_X3 (2 << 0) +PAD_CTL_DSE_X4 (3 << 0) -- cgit v1.2.3 From 403e27dc1f90ce9ac4833c6d56cb08023b74e804 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:36:55 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'numa-memblock' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/vm/numa-memblock/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/numa-memblock/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/numa-memblock/arch-support.txt b/Documentation/features/vm/numa-memblock/arch-support.txt new file mode 100644 index 000000000000..e7c252a0c531 --- /dev/null +++ b/Documentation/features/vm/numa-memblock/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: numa-memblock +# Kconfig: HAVE_MEMBLOCK_NODE_MAP +# description: arch supports NUMA aware memblocks +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | .. | + | arm: | .. | + | arm64: | .. | + | avr32: | .. | + | blackfin: | .. | + | c6x: | .. | + | cris: | .. | + | frv: | .. | + | h8300: | .. | + | hexagon: | .. | + | ia64: | ok | + | m32r: | TODO | + | m68k: | .. | + | metag: | ok | + | microblaze: | ok | + | mips: | ok | + | mn10300: | TODO | + | nios2: | .. | + | openrisc: | .. | + | parisc: | .. | + | powerpc: | ok | + | s390: | ok | + | score: | ok | + | sh: | ok | + | sparc: | ok | + | tile: | TODO | + | um: | .. | + | unicore32: | .. | + | x86: | ok | + | xtensa: | .. | + ----------------------- -- cgit v1.2.3 From c197645c597f6615f7476881789ba97774dac4f5 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:36:56 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'PG_uncached' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/vm/PG_uncached/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/PG_uncached/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/PG_uncached/arch-support.txt b/Documentation/features/vm/PG_uncached/arch-support.txt new file mode 100644 index 000000000000..991974275a3e --- /dev/null +++ b/Documentation/features/vm/PG_uncached/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: PG_uncached +# Kconfig: ARCH_USES_PG_UNCACHED +# description: arch supports the PG_uncached page flag +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From b85c92c32739bc6dacb8e1f89a760d4ccf095a0d Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:36:57 +0200 Subject: Documentation/features/lib: Add feature description and arch support status file for 'strncasecmp' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/lib/strncasecmp/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/lib/strncasecmp/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/lib/strncasecmp/arch-support.txt b/Documentation/features/lib/strncasecmp/arch-support.txt new file mode 100644 index 000000000000..12b1c9358e57 --- /dev/null +++ b/Documentation/features/lib/strncasecmp/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: strncasecmp +# Kconfig: __HAVE_ARCH_STRNCASECMP +# description: arch provides an optimized strncasecmp() function +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | TODO | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 6c7cca4dc10950ee299ef2cb1db81733679380df Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:36:59 +0200 Subject: Documentation/features/io: Add feature description and arch support status file for 'sg-chain' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/io/sg-chain/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/io/sg-chain/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/io/sg-chain/arch-support.txt b/Documentation/features/io/sg-chain/arch-support.txt new file mode 100644 index 000000000000..b9b675539b9d --- /dev/null +++ b/Documentation/features/io/sg-chain/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: sg-chain +# Kconfig: ARCH_HAS_SG_CHAIN +# description: arch supports chained scatter-gather lists +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | ok | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From bebcfbb0ceb5228f5931f6869a72b6e92ea10592 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:00 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'huge-vmap' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/vm/huge-vmap/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/huge-vmap/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/huge-vmap/arch-support.txt b/Documentation/features/vm/huge-vmap/arch-support.txt new file mode 100644 index 000000000000..af6816bccb43 --- /dev/null +++ b/Documentation/features/vm/huge-vmap/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: huge-vmap +# Kconfig: HAVE_ARCH_HUGE_VMAP +# description: arch supports the ioremap_pud_enabled() and ioremap_pmd_enabled() VM APIs +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From f643e6a69a60d1f91bc4bc0375ae2d065081f61b Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:01 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'pte_special' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/vm/pte_special/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/pte_special/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/pte_special/arch-support.txt b/Documentation/features/vm/pte_special/arch-support.txt new file mode 100644 index 000000000000..aaaa21db6226 --- /dev/null +++ b/Documentation/features/vm/pte_special/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: pte_special +# Kconfig: __HAVE_ARCH_PTE_SPECIAL +# description: arch supports the pte_special()/pte_mkspecial() VM APIs +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 61e06e71ccbba66c652ab741d43a9c9d0fd6a5a9 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:02 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'pmdp_splitting_flush' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../vm/pmdp_splitting_flush/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/pmdp_splitting_flush/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/pmdp_splitting_flush/arch-support.txt b/Documentation/features/vm/pmdp_splitting_flush/arch-support.txt new file mode 100644 index 000000000000..26f74b457e0b --- /dev/null +++ b/Documentation/features/vm/pmdp_splitting_flush/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: pmdp_splitting_flush +# Kconfig: __HAVE_ARCH_PMDP_SPLITTING_FLUSH +# description: arch supports the pmdp_splitting_flush() VM API +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 2729924765bcfa9e4cf7595c49b472b561413255 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:03 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'KASAN' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/debug/KASAN/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/KASAN/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt new file mode 100644 index 000000000000..14531da2fb54 --- /dev/null +++ b/Documentation/features/debug/KASAN/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: KASAN +# Kconfig: HAVE_ARCH_KASAN +# description: arch supports the KASAN runtime memory checker +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 44121b9ed0384088a6899cfb2ca4ede1428d412f Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:04 +0200 Subject: Documentation/features/time: Add feature description and arch support status file for 'modern-timekeeping' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../time/modern-timekeeping/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/time/modern-timekeeping/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/time/modern-timekeeping/arch-support.txt b/Documentation/features/time/modern-timekeeping/arch-support.txt new file mode 100644 index 000000000000..17f68a02e84d --- /dev/null +++ b/Documentation/features/time/modern-timekeeping/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: modern-timekeeping +# Kconfig: !ARCH_USES_GETTIMEOFFSET +# description: arch does not use arch_gettimeoffset() anymore +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | ok | + | arc: | ok | + | arm: | TODO | + | arm64: | ok | + | avr32: | ok | + | blackfin: | TODO | + | c6x: | ok | + | cris: | TODO | + | frv: | ok | + | h8300: | ok | + | hexagon: | ok | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | ok | + | microblaze: | ok | + | mips: | ok | + | mn10300: | ok | + | nios2: | ok | + | openrisc: | ok | + | parisc: | ok | + | powerpc: | ok | + | s390: | ok | + | score: | ok | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | ok | + | unicore32: | ok | + | x86: | ok | + | xtensa: | ok | + ----------------------- -- cgit v1.2.3 From 4e3cd4571904933300620f5464872c4e10d3bd4a Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:05 +0200 Subject: Documentation/features/time: Add feature description and arch support status file for 'virt-cpuacct' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/time/virt-cpuacct/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/time/virt-cpuacct/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/time/virt-cpuacct/arch-support.txt b/Documentation/features/time/virt-cpuacct/arch-support.txt new file mode 100644 index 000000000000..cf3c3e383d15 --- /dev/null +++ b/Documentation/features/time/virt-cpuacct/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: virt-cpuacct +# Kconfig: HAVE_VIRT_CPU_ACCOUNTING +# description: arch supports precise virtual CPU time accounting +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | ok | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | ok | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 1aebadbca627c8840adcf78e68a9ab81c6490307 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:07 +0200 Subject: Documentation/features/time: Add feature description and arch support status file for 'irq-time-acct' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/time/irq-time-acct/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/time/irq-time-acct/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/time/irq-time-acct/arch-support.txt b/Documentation/features/time/irq-time-acct/arch-support.txt new file mode 100644 index 000000000000..e63316239938 --- /dev/null +++ b/Documentation/features/time/irq-time-acct/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: irq-time-acct +# Kconfig: HAVE_IRQ_TIME_ACCOUNTING +# description: arch supports precise IRQ time accounting +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | .. | + | arc: | TODO | + | arm: | ok | + | arm64: | .. | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | .. | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | .. | + | powerpc: | .. | + | s390: | .. | + | score: | TODO | + | sh: | TODO | + | sparc: | .. | + | tile: | .. | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | ok | + ----------------------- -- cgit v1.2.3 From cc436a080ad45a0d98c5a37a4fd9c896ea6bcd8a Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:09 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'THP' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- Documentation/features/vm/THP/arch-support.txt | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/THP/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/THP/arch-support.txt b/Documentation/features/vm/THP/arch-support.txt new file mode 100644 index 000000000000..972d02c2a74c --- /dev/null +++ b/Documentation/features/vm/THP/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: THP +# Kconfig: HAVE_ARCH_TRANSPARENT_HUGEPAGE +# description: arch supports transparent hugepages +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | .. | + | arm: | ok | + | arm64: | ok | + | avr32: | .. | + | blackfin: | .. | + | c6x: | .. | + | cris: | .. | + | frv: | .. | + | h8300: | .. | + | hexagon: | .. | + | ia64: | TODO | + | m32r: | .. | + | m68k: | .. | + | metag: | .. | + | microblaze: | .. | + | mips: | ok | + | mn10300: | .. | + | nios2: | .. | + | openrisc: | .. | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | .. | + | sh: | .. | + | sparc: | ok | + | tile: | TODO | + | um: | .. | + | unicore32: | .. | + | x86: | ok | + | xtensa: | .. | + ----------------------- -- cgit v1.2.3 From a521dc564bcce456354a01d2603ff946af141d32 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:10 +0200 Subject: Documentation/features/locking: Add feature description and arch support status file for 'rwsem-optimized' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../locking/rwsem-optimized/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/locking/rwsem-optimized/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/locking/rwsem-optimized/arch-support.txt b/Documentation/features/locking/rwsem-optimized/arch-support.txt new file mode 100644 index 000000000000..ac93d7ab66c4 --- /dev/null +++ b/Documentation/features/locking/rwsem-optimized/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: rwsem-optimized +# Kconfig: Optimized asm/rwsem.h +# description: arch provides optimized rwsem APIs +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | ok | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | ok | + ----------------------- -- cgit v1.2.3 From 65ee8aeb3759908606486248363026cc9b734d9e Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:12 +0200 Subject: Documentation/features/sched: Add feature description and arch support status file for 'numa-balancing' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/sched/numa-balancing/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/sched/numa-balancing/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/sched/numa-balancing/arch-support.txt b/Documentation/features/sched/numa-balancing/arch-support.txt new file mode 100644 index 000000000000..ac7cd6b1502b --- /dev/null +++ b/Documentation/features/sched/numa-balancing/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: numa-balancing +# Kconfig: ARCH_SUPPORTS_NUMA_BALANCING +# description: arch supports NUMA balancing +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | .. | + | arm: | .. | + | arm64: | .. | + | avr32: | .. | + | blackfin: | .. | + | c6x: | .. | + | cris: | .. | + | frv: | .. | + | h8300: | .. | + | hexagon: | .. | + | ia64: | TODO | + | m32r: | .. | + | m68k: | .. | + | metag: | .. | + | microblaze: | .. | + | mips: | TODO | + | mn10300: | .. | + | nios2: | .. | + | openrisc: | .. | + | parisc: | .. | + | powerpc: | ok | + | s390: | .. | + | score: | .. | + | sh: | .. | + | sparc: | TODO | + | tile: | TODO | + | um: | .. | + | unicore32: | .. | + | x86: | ok | + | xtensa: | .. | + ----------------------- -- cgit v1.2.3 From cd66af211609bb0cc2ab2f32412be41a7481f211 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:13 +0200 Subject: Documentation/features/io: Add feature description and arch support status file for 'dma-contiguous' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/io/dma-contiguous/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/io/dma-contiguous/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt new file mode 100644 index 000000000000..a97e8e3f4ebb --- /dev/null +++ b/Documentation/features/io/dma-contiguous/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: dma-contiguous +# Kconfig: HAVE_DMA_CONTIGUOUS +# description: arch supports the DMA CMA (continuous memory allocator) +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 3c1b5142691f094591b6c1d6e7a9fc5599409c28 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:14 +0200 Subject: Documentation/features/io: Add feature description and arch support status file for 'dma_map_attrs' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/io/dma_map_attrs/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/io/dma_map_attrs/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/io/dma_map_attrs/arch-support.txt b/Documentation/features/io/dma_map_attrs/arch-support.txt new file mode 100644 index 000000000000..51d0f1c02a3e --- /dev/null +++ b/Documentation/features/io/dma_map_attrs/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: dma_map_attrs +# Kconfig: HAVE_DMA_ATTRS +# description: arch provides dma_*map*_attrs() APIs +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | ok | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | ok | + | hexagon: | ok | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | ok | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | ok | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | ok | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From f58519e9f7d65c41c17944e25d5343a07454b3a7 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:15 +0200 Subject: Documentation/features/core: Add feature description and arch support status file for 'tracehook' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/core/tracehook/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/core/tracehook/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/core/tracehook/arch-support.txt b/Documentation/features/core/tracehook/arch-support.txt new file mode 100644 index 000000000000..728061d763b1 --- /dev/null +++ b/Documentation/features/core/tracehook/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: tracehook +# Kconfig: HAVE_ARCH_TRACEHOOK +# description: arch supports tracehook (ptrace) register handling APIs +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | ok | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | ok | + | c6x: | ok | + | cris: | TODO | + | frv: | ok | + | h8300: | TODO | + | hexagon: | ok | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | ok | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | ok | + | nios2: | ok | + | openrisc: | ok | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From c0512abd5a3fef006975e8e9bb15b1eb99d12d79 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:16 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'ioremap_prot' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/vm/ioremap_prot/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/ioremap_prot/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt new file mode 100644 index 000000000000..90c53749fde7 --- /dev/null +++ b/Documentation/features/vm/ioremap_prot/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: ioremap_prot +# Kconfig: HAVE_IOREMAP_PROT +# description: arch has ioremap_prot() +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | ok | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | TODO | + | score: | TODO | + | sh: | ok | + | sparc: | TODO | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 41b8ea4be1c2fbd152c413d68877318e3a1c76a0 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:17 +0200 Subject: Documentation/features/locking: Add feature description and arch support status file for 'lockdep' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/locking/lockdep/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/locking/lockdep/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/locking/lockdep/arch-support.txt b/Documentation/features/locking/lockdep/arch-support.txt new file mode 100644 index 000000000000..cf90635bdcbb --- /dev/null +++ b/Documentation/features/locking/lockdep/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: lockdep +# Kconfig: LOCKDEP_SUPPORT +# description: arch supports the runtime locking correctness debug facility +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | ok | + | arm: | ok | + | arm64: | ok | + | avr32: | ok | + | blackfin: | ok | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | ok | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | ok | + | microblaze: | ok | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | ok | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | ok | + | unicore32: | ok | + | x86: | ok | + | xtensa: | ok | + ----------------------- -- cgit v1.2.3 From 6d6b54cb2187df8b09ce40012648606508be9b18 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:18 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'stackprotector' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/debug/stackprotector/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/stackprotector/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/stackprotector/arch-support.txt b/Documentation/features/debug/stackprotector/arch-support.txt new file mode 100644 index 000000000000..0fa423313409 --- /dev/null +++ b/Documentation/features/debug/stackprotector/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: stackprotector +# Kconfig: HAVE_CC_STACKPROTECTOR +# description: arch supports compiler driven stack overflow protection +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | ok | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From d8affc78130a87ea6a4027d6a8ede91486bfef27 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:19 +0200 Subject: Documentation/features/core: Add feature description and arch support status file for 'jump-labels' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/core/jump-labels/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/core/jump-labels/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Documentation/features/core/jump-labels/arch-support.txt new file mode 100644 index 000000000000..136868b636e6 --- /dev/null +++ b/Documentation/features/core/jump-labels/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: jump-labels +# Kconfig: HAVE_ARCH_JUMP_LABEL +# description: arch supports live patched, high efficiency branches +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | ok | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 5b8473a6d7d08e9da9bd132c6e8ce12b8cfdbf5f Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:21 +0200 Subject: Documentation/features/seccomp: Add feature description and arch support status file for 'seccomp-filter' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../seccomp/seccomp-filter/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/seccomp/seccomp-filter/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt new file mode 100644 index 000000000000..bea800910342 --- /dev/null +++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: seccomp-filter +# Kconfig: HAVE_ARCH_SECCOMP_FILTER +# description: arch supports seccomp filters +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 9df43ac1858ecddd8d380e08263302490232d7ea Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:22 +0200 Subject: Documentation/features/time: Add feature description and arch support status file for 'context-tracking' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../time/context-tracking/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/time/context-tracking/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt new file mode 100644 index 000000000000..a1e3eea7003f --- /dev/null +++ b/Documentation/features/time/context-tracking/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: context-tracking +# Kconfig: HAVE_CONTEXT_TRACKING +# description: arch supports context tracking for NO_HZ_FULL +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 47af18fea1a47aa98f416bc6ba9d67ca557859ab Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:23 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'kgdb' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- Documentation/features/debug/kgdb/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/kgdb/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/kgdb/arch-support.txt b/Documentation/features/debug/kgdb/arch-support.txt new file mode 100644 index 000000000000..862e15d6f79e --- /dev/null +++ b/Documentation/features/debug/kgdb/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: kgdb +# Kconfig: HAVE_ARCH_KGDB +# description: arch supports the kGDB kernel debugger +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | ok | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | ok | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | ok | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | ok | + | mips: | ok | + | mn10300: | ok | + | nios2: | ok | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | TODO | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 28dfffd6d14f9cb2277e9bead011e8d510e2c4fa Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:24 +0200 Subject: Documentation/features/time: Add feature description and arch support status file for 'clockevents' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/time/clockevents/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/time/clockevents/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt new file mode 100644 index 000000000000..ff670b2207f1 --- /dev/null +++ b/Documentation/features/time/clockevents/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: clockevents +# Kconfig: GENERIC_CLOCKEVENTS +# description: arch support generic clock events +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | ok | + | arc: | ok | + | arm: | ok | + | arm64: | ok | + | avr32: | ok | + | blackfin: | ok | + | c6x: | ok | + | cris: | ok | + | frv: | TODO | + | h8300: | ok | + | hexagon: | ok | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | ok | + | metag: | ok | + | microblaze: | ok | + | mips: | ok | + | mn10300: | ok | + | nios2: | ok | + | openrisc: | ok | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | ok | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | ok | + | unicore32: | ok | + | x86: | ok | + | xtensa: | ok | + ----------------------- -- cgit v1.2.3 From 343163ca15954bcd926ced32616821d540612104 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:25 +0200 Subject: Documentation/features/vm: Add feature description and arch support status file for 'ELF-ASLR' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/vm/ELF-ASLR/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/vm/ELF-ASLR/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/vm/ELF-ASLR/arch-support.txt b/Documentation/features/vm/ELF-ASLR/arch-support.txt new file mode 100644 index 000000000000..ec4dd28e1297 --- /dev/null +++ b/Documentation/features/vm/ELF-ASLR/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: ELF-ASLR +# Kconfig: ARCH_HAS_ELF_RANDOMIZE +# description: arch randomizes the stack, heap and binary images of ELF binaries +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 6a6787724dc21925f6d289c9a019ed6026db5183 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:26 +0200 Subject: Documentation/features/time: Add feature description and arch support status file for 'arch-tick-broadcast' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../time/arch-tick-broadcast/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/time/arch-tick-broadcast/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/time/arch-tick-broadcast/arch-support.txt b/Documentation/features/time/arch-tick-broadcast/arch-support.txt new file mode 100644 index 000000000000..8acb439a4a17 --- /dev/null +++ b/Documentation/features/time/arch-tick-broadcast/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: arch-tick-broadcast +# Kconfig: ARCH_HAS_TICK_BROADCAST +# description: arch provides tick_broadcast() +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | TODO | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From fd7d6cee93aae351b671621ad9024a8f09214284 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:27 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'kprobes' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/debug/kprobes/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/kprobes/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/kprobes/arch-support.txt b/Documentation/features/debug/kprobes/arch-support.txt new file mode 100644 index 000000000000..a44bfff6940b --- /dev/null +++ b/Documentation/features/debug/kprobes/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: kprobes +# Kconfig: HAVE_KPROBES +# description: arch supports live patched kernel probe +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | ok | + | arm: | ok | + | arm64: | TODO | + | avr32: | ok | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 08716c0da7d6f3f7888dfc2980aec6ec226ddd2d Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:28 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'optprobes' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/debug/optprobes/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/optprobes/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/optprobes/arch-support.txt b/Documentation/features/debug/optprobes/arch-support.txt new file mode 100644 index 000000000000..b8999d8544ca --- /dev/null +++ b/Documentation/features/debug/optprobes/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: optprobes +# Kconfig: HAVE_OPTPROBES +# description: arch supports live patched optprobes +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 9cf5bcc3ddc4f291f54e680b75ad3957e2d468f9 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:29 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'kprobes-on-ftrace' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../debug/kprobes-on-ftrace/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/kprobes-on-ftrace/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt new file mode 100644 index 000000000000..40f44d041fb4 --- /dev/null +++ b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: kprobes-on-ftrace +# Kconfig: HAVE_KPROBES_ON_FTRACE +# description: arch supports combined kprobes and ftrace live patching +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 138943ea3aa2b69960250c218637468bb157f49c Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:31 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'uprobes' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/debug/uprobes/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/uprobes/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/uprobes/arch-support.txt b/Documentation/features/debug/uprobes/arch-support.txt new file mode 100644 index 000000000000..4efe36c3ace9 --- /dev/null +++ b/Documentation/features/debug/uprobes/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: uprobes +# Kconfig: ARCH_SUPPORTS_UPROBES +# description: arch supports live patched user probes +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From a382c9694c2a8fb0d9525fa3289c1c7eeee73ae8 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:32 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'kretprobes' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/debug/kretprobes/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/kretprobes/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/kretprobes/arch-support.txt b/Documentation/features/debug/kretprobes/arch-support.txt new file mode 100644 index 000000000000..d87c1ce24204 --- /dev/null +++ b/Documentation/features/debug/kretprobes/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: kretprobes +# Kconfig: HAVE_KRETPROBES +# description: arch supports kernel function-return probes +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | ok | + | arm: | ok | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 5d5cd30e6a897fead07639d9684e9c6910e2527c Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:33 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'user-ret-profiler' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../debug/user-ret-profiler/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/user-ret-profiler/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/user-ret-profiler/arch-support.txt b/Documentation/features/debug/user-ret-profiler/arch-support.txt new file mode 100644 index 000000000000..44cc1ff3f603 --- /dev/null +++ b/Documentation/features/debug/user-ret-profiler/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: user-ret-profiler +# Kconfig: HAVE_USER_RETURN_NOTIFIER +# description: arch supports user-space return from system call profiler +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 8fa369c0485c843f93045974e2a93cdc09828db1 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:34 +0200 Subject: Documentation/features/core: Add feature description and arch support status file for 'generic-idle-thread' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../core/generic-idle-thread/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/core/generic-idle-thread/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt new file mode 100644 index 000000000000..6d930fcbe519 --- /dev/null +++ b/Documentation/features/core/generic-idle-thread/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: generic-idle-thread +# Kconfig: GENERIC_SMP_IDLE_THREAD +# description: arch makes use of the generic SMP idle thread facility +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | ok | + | arc: | ok | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | ok | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | ok | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | ok | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | ok | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | ok | + ----------------------- -- cgit v1.2.3 From 8994f7bbe2110dd6fec24f8474392d105d99b253 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:35 +0200 Subject: Documentation/features/perf: Add feature description and arch support status file for 'kprobes-event' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/perf/kprobes-event/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/perf/kprobes-event/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt b/Documentation/features/perf/kprobes-event/arch-support.txt new file mode 100644 index 000000000000..9855ad044386 --- /dev/null +++ b/Documentation/features/perf/kprobes-event/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: kprobes-event +# Kconfig: HAVE_REGS_AND_STACK_ACCESS_API +# description: arch supports kprobes with perf events +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | ok | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | TODO | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 318d10dd83d0c61422f544f9be2634663e094a2c Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:36 +0200 Subject: Documentation/features/io: Add feature description and arch support status file for 'dma-api-debug' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/io/dma-api-debug/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/io/dma-api-debug/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/io/dma-api-debug/arch-support.txt b/Documentation/features/io/dma-api-debug/arch-support.txt new file mode 100644 index 000000000000..4f4a3443b114 --- /dev/null +++ b/Documentation/features/io/dma-api-debug/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: dma-api-debug +# Kconfig: HAVE_DMA_API_DEBUG +# description: arch supports DMA debug facilities +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | ok | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | ok | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | ok | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | ok | + | tile: | ok | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From e30119a9dab9d407a6cd1143fb2ba6620719abe2 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:37 +0200 Subject: Documentation/features/perf: Add feature description and arch support status file for 'perf-regs' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/perf/perf-regs/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/perf/perf-regs/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/perf/perf-regs/arch-support.txt b/Documentation/features/perf/perf-regs/arch-support.txt new file mode 100644 index 000000000000..e2b4a78ec543 --- /dev/null +++ b/Documentation/features/perf/perf-regs/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: perf-regs +# Kconfig: HAVE_PERF_REGS +# description: arch supports perf events register access +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 05934cad2dd9c4b36261352d2933cc9c2b679f0c Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:38 +0200 Subject: Documentation/features/perf: Add feature description and arch support status file for 'perf-stackdump' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/perf/perf-stackdump/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/perf/perf-stackdump/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/perf/perf-stackdump/arch-support.txt b/Documentation/features/perf/perf-stackdump/arch-support.txt new file mode 100644 index 000000000000..3dc24b0673c0 --- /dev/null +++ b/Documentation/features/perf/perf-stackdump/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: perf-stackdump +# Kconfig: HAVE_PERF_USER_STACK_DUMP +# description: arch supports perf events stack dumps +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 98008be7e87ffc825551bdafad706de10a61f5bc Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:39 +0200 Subject: Documentation/features/locking: Add feature description and arch support status file for 'cmpxchg-local' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../locking/cmpxchg-local/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/locking/cmpxchg-local/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt new file mode 100644 index 000000000000..d9c310889bc1 --- /dev/null +++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: cmpxchg-local +# Kconfig: HAVE_CMPXCHG_LOCAL +# description: arch supports the this_cpu_cmpxchg() API +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 5fac5f55f3fd4d9e639778c0d6e412d8ff0b5528 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:40 +0200 Subject: Documentation/features/debug: Add feature description and arch support status file for 'gcov-profile-all' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../debug/gcov-profile-all/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/debug/gcov-profile-all/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt new file mode 100644 index 000000000000..38dea8eeba0a --- /dev/null +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: gcov-profile-all +# Kconfig: ARCH_HAS_GCOV_PROFILE_ALL +# description: arch supports whole-kernel GCOV code coverage profiling +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | ok | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | ok | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 33006fae4bd7633ba4486a3cf64ad1cd1e8aa093 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:42 +0200 Subject: Documentation/features/locking: Add feature description and arch support status file for 'queued-spinlocks' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../locking/queued-spinlocks/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/locking/queued-spinlocks/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt b/Documentation/features/locking/queued-spinlocks/arch-support.txt new file mode 100644 index 000000000000..e973b1a9572f --- /dev/null +++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: queued-spinlocks +# Kconfig: ARCH_USE_QUEUED_SPINLOCKS +# description: arch supports queued spinlocks +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 2eda9972bbd12b9feb92ec057deac8e8846e650d Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:43 +0200 Subject: Documentation/features/locking: Add feature description and arch support status file for 'queued-rwlocks' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../locking/queued-rwlocks/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/locking/queued-rwlocks/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/locking/queued-rwlocks/arch-support.txt b/Documentation/features/locking/queued-rwlocks/arch-support.txt new file mode 100644 index 000000000000..68c3a5ddd9b9 --- /dev/null +++ b/Documentation/features/locking/queued-rwlocks/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: queued-rwlocks +# Kconfig: ARCH_USE_QUEUED_RWLOCKS +# description: arch supports queued rwlocks +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | TODO | + | arm64: | TODO | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | TODO | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | TODO | + | s390: | TODO | + | score: | TODO | + | sh: | TODO | + | sparc: | TODO | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From b07b6ecc01fa435d1c5d3fc50ee675ed36dd89d5 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:37:44 +0200 Subject: Documentation/features/core: Add feature description and arch support status file for 'BPF-JIT' Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- .../features/core/BPF-JIT/arch-support.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/features/core/BPF-JIT/arch-support.txt (limited to 'Documentation') diff --git a/Documentation/features/core/BPF-JIT/arch-support.txt b/Documentation/features/core/BPF-JIT/arch-support.txt new file mode 100644 index 000000000000..c1b4f917238f --- /dev/null +++ b/Documentation/features/core/BPF-JIT/arch-support.txt @@ -0,0 +1,40 @@ +# +# Feature name: BPF-JIT +# Kconfig: HAVE_BPF_JIT +# description: arch supports BPF JIT optimizations +# + ----------------------- + | arch |status| + ----------------------- + | alpha: | TODO | + | arc: | TODO | + | arm: | ok | + | arm64: | ok | + | avr32: | TODO | + | blackfin: | TODO | + | c6x: | TODO | + | cris: | TODO | + | frv: | TODO | + | h8300: | TODO | + | hexagon: | TODO | + | ia64: | TODO | + | m32r: | TODO | + | m68k: | TODO | + | metag: | TODO | + | microblaze: | TODO | + | mips: | ok | + | mn10300: | TODO | + | nios2: | TODO | + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | + | s390: | ok | + | score: | TODO | + | sh: | TODO | + | sparc: | ok | + | tile: | TODO | + | um: | TODO | + | unicore32: | TODO | + | x86: | ok | + | xtensa: | TODO | + ----------------------- -- cgit v1.2.3 From 669f6f96c680a741257ada44a28b580df2e1fc25 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Wed, 3 Jun 2015 12:39:26 +0200 Subject: Documentation/features: Explain kernel feature descriptions and add visualization script The previous patches added arch support matrices for more than 40 generic kernel features that need per architecture support. The structure of the feature descriptions is the following: Each feature has its own directory under Documentation/features/subsystem_name/feature_name/, and the arch-support.txt file shows its current arch porting status. For example, lockdep support is shown the following way: triton:~/tip> cat Documentation/features/locking/lockdep/arch-support.txt # # Feature name: lockdep # Kconfig: LOCKDEP_SUPPORT # description: arch supports the runtime locking correctness debug facility # ----------------------- | arch |status| ----------------------- | alpha: | TODO | | arc: | ok | | arm: | ok | | arm64: | ok | | avr32: | ok | | blackfin: | ok | | c6x: | TODO | | cris: | TODO | | frv: | TODO | | h8300: | TODO | | hexagon: | ok | | ia64: | TODO | | m32r: | TODO | | m68k: | TODO | | metag: | ok | | microblaze: | ok | | mips: | ok | | mn10300: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | | powerpc: | ok | | s390: | ok | | score: | ok | | sh: | ok | | sparc: | ok | | tile: | ok | | um: | ok | | unicore32: | ok | | x86: | ok | | xtensa: | ok | ----------------------- For generic kernel features that need architecture support, the arch-support.txt file in each feature directory shows the arch support matrix, for all upstream Linux architectures. The meaning of entries in the tables is: | ok | # feature supported by the architecture |TODO| # feature not yet supported by the architecture | .. | # feature cannot be supported by the hardware This directory structure can be used in the future to add other files - such as porting guides, testing description, etc. The Documentation/features/ hierarchy may also include generic kernel features that works on every architecture, in that case the arch-support.txt file will list every architecture as supported. To list an architecture's unsupported features, just do something like: triton:~/tip> git grep -lE 'x86.*TODO' Documentation/features/*/*/arch-support.txt Documentation/features/lib/strncasecmp/arch-support.txt Documentation/features/time/arch-tick-broadcast/arch-support.txt which will print the list of not yet supported features. The Documentation/features/list-arch.sh script will print the current support matrix of one architecture: triton:~/tip> Documentation/features/list-arch.sh # # Kernel feature support matrix of the 'x86' architecture: # core/ BPF-JIT : ok | HAVE_BPF_JIT # arch supports BPF JIT optimizations core/ generic-idle-thread : ok | GENERIC_SMP_IDLE_THREAD # arch makes use of the generic SMP idle thread facility core/ jump-labels : ok | HAVE_ARCH_JUMP_LABEL # arch supports live patched, high efficiency branches core/ tracehook : ok | HAVE_ARCH_TRACEHOOK # arch supports tracehook (ptrace) register handling APIs debug/ gcov-profile-all : ok | ARCH_HAS_GCOV_PROFILE_ALL # arch supports whole-kernel GCOV code coverage profiling debug/ KASAN : ok | HAVE_ARCH_KASAN # arch supports the KASAN runtime memory checker debug/ kgdb : ok | HAVE_ARCH_KGDB # arch supports the kGDB kernel debugger debug/ kprobes : ok | HAVE_KPROBES # arch supports live patched kernel probe debug/ kprobes-on-ftrace : ok | HAVE_KPROBES_ON_FTRACE # arch supports combined kprobes and ftrace live patching debug/ kretprobes : ok | HAVE_KRETPROBES # arch supports kernel function-return probes debug/ optprobes : ok | HAVE_OPTPROBES # arch supports live patched optprobes debug/ stackprotector : ok | HAVE_CC_STACKPROTECTOR # arch supports compiler driven stack overflow protection debug/ uprobes : ok | ARCH_SUPPORTS_UPROBES # arch supports live patched user probes debug/ user-ret-profiler : ok | HAVE_USER_RETURN_NOTIFIER # arch supports user-space return from system call profiler io/ dma-api-debug : ok | HAVE_DMA_API_DEBUG # arch supports DMA debug facilities io/ dma-contiguous : ok | HAVE_DMA_CONTIGUOUS # arch supports the DMA CMA (continuous memory allocator) io/ dma_map_attrs : ok | HAVE_DMA_ATTRS # arch provides dma_*map*_attrs() APIs io/ sg-chain : ok | ARCH_HAS_SG_CHAIN # arch supports chained scatter-gather lists lib/ strncasecmp : TODO | __HAVE_ARCH_STRNCASECMP # arch provides an optimized strncasecmp() function locking/ cmpxchg-local : ok | HAVE_CMPXCHG_LOCAL # arch supports the this_cpu_cmpxchg() API locking/ lockdep : ok | LOCKDEP_SUPPORT # arch supports the runtime locking correctness debug facility locking/ queued-rwlocks : ok | ARCH_USE_QUEUED_RWLOCKS # arch supports queued rwlocks locking/ queued-spinlocks : ok | ARCH_USE_QUEUED_SPINLOCKS # arch supports queued spinlocks locking/ rwsem-optimized : ok | Optimized asm/rwsem.h # arch provides optimized rwsem APIs perf/ kprobes-event : ok | HAVE_REGS_AND_STACK_ACCESS_API # arch supports kprobes with perf events perf/ perf-regs : ok | HAVE_PERF_REGS # arch supports perf events register access perf/ perf-stackdump : ok | HAVE_PERF_USER_STACK_DUMP # arch supports perf events stack dumps sched/ numa-balancing : ok | ARCH_SUPPORTS_NUMA_BALANCING # arch supports NUMA balancing seccomp/ seccomp-filter : ok | HAVE_ARCH_SECCOMP_FILTER # arch supports seccomp filters time/ arch-tick-broadcast : TODO | ARCH_HAS_TICK_BROADCAST # arch provides tick_broadcast() time/ clockevents : ok | GENERIC_CLOCKEVENTS # arch support generic clock events time/ context-tracking : ok | HAVE_CONTEXT_TRACKING # arch supports context tracking for NO_HZ_FULL time/ irq-time-acct : ok | HAVE_IRQ_TIME_ACCOUNTING # arch supports precise IRQ time accounting time/ modern-timekeeping : ok | !ARCH_USES_GETTIMEOFFSET # arch does not use arch_gettimeoffset() anymore time/ virt-cpuacct : ok | HAVE_VIRT_CPU_ACCOUNTING # arch supports precise virtual CPU time accounting vm/ ELF-ASLR : ok | ARCH_HAS_ELF_RANDOMIZE # arch randomizes the stack, heap and binary images of ELF binaries vm/ huge-vmap : ok | HAVE_ARCH_HUGE_VMAP # arch supports the ioremap_pud_enabled() and ioremap_pmd_enabled() VM APIs vm/ ioremap_prot : ok | HAVE_IOREMAP_PROT # arch has ioremap_prot() vm/ numa-memblock : ok | HAVE_MEMBLOCK_NODE_MAP # arch supports NUMA aware memblocks vm/ PG_uncached : ok | ARCH_USES_PG_UNCACHED # arch supports the PG_uncached page flag vm/ pmdp_splitting_flush : ok | __HAVE_ARCH_PMDP_SPLITTING_FLUSH # arch supports the pmdp_splitting_flush() VM API vm/ pte_special : ok | __HAVE_ARCH_PTE_SPECIAL # arch supports the pte_special()/pte_mkspecial() VM APIs vm/ THP : ok | HAVE_ARCH_TRANSPARENT_HUGEPAGE # arch supports transparent hugepages Cc: Cc: Cc: Cc: Andrew Morton Cc: H. Peter Anvin Cc: Jonathan Corbet Cc: Josh Triplett Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Signed-off-by: Ingo Molnar --- Documentation/features/arch-support.txt | 11 +++++++++++ Documentation/features/list-arch.sh | 24 ++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 Documentation/features/arch-support.txt create mode 100755 Documentation/features/list-arch.sh (limited to 'Documentation') diff --git a/Documentation/features/arch-support.txt b/Documentation/features/arch-support.txt new file mode 100644 index 000000000000..d22a1095e661 --- /dev/null +++ b/Documentation/features/arch-support.txt @@ -0,0 +1,11 @@ + +For generic kernel features that need architecture support, the +arch-support.txt file in each feature directory shows the arch +support matrix, for all upstream Linux architectures. + +The meaning of entries in the tables is: + + | ok | # feature supported by the architecture + |TODO| # feature not yet supported by the architecture + | .. | # feature cannot be supported by the hardware + diff --git a/Documentation/features/list-arch.sh b/Documentation/features/list-arch.sh new file mode 100755 index 000000000000..6065124a072f --- /dev/null +++ b/Documentation/features/list-arch.sh @@ -0,0 +1,24 @@ +# +# Small script that visualizes the kernel feature support status +# of an architecture. +# +# (If no arguments are given then it will print the host architecture's status.) +# + +ARCH=${1:-$(arch | sed 's/x86_64/x86/' | sed 's/i386/x86/')} + +cd $(dirname $0) +echo "#" +echo "# Kernel feature support matrix of the '$ARCH' architecture:" +echo "#" + +for F in */*/arch-support.txt; do + SUBSYS=$(echo $F | cut -d/ -f1) + N=$(grep -h "^# Feature name:" $F | cut -c25-) + C=$(grep -h "^# Kconfig:" $F | cut -c25-) + D=$(grep -h "^# description:" $F | cut -c25-) + S=$(grep -hw $ARCH $F | cut -d\| -f3) + + printf "%10s/%-22s:%s| %35s # %s\n" "$SUBSYS" "$N" "$S" "$C" "$D" +done + -- cgit v1.2.3 From 4d52b2acefdfceae0e47ed08324a96f511dc80b1 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 26 May 2015 14:42:57 +0200 Subject: clk: mvebu: add missing CESA gate clk Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by: Boris Brezillon Acked-by: Gregory CLEMENT Signed-off-by: Michael Turquette --- Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 1 + drivers/clk/mvebu/armada-370.c | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt index 31c7c0c1ce8f..660e64912cce 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt @@ -19,6 +19,7 @@ ID Clock Peripheral 9 pex1 PCIe Cntrl 1 15 sata0 SATA Host 0 17 sdio SDHCI Host +23 crypto CESA (crypto engine) 25 tdm Time Division Mplx 28 ddr DDR Cntrl 30 sata1 SATA Host 0 diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c index 756f0f39d6a3..c19fd77e6c27 100644 --- a/drivers/clk/mvebu/armada-370.c +++ b/drivers/clk/mvebu/armada-370.c @@ -163,6 +163,7 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = { { "pex1", "pex1_en", 9, 0 }, { "sata0", NULL, 15, 0 }, { "sdio", NULL, 17, 0 }, + { "crypto", NULL, 23, 0 }, { "tdm", NULL, 25, 0 }, { "ddr", NULL, 28, CLK_IGNORE_UNUSED }, { "sata1", NULL, 30, 0 }, -- cgit v1.2.3 From 19fbbbbcd3a3a8e307a4768784166abf7b55b779 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 3 Jun 2015 07:25:19 +0200 Subject: Add TI CDCE925 I2C controlled clock synthesizer driver This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by: Mike Looijmans Signed-off-by: Michael Turquette --- .../devicetree/bindings/clock/ti,cdce925.txt | 42 ++ drivers/clk/Kconfig | 17 + drivers/clk/Makefile | 1 + drivers/clk/clk-cdce925.c | 749 +++++++++++++++++++++ 4 files changed, 809 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,cdce925.txt create mode 100644 drivers/clk/clk-cdce925.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt new file mode 100644 index 000000000000..4c7669ad681b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt @@ -0,0 +1,42 @@ +Binding for TO CDCE925 programmable I2C clock synthesizers. + +Reference +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] http://www.ti.com/product/cdce925 + +The driver provides clock sources for each output Y1 through Y5. + +Required properties: + - compatible: Shall be "ti,cdce925" + - reg: I2C device address. + - clocks: Points to a fixed parent clock that provides the input frequency. + - #clock-cells: From common clock bindings: Shall be 1. + +Optional properties: + - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a + board, or to compensate for external influences. + +For both PLL1 and PLL2 an optional child node can be used to specify spread +spectrum clocking parameters for a board. + - spread-spectrum: SSC mode as defined in the data sheet. + - spread-spectrum-center: Use "centered" mode instead of "max" mode. When + present, the clock runs at the requested frequency on average. Otherwise + the requested frequency is the maximum value of the SCC range. + + +Example: + + clockgen: cdce925pw@64 { + compatible = "cdce925"; + reg = <0x64>; + clocks = <&xtal_27Mhz>; + #clock-cells = <1>; + xtal-load-pf = <5>; + /* PLL options to get SSC 1% centered */ + PLL2 { + spread-spectrum = <4>; + spread-spectrum-center; + }; + }; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 67e3a84d2805..e33ff4e3e18d 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -78,6 +78,23 @@ config COMMON_CLK_SI570 This driver supports Silicon Labs 570/571/598/599 programmable clock generators. +config COMMON_CLK_CDCE925 + tristate "Clock driver for TI CDCE925 devices" + depends on I2C + depends on OF + select REGMAP_I2C + help + ---help--- + This driver supports the TI CDCE925 programmable clock synthesizer. + The chip contains two PLLs with spread-spectrum clocking support and + five output dividers. The driver only supports the following setup, + and uses a fixed setting for the output muxes. + Y1 is derived from the input clock + Y2 and Y3 derive from PLL1 + Y4 and Y5 derive from PLL2 + Given a target output frequency, the driver will set the PLL and + divider to best approximate the desired output. + config COMMON_CLK_S2MPS11 tristate "Clock driver for S2MPS1X/S5M8767 MFD" depends on MFD_SEC_CORE diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d965b3f6a372..00ae2de0803a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c new file mode 100644 index 000000000000..56b870d331a1 --- /dev/null +++ b/drivers/clk/clk-cdce925.c @@ -0,0 +1,749 @@ +/* + * Driver for TI Dual PLL CDCE925 clock synthesizer + * + * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1 + * and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve + * basis. Clients can directly request any frequency that the chip can + * deliver using the standard clk framework. In addition, the device can + * be configured and activated via the devicetree. + * + * Copyright (C) 2014, Topic Embedded Products + * Licenced under GPL + */ +#include +#include +#include +#include +#include +#include +#include + +/* The chip has 2 PLLs which can be routed through dividers to 5 outputs. + * Model this as 2 PLL clocks which are parents to the outputs. + */ +#define NUMBER_OF_PLLS 2 +#define NUMBER_OF_OUTPUTS 5 + +#define CDCE925_REG_GLOBAL1 0x01 +#define CDCE925_REG_Y1SPIPDIVH 0x02 +#define CDCE925_REG_PDIVL 0x03 +#define CDCE925_REG_XCSEL 0x05 +/* PLL parameters start at 0x10, steps of 0x10 */ +#define CDCE925_OFFSET_PLL 0x10 +/* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ +#define CDCE925_PLL_MUX_OUTPUTS 0x14 +#define CDCE925_PLL_MULDIV 0x18 + +#define CDCE925_PLL_FREQUENCY_MIN 80000000ul +#define CDCE925_PLL_FREQUENCY_MAX 230000000ul +struct clk_cdce925_chip; + +struct clk_cdce925_output { + struct clk_hw hw; + struct clk_cdce925_chip *chip; + u8 index; + u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */ +}; +#define to_clk_cdce925_output(_hw) \ + container_of(_hw, struct clk_cdce925_output, hw) + +struct clk_cdce925_pll { + struct clk_hw hw; + struct clk_cdce925_chip *chip; + u8 index; + u16 m; /* 1..511 */ + u16 n; /* 1..4095 */ +}; +#define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) + +struct clk_cdce925_chip { + struct regmap *regmap; + struct i2c_client *i2c_client; + struct clk_cdce925_pll pll[NUMBER_OF_PLLS]; + struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS]; + struct clk *dt_clk[NUMBER_OF_OUTPUTS]; + struct clk_onecell_data onecell; +}; + +/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ + +static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, + u16 n, u16 m) +{ + if ((!m || !n) || (m == n)) + return parent_rate; /* In bypass mode runs at same frequency */ + return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); +} + +static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ + struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); + + return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); +} + +static void cdce925_pll_find_rate(unsigned long rate, + unsigned long parent_rate, u16 *n, u16 *m) +{ + unsigned long un; + unsigned long um; + unsigned long g; + + if (rate <= parent_rate) { + /* Can always deliver parent_rate in bypass mode */ + rate = parent_rate; + *n = 0; + *m = 0; + } else { + /* In PLL mode, need to apply min/max range */ + if (rate < CDCE925_PLL_FREQUENCY_MIN) + rate = CDCE925_PLL_FREQUENCY_MIN; + else if (rate > CDCE925_PLL_FREQUENCY_MAX) + rate = CDCE925_PLL_FREQUENCY_MAX; + + g = gcd(rate, parent_rate); + um = parent_rate / g; + un = rate / g; + /* When outside hw range, reduce to fit (rounding errors) */ + while ((un > 4095) || (um > 511)) { + un >>= 1; + um >>= 1; + } + if (un == 0) + un = 1; + if (um == 0) + um = 1; + + *n = un; + *m = um; + } +} + +static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u16 n, m; + + cdce925_pll_find_rate(rate, *parent_rate, &n, &m); + return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); +} + +static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); + + if (!rate || (rate == parent_rate)) { + data->m = 0; /* Bypass mode */ + data->n = 0; + return 0; + } + + if ((rate < CDCE925_PLL_FREQUENCY_MIN) || + (rate > CDCE925_PLL_FREQUENCY_MAX)) { + pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); + return -EINVAL; + } + + if (rate < parent_rate) { + pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, + rate, parent_rate); + return -EINVAL; + } + + cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); + return 0; +} + + +/* calculate p = max(0, 4 - int(log2 (n/m))) */ +static u8 cdce925_pll_calc_p(u16 n, u16 m) +{ + u8 p; + u16 r = n / m; + + if (r >= 16) + return 0; + p = 4; + while (r > 1) { + r >>= 1; + --p; + } + return p; +} + +/* Returns VCO range bits for VCO1_0_RANGE */ +static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) +{ + struct clk *parent = clk_get_parent(hw->clk); + unsigned long rate = clk_get_rate(parent); + + rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); + if (rate >= 175000000) + return 0x3; + if (rate >= 150000000) + return 0x02; + if (rate >= 125000000) + return 0x01; + return 0x00; +} + +/* I2C clock, hence everything must happen in (un)prepare because this + * may sleep */ +static int cdce925_pll_prepare(struct clk_hw *hw) +{ + struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); + u16 n = data->n; + u16 m = data->m; + u16 r; + u8 q; + u8 p; + u16 nn; + u8 pll[4]; /* Bits are spread out over 4 byte registers */ + u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; + unsigned i; + + if ((!m || !n) || (m == n)) { + /* Set PLL mux to bypass mode, leave the rest as is */ + regmap_update_bits(data->chip->regmap, + reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); + } else { + /* According to data sheet: */ + /* p = max(0, 4 - int(log2 (n/m))) */ + p = cdce925_pll_calc_p(n, m); + /* nn = n * 2^p */ + nn = n * BIT(p); + /* q = int(nn/m) */ + q = nn / m; + if ((q < 16) || (1 > 64)) { + pr_debug("%s invalid q=%d\n", __func__, q); + return -EINVAL; + } + r = nn - (m*q); + if (r > 511) { + pr_debug("%s invalid r=%d\n", __func__, r); + return -EINVAL; + } + pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, + n, m, p, q, r); + /* encode into register bits */ + pll[0] = n >> 4; + pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); + pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); + pll[3] = ((q & 0x07) << 5) | (p << 2) | + cdce925_pll_calc_range_bits(hw, n, m); + /* Write to registers */ + for (i = 0; i < ARRAY_SIZE(pll); ++i) + regmap_write(data->chip->regmap, + reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); + /* Enable PLL */ + regmap_update_bits(data->chip->regmap, + reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); + } + + return 0; +} + +static void cdce925_pll_unprepare(struct clk_hw *hw) +{ + struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); + u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; + + regmap_update_bits(data->chip->regmap, + reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); +} + +static const struct clk_ops cdce925_pll_ops = { + .prepare = cdce925_pll_prepare, + .unprepare = cdce925_pll_unprepare, + .recalc_rate = cdce925_pll_recalc_rate, + .round_rate = cdce925_pll_round_rate, + .set_rate = cdce925_pll_set_rate, +}; + + +static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) +{ + switch (data->index) { + case 0: + regmap_update_bits(data->chip->regmap, + CDCE925_REG_Y1SPIPDIVH, + 0x03, (pdiv >> 8) & 0x03); + regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); + break; + case 1: + regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); + break; + case 2: + regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); + break; + case 3: + regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); + break; + case 4: + regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); + break; + } +} + +static void cdce925_clk_activate(struct clk_cdce925_output *data) +{ + switch (data->index) { + case 0: + regmap_update_bits(data->chip->regmap, + CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); + break; + case 1: + case 2: + regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); + break; + case 3: + case 4: + regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); + break; + } +} + +static int cdce925_clk_prepare(struct clk_hw *hw) +{ + struct clk_cdce925_output *data = to_clk_cdce925_output(hw); + + cdce925_clk_set_pdiv(data, data->pdiv); + cdce925_clk_activate(data); + return 0; +} + +static void cdce925_clk_unprepare(struct clk_hw *hw) +{ + struct clk_cdce925_output *data = to_clk_cdce925_output(hw); + + /* Disable clock by setting divider to "0" */ + cdce925_clk_set_pdiv(data, 0); +} + +static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cdce925_output *data = to_clk_cdce925_output(hw); + + if (data->pdiv) + return parent_rate / data->pdiv; + return 0; +} + +static u16 cdce925_calc_divider(unsigned long rate, + unsigned long parent_rate) +{ + unsigned long divider; + + if (!rate) + return 0; + if (rate >= parent_rate) + return 1; + + divider = DIV_ROUND_CLOSEST(parent_rate, rate); + if (divider > 0x7F) + divider = 0x7F; + + return (u16)divider; +} + +static unsigned long cdce925_clk_best_parent_rate( + struct clk_hw *hw, unsigned long rate) +{ + struct clk *pll = clk_get_parent(hw->clk); + struct clk *root = clk_get_parent(pll); + unsigned long root_rate = clk_get_rate(root); + unsigned long best_rate_error = rate; + u16 pdiv_min; + u16 pdiv_max; + u16 pdiv_best; + u16 pdiv_now; + + if (root_rate % rate == 0) + return root_rate; /* Don't need the PLL, use bypass */ + + pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); + pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); + + if (pdiv_min > pdiv_max) + return 0; /* No can do? */ + + pdiv_best = pdiv_min; + for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { + unsigned long target_rate = rate * pdiv_now; + long pll_rate = clk_round_rate(pll, target_rate); + unsigned long actual_rate; + unsigned long rate_error; + + if (pll_rate <= 0) + continue; + actual_rate = pll_rate / pdiv_now; + rate_error = abs((long)actual_rate - (long)rate); + if (rate_error < best_rate_error) { + pdiv_best = pdiv_now; + best_rate_error = rate_error; + } + /* TODO: Consider PLL frequency based on smaller n/m values + * and pick the better one if the error is equal */ + } + + return rate * pdiv_best; +} + +static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long l_parent_rate = *parent_rate; + u16 divider = cdce925_calc_divider(rate, l_parent_rate); + + if (l_parent_rate / divider != rate) { + l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); + divider = cdce925_calc_divider(rate, l_parent_rate); + *parent_rate = l_parent_rate; + } + + if (divider) + return (long)(l_parent_rate / divider); + return 0; +} + +static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cdce925_output *data = to_clk_cdce925_output(hw); + + data->pdiv = cdce925_calc_divider(rate, parent_rate); + + return 0; +} + +static const struct clk_ops cdce925_clk_ops = { + .prepare = cdce925_clk_prepare, + .unprepare = cdce925_clk_unprepare, + .recalc_rate = cdce925_clk_recalc_rate, + .round_rate = cdce925_clk_round_rate, + .set_rate = cdce925_clk_set_rate, +}; + + +static u16 cdce925_y1_calc_divider(unsigned long rate, + unsigned long parent_rate) +{ + unsigned long divider; + + if (!rate) + return 0; + if (rate >= parent_rate) + return 1; + + divider = DIV_ROUND_CLOSEST(parent_rate, rate); + if (divider > 0x3FF) /* Y1 has 10-bit divider */ + divider = 0x3FF; + + return (u16)divider; +} + +static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long l_parent_rate = *parent_rate; + u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); + + if (divider) + return (long)(l_parent_rate / divider); + return 0; +} + +static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cdce925_output *data = to_clk_cdce925_output(hw); + + data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); + + return 0; +} + +static const struct clk_ops cdce925_clk_y1_ops = { + .prepare = cdce925_clk_prepare, + .unprepare = cdce925_clk_unprepare, + .recalc_rate = cdce925_clk_recalc_rate, + .round_rate = cdce925_clk_y1_round_rate, + .set_rate = cdce925_clk_y1_set_rate, +}; + + +static struct regmap_config cdce925_regmap_config = { + .name = "configuration0", + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .max_register = 0x2F, +}; + +#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 +#define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 + +static int cdce925_regmap_i2c_write( + void *context, const void *data, size_t count) +{ + struct device *dev = context; + struct i2c_client *i2c = to_i2c_client(dev); + int ret; + u8 reg_data[2]; + + if (count != 2) + return -ENOTSUPP; + + /* First byte is command code */ + reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; + reg_data[1] = ((u8 *)data)[1]; + + dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, + reg_data[0], reg_data[1]); + + ret = i2c_master_send(i2c, reg_data, count); + if (likely(ret == count)) + return 0; + else if (ret < 0) + return ret; + else + return -EIO; +} + +static int cdce925_regmap_i2c_read(void *context, + const void *reg, size_t reg_size, void *val, size_t val_size) +{ + struct device *dev = context; + struct i2c_client *i2c = to_i2c_client(dev); + struct i2c_msg xfer[2]; + int ret; + u8 reg_data[2]; + + if (reg_size != 1) + return -ENOTSUPP; + + xfer[0].addr = i2c->addr; + xfer[0].flags = 0; + xfer[0].buf = reg_data; + if (val_size == 1) { + reg_data[0] = + CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; + xfer[0].len = 1; + } else { + reg_data[0] = + CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; + reg_data[1] = val_size; + xfer[0].len = 2; + } + + xfer[1].addr = i2c->addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = val_size; + xfer[1].buf = val; + + ret = i2c_transfer(i2c->adapter, xfer, 2); + if (likely(ret == 2)) { + dev_dbg(&i2c->dev, "%s(%zu, %u) %#x %#x\n", __func__, + reg_size, val_size, reg_data[0], *((u8 *)val)); + return 0; + } else if (ret < 0) + return ret; + else + return -EIO; +} + +/* The CDCE925 uses a funky way to read/write registers. Bulk mode is + * just weird, so just use the single byte mode exclusively. */ +static struct regmap_bus regmap_cdce925_bus = { + .write = cdce925_regmap_i2c_write, + .read = cdce925_regmap_i2c_read, +}; + +static int cdce925_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct clk_cdce925_chip *data; + struct device_node *node = client->dev.of_node; + const char *parent_name; + const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,}; + struct clk_init_data init; + struct clk *clk; + u32 value; + int i; + int err; + struct device_node *np_output; + char child_name[6]; + + dev_dbg(&client->dev, "%s\n", __func__); + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->i2c_client = client; + data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, + &client->dev, &cdce925_regmap_config); + if (IS_ERR(data->regmap)) { + dev_err(&client->dev, "failed to allocate register map\n"); + return PTR_ERR(data->regmap); + } + i2c_set_clientdata(client, data); + + parent_name = of_clk_get_parent_name(node, 0); + if (!parent_name) { + dev_err(&client->dev, "missing parent clock\n"); + return -ENODEV; + } + dev_dbg(&client->dev, "parent is: %s\n", parent_name); + + if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) + regmap_write(data->regmap, + CDCE925_REG_XCSEL, (value << 3) & 0xF8); + /* PWDN bit */ + regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); + + /* Set input source for Y1 to be the XTAL */ + regmap_update_bits(data->regmap, 0x02, BIT(7), 0); + + init.ops = &cdce925_pll_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = parent_name ? 1 : 0; + + /* Register PLL clocks */ + for (i = 0; i < NUMBER_OF_PLLS; ++i) { + pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d", + client->dev.of_node->name, i); + init.name = pll_clk_name[i]; + data->pll[i].chip = data; + data->pll[i].hw.init = &init; + data->pll[i].index = i; + clk = devm_clk_register(&client->dev, &data->pll[i].hw); + if (IS_ERR(clk)) { + dev_err(&client->dev, "Failed register PLL %d\n", i); + err = PTR_ERR(clk); + goto error; + } + sprintf(child_name, "PLL%d", i+1); + np_output = of_get_child_by_name(node, child_name); + if (!np_output) + continue; + if (!of_property_read_u32(np_output, + "clock-frequency", &value)) { + err = clk_set_rate(clk, value); + if (err) + dev_err(&client->dev, + "unable to set PLL frequency %ud\n", + value); + } + if (!of_property_read_u32(np_output, + "spread-spectrum", &value)) { + u8 flag = of_property_read_bool(np_output, + "spread-spectrum-center") ? 0x80 : 0x00; + regmap_update_bits(data->regmap, + 0x16 + (i*CDCE925_OFFSET_PLL), + 0x80, flag); + regmap_update_bits(data->regmap, + 0x12 + (i*CDCE925_OFFSET_PLL), + 0x07, value & 0x07); + } + } + + /* Register output clock Y1 */ + init.ops = &cdce925_clk_y1_ops; + init.flags = 0; + init.num_parents = 1; + init.parent_names = &parent_name; /* Mux Y1 to input */ + init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name); + data->clk[0].chip = data; + data->clk[0].hw.init = &init; + data->clk[0].index = 0; + data->clk[0].pdiv = 1; + clk = devm_clk_register(&client->dev, &data->clk[0].hw); + kfree(init.name); /* clock framework made a copy of the name */ + if (IS_ERR(clk)) { + dev_err(&client->dev, "clock registration Y1 failed\n"); + err = PTR_ERR(clk); + goto error; + } + data->dt_clk[0] = clk; + + /* Register output clocks Y2 .. Y5*/ + init.ops = &cdce925_clk_ops; + init.flags = CLK_SET_RATE_PARENT; + init.num_parents = 1; + for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) { + init.name = kasprintf(GFP_KERNEL, "%s.Y%d", + client->dev.of_node->name, i+1); + data->clk[i].chip = data; + data->clk[i].hw.init = &init; + data->clk[i].index = i; + data->clk[i].pdiv = 1; + switch (i) { + case 1: + case 2: + /* Mux Y2/3 to PLL1 */ + init.parent_names = &pll_clk_name[0]; + break; + case 3: + case 4: + /* Mux Y4/5 to PLL2 */ + init.parent_names = &pll_clk_name[1]; + break; + } + clk = devm_clk_register(&client->dev, &data->clk[i].hw); + kfree(init.name); /* clock framework made a copy of the name */ + if (IS_ERR(clk)) { + dev_err(&client->dev, "clock registration failed\n"); + err = PTR_ERR(clk); + goto error; + } + data->dt_clk[i] = clk; + } + + /* Register the output clocks */ + data->onecell.clk_num = NUMBER_OF_OUTPUTS; + data->onecell.clks = data->dt_clk; + err = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get, + &data->onecell); + if (err) + dev_err(&client->dev, "unable to add OF clock provider\n"); + + err = 0; + +error: + for (i = 0; i < NUMBER_OF_PLLS; ++i) + /* clock framework made a copy of the name */ + kfree(pll_clk_name[i]); + + return err; +} + +static const struct i2c_device_id cdce925_id[] = { + { "cdce925", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, cdce925_id); + +static const struct of_device_id clk_cdce925_of_match[] = { + { .compatible = "ti,cdce925" }, + { }, +}; +MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); + +static struct i2c_driver cdce925_driver = { + .driver = { + .name = "cdce925", + .of_match_table = of_match_ptr(clk_cdce925_of_match), + }, + .probe = cdce925_probe, + .id_table = cdce925_id, +}; +module_i2c_driver(cdce925_driver); + +MODULE_AUTHOR("Mike Looijmans "); +MODULE_DESCRIPTION("cdce925 driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 59e85635d3e03ef9ac74ec8e39834a25b8e59dc7 Mon Sep 17 00:00:00 2001 From: kongxinwei Date: Wed, 20 May 2015 19:16:36 +0800 Subject: dt-bindings: Document the hi6220 thermal sensor bindings This adds documentation of device tree bindings for the thermal sensor controller of hi6220 SoC. Signed-off-by: Leo Yan Signed-off-by: kongxinwei Signed-off-by: Eduardo Valentin --- .../bindings/thermal/hisilicon-thermal.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt new file mode 100644 index 000000000000..d48fc5280d5a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt @@ -0,0 +1,23 @@ +* Temperature Sensor on hisilicon SoCs + +** Required properties : + +- compatible: "hisilicon,tsensor". +- reg: physical base address of thermal sensor and length of memory mapped + region. +- interrupt: The interrupt number to the cpu. Defines the interrupt used + by /SOCTHERM/tsensor. +- clock-names: Input clock name, should be 'thermal_clk'. +- clocks: phandles for clock specified in "clock-names" property. +- #thermal-sensor-cells: Should be 1. See ./thermal.txt for a description. + +Example : + + tsensor: tsensor@0,f7030700 { + compatible = "hisilicon,tsensor"; + reg = <0x0 0xf7030700 0x0 0x1000>; + interrupts = <0 7 0x4>; + clocks = <&sys_ctrl HI6220_TSENSOR_CLK>; + clock-names = "thermal_clk"; + #thermal-sensor-cells = <1>; + } -- cgit v1.2.3 From 2a10154abcb75ad0d7b6bfea6210ac743ec60897 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Tue, 2 Jun 2015 09:34:37 -0500 Subject: net: phy: dp83867: Add TI dp83867 phy Add support for the TI dp83867 Gigabit ethernet phy device. The DP83867 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. Signed-off-by: Dan Murphy Signed-off-by: David S. Miller --- .../devicetree/bindings/net/ti,dp83867.txt | 19 ++ drivers/net/phy/Kconfig | 6 +- drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83867.c | 239 +++++++++++++++++++++ include/dt-bindings/net/ti-dp83867.h | 45 ++++ 5 files changed, 309 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83867.txt create mode 100644 drivers/net/phy/dp83867.c create mode 100644 include/dt-bindings/net/ti-dp83867.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt new file mode 100644 index 000000000000..46bb67a222ea --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -0,0 +1,19 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - reg - The ID number for the phy, usually a small integer + - ti,rx_int_delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx_int_delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo_depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Example: + + ethernet-phy@0 { + reg = <0>; + ti,rx_int_delay = ; + ti,tx_int_delay = ; + ti,fifo_depth = ; + }; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 7c0cb87d1f2f..cf18940f4e84 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -112,6 +112,11 @@ config MICREL_PHY ---help--- Supports the KSZ9021, VSC8201, KS8001 PHYs. +config DP83867_PHY + tristate "Drivers for Texas Instruments DP83867 Gigabit PHY" + ---help--- + Currently supports the DP83867 PHY. + config FIXED_PHY tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" depends on PHYLIB @@ -205,7 +210,6 @@ config MDIO_BCM_UNIMAC This hardware can be found in the Broadcom GENET Ethernet MAC controllers as well as some Broadcom Ethernet switches such as the Starfighter 2 switches. - endif # PHYLIB config MICREL_KS8995MA diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index e97e7f921862..fcc25a0c45cd 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o obj-$(CONFIG_NATIONAL_PHY) += national.o obj-$(CONFIG_DP83640_PHY) += dp83640.o +obj-$(CONFIG_DP83867_PHY) += dp83867.o obj-$(CONFIG_STE10XP) += ste10Xp.o obj-$(CONFIG_MICREL_PHY) += micrel.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c new file mode 100644 index 000000000000..ef0b4eb15f8d --- /dev/null +++ b/drivers/net/phy/dp83867.c @@ -0,0 +1,239 @@ +/* + * Driver for the Texas Instruments DP83867 PHY + * + * Copyright (C) 2015 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define DP83867_PHY_ID 0x2000a231 +#define DP83867_DEVADDR 0x1f + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define MII_DP83867_ISR 0x13 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 + +#define DP83867_SW_RESET BIT(15) +#define DP83867_SW_RESTART BIT(14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +struct dp83867_private { + int rx_id_delay; + int tx_id_delay; + int fifo_depth; +}; + +static int dp83867_ack_interrupt(struct phy_device *phydev) +{ + int err = phy_read(phydev, MII_DP83867_ISR); + + if (err < 0) + return err; + + return 0; +} + +static int dp83867_config_intr(struct phy_device *phydev) +{ + int micr_status; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { + micr_status = phy_read(phydev, MII_DP83867_MICR); + if (micr_status < 0) + return micr_status; + + micr_status |= + (MII_DP83867_MICR_AN_ERR_INT_EN | + MII_DP83867_MICR_SPEED_CHNG_INT_EN | + MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | + MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); + + return phy_write(phydev, MII_DP83867_MICR, micr_status); + } + + micr_status = 0x0; + return phy_write(phydev, MII_DP83867_MICR, micr_status); +} + +#ifdef CONFIG_OF_MDIO +static int dp83867_of_init(struct phy_device *phydev) +{ + struct dp83867_private *dp83867 = phydev->priv; + struct device *dev = &phydev->dev; + struct device_node *of_node = dev->of_node; + int ret; + + if (!of_node && dev->parent->of_node) + of_node = dev->parent->of_node; + + if (!phydev->dev.of_node) + return -ENODEV; + + ret = of_property_read_u32(of_node, "ti,rx_int_delay", + &dp83867->rx_id_delay); + if (ret) + return ret; + + ret = of_property_read_u32(of_node, "ti,tx_int_delay", + &dp83867->tx_id_delay); + if (ret) + return ret; + + ret = of_property_read_u32(of_node, "ti,fifo_depth", + &dp83867->fifo_depth); + if (ret) + return ret; + + return 0; +} +#else +static int dp83867_of_init(struct phy_device *phydev) +{ + return 0; +} +#endif /* CONFIG_OF_MDIO */ + +static int dp83867_config_init(struct phy_device *phydev) +{ + struct dp83867_private *dp83867; + int ret; + u16 val, delay; + + if (!phydev->priv) { + dp83867 = devm_kzalloc(&phydev->dev, sizeof(*dp83867), + GFP_KERNEL); + if (!dp83867) + return -ENOMEM; + + phydev->priv = dp83867; + ret = dp83867_of_init(phydev); + if (ret) + return ret; + } else { + dp83867 = (struct dp83867_private *)phydev->priv; + } + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write(phydev, MII_DP83867_PHYCTRL, + (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + if (ret) + return ret; + } + + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, val); + + delay = (dp83867->rx_id_delay | + (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, + DP83867_DEVADDR, phydev->addr, delay); + } + + return 0; +} + +static int dp83867_phy_reset(struct phy_device *phydev) +{ + int err; + + err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); + if (err < 0) + return err; + + return dp83867_config_init(phydev); +} + +static struct phy_driver dp83867_driver[] = { + { + .phy_id = DP83867_PHY_ID, + .phy_id_mask = 0xfffffff0, + .name = "TI DP83867", + .features = PHY_GBIT_FEATURES, + .flags = PHY_HAS_INTERRUPT, + + .config_init = dp83867_config_init, + .soft_reset = dp83867_phy_reset, + + /* IRQ related */ + .ack_interrupt = dp83867_ack_interrupt, + .config_intr = dp83867_config_intr, + + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + + .driver = {.owner = THIS_MODULE,} + }, +}; +module_phy_driver(dp83867_driver); + +static struct mdio_device_id __maybe_unused dp83867_tbl[] = { + { DP83867_PHY_ID, 0xfffffff0 }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, dp83867_tbl); + +MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); +MODULE_AUTHOR("Dan Murphy + * + * Copyright: (C) 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif -- cgit v1.2.3 From f5ed2febda3ae51cc382a1341381506cec09248b Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Wed, 3 Jun 2015 20:43:40 -0700 Subject: switchdev: documentation: fix longer-than-80-char lines Signed-off-by: Scott Feldman Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 36 +++++++++++++++++----------------- 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index 616f89267d23..5061d6e12e2f 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -114,11 +114,11 @@ would be sub-port 0 on port 1 on switch 1. Switch ID ^^^^^^^^^ -The switchdev driver must implement the switchdev op switchdev_port_attr_get for -SWITCHDEV_ATTR_PORT_PARENT_ID for each port netdev, returning the same physical ID -for each port of a switch. The ID must be unique between switches on the same -system. The ID does not need to be unique between switches on different -systems. +The switchdev driver must implement the switchdev op switchdev_port_attr_get +for SWITCHDEV_ATTR_PORT_PARENT_ID for each port netdev, returning the same +physical ID for each port of a switch. The ID must be unique between switches +on the same system. The ID does not need to be unique between switches on +different systems. The switch ID is used to locate ports on a switch and to know if aggregated ports belong to the same switch. @@ -194,11 +194,11 @@ in turn, will notify the bridge driver using the switchdev notifier call: err = call_switchdev_notifiers(val, dev, info); -Where val is SWITCHDEV_FDB_ADD when learning and SWITCHDEV_FDB_DEL when forgetting, and -info points to a struct switchdev_notifier_fdb_info. On SWITCHDEV_FDB_ADD, the bridge -driver will install the FDB entry into the bridge's FDB and mark the entry as -NTF_EXT_LEARNED. The iproute2 bridge command will label these entries -"offload": +Where val is SWITCHDEV_FDB_ADD when learning and SWITCHDEV_FDB_DEL when +forgetting, and info points to a struct switchdev_notifier_fdb_info. On +SWITCHDEV_FDB_ADD, the bridge driver will install the FDB entry into the +bridge's FDB and mark the entry as NTF_EXT_LEARNED. The iproute2 bridge +command will label these entries "offload": $ bridge fdb 52:54:00:12:35:01 dev sw1p1 master br0 permanent @@ -229,18 +229,18 @@ the bridge's FDB. It's possible, but not optimal, to enable learning on the device port and on the bridge port, and disable learning_sync. To support learning and learning_sync port attributes, the driver implements -switchdev op switchdev_port_attr_get/set for SWITCHDEV_ATTR_PORT_BRIDGE_FLAGS. The driver -should initialize the attributes to the hardware defaults. +switchdev op switchdev_port_attr_get/set for SWITCHDEV_ATTR_PORT_BRIDGE_FLAGS. +The driver should initialize the attributes to the hardware defaults. FDB Ageing ^^^^^^^^^^ There are two FDB ageing models supported: 1) ageing by the device, and 2) ageing by the kernel. Ageing by the device is preferred if many FDB entries -are supported. The driver calls call_switchdev_notifiers(SWITCHDEV_FDB_DEL, ...) to -age out the FDB entry. In this model, ageing by the kernel should be turned -off. XXX: how to turn off ageing in kernel on a per-port basis or otherwise -prevent the kernel from ageing out the FDB entry? +are supported. The driver calls call_switchdev_notifiers(SWITCHDEV_FDB_DEL, +...) to age out the FDB entry. In this model, ageing by the kernel should be +turned off. XXX: how to turn off ageing in kernel on a per-port basis or +otherwise prevent the kernel from ageing out the FDB entry? In the kernel ageing model, the standard bridge ageing mechanism is used to age out stale FDB entries. To keep an FDB entry "alive", the driver should refresh @@ -262,8 +262,8 @@ STP State Change on Port Internally or with a third-party STP protocol implementation (e.g. mstpd), the bridge driver maintains the STP state for ports, and will notify the switch -driver of STP state change on a port using the switchdev op switchdev_attr_port_set for -SWITCHDEV_ATTR_PORT_STP_UPDATE. +driver of STP state change on a port using the switchdev op +switchdev_attr_port_set for SWITCHDEV_ATTR_PORT_STP_UPDATE. State is one of BR_STATE_*. The switch driver can use STP state updates to update ingress packet filter list for the port. For example, if port is -- cgit v1.2.3 From d290f1fc7092814ee0e14b80ad09b06af7bd3484 Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Wed, 3 Jun 2015 20:43:41 -0700 Subject: switchdev: documentation: fix grammer error Signed-off-by: Scott Feldman Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index 5061d6e12e2f..0554b68e1fab 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -142,7 +142,7 @@ The port netdevs representing the physical switch ports can be organized into higher-level switching constructs. The default construct is a standalone router port, used to offload L3 forwarding. Two or more ports can be bonded together to form a LAG. Two or more ports (or LAGs) can be bridged to bridge -to L2 networks. VLANs can be applied to sub-divide L2 networks. L2-over-L3 +L2 networks. VLANs can be applied to sub-divide L2 networks. L2-over-L3 tunnels can be built on ports. These constructs are built using standard Linux tools such as the bridge driver, the bonding/team drivers, and netlink-based tools such as iproute2. -- cgit v1.2.3 From 4b5364fbdce7e4b947e6e76d7341675ea2e12f4d Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Wed, 3 Jun 2015 20:43:42 -0700 Subject: switchdev: documentation: for static FDB ops, use switchdev_port_fdb_xxx ops Signed-off-by: Scott Feldman Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index 0554b68e1fab..00c703ce6903 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -177,6 +177,10 @@ entries are installed, for example, using iproute2 bridge cmd: bridge fdb add ADDR dev DEV [vlan VID] [self] +The driver should use the helper switchdev_port_fdb_xxx ops for ndo_fdb_xxx +ops, and handle add/delete/dump of SWITCHDEV_OBJ_PORT_FDB object using +switchdev_port_obj_xxx ops. + XXX: what should be done if offloading this rule to hardware fails (for example, due to full capacity in hardware tables) ? -- cgit v1.2.3 From 7616dcbb212eeec00c9bcc0fecb953fdee60634c Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Wed, 3 Jun 2015 20:43:43 -0700 Subject: switchdev: documentation: use switchdev_port_obj_xxx for IPv4 FIB add/modify/delete ops Clarify in documentation and code that IPV4 FIB add operation is used for both adding a new FIB entry to the device and for modifying an existing FIB entry on the device. Also, remove left-over references to ipv4_fib ops and replace with details on SWITCHDEV_PORT_IPV4_FIB object. Signed-off-by: Scott Feldman Acked-by: Jiri Pirko Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 53 +++++++++++++++++++--------------- net/switchdev/switchdev.c | 4 +-- 2 files changed, 31 insertions(+), 26 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index 00c703ce6903..da82cd75a4f6 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -300,33 +300,38 @@ IGMP Snooping XXX: complete this section -L3 routing ----------- +L3 Routing Offload +------------------ Offloading L3 routing requires that device be programmed with FIB entries from the kernel, with the device doing the FIB lookup and forwarding. The device does a longest prefix match (LPM) on FIB entries matching route prefix and -forwards the packet to the matching FIB entry's nexthop(s) egress ports. To -program the device, the switchdev driver is called with add/delete ops for IPv4 -and IPv6 FIB entries. For IPv4, the driver implements switchdev ops: - - int (*switchdev_fib_ipv4_add)(struct net_device *dev, - __be32 dst, int dst_len, - struct fib_info *fi, - u8 tos, u8 type, - u32 nlflags, u32 tb_id); - - int (*switchdev_fib_ipv4_del)(struct net_device *dev, - __be32 dst, int dst_len, - struct fib_info *fi, - u8 tos, u8 type, - u32 tb_id); - -to add/delete IPv4 dst/dest_len prefix on table tb_id. The *fi structure holds -details on the route and route's nexthops. *dev is one of the port netdevs -mentioned in the routes next hop list. If the output port netdevs referenced -in the route's nexthop list don't all have the same switch ID, the driver is -not called to add/delete the FIB entry. +forwards the packet to the matching FIB entry's nexthop(s) egress ports. + +To program the device, the driver implements support for +SWITCHDEV_OBJ_IPV[4|6]_FIB object using switchdev_port_obj_xxx ops. +switchdev_port_obj_add is used for both adding a new FIB entry to the device, +or modifying an existing entry on the device. + +XXX: Currently, only SWITCHDEV_OBJ_IPV4_FIB objects are supported. + +SWITCHDEV_OBJ_IPV4_FIB object passes: + + struct switchdev_obj_ipv4_fib { /* IPV4_FIB */ + u32 dst; + int dst_len; + struct fib_info *fi; + u8 tos; + u8 type; + u32 nlflags; + u32 tb_id; + } ipv4_fib; + +to add/modify/delete IPv4 dst/dest_len prefix on table tb_id. The *fi +structure holds details on the route and route's nexthops. *dev is one of the +port netdevs mentioned in the routes next hop list. If the output port netdevs +referenced in the route's nexthop list don't all have the same switch ID, the +driver is not called to add/modify/delete the FIB entry. Routes offloaded to the device are labeled with "offload" in the ip route listing: @@ -344,7 +349,7 @@ listing: 12.0.0.4 via 11.0.0.9 dev sw1p2 proto zebra metric 20 offload 192.168.0.0/24 dev eth0 proto kernel scope link src 192.168.0.15 -XXX: add/del IPv6 FIB API +XXX: add/mod/del IPv6 FIB API Nexthop Resolution ^^^^^^^^^^^^^^^^^^ diff --git a/net/switchdev/switchdev.c b/net/switchdev/switchdev.c index ac853acbe211..e008057dab46 100644 --- a/net/switchdev/switchdev.c +++ b/net/switchdev/switchdev.c @@ -803,7 +803,7 @@ static struct net_device *switchdev_get_dev_by_nhs(struct fib_info *fi) } /** - * switchdev_fib_ipv4_add - Add IPv4 route entry to switch + * switchdev_fib_ipv4_add - Add/modify switch IPv4 route entry * * @dst: route's IPv4 destination address * @dst_len: destination address length (prefix length) @@ -813,7 +813,7 @@ static struct net_device *switchdev_get_dev_by_nhs(struct fib_info *fi) * @nlflags: netlink flags passed in (NLM_F_*) * @tb_id: route table ID * - * Add IPv4 route entry to switch device. + * Add/modify switch IPv4 route entry. */ int switchdev_fib_ipv4_add(u32 dst, int dst_len, struct fib_info *fi, u8 tos, u8 type, u32 nlflags, u32 tb_id) -- cgit v1.2.3 From 6b212f0f09fa9abdaa62f560b70e64d8f20cd4af Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Thu, 4 Jun 2015 00:01:20 +0900 Subject: crypto: doc - Fix typo in crypto-API.tmpl This patch fix some spelling typo found in crypto-API.tmpl Signed-off-by: Masanari Iida Acked-by: Stephan Mueller Signed-off-by: Herbert Xu --- Documentation/DocBook/crypto-API.tmpl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/crypto-API.tmpl b/Documentation/DocBook/crypto-API.tmpl index f3fc07795620..0992531ffefb 100644 --- a/Documentation/DocBook/crypto-API.tmpl +++ b/Documentation/DocBook/crypto-API.tmpl @@ -119,7 +119,7 @@ Note: The terms "transformation" and cipher algorithm are used - interchangably. + interchangeably. @@ -1563,7 +1563,7 @@ struct sockaddr_alg sa = { Zero-Copy Interface - In addition to the send/write/read/recv system call familty, the AF_ALG + In addition to the send/write/read/recv system call family, the AF_ALG interface can be accessed with the zero-copy interface of splice/vmsplice. As the name indicates, the kernel tries to avoid a copy operation into kernel space. -- cgit v1.2.3 From 7164873e7c69d6bab74726debc3b495a86332b1f Mon Sep 17 00:00:00 2001 From: Vishnu Patekar Date: Tue, 2 Jun 2015 11:08:40 +0200 Subject: pinctrl: sunxi: Add allwinner A33 PIO controller support A33 PIO has 7 ports which starts from PB and has two interrupt ports. Signed-off-by: Vishnu Patekar Acked-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Hans de Goede Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +++++++++++++++++++++ 4 files changed, 520 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index fdd8046e650a..9462ab7ddd1f 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -16,6 +16,8 @@ Required properties: "allwinner,sun7i-a20-pinctrl" "allwinner,sun8i-a23-pinctrl" "allwinner,sun8i-a23-r-pinctrl" + "allwinner,sun8i-a33-pinctrl" + - reg: Should contain the register physical address and length for the pin controller. diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 2eb893e0ea1e..ae27872ff3a6 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -38,6 +38,10 @@ config PINCTRL_SUN8I_A23 def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_A33 + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN8I_A23_R def_bool MACH_SUN8I depends on RESET_CONTROLLER diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index b796d579dce6..227a1213947c 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c new file mode 100644 index 000000000000..00265f0435a7 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -0,0 +1,513 @@ +/* + * Allwinner a33 SoCs pinctrl driver. + * + * Copyright (C) 2015 Vishnu Patekar + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai + * Copyright (C) 2014 Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a33_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "aif2"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm1")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */ + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = { + .pins = sun8i_a33_pins, + .npins = ARRAY_SIZE(sun8i_a33_pins), + .irq_banks = 2, +}; + +static int sun8i_a33_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_a33_pinctrl_data); +} + +static const struct of_device_id sun8i_a33_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a33-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match); + +static struct platform_driver sun8i_a33_pinctrl_driver = { + .probe = sun8i_a33_pinctrl_probe, + .driver = { + .name = "sun8i-a33-pinctrl", + .of_match_table = sun8i_a33_pinctrl_match, + }, +}; +module_platform_driver(sun8i_a33_pinctrl_driver); + +MODULE_AUTHOR("Vishnu Patekar "); +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From e2bfba418598951733aff5822ca617efdbc06715 Mon Sep 17 00:00:00 2001 From: Rojhalat Ibrahim Date: Tue, 2 Jun 2015 11:38:06 +0200 Subject: fix documentation after renaming gpiod_set_array to gpiod_set_array_value Patch "gpiolib: rename gpiod_set_array to gpiod_set_array_value" omitted to also change the function names in the documentation. Let's fix that. Signed-off-by: Rojhalat Ibrahim Signed-off-by: Linus Walleij --- Documentation/gpio/consumer.txt | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'Documentation') diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt index c21c1313f09e..bbc8b5888b80 100644 --- a/Documentation/gpio/consumer.txt +++ b/Documentation/gpio/consumer.txt @@ -241,18 +241,18 @@ Set multiple GPIO outputs with a single function call ----------------------------------------------------- The following functions set the output values of an array of GPIOs: - void gpiod_set_array(unsigned int array_size, - struct gpio_desc **desc_array, - int *value_array) - void gpiod_set_raw_array(unsigned int array_size, - struct gpio_desc **desc_array, - int *value_array) - void gpiod_set_array_cansleep(unsigned int array_size, - struct gpio_desc **desc_array, - int *value_array) - void gpiod_set_raw_array_cansleep(unsigned int array_size, - struct gpio_desc **desc_array, - int *value_array) + void gpiod_set_array_value(unsigned int array_size, + struct gpio_desc **desc_array, + int *value_array) + void gpiod_set_raw_array_value(unsigned int array_size, + struct gpio_desc **desc_array, + int *value_array) + void gpiod_set_array_value_cansleep(unsigned int array_size, + struct gpio_desc **desc_array, + int *value_array) + void gpiod_set_raw_array_value_cansleep(unsigned int array_size, + struct gpio_desc **desc_array, + int *value_array) The array can be an arbitrary set of GPIOs. The functions will try to set GPIOs belonging to the same bank or chip simultaneously if supported by the @@ -271,8 +271,8 @@ matches the desired group of GPIOs, those GPIOs can be set by simply using the struct gpio_descs returned by gpiod_get_array(): struct gpio_descs *my_gpio_descs = gpiod_get_array(...); - gpiod_set_array(my_gpio_descs->ndescs, my_gpio_descs->desc, - my_gpio_values); + gpiod_set_array_value(my_gpio_descs->ndescs, my_gpio_descs->desc, + my_gpio_values); It is also possible to set a completely arbitrary array of descriptors. The descriptors may be obtained using any combination of gpiod_get() and -- cgit v1.2.3 From 0637e965ba20da9cb29cade3a7026db307473f05 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Thu, 4 Jun 2015 11:41:20 +0800 Subject: dt: Add documentation for the ZTE SPDIF controller This patch adds the devicetree documentation for the ZTE zx296702 SPDIF audio controller. Signed-off-by: Jun Nie Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/zte,zx-spdif.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/zte,zx-spdif.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt b/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt new file mode 100644 index 000000000000..989544ea6eb5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt @@ -0,0 +1,28 @@ +ZTE ZX296702 SPDIF controller + +Required properties: + - compatible : Must be "zte,zx296702-spdif" + - reg : Must contain SPDIF core's registers location and length + - clocks : Pairs of phandle and specifier referencing the controller's clocks. + - clock-names: "tx" for the clock to the SPDIF interface. + - dmas: Pairs of phandle and specifier for the DMA channel that is used by + the core. The core expects one dma channel for transmit. + - dma-names : Must be "tx" + +For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties +please check: + * resource-names.txt + * clock/clock-bindings.txt + * dma/dma.txt + +Example: + spdif0: spdif0@0b004000 { + compatible = "zte,zx296702-spdif"; + reg = <0x0b004000 0x1000>; + clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; + clock-names = "tx"; + interrupts = ; + dmas = <&dma 4>; + dma-names = "tx"; + status = "okay"; + }; -- cgit v1.2.3 From dc772a4cf76113d7269e4fb1c45e5d85c0cf458e Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Thu, 4 Jun 2015 11:41:21 +0800 Subject: dt: Add documentation for the ZTE I2S controller This patch adds the devicetree documentation for the ZTE zx296702 I2S audio controller. Signed-off-by: Jun Nie Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/zte,zx-i2s.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/zte,zx-i2s.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt new file mode 100644 index 000000000000..7e5aa6f6b5a1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt @@ -0,0 +1,44 @@ +ZTE ZX296702 I2S controller + +Required properties: + - compatible : Must be "zte,zx296702-i2s" + - reg : Must contain I2S core's registers location and length + - clocks : Pairs of phandle and specifier referencing the controller's clocks. + - clock-names: "tx" for the clock to the I2S interface. + - dmas: Pairs of phandle and specifier for the DMA channel that is used by + the core. The core expects two dma channels for transmit. + - dma-names : Must be "tx" and "rx" + +For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties +please check: + * resource-names.txt + * clock/clock-bindings.txt + * dma/dma.txt + +Example: + i2s0: i2s0@0b005000 { + #sound-dai-cells = <0>; + compatible = "zte,zx296702-i2s"; + reg = <0x0b005000 0x1000>; + clocks = <&lsp0clk ZX296702_I2S0_DIV>; + clock-names = "tx"; + interrupts = ; + dmas = <&dma 5>, <&dma 6>; + dma-names = "tx", "rx"; + status = "okay"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "zx296702_snd"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; -- cgit v1.2.3 From f077825a8758d79838a757dafb79adcdd047ef3a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 1 Apr 2015 15:06:40 +0200 Subject: KVM: x86: API changes for SMM support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch includes changes to the external API for SMM support. Userspace can predicate the availability of the new fields and ioctls on a new capability, KVM_CAP_X86_SMM, which is added at the end of the patch series. Reviewed-by: Radim Krčmář Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/api.txt | 40 +++++++++++++++++++++++++++++++++------ arch/x86/include/asm/kvm_host.h | 3 +++ arch/x86/include/uapi/asm/kvm.h | 11 ++++++++++- arch/x86/kvm/kvm_cache_regs.h | 5 +++++ arch/x86/kvm/lapic.h | 5 +++++ arch/x86/kvm/x86.c | 40 +++++++++++++++++++++++++++++++++++++-- include/uapi/linux/kvm.h | 5 ++++- 7 files changed, 99 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 695544420ff2..2ddefd58b1aa 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -820,11 +820,21 @@ struct kvm_vcpu_events { } nmi; __u32 sipi_vector; __u32 flags; + struct { + __u8 smm; + __u8 pending; + __u8 smm_inside_nmi; + __u8 latched_init; + } smi; }; -KVM_VCPUEVENT_VALID_SHADOW may be set in the flags field to signal that -interrupt.shadow contains a valid state. Otherwise, this field is undefined. +Only two fields are defined in the flags field: + +- KVM_VCPUEVENT_VALID_SHADOW may be set in the flags field to signal that + interrupt.shadow contains a valid state. +- KVM_VCPUEVENT_VALID_SMM may be set in the flags field to signal that + smi contains a valid state. 4.32 KVM_SET_VCPU_EVENTS @@ -841,17 +851,20 @@ vcpu. See KVM_GET_VCPU_EVENTS for the data structure. Fields that may be modified asynchronously by running VCPUs can be excluded -from the update. These fields are nmi.pending and sipi_vector. Keep the -corresponding bits in the flags field cleared to suppress overwriting the -current in-kernel state. The bits are: +from the update. These fields are nmi.pending, sipi_vector, smi.smm, +smi.pending. Keep the corresponding bits in the flags field cleared to +suppress overwriting the current in-kernel state. The bits are: KVM_VCPUEVENT_VALID_NMI_PENDING - transfer nmi.pending to the kernel KVM_VCPUEVENT_VALID_SIPI_VECTOR - transfer sipi_vector +KVM_VCPUEVENT_VALID_SMM - transfer the smi sub-struct. If KVM_CAP_INTR_SHADOW is available, KVM_VCPUEVENT_VALID_SHADOW can be set in the flags field to signal that interrupt.shadow contains a valid state and shall be written into the VCPU. +KVM_VCPUEVENT_VALID_SMM can only be set if KVM_CAP_X86_SMM is available. + 4.33 KVM_GET_DEBUGREGS @@ -2979,6 +2992,16 @@ len must be a multiple of sizeof(struct kvm_s390_irq). It must be > 0 and it must not exceed (max_vcpus + 32) * sizeof(struct kvm_s390_irq), which is the maximum number of possibly pending cpu-local interrupts. +4.90 KVM_SMI + +Capability: KVM_CAP_X86_SMM +Architectures: x86 +Type: vcpu ioctl +Parameters: none +Returns: 0 on success, -1 on error + +Queues an SMI on the thread's vcpu. + 5. The kvm_run structure ------------------------ @@ -3014,7 +3037,12 @@ an interrupt can be injected now with KVM_INTERRUPT. The value of the current interrupt flag. Only valid if in-kernel local APIC is not used. - __u8 padding2[2]; + __u16 flags; + +More architecture-specific flags detailing state of the VCPU that may +affect the device's behavior. The only currently defined flag is +KVM_RUN_X86_SMM, which is valid on x86 machines and is set if the +VCPU is in system management mode. /* in (pre_kvm_run), out (post_kvm_run) */ __u64 cr8; diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 4e299fcd0eb6..d52d7aea375f 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -471,6 +471,7 @@ struct kvm_vcpu_arch { atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ unsigned nmi_pending; /* NMI queued after currently running handler */ bool nmi_injected; /* Trying to inject an NMI this entry */ + bool smi_pending; /* SMI queued after currently running handler */ struct mtrr_state_type mtrr_state; u64 pat; @@ -1115,6 +1116,8 @@ enum { #define HF_NMI_MASK (1 << 3) #define HF_IRET_MASK (1 << 4) #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ +#define HF_SMM_MASK (1 << 6) +#define HF_SMM_INSIDE_NMI_MASK (1 << 7) /* * Hardware virtualization extension instructions may fault if a diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h index 2fec75e4b1e1..a4ae82eb82aa 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -106,6 +106,8 @@ struct kvm_ioapic_state { #define KVM_IRQCHIP_IOAPIC 2 #define KVM_NR_IRQCHIPS 3 +#define KVM_RUN_X86_SMM (1 << 0) + /* for KVM_GET_REGS and KVM_SET_REGS */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ @@ -281,6 +283,7 @@ struct kvm_reinject_control { #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 +#define KVM_VCPUEVENT_VALID_SMM 0x00000008 /* Interrupt shadow states */ #define KVM_X86_SHADOW_INT_MOV_SS 0x01 @@ -309,7 +312,13 @@ struct kvm_vcpu_events { } nmi; __u32 sipi_vector; __u32 flags; - __u32 reserved[10]; + struct { + __u8 smm; + __u8 pending; + __u8 smm_inside_nmi; + __u8 latched_init; + } smi; + __u32 reserved[9]; }; /* for KVM_GET/SET_DEBUGREGS */ diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 544076c4f44b..e1e89ee4af75 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -99,4 +99,9 @@ static inline bool is_guest_mode(struct kvm_vcpu *vcpu) return vcpu->arch.hflags & HF_GUEST_MASK; } +static inline bool is_smm(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.hflags & HF_SMM_MASK; +} + #endif diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 9d8fcde52027..f2f4e10ab772 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -159,6 +159,11 @@ static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) irq->msi_redir_hint); } +static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) +{ + return kvm_vcpu_has_lapic(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); +} + bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); void wait_lapic_expire(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7aec25f2f45c..aa46ac1ff48b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3101,6 +3101,11 @@ static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) return 0; } +static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) +{ + return 0; +} + static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, struct kvm_tpr_access_ctl *tac) { @@ -3206,8 +3211,15 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, events->sipi_vector = 0; /* never valid when reporting to user space */ + events->smi.smm = is_smm(vcpu); + events->smi.pending = vcpu->arch.smi_pending; + events->smi.smm_inside_nmi = + !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); + events->smi.latched_init = kvm_lapic_latched_init(vcpu); + events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING - | KVM_VCPUEVENT_VALID_SHADOW); + | KVM_VCPUEVENT_VALID_SHADOW + | KVM_VCPUEVENT_VALID_SMM); memset(&events->reserved, 0, sizeof(events->reserved)); } @@ -3216,7 +3228,8 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, { if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR - | KVM_VCPUEVENT_VALID_SHADOW)) + | KVM_VCPUEVENT_VALID_SHADOW + | KVM_VCPUEVENT_VALID_SMM)) return -EINVAL; process_nmi(vcpu); @@ -3241,6 +3254,24 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, kvm_vcpu_has_lapic(vcpu)) vcpu->arch.apic->sipi_vector = events->sipi_vector; + if (events->flags & KVM_VCPUEVENT_VALID_SMM) { + if (events->smi.smm) + vcpu->arch.hflags |= HF_SMM_MASK; + else + vcpu->arch.hflags &= ~HF_SMM_MASK; + vcpu->arch.smi_pending = events->smi.pending; + if (events->smi.smm_inside_nmi) + vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; + else + vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; + if (kvm_vcpu_has_lapic(vcpu)) { + if (events->smi.latched_init) + set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); + else + clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); + } + } + kvm_make_request(KVM_REQ_EVENT, vcpu); return 0; @@ -3500,6 +3531,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp, r = kvm_vcpu_ioctl_nmi(vcpu); break; } + case KVM_SMI: { + r = kvm_vcpu_ioctl_smi(vcpu); + break; + } case KVM_SET_CPUID: { struct kvm_cpuid __user *cpuid_arg = argp; struct kvm_cpuid cpuid; @@ -6182,6 +6217,7 @@ static void post_kvm_run_save(struct kvm_vcpu *vcpu) struct kvm_run *kvm_run = vcpu->run; kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; + kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; kvm_run->cr8 = kvm_get_cr8(vcpu); kvm_run->apic_base = kvm_get_apic_base(vcpu); if (irqchip_in_kernel(vcpu->kvm)) diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 75bd9f7fd846..eace8babd227 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -202,7 +202,7 @@ struct kvm_run { __u32 exit_reason; __u8 ready_for_interrupt_injection; __u8 if_flag; - __u8 padding2[2]; + __u16 flags; /* in (pre_kvm_run), out (post_kvm_run) */ __u64 cr8; @@ -815,6 +815,7 @@ struct kvm_ppc_smmu_info { #define KVM_CAP_S390_IRQ_STATE 114 #define KVM_CAP_PPC_HWRNG 115 #define KVM_CAP_DISABLE_QUIRKS 116 +#define KVM_CAP_X86_SMM 117 #ifdef KVM_CAP_IRQ_ROUTING @@ -1200,6 +1201,8 @@ struct kvm_s390_ucas_mapping { /* Available with KVM_CAP_S390_IRQ_STATE */ #define KVM_S390_SET_IRQ_STATE _IOW(KVMIO, 0xb5, struct kvm_s390_irq_state) #define KVM_S390_GET_IRQ_STATE _IOW(KVMIO, 0xb6, struct kvm_s390_irq_state) +/* Available with KVM_CAP_X86_SMM */ +#define KVM_SMI _IO(KVMIO, 0xb7) #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) -- cgit v1.2.3 From 582ed8d51e2b6cb8a168c94852bca482685c2509 Mon Sep 17 00:00:00 2001 From: "Luis R. Rodriguez" Date: Thu, 28 May 2015 11:56:01 -0700 Subject: Documentation: extend use case for EXPORT_SYMBOL_GPL() Current documentation over use case for EXPORT_SYMBOL_GPL() only acknowledges functions which are "an internal implementation issue, and not really an interface". In practice these days though we have some maintainers taking on preferences to require all new functionality go in with EXPORT_SYMBOL_GPL(). A maintainer asking developers to use EXPORT_SYMBOL_GPL() for new functionality tends to be a well accepted and understood position that maintainers can take and typically requires the maintainers educating contributing developers on their own positions and requirements. Developers who submit code to maintainers not familiar with these preferences as optional for new functionality need explicit guidence though as existing documentation does not acknowledge this as a valid possibility. Without this being documented some maintainers are reluctant to accept new functionality with EXPORT_SYMBOL_GPL(). This extends the use case documentation for EXPORT_SYMBOL_GPL() to acknowledge acceptance for new functionality. Signed-off-by: Luis R. Rodriguez [jc: wording tweaked with permission] Signed-off-by: Jonathan Corbet --- Documentation/DocBook/kernel-hacking.tmpl | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/DocBook/kernel-hacking.tmpl b/Documentation/DocBook/kernel-hacking.tmpl index e84f09467cd7..589b40cc5eb5 100644 --- a/Documentation/DocBook/kernel-hacking.tmpl +++ b/Documentation/DocBook/kernel-hacking.tmpl @@ -954,6 +954,8 @@ printk(KERN_INFO "my ip: %pI4\n", &ipaddress); MODULE_LICENSE() that specifies a GPL compatible license. It implies that the function is considered an internal implementation issue, and not really an interface. + Some maintainers and developers may however + require EXPORT_SYMBOL_GPL() when adding any new APIs or functionality. -- cgit v1.2.3 From 1df1b3618d95f7a6668c1a8e749e1be96a7e3fe1 Mon Sep 17 00:00:00 2001 From: Prarit Bhargava Date: Mon, 1 Jun 2015 09:36:04 -0400 Subject: Documentation, intel_pstate: Improve legacy mode internal governors description The current documentation is incomplete wrt the intel_pstate legacy internal governors. The confusion comes from the general cpufreq governors which also use the names performance and powersave. This patch better differentiates between the two sets of governors and gives an explanation of how the internal P-state governors behave differently from one another. Also fix two minor typos. Cc: Prarit Bhargava Cc: "Rafael J. Wysocki" Cc: Kristen Carlson Accardi Cc: Dirk Brandewie Cc: x86@kernel.org Acked-by: Viresh Kumar Signed-off-by: Prarit Bhargava Signed-off-by: Jonathan Corbet --- Documentation/cpu-freq/governors.txt | 2 +- Documentation/cpu-freq/intel-pstate.txt | 21 +++++++++++---------- 2 files changed, 12 insertions(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cpu-freq/governors.txt b/Documentation/cpu-freq/governors.txt index 77ec21574fb1..c15aa75f5227 100644 --- a/Documentation/cpu-freq/governors.txt +++ b/Documentation/cpu-freq/governors.txt @@ -36,7 +36,7 @@ Contents: 1. What Is A CPUFreq Governor? ============================== -Most cpufreq drivers (in fact, all except one, longrun) or even most +Most cpufreq drivers (except the intel_pstate and longrun) or even most cpu frequency scaling algorithms only offer the CPU to be set to one frequency. In order to offer dynamic frequency scaling, the cpufreq core must be able to tell these drivers of a "target frequency". So diff --git a/Documentation/cpu-freq/intel-pstate.txt b/Documentation/cpu-freq/intel-pstate.txt index 655750743fb0..be8d4006bf76 100644 --- a/Documentation/cpu-freq/intel-pstate.txt +++ b/Documentation/cpu-freq/intel-pstate.txt @@ -3,24 +3,25 @@ Intel P-state driver This driver provides an interface to control the P state selection for SandyBridge+ Intel processors. The driver can operate two different -modes based on the processor model legacy and Hardware P state (HWP) +modes based on the processor model, legacy mode and Hardware P state (HWP) mode. -In legacy mode the driver implements a scaling driver with an internal -governor for Intel Core processors. The driver follows the same model -as the Transmeta scaling driver (longrun.c) and implements the -setpolicy() instead of target(). Scaling drivers that implement -setpolicy() are assumed to implement internal governors by the cpufreq -core. All the logic for selecting the current P state is contained -within the driver; no external governor is used by the cpufreq core. +In legacy mode, the Intel P-state implements two internal governors, +performance and powersave, that differ from the general cpufreq governors of +the same name (the general cpufreq governors implement target(), whereas the +internal Intel P-state governors implement setpolicy()). The internal +performance governor sets the max_perf_pct and min_perf_pct to 100; that is, +the governor selects the highest available P state to maximize the performance +of the core. The internal powersave governor selects the appropriate P state +based on the current load on the CPU. In HWP mode P state selection is implemented in the processor itself. The driver provides the interfaces between the cpufreq core and the processor to control P state selection based on user preferences and reporting frequency to the cpufreq core. In this mode the -internal governor code is disabled. +internal Intel P-state governor code is disabled. -In addtion to the interfaces provided by the cpufreq core for +In addition to the interfaces provided by the cpufreq core for controlling frequency the driver provides sysfs files for controlling P state selection. These files have been added to /sys/devices/system/cpu/intel_pstate/ -- cgit v1.2.3 From 03e8f01a67d6fc02fafc1b23394cc750fec290e1 Mon Sep 17 00:00:00 2001 From: Frans Klaver Date: Thu, 4 Jun 2015 21:27:38 +0200 Subject: Doc: networking: txtimestamp: fix printf format warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Documentation/networking/timestamping/txtimestamp.c: In function ‘__print_timestamp’: Documentation/networking/timestamping/txtimestamp.c:99:3: warning: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘int64_t’ [-Wformat=] fprintf(stderr, " (%+ld us)", cur_ms - prev_ms); int64_t differs per platform, so a type specifier that differs along with it is required. Signed-off-by: Frans Klaver Signed-off-by: Jonathan Corbet --- Documentation/networking/timestamping/txtimestamp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/timestamping/txtimestamp.c b/Documentation/networking/timestamping/txtimestamp.c index 8217510d3842..5df07047ca86 100644 --- a/Documentation/networking/timestamping/txtimestamp.c +++ b/Documentation/networking/timestamping/txtimestamp.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -49,7 +50,6 @@ #include #include #include -#include #include #include #include @@ -96,7 +96,7 @@ static void __print_timestamp(const char *name, struct timespec *cur, prev_ms = (long) ts_prev.tv_sec * 1000 * 1000; prev_ms += ts_prev.tv_nsec / 1000; - fprintf(stderr, " (%+ld us)", cur_ms - prev_ms); + fprintf(stderr, " (%+" PRId64 " us)", cur_ms - prev_ms); } ts_prev = *cur; -- cgit v1.2.3 From 47016077b665b274c6c18f660a9a60898284e700 Mon Sep 17 00:00:00 2001 From: Andreas Gruenbacher Date: Fri, 5 Jun 2015 01:11:22 +0200 Subject: vfs: Minor documentation fix The check_acl inode operation and the IPERM_FLAG_RCU flag are long gone; update the documentation. Signed-off-by: Andreas Gruenbacher Signed-off-by: Jonathan Corbet --- Documentation/filesystems/porting | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/porting b/Documentation/filesystems/porting index e69274de8d0c..7a34c7eba610 100644 --- a/Documentation/filesystems/porting +++ b/Documentation/filesystems/porting @@ -379,10 +379,10 @@ may now be called in rcu-walk mode (nd->flags & LOOKUP_RCU). -ECHILD should be returned if the filesystem cannot handle rcu-walk. See Documentation/filesystems/vfs.txt for more details. - permission and check_acl are inode permission checks that are called -on many or all directory inodes on the way down a path walk (to check for -exec permission). These must now be rcu-walk aware (flags & IPERM_FLAG_RCU). -See Documentation/filesystems/vfs.txt for more details. + permission is an inode permission check that is called on many or all +directory inodes on the way down a path walk (to check for exec permission). It +must now be rcu-walk aware (mask & MAY_NOT_BLOCK). See +Documentation/filesystems/vfs.txt for more details. -- [mandatory] -- cgit v1.2.3 From 52aeeb3727af9b5ee4c85c42baff92501b5ceae1 Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Mon, 1 Jun 2015 15:06:51 +0300 Subject: powerpc/fsl: Add FMan Port 10G compatibles This patch adds two boolean properties to FMan Port. FMan has 3 types of ports: - 1G ports By default, all ports support 1G rate - 10G Ports Port which use 10G hardware, and configured as 10G - 10G Best effort ports Ports which use 1G hardware, configured as 10G, in this case, the rate is not guaranteed. The new properties help to distinguish the different type of ports. Signed-off-by: Igal Liberman Signed-off-by: Scott Wood --- Documentation/devicetree/bindings/powerpc/fsl/fman.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt index edda55f74004..1fc5328c0651 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt @@ -189,6 +189,19 @@ PROPERTIES Definition: There is one reg region describing the port configuration registers. +- fsl,fman-10g-port + Usage: optional + Value type: boolean + Definition: The default port rate is 1G. + If this property exists, the port is s 10G port. + +- fsl,fman-best-effort-port + Usage: optional + Value type: boolean + Definition: Can be defined only if 10G-support is set. + This property marks a best-effort 10G port (10G port that + may not be capable of line rate). + EXAMPLE port@a8000 { -- cgit v1.2.3 From 3833fe5f908f08280610b8e17a184d8c7e218148 Mon Sep 17 00:00:00 2001 From: Bintian Wang Date: Wed, 25 Feb 2015 15:23:11 +0800 Subject: arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon hi6220 SoC mobile platform. Signed-off-by: Bintian Wang Suggested-by: Arnd Bergmann Acked-by: Haojian Zhuang Acked-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Wei Xu --- .../bindings/arm/hisilicon/hisilicon.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 35b1bd49cfa1..c431c67524d6 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -1,5 +1,8 @@ Hisilicon Platforms Device Tree Bindings ---------------------------------------------------- +Hi6220 SoC +Required root node properties: + - compatible = "hisilicon,hi6220"; Hi4511 Board Required root node properties: @@ -13,6 +16,9 @@ HiP01 ca9x2 Board Required root node properties: - compatible = "hisilicon,hip01-ca9x2"; +HiKey Board +Required root node properties: + - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; Hisilicon system controller @@ -40,6 +46,87 @@ Example: reboot-offset = <0x4>; }; +----------------------------------------------------------------------- +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; + + +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; + + +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; + + +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; + ----------------------------------------------------------------------- Hisilicon HiP01 system controller -- cgit v1.2.3 From db0f90ef063c058e4179ecf2c66e54971e0a1ec1 Mon Sep 17 00:00:00 2001 From: Bintian Wang Date: Sat, 7 Feb 2015 14:48:13 +0800 Subject: clk: hi6220: Document devicetree bindings for hi6220 clock Document DT files bindings for Hisilicon hi6220 clock. Signed-off-by: Bintian Wang Acked-by: Haojian Zhuang Suggested-by: Arnd Bergmann Acked-by: Stephen Boyd Acked-by: Michael Turquette Signed-off-by: Wei Xu --- .../devicetree/bindings/clock/hi6220-clock.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt new file mode 100644 index 000000000000..259e30af9597 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt @@ -0,0 +1,34 @@ +* Hisilicon Hi6220 Clock Controller + +Clock control registers reside in different Hi6220 system controllers, +please refer the following document to know more about the binding rules +for these system controllers: + +Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt + +Required Properties: + +- compatible: the compatible should be one of the following strings to + indicate the clock controller functionality. + + - "hisilicon,hi6220-aoctrl" + - "hisilicon,hi6220-sysctrl" + - "hisilicon,hi6220-mediactrl" + - "hisilicon,hi6220-pmctrl" + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +For example: + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; + +Each clock is assigned an identifier and client nodes use this identifier +to specify the clock which they consume. + +All these identifier could be found in . -- cgit v1.2.3 From 22b6ae48c4d4089eac94662a8fb9cb6b9e48727b Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 28 Apr 2015 08:43:50 -0300 Subject: [media] DocBook/media: document new xfer_func fields Document the new field and defines to set the transfer function needed to correctly decode the colors of an image. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/pixfmt.xml | 113 +++++++++++++++++---- Documentation/DocBook/media/v4l/subdev-formats.xml | 12 ++- 2 files changed, 101 insertions(+), 24 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index 6c3d65346076..e7d88482a522 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -155,6 +155,14 @@ see . This information supplements the colorspace and must be set by the driver for capture streams and by the application for output streams, +see . + + + &v4l2-xfer-func; + xfer_func + This information supplements the +colorspace and must be set by the driver for +capture streams and by the application for output streams, see . @@ -262,11 +270,19 @@ see . This information supplements the colorspace and must be set by the driver for capture streams and by the application for output streams, +see . + + + &v4l2-xfer-func; + xfer_func + This information supplements the +colorspace and must be set by the driver for +capture streams and by the application for output streams, see . __u8 - reserved[8] + reserved[7] Reserved for future extensions. Should be zeroed by the application. @@ -476,15 +492,16 @@ is also very useful.
Defining Colorspaces in V4L2 - In V4L2 colorspaces are defined by three values. The first is the colorspace -identifier (&v4l2-colorspace;) which defines the chromaticities, the transfer + In V4L2 colorspaces are defined by four values. The first is the colorspace +identifier (&v4l2-colorspace;) which defines the chromaticities, the default transfer function, the default Y'CbCr encoding and the default quantization method. The second -is the Y'CbCr encoding identifier (&v4l2-ycbcr-encoding;) to specify non-standard -Y'CbCr encodings and the third is the quantization identifier (&v4l2-quantization;) -to specify non-standard quantization methods. Most of the time only the colorspace -field of &v4l2-pix-format; or &v4l2-pix-format-mplane; needs to be filled in. Note -that the default R'G'B' quantization is full range for all colorspaces except for -BT.2020 which uses limited range R'G'B' quantization. +is the transfer function identifier (&v4l2-xfer-func;) to specify non-standard +transfer functions. The third is the Y'CbCr encoding identifier (&v4l2-ycbcr-encoding;) +to specify non-standard Y'CbCr encodings and the fourth is the quantization identifier +(&v4l2-quantization;) to specify non-standard quantization methods. Most of the time +only the colorspace field of &v4l2-pix-format; or &v4l2-pix-format-mplane; needs to +be filled in. Note that the default R'G'B' quantization is full range for all +colorspaces except for BT.2020 which uses limited range R'G'B' quantization. V4L2 Colorspaces @@ -549,6 +566,45 @@ BT.2020 which uses limited range R'G'B' quantization.
+ + V4L2 Transfer Function + + &cs-def; + + + Identifier + Details + + + + + V4L2_XFER_FUNC_DEFAULT + Use the default transfer function as defined by the colorspace. + + + V4L2_XFER_FUNC_709 + Use the Rec. 709 transfer function. + + + V4L2_XFER_FUNC_SRGB + Use the sRGB transfer function. + + + V4L2_XFER_FUNC_ADOBERGB + Use the AdobeRGB transfer function. + + + V4L2_XFER_FUNC_SMPTE240M + Use the SMPTE 240M transfer function. + + + V4L2_XFER_FUNC_NONE + Do not use a transfer function (i.e. use linear RGB values). + + + +
+ V4L2 Y'CbCr Encodings @@ -636,7 +692,8 @@ is mapped to [16…235]. Cb and Cr are mapped from [-0.5…0.5] to [16
Colorspace SMPTE 170M (<constant>V4L2_COLORSPACE_SMPTE170M</constant>) The standard defines the colorspace used by NTSC and PAL and by SDTV -in general. The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. +in general. The default transfer function is V4L2_XFER_FUNC_709. +The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are:
@@ -718,7 +775,8 @@ rarely seen.
Colorspace Rec. 709 (<constant>V4L2_COLORSPACE_REC709</constant>) - The standard defines the colorspace used by HDTV in general. The default + The standard defines the colorspace used by HDTV in general. +The default transfer function is V4L2_XFER_FUNC_709. The default Y'CbCr encoding is V4L2_YCBCR_ENC_709. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are:
@@ -829,9 +887,11 @@ The xvYCC encodings always use full range quantization.
Colorspace sRGB (<constant>V4L2_COLORSPACE_SRGB</constant>) - The standard defines the colorspace used by most webcams and computer graphics. The -default Y'CbCr encoding is V4L2_YCBCR_ENC_SYCC. The default Y'CbCr quantization -is full range. The chromaticities of the primary colors and the white reference are: + The standard defines the colorspace used by most webcams +and computer graphics. The default transfer function is V4L2_XFER_FUNC_SRGB. +The default Y'CbCr encoding is V4L2_YCBCR_ENC_SYCC. The default Y'CbCr +quantization is full range. The chromaticities of the primary colors and the white +reference are:
sRGB Chromaticities @@ -908,6 +968,7 @@ values before quantization, but this encoding does not do that. Colorspace Adobe RGB (<constant>V4L2_COLORSPACE_ADOBERGB</constant>) The standard defines the colorspace used by computer graphics that use the AdobeRGB colorspace. This is also known as the standard. +The default transfer function is V4L2_XFER_FUNC_ADOBERGB. The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are: @@ -979,7 +1040,8 @@ SMPTE 170M/BT.601. The Y'CbCr quantization is limited range.
Colorspace BT.2020 (<constant>V4L2_COLORSPACE_BT2020</constant>) The standard defines the colorspace used by Ultra-high definition -television (UHDTV). The default Y'CbCr encoding is V4L2_YCBCR_ENC_BT2020. +television (UHDTV). The default transfer function is V4L2_XFER_FUNC_709. +The default Y'CbCr encoding is V4L2_YCBCR_ENC_BT2020. The default R'G'B' quantization is limited range (!), and so is the default Y'CbCr quantization. The chromaticities of the primary colors and the white reference are:
@@ -1094,8 +1156,10 @@ clamped to the range [-0.5…0.5]. The Yc'CbcCrc quantization is limited ra
Colorspace SMPTE 240M (<constant>V4L2_COLORSPACE_SMPTE240M</constant>) - The standard was an interim standard used during the early days of HDTV (1988-1998). -It has been superseded by Rec. 709. The default Y'CbCr encoding is V4L2_YCBCR_ENC_SMPTE240M. + The standard was an interim standard used during +the early days of HDTV (1988-1998). It has been superseded by Rec. 709. +The default transfer function is V4L2_XFER_FUNC_SMPTE240M. +The default Y'CbCr encoding is V4L2_YCBCR_ENC_SMPTE240M. The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are:
@@ -1168,8 +1232,10 @@ clamped to the range [-0.5…0.5]. The Y'CbCr quantization is limited range
Colorspace NTSC 1953 (<constant>V4L2_COLORSPACE_470_SYSTEM_M</constant>) This standard defines the colorspace used by NTSC in 1953. In practice this -colorspace is obsolete and SMPTE 170M should be used instead. The default Y'CbCr encoding -is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. +colorspace is obsolete and SMPTE 170M should be used instead. +The default transfer function is V4L2_XFER_FUNC_709. +The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. +The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are:
NTSC 1953 Chromaticities @@ -1246,8 +1312,10 @@ This transform is identical to one defined in SMPTE 170M/BT.601.
Colorspace EBU Tech. 3213 (<constant>V4L2_COLORSPACE_470_SYSTEM_BG</constant>) The standard defines the colorspace used by PAL/SECAM in 1975. In practice this -colorspace is obsolete and SMPTE 170M should be used instead. The default Y'CbCr encoding -is V4L2_YCBCR_ENC_601. The default Y'CbCr quantization is limited range. +colorspace is obsolete and SMPTE 170M should be used instead. +The default transfer function is V4L2_XFER_FUNC_709. +The default Y'CbCr encoding is V4L2_YCBCR_ENC_601. +The default Y'CbCr quantization is limited range. The chromaticities of the primary colors and the white reference are:
EBU Tech. 3213 Chromaticities @@ -1320,7 +1388,8 @@ This transform is identical to one defined in SMPTE 170M/BT.601.
Colorspace JPEG (<constant>V4L2_COLORSPACE_JPEG</constant>) This colorspace defines the colorspace used by most (Motion-)JPEG formats. The chromaticities -of the primary colors and the white reference are identical to sRGB. The Y'CbCr encoding is +of the primary colors and the white reference are identical to sRGB. The transfer +function use is V4L2_XFER_FUNC_SRGB. The Y'CbCr encoding is V4L2_YCBCR_ENC_601 with full range quantization where Y' is scaled to [0…255] and Cb/Cr are scaled to [-128…128] and then clipped to [-128…127]. diff --git a/Documentation/DocBook/media/v4l/subdev-formats.xml b/Documentation/DocBook/media/v4l/subdev-formats.xml index 2588ad781242..4e73345e3eab 100644 --- a/Documentation/DocBook/media/v4l/subdev-formats.xml +++ b/Documentation/DocBook/media/v4l/subdev-formats.xml @@ -50,8 +50,16 @@ capture streams and by the application for output streams, see . - __u32 - reserved[6] + &v4l2-xfer-func; + xfer_func + This information supplements the +colorspace and must be set by the driver for +capture streams and by the application for output streams, +see . + + + __u16 + reserved[11] Reserved for future extensions. Applications and drivers must set the array to zero. -- cgit v1.2.3 From 64d5702229d86deacf42a43bc893a981f72d4908 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sun, 31 May 2015 08:10:32 -0300 Subject: [media] vivid.txt: update the vivid documentation Document the new Transfer Function control (and fix the documentation for the other colorspace controls which were not quite correct). Mention the support for 4:2:0 and more multiplanar formats. Update the TODO list at the end. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/vivid.txt | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/video4linux/vivid.txt b/Documentation/video4linux/vivid.txt index cd4b5a1ac529..0c1b3a6ba6be 100644 --- a/Documentation/video4linux/vivid.txt +++ b/Documentation/video4linux/vivid.txt @@ -631,26 +631,33 @@ Timestamp Source: selects when the timestamp for each buffer is taken. Colorspace: selects which colorspace should be used when generating the image. This only applies if the CSC Colorbar test pattern is selected, - otherwise the test pattern will go through unconverted (except for - the so-called 'Transfer Function' corrections and the R'G'B' to Y'CbCr - conversion). This behavior is also what you want, since a 75% Colorbar + otherwise the test pattern will go through unconverted. + This behavior is also what you want, since a 75% Colorbar should really have 75% signal intensity and should not be affected by colorspace conversions. Changing the colorspace will result in the V4L2_EVENT_SOURCE_CHANGE to be sent since it emulates a detected colorspace change. +Transfer Function: selects which colorspace transfer function should be used when + generating an image. This only applies if the CSC Colorbar test pattern is + selected, otherwise the test pattern will go through unconverted. + This behavior is also what you want, since a 75% Colorbar + should really have 75% signal intensity and should not be affected + by colorspace conversions. + + Changing the transfer function will result in the V4L2_EVENT_SOURCE_CHANGE + to be sent since it emulates a detected colorspace change. + Y'CbCr Encoding: selects which Y'CbCr encoding should be used when generating - a Y'CbCr image. This only applies if the CSC Colorbar test pattern is - selected, and if the format is set to a Y'CbCr format as opposed to an - RGB format. + a Y'CbCr image. This only applies if the format is set to a Y'CbCr format + as opposed to an RGB format. Changing the Y'CbCr encoding will result in the V4L2_EVENT_SOURCE_CHANGE to be sent since it emulates a detected colorspace change. Quantization: selects which quantization should be used for the RGB or Y'CbCr - encoding when generating the test pattern. This only applies if the CSC - Colorbar test pattern is selected. + encoding when generating the test pattern. Changing the quantization will result in the V4L2_EVENT_SOURCE_CHANGE to be sent since it emulates a detected colorspace change. @@ -985,8 +992,9 @@ to change crop and compose rectangles on the fly. Section 12: Formats ------------------- -The driver supports all the regular packed YUYV formats, 16, 24 and 32 RGB -packed formats and two multiplanar formats (one luma and one chroma plane). +The driver supports all the regular packed and planar 4:4:4, 4:2:2 and 4:2:0 +YUYV formats, 8, 16, 24 and 32 RGB packed formats and various multiplanar +formats. The alpha component can be set through the 'Alpha Component' User control for those formats that support it. If the 'Apply Alpha To Red Only' control @@ -1119,11 +1127,9 @@ Just as a reminder and in no particular order: - Use per-queue locks and/or per-device locks to improve throughput - Add support to loop from a specific output to a specific input across vivid instances -- Add support for VIDIOC_EXPBUF once support for that has been added to vb2 - The SDR radio should use the same 'frequencies' for stations as the normal radio receiver, and give back noise if the frequency doesn't match up with a station frequency -- Improve the sine generation of the SDR radio. - Make a thread for the RDS generation, that would help in particular for the "Controls" RDS Rx I/O Mode as the read-only RDS controls could be updated in real-time. -- cgit v1.2.3 From f481b069e674378758c73761827e83ab05c46b52 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sun, 17 May 2015 17:30:37 +0200 Subject: KVM: implement multiple address spaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only two ioctls have to be modified; the address space id is placed in the higher 16 bits of their slot id argument. As of this patch, no architecture defines more than one address space; x86 will be the first. Reviewed-by: Radim Krčmář Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/api.txt | 12 ++++++ arch/powerpc/include/asm/kvm_book3s_64.h | 2 +- include/linux/kvm_host.h | 26 ++++++++++-- include/uapi/linux/kvm.h | 1 + virt/kvm/kvm_main.c | 70 ++++++++++++++++++++------------ 5 files changed, 79 insertions(+), 32 deletions(-) (limited to 'Documentation') diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 2ddefd58b1aa..461956a0ee8e 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -254,6 +254,11 @@ since the last call to this ioctl. Bit 0 is the first page in the memory slot. Ensure the entire structure is cleared to avoid padding issues. +If KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 specifies +the address space for which you want to return the dirty bitmap. +They must be less than the value that KVM_CHECK_EXTENSION returns for +the KVM_CAP_MULTI_ADDRESS_SPACE capability. + 4.9 KVM_SET_MEMORY_ALIAS @@ -924,6 +929,13 @@ slot. When changing an existing slot, it may be moved in the guest physical memory space, or its flags may be modified. It may not be resized. Slots may not overlap in guest physical address space. +If KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of "slot" +specifies the address space which is being modified. They must be +less than the value that KVM_CHECK_EXTENSION returns for the +KVM_CAP_MULTI_ADDRESS_SPACE capability. Slots in separate address spaces +are unrelated; the restriction on overlapping slots only applies within +each address space. + Memory for the region is taken starting at the address denoted by the field userspace_addr, which must point at user addressable memory for the entire memory slot size. Any object may back this memory, including diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h index 3536d12eb798..2aa79c864e91 100644 --- a/arch/powerpc/include/asm/kvm_book3s_64.h +++ b/arch/powerpc/include/asm/kvm_book3s_64.h @@ -430,7 +430,7 @@ static inline void note_hpte_modification(struct kvm *kvm, */ static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm) { - return rcu_dereference_raw_notrace(kvm->memslots); + return rcu_dereference_raw_notrace(kvm->memslots[0]); } extern void kvmppc_mmu_debugfs_init(struct kvm *kvm); diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index ba1ea43998e4..9564fd78c547 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -44,6 +44,10 @@ /* Two fragments for cross MMIO pages. */ #define KVM_MAX_MMIO_FRAGMENTS 2 +#ifndef KVM_ADDRESS_SPACE_NUM +#define KVM_ADDRESS_SPACE_NUM 1 +#endif + /* * For the normal pfn, the highest 12 bits should be zero, * so we can mask bit 62 ~ bit 52 to indicate the error pfn, @@ -331,6 +335,13 @@ struct kvm_kernel_irq_routing_entry { #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) #endif +#ifndef __KVM_VCPU_MULTIPLE_ADDRESS_SPACE +static inline int kvm_arch_vcpu_memslots_id(struct kvm_vcpu *vcpu) +{ + return 0; +} +#endif + /* * Note: * memslots are not sorted by id anymore, please use id_to_memslot() @@ -349,7 +360,7 @@ struct kvm { spinlock_t mmu_lock; struct mutex slots_lock; struct mm_struct *mm; /* userspace tied to this vm */ - struct kvm_memslots *memslots; + struct kvm_memslots *memslots[KVM_ADDRESS_SPACE_NUM]; struct srcu_struct srcu; struct srcu_struct irq_srcu; #ifdef CONFIG_KVM_APIC_ARCHITECTURE @@ -464,16 +475,23 @@ void kvm_exit(void); void kvm_get_kvm(struct kvm *kvm); void kvm_put_kvm(struct kvm *kvm); -static inline struct kvm_memslots *kvm_memslots(struct kvm *kvm) +static inline struct kvm_memslots *__kvm_memslots(struct kvm *kvm, int as_id) { - return rcu_dereference_check(kvm->memslots, + return rcu_dereference_check(kvm->memslots[as_id], srcu_read_lock_held(&kvm->srcu) || lockdep_is_held(&kvm->slots_lock)); } +static inline struct kvm_memslots *kvm_memslots(struct kvm *kvm) +{ + return __kvm_memslots(kvm, 0); +} + static inline struct kvm_memslots *kvm_vcpu_memslots(struct kvm_vcpu *vcpu) { - return kvm_memslots(vcpu->kvm); + int as_id = kvm_arch_vcpu_memslots_id(vcpu); + + return __kvm_memslots(vcpu->kvm, as_id); } static inline struct kvm_memory_slot * diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index eace8babd227..5ff1038437e3 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -816,6 +816,7 @@ struct kvm_ppc_smmu_info { #define KVM_CAP_PPC_HWRNG 115 #define KVM_CAP_DISABLE_QUIRKS 116 #define KVM_CAP_X86_SMM 117 +#define KVM_CAP_MULTI_ADDRESS_SPACE 118 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 3a121cedcc77..848af90b8091 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -518,9 +518,11 @@ static struct kvm *kvm_create_vm(unsigned long type) BUILD_BUG_ON(KVM_MEM_SLOTS_NUM > SHRT_MAX); r = -ENOMEM; - kvm->memslots = kvm_alloc_memslots(); - if (!kvm->memslots) - goto out_err_no_srcu; + for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { + kvm->memslots[i] = kvm_alloc_memslots(); + if (!kvm->memslots[i]) + goto out_err_no_srcu; + } if (init_srcu_struct(&kvm->srcu)) goto out_err_no_srcu; @@ -562,7 +564,8 @@ out_err_no_srcu: out_err_no_disable: for (i = 0; i < KVM_NR_BUSES; i++) kfree(kvm->buses[i]); - kvm_free_memslots(kvm, kvm->memslots); + for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) + kvm_free_memslots(kvm, kvm->memslots[i]); kvm_arch_free_vm(kvm); return ERR_PTR(r); } @@ -612,7 +615,8 @@ static void kvm_destroy_vm(struct kvm *kvm) #endif kvm_arch_destroy_vm(kvm); kvm_destroy_devices(kvm); - kvm_free_memslots(kvm, kvm->memslots); + for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) + kvm_free_memslots(kvm, kvm->memslots[i]); cleanup_srcu_struct(&kvm->irq_srcu); cleanup_srcu_struct(&kvm->srcu); kvm_arch_free_vm(kvm); @@ -729,9 +733,9 @@ static int check_memory_region_flags(const struct kvm_userspace_memory_region *m } static struct kvm_memslots *install_new_memslots(struct kvm *kvm, - struct kvm_memslots *slots) + int as_id, struct kvm_memslots *slots) { - struct kvm_memslots *old_memslots = kvm_memslots(kvm); + struct kvm_memslots *old_memslots = __kvm_memslots(kvm, as_id); /* * Set the low bit in the generation, which disables SPTE caching @@ -740,7 +744,7 @@ static struct kvm_memslots *install_new_memslots(struct kvm *kvm, WARN_ON(old_memslots->generation & 1); slots->generation = old_memslots->generation + 1; - rcu_assign_pointer(kvm->memslots, slots); + rcu_assign_pointer(kvm->memslots[as_id], slots); synchronize_srcu_expedited(&kvm->srcu); /* @@ -772,6 +776,7 @@ int __kvm_set_memory_region(struct kvm *kvm, struct kvm_memory_slot *slot; struct kvm_memory_slot old, new; struct kvm_memslots *slots = NULL, *old_memslots; + int as_id, id; enum kvm_mr_change change; r = check_memory_region_flags(mem); @@ -779,24 +784,27 @@ int __kvm_set_memory_region(struct kvm *kvm, goto out; r = -EINVAL; + as_id = mem->slot >> 16; + id = (u16)mem->slot; + /* General sanity checks */ if (mem->memory_size & (PAGE_SIZE - 1)) goto out; if (mem->guest_phys_addr & (PAGE_SIZE - 1)) goto out; /* We can read the guest memory with __xxx_user() later on. */ - if ((mem->slot < KVM_USER_MEM_SLOTS) && + if ((id < KVM_USER_MEM_SLOTS) && ((mem->userspace_addr & (PAGE_SIZE - 1)) || !access_ok(VERIFY_WRITE, (void __user *)(unsigned long)mem->userspace_addr, mem->memory_size))) goto out; - if (mem->slot >= KVM_MEM_SLOTS_NUM) + if (as_id >= KVM_ADDRESS_SPACE_NUM || id >= KVM_MEM_SLOTS_NUM) goto out; if (mem->guest_phys_addr + mem->memory_size < mem->guest_phys_addr) goto out; - slot = id_to_memslot(kvm_memslots(kvm), mem->slot); + slot = id_to_memslot(__kvm_memslots(kvm, as_id), id); base_gfn = mem->guest_phys_addr >> PAGE_SHIFT; npages = mem->memory_size >> PAGE_SHIFT; @@ -805,7 +813,7 @@ int __kvm_set_memory_region(struct kvm *kvm, new = old = *slot; - new.id = mem->slot; + new.id = id; new.base_gfn = base_gfn; new.npages = npages; new.flags = mem->flags; @@ -840,9 +848,9 @@ int __kvm_set_memory_region(struct kvm *kvm, if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) { /* Check for overlaps */ r = -EEXIST; - kvm_for_each_memslot(slot, kvm_memslots(kvm)) { + kvm_for_each_memslot(slot, __kvm_memslots(kvm, as_id)) { if ((slot->id >= KVM_USER_MEM_SLOTS) || - (slot->id == mem->slot)) + (slot->id == id)) continue; if (!((base_gfn + npages <= slot->base_gfn) || (base_gfn >= slot->base_gfn + slot->npages))) @@ -871,13 +879,13 @@ int __kvm_set_memory_region(struct kvm *kvm, slots = kvm_kvzalloc(sizeof(struct kvm_memslots)); if (!slots) goto out_free; - memcpy(slots, kvm_memslots(kvm), sizeof(struct kvm_memslots)); + memcpy(slots, __kvm_memslots(kvm, as_id), sizeof(struct kvm_memslots)); if ((change == KVM_MR_DELETE) || (change == KVM_MR_MOVE)) { - slot = id_to_memslot(slots, mem->slot); + slot = id_to_memslot(slots, id); slot->flags |= KVM_MEMSLOT_INVALID; - old_memslots = install_new_memslots(kvm, slots); + old_memslots = install_new_memslots(kvm, as_id, slots); /* slot was deleted or moved, clear iommu mapping */ kvm_iommu_unmap_pages(kvm, &old); @@ -909,7 +917,7 @@ int __kvm_set_memory_region(struct kvm *kvm, } update_memslots(slots, &new); - old_memslots = install_new_memslots(kvm, slots); + old_memslots = install_new_memslots(kvm, as_id, slots); kvm_arch_commit_memory_region(kvm, mem, &old, &new, change); @@ -956,7 +964,7 @@ EXPORT_SYMBOL_GPL(kvm_set_memory_region); static int kvm_vm_ioctl_set_memory_region(struct kvm *kvm, struct kvm_userspace_memory_region *mem) { - if (mem->slot >= KVM_USER_MEM_SLOTS) + if ((u16)mem->slot >= KVM_USER_MEM_SLOTS) return -EINVAL; return kvm_set_memory_region(kvm, mem); @@ -967,16 +975,18 @@ int kvm_get_dirty_log(struct kvm *kvm, { struct kvm_memslots *slots; struct kvm_memory_slot *memslot; - int r, i; + int r, i, as_id, id; unsigned long n; unsigned long any = 0; r = -EINVAL; - if (log->slot >= KVM_USER_MEM_SLOTS) + as_id = log->slot >> 16; + id = (u16)log->slot; + if (as_id >= KVM_ADDRESS_SPACE_NUM || id >= KVM_USER_MEM_SLOTS) goto out; - slots = kvm_memslots(kvm); - memslot = id_to_memslot(slots, log->slot); + slots = __kvm_memslots(kvm, as_id); + memslot = id_to_memslot(slots, id); r = -ENOENT; if (!memslot->dirty_bitmap) goto out; @@ -1027,17 +1037,19 @@ int kvm_get_dirty_log_protect(struct kvm *kvm, { struct kvm_memslots *slots; struct kvm_memory_slot *memslot; - int r, i; + int r, i, as_id, id; unsigned long n; unsigned long *dirty_bitmap; unsigned long *dirty_bitmap_buffer; r = -EINVAL; - if (log->slot >= KVM_USER_MEM_SLOTS) + as_id = log->slot >> 16; + id = (u16)log->slot; + if (as_id >= KVM_ADDRESS_SPACE_NUM || id >= KVM_USER_MEM_SLOTS) goto out; - slots = kvm_memslots(kvm); - memslot = id_to_memslot(slots, log->slot); + slots = __kvm_memslots(kvm, as_id); + memslot = id_to_memslot(slots, id); dirty_bitmap = memslot->dirty_bitmap; r = -ENOENT; @@ -2619,6 +2631,10 @@ static long kvm_vm_ioctl_check_extension_generic(struct kvm *kvm, long arg) #ifdef CONFIG_HAVE_KVM_IRQ_ROUTING case KVM_CAP_IRQ_ROUTING: return KVM_MAX_IRQ_ROUTES; +#endif +#if KVM_ADDRESS_SPACE_NUM > 1 + case KVM_CAP_MULTI_ADDRESS_SPACE: + return KVM_ADDRESS_SPACE_NUM; #endif default: break; -- cgit v1.2.3 From 699023e239658e62da6f42f47d31b54788521ec1 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 18 May 2015 15:03:39 +0200 Subject: KVM: x86: add SMM to the MMU role, support SMRAM address space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is now very simple to do. The only interesting part is a simple trick to find the right memslot in gfn_to_rmap, retrieving the address space from the spte role word. The same trick is used in the auditing code. The comment on top of union kvm_mmu_page_role has been stale forever, so remove it. Speaking of stale code, remove pad_for_nice_hex_output too: it was splitting the "access" bitfield across two bytes and thus had effectively turned into pad_for_ugly_hex_output. Reviewed-by: Radim Krčmář Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/mmu.txt | 6 ++++++ arch/x86/include/asm/kvm_host.h | 26 +++++++++++++++----------- arch/x86/kvm/mmu.c | 15 ++++++++++++--- arch/x86/kvm/mmu_audit.c | 10 +++++++--- arch/x86/kvm/x86.c | 2 ++ 5 files changed, 42 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/virtual/kvm/mmu.txt b/Documentation/virtual/kvm/mmu.txt index c59bd9bc41ef..3a4d681c3e98 100644 --- a/Documentation/virtual/kvm/mmu.txt +++ b/Documentation/virtual/kvm/mmu.txt @@ -173,6 +173,12 @@ Shadow pages contain the following information: Contains the value of cr4.smap && !cr0.wp for which the page is valid (pages for which this is true are different from other pages; see the treatment of cr0.wp=0 below). + role.smm: + Is 1 if the page is valid in system management mode. This field + determines which of the kvm_memslots array was used to build this + shadow page; it is also used to go back from a struct kvm_mmu_page + to a memslot, through the kvm_memslots_for_spte_role macro and + __gfn_to_memslot. gfn: Either the guest page table containing the translations shadowed by this page, or the base page frame for linear translations. See role.direct. diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 5a5e13af6e03..47006683f2fe 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -184,23 +184,12 @@ struct kvm_mmu_memory_cache { void *objects[KVM_NR_MEM_OBJS]; }; -/* - * kvm_mmu_page_role, below, is defined as: - * - * bits 0:3 - total guest paging levels (2-4, or zero for real mode) - * bits 4:7 - page table level for this shadow (1-4) - * bits 8:9 - page table quadrant for 2-level guests - * bit 16 - direct mapping of virtual to physical mapping at gfn - * used for real mode and two-dimensional paging - * bits 17:19 - common access permissions for all ptes in this shadow page - */ union kvm_mmu_page_role { unsigned word; struct { unsigned level:4; unsigned cr4_pae:1; unsigned quadrant:2; - unsigned pad_for_nice_hex_output:6; unsigned direct:1; unsigned access:3; unsigned invalid:1; @@ -208,6 +197,15 @@ union kvm_mmu_page_role { unsigned cr0_wp:1; unsigned smep_andnot_wp:1; unsigned smap_andnot_wp:1; + unsigned :8; + + /* + * This is left at the top of the word so that + * kvm_memslots_for_spte_role can extract it with a + * simple shift. While there is room, give it a whole + * byte so it is also faster to load it from memory. + */ + unsigned smm:8; }; }; @@ -1120,6 +1118,12 @@ enum { #define HF_SMM_MASK (1 << 6) #define HF_SMM_INSIDE_NMI_MASK (1 << 7) +#define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE +#define KVM_ADDRESS_SPACE_NUM 2 + +#define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) +#define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) + /* * Hardware virtualization extension instructions may fault if a * reboot turns off virtualization while processes are running. diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 7619e9e1745c..c88f0e443669 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -806,13 +806,15 @@ static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) { + struct kvm_memslots *slots; struct kvm_memory_slot *slot; struct kvm_lpage_info *linfo; gfn_t gfn; int i; gfn = sp->gfn; - slot = gfn_to_memslot(kvm, gfn); + slots = kvm_memslots_for_spte_role(kvm, sp->role); + slot = __gfn_to_memslot(slots, gfn); for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { linfo = lpage_info_slot(gfn, slot, i); linfo->write_count += 1; @@ -822,13 +824,15 @@ static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) { + struct kvm_memslots *slots; struct kvm_memory_slot *slot; struct kvm_lpage_info *linfo; gfn_t gfn; int i; gfn = sp->gfn; - slot = gfn_to_memslot(kvm, gfn); + slots = kvm_memslots_for_spte_role(kvm, sp->role); + slot = __gfn_to_memslot(slots, gfn); for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { linfo = lpage_info_slot(gfn, slot, i); linfo->write_count -= 1; @@ -1045,9 +1049,11 @@ static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, */ static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, struct kvm_mmu_page *sp) { + struct kvm_memslots *slots; struct kvm_memory_slot *slot; - slot = gfn_to_memslot(kvm, gfn); + slots = kvm_memslots_for_spte_role(kvm, sp->role); + slot = __gfn_to_memslot(slots, gfn); return __gfn_to_rmap(gfn, sp->role.level, slot); } @@ -3924,6 +3930,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) struct kvm_mmu *context = &vcpu->arch.mmu; context->base_role.word = 0; + context->base_role.smm = is_smm(vcpu); context->page_fault = tdp_page_fault; context->sync_page = nonpaging_sync_page; context->invlpg = nonpaging_invlpg; @@ -3985,6 +3992,7 @@ void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) = smep && !is_write_protection(vcpu); context->base_role.smap_andnot_wp = smap && !is_write_protection(vcpu); + context->base_role.smm = is_smm(vcpu); } EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); @@ -4268,6 +4276,7 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, mask.nxe = 1; mask.smep_andnot_wp = 1; mask.smap_andnot_wp = 1; + mask.smm = 1; /* * If we don't have indirect shadow pages, it means no page is diff --git a/arch/x86/kvm/mmu_audit.c b/arch/x86/kvm/mmu_audit.c index 78288c15400c..a4f62e6f2db2 100644 --- a/arch/x86/kvm/mmu_audit.c +++ b/arch/x86/kvm/mmu_audit.c @@ -131,12 +131,16 @@ static void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) static DEFINE_RATELIMIT_STATE(ratelimit_state, 5 * HZ, 10); unsigned long *rmapp; struct kvm_mmu_page *rev_sp; + struct kvm_memslots *slots; + struct kvm_memory_slot *slot; gfn_t gfn; rev_sp = page_header(__pa(sptep)); gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt); - if (!gfn_to_memslot(kvm, gfn)) { + slots = kvm_memslots_for_spte_role(kvm, rev_sp->role); + slot = __gfn_to_memslot(slots, gfn); + if (!slot) { if (!__ratelimit(&ratelimit_state)) return; audit_printk(kvm, "no memslot for gfn %llx\n", gfn); @@ -146,7 +150,7 @@ static void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) return; } - rmapp = gfn_to_rmap(kvm, gfn, rev_sp); + rmapp = __gfn_to_rmap(gfn, rev_sp->role.level, slot); if (!*rmapp) { if (!__ratelimit(&ratelimit_state)) return; @@ -197,7 +201,7 @@ static void audit_write_protection(struct kvm *kvm, struct kvm_mmu_page *sp) if (sp->role.direct || sp->unsync || sp->role.invalid) return; - slots = kvm_memslots(kvm); + slots = kvm_memslots_for_spte_role(kvm, sp->role); slot = __gfn_to_memslot(slots, sp->gfn); rmapp = __gfn_to_rmap(sp->gfn, PT_PAGE_TABLE_LEVEL, slot); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index caa0d5f8e6b3..7489871b63df 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5490,6 +5490,8 @@ static void kvm_smm_changed(struct kvm_vcpu *vcpu) kvm_make_request(KVM_REQ_EVENT, vcpu); } } + + kvm_mmu_reset_context(vcpu); } static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) -- cgit v1.2.3 From e80a4a9426adeaa34c009bc0bc61365e0580bf01 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 4 Jun 2015 16:32:48 +0200 Subject: KVM: x86: mark legacy PCI device assignment as deprecated Follow up to commit e194bbdf362ba7d53cfd23ba24f1a7c90ef69a74. Suggested-by: Bandan Das Suggested-by: Alex Williamson Signed-off-by: Paolo Bonzini --- Documentation/virtual/kvm/api.txt | 14 +++++++------- arch/x86/kvm/Kconfig | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 461956a0ee8e..a7926a90156f 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -1294,7 +1294,7 @@ The flags bitmap is defined as: /* the host supports the ePAPR idle hcall #define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0) -4.48 KVM_ASSIGN_PCI_DEVICE +4.48 KVM_ASSIGN_PCI_DEVICE (deprecated) Capability: none Architectures: x86 @@ -1344,7 +1344,7 @@ Errors: have their standard meanings. -4.49 KVM_DEASSIGN_PCI_DEVICE +4.49 KVM_DEASSIGN_PCI_DEVICE (deprecated) Capability: none Architectures: x86 @@ -1363,7 +1363,7 @@ Errors: Other error conditions may be defined by individual device types or have their standard meanings. -4.50 KVM_ASSIGN_DEV_IRQ +4.50 KVM_ASSIGN_DEV_IRQ (deprecated) Capability: KVM_CAP_ASSIGN_DEV_IRQ Architectures: x86 @@ -1403,7 +1403,7 @@ Errors: have their standard meanings. -4.51 KVM_DEASSIGN_DEV_IRQ +4.51 KVM_DEASSIGN_DEV_IRQ (deprecated) Capability: KVM_CAP_ASSIGN_DEV_IRQ Architectures: x86 @@ -1477,7 +1477,7 @@ struct kvm_irq_routing_s390_adapter { }; -4.53 KVM_ASSIGN_SET_MSIX_NR +4.53 KVM_ASSIGN_SET_MSIX_NR (deprecated) Capability: none Architectures: x86 @@ -1499,7 +1499,7 @@ struct kvm_assigned_msix_nr { #define KVM_MAX_MSIX_PER_DEV 256 -4.54 KVM_ASSIGN_SET_MSIX_ENTRY +4.54 KVM_ASSIGN_SET_MSIX_ENTRY (deprecated) Capability: none Architectures: x86 @@ -1655,7 +1655,7 @@ should skip processing the bitmap and just invalidate everything. It must be set to the number of set bits in the bitmap. -4.61 KVM_ASSIGN_SET_INTX_MASK +4.61 KVM_ASSIGN_SET_INTX_MASK (deprecated) Capability: KVM_CAP_PCI_2_3 Architectures: x86 diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig index a0f06a5947c5..d8a1d56276e1 100644 --- a/arch/x86/kvm/Kconfig +++ b/arch/x86/kvm/Kconfig @@ -86,7 +86,7 @@ config KVM_MMU_AUDIT auditing of KVM MMU events at runtime. config KVM_DEVICE_ASSIGNMENT - bool "KVM legacy PCI device assignment support" + bool "KVM legacy PCI device assignment support (DEPRECATED)" depends on KVM && PCI && IOMMU_API default n ---help--- -- cgit v1.2.3 From 29e5eea06bc19114b1df668f85b605914766a899 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Apr 2015 11:25:54 +0200 Subject: ARM: EXYNOS: Get current parent clock for power domain on/off Using a fixed (by DTS) parent for clocks when turning on the power domain may introduce issues in other drivers. For example when such driver changes the parent during runtime and expects that he is the only place of such change. Do not rely on DTS providing the fixed parent for such clocks. Instead before switching domain off, grab a current parent of a clock with clk_get_parent(). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- .../devicetree/bindings/arm/exynos/power_domain.txt | 7 ++++--- arch/arm/mach-exynos/pm_domains.c | 16 +++++++++------- 2 files changed, 13 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 5da38c5ed476..e151057d92f0 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -19,9 +19,10 @@ Optional Properties: domains. - clock-names: The following clocks can be specified: - oscclk: Oscillator clock. - - pclkN, clkN: Pairs of parent of input clock and input clock to the - devices in this power domain. Maximum of 4 pairs (N = 0 to 3) - are supported currently. + - clkN: Input clocks to the devices in this power domain. These clocks + will be reparented to oscclk before swithing power domain off. + Their original parent will be brought back after turning on + the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - asbN: Clocks required by asynchronous bridges (ASB) present in the power domain. These clock should be enabled during power domain on/off operations. diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 440324c94d28..1639645bddeb 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -62,6 +62,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; + pd->pclk[i] = clk_get_parent(pd->clk[i]); if (clk_set_parent(pd->clk[i], pd->oscclk)) pr_err("%s: error setting oscclk as parent to clock %d\n", pd->name, i); @@ -90,6 +91,9 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; + + if (IS_ERR(pd->clk[i])) + continue; /* Skip on first power up */ if (clk_set_parent(pd->clk[i], pd->pclk[i])) pr_err("%s: error setting parent to clock%d\n", pd->name, i); @@ -182,13 +186,11 @@ static __init int exynos4_pm_init_power_domain(void) pd->clk[i] = clk_get(dev, clk_name); if (IS_ERR(pd->clk[i])) break; - snprintf(clk_name, sizeof(clk_name), "pclk%d", i); - pd->pclk[i] = clk_get(dev, clk_name); - if (IS_ERR(pd->pclk[i])) { - clk_put(pd->clk[i]); - pd->clk[i] = ERR_PTR(-EINVAL); - break; - } + /* + * Skip setting parent on first power up. + * The parent at this time may not be useful at all. + */ + pd->pclk[i] = ERR_PTR(-EINVAL); } if (IS_ERR(pd->clk[0])) -- cgit v1.2.3 From 496c28b13eb9d4f9c751b672daad8b110084cfd8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 29 May 2015 11:27:43 +0200 Subject: irqchip: renesas: intc-irqpin: Improve binding documentation Add missing documentation for required properties: - interrupt-controller, - parent interrupts (one entry per provided interrupt). Add missing documentation for optional properties: - functional clock (managed since commit 705bc96c2c15313c ("irqchip: renesas-intc-irqpin: Add minimal runtime PM support")), - power-domains. Add an example, taken from r8a7740.dtsi. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Cc: Jason Cooper Link: http://lkml.kernel.org/r/1432891663-23641-1-git-send-email-geert%2Brenesas@glider.be Signed-off-by: Thomas Gleixner --- .../interrupt-controller/renesas,intc-irqpin.txt | 39 ++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt index 4f7946ae8adc..772c550d3b4b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -13,9 +13,12 @@ Required properties: - reg: Base address and length of each register bank used by the external IRQ pins driven by the interrupt controller hardware module. The base addresses, length and number of required register banks varies with soctype. - +- interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory + interrupts.txt in this directory. +- interrupts: Must contain a list of interrupt specifiers. For each interrupt + provided by this irqpin controller instance, there must be one entry, + referring to the corresponding parent interrupt. Optional properties: @@ -25,3 +28,35 @@ Optional properties: if different from the default 4 bits - control-parent: disable and enable interrupts on the parent interrupt controller, needed for some broken implementations +- clocks: Must contain a reference to the functional clock. This property is + mandatory if the hardware implements a controllable functional clock for + the irqpin controller instance. +- power-domains: Must contain a reference to the power domain. This property is + mandatory if the irqpin controller instance is part of a controllable power + domain. + + +Example +------- + + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", + "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; -- cgit v1.2.3 From dcd19de36775b689df602139f3e40bfb114d5d12 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Fri, 5 Jun 2015 15:56:34 -0500 Subject: PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver APM X-Gene v1 SoC supports its own implementation of MSI, which is not compliant to GIC V2M specification for MSI Termination. There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. This MSI block supports 2048 MSI termination ports coalesced into 16 physical HW IRQ lines and shared across all 5 PCIe ports. As there are only 16 HW IRQs to serve 2048 MSI vectors, to support set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores). To steer MSI interrupt to target CPU, MSI vector is moved around these HW IRQs lines. With this approach, the total MSI vectors this driver supports is reduced to 256. [bhelgaas: squash doc, driver, maintainer update] Signed-off-by: Duc Dang Signed-off-by: Tanmay Inamdar Signed-off-by: Bjorn Helgaas Reviewed-by: Marc Zyngier --- .../devicetree/bindings/pci/xgene-pci-msi.txt | 68 +++ MAINTAINERS | 8 + drivers/pci/host/Kconfig | 9 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-xgene-msi.c | 596 +++++++++++++++++++++ drivers/pci/host/pci-xgene.c | 21 + 6 files changed, 703 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xgene-pci-msi.txt create mode 100644 drivers/pci/host/pci-xgene-msi.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt new file mode 100644 index 000000000000..36d881c8e6d4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt @@ -0,0 +1,68 @@ +* AppliedMicro X-Gene v1 PCIe MSI controller + +Required properties: + +- compatible: should be "apm,xgene1-msi" to identify + X-Gene v1 PCIe MSI controller block. +- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node +- reg: physical base address (0x79000000) and length (0x900000) for controller + registers. These registers include the MSI termination address and data + registers as well as the MSI interrupt status registers. +- reg-names: not required +- interrupts: A list of 16 interrupt outputs of the controller, starting from + interrupt number 0x10 to 0x1f. +- interrupt-names: not required + +Each PCIe node needs to have property msi-parent that points to msi controller node + +Examples: + +SoC DTSI: + + + MSI node: + msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x00 0x79000000 0x0 0x900000>; + interrupts = <0x0 0x10 0x4> + <0x0 0x11 0x4> + <0x0 0x12 0x4> + <0x0 0x13 0x4> + <0x0 0x14 0x4> + <0x0 0x15 0x4> + <0x0 0x16 0x4> + <0x0 0x17 0x4> + <0x0 0x18 0x4> + <0x0 0x19 0x4> + <0x0 0x1a 0x4> + <0x0 0x1b 0x4> + <0x0 0x1c 0x4> + <0x0 0x1d 0x4> + <0x0 0x1e 0x4> + <0x0 0x1f 0x4>; + }; + + + PCIe controller node with msi-parent property pointing to MSI node: + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + dma-coherent; + clocks = <&pcie0clk 0>; + msi-parent= <&msi>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 781e099495d3..59aa7b321c40 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7564,6 +7564,14 @@ L: linux-pci@vger.kernel.org S: Orphan F: drivers/pci/host/*spear* +PCI MSI DRIVER FOR APPLIEDMICRO XGENE +M: Duc Dang +L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt +F: drivers/pci/host/pci-xgene-msi.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: linux-pcmcia@lists.infradead.org diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 1dfb567b3522..9c48e9986bc7 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -89,11 +89,20 @@ config PCI_XGENE depends on ARCH_XGENE depends on OF select PCIEPORTBUS + select PCI_MSI_IRQ_DOMAIN if PCI_MSI help Say Y here if you want internal PCI support on APM X-Gene SoC. There are 5 internal PCIe ports available. Each port is GEN3 capable and have varied lanes from x1 to x8. +config PCI_XGENE_MSI + bool "X-Gene v1 PCIe MSI feature" + depends on PCI_XGENE && PCI_MSI + default y + help + Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC. + This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC. + config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on OF && ARM diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index f733b4e27642..1957431d3fcc 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o obj-$(CONFIG_PCI_XGENE) += pci-xgene.o +obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o diff --git a/drivers/pci/host/pci-xgene-msi.c b/drivers/pci/host/pci-xgene-msi.c new file mode 100644 index 000000000000..2d31d4d6fd08 --- /dev/null +++ b/drivers/pci/host/pci-xgene-msi.c @@ -0,0 +1,596 @@ +/* + * APM X-Gene MSI Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Author: Tanmay Inamdar + * Duc Dang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MSI_IR0 0x000000 +#define MSI_INT0 0x800000 +#define IDX_PER_GROUP 8 +#define IRQS_PER_IDX 16 +#define NR_HW_IRQS 16 +#define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) + +struct xgene_msi_group { + struct xgene_msi *msi; + int gic_irq; + u32 msi_grp; +}; + +struct xgene_msi { + struct device_node *node; + struct msi_controller mchip; + struct irq_domain *domain; + u64 msi_addr; + void __iomem *msi_regs; + unsigned long *bitmap; + struct mutex bitmap_lock; + struct xgene_msi_group *msi_groups; + int num_cpus; +}; + +/* Global data */ +static struct xgene_msi xgene_msi_ctrl; + +static struct irq_chip xgene_msi_top_irq_chip = { + .name = "X-Gene1 MSI", + .irq_enable = pci_msi_unmask_irq, + .irq_disable = pci_msi_mask_irq, + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static struct msi_domain_info xgene_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX), + .chip = &xgene_msi_top_irq_chip, +}; + +/* + * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where + * n is group number (0..F), x is index of registers in each group (0..7) + * The register layout is as follows: + * MSI0IR0 base_addr + * MSI0IR1 base_addr + 0x10000 + * ... ... + * MSI0IR6 base_addr + 0x60000 + * MSI0IR7 base_addr + 0x70000 + * MSI1IR0 base_addr + 0x80000 + * MSI1IR1 base_addr + 0x90000 + * ... ... + * MSI1IR7 base_addr + 0xF0000 + * MSI2IR0 base_addr + 0x100000 + * ... ... + * MSIFIR0 base_addr + 0x780000 + * MSIFIR1 base_addr + 0x790000 + * ... ... + * MSIFIR7 base_addr + 0x7F0000 + * MSIINT0 base_addr + 0x800000 + * MSIINT1 base_addr + 0x810000 + * ... ... + * MSIINTF base_addr + 0x8F0000 + * + * Each index register supports 16 MSI vectors (0..15) to generate interrupt. + * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination + * registers. + * + * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate + * the MSI pending status caused by 1 of its 8 index registers. + */ + +/* MSInIRx read helper */ +static u32 xgene_msi_ir_read(struct xgene_msi *msi, + u32 msi_grp, u32 msir_idx) +{ + return readl_relaxed(msi->msi_regs + MSI_IR0 + + (msi_grp << 19) + (msir_idx << 16)); +} + +/* MSIINTn read helper */ +static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp) +{ + return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16)); +} + +/* + * With 2048 MSI vectors supported, the MSI message can be constructed using + * following scheme: + * - Divide into 8 256-vector groups + * Group 0: 0-255 + * Group 1: 256-511 + * Group 2: 512-767 + * ... + * Group 7: 1792-2047 + * - Each 256-vector group is divided into 16 16-vector groups + * As an example: 16 16-vector groups for 256-vector group 0-255 is + * Group 0: 0-15 + * Group 1: 16-32 + * ... + * Group 15: 240-255 + * - The termination address of MSI vector in 256-vector group n and 16-vector + * group x is the address of MSIxIRn + * - The data for MSI vector in 16-vector group x is x + */ +static u32 hwirq_to_reg_set(unsigned long hwirq) +{ + return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX)); +} + +static u32 hwirq_to_group(unsigned long hwirq) +{ + return (hwirq % NR_HW_IRQS); +} + +static u32 hwirq_to_msi_data(unsigned long hwirq) +{ + return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX); +} + +static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct xgene_msi *msi = irq_data_get_irq_chip_data(data); + u32 reg_set = hwirq_to_reg_set(data->hwirq); + u32 group = hwirq_to_group(data->hwirq); + u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16); + + msg->address_hi = upper_32_bits(target_addr); + msg->address_lo = lower_32_bits(target_addr); + msg->data = hwirq_to_msi_data(data->hwirq); +} + +/* + * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain + * the expected behaviour of .set_affinity for each MSI interrupt, the 16 + * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs + * for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another + * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a + * consequence, the total MSI vectors that X-Gene v1 supports will be + * reduced to 256 (2048/8) vectors. + */ +static int hwirq_to_cpu(unsigned long hwirq) +{ + return (hwirq % xgene_msi_ctrl.num_cpus); +} + +static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) +{ + return (hwirq - hwirq_to_cpu(hwirq)); +} + +static int xgene_msi_set_affinity(struct irq_data *irqdata, + const struct cpumask *mask, bool force) +{ + int target_cpu = cpumask_first(mask); + int curr_cpu; + + curr_cpu = hwirq_to_cpu(irqdata->hwirq); + if (curr_cpu == target_cpu) + return IRQ_SET_MASK_OK_DONE; + + /* Update MSI number to target the new CPU */ + irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu; + + return IRQ_SET_MASK_OK; +} + +static struct irq_chip xgene_msi_bottom_irq_chip = { + .name = "MSI", + .irq_set_affinity = xgene_msi_set_affinity, + .irq_compose_msi_msg = xgene_compose_msi_msg, +}; + +static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct xgene_msi *msi = domain->host_data; + int msi_irq; + + mutex_lock(&msi->bitmap_lock); + + msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0, + msi->num_cpus, 0); + if (msi_irq < NR_MSI_VEC) + bitmap_set(msi->bitmap, msi_irq, msi->num_cpus); + else + msi_irq = -ENOSPC; + + mutex_unlock(&msi->bitmap_lock); + + if (msi_irq < 0) + return msi_irq; + + irq_domain_set_info(domain, virq, msi_irq, + &xgene_msi_bottom_irq_chip, domain->host_data, + handle_simple_irq, NULL, NULL); + set_irq_flags(virq, IRQF_VALID); + + return 0; +} + +static void xgene_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct xgene_msi *msi = irq_data_get_irq_chip_data(d); + u32 hwirq; + + mutex_lock(&msi->bitmap_lock); + + hwirq = hwirq_to_canonical_hwirq(d->hwirq); + bitmap_clear(msi->bitmap, hwirq, msi->num_cpus); + + mutex_unlock(&msi->bitmap_lock); + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops msi_domain_ops = { + .alloc = xgene_irq_domain_alloc, + .free = xgene_irq_domain_free, +}; + +static int xgene_allocate_domains(struct xgene_msi *msi) +{ + msi->domain = irq_domain_add_linear(NULL, NR_MSI_VEC, + &msi_domain_ops, msi); + if (!msi->domain) + return -ENOMEM; + + msi->mchip.domain = pci_msi_create_irq_domain(msi->mchip.of_node, + &xgene_msi_domain_info, + msi->domain); + + if (!msi->mchip.domain) { + irq_domain_remove(msi->domain); + return -ENOMEM; + } + + return 0; +} + +static void xgene_free_domains(struct xgene_msi *msi) +{ + if (msi->mchip.domain) + irq_domain_remove(msi->mchip.domain); + if (msi->domain) + irq_domain_remove(msi->domain); +} + +static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi) +{ + int size = BITS_TO_LONGS(NR_MSI_VEC) * sizeof(long); + + xgene_msi->bitmap = kzalloc(size, GFP_KERNEL); + if (!xgene_msi->bitmap) + return -ENOMEM; + + mutex_init(&xgene_msi->bitmap_lock); + + xgene_msi->msi_groups = kcalloc(NR_HW_IRQS, + sizeof(struct xgene_msi_group), + GFP_KERNEL); + if (!xgene_msi->msi_groups) + return -ENOMEM; + + return 0; +} + +static void xgene_msi_isr(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct xgene_msi_group *msi_groups; + struct xgene_msi *xgene_msi; + unsigned int virq; + int msir_index, msir_val, hw_irq; + u32 intr_index, grp_select, msi_grp; + + chained_irq_enter(chip, desc); + + msi_groups = irq_desc_get_handler_data(desc); + xgene_msi = msi_groups->msi; + msi_grp = msi_groups->msi_grp; + + /* + * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt + * If bit x of this register is set (x is 0..7), one or more interupts + * corresponding to MSInIRx is set. + */ + grp_select = xgene_msi_int_read(xgene_msi, msi_grp); + while (grp_select) { + msir_index = ffs(grp_select) - 1; + /* + * Calculate MSInIRx address to read to check for interrupts + * (refer to termination address and data assignment + * described in xgene_compose_msi_msg() ) + */ + msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index); + while (msir_val) { + intr_index = ffs(msir_val) - 1; + /* + * Calculate MSI vector number (refer to the termination + * address and data assignment described in + * xgene_compose_msi_msg function) + */ + hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) * + NR_HW_IRQS) + msi_grp; + /* + * As we have multiple hw_irq that maps to single MSI, + * always look up the virq using the hw_irq as seen from + * CPU0 + */ + hw_irq = hwirq_to_canonical_hwirq(hw_irq); + virq = irq_find_mapping(xgene_msi->domain, hw_irq); + WARN_ON(!virq); + if (virq != 0) + generic_handle_irq(virq); + msir_val &= ~(1 << intr_index); + } + grp_select &= ~(1 << msir_index); + + if (!grp_select) { + /* + * We handled all interrupts happened in this group, + * resample this group MSI_INTx register in case + * something else has been made pending in the meantime + */ + grp_select = xgene_msi_int_read(xgene_msi, msi_grp); + } + } + + chained_irq_exit(chip, desc); +} + +static int xgene_msi_remove(struct platform_device *pdev) +{ + int virq, i; + struct xgene_msi *msi = platform_get_drvdata(pdev); + + for (i = 0; i < NR_HW_IRQS; i++) { + virq = msi->msi_groups[i].gic_irq; + if (virq != 0) { + irq_set_chained_handler(virq, NULL); + irq_set_handler_data(virq, NULL); + } + } + kfree(msi->msi_groups); + + kfree(msi->bitmap); + msi->bitmap = NULL; + + xgene_free_domains(msi); + + return 0; +} + +static int xgene_msi_hwirq_alloc(unsigned int cpu) +{ + struct xgene_msi *msi = &xgene_msi_ctrl; + struct xgene_msi_group *msi_group; + cpumask_var_t mask; + int i; + int err; + + for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { + msi_group = &msi->msi_groups[i]; + if (!msi_group->gic_irq) + continue; + + irq_set_chained_handler(msi_group->gic_irq, + xgene_msi_isr); + err = irq_set_handler_data(msi_group->gic_irq, msi_group); + if (err) { + pr_err("failed to register GIC IRQ handler\n"); + return -EINVAL; + } + /* + * Statically allocate MSI GIC IRQs to each CPU core. + * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated + * to each core. + */ + if (alloc_cpumask_var(&mask, GFP_KERNEL)) { + cpumask_clear(mask); + cpumask_set_cpu(cpu, mask); + err = irq_set_affinity(msi_group->gic_irq, mask); + if (err) + pr_err("failed to set affinity for GIC IRQ"); + free_cpumask_var(mask); + } else { + pr_err("failed to alloc CPU mask for affinity\n"); + err = -EINVAL; + } + + if (err) { + irq_set_chained_handler(msi_group->gic_irq, NULL); + irq_set_handler_data(msi_group->gic_irq, NULL); + return err; + } + } + + return 0; +} + +static void xgene_msi_hwirq_free(unsigned int cpu) +{ + struct xgene_msi *msi = &xgene_msi_ctrl; + struct xgene_msi_group *msi_group; + int i; + + for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { + msi_group = &msi->msi_groups[i]; + if (!msi_group->gic_irq) + continue; + + irq_set_chained_handler(msi_group->gic_irq, NULL); + irq_set_handler_data(msi_group->gic_irq, NULL); + } +} + +static int xgene_msi_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + unsigned cpu = (unsigned long)hcpu; + + switch (action) { + case CPU_ONLINE: + case CPU_ONLINE_FROZEN: + xgene_msi_hwirq_alloc(cpu); + break; + case CPU_DEAD: + case CPU_DEAD_FROZEN: + xgene_msi_hwirq_free(cpu); + break; + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block xgene_msi_cpu_notifier = { + .notifier_call = xgene_msi_cpu_callback, +}; + +static const struct of_device_id xgene_msi_match_table[] = { + {.compatible = "apm,xgene1-msi"}, + {}, +}; + +static int xgene_msi_probe(struct platform_device *pdev) +{ + struct resource *res; + int rc, irq_index; + struct xgene_msi *xgene_msi; + unsigned int cpu; + int virt_msir; + u32 msi_val, msi_idx; + + xgene_msi = &xgene_msi_ctrl; + + platform_set_drvdata(pdev, xgene_msi); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xgene_msi->msi_regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(xgene_msi->msi_regs)) { + dev_err(&pdev->dev, "no reg space\n"); + rc = -EINVAL; + goto error; + } + xgene_msi->msi_addr = res->start; + + xgene_msi->num_cpus = num_possible_cpus(); + + rc = xgene_msi_init_allocator(xgene_msi); + if (rc) { + dev_err(&pdev->dev, "Error allocating MSI bitmap\n"); + goto error; + } + + rc = xgene_allocate_domains(xgene_msi); + if (rc) { + dev_err(&pdev->dev, "Failed to allocate MSI domain\n"); + goto error; + } + + for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { + virt_msir = platform_get_irq(pdev, irq_index); + if (virt_msir < 0) { + dev_err(&pdev->dev, "Cannot translate IRQ index %d\n", + irq_index); + rc = -EINVAL; + goto error; + } + xgene_msi->msi_groups[irq_index].gic_irq = virt_msir; + xgene_msi->msi_groups[irq_index].msi_grp = irq_index; + xgene_msi->msi_groups[irq_index].msi = xgene_msi; + } + + /* + * MSInIRx registers are read-to-clear; before registering + * interrupt handlers, read all of them to clear spurious + * interrupts that may occur before the driver is probed. + */ + for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { + for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++) + msi_val = xgene_msi_ir_read(xgene_msi, irq_index, + msi_idx); + /* Read MSIINTn to confirm */ + msi_val = xgene_msi_int_read(xgene_msi, irq_index); + if (msi_val) { + dev_err(&pdev->dev, "Failed to clear spurious IRQ\n"); + rc = -EINVAL; + goto error; + } + } + + cpu_notifier_register_begin(); + + for_each_online_cpu(cpu) + if (xgene_msi_hwirq_alloc(cpu)) { + dev_err(&pdev->dev, "failed to register MSI handlers\n"); + cpu_notifier_register_done(); + goto error; + } + + rc = __register_hotcpu_notifier(&xgene_msi_cpu_notifier); + if (rc) { + dev_err(&pdev->dev, "failed to add CPU MSI notifier\n"); + cpu_notifier_register_done(); + goto error; + } + + cpu_notifier_register_done(); + + xgene_msi->mchip.of_node = pdev->dev.of_node; + rc = of_pci_msi_chip_add(&xgene_msi->mchip); + if (rc) { + dev_err(&pdev->dev, "failed to add MSI controller chip\n"); + goto error_notifier; + } + + dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n"); + + return 0; + +error_notifier: + unregister_hotcpu_notifier(&xgene_msi_cpu_notifier); +error: + xgene_msi_remove(pdev); + return rc; +} + +static struct platform_driver xgene_msi_driver = { + .driver = { + .name = "xgene-msi", + .owner = THIS_MODULE, + .of_match_table = xgene_msi_match_table, + }, + .probe = xgene_msi_probe, + .remove = xgene_msi_remove, +}; + +static int __init xgene_pcie_msi_init(void) +{ + return platform_driver_register(&xgene_msi_driver); +} +subsys_initcall(xgene_pcie_msi_init); diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c index ee082c0366ec..3e5a636c9a9a 100644 --- a/drivers/pci/host/pci-xgene.c +++ b/drivers/pci/host/pci-xgene.c @@ -468,6 +468,23 @@ static int xgene_pcie_setup(struct xgene_pcie_port *port, return 0; } +static int xgene_pcie_msi_enable(struct pci_bus *bus) +{ + struct device_node *msi_node; + + msi_node = of_parse_phandle(bus->dev.of_node, + "msi-parent", 0); + if (!msi_node) + return -ENODEV; + + bus->msi = of_pci_find_msi_chip_by_node(msi_node); + if (!bus->msi) + return -ENODEV; + + bus->msi->dev = &bus->dev; + return 0; +} + static int xgene_pcie_probe_bridge(struct platform_device *pdev) { struct device_node *dn = pdev->dev.of_node; @@ -504,6 +521,10 @@ static int xgene_pcie_probe_bridge(struct platform_device *pdev) if (!bus) return -ENOMEM; + if (IS_ENABLED(CONFIG_PCI_MSI)) + if (xgene_pcie_msi_enable(bus)) + dev_info(port->dev, "failed to enable MSI\n"); + pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); pci_bus_add_devices(bus); -- cgit v1.2.3 From b322582fc1cfda977996e315b3c9e83018a39af3 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Fri, 5 Jun 2015 21:38:19 +0900 Subject: Doc:nfc: Fix typo in nfc-hci.txt This patch fix a spelling typo in nfc-hci.txt Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/nfc/nfc-hci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/nfc/nfc-hci.txt b/Documentation/nfc/nfc-hci.txt index 0686c9e211c2..0dc078cab972 100644 --- a/Documentation/nfc/nfc-hci.txt +++ b/Documentation/nfc/nfc-hci.txt @@ -122,7 +122,7 @@ This must be done from a context that can sleep. PHY Management -------------- -The physical link (i2c, ...) management is defined by the following struture: +The physical link (i2c, ...) management is defined by the following structure: struct nfc_phy_ops { int (*write)(void *dev_id, struct sk_buff *skb); -- cgit v1.2.3 From 12545fa33ad3363c639ec56bb84c8a58cfbcf65b Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 1 Jun 2015 13:13:54 +0200 Subject: clk: meson: Document bindings for Meson8b clock controller Add documentation for the clock controller. Signed-off-by: Carlo Caione Signed-off-by: Stephen Boyd --- .../bindings/clock/amlogic,meson8b-clkc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt new file mode 100644 index 000000000000..2b7b3fa588d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -0,0 +1,40 @@ +* Amlogic Meson8b Clock and Reset Unit + +The Amlogic Meson8b clock controller generates and supplies clock to various +controllers within the SoC. + +Required Properties: + +- compatible: should be "amlogic,meson8b-clkc" +- reg: it must be composed by two tuples: + 0) physical base address of the xtal register and length of memory + mapped region. + 1) physical base address of the clock controller and length of memory + mapped region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be +used in device tree sources. + +Example: Clock controller node: + + clkc: clock-controller@c1104000 { + #clock-cells = <1>; + compatible = "amlogic,meson8b-clkc"; + reg = <0xc1108000 0x4>, <0xc1104000 0x460>; + }; + + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart_AO: serial@c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clkc CLKID_CLK81>; + status = "disabled"; + }; -- cgit v1.2.3 From 63344b6592f1d69e13d0e32d8b213137ab6b663e Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 1 Jun 2015 07:15:53 -0300 Subject: [media] vivid: move video loopback control to the capture device This has been on my TODO list for some time now: the control that enables the video loopback was part of the controls of the video output device instead of the video capture device. In practice this was quite annoying since you expect it at the capture side since that's where you want to make the decision whether to use the TPG or looped video. This patch moves the control from the output to the capture side. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/vivid.txt | 2 +- drivers/media/platform/vivid/vivid-core.h | 2 +- drivers/media/platform/vivid/vivid-ctrls.c | 81 +++++++++++++++--------------- 3 files changed, 42 insertions(+), 43 deletions(-) (limited to 'Documentation') diff --git a/Documentation/video4linux/vivid.txt b/Documentation/video4linux/vivid.txt index 0c1b3a6ba6be..e35d376b7f64 100644 --- a/Documentation/video4linux/vivid.txt +++ b/Documentation/video4linux/vivid.txt @@ -895,7 +895,7 @@ Section 10.1: Video and Sliced VBI looping The way to enable video/VBI looping is currently fairly crude. A 'Loop Video' control is available in the "Vivid" control class of the video -output and VBI output devices. When checked the video looping will be enabled. +capture and VBI capture devices. When checked the video looping will be enabled. Once enabled any video S-Video or HDMI input will show a static test pattern until the video output has started. At that time the video output will be looped to the video input provided that: diff --git a/drivers/media/platform/vivid/vivid-core.h b/drivers/media/platform/vivid/vivid-core.h index 3755b1858426..c72349c83fab 100644 --- a/drivers/media/platform/vivid/vivid-core.h +++ b/drivers/media/platform/vivid/vivid-core.h @@ -139,7 +139,7 @@ struct vivid_dev { struct v4l2_ctrl_handler ctrl_hdl_user_aud; struct v4l2_ctrl_handler ctrl_hdl_streaming; struct v4l2_ctrl_handler ctrl_hdl_sdtv_cap; - struct v4l2_ctrl_handler ctrl_hdl_loop_out; + struct v4l2_ctrl_handler ctrl_hdl_loop_cap; struct video_device vid_cap_dev; struct v4l2_ctrl_handler ctrl_hdl_vid_cap; struct video_device vid_out_dev; diff --git a/drivers/media/platform/vivid/vivid-ctrls.c b/drivers/media/platform/vivid/vivid-ctrls.c index 1898751c20c8..339c8b7e53c8 100644 --- a/drivers/media/platform/vivid/vivid-ctrls.c +++ b/drivers/media/platform/vivid/vivid-ctrls.c @@ -793,6 +793,37 @@ static const struct v4l2_ctrl_config vivid_ctrl_limited_rgb_range = { }; +/* Video Loop Control */ + +static int vivid_loop_cap_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_loop_cap); + + switch (ctrl->id) { + case VIVID_CID_LOOP_VIDEO: + dev->loop_video = ctrl->val; + vivid_update_quality(dev); + vivid_send_source_change(dev, SVID); + vivid_send_source_change(dev, HDMI); + break; + } + return 0; +} + +static const struct v4l2_ctrl_ops vivid_loop_cap_ctrl_ops = { + .s_ctrl = vivid_loop_cap_s_ctrl, +}; + +static const struct v4l2_ctrl_config vivid_ctrl_loop_video = { + .ops = &vivid_loop_cap_ctrl_ops, + .id = VIVID_CID_LOOP_VIDEO, + .name = "Loop Video", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .max = 1, + .step = 1, +}; + + /* VBI Capture Control */ static int vivid_vbi_cap_s_ctrl(struct v4l2_ctrl *ctrl) @@ -1226,38 +1257,6 @@ static const struct v4l2_ctrl_config vivid_ctrl_radio_tx_rds_blockio = { }; - -/* Video Loop Control */ - -static int vivid_loop_out_s_ctrl(struct v4l2_ctrl *ctrl) -{ - struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_loop_out); - - switch (ctrl->id) { - case VIVID_CID_LOOP_VIDEO: - dev->loop_video = ctrl->val; - vivid_update_quality(dev); - vivid_send_source_change(dev, SVID); - vivid_send_source_change(dev, HDMI); - break; - } - return 0; -} - -static const struct v4l2_ctrl_ops vivid_loop_out_ctrl_ops = { - .s_ctrl = vivid_loop_out_s_ctrl, -}; - -static const struct v4l2_ctrl_config vivid_ctrl_loop_video = { - .ops = &vivid_loop_out_ctrl_ops, - .id = VIVID_CID_LOOP_VIDEO, - .name = "Loop Video", - .type = V4L2_CTRL_TYPE_BOOLEAN, - .max = 1, - .step = 1, -}; - - static const struct v4l2_ctrl_config vivid_ctrl_class = { .ops = &vivid_user_gen_ctrl_ops, .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_WRITE_ONLY, @@ -1275,7 +1274,7 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, struct v4l2_ctrl_handler *hdl_user_aud = &dev->ctrl_hdl_user_aud; struct v4l2_ctrl_handler *hdl_streaming = &dev->ctrl_hdl_streaming; struct v4l2_ctrl_handler *hdl_sdtv_cap = &dev->ctrl_hdl_sdtv_cap; - struct v4l2_ctrl_handler *hdl_loop_out = &dev->ctrl_hdl_loop_out; + struct v4l2_ctrl_handler *hdl_loop_cap = &dev->ctrl_hdl_loop_cap; struct v4l2_ctrl_handler *hdl_vid_cap = &dev->ctrl_hdl_vid_cap; struct v4l2_ctrl_handler *hdl_vid_out = &dev->ctrl_hdl_vid_out; struct v4l2_ctrl_handler *hdl_vbi_cap = &dev->ctrl_hdl_vbi_cap; @@ -1301,8 +1300,8 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_class, NULL); v4l2_ctrl_handler_init(hdl_sdtv_cap, 2); v4l2_ctrl_new_custom(hdl_sdtv_cap, &vivid_ctrl_class, NULL); - v4l2_ctrl_handler_init(hdl_loop_out, 1); - v4l2_ctrl_new_custom(hdl_loop_out, &vivid_ctrl_class, NULL); + v4l2_ctrl_handler_init(hdl_loop_cap, 1); + v4l2_ctrl_new_custom(hdl_loop_cap, &vivid_ctrl_class, NULL); v4l2_ctrl_handler_init(hdl_vid_cap, 55); v4l2_ctrl_new_custom(hdl_vid_cap, &vivid_ctrl_class, NULL); v4l2_ctrl_handler_init(hdl_vid_out, 26); @@ -1473,7 +1472,7 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, } if ((dev->has_vid_cap && dev->has_vid_out) || (dev->has_vbi_cap && dev->has_vbi_out)) - v4l2_ctrl_new_custom(hdl_loop_out, &vivid_ctrl_loop_video, NULL); + v4l2_ctrl_new_custom(hdl_loop_cap, &vivid_ctrl_loop_video, NULL); if (dev->has_fb) v4l2_ctrl_new_custom(hdl_user_gen, &vivid_ctrl_clear_fb, NULL); @@ -1556,8 +1555,8 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, return hdl_streaming->error; if (hdl_sdr_cap->error) return hdl_sdr_cap->error; - if (hdl_loop_out->error) - return hdl_loop_out->error; + if (hdl_loop_cap->error) + return hdl_loop_cap->error; if (dev->autogain) v4l2_ctrl_auto_cluster(2, &dev->autogain, 0, true); @@ -1568,6 +1567,7 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, v4l2_ctrl_add_handler(hdl_vid_cap, hdl_user_aud, NULL); v4l2_ctrl_add_handler(hdl_vid_cap, hdl_streaming, NULL); v4l2_ctrl_add_handler(hdl_vid_cap, hdl_sdtv_cap, NULL); + v4l2_ctrl_add_handler(hdl_vid_cap, hdl_loop_cap, NULL); if (hdl_vid_cap->error) return hdl_vid_cap->error; dev->vid_cap_dev.ctrl_handler = hdl_vid_cap; @@ -1576,7 +1576,6 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, v4l2_ctrl_add_handler(hdl_vid_out, hdl_user_gen, NULL); v4l2_ctrl_add_handler(hdl_vid_out, hdl_user_aud, NULL); v4l2_ctrl_add_handler(hdl_vid_out, hdl_streaming, NULL); - v4l2_ctrl_add_handler(hdl_vid_out, hdl_loop_out, NULL); if (hdl_vid_out->error) return hdl_vid_out->error; dev->vid_out_dev.ctrl_handler = hdl_vid_out; @@ -1585,6 +1584,7 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, v4l2_ctrl_add_handler(hdl_vbi_cap, hdl_user_gen, NULL); v4l2_ctrl_add_handler(hdl_vbi_cap, hdl_streaming, NULL); v4l2_ctrl_add_handler(hdl_vbi_cap, hdl_sdtv_cap, NULL); + v4l2_ctrl_add_handler(hdl_vbi_cap, hdl_loop_cap, NULL); if (hdl_vbi_cap->error) return hdl_vbi_cap->error; dev->vbi_cap_dev.ctrl_handler = hdl_vbi_cap; @@ -1592,7 +1592,6 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, if (dev->has_vbi_out) { v4l2_ctrl_add_handler(hdl_vbi_out, hdl_user_gen, NULL); v4l2_ctrl_add_handler(hdl_vbi_out, hdl_streaming, NULL); - v4l2_ctrl_add_handler(hdl_vbi_out, hdl_loop_out, NULL); if (hdl_vbi_out->error) return hdl_vbi_out->error; dev->vbi_out_dev.ctrl_handler = hdl_vbi_out; @@ -1635,5 +1634,5 @@ void vivid_free_controls(struct vivid_dev *dev) v4l2_ctrl_handler_free(&dev->ctrl_hdl_user_aud); v4l2_ctrl_handler_free(&dev->ctrl_hdl_streaming); v4l2_ctrl_handler_free(&dev->ctrl_hdl_sdtv_cap); - v4l2_ctrl_handler_free(&dev->ctrl_hdl_loop_out); + v4l2_ctrl_handler_free(&dev->ctrl_hdl_loop_cap); } -- cgit v1.2.3 From dc8b1c0e89f3473221f35b7aaf7419e2d2c16fe9 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 5 Jun 2015 05:11:15 -0300 Subject: [media] DocBook media: correct description of reserved fields Make sure that the documentation clearly states who is zeroing reserved fields: drivers and/or applications. This patch syncs the documentation with the checks that v4l2-compliance and valgrind do. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/v4l/io.xml | 12 ++++++------ Documentation/DocBook/media/v4l/pixfmt.xml | 8 ++++---- Documentation/DocBook/media/v4l/vidioc-create-bufs.xml | 3 ++- .../DocBook/media/v4l/vidioc-enum-frameintervals.xml | 3 ++- Documentation/DocBook/media/v4l/vidioc-enum-framesizes.xml | 3 ++- Documentation/DocBook/media/v4l/vidioc-expbuf.xml | 3 ++- Documentation/DocBook/media/v4l/vidioc-g-selection.xml | 2 +- Documentation/DocBook/media/v4l/vidioc-querybuf.xml | 3 ++- Documentation/DocBook/media/v4l/vidioc-reqbufs.xml | 4 ++-- 9 files changed, 23 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/v4l/io.xml b/Documentation/DocBook/media/v4l/io.xml index bfe666204888..7bbc2a48911e 100644 --- a/Documentation/DocBook/media/v4l/io.xml +++ b/Documentation/DocBook/media/v4l/io.xml @@ -841,15 +841,15 @@ is the file descriptor associated with a DMABUF buffer. __u32 reserved2 - A place holder for future extensions. Applications -should set this to 0. + A place holder for future extensions. Drivers and applications +must set this to 0. __u32 reserved - A place holder for future extensions. Applications -should set this to 0. + A place holder for future extensions. Drivers and applications +must set this to 0. @@ -930,8 +930,8 @@ should set this to 0. __u32 reserved[11] - Reserved for future use. Should be zeroed by an - application. + Reserved for future use. Should be zeroed by drivers and + applications. diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml index e7d88482a522..965ea916784a 100644 --- a/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/Documentation/DocBook/media/v4l/pixfmt.xml @@ -198,8 +198,8 @@ see . __u16 reserved[6] - Reserved for future extensions. Should be zeroed by the - application. + Reserved for future extensions. Should be zeroed by drivers and + applications. @@ -283,8 +283,8 @@ see . __u8 reserved[7] - Reserved for future extensions. Should be zeroed by the - application. + Reserved for future extensions. Should be zeroed by drivers + and applications. diff --git a/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml b/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml index 9b700a5f4df7..8ffe74f84af1 100644 --- a/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml +++ b/Documentation/DocBook/media/v4l/vidioc-create-bufs.xml @@ -134,7 +134,8 @@ information. __u32 reserved[8] - A place holder for future extensions. + A place holder for future extensions. Drivers and applications +must set the array to zero. diff --git a/Documentation/DocBook/media/v4l/vidioc-enum-frameintervals.xml b/Documentation/DocBook/media/v4l/vidioc-enum-frameintervals.xml index 5fd72c4c33e3..7c839ab0afbb 100644 --- a/Documentation/DocBook/media/v4l/vidioc-enum-frameintervals.xml +++ b/Documentation/DocBook/media/v4l/vidioc-enum-frameintervals.xml @@ -217,7 +217,8 @@ enumerated. __u32 reserved[2] - Reserved space for future use. + Reserved space for future use. Must be zeroed by drivers and + applications. diff --git a/Documentation/DocBook/media/v4l/vidioc-enum-framesizes.xml b/Documentation/DocBook/media/v4l/vidioc-enum-framesizes.xml index a78454b5abcd..9ed68ac8f474 100644 --- a/Documentation/DocBook/media/v4l/vidioc-enum-framesizes.xml +++ b/Documentation/DocBook/media/v4l/vidioc-enum-framesizes.xml @@ -223,7 +223,8 @@ application should zero out all members except for the __u32 reserved[2] - Reserved space for future use. + Reserved space for future use. Must be zeroed by drivers and + applications. diff --git a/Documentation/DocBook/media/v4l/vidioc-expbuf.xml b/Documentation/DocBook/media/v4l/vidioc-expbuf.xml index 4165e7bfa4ff..a78c9207422f 100644 --- a/Documentation/DocBook/media/v4l/vidioc-expbuf.xml +++ b/Documentation/DocBook/media/v4l/vidioc-expbuf.xml @@ -184,7 +184,8 @@ of open() for more details. __u32 reserved[11] - Reserved field for future use. Must be set to zero. + Reserved field for future use. Drivers and applications must +set the array to zero. diff --git a/Documentation/DocBook/media/v4l/vidioc-g-selection.xml b/Documentation/DocBook/media/v4l/vidioc-g-selection.xml index 0bb5c060db27..7865351688da 100644 --- a/Documentation/DocBook/media/v4l/vidioc-g-selection.xml +++ b/Documentation/DocBook/media/v4l/vidioc-g-selection.xml @@ -199,7 +199,7 @@ exist no rectangle that satisfies the constraints. __u32 reserved[9] - Reserved fields for future use. + Reserved fields for future use. Drivers and applications must zero this array. diff --git a/Documentation/DocBook/media/v4l/vidioc-querybuf.xml b/Documentation/DocBook/media/v4l/vidioc-querybuf.xml index a597155c052d..50bfcb5e8508 100644 --- a/Documentation/DocBook/media/v4l/vidioc-querybuf.xml +++ b/Documentation/DocBook/media/v4l/vidioc-querybuf.xml @@ -60,7 +60,8 @@ buffer at any time after buffers have been allocated with the field. Valid index numbers range from zero to the number of buffers allocated with &VIDIOC-REQBUFS; (&v4l2-requestbuffers; count) minus one. -The reserved field should to set to 0. +The reserved and reserved2 +fields must be set to 0. When using the multi-planar API, the m.planes field must contain a userspace pointer to an array of &v4l2-plane; and the length field has diff --git a/Documentation/DocBook/media/v4l/vidioc-reqbufs.xml b/Documentation/DocBook/media/v4l/vidioc-reqbufs.xml index 78a06a9a5ece..0f193fda0470 100644 --- a/Documentation/DocBook/media/v4l/vidioc-reqbufs.xml +++ b/Documentation/DocBook/media/v4l/vidioc-reqbufs.xml @@ -112,8 +112,8 @@ as the &v4l2-format; type field. See __u32 reserved[2] - A place holder for future extensions. This array should -be zeroed by applications. + A place holder for future extensions. Drivers and applications +must set the array to zero. -- cgit v1.2.3 From 4eb2088c07cdc90d43a5a02d13c2f8aa20c470a9 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Thu, 21 May 2015 12:13:05 +0530 Subject: powerpc/dscr: Add documentation for DSCR support This patch adds a new documentation file explaining the DSCR support on powerpc platforms. This explains DSCR related data structure, code paths and also available user interfaces. Any further functional changes to the DSCR support in the kernel should definitely update the documentation here. Signed-off-by: Anshuman Khandual Signed-off-by: Michael Ellerman --- Documentation/powerpc/00-INDEX | 2 + Documentation/powerpc/dscr.txt | 83 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 Documentation/powerpc/dscr.txt (limited to 'Documentation') diff --git a/Documentation/powerpc/00-INDEX b/Documentation/powerpc/00-INDEX index 6fd0e8bb8140..9dc845cf7d88 100644 --- a/Documentation/powerpc/00-INDEX +++ b/Documentation/powerpc/00-INDEX @@ -30,3 +30,5 @@ ptrace.txt - Information on the ptrace interfaces for hardware debug registers. transactional_memory.txt - Overview of the Power8 transactional memory support. +dscr.txt + - Overview DSCR (Data Stream Control Register) support. diff --git a/Documentation/powerpc/dscr.txt b/Documentation/powerpc/dscr.txt new file mode 100644 index 000000000000..1ff4400c57b3 --- /dev/null +++ b/Documentation/powerpc/dscr.txt @@ -0,0 +1,83 @@ + DSCR (Data Stream Control Register) + ================================================ + +DSCR register in powerpc allows user to have some control of prefetch of data +stream in the processor. Please refer to the ISA documents or related manual +for more detailed information regarding how to use this DSCR to attain this +control of the pefetches . This document here provides an overview of kernel +support for DSCR, related kernel objects, it's functionalities and exported +user interface. + +(A) Data Structures: + + (1) thread_struct: + dscr /* Thread DSCR value */ + dscr_inherit /* Thread has changed default DSCR */ + + (2) PACA: + dscr_default /* per-CPU DSCR default value */ + + (3) sysfs.c: + dscr_default /* System DSCR default value */ + +(B) Scheduler Changes: + + Scheduler will write the per-CPU DSCR default which is stored in the + CPU's PACA value into the register if the thread has dscr_inherit value + cleared which means that it has not changed the default DSCR till now. + If the dscr_inherit value is set which means that it has changed the + default DSCR value, scheduler will write the changed value which will + now be contained in thread struct's dscr into the register instead of + the per-CPU default PACA based DSCR value. + + NOTE: Please note here that the system wide global DSCR value never + gets used directly in the scheduler process context switch at all. + +(C) SYSFS Interface: + + Global DSCR default: /sys/devices/system/cpu/dscr_default + CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr + + Changing the global DSCR default in the sysfs will change all the CPU + specific DSCR defaults immediately in their PACA structures. Again if + the current process has the dscr_inherit clear, it also writes the new + value into every CPU's DSCR register right away and updates the current + thread's DSCR value as well. + + Changing the CPU specif DSCR default value in the sysfs does exactly + the same thing as above but unlike the global one above, it just changes + stuff for that particular CPU instead for all the CPUs on the system. + +(D) User Space Instructions: + + The DSCR register can be accessed in the user space using any of these + two SPR numbers available for that purpose. + + (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only) + (2) Privileged state SPR: 0x11 (Privileged) + + Accessing DSCR through privileged SPR number (0x11) from user space + works, as it is emulated following an illegal instruction exception + inside the kernel. Both mfspr and mtspr instructions are emulated. + + Accessing DSCR through user level SPR (0x03) from user space will first + create a facility unavailable exception. Inside this exception handler + all mfspr isntruction based read attempts will get emulated and returned + where as the first mtspr instruction based write attempts will enable + the DSCR facility for the next time around (both for read and write) by + setting DSCR facility in the FSCR register. + +(E) Specifics about 'dscr_inherit': + + The thread struct element 'dscr_inherit' represents whether the thread + in question has attempted and changed the DSCR itself using any of the + following methods. This element signifies whether the thread wants to + use the CPU default DSCR value or its own changed DSCR value in the + kernel. + + (1) mtspr instruction (SPR number 0x03) + (2) mtspr instruction (SPR number 0x11) + (3) ptrace interface (Explicitly set user DSCR value) + + Any child of the process created after this event in the process inherits + this same behaviour as well. -- cgit v1.2.3 From d838270e2516db11084bed4e294017eb7b646a75 Mon Sep 17 00:00:00 2001 From: Toshi Kani Date: Thu, 4 Jun 2015 18:55:15 +0200 Subject: x86/mm, asm-generic: Add ioremap_wt() for creating Write-Through mappings Add ioremap_wt() for creating Write-Through mappings on x86. It follows the same model as ioremap_wc() for multi-arch support. Define ARCH_HAS_IOREMAP_WT in the x86 version of io.h to indicate that ioremap_wt() is implemented on x86. Also update the PAT documentation file to cover ioremap_wt(). Signed-off-by: Toshi Kani Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Elliott@hp.com Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Luis R. Rodriguez Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: arnd@arndb.de Cc: hch@lst.de Cc: hmh@hmh.eng.br Cc: jgross@suse.com Cc: konrad.wilk@oracle.com Cc: linux-mm Cc: linux-nvdimm@lists.01.org Cc: stefan.bader@canonical.com Cc: yigal@plexistor.com Link: http://lkml.kernel.org/r/1433436928-31903-8-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/pat.txt | 4 +++- arch/x86/include/asm/io.h | 2 ++ arch/x86/mm/ioremap.c | 21 +++++++++++++++++++++ include/asm-generic/io.h | 9 +++++++++ include/asm-generic/iomap.h | 4 ++++ 5 files changed, 39 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt index 521bd8adc3b8..db0de6cfc351 100644 --- a/Documentation/x86/pat.txt +++ b/Documentation/x86/pat.txt @@ -12,7 +12,7 @@ virtual addresses. PAT allows for different types of memory attributes. The most commonly used ones that will be supported at this time are Write-back, Uncached, -Write-combined and Uncached Minus. +Write-combined, Write-through and Uncached Minus. PAT APIs @@ -40,6 +40,8 @@ ioremap_nocache | -- | UC- | UC- | | | | | ioremap_wc | -- | -- | WC | | | | | +ioremap_wt | -- | -- | WT | + | | | | set_memory_uc | UC- | -- | -- | set_memory_wb | | | | | | | | diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index a94463063b46..83ec9b1d77cc 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -35,6 +35,7 @@ */ #define ARCH_HAS_IOREMAP_WC +#define ARCH_HAS_IOREMAP_WT #include #include @@ -320,6 +321,7 @@ extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, enum page_cache_mode pcm); extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); +extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); extern bool is_early_ioremap_ptep(pte_t *ptep); diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index cc0f17c5ad9f..07cd46a8f30a 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -172,6 +172,10 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr, prot = __pgprot(pgprot_val(prot) | cachemode2protval(_PAGE_CACHE_MODE_WC)); break; + case _PAGE_CACHE_MODE_WT: + prot = __pgprot(pgprot_val(prot) | + cachemode2protval(_PAGE_CACHE_MODE_WT)); + break; case _PAGE_CACHE_MODE_WB: break; } @@ -297,6 +301,23 @@ void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size) } EXPORT_SYMBOL(ioremap_wc); +/** + * ioremap_wt - map memory into CPU space write through + * @phys_addr: bus address of the memory + * @size: size of the resource to map + * + * This version of ioremap ensures that the memory is marked write through. + * Write through stores data into memory while keeping the cache up-to-date. + * + * Must be freed with iounmap. + */ +void __iomem *ioremap_wt(resource_size_t phys_addr, unsigned long size) +{ + return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WT, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_wt); + void __iomem *ioremap_cache(resource_size_t phys_addr, unsigned long size) { return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WB, diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 90ccba7f9f9a..f56094cfdeff 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -785,8 +785,17 @@ static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size) } #endif +#ifndef ioremap_wt +#define ioremap_wt ioremap_wt +static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size) +{ + return ioremap_nocache(offset, size); +} +#endif + #ifndef iounmap #define iounmap iounmap + static inline void iounmap(void __iomem *addr) { } diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h index 1b41011643a5..d8f8622fa044 100644 --- a/include/asm-generic/iomap.h +++ b/include/asm-generic/iomap.h @@ -66,6 +66,10 @@ extern void ioport_unmap(void __iomem *); #define ioremap_wc ioremap_nocache #endif +#ifndef ARCH_HAS_IOREMAP_WT +#define ioremap_wt ioremap_nocache +#endif + #ifdef CONFIG_PCI /* Destroy a virtual mapping cookie for a PCI BAR (memory or IO) */ struct pci_dev; -- cgit v1.2.3 From 623dffb2a2e059e1ace45b59b3ff21c66c419614 Mon Sep 17 00:00:00 2001 From: Toshi Kani Date: Thu, 4 Jun 2015 18:55:20 +0200 Subject: x86/mm/pat: Add set_memory_wt() for Write-Through type Now that reserve_ram_pages_type() accepts the WT type, add set_memory_wt(), set_memory_array_wt() and set_pages_array_wt() in order to be able to set memory to Write-Through page cache mode. Also, extend ioremap_change_attr() to accept the WT type. Signed-off-by: Toshi Kani Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Elliott@hp.com Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Luis R. Rodriguez Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: arnd@arndb.de Cc: hch@lst.de Cc: hmh@hmh.eng.br Cc: jgross@suse.com Cc: konrad.wilk@oracle.com Cc: linux-mm Cc: linux-nvdimm@lists.01.org Cc: stefan.bader@canonical.com Cc: yigal@plexistor.com Link: http://lkml.kernel.org/r/1433436928-31903-13-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/pat.txt | 9 ++++-- arch/x86/include/asm/cacheflush.h | 6 +++- arch/x86/mm/ioremap.c | 3 ++ arch/x86/mm/pageattr.c | 62 +++++++++++++++++++++++++++++++-------- 4 files changed, 63 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/x86/pat.txt b/Documentation/x86/pat.txt index db0de6cfc351..54944c71b819 100644 --- a/Documentation/x86/pat.txt +++ b/Documentation/x86/pat.txt @@ -48,6 +48,9 @@ set_memory_uc | UC- | -- | -- | set_memory_wc | WC | -- | -- | set_memory_wb | | | | | | | | +set_memory_wt | WT | -- | -- | + set_memory_wb | | | | + | | | | pci sysfs resource | -- | -- | UC- | | | | | pci sysfs resource_wc | -- | -- | WC | @@ -150,8 +153,8 @@ can be more restrictive, in case of any existing aliasing for that address. For example: If there is an existing uncached mapping, a new ioremap_wc can return uncached mapping in place of write-combine requested. -set_memory_[uc|wc] and set_memory_wb should be used in pairs, where driver will -first make a region uc or wc and switch it back to wb after use. +set_memory_[uc|wc|wt] and set_memory_wb should be used in pairs, where driver +will first make a region uc, wc or wt and switch it back to wb after use. Over time writes to /proc/mtrr will be deprecated in favor of using PAT based interfaces. Users writing to /proc/mtrr are suggested to use above interfaces. @@ -159,7 +162,7 @@ interfaces. Users writing to /proc/mtrr are suggested to use above interfaces. Drivers should use ioremap_[uc|wc] to access PCI BARs with [uc|wc] access types. -Drivers should use set_memory_[uc|wc] to set access type for RAM ranges. +Drivers should use set_memory_[uc|wc|wt] to set access type for RAM ranges. PAT debugging diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h index 47c8e32f621a..b6f7457d12e4 100644 --- a/arch/x86/include/asm/cacheflush.h +++ b/arch/x86/include/asm/cacheflush.h @@ -8,7 +8,7 @@ /* * The set_memory_* API can be used to change various attributes of a virtual * address range. The attributes include: - * Cachability : UnCached, WriteCombining, WriteBack + * Cachability : UnCached, WriteCombining, WriteThrough, WriteBack * Executability : eXeutable, NoteXecutable * Read/Write : ReadOnly, ReadWrite * Presence : NotPresent @@ -35,9 +35,11 @@ int _set_memory_uc(unsigned long addr, int numpages); int _set_memory_wc(unsigned long addr, int numpages); +int _set_memory_wt(unsigned long addr, int numpages); int _set_memory_wb(unsigned long addr, int numpages); int set_memory_uc(unsigned long addr, int numpages); int set_memory_wc(unsigned long addr, int numpages); +int set_memory_wt(unsigned long addr, int numpages); int set_memory_wb(unsigned long addr, int numpages); int set_memory_x(unsigned long addr, int numpages); int set_memory_nx(unsigned long addr, int numpages); @@ -48,10 +50,12 @@ int set_memory_4k(unsigned long addr, int numpages); int set_memory_array_uc(unsigned long *addr, int addrinarray); int set_memory_array_wc(unsigned long *addr, int addrinarray); +int set_memory_array_wt(unsigned long *addr, int addrinarray); int set_memory_array_wb(unsigned long *addr, int addrinarray); int set_pages_array_uc(struct page **pages, int addrinarray); int set_pages_array_wc(struct page **pages, int addrinarray); +int set_pages_array_wt(struct page **pages, int addrinarray); int set_pages_array_wb(struct page **pages, int addrinarray); /* diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 07cd46a8f30a..8405c0c6a535 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -42,6 +42,9 @@ int ioremap_change_attr(unsigned long vaddr, unsigned long size, case _PAGE_CACHE_MODE_WC: err = _set_memory_wc(vaddr, nrpages); break; + case _PAGE_CACHE_MODE_WT: + err = _set_memory_wt(vaddr, nrpages); + break; case _PAGE_CACHE_MODE_WB: err = _set_memory_wb(vaddr, nrpages); break; diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 31b4f3fd1207..727158cb3b3c 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -1503,12 +1503,10 @@ EXPORT_SYMBOL(set_memory_uc); static int _set_memory_array(unsigned long *addr, int addrinarray, enum page_cache_mode new_type) { + enum page_cache_mode set_type; int i, j; int ret; - /* - * for now UC MINUS. see comments in ioremap_nocache() - */ for (i = 0; i < addrinarray; i++) { ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, new_type, NULL); @@ -1516,9 +1514,12 @@ static int _set_memory_array(unsigned long *addr, int addrinarray, goto out_free; } + /* If WC, set to UC- first and then WC */ + set_type = (new_type == _PAGE_CACHE_MODE_WC) ? + _PAGE_CACHE_MODE_UC_MINUS : new_type; + ret = change_page_attr_set(addr, addrinarray, - cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), - 1); + cachemode2pgprot(set_type), 1); if (!ret && new_type == _PAGE_CACHE_MODE_WC) ret = change_page_attr_set_clr(addr, addrinarray, @@ -1550,6 +1551,12 @@ int set_memory_array_wc(unsigned long *addr, int addrinarray) } EXPORT_SYMBOL(set_memory_array_wc); +int set_memory_array_wt(unsigned long *addr, int addrinarray) +{ + return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); +} +EXPORT_SYMBOL_GPL(set_memory_array_wt); + int _set_memory_wc(unsigned long addr, int numpages) { int ret; @@ -1575,21 +1582,39 @@ int set_memory_wc(unsigned long addr, int numpages) ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, _PAGE_CACHE_MODE_WC, NULL); if (ret) - goto out_err; + return ret; ret = _set_memory_wc(addr, numpages); if (ret) - goto out_free; + free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); - return 0; - -out_free: - free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); -out_err: return ret; } EXPORT_SYMBOL(set_memory_wc); +int _set_memory_wt(unsigned long addr, int numpages) +{ + return change_page_attr_set(&addr, numpages, + cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); +} + +int set_memory_wt(unsigned long addr, int numpages) +{ + int ret; + + ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, + _PAGE_CACHE_MODE_WT, NULL); + if (ret) + return ret; + + ret = _set_memory_wt(addr, numpages); + if (ret) + free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); + + return ret; +} +EXPORT_SYMBOL_GPL(set_memory_wt); + int _set_memory_wb(unsigned long addr, int numpages) { /* WB cache mode is hard wired to all cache attribute bits being 0 */ @@ -1680,6 +1705,7 @@ static int _set_pages_array(struct page **pages, int addrinarray, { unsigned long start; unsigned long end; + enum page_cache_mode set_type; int i; int free_idx; int ret; @@ -1693,8 +1719,12 @@ static int _set_pages_array(struct page **pages, int addrinarray, goto err_out; } + /* If WC, set to UC- first and then WC */ + set_type = (new_type == _PAGE_CACHE_MODE_WC) ? + _PAGE_CACHE_MODE_UC_MINUS : new_type; + ret = cpa_set_pages_array(pages, addrinarray, - cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS)); + cachemode2pgprot(set_type)); if (!ret && new_type == _PAGE_CACHE_MODE_WC) ret = change_page_attr_set_clr(NULL, addrinarray, cachemode2pgprot( @@ -1728,6 +1758,12 @@ int set_pages_array_wc(struct page **pages, int addrinarray) } EXPORT_SYMBOL(set_pages_array_wc); +int set_pages_array_wt(struct page **pages, int addrinarray) +{ + return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); +} +EXPORT_SYMBOL_GPL(set_pages_array_wt); + int set_pages_wb(struct page *page, int numpages) { unsigned long addr = (unsigned long)page_address(page); -- cgit v1.2.3 From 88d538672ea26223bca08225bc49f4e65e71683d Mon Sep 17 00:00:00 2001 From: Ashok Raj Date: Thu, 4 Jun 2015 18:55:23 +0200 Subject: x86/mce: Add infrastructure to support Local MCE Initialize and prepare for handling LMCEs. Add a boot-time option to disable LMCEs. Signed-off-by: Ashok Raj [ Simplify stuff, align statements for better readability, reflow comments; kill unused lmce_clear(); save us an MSR write if LMCE is already enabled. ] Signed-off-by: Borislav Petkov Cc: Andrew Morton Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/1433436928-31903-16-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- Documentation/x86/x86_64/boot-options.txt | 3 +++ arch/x86/include/asm/mce.h | 5 ++++ arch/x86/kernel/cpu/mcheck/mce.c | 3 +++ arch/x86/kernel/cpu/mcheck/mce_intel.c | 43 +++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+) (limited to 'Documentation') diff --git a/Documentation/x86/x86_64/boot-options.txt b/Documentation/x86/x86_64/boot-options.txt index 5223479291a2..68ed3114c363 100644 --- a/Documentation/x86/x86_64/boot-options.txt +++ b/Documentation/x86/x86_64/boot-options.txt @@ -31,6 +31,9 @@ Machine check (e.g. BIOS or hardware monitoring applications), conflicting with OS's error handling, and you cannot deactivate the agent, then this option will be a help. + mce=no_lmce + Do not opt-in to Local MCE delivery. Use legacy method + to broadcast MCEs. mce=bootlog Enable logging of machine checks left over from booting. Disabled by default on AMD because some BIOS leave bogus ones. diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index ae2bfb895994..982dfc3679ad 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -109,6 +109,7 @@ struct mce_log { struct mca_config { bool dont_log_ce; bool cmci_disabled; + bool lmce_disabled; bool ignore_ce; bool disabled; bool ser; @@ -184,12 +185,16 @@ void cmci_clear(void); void cmci_reenable(void); void cmci_rediscover(void); void cmci_recheck(void); +void lmce_clear(void); +void lmce_enable(void); #else static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } static inline void cmci_clear(void) {} static inline void cmci_reenable(void) {} static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} +static inline void lmce_clear(void) {} +static inline void lmce_enable(void) {} #endif #ifdef CONFIG_X86_MCE_AMD diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 0cbcd3183acf..c8c6577b4ada 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1982,6 +1982,7 @@ void mce_disable_bank(int bank) /* * mce=off Disables machine check * mce=no_cmci Disables CMCI + * mce=no_lmce Disables LMCE * mce=dont_log_ce Clears corrected events silently, no log created for CEs. * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) @@ -2005,6 +2006,8 @@ static int __init mcheck_enable(char *str) cfg->disabled = true; else if (!strcmp(str, "no_cmci")) cfg->cmci_disabled = true; + else if (!strcmp(str, "no_lmce")) + cfg->lmce_disabled = true; else if (!strcmp(str, "dont_log_ce")) cfg->dont_log_ce = true; else if (!strcmp(str, "ignore_ce")) diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index b4a41cf030ed..2d872deb2c50 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -91,6 +91,36 @@ static int cmci_supported(int *banks) return !!(cap & MCG_CMCI_P); } +static bool lmce_supported(void) +{ + u64 tmp; + + if (mca_cfg.lmce_disabled) + return false; + + rdmsrl(MSR_IA32_MCG_CAP, tmp); + + /* + * LMCE depends on recovery support in the processor. Hence both + * MCG_SER_P and MCG_LMCE_P should be present in MCG_CAP. + */ + if ((tmp & (MCG_SER_P | MCG_LMCE_P)) != + (MCG_SER_P | MCG_LMCE_P)) + return false; + + /* + * BIOS should indicate support for LMCE by setting bit 20 in + * IA32_FEATURE_CONTROL without which touching MCG_EXT_CTL will + * generate a #GP fault. + */ + rdmsrl(MSR_IA32_FEATURE_CONTROL, tmp); + if ((tmp & (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE)) == + (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE)) + return true; + + return false; +} + bool mce_intel_cmci_poll(void) { if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE) @@ -405,6 +435,19 @@ static void intel_init_cmci(void) cmci_recheck(); } +void intel_init_lmce(void) +{ + u64 val; + + if (!lmce_supported()) + return; + + rdmsrl(MSR_IA32_MCG_EXT_CTL, val); + + if (!(val & MCG_EXT_CTL_LMCE_EN)) + wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); +} + void mce_intel_feature_init(struct cpuinfo_x86 *c) { intel_init_thermal(c); -- cgit v1.2.3 From bf04c1a367e3d52b2e071cc7c7047c27dc1c3c5f Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 27 May 2015 14:47:51 +0200 Subject: iio: adc: vf610: implement configurable conversion modes Support configurable conversion mode through sysfs. So far, the mode used was low-power, which is enabled by default now. Beside that, the modes normal and high-speed are selectable as well. Use the new device tree property which specifies the maximum ADC conversion clock frequencies. Depending on the mode used, the available resulting conversion frequency are calculated dynamically. Acked-by: Fugang Duan Signed-off-by: Stefan Agner Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio-vf610 | 7 + .../devicetree/bindings/iio/adc/vf610-adc.txt | 9 ++ drivers/iio/adc/vf610_adc.c | 146 +++++++++++++++------ 3 files changed, 120 insertions(+), 42 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-vf610 (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio-vf610 b/Documentation/ABI/testing/sysfs-bus-iio-vf610 new file mode 100644 index 000000000000..ecbc1f4af921 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-vf610 @@ -0,0 +1,7 @@ +What: /sys/bus/iio/devices/iio:deviceX/conversion_mode +KernelVersion: 4.2 +Contact: linux-iio@vger.kernel.org +Description: + Specifies the hardware conversion mode used. The three + available modes are "normal", "high-speed" and "low-power", + where the last is the default mode. diff --git a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt index 1a4a43d5c9ea..3eb40e20c143 100644 --- a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt @@ -11,6 +11,13 @@ Required properties: - clock-names: Must contain "adc", matching entry in the clocks property. - vref-supply: The regulator supply ADC reference voltage. +Recommended properties: +- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating + requirements. Three values are required, depending on conversion mode: + - Frequency in normal mode (ADLPC=0, ADHSC=0) + - Frequency in high-speed mode (ADLPC=0, ADHSC=1) + - Frequency in low-power mode (ADLPC=1, ADHSC=0) + Example: adc0: adc@4003b000 { compatible = "fsl,vf610-adc"; @@ -18,5 +25,7 @@ adc0: adc@4003b000 { interrupts = <0 53 0x04>; clocks = <&clks VF610_CLK_ADC0>; clock-names = "adc"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; vref-supply = <®_vcc_3v3_mcu>; }; diff --git a/drivers/iio/adc/vf610_adc.c b/drivers/iio/adc/vf610_adc.c index 56292ae4538d..480f335a0f9f 100644 --- a/drivers/iio/adc/vf610_adc.c +++ b/drivers/iio/adc/vf610_adc.c @@ -118,15 +118,21 @@ enum average_sel { VF610_ADC_SAMPLE_32, }; +enum conversion_mode_sel { + VF610_ADC_CONV_NORMAL, + VF610_ADC_CONV_HIGH_SPEED, + VF610_ADC_CONV_LOW_POWER, +}; + struct vf610_adc_feature { enum clk_sel clk_sel; enum vol_ref vol_ref; + enum conversion_mode_sel conv_mode; int clk_div; int sample_rate; int res_mode; - bool lpm; bool calibration; bool ovwren; }; @@ -139,6 +145,8 @@ struct vf610_adc { u32 vref_uv; u32 value; struct regulator *vref; + + u32 max_adck_rate[3]; struct vf610_adc_feature adc_feature; u32 sample_freq_avail[5]; @@ -148,46 +156,22 @@ struct vf610_adc { static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 }; -#define VF610_ADC_CHAN(_idx, _chan_type) { \ - .type = (_chan_type), \ - .indexed = 1, \ - .channel = (_idx), \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_SAMP_FREQ), \ -} - -#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ - .type = (_chan_type), \ - .channel = (_idx), \ - .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ -} - -static const struct iio_chan_spec vf610_adc_iio_channels[] = { - VF610_ADC_CHAN(0, IIO_VOLTAGE), - VF610_ADC_CHAN(1, IIO_VOLTAGE), - VF610_ADC_CHAN(2, IIO_VOLTAGE), - VF610_ADC_CHAN(3, IIO_VOLTAGE), - VF610_ADC_CHAN(4, IIO_VOLTAGE), - VF610_ADC_CHAN(5, IIO_VOLTAGE), - VF610_ADC_CHAN(6, IIO_VOLTAGE), - VF610_ADC_CHAN(7, IIO_VOLTAGE), - VF610_ADC_CHAN(8, IIO_VOLTAGE), - VF610_ADC_CHAN(9, IIO_VOLTAGE), - VF610_ADC_CHAN(10, IIO_VOLTAGE), - VF610_ADC_CHAN(11, IIO_VOLTAGE), - VF610_ADC_CHAN(12, IIO_VOLTAGE), - VF610_ADC_CHAN(13, IIO_VOLTAGE), - VF610_ADC_CHAN(14, IIO_VOLTAGE), - VF610_ADC_CHAN(15, IIO_VOLTAGE), - VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), - /* sentinel */ -}; - static inline void vf610_adc_calculate_rates(struct vf610_adc *info) { + struct vf610_adc_feature *adc_feature = &info->adc_feature; unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); - int i; + int divisor, i; + + adck_rate = info->max_adck_rate[adc_feature->conv_mode]; + + if (adck_rate) { + /* calculate clk divider which is within specification */ + divisor = ipg_rate / adck_rate; + adc_feature->clk_div = 1 << fls(divisor + 1); + } else { + /* fall-back value using a safe divisor */ + adc_feature->clk_div = 8; + } /* * Calculate ADC sample frequencies @@ -219,10 +203,8 @@ static inline void vf610_adc_cfg_init(struct vf610_adc *info) adc_feature->res_mode = 12; adc_feature->sample_rate = 1; - adc_feature->lpm = true; - /* Use a save ADCK which is below 20MHz on all devices */ - adc_feature->clk_div = 8; + adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER; vf610_adc_calculate_rates(info); } @@ -304,10 +286,12 @@ static void vf610_adc_cfg_set(struct vf610_adc *info) cfg_data = readl(info->regs + VF610_REG_ADC_CFG); cfg_data &= ~VF610_ADC_ADLPC_EN; - if (adc_feature->lpm) + if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER) cfg_data |= VF610_ADC_ADLPC_EN; cfg_data &= ~VF610_ADC_ADHSC_EN; + if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED) + cfg_data |= VF610_ADC_ADHSC_EN; writel(cfg_data, info->regs + VF610_REG_ADC_CFG); } @@ -409,6 +393,81 @@ static void vf610_adc_hw_init(struct vf610_adc *info) vf610_adc_cfg_set(info); } +static int vf610_set_conversion_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct vf610_adc *info = iio_priv(indio_dev); + + mutex_lock(&indio_dev->mlock); + info->adc_feature.conv_mode = mode; + vf610_adc_calculate_rates(info); + vf610_adc_hw_init(info); + mutex_unlock(&indio_dev->mlock); + + return 0; +} + +static int vf610_get_conversion_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct vf610_adc *info = iio_priv(indio_dev); + + return info->adc_feature.conv_mode; +} + +static const char * const vf610_conv_modes[] = { "normal", "high-speed", + "low-power" }; + +static const struct iio_enum vf610_conversion_mode = { + .items = vf610_conv_modes, + .num_items = ARRAY_SIZE(vf610_conv_modes), + .get = vf610_get_conversion_mode, + .set = vf610_set_conversion_mode, +}; + +static const struct iio_chan_spec_ext_info vf610_ext_info[] = { + IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode), + {}, +}; + +#define VF610_ADC_CHAN(_idx, _chan_type) { \ + .type = (_chan_type), \ + .indexed = 1, \ + .channel = (_idx), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .ext_info = vf610_ext_info, \ +} + +#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ + .type = (_chan_type), \ + .channel = (_idx), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ +} + +static const struct iio_chan_spec vf610_adc_iio_channels[] = { + VF610_ADC_CHAN(0, IIO_VOLTAGE), + VF610_ADC_CHAN(1, IIO_VOLTAGE), + VF610_ADC_CHAN(2, IIO_VOLTAGE), + VF610_ADC_CHAN(3, IIO_VOLTAGE), + VF610_ADC_CHAN(4, IIO_VOLTAGE), + VF610_ADC_CHAN(5, IIO_VOLTAGE), + VF610_ADC_CHAN(6, IIO_VOLTAGE), + VF610_ADC_CHAN(7, IIO_VOLTAGE), + VF610_ADC_CHAN(8, IIO_VOLTAGE), + VF610_ADC_CHAN(9, IIO_VOLTAGE), + VF610_ADC_CHAN(10, IIO_VOLTAGE), + VF610_ADC_CHAN(11, IIO_VOLTAGE), + VF610_ADC_CHAN(12, IIO_VOLTAGE), + VF610_ADC_CHAN(13, IIO_VOLTAGE), + VF610_ADC_CHAN(14, IIO_VOLTAGE), + VF610_ADC_CHAN(15, IIO_VOLTAGE), + VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), + /* sentinel */ +}; + static int vf610_adc_read_data(struct vf610_adc *info) { int result; @@ -651,6 +710,9 @@ static int vf610_adc_probe(struct platform_device *pdev) info->vref_uv = regulator_get_voltage(info->vref); + of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency", + info->max_adck_rate, 3); + platform_set_drvdata(pdev, indio_dev); init_completion(&info->completion); -- cgit v1.2.3 From 0a45dcab22f6aa12cd0a022a69aca10103a43c0c Mon Sep 17 00:00:00 2001 From: Hao Liu Date: Tue, 26 May 2015 07:32:28 +0000 Subject: dmaengine: sirf: add CSRatlas7 SoC support add support for new CSR atlas7 SoC. atlas7 exists V1 and V2 IP. atlas7 DMAv1 is basically moved from marco, which has never been delivered to customers and renamed in this patch. atlas7 DMAv2 supports chain DMA by a chain table, this patch also adds chain DMA support for atlas7. atlas7 DMAv1 and DMAv2 co-exist in the same chip. there are some HW configuration differences(register offset etc.) with old prima2 chips, so we use compatible string to differentiate old prima2 and new atlas7, then results in different set in HW for them. Signed-off-by: Hao Liu Signed-off-by: Yanchang Li Signed-off-by: Barry Song Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/sirfsoc-dma.txt | 3 +- drivers/dma/sirf-dma.c | 423 ++++++++++++++++----- 2 files changed, 336 insertions(+), 90 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt b/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt index ecbc96ad36f8..ccd52d6a231a 100644 --- a/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt +++ b/Documentation/devicetree/bindings/dma/sirfsoc-dma.txt @@ -3,7 +3,8 @@ See dma.txt first Required properties: -- compatible: Should be "sirf,prima2-dmac" or "sirf,marco-dmac" +- compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or + "sirf,atlas7-dmac-v2" - reg: Should contain DMA registers location and length. - interrupts: Should contain one interrupt shared by all channel - #dma-cells: must be <1>. used to represent the number of integer diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c index a1afda43b8ef..8c5186cc9f63 100644 --- a/drivers/dma/sirf-dma.c +++ b/drivers/dma/sirf-dma.c @@ -23,8 +23,13 @@ #include "dmaengine.h" +#define SIRFSOC_DMA_VER_A7V1 1 +#define SIRFSOC_DMA_VER_A7V2 2 +#define SIRFSOC_DMA_VER_A6 4 + #define SIRFSOC_DMA_DESCRIPTORS 16 #define SIRFSOC_DMA_CHANNELS 16 +#define SIRFSOC_DMA_TABLE_NUM 256 #define SIRFSOC_DMA_CH_ADDR 0x00 #define SIRFSOC_DMA_CH_XLEN 0x04 @@ -35,15 +40,44 @@ #define SIRFSOC_DMA_CH_VALID 0x140 #define SIRFSOC_DMA_CH_INT 0x144 #define SIRFSOC_DMA_INT_EN 0x148 -#define SIRFSOC_DMA_INT_EN_CLR 0x14C +#define SIRFSOC_DMA_INT_EN_CLR 0x14C #define SIRFSOC_DMA_CH_LOOP_CTRL 0x150 -#define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x15C +#define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x154 +#define SIRFSOC_DMA_WIDTH_ATLAS7 0x10 +#define SIRFSOC_DMA_VALID_ATLAS7 0x14 +#define SIRFSOC_DMA_INT_ATLAS7 0x18 +#define SIRFSOC_DMA_INT_EN_ATLAS7 0x1c +#define SIRFSOC_DMA_LOOP_CTRL_ATLAS7 0x20 +#define SIRFSOC_DMA_CUR_DATA_ADDR 0x34 +#define SIRFSOC_DMA_MUL_ATLAS7 0x38 +#define SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7 0x158 +#define SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7 0x15C +#define SIRFSOC_DMA_IOBG_SCMD_EN 0x800 +#define SIRFSOC_DMA_EARLY_RESP_SET 0x818 +#define SIRFSOC_DMA_EARLY_RESP_CLR 0x81C #define SIRFSOC_DMA_MODE_CTRL_BIT 4 #define SIRFSOC_DMA_DIR_CTRL_BIT 5 +#define SIRFSOC_DMA_MODE_CTRL_BIT_ATLAS7 2 +#define SIRFSOC_DMA_CHAIN_CTRL_BIT_ATLAS7 3 +#define SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7 4 +#define SIRFSOC_DMA_TAB_NUM_ATLAS7 7 +#define SIRFSOC_DMA_CHAIN_INT_BIT_ATLAS7 5 +#define SIRFSOC_DMA_CHAIN_FLAG_SHIFT_ATLAS7 25 +#define SIRFSOC_DMA_CHAIN_ADDR_SHIFT 32 + +#define SIRFSOC_DMA_INT_FINI_INT_ATLAS7 BIT(0) +#define SIRFSOC_DMA_INT_CNT_INT_ATLAS7 BIT(1) +#define SIRFSOC_DMA_INT_PAU_INT_ATLAS7 BIT(2) +#define SIRFSOC_DMA_INT_LOOP_INT_ATLAS7 BIT(3) +#define SIRFSOC_DMA_INT_INV_INT_ATLAS7 BIT(4) +#define SIRFSOC_DMA_INT_END_INT_ATLAS7 BIT(5) +#define SIRFSOC_DMA_INT_ALL_ATLAS7 0x3F /* xlen and dma_width register is in 4 bytes boundary */ #define SIRFSOC_DMA_WORD_LEN 4 +#define SIRFSOC_DMA_XLEN_MAX_V1 0x800 +#define SIRFSOC_DMA_XLEN_MAX_V2 0x1000 struct sirfsoc_dma_desc { struct dma_async_tx_descriptor desc; @@ -56,7 +90,9 @@ struct sirfsoc_dma_desc { int width; /* DMA width */ int dir; bool cyclic; /* is loop DMA? */ + bool chain; /* is chain DMA? */ u32 addr; /* DMA buffer address */ + u64 chain_table[SIRFSOC_DMA_TABLE_NUM]; /* chain tbl */ }; struct sirfsoc_dma_chan { @@ -87,10 +123,25 @@ struct sirfsoc_dma { void __iomem *base; int irq; struct clk *clk; - bool is_marco; + int type; + void (*exec_desc)(struct sirfsoc_dma_desc *sdesc, + int cid, int burst_mode, void __iomem *base); struct sirfsoc_dma_regs regs_save; }; +struct sirfsoc_dmadata { + void (*exec)(struct sirfsoc_dma_desc *sdesc, + int cid, int burst_mode, void __iomem *base); + int type; +}; + +enum sirfsoc_dma_chain_flag { + SIRFSOC_DMA_CHAIN_NORMAL = 0x01, + SIRFSOC_DMA_CHAIN_PAUSE = 0x02, + SIRFSOC_DMA_CHAIN_LOOP = 0x03, + SIRFSOC_DMA_CHAIN_END = 0x04 +}; + #define DRV_NAME "sirfsoc_dma" static int sirfsoc_dma_runtime_suspend(struct device *dev); @@ -109,48 +160,105 @@ static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c) return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]); } +static void sirfsoc_dma_execute_hw_a7v2(struct sirfsoc_dma_desc *sdesc, + int cid, int burst_mode, void __iomem *base) +{ + if (sdesc->chain) { + /* DMA v2 HW chain mode */ + writel_relaxed((sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7) | + (sdesc->chain << + SIRFSOC_DMA_CHAIN_CTRL_BIT_ATLAS7) | + (0x8 << SIRFSOC_DMA_TAB_NUM_ATLAS7) | 0x3, + base + SIRFSOC_DMA_CH_CTRL); + } else { + /* DMA v2 legacy mode */ + writel_relaxed(sdesc->xlen, base + SIRFSOC_DMA_CH_XLEN); + writel_relaxed(sdesc->ylen, base + SIRFSOC_DMA_CH_YLEN); + writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_ATLAS7); + writel_relaxed((sdesc->width*((sdesc->ylen+1)>>1)), + base + SIRFSOC_DMA_MUL_ATLAS7); + writel_relaxed((sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7) | + (sdesc->chain << + SIRFSOC_DMA_CHAIN_CTRL_BIT_ATLAS7) | + 0x3, base + SIRFSOC_DMA_CH_CTRL); + } + writel_relaxed(sdesc->chain ? SIRFSOC_DMA_INT_END_INT_ATLAS7 : + (SIRFSOC_DMA_INT_FINI_INT_ATLAS7 | + SIRFSOC_DMA_INT_LOOP_INT_ATLAS7), + base + SIRFSOC_DMA_INT_EN_ATLAS7); + writel(sdesc->addr, base + SIRFSOC_DMA_CH_ADDR); + if (sdesc->cyclic) + writel(0x10001, base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); +} + +static void sirfsoc_dma_execute_hw_a7v1(struct sirfsoc_dma_desc *sdesc, + int cid, int burst_mode, void __iomem *base) +{ + writel_relaxed(1, base + SIRFSOC_DMA_IOBG_SCMD_EN); + writel_relaxed((1 << cid), base + SIRFSOC_DMA_EARLY_RESP_SET); + writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4); + writel_relaxed(cid | (burst_mode << SIRFSOC_DMA_MODE_CTRL_BIT) | + (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT), + base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); + writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN); + writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN); + writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) | + (1 << cid), base + SIRFSOC_DMA_INT_EN); + writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); + if (sdesc->cyclic) { + writel((1 << cid) | 1 << (cid + 16) | + readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7), + base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7); + } + +} + +static void sirfsoc_dma_execute_hw_a6(struct sirfsoc_dma_desc *sdesc, + int cid, int burst_mode, void __iomem *base) +{ + writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4); + writel_relaxed(cid | (burst_mode << SIRFSOC_DMA_MODE_CTRL_BIT) | + (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT), + base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); + writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN); + writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN); + writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) | + (1 << cid), base + SIRFSOC_DMA_INT_EN); + writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); + if (sdesc->cyclic) { + writel((1 << cid) | 1 << (cid + 16) | + readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL), + base + SIRFSOC_DMA_CH_LOOP_CTRL); + } + +} + /* Execute all queued DMA descriptors */ static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan) { struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan); int cid = schan->chan.chan_id; struct sirfsoc_dma_desc *sdesc = NULL; + void __iomem *base; /* * lock has been held by functions calling this, so we don't hold * lock again */ - + base = sdma->base; sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc, - node); + node); /* Move the first queued descriptor to active list */ list_move_tail(&sdesc->node, &schan->active); - /* Start the DMA transfer */ - writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 + - cid * 4); - writel_relaxed(cid | (schan->mode << SIRFSOC_DMA_MODE_CTRL_BIT) | - (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT), - sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); - writel_relaxed(sdesc->xlen, sdma->base + cid * 0x10 + - SIRFSOC_DMA_CH_XLEN); - writel_relaxed(sdesc->ylen, sdma->base + cid * 0x10 + - SIRFSOC_DMA_CH_YLEN); - writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) | - (1 << cid), sdma->base + SIRFSOC_DMA_INT_EN); + if (sdma->type == SIRFSOC_DMA_VER_A7V2) + cid = 0; - /* - * writel has an implict memory write barrier to make sure data is - * flushed into memory before starting DMA - */ - writel(sdesc->addr >> 2, sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); + /* Start the DMA transfer */ + sdma->exec_desc(sdesc, cid, schan->mode, base); - if (sdesc->cyclic) { - writel((1 << cid) | 1 << (cid + 16) | - readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); + if (sdesc->cyclic) schan->happened_cyclic = schan->completed_cyclic = 0; - } } /* Interrupt handler */ @@ -160,27 +268,65 @@ static irqreturn_t sirfsoc_dma_irq(int irq, void *data) struct sirfsoc_dma_chan *schan; struct sirfsoc_dma_desc *sdesc = NULL; u32 is; + bool chain; int ch; + void __iomem *reg; + + switch (sdma->type) { + case SIRFSOC_DMA_VER_A6: + case SIRFSOC_DMA_VER_A7V1: + is = readl(sdma->base + SIRFSOC_DMA_CH_INT); + reg = sdma->base + SIRFSOC_DMA_CH_INT; + while ((ch = fls(is) - 1) >= 0) { + is &= ~(1 << ch); + writel_relaxed(1 << ch, reg); + schan = &sdma->channels[ch]; + spin_lock(&schan->lock); + sdesc = list_first_entry(&schan->active, + struct sirfsoc_dma_desc, node); + if (!sdesc->cyclic) { + /* Execute queued descriptors */ + list_splice_tail_init(&schan->active, + &schan->completed); + dma_cookie_complete(&sdesc->desc); + if (!list_empty(&schan->queued)) + sirfsoc_dma_execute(schan); + } else + schan->happened_cyclic++; + spin_unlock(&schan->lock); + } + break; - is = readl(sdma->base + SIRFSOC_DMA_CH_INT); - while ((ch = fls(is) - 1) >= 0) { - is &= ~(1 << ch); - writel_relaxed(1 << ch, sdma->base + SIRFSOC_DMA_CH_INT); - schan = &sdma->channels[ch]; + case SIRFSOC_DMA_VER_A7V2: + is = readl(sdma->base + SIRFSOC_DMA_INT_ATLAS7); + reg = sdma->base + SIRFSOC_DMA_INT_ATLAS7; + writel_relaxed(SIRFSOC_DMA_INT_ALL_ATLAS7, reg); + schan = &sdma->channels[0]; spin_lock(&schan->lock); - - sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, - node); + sdesc = list_first_entry(&schan->active, + struct sirfsoc_dma_desc, node); if (!sdesc->cyclic) { - /* Execute queued descriptors */ - list_splice_tail_init(&schan->active, &schan->completed); - if (!list_empty(&schan->queued)) - sirfsoc_dma_execute(schan); - } else + chain = sdesc->chain; + if ((chain && (is & SIRFSOC_DMA_INT_END_INT_ATLAS7)) || + (!chain && + (is & SIRFSOC_DMA_INT_FINI_INT_ATLAS7))) { + /* Execute queued descriptors */ + list_splice_tail_init(&schan->active, + &schan->completed); + dma_cookie_complete(&sdesc->desc); + if (!list_empty(&schan->queued)) + sirfsoc_dma_execute(schan); + } + } else if (sdesc->cyclic && (is & + SIRFSOC_DMA_INT_LOOP_INT_ATLAS7)) schan->happened_cyclic++; spin_unlock(&schan->lock); + break; + + default: + break; } /* Schedule tasklet */ @@ -227,16 +373,15 @@ static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma) schan->chan.completed_cookie = last_cookie; spin_unlock_irqrestore(&schan->lock, flags); } else { - /* for cyclic channel, desc is always in active list */ - sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, - node); - - if (!sdesc || (sdesc && !sdesc->cyclic)) { - /* without active cyclic DMA */ + if (list_empty(&schan->active)) { spin_unlock_irqrestore(&schan->lock, flags); continue; } + /* for cyclic channel, desc is always in active list */ + sdesc = list_first_entry(&schan->active, + struct sirfsoc_dma_desc, node); + /* cyclic DMA */ happened_cyclic = schan->happened_cyclic; spin_unlock_irqrestore(&schan->lock, flags); @@ -307,20 +452,32 @@ static int sirfsoc_dma_terminate_all(struct dma_chan *chan) spin_lock_irqsave(&schan->lock, flags); - if (!sdma->is_marco) { - writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) & - ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN); - writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) - & ~((1 << cid) | 1 << (cid + 16)), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); - } else { + switch (sdma->type) { + case SIRFSOC_DMA_VER_A7V1: writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR); writel_relaxed((1 << cid) | 1 << (cid + 16), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR); + sdma->base + + SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7); + writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID); + break; + case SIRFSOC_DMA_VER_A7V2: + writel_relaxed(0, sdma->base + SIRFSOC_DMA_INT_EN_ATLAS7); + writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); + writel_relaxed(0, sdma->base + SIRFSOC_DMA_VALID_ATLAS7); + break; + case SIRFSOC_DMA_VER_A6: + writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) & + ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN); + writel_relaxed(readl_relaxed(sdma->base + + SIRFSOC_DMA_CH_LOOP_CTRL) & + ~((1 << cid) | 1 << (cid + 16)), + sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); + writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID); + break; + default: + break; } - writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID); - list_splice_tail_init(&schan->active, &schan->free); list_splice_tail_init(&schan->queued, &schan->free); @@ -338,13 +495,25 @@ static int sirfsoc_dma_pause_chan(struct dma_chan *chan) spin_lock_irqsave(&schan->lock, flags); - if (!sdma->is_marco) - writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) - & ~((1 << cid) | 1 << (cid + 16)), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); - else + switch (sdma->type) { + case SIRFSOC_DMA_VER_A7V1: writel_relaxed((1 << cid) | 1 << (cid + 16), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_CLR); + sdma->base + + SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7); + break; + case SIRFSOC_DMA_VER_A7V2: + writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); + break; + case SIRFSOC_DMA_VER_A6: + writel_relaxed(readl_relaxed(sdma->base + + SIRFSOC_DMA_CH_LOOP_CTRL) & + ~((1 << cid) | 1 << (cid + 16)), + sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); + break; + + default: + break; + } spin_unlock_irqrestore(&schan->lock, flags); @@ -359,14 +528,25 @@ static int sirfsoc_dma_resume_chan(struct dma_chan *chan) unsigned long flags; spin_lock_irqsave(&schan->lock, flags); - - if (!sdma->is_marco) - writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) - | ((1 << cid) | 1 << (cid + 16)), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); - else + switch (sdma->type) { + case SIRFSOC_DMA_VER_A7V1: writel_relaxed((1 << cid) | 1 << (cid + 16), - sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); + sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7); + break; + case SIRFSOC_DMA_VER_A7V2: + writel_relaxed(0x10001, + sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); + break; + case SIRFSOC_DMA_VER_A6: + writel_relaxed(readl_relaxed(sdma->base + + SIRFSOC_DMA_CH_LOOP_CTRL) | + ((1 << cid) | 1 << (cid + 16)), + sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); + break; + + default: + break; + } spin_unlock_irqrestore(&schan->lock, flags); @@ -473,14 +653,31 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, spin_lock_irqsave(&schan->lock, flags); - sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, - node); - dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) * - (sdesc->width * SIRFSOC_DMA_WORD_LEN); + if (list_empty(&schan->active)) { + ret = dma_cookie_status(chan, cookie, txstate); + dma_set_residue(txstate, 0); + spin_unlock_irqrestore(&schan->lock, flags); + return ret; + } + sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, node); + if (sdesc->cyclic) + dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) * + (sdesc->width * SIRFSOC_DMA_WORD_LEN); + else + dma_request_bytes = sdesc->xlen * SIRFSOC_DMA_WORD_LEN; ret = dma_cookie_status(chan, cookie, txstate); - dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) - << 2; + + if (sdma->type == SIRFSOC_DMA_VER_A7V2) + cid = 0; + + if (sdma->type == SIRFSOC_DMA_VER_A7V2) { + dma_pos = readl_relaxed(sdma->base + SIRFSOC_DMA_CUR_DATA_ADDR); + } else { + dma_pos = readl_relaxed( + sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) << 2; + } + residue = dma_request_bytes - (dma_pos - sdesc->addr); dma_set_residue(txstate, residue); @@ -647,6 +844,7 @@ static int sirfsoc_dma_probe(struct platform_device *op) struct dma_device *dma; struct sirfsoc_dma *sdma; struct sirfsoc_dma_chan *schan; + struct sirfsoc_dmadata *data; struct resource res; ulong regs_start, regs_size; u32 id; @@ -657,9 +855,11 @@ static int sirfsoc_dma_probe(struct platform_device *op) dev_err(dev, "Memory exhausted!\n"); return -ENOMEM; } - - if (of_device_is_compatible(dn, "sirf,marco-dmac")) - sdma->is_marco = true; + data = (struct sirfsoc_dmadata *) + (of_match_device(op->dev.driver->of_match_table, + &op->dev)->data); + sdma->exec_desc = data->exec; + sdma->type = data->type; if (of_property_read_u32(dn, "cell-index", &id)) { dev_err(dev, "Fail to get DMAC index\n"); @@ -816,6 +1016,8 @@ static int sirfsoc_dma_pm_suspend(struct device *dev) struct sirfsoc_dma_chan *schan; int ch; int ret; + int count; + u32 int_offset; /* * if we were runtime-suspended before, resume to enable clock @@ -827,11 +1029,19 @@ static int sirfsoc_dma_pm_suspend(struct device *dev) return ret; } + if (sdma->type == SIRFSOC_DMA_VER_A7V2) { + count = 1; + int_offset = SIRFSOC_DMA_INT_EN_ATLAS7; + } else { + count = SIRFSOC_DMA_CHANNELS; + int_offset = SIRFSOC_DMA_INT_EN; + } + /* * DMA controller will lose all registers while suspending * so we need to save registers for active channels */ - for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) { + for (ch = 0; ch < count; ch++) { schan = &sdma->channels[ch]; if (list_empty(&schan->active)) continue; @@ -841,7 +1051,7 @@ static int sirfsoc_dma_pm_suspend(struct device *dev) save->ctrl[ch] = readl_relaxed(sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL); } - save->interrupt_en = readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN); + save->interrupt_en = readl_relaxed(sdma->base + int_offset); /* Disable clock */ sirfsoc_dma_runtime_suspend(dev); @@ -857,14 +1067,27 @@ static int sirfsoc_dma_pm_resume(struct device *dev) struct sirfsoc_dma_chan *schan; int ch; int ret; + int count; + u32 int_offset; + u32 width_offset; /* Enable clock before accessing register */ ret = sirfsoc_dma_runtime_resume(dev); if (ret < 0) return ret; - writel_relaxed(save->interrupt_en, sdma->base + SIRFSOC_DMA_INT_EN); - for (ch = 0; ch < SIRFSOC_DMA_CHANNELS; ch++) { + if (sdma->type == SIRFSOC_DMA_VER_A7V2) { + count = 1; + int_offset = SIRFSOC_DMA_INT_EN_ATLAS7; + width_offset = SIRFSOC_DMA_WIDTH_ATLAS7; + } else { + count = SIRFSOC_DMA_CHANNELS; + int_offset = SIRFSOC_DMA_INT_EN; + width_offset = SIRFSOC_DMA_WIDTH_0; + } + + writel_relaxed(save->interrupt_en, sdma->base + int_offset); + for (ch = 0; ch < count; ch++) { schan = &sdma->channels[ch]; if (list_empty(&schan->active)) continue; @@ -872,15 +1095,21 @@ static int sirfsoc_dma_pm_resume(struct device *dev) struct sirfsoc_dma_desc, node); writel_relaxed(sdesc->width, - sdma->base + SIRFSOC_DMA_WIDTH_0 + ch * 4); + sdma->base + width_offset + ch * 4); writel_relaxed(sdesc->xlen, sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN); writel_relaxed(sdesc->ylen, sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN); writel_relaxed(save->ctrl[ch], sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL); - writel_relaxed(sdesc->addr >> 2, - sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR); + if (sdma->type == SIRFSOC_DMA_VER_A7V2) { + writel_relaxed(sdesc->addr, + sdma->base + SIRFSOC_DMA_CH_ADDR); + } else { + writel_relaxed(sdesc->addr >> 2, + sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR); + + } } /* if we were runtime-suspended before, suspend again */ @@ -896,9 +1125,25 @@ static const struct dev_pm_ops sirfsoc_dma_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_dma_pm_suspend, sirfsoc_dma_pm_resume) }; +struct sirfsoc_dmadata sirfsoc_dmadata_a6 = { + .exec = sirfsoc_dma_execute_hw_a6, + .type = SIRFSOC_DMA_VER_A6, +}; + +struct sirfsoc_dmadata sirfsoc_dmadata_a7v1 = { + .exec = sirfsoc_dma_execute_hw_a7v1, + .type = SIRFSOC_DMA_VER_A7V1, +}; + +struct sirfsoc_dmadata sirfsoc_dmadata_a7v2 = { + .exec = sirfsoc_dma_execute_hw_a7v2, + .type = SIRFSOC_DMA_VER_A7V2, +}; + static const struct of_device_id sirfsoc_dma_match[] = { - { .compatible = "sirf,prima2-dmac", }, - { .compatible = "sirf,marco-dmac", }, + { .compatible = "sirf,prima2-dmac", .data = &sirfsoc_dmadata_a6,}, + { .compatible = "sirf,atlas7-dmac", .data = &sirfsoc_dmadata_a7v1,}, + { .compatible = "sirf,atlas7-dmac-v2", .data = &sirfsoc_dmadata_a7v2,}, {}, }; @@ -925,7 +1170,7 @@ static void __exit sirfsoc_dma_exit(void) subsys_initcall(sirfsoc_dma_init); module_exit(sirfsoc_dma_exit); -MODULE_AUTHOR("Rongjun Ying , " - "Barry Song "); +MODULE_AUTHOR("Rongjun Ying "); +MODULE_AUTHOR("Barry Song "); MODULE_DESCRIPTION("SIRFSOC DMA control driver"); MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 2cd23553b488589f287457b7396470f5e3c40698 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Mon, 8 Jun 2015 08:28:07 +0200 Subject: x86/asm/entry: Rename compat syscall entry points Rename the following system call entry points: ia32_cstar_target -> entry_SYSCALL_compat ia32_syscall -> entry_INT80_compat The generic naming scheme for x86 system call entry points is: entry_MNEMONIC_qualifier where 'qualifier' is one of _32, _64 or _compat. Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- Documentation/x86/entry_64.txt | 4 ++-- arch/x86/entry/entry_64_compat.S | 8 ++++---- arch/x86/entry/syscall_32.c | 6 +++--- arch/x86/include/asm/proto.h | 4 ++-- arch/x86/kernel/asm-offsets_64.c | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/traps.c | 2 +- arch/x86/xen/xen-asm_64.S | 2 +- 8 files changed, 15 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/x86/entry_64.txt b/Documentation/x86/entry_64.txt index 9132b86176a3..33884d156125 100644 --- a/Documentation/x86/entry_64.txt +++ b/Documentation/x86/entry_64.txt @@ -18,10 +18,10 @@ Some of these entries are: - system_call: syscall instruction from 64-bit code. - - ia32_syscall: int 0x80 from 32-bit or 64-bit code; compat syscall + - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall either way. - - ia32_syscall, ia32_sysenter: syscall and sysenter from 32-bit + - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit code - interrupt: An array of entries. Every IDT vector that doesn't diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 9558dacf32b9..8058892fb5ff 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -288,7 +288,7 @@ ENDPROC(ia32_sysenter_target) * path below. We set up a complete hardware stack frame to share code * with the int 0x80 path. */ -ENTRY(ia32_cstar_target) +ENTRY(entry_SYSCALL_compat) /* * Interrupts are off on entry. * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, @@ -409,7 +409,7 @@ cstar_tracesys: RESTORE_EXTRA_REGS jmp cstar_do_call -END(ia32_cstar_target) +END(entry_SYSCALL_compat) ia32_badarg: ASM_CLAC @@ -445,7 +445,7 @@ ia32_ret_from_sys_call: * Assumes it is only called from user space and entered with interrupts off. */ -ENTRY(ia32_syscall) +ENTRY(entry_INT80_compat) /* * Interrupts are off on entry. * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, @@ -511,7 +511,7 @@ ia32_tracesys: movl %eax, %eax /* zero extension */ RESTORE_EXTRA_REGS jmp ia32_do_call -END(ia32_syscall) +END(entry_INT80_compat) .macro PTREGSCALL label, func ALIGN diff --git a/arch/x86/entry/syscall_32.c b/arch/x86/entry/syscall_32.c index 3777189c4a19..e398d033673f 100644 --- a/arch/x86/entry/syscall_32.c +++ b/arch/x86/entry/syscall_32.c @@ -10,7 +10,7 @@ #else #define SYM(sym, compat) sym #define ia32_sys_call_table sys_call_table -#define __NR_ia32_syscall_max __NR_syscall_max +#define __NR_entry_INT80_compat_max __NR_syscall_max #endif #define __SYSCALL_I386(nr, sym, compat) extern asmlinkage void SYM(sym, compat)(void) ; @@ -23,11 +23,11 @@ typedef asmlinkage void (*sys_call_ptr_t)(void); extern asmlinkage void sys_ni_syscall(void); -__visible const sys_call_ptr_t ia32_sys_call_table[__NR_ia32_syscall_max+1] = { +__visible const sys_call_ptr_t ia32_sys_call_table[__NR_entry_INT80_compat_max+1] = { /* * Smells like a compiler bug -- it doesn't work * when the & below is removed. */ - [0 ... __NR_ia32_syscall_max] = &sys_ni_syscall, + [0 ... __NR_entry_INT80_compat_max] = &sys_ni_syscall, #include }; diff --git a/arch/x86/include/asm/proto.h b/arch/x86/include/asm/proto.h index a90f8972dad5..7d2961a231f1 100644 --- a/arch/x86/include/asm/proto.h +++ b/arch/x86/include/asm/proto.h @@ -8,8 +8,8 @@ void system_call(void); void syscall_init(void); -void ia32_syscall(void); -void ia32_cstar_target(void); +void entry_INT80_compat(void); +void entry_SYSCALL_compat(void); void ia32_sysenter_target(void); void x86_configure_nx(void); diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c index dcaab87da629..599afcf0005f 100644 --- a/arch/x86/kernel/asm-offsets_64.c +++ b/arch/x86/kernel/asm-offsets_64.c @@ -66,7 +66,7 @@ int main(void) DEFINE(__NR_syscall_max, sizeof(syscalls_64) - 1); DEFINE(NR_syscalls, sizeof(syscalls_64)); - DEFINE(__NR_ia32_syscall_max, sizeof(syscalls_ia32) - 1); + DEFINE(__NR_entry_INT80_compat_max, sizeof(syscalls_ia32) - 1); DEFINE(IA32_NR_syscalls, sizeof(syscalls_ia32)); return 0; diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 6bec0b55863e..f0b85c401014 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1207,7 +1207,7 @@ void syscall_init(void) wrmsrl(MSR_LSTAR, system_call); #ifdef CONFIG_IA32_EMULATION - wrmsrl(MSR_CSTAR, ia32_cstar_target); + wrmsrl(MSR_CSTAR, entry_SYSCALL_compat); /* * This only works on Intel CPUs. * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 5e0791f9d3dc..edf97986a53d 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -992,7 +992,7 @@ void __init trap_init(void) set_bit(i, used_vectors); #ifdef CONFIG_IA32_EMULATION - set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); + set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_compat); set_bit(IA32_SYSCALL_VECTOR, used_vectors); #endif diff --git a/arch/x86/xen/xen-asm_64.S b/arch/x86/xen/xen-asm_64.S index 04529e620559..3c43c03a499c 100644 --- a/arch/x86/xen/xen-asm_64.S +++ b/arch/x86/xen/xen-asm_64.S @@ -122,7 +122,7 @@ ENDPROC(xen_syscall_target) /* 32-bit compat syscall target */ ENTRY(xen_syscall32_target) undo_xen_syscall - jmp ia32_cstar_target + jmp entry_SYSCALL_compat ENDPROC(xen_syscall32_target) /* 32-bit compat sysenter target */ -- cgit v1.2.3 From 315d27aacf1801b009e8f7ec9f92adba6243aec2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 1 Jun 2015 08:56:49 -0300 Subject: [media] DocBook: document DVB net API The DVB network API was not documented. There are just some placeholders there. Replace it by a proper documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 2 +- Documentation/DocBook/media/dvb/dvbapi.xml | 2 +- Documentation/DocBook/media/dvb/net.xml | 374 ++++++++++++++++++----------- Documentation/DocBook/media_api.tmpl | 20 +- 4 files changed, 245 insertions(+), 153 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index dbc9a56e8260..ae9d5a0404aa 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -91,7 +91,7 @@ STRUCTS = \ $(shell perl -ne 'print "$$1 " if (/^struct\s+([^\s]+)\s+/)' $(srctree)/include/uapi/linux/dvb/ca.h) \ $(shell perl -ne 'print "$$1 " if (/^struct\s+([^\s]+)\s+/)' $(srctree)/include/uapi/linux/dvb/dmx.h) \ $(shell perl -ne 'print "$$1 " if (!/dtv\_cmds\_h/ && /^struct\s+([^\s]+)\s+/)' $(srctree)/include/uapi/linux/dvb/frontend.h) \ - $(shell perl -ne 'print "$$1 " if (/^struct\s+([A-Z][^\s]+)\s+/)' $(srctree)/include/uapi/linux/dvb/net.h) \ + $(shell perl -ne 'print "$$1 " if (/^struct\s+([^\s]+)\s+/ && !/_old/)' $(srctree)/include/uapi/linux/dvb/net.h) \ $(shell perl -ne 'print "$$1 " if (/^struct\s+([^\s]+)\s+/)' $(srctree)/include/uapi/linux/dvb/video.h) \ $(shell perl -ne 'print "$$1 " if /^struct\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/media.h) \ $(shell perl -ne 'print "$$1 " if /^struct\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/v4l2-subdev.h) \ diff --git a/Documentation/DocBook/media/dvb/dvbapi.xml b/Documentation/DocBook/media/dvb/dvbapi.xml index dc8cb558f9fd..858fd7d17104 100644 --- a/Documentation/DocBook/media/dvb/dvbapi.xml +++ b/Documentation/DocBook/media/dvb/dvbapi.xml @@ -108,7 +108,7 @@ Added ISDB-T test originally written by Patrick Boettcher &sub-ca; - + &sub-net; diff --git a/Documentation/DocBook/media/dvb/net.xml b/Documentation/DocBook/media/dvb/net.xml index d4ef21764959..aeac41ca7eae 100644 --- a/Documentation/DocBook/media/dvb/net.xml +++ b/Documentation/DocBook/media/dvb/net.xml @@ -1,156 +1,238 @@ DVB Network API -The DVB net device enables feeding of MPE (multi protocol encapsulation) packets -received via DVB into the Linux network protocol stack, e.g. for internet via satellite -applications. It can be accessed through /dev/dvb/adapter0/net0. Data types and -and ioctl definitions can be accessed by including linux/dvb/net.h in your -application. - -
-DVB Net Data Types - -
-struct dvb_net_if - -struct dvb_net_if { - __u16 pid; - __u16 if_num; - __u8 feedtype; -#define DVB_NET_FEEDTYPE_MPE 0 /⋆ multi protocol encapsulation ⋆/ -#define DVB_NET_FEEDTYPE_ULE 1 /⋆ ultra lightweight encapsulation ⋆/ -}; - -
+The DVB net device controls the mapping of data packages that are + part of a transport stream to be mapped into a virtual network interface, + visible through the standard Linux network protocol stack. +Currently, two encapsulations are supported: + + + Multi Protocol Encapsulation (MPE) + + Ultra Lightweight Encapsulation (ULE) + + +In order to create the Linux virtual network interfaces, an application + needs to tell to the Kernel what are the PIDs and the encapsulation types + that are present on the transport stream. This is done through + /dev/dvb/adapter?/net? device node. + The data will be available via virtual dvb?_? + network interfaces, and will be controled/routed via the standard + ip tools (like ip, route, netstat, ifconfig, etc). + Data types and and ioctl definitions are defined via + linux/dvb/net.h header. -
DVB net Function Calls -To be written… - - -
NET_ADD_IF -DESCRIPTION - -
-This ioctl is undocumented. Documentation is welcome. - - -SYNOPSIS - - -int ioctl(fd, int request = NET_ADD_IF, - struct dvb_net_if *if); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals NET_ADD_IF for this command. - - -struct dvb_net_if *if - - -Undocumented. - - + + + + + ioctl NET_ADD_IF + &manvol; + + + + NET_ADD_IF + Creates a new network interface for a given Packet ID. + + + + + + int ioctl + int fd + int request + struct dvb_net_if *net_if + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_TONE + + + + net_if + + pointer to &dvb-net-if; + + + + + + + Description + +The NET_ADD_IF ioctl system call selects the Packet ID (PID) that + contains a TCP/IP traffic, the type of encapsulation to be used (MPE or ULE) + and the interface number for the new interface to be created. When the + system call successfully returns, a new virtual network interface is created. +The &dvb-net-if;::ifnum field will be filled with the number of the + created interface. + &return-value-dvb; - + + + +struct <structname>dvb_net_if</structname> description + +
+ struct <structname>dvb_net_if</structname> + + &cs-def; + + + ID + Description + + + + + pid + Packet ID (PID) of the MPEG-TS that contains + data + + ifnum + number of the DVB interface. + + feedtype + Encapsulation type of the feed. It can be: + DVB_NET_FEEDTYPE_MPE for MPE encoding + or + DVB_NET_FEEDTYPE_ULE for ULE encoding. + + + + +
+ + + + + + ioctl NET_REMOVE_IF + &manvol; + + + + NET_REMOVE_IF + Removes a network interface. + + + + + + int ioctl + int fd + int request + int ifnum + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_TONE + + + + net_if + + number of the interface to be removed + + + + + + + Description + +The NET_REMOVE_IF ioctl deletes an interface previously created + via &NET-ADD-IF;. -
NET_REMOVE_IF -DESCRIPTION - - -This ioctl is undocumented. Documentation is welcome. - - -SYNOPSIS - - -int ioctl(fd, int request = NET_REMOVE_IF); - - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals NET_REMOVE_IF for this command. - - &return-value-dvb; -
+ + + + + + + ioctl NET_GET_IF + &manvol; + + + + NET_GET_IF + Read the configuration data of an interface created via + &NET-ADD-IF;. + + + + + + int ioctl + int fd + int request + struct dvb_net_if *net_if + + + + + + Arguments + + + fd + + &fe_fd; + + + + request + + FE_SET_TONE + + + + net_if + + pointer to &dvb-net-if; + + + + + + + Description + +The NET_GET_IF ioctl uses the interface number given by the + &dvb-net-if;::ifnum field and fills the content of &dvb-net-if; with + the packet ID and encapsulation type used on such interface. If the + interface was not created yet with &NET-ADD-IF;, it will return -1 and + fill the errno with EINVAL + error code. -
NET_GET_IF -DESCRIPTION - - -This ioctl is undocumented. Documentation is welcome. - - -SYNOPSIS - - -int ioctl(fd, int request = NET_GET_IF, - struct dvb_net_if *if); - - -PARAMETERS - - -int fd - -File descriptor returned by a previous call to open(). - - -int request - -Equals NET_GET_IF for this command. - - -struct dvb_net_if *if - - -Undocumented. - - &return-value-dvb; -
+ +
diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 1e194514841c..43eda245a1b5 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -95,12 +95,22 @@ For discussing improvements, reporting troubles, sending new drivers, etc, please mail to: Linux Media Mailing List (LMML).. -&sub-v4l2; -&sub-dvbapi; -&sub-remote_controllers; -&sub-media-controller; + +&sub-v4l2; + + +&sub-dvbapi; + + +&sub-remote_controllers; + + +&sub-media-controller; + -&sub-gen-errors; + +&sub-gen-errors; + &sub-fdl-appendix; -- cgit v1.2.3 From eda6bc2d4ca480c2b82a3e3b5431f0571674c4de Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 2 Jun 2015 07:40:53 -0300 Subject: [media] DocBook: specify language and encoding for the document Define the usage of UTF-8 encoding and let clear that the document is in English. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media_api.tmpl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 43eda245a1b5..6591b3a37600 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -1,4 +1,4 @@ - + %media-entities; @@ -33,7 +33,7 @@ ------------------------"> ]> - + LINUX MEDIA INFRASTRUCTURE API -- cgit v1.2.3 From 96048dc1444efd906dc82c0e35b018879de20084 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 2 Jun 2015 08:36:36 -0300 Subject: [media] DocBook: Change DTD schema to version 4.5 According with the docs at docbook.org, no backward compatible changes were done between 4.2 and 4.5 schemas. Some fixes were added, together with new features. So, let's use the latest 4.x schema. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media_api.tmpl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 6591b3a37600..2e7d7692821e 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -1,6 +1,6 @@ - %media-entities; -- cgit v1.2.3 From 21e397bd90c303ea9fe18a1f63ddfa67c48f7150 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 8 Jun 2015 15:19:56 +0300 Subject: ASoC: tas2552: Update DT binding document regarding clock configuration Add overview of tas2552's clock configuration and selection. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/tas2552.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/tas2552.txt b/Documentation/devicetree/bindings/sound/tas2552.txt index 55e2a0af5645..c49992c0b62a 100644 --- a/Documentation/devicetree/bindings/sound/tas2552.txt +++ b/Documentation/devicetree/bindings/sound/tas2552.txt @@ -14,6 +14,12 @@ Required properties: Optional properties: - enable-gpio - gpio pin to enable/disable the device +tas2552 can receive it's reference clock via MCLK, BCLK, IVCLKIN pin or use the +internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM +reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK. +For system integration the dt-bindings/sound/tas2552.h header file provides +defined values to selct and configure the PLL and PDM reference clocks. + Example: tas2552: tas2552@41 { -- cgit v1.2.3 From 7832a91596aeea5c82b956935312d1acf886660a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 2 Jun 2015 14:59:07 -0300 Subject: [media] Docbook: typo fix: use note(d) instead of notice(d) We don't want to announce anything, but to add a note ;) So: notice -> note notided -> noted While here, fix another typo at media_api.tmpl: with -> which Reported-by: Jonathan Corbet Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 8 ++++---- Documentation/DocBook/media/dvb/frontend.xml | 2 +- Documentation/DocBook/media/v4l/remote_controllers.xml | 2 +- Documentation/DocBook/media_api.tmpl | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 5dfde521e9fe..746b4e2ae346 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -193,7 +193,7 @@ get/set up to 64 properties. The actual meaning of each property is described on Most of the digital TV standards currently offers more than one possible modulation (sometimes called as "constellation" on some standards). This - enum contains the values used by the Kernel. Please notice that not all + enum contains the values used by the Kernel. Please note that not all modulations are supported by a given standard. @@ -1098,7 +1098,7 @@ enum fe_interleaving { For most delivery systems, dtv_property.stat.len will be 1 if the stats is supported, and the properties will return a single value for each parameter. - It should be noticed, however, that new OFDM delivery systems + It should be noted, however, that new OFDM delivery systems like ISDB can use different modulation types for each group of carriers. On such standards, up to 3 groups of statistics can be provided, and dtv_property.stat.len is updated @@ -1162,7 +1162,7 @@ enum fe_interleaving { <constant>DTV_STAT_PRE_TOTAL_BIT_COUNT</constant> Measures the amount of bits received before the inner code block, during the same period as DTV_STAT_PRE_ERROR_BIT_COUNT measurement was taken. - It should be noticed that this measurement can be smaller than the total amount of bits on the transport stream, + It should be noted that this measurement can be smaller than the total amount of bits on the transport stream, as the frontend may need to manually restart the measurement, losing some data between each measurement interval. This measurement is monotonically increased, as the frontend gets more bit count measurements. The frontend may reset it when a channel/transponder is tuned. @@ -1191,7 +1191,7 @@ enum fe_interleaving { <constant>DTV_STAT_POST_TOTAL_BIT_COUNT</constant> Measures the amount of bits received after the inner coding, during the same period as DTV_STAT_POST_ERROR_BIT_COUNT measurement was taken. - It should be noticed that this measurement can be smaller than the total amount of bits on the transport stream, + It should be noted that this measurement can be smaller than the total amount of bits on the transport stream, as the frontend may need to manually restart the measurement, losing some data between each measurement interval. This measurement is monotonically increased, as the frontend gets more bit count measurements. The frontend may reset it when a channel/transponder is tuned. diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index 9d8e95cd9694..dc6a1134478d 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -48,7 +48,7 @@ specification is available at The information about the frontend tuner locking status can be queried using FE_READ_STATUS. Signal statistics are provided via FE_GET_PROPERTY. - Please notice that several statistics require the demodulator to be fully + Please note that several statistics require the demodulator to be fully locked (e. g. with FE_HAS_LOCK bit set). See Frontend statistics indicators for more details. diff --git a/Documentation/DocBook/media/v4l/remote_controllers.xml b/Documentation/DocBook/media/v4l/remote_controllers.xml index 5124a6c4daa8..b86844e80257 100644 --- a/Documentation/DocBook/media/v4l/remote_controllers.xml +++ b/Documentation/DocBook/media/v4l/remote_controllers.xml @@ -284,7 +284,7 @@ different IR's. Due to that, V4L2 API now specifies a standard for mapping Media
-It should be noticed that, sometimes, there some fundamental missing keys at some cheaper IR's. Due to that, it is recommended to: +It should be noted that, sometimes, there some fundamental missing keys at some cheaper IR's. Due to that, it is recommended to: Notes diff --git a/Documentation/DocBook/media_api.tmpl b/Documentation/DocBook/media_api.tmpl index 2e7d7692821e..f3f5fe5b64c9 100644 --- a/Documentation/DocBook/media_api.tmpl +++ b/Documentation/DocBook/media_api.tmpl @@ -87,8 +87,8 @@ . The third part covers the Remote Controller API. The fourth part covers the Media Controller API. - It should also be noticed that a media device may also have audio - components, like mixers, PCM capture, PCM playback, etc, with + It should also be noted that a media device may also have audio + components, like mixers, PCM capture, PCM playback, etc, which are controlled via ALSA API. For additional information and for the latest development code, see: http://linuxtv.org. -- cgit v1.2.3 From bf45caf28146dae26140f19bc3b666647d0b6aac Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 2 Jun 2015 16:17:16 -0300 Subject: [media] DocBook: fix some syntax issues at dvbproperty.xml Some minor English syntax fixes. Reported-by: Jonathan Corbet Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 746b4e2ae346..28e306ee5827 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -1,12 +1,12 @@
DVB Frontend properties Tuning into a Digital TV physical channel and starting decoding it - requires to change a set of parameters, in order to control the + requires changing a set of parameters, in order to control the tuner, the demodulator, the Linear Low-noise Amplifier (LNA) and to set the antenna subsystem via Satellite Equipment Control (SEC), on satellite systems. The actual parameters are specific to each particular digital - TV standards, and may change as the digital TV specs evolutes. -In the past, the strategy used were to have an union with the parameters + TV standards, and may change as the digital TV specs evolves. +In the past, the strategy used was to have a union with the parameters needed to tune for DVB-S, DVB-C, DVB-T and ATSC delivery systems grouped there. The problem is that, as the second generation standards appeared, those structs were not big enough to contain the additional parameters. -- cgit v1.2.3 From ec8f3386a7ef6af7f185aba486402e82cd84b0ad Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 2 Jun 2015 16:41:01 -0300 Subject: [media] DocBook: Use constant tag for monospaced fonts As reminded by Jonathan, several places where emphasys role="tt" were used are actually trying to change the font to monospaced. We do that, on other places, by using the constant tag. So, use it here too. Reported-by: Jonathan Corbet Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/audio.xml | 6 +++--- Documentation/DocBook/media/dvb/ca.xml | 4 ++-- Documentation/DocBook/media/dvb/demux.xml | 10 +++++----- Documentation/DocBook/media/dvb/frontend.xml | 4 ++-- Documentation/DocBook/media/dvb/intro.xml | 30 ++++++++++++++-------------- Documentation/DocBook/media/dvb/kdapi.xml | 4 ++-- Documentation/DocBook/media/dvb/net.xml | 4 ++-- Documentation/DocBook/media/dvb/video.xml | 2 +- 8 files changed, 32 insertions(+), 32 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/audio.xml b/Documentation/DocBook/media/dvb/audio.xml index a853e5b81ec7..ea56743ddbe7 100644 --- a/Documentation/DocBook/media/dvb/audio.xml +++ b/Documentation/DocBook/media/dvb/audio.xml @@ -1,7 +1,7 @@ DVB Audio Device The DVB audio device controls the MPEG2 audio decoder of the DVB hardware. It -can be accessed through /dev/dvb/adapter0/audio0. Data types and and -ioctl definitions can be accessed by including linux/dvb/audio.h in your +can be accessed through /dev/dvb/adapter?/audio?. Data types and and +ioctl definitions can be accessed by including linux/dvb/audio.h in your application. Please note that some DVB cards don’t have their own MPEG decoder, which results in @@ -32,7 +32,7 @@ typedef enum { AUDIO_SOURCE_DEMUX selects the demultiplexer (fed either by the frontend or the DVR device) as the source of the video stream. If AUDIO_SOURCE_MEMORY -is selected the stream comes from the application through the write() system +is selected the stream comes from the application through the write() system call. diff --git a/Documentation/DocBook/media/dvb/ca.xml b/Documentation/DocBook/media/dvb/ca.xml index bf9e790d674f..d0b07e763908 100644 --- a/Documentation/DocBook/media/dvb/ca.xml +++ b/Documentation/DocBook/media/dvb/ca.xml @@ -1,7 +1,7 @@ DVB CA Device The DVB CA device controls the conditional access hardware. It can be accessed through -/dev/dvb/adapter0/ca0. Data types and and ioctl definitions can be accessed by -including linux/dvb/ca.h in your application. +/dev/dvb/adapter?/ca?. Data types and and ioctl definitions can be accessed by +including linux/dvb/ca.h in your application.
diff --git a/Documentation/DocBook/media/dvb/demux.xml b/Documentation/DocBook/media/dvb/demux.xml index fae0e0556ca5..11a831d58643 100644 --- a/Documentation/DocBook/media/dvb/demux.xml +++ b/Documentation/DocBook/media/dvb/demux.xml @@ -1,8 +1,8 @@ DVB Demux Device The DVB demux device controls the filters of the DVB hardware/software. It can be -accessed through /dev/adapter0/demux0. Data types and and ioctl definitions can be -accessed by including linux/dvb/dmx.h in your application. +accessed through /dev/adapter?/demux?. Data types and and ioctl definitions can be +accessed by including linux/dvb/dmx.h in your application.
Demux Data Types @@ -21,11 +21,11 @@ typedef enum DMX_OUT_TSDEMUX_TAP /⋆ Like TS_TAP but retrieved from the DMX device ⋆/ } dmx_output_t; -DMX_OUT_TAP delivers the stream output to the demux device on which the ioctl is +DMX_OUT_TAP delivers the stream output to the demux device on which the ioctl is called. -DMX_OUT_TS_TAP routes output to the logical DVR device /dev/dvb/adapter0/dvr0, -which delivers a TS multiplexed from all filters for which DMX_OUT_TS_TAP was +DMX_OUT_TS_TAP routes output to the logical DVR device /dev/dvb/adapter?/dvr?, +which delivers a TS multiplexed from all filters for which DMX_OUT_TS_TAP was specified.
diff --git a/Documentation/DocBook/media/dvb/frontend.xml b/Documentation/DocBook/media/dvb/frontend.xml index dc6a1134478d..01210b33c130 100644 --- a/Documentation/DocBook/media/dvb/frontend.xml +++ b/Documentation/DocBook/media/dvb/frontend.xml @@ -14,9 +14,9 @@ Satellite Equipment Control (SEC) hardware (only for Satellite). The frontend can be accessed through - /dev/dvb/adapter?/frontend?. Data types and + /dev/dvb/adapter?/frontend?. Data types and ioctl definitions can be accessed by including - linux/dvb/frontend.h in your application. + linux/dvb/frontend.h in your application. NOTE: Transmission via the internet (DVB-IP) diff --git a/Documentation/DocBook/media/dvb/intro.xml b/Documentation/DocBook/media/dvb/intro.xml index 1f7a35a2b365..bcc72c216402 100644 --- a/Documentation/DocBook/media/dvb/intro.xml +++ b/Documentation/DocBook/media/dvb/intro.xml @@ -129,41 +129,41 @@ hardware. It can depend on the individual security requirements of the platform, if and how many of the CA functions are made available to the application through this device. -All devices can be found in the /dev -tree under /dev/dvb. The individual devices +All devices can be found in the /dev +tree under /dev/dvb. The individual devices are called: -/dev/dvb/adapterN/audioM, +/dev/dvb/adapterN/audioM, -/dev/dvb/adapterN/videoM, +/dev/dvb/adapterN/videoM, -/dev/dvb/adapterN/frontendM, +/dev/dvb/adapterN/frontendM, -/dev/dvb/adapterN/netM, +/dev/dvb/adapterN/netM, -/dev/dvb/adapterN/demuxM, +/dev/dvb/adapterN/demuxM, -/dev/dvb/adapterN/dvrM, +/dev/dvb/adapterN/dvrM, -/dev/dvb/adapterN/caM, +/dev/dvb/adapterN/caM, where N enumerates the DVB PCI cards in a system starting from 0, and M enumerates the devices of each type within each -adapter, starting from 0, too. We will omit the “/dev/dvb/adapterN/” in the further dicussion +adapter, starting from 0, too. We will omit the “ +/dev/dvb/adapterN/” in the further dicussion of these devices. The naming scheme for the devices is the same wheter devfs is used or not. @@ -202,10 +202,10 @@ a partial path like: To enable applications to support different API version, an -additional include file linux/dvb/version.h exists, which defines the -constant DVB_API_VERSION. This document -describes DVB_API_VERSION 5.10. +additional include file +linux/dvb/version.h exists, which defines the +constant DVB_API_VERSION. This document +describes DVB_API_VERSION 5.10.
diff --git a/Documentation/DocBook/media/dvb/kdapi.xml b/Documentation/DocBook/media/dvb/kdapi.xml index f648115f7149..68bcd33a82c3 100644 --- a/Documentation/DocBook/media/dvb/kdapi.xml +++ b/Documentation/DocBook/media/dvb/kdapi.xml @@ -1,8 +1,8 @@ Kernel Demux API The kernel demux API defines a driver-internal interface for registering low-level, hardware specific driver to a hardware independent demux layer. It is only of interest for -DVB device driver writers. The header file for this API is named demux.h and located in -drivers/media/dvb-core. +DVB device driver writers. The header file for this API is named demux.h and located in +">drivers/media/dvb-core. Maintainer note: This section must be reviewed. It is probably out of date. diff --git a/Documentation/DocBook/media/dvb/net.xml b/Documentation/DocBook/media/dvb/net.xml index aeac41ca7eae..d2e44b7e07df 100644 --- a/Documentation/DocBook/media/dvb/net.xml +++ b/Documentation/DocBook/media/dvb/net.xml @@ -13,12 +13,12 @@ In order to create the Linux virtual network interfaces, an application needs to tell to the Kernel what are the PIDs and the encapsulation types that are present on the transport stream. This is done through - /dev/dvb/adapter?/net? device node. + /dev/dvb/adapter?/net? device node. The data will be available via virtual dvb?_? network interfaces, and will be controled/routed via the standard ip tools (like ip, route, netstat, ifconfig, etc). Data types and and ioctl definitions are defined via - linux/dvb/net.h header. + linux/dvb/net.h header.
DVB net Function Calls diff --git a/Documentation/DocBook/media/dvb/video.xml b/Documentation/DocBook/media/dvb/video.xml index 1ea786f9b798..71547fcd7ba0 100644 --- a/Documentation/DocBook/media/dvb/video.xml +++ b/Documentation/DocBook/media/dvb/video.xml @@ -24,7 +24,7 @@ have been created to replace that functionality.
video_format_t -The video_format_t data type defined by +The video_format_t data type defined by typedef enum { -- cgit v1.2.3 From d96097e03f5155115542d42580b1439cafdb6088 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Fri, 5 Jun 2015 21:38:19 +0900 Subject: NFC: Fix typo in nfc-hci.txt This patch fix a spelling typo in nfc-hci.txt Signed-off-by: Masanari Iida Signed-off-by: Samuel Ortiz --- Documentation/nfc/nfc-hci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/nfc/nfc-hci.txt b/Documentation/nfc/nfc-hci.txt index 0686c9e211c2..0dc078cab972 100644 --- a/Documentation/nfc/nfc-hci.txt +++ b/Documentation/nfc/nfc-hci.txt @@ -122,7 +122,7 @@ This must be done from a context that can sleep. PHY Management -------------- -The physical link (i2c, ...) management is defined by the following struture: +The physical link (i2c, ...) management is defined by the following structure: struct nfc_phy_ops { int (*write)(void *dev_id, struct sk_buff *skb); -- cgit v1.2.3 From ab714817d7e891608d31f6996b1e4c43cf2bf342 Mon Sep 17 00:00:00 2001 From: "Mark A. Greer" Date: Fri, 24 Apr 2015 10:37:22 -0700 Subject: NFC: trf7970a: Handle extra byte in response to Type 5 RMB commands The current versions of the trf7970a has an erratum where it returns an extra byte in the response to 'Read Multiple Block' (RMB) commands. This command is issued to Type 5 tags (i.e., ISO/IEC 15693 tags) by the neard daemon. To handle this, define a new Device Tree property, 't5t-rmb-extra-byte-quirk', which indicates that the associated trf7970a device has this erratum. The trf7970a device driver will then ensure that the response length to RMB commands is reduced by one byte (for devices with the erratum). Signed-off-by: Mark A. Greer Signed-off-by: Samuel Ortiz --- .../devicetree/bindings/net/nfc/trf7970a.txt | 4 ++++ drivers/nfc/trf7970a.c | 23 ++++++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt index 7c89ca290ced..32b35a07abe4 100644 --- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt +++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt @@ -18,6 +18,9 @@ Optional SoC Specific Properties: "IRQ Status Read" erratum. - en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF" erratum. +- t5t-rmb-extra-byte-quirk: Specify that the trf7970a has the erratum + where an extra byte is returned by Read Multiple Block commands issued + to Type 5 tags. Example (for ARM-based BeagleBone with TRF7970A on SPI1): @@ -39,6 +42,7 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1): autosuspend-delay = <30000>; irq-status-read-quirk; en2-rf-quirk; + t5t-rmb-extra-byte-quirk; status = "okay"; }; }; diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c index aa6a333b2ead..85b4d86772d8 100644 --- a/drivers/nfc/trf7970a.c +++ b/drivers/nfc/trf7970a.c @@ -149,6 +149,7 @@ */ #define TRF7970A_QUIRK_IRQ_STATUS_READ BIT(0) #define TRF7970A_QUIRK_EN2_MUST_STAY_LOW BIT(1) +#define TRF7970A_QUIRK_T5T_RMB_EXTRA_BYTE BIT(2) /* Direct commands */ #define TRF7970A_CMD_IDLE 0x00 @@ -446,6 +447,7 @@ struct trf7970a { u8 md_rf_tech; u8 tx_cmd; bool issue_eof; + bool adjust_resp_len; int en2_gpio; int en_gpio; struct mutex lock; @@ -626,6 +628,11 @@ static void trf7970a_send_upstream(struct trf7970a *trf) trf->aborting = false; } + if (trf->adjust_resp_len) { + skb_trim(trf->rx_skb, trf->rx_skb->len - 1); + trf->adjust_resp_len = false; + } + trf->cb(trf->ddev, trf->cb_arg, trf->rx_skb); trf->rx_skb = NULL; @@ -1429,10 +1436,15 @@ static int trf7970a_per_cmd_config(struct trf7970a *trf, struct sk_buff *skb) trf->iso_ctrl = iso_ctrl; } - if ((trf->framing == NFC_DIGITAL_FRAMING_ISO15693_T5T) && - trf7970a_is_iso15693_write_or_lock(req[1]) && - (req[0] & ISO15693_REQ_FLAG_OPTION)) - trf->issue_eof = true; + if (trf->framing == NFC_DIGITAL_FRAMING_ISO15693_T5T) { + if (trf7970a_is_iso15693_write_or_lock(req[1]) && + (req[0] & ISO15693_REQ_FLAG_OPTION)) + trf->issue_eof = true; + else if ((trf->quirks & + TRF7970A_QUIRK_T5T_RMB_EXTRA_BYTE) && + (req[1] == ISO15693_CMD_READ_MULTIPLE_BLOCK)) + trf->adjust_resp_len = true; + } } return 0; @@ -1992,6 +2004,9 @@ static int trf7970a_probe(struct spi_device *spi) return ret; } + if (of_property_read_bool(np, "t5t-rmb-extra-byte-quirk")) + trf->quirks |= TRF7970A_QUIRK_T5T_RMB_EXTRA_BYTE; + if (of_property_read_bool(np, "irq-status-read-quirk")) trf->quirks |= TRF7970A_QUIRK_IRQ_STATUS_READ; -- cgit v1.2.3 From bbf5f037fad47e4affef6696aaf88a40b261e639 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 May 2015 15:37:18 +0200 Subject: iio: st_accel: support the LIS331DL sensor This adds support for the LIS331DL sensor version. This is a simple 8bit-only accelerometer. Signed-off-by: Linus Walleij Acked-by: Denis Ciocca Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/st-sensors.txt | 1 + drivers/iio/accel/st_accel.h | 1 + drivers/iio/accel/st_accel_core.c | 70 ++++++++++++++++++++++ drivers/iio/accel/st_accel_i2c.c | 4 ++ 4 files changed, 76 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index fb5e0c2d18b5..8a6be3bdf267 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -30,6 +30,7 @@ Accelerometers: - st,lsm330d-accel - st,lsm330dl-accel - st,lsm330dlc-accel +- st,lis331dl-accel - st,lis331dlh-accel - st,lsm303dl-accel - st,lsm303dlm-accel diff --git a/drivers/iio/accel/st_accel.h b/drivers/iio/accel/st_accel.h index 7ee9724b1428..aa1001931d0c 100644 --- a/drivers/iio/accel/st_accel.h +++ b/drivers/iio/accel/st_accel.h @@ -20,6 +20,7 @@ #define LSM330D_ACCEL_DEV_NAME "lsm330d_accel" #define LSM330DL_ACCEL_DEV_NAME "lsm330dl_accel" #define LSM330DLC_ACCEL_DEV_NAME "lsm330dlc_accel" +#define LIS331DL_ACCEL_DEV_NAME "lis331dl_accel" #define LIS331DLH_ACCEL_DEV_NAME "lis331dlh" #define LSM303DL_ACCEL_DEV_NAME "lsm303dl_accel" #define LSM303DLH_ACCEL_DEV_NAME "lsm303dlh_accel" diff --git a/drivers/iio/accel/st_accel_core.c b/drivers/iio/accel/st_accel_core.c index ad19fb4304df..970e9f904dde 100644 --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -153,6 +153,28 @@ #define ST_ACCEL_4_IG1_EN_MASK 0x08 #define ST_ACCEL_4_MULTIREAD_BIT true +/* CUSTOM VALUES FOR SENSOR 5 */ +#define ST_ACCEL_5_WAI_EXP 0x3b +#define ST_ACCEL_5_ODR_ADDR 0x20 +#define ST_ACCEL_5_ODR_MASK 0x80 +#define ST_ACCEL_5_ODR_AVL_100HZ_VAL 0x00 +#define ST_ACCEL_5_ODR_AVL_400HZ_VAL 0x01 +#define ST_ACCEL_5_PW_ADDR 0x20 +#define ST_ACCEL_5_PW_MASK 0x40 +#define ST_ACCEL_5_FS_ADDR 0x20 +#define ST_ACCEL_5_FS_MASK 0x20 +#define ST_ACCEL_5_FS_AVL_2_VAL 0X00 +#define ST_ACCEL_5_FS_AVL_8_VAL 0X01 +/* TODO: check these resulting gain settings, these are not in the datsheet */ +#define ST_ACCEL_5_FS_AVL_2_GAIN IIO_G_TO_M_S_2(18000) +#define ST_ACCEL_5_FS_AVL_8_GAIN IIO_G_TO_M_S_2(72000) +#define ST_ACCEL_5_DRDY_IRQ_ADDR 0x22 +#define ST_ACCEL_5_DRDY_IRQ_INT1_MASK 0x04 +#define ST_ACCEL_5_DRDY_IRQ_INT2_MASK 0x20 +#define ST_ACCEL_5_IG1_EN_ADDR 0x21 +#define ST_ACCEL_5_IG1_EN_MASK 0x08 +#define ST_ACCEL_5_MULTIREAD_BIT false + static const struct iio_chan_spec st_accel_8bit_channels[] = { ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), @@ -470,6 +492,54 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { .multi_read_bit = ST_ACCEL_4_MULTIREAD_BIT, .bootime = 2, /* guess */ }, + { + .wai = ST_ACCEL_5_WAI_EXP, + .sensors_supported = { + [0] = LIS331DL_ACCEL_DEV_NAME, + }, + .ch = (struct iio_chan_spec *)st_accel_8bit_channels, + .odr = { + .addr = ST_ACCEL_5_ODR_ADDR, + .mask = ST_ACCEL_5_ODR_MASK, + .odr_avl = { + { 100, ST_ACCEL_5_ODR_AVL_100HZ_VAL }, + { 400, ST_ACCEL_5_ODR_AVL_400HZ_VAL, }, + }, + }, + .pw = { + .addr = ST_ACCEL_5_PW_ADDR, + .mask = ST_ACCEL_5_PW_MASK, + .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE, + .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, + }, + .enable_axis = { + .addr = ST_SENSORS_DEFAULT_AXIS_ADDR, + .mask = ST_SENSORS_DEFAULT_AXIS_MASK, + }, + .fs = { + .addr = ST_ACCEL_5_FS_ADDR, + .mask = ST_ACCEL_5_FS_MASK, + .fs_avl = { + [0] = { + .num = ST_ACCEL_FS_AVL_2G, + .value = ST_ACCEL_5_FS_AVL_2_VAL, + .gain = ST_ACCEL_5_FS_AVL_2_GAIN, + }, + [1] = { + .num = ST_ACCEL_FS_AVL_8G, + .value = ST_ACCEL_5_FS_AVL_8_VAL, + .gain = ST_ACCEL_5_FS_AVL_8_GAIN, + }, + }, + }, + .drdy_irq = { + .addr = ST_ACCEL_5_DRDY_IRQ_ADDR, + .mask_int1 = ST_ACCEL_5_DRDY_IRQ_INT1_MASK, + .mask_int2 = ST_ACCEL_5_DRDY_IRQ_INT2_MASK, + }, + .multi_read_bit = ST_ACCEL_5_MULTIREAD_BIT, + .bootime = 2, /* guess */ + }, }; static int st_accel_read_raw(struct iio_dev *indio_dev, diff --git a/drivers/iio/accel/st_accel_i2c.c b/drivers/iio/accel/st_accel_i2c.c index 6b720c190b2d..d4ad72ca4a3d 100644 --- a/drivers/iio/accel/st_accel_i2c.c +++ b/drivers/iio/accel/st_accel_i2c.c @@ -48,6 +48,10 @@ static const struct of_device_id st_accel_of_match[] = { .compatible = "st,lsm330dlc-accel", .data = LSM330DLC_ACCEL_DEV_NAME, }, + { + .compatible = "st,lis331dl-accel", + .data = LIS331DL_ACCEL_DEV_NAME, + }, { .compatible = "st,lis331dlh-accel", .data = LIS331DLH_ACCEL_DEV_NAME, -- cgit v1.2.3 From a28ab162bdf04d0e5d814478340ba32999233e7e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 6 Jun 2015 19:05:51 +0900 Subject: Documentation: ARM: EXYNOS: Describe boot loaders interface Various boot loaders for Exynos based boards use certain memory addresses during booting for different purposes. Mostly this is one of following : 1. as a CPU boot address, 2. for storing magic cookie related to low power mode (AFTR, sleep). The document, based solely on kernel source code, tries to group the information scattered over different files. This would help in the future when adding support for new SoC or when extending features related to low power modes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Jonathan Corbet --- Documentation/arm/Samsung/Bootloader-interface.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/arm/Samsung/Bootloader-interface.txt (limited to 'Documentation') diff --git a/Documentation/arm/Samsung/Bootloader-interface.txt b/Documentation/arm/Samsung/Bootloader-interface.txt new file mode 100644 index 000000000000..b96ead9a6919 --- /dev/null +++ b/Documentation/arm/Samsung/Bootloader-interface.txt @@ -0,0 +1,53 @@ + Interface between kernel and boot loaders on Exynos boards + ========================================================== + +Author: Krzysztof Kozlowski +Date : 6 June 2015 + +The document tries to describe currently used interface between Linux kernel +and boot loaders on Samsung Exynos based boards. This is not a definition +of interface but rather a description of existing state, a reference +for information purpose only. + +In the document "boot loader" means any of following: U-boot, proprietary +SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before +executing kernel. + + +1. Non-Secure mode +Address: sysram_ns_base_addr +Offset Value Purpose +============================================================================= +0x08 exynos_cpu_resume_ns System suspend +0x0c 0x00000bad (Magic cookie) System suspend +0x1c exynos4_secondary_startup Secondary CPU boot +0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot +0x20 0xfcba0d10 (Magic cookie) AFTR +0x24 exynos_cpu_resume_ns AFTR +0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR + + +2. Secure mode +Address: sysram_base_addr +Offset Value Purpose +============================================================================= +0x00 exynos4_secondary_startup Secondary CPU boot +0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot +4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot +0x20 exynos_cpu_resume (Exynos4210 r1.0) AFTR +0x24 0xfcba0d10 (Magic cookie, Exynos4210 r1.0) AFTR + +Address: pmu_base_addr +Offset Value Purpose +============================================================================= +0x0800 exynos_cpu_resume AFTR +0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot +0x0818 0xfcba0d10 (Magic cookie, Exynos4210 r1.1) AFTR +0x081C exynos_cpu_resume (Exynos4210 r1.1) AFTR + + +3. Other (regardless of secure/non-secure mode) +Address: pmu_base_addr +Offset Value Purpose +============================================================================= +0x0908 Non-zero (only Exynos3250) Secondary CPU boot up indicator -- cgit v1.2.3 From b3fd7368f8f60bc9a7ffc2a5311db5f4dbd42180 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sat, 6 Jun 2015 15:42:28 +0200 Subject: Move freefall program from Documentation/ to tools/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Acked-by: Pavel Machek Signed-off-by: Jonathan Corbet --- Documentation/laptops/.gitignore | 1 - Documentation/laptops/00-INDEX | 2 - Documentation/laptops/Makefile | 2 +- Documentation/laptops/freefall.c | 174 --------------------------------------- tools/Makefile | 14 +++- tools/laptop/freefall/Makefile | 17 ++++ tools/laptop/freefall/freefall.c | 174 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 204 insertions(+), 180 deletions(-) delete mode 100644 Documentation/laptops/freefall.c create mode 100644 tools/laptop/freefall/Makefile create mode 100644 tools/laptop/freefall/freefall.c (limited to 'Documentation') diff --git a/Documentation/laptops/.gitignore b/Documentation/laptops/.gitignore index da2bd065f4bc..9fc984e64386 100644 --- a/Documentation/laptops/.gitignore +++ b/Documentation/laptops/.gitignore @@ -1,2 +1 @@ dslm -freefall diff --git a/Documentation/laptops/00-INDEX b/Documentation/laptops/00-INDEX index a3b4f209e562..7c0ac2a26b9e 100644 --- a/Documentation/laptops/00-INDEX +++ b/Documentation/laptops/00-INDEX @@ -8,8 +8,6 @@ disk-shock-protection.txt - information on hard disk shock protection. dslm.c - Simple Disk Sleep Monitor program -freefall.c - - (HP/DELL) laptop accelerometer program for disk protection. laptop-mode.txt - how to conserve battery power using laptop-mode. sony-laptop.txt diff --git a/Documentation/laptops/Makefile b/Documentation/laptops/Makefile index 2b0fa5edf1d3..0abe44f68965 100644 --- a/Documentation/laptops/Makefile +++ b/Documentation/laptops/Makefile @@ -1,5 +1,5 @@ # List of programs to build -hostprogs-y := dslm freefall +hostprogs-y := dslm # Tell kbuild to always build the programs always := $(hostprogs-y) diff --git a/Documentation/laptops/freefall.c b/Documentation/laptops/freefall.c deleted file mode 100644 index 5e44b20b1848..000000000000 --- a/Documentation/laptops/freefall.c +++ /dev/null @@ -1,174 +0,0 @@ -/* Disk protection for HP/DELL machines. - * - * Copyright 2008 Eric Piel - * Copyright 2009 Pavel Machek - * Copyright 2012 Sonal Santan - * Copyright 2014 Pali Rohár - * - * GPLv2. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int noled; -static char unload_heads_path[64]; -static char device_path[32]; -static const char app_name[] = "FREE FALL"; - -static int set_unload_heads_path(char *device) -{ - if (strlen(device) <= 5 || strncmp(device, "/dev/", 5) != 0) - return -EINVAL; - strncpy(device_path, device, sizeof(device_path) - 1); - - snprintf(unload_heads_path, sizeof(unload_heads_path) - 1, - "/sys/block/%s/device/unload_heads", device+5); - return 0; -} - -static int valid_disk(void) -{ - int fd = open(unload_heads_path, O_RDONLY); - - if (fd < 0) { - perror(unload_heads_path); - return 0; - } - - close(fd); - return 1; -} - -static void write_int(char *path, int i) -{ - char buf[1024]; - int fd = open(path, O_RDWR); - - if (fd < 0) { - perror("open"); - exit(1); - } - - sprintf(buf, "%d", i); - - if (write(fd, buf, strlen(buf)) != strlen(buf)) { - perror("write"); - exit(1); - } - - close(fd); -} - -static void set_led(int on) -{ - if (noled) - return; - write_int("/sys/class/leds/hp::hddprotect/brightness", on); -} - -static void protect(int seconds) -{ - const char *str = (seconds == 0) ? "Unparked" : "Parked"; - - write_int(unload_heads_path, seconds*1000); - syslog(LOG_INFO, "%s %s disk head\n", str, device_path); -} - -static int on_ac(void) -{ - /* /sys/class/power_supply/AC0/online */ - return 1; -} - -static int lid_open(void) -{ - /* /proc/acpi/button/lid/LID/state */ - return 1; -} - -static void ignore_me(int signum) -{ - protect(0); - set_led(0); -} - -int main(int argc, char **argv) -{ - int fd, ret; - struct stat st; - struct sched_param param; - - if (argc == 1) - ret = set_unload_heads_path("/dev/sda"); - else if (argc == 2) - ret = set_unload_heads_path(argv[1]); - else - ret = -EINVAL; - - if (ret || !valid_disk()) { - fprintf(stderr, "usage: %s (default: /dev/sda)\n", - argv[0]); - exit(1); - } - - fd = open("/dev/freefall", O_RDONLY); - if (fd < 0) { - perror("/dev/freefall"); - return EXIT_FAILURE; - } - - if (stat("/sys/class/leds/hp::hddprotect/brightness", &st)) - noled = 1; - - if (daemon(0, 0) != 0) { - perror("daemon"); - return EXIT_FAILURE; - } - - openlog(app_name, LOG_CONS | LOG_PID | LOG_NDELAY, LOG_LOCAL1); - - param.sched_priority = sched_get_priority_max(SCHED_FIFO); - sched_setscheduler(0, SCHED_FIFO, ¶m); - mlockall(MCL_CURRENT|MCL_FUTURE); - - signal(SIGALRM, ignore_me); - - for (;;) { - unsigned char count; - - ret = read(fd, &count, sizeof(count)); - alarm(0); - if ((ret == -1) && (errno == EINTR)) { - /* Alarm expired, time to unpark the heads */ - continue; - } - - if (ret != sizeof(count)) { - perror("read"); - break; - } - - protect(21); - set_led(1); - if (1 || on_ac() || lid_open()) - alarm(2); - else - alarm(20); - } - - closelog(); - close(fd); - return EXIT_SUCCESS; -} diff --git a/tools/Makefile b/tools/Makefile index 9a617adc6675..4557c39805e7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -18,6 +18,7 @@ help: @echo ' vm - misc vm tools' @echo ' x86_energy_perf_policy - Intel energy policy tool' @echo ' tmon - thermal monitoring and tuning tool' + @echo ' freefall - laptop accelerometer program for disk protection' @echo '' @echo 'You can do:' @echo ' $$ make -C tools/ _install' @@ -62,6 +63,9 @@ turbostat x86_energy_perf_policy: FORCE tmon: FORCE $(call descend,thermal/$@) +freefall: FORCE + $(call descend,laptop/$@) + acpi_install: $(call descend,power/$(@:_install=),install) @@ -80,10 +84,13 @@ turbostat_install x86_energy_perf_policy_install: tmon_install: $(call descend,thermal/$(@:_install=),install) +freefall_install: + $(call descend,laptop/$(@:_install=),install) + install: acpi_install cgroup_install cpupower_install hv_install firewire_install lguest_install \ perf_install selftests_install turbostat_install usb_install \ virtio_install vm_install net_install x86_energy_perf_policy_install \ - tmon + tmon freefall_install acpi_clean: $(call descend,power/acpi,clean) @@ -112,8 +119,11 @@ turbostat_clean x86_energy_perf_policy_clean: tmon_clean: $(call descend,thermal/tmon,clean) +freefall_clean: + $(call descend,laptop/freefall,clean) + clean: acpi_clean cgroup_clean cpupower_clean hv_clean firewire_clean lguest_clean \ perf_clean selftests_clean turbostat_clean usb_clean virtio_clean \ - vm_clean net_clean x86_energy_perf_policy_clean tmon_clean + vm_clean net_clean x86_energy_perf_policy_clean tmon_clean freefall_clean .PHONY: FORCE diff --git a/tools/laptop/freefall/Makefile b/tools/laptop/freefall/Makefile new file mode 100644 index 000000000000..48c6c9328419 --- /dev/null +++ b/tools/laptop/freefall/Makefile @@ -0,0 +1,17 @@ +PREFIX ?= /usr +SBINDIR ?= sbin +INSTALL ?= install +CC = $(CROSS_COMPILE)gcc + +TARGET = freefall + +all: $(TARGET) + +%: %.c + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $< + +clean: + $(RM) $(TARGET) + +install: freefall + $(INSTALL) -D -m 755 $(TARGET) $(DESTDIR)$(PREFIX)/$(SBINDIR)/$(TARGET) diff --git a/tools/laptop/freefall/freefall.c b/tools/laptop/freefall/freefall.c new file mode 100644 index 000000000000..5e44b20b1848 --- /dev/null +++ b/tools/laptop/freefall/freefall.c @@ -0,0 +1,174 @@ +/* Disk protection for HP/DELL machines. + * + * Copyright 2008 Eric Piel + * Copyright 2009 Pavel Machek + * Copyright 2012 Sonal Santan + * Copyright 2014 Pali Rohár + * + * GPLv2. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int noled; +static char unload_heads_path[64]; +static char device_path[32]; +static const char app_name[] = "FREE FALL"; + +static int set_unload_heads_path(char *device) +{ + if (strlen(device) <= 5 || strncmp(device, "/dev/", 5) != 0) + return -EINVAL; + strncpy(device_path, device, sizeof(device_path) - 1); + + snprintf(unload_heads_path, sizeof(unload_heads_path) - 1, + "/sys/block/%s/device/unload_heads", device+5); + return 0; +} + +static int valid_disk(void) +{ + int fd = open(unload_heads_path, O_RDONLY); + + if (fd < 0) { + perror(unload_heads_path); + return 0; + } + + close(fd); + return 1; +} + +static void write_int(char *path, int i) +{ + char buf[1024]; + int fd = open(path, O_RDWR); + + if (fd < 0) { + perror("open"); + exit(1); + } + + sprintf(buf, "%d", i); + + if (write(fd, buf, strlen(buf)) != strlen(buf)) { + perror("write"); + exit(1); + } + + close(fd); +} + +static void set_led(int on) +{ + if (noled) + return; + write_int("/sys/class/leds/hp::hddprotect/brightness", on); +} + +static void protect(int seconds) +{ + const char *str = (seconds == 0) ? "Unparked" : "Parked"; + + write_int(unload_heads_path, seconds*1000); + syslog(LOG_INFO, "%s %s disk head\n", str, device_path); +} + +static int on_ac(void) +{ + /* /sys/class/power_supply/AC0/online */ + return 1; +} + +static int lid_open(void) +{ + /* /proc/acpi/button/lid/LID/state */ + return 1; +} + +static void ignore_me(int signum) +{ + protect(0); + set_led(0); +} + +int main(int argc, char **argv) +{ + int fd, ret; + struct stat st; + struct sched_param param; + + if (argc == 1) + ret = set_unload_heads_path("/dev/sda"); + else if (argc == 2) + ret = set_unload_heads_path(argv[1]); + else + ret = -EINVAL; + + if (ret || !valid_disk()) { + fprintf(stderr, "usage: %s (default: /dev/sda)\n", + argv[0]); + exit(1); + } + + fd = open("/dev/freefall", O_RDONLY); + if (fd < 0) { + perror("/dev/freefall"); + return EXIT_FAILURE; + } + + if (stat("/sys/class/leds/hp::hddprotect/brightness", &st)) + noled = 1; + + if (daemon(0, 0) != 0) { + perror("daemon"); + return EXIT_FAILURE; + } + + openlog(app_name, LOG_CONS | LOG_PID | LOG_NDELAY, LOG_LOCAL1); + + param.sched_priority = sched_get_priority_max(SCHED_FIFO); + sched_setscheduler(0, SCHED_FIFO, ¶m); + mlockall(MCL_CURRENT|MCL_FUTURE); + + signal(SIGALRM, ignore_me); + + for (;;) { + unsigned char count; + + ret = read(fd, &count, sizeof(count)); + alarm(0); + if ((ret == -1) && (errno == EINTR)) { + /* Alarm expired, time to unpark the heads */ + continue; + } + + if (ret != sizeof(count)) { + perror("read"); + break; + } + + protect(21); + set_led(1); + if (1 || on_ac() || lid_open()) + alarm(2); + else + alarm(20); + } + + closelog(); + close(fd); + return EXIT_SUCCESS; +} -- cgit v1.2.3 From fc10639dfdc2603e8776ebbf6b20ff8b03340ed3 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Sat, 6 Jun 2015 23:43:21 +0900 Subject: Doc: ja_JP: Fix typo in HOWTO This patch fix a spelling typo in ja_JP/HOWTO. Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/ja_JP/HOWTO | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/ja_JP/HOWTO b/Documentation/ja_JP/HOWTO index b61885c35ce1..5a0f2bdc2cf9 100644 --- a/Documentation/ja_JP/HOWTO +++ b/Documentation/ja_JP/HOWTO @@ -445,7 +445,7 @@ MAINTAINERS ファイルにリストがありますので参照してくださ メールの先頭でなく、各引用行の間にあなたの言いたいことを追加するべきで す。 -もしパッチをメールに付ける場合は、Documentaion/SubmittingPatches に提 +もしパッチをメールに付ける場合は、Documentation/SubmittingPatches に提 示されているように、それは プレーンな可読テキストにすることを忘れない ようにしましょう。カーネル開発者は 添付や圧縮したパッチを扱いたがりま せん- -- cgit v1.2.3 From bd55daf48dc9a7583031c6c0c6930d7f836f56af Mon Sep 17 00:00:00 2001 From: Jeffrey Rogers Date: Sat, 6 Jun 2015 17:18:45 -0400 Subject: kbuild: edit explanation of clean-files variable Commit 976591810f8a (kbuild Update documentation of clean-files and clean-dirs) changed the example for the clean-files variable, but left the explanation unchanged. Edit the explanation to match the example. Signed-off-by: Jeffrey Rogers Signed-off-by: Jonathan Corbet --- Documentation/kbuild/makefiles.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt index 74b6c6d97210..e63b446d973c 100644 --- a/Documentation/kbuild/makefiles.txt +++ b/Documentation/kbuild/makefiles.txt @@ -755,8 +755,8 @@ Additional files can be specified in kbuild makefiles by use of $(clean-files). #lib/Makefile clean-files := crc32table.h -When executing "make clean", the two files "devlist.h classlist.h" will be -deleted. Kbuild will assume files to be in the same relative directory as the +When executing "make clean", the file "crc32table.h" will be deleted. +Kbuild will assume files to be in the same relative directory as the Makefile, except if prefixed with $(objtree). To delete a directory hierarchy use: -- cgit v1.2.3 From ac7ba51c215db5739eb640f2f26025ced8668285 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 8 Jun 2015 14:30:55 -0500 Subject: net: phy: dp83867: Fix device tree entries Fix the device tree entries to modify the '_' to '-'. Also changes the names of the internal delay properties from -int- to -internal- as the -int- appeared as a keyword. Signed-off-by: Dan Murphy Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/ti,dp83867.txt | 18 ++++++++++++------ drivers/net/phy/dp83867.c | 6 +++--- 2 files changed, 15 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index 46bb67a222ea..58d935b58598 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -2,18 +2,24 @@ Required properties: - reg - The ID number for the phy, usually a small integer - - ti,rx_int_delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h for applicable values - - ti,tx_int_delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h for applicable values - - ti,fifo_depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable values +Default child nodes are standard Ethernet PHY device +nodes as described in Documentation/devicetree/bindings/net/phy.txt + Example: ethernet-phy@0 { reg = <0>; - ti,rx_int_delay = ; - ti,tx_int_delay = ; - ti,fifo_depth = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; }; + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index ef0b4eb15f8d..c7a12e2e07b7 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -113,17 +113,17 @@ static int dp83867_of_init(struct phy_device *phydev) if (!phydev->dev.of_node) return -ENODEV; - ret = of_property_read_u32(of_node, "ti,rx_int_delay", + ret = of_property_read_u32(of_node, "ti,rx-internal-delay", &dp83867->rx_id_delay); if (ret) return ret; - ret = of_property_read_u32(of_node, "ti,tx_int_delay", + ret = of_property_read_u32(of_node, "ti,tx-internal-delay", &dp83867->tx_id_delay); if (ret) return ret; - ret = of_property_read_u32(of_node, "ti,fifo_depth", + ret = of_property_read_u32(of_node, "ti,fifo-depth", &dp83867->fifo_depth); if (ret) return ret; -- cgit v1.2.3 From 0d03943c0b50ad47ec6bb157a5d02d6ba9da477e Mon Sep 17 00:00:00 2001 From: Thomas de Beauchene Date: Sun, 7 Jun 2015 16:30:23 +0200 Subject: Documentation: filesystems: updated struct file_operations documentation in vfs.txt Updated struct file_operations documentation in vfs.txt to match current implementation Signed-off-by: Thomas de Beauchene Signed-off-by: Jonathan Corbet --- Documentation/filesystems/vfs.txt | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index 5d833b32bbcd..2dd5274671c8 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -797,7 +797,7 @@ struct file_operations ---------------------- This describes how the VFS can manipulate an open file. As of kernel -3.12, the following members are defined: +4.1, the following members are defined: struct file_operations { struct module *owner; @@ -811,8 +811,9 @@ struct file_operations { long (*unlocked_ioctl) (struct file *, unsigned int, unsigned long); long (*compat_ioctl) (struct file *, unsigned int, unsigned long); int (*mmap) (struct file *, struct vm_area_struct *); + int (*mremap)(struct file *, struct vm_area_struct *); int (*open) (struct inode *, struct file *); - int (*flush) (struct file *); + int (*flush) (struct file *, fl_owner_t id); int (*release) (struct inode *, struct file *); int (*fsync) (struct file *, loff_t, loff_t, int datasync); int (*aio_fsync) (struct kiocb *, int datasync); @@ -822,11 +823,15 @@ struct file_operations { unsigned long (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); int (*check_flags)(int); int (*flock) (struct file *, int, struct file_lock *); - ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, size_t, unsigned int); - ssize_t (*splice_read)(struct file *, struct pipe_inode_info *, size_t, unsigned int); - int (*setlease)(struct file *, long arg, struct file_lock **, void **); - long (*fallocate)(struct file *, int mode, loff_t offset, loff_t len); + ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int); + ssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int); + int (*setlease)(struct file *, long, struct file_lock **, void **); + long (*fallocate)(struct file *file, int mode, loff_t offset, + loff_t len); void (*show_fdinfo)(struct seq_file *m, struct file *f); +#ifndef CONFIG_MMU + unsigned (*mmap_capabilities)(struct file *); +#endif }; Again, all methods are called without any locks being held, unless -- cgit v1.2.3 From 5163fb62541e38fea400f96dcef9aa539fd00b48 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 4 Jun 2015 15:10:04 +0800 Subject: ahci: added support for Freescale AHCI sata Freescale introduced QorIQ series SOCs, like ls1021 ls2085, with AHCI sata support. It complies with the serial ATA 3.0 specification and the AHCI 1.3 specification. Signed-off-by: Shaohui Xie Signed-off-by: Yuantian Tang Signed-off-by: Tejun Heo --- Documentation/devicetree/bindings/ata/ahci-platform.txt | 2 ++ drivers/ata/ahci_platform.c | 1 + 2 files changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index c2340eeeb97f..a2321819e7f5 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -16,6 +16,8 @@ Required properties: - "snps,dwc-ahci" - "snps,exynos5440-ahci" - "snps,spear-ahci" + - "fsl,qoriq-ahci" : for qoriq series socs which include ls1021, ls2085, etc. + - "fsl,-ahci" : chip could be ls1021, ls2085 etc. - "generic-ahci" - interrupts : - reg : diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index 78d6ae0b90c4..614c78f510f0 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -74,6 +74,7 @@ static const struct of_device_id ahci_of_match[] = { { .compatible = "ibm,476gtr-ahci", }, { .compatible = "snps,dwc-ahci", }, { .compatible = "hisilicon,hisi-ahci", }, + { .compatible = "fsl,qoriq-ahci", }, {}, }; MODULE_DEVICE_TABLE(of, ahci_of_match); -- cgit v1.2.3 From 8c3641e957a948f41f0174290096ed7a3b95e703 Mon Sep 17 00:00:00 2001 From: Dave Hansen Date: Sun, 7 Jun 2015 11:37:02 -0700 Subject: x86/mpx: Introduce a boot-time disable flag MPX has the _potential_ to cause some issues. Say part of your init system tried to protect one of its components from buffer overflows with MPX. If there were a false positive, it's possible that MPX could keep a system from booting. MPX could also potentially cause performance issues since it is present in hot paths like the unmap path. Allow it to be disabled at boot time. Signed-off-by: Dave Hansen Reviewed-by: Thomas Gleixner Cc: Dave Hansen Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20150607183702.2E8B77AB@viggo.jf.intel.com Signed-off-by: Ingo Molnar --- Documentation/kernel-parameters.txt | 4 ++++ arch/x86/kernel/cpu/common.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..8b7e5c342302 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -937,6 +937,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Enable debug messages at boot time. See Documentation/dynamic-debug-howto.txt for details. + nompx [X86] Disables Intel Memory Protection Extensions. + See Documentation/x86/intel_mpx.txt for more + information about the feature. + eagerfpu= [X86] on enable eager fpu restore off disable eager fpu restore diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 401ccb03054e..3956858e5312 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -144,6 +144,22 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { } }; EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); +static int __init x86_mpx_setup(char *s) +{ + /* require an exact match without trailing characters */ + if (strlen(s)) + return 0; + + /* do not emit a message if the feature is not present */ + if (!boot_cpu_has(X86_FEATURE_MPX)) + return 1; + + setup_clear_cpu_cap(X86_FEATURE_MPX); + pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); + return 1; +} +__setup("nompx", x86_mpx_setup); + #ifdef CONFIG_X86_32 static int cachesize_override = -1; static int disable_x86_serial_nr = 1; -- cgit v1.2.3 From d4b5c782b9f4ef5b3c34cb369989cc2fc68f7391 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Tue, 5 May 2015 13:27:44 -0700 Subject: dt/bindings: Add binding for the BCM2835 mailbox driver This patch was split out of Lubomir's original mailbox patch by Eric Anholt, and the required properties documentation and examples have been filled out more completely and updated for the driver being changed to expose a single channel. Signed-off-by: Lubomir Rintel Signed-off-by: Craig McGeachie Signed-off-by: Eric Anholt Acked-by: Lee Jones Acked-by: Stephen Warren Signed-off-by: Jassi Brar --- .../bindings/mailbox/brcm,bcm2835-mbox.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt new file mode 100644 index 000000000000..e893615ef635 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt @@ -0,0 +1,26 @@ +Broadcom BCM2835 VideoCore mailbox IPC + +Required properties: + +- compatible: Should be "brcm,bcm2835-mbox" +- reg: Specifies base physical address and size of the registers +- interrupts: The interrupt number + See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +- #mbox-cells: Specifies the number of cells needed to encode a mailbox + channel. The value shall be 0, since there is only one + mailbox channel implemented by the device. + +Example: + +mailbox: mailbox@7e00b800 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; + #mbox-cells = <0>; +}; + +firmware: firmware { + compatible = "raspberrypi,firmware"; + mboxes = <&mailbox>; + #power-domain-cells = <1>; +}; -- cgit v1.2.3 From 8721fa692bc218df3f0ad30740baedf176a41f56 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Wed, 10 Jun 2015 00:17:42 +0900 Subject: Doc: sound:oss: Fix typo in sound/oss This patch fix some spelling typo found in Documentations/sound/oss. Signed-off-by: Masanari Iida Signed-off-by: Takashi Iwai --- Documentation/sound/oss/PSS-updates | 2 +- Documentation/sound/oss/README.OSS | 2 +- Documentation/sound/oss/btaudio | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/sound/oss/PSS-updates b/Documentation/sound/oss/PSS-updates index c84dd7597e64..11914a1dc7e7 100644 --- a/Documentation/sound/oss/PSS-updates +++ b/Documentation/sound/oss/PSS-updates @@ -41,7 +41,7 @@ pss_no_sound This module parameter is a flag that can be used to tell the driver to just configure non-sound components. 0 configures all components, a non-0 -value will only attept to configure the CDROM and joystick ports. This +value will only attempt to configure the CDROM and joystick ports. This parameter can be used by a user who only wished to use the builtin joystick and/or CDROM port(s) of his PSS sound card. If this driver is loaded with this parameter and with the parameter below set to true then a user can safely unload diff --git a/Documentation/sound/oss/README.OSS b/Documentation/sound/oss/README.OSS index 4be259428a1c..a085ea3611a1 100644 --- a/Documentation/sound/oss/README.OSS +++ b/Documentation/sound/oss/README.OSS @@ -1346,7 +1346,7 @@ implement nice real-time signal processing audio effect software and network telephones. The ACI mixer has to be switched into the "solo" mode for duplex operation in order to avoid feedback caused by the mixer (input hears output signal). You can de-/activate this mode -through toggleing the record button for the wave controller with an +through toggling the record button for the wave controller with an OSS-mixer. The PCM20 contains a radio tuner, which is also controlled by diff --git a/Documentation/sound/oss/btaudio b/Documentation/sound/oss/btaudio index 1a693e69d44b..effdb9a3f898 100644 --- a/Documentation/sound/oss/btaudio +++ b/Documentation/sound/oss/btaudio @@ -29,7 +29,7 @@ Driver Status Still somewhat experimental. The driver should work stable, i.e. it should'nt crash your box. It might not work as expected, have bugs, -not being fully OSS API compilant, ... +not being fully OSS API compliant, ... Latest versions are available from http://bytesex.org/bttv/, the driver is in the bttv tarball. Kernel patches might be available too, -- cgit v1.2.3 From 0f7d6ece6363f315b3b830dc19e6732537719224 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 9 Jun 2015 19:17:53 +0530 Subject: regulator: max8973: add support for MAX77621 Maxim MAX77621 device is high-efficiency, three-phase, DC-DC step-down switching regulator delivers peak output currents up to 16A. This device is extension of MAX8973 and compatible with the register definition. The MAX77621 has the SHUTDOWN pin which is EN pin on the MAX8973. On MAX77621, the SHUTDOWN pin (active low) reset device register to its POR/OTP value. The voltage output is enabled when SHUTDONW pin is HIGH and EN bit on VOUT register is HIGH. For MAX8973, VOUT is enabled when EN bit or EN pin is high. Add support of the MAX77621 device on max8973 regulator driver with following changes: - Make sure SHUTDOWN pin is set HIGH through GPIO calls if GPIO from AP connected to SHUTDOWN pin provided. - Enable/disable the rail through register access only. Signed-off-by: Laxman Dewangan Signed-off-by: Mark Brown --- .../bindings/regulator/max8973-regulator.txt | 4 +- drivers/regulator/max8973-regulator.c | 104 +++++++++++++++++---- 2 files changed, 87 insertions(+), 21 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt index 201a26337387..55efb24e5683 100644 --- a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt @@ -2,7 +2,9 @@ Required properties: -- compatible: must be "maxim,max8973" +- compatible: must be one of following: + "maxim,max8973" + "maxim,max77621". - reg: the i2c slave address of the regulator. It should be 0x1b. Any standard regulator properties can be used to configure the single max8973 diff --git a/drivers/regulator/max8973-regulator.c b/drivers/regulator/max8973-regulator.c index 663e4df44048..89e53e049399 100644 --- a/drivers/regulator/max8973-regulator.c +++ b/drivers/regulator/max8973-regulator.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -91,6 +92,11 @@ #define MAX8973_VOLATGE_STEP 6250 #define MAX8973_BUCK_N_VOLTAGE 0x80 +enum device_id { + MAX8973, + MAX77621 +}; + /* Maxim 8973 chip information */ struct max8973_chip { struct device *dev; @@ -104,6 +110,7 @@ struct max8973_chip { int curr_vout_reg; int curr_gpio_val; struct regulator_ops ops; + enum device_id id; }; /* @@ -390,7 +397,7 @@ static int max8973_init_dcdc(struct max8973_chip *max, } /* If external control is enabled then disable EN bit */ - if (max->enable_external_control) { + if (max->enable_external_control && (max->id == MAX8973)) { ret = regmap_update_bits(max->regmap, MAX8973_VOUT, MAX8973_VOUT_ENABLE, 0); if (ret < 0) @@ -448,6 +455,13 @@ static struct max8973_regulator_platform_data *max8973_parse_dt( return pdata; } +static const struct of_device_id of_max8973_match_tbl[] = { + { .compatible = "maxim,max8973", .data = (void *)MAX8973, }, + { .compatible = "maxim,max77621", .data = (void *)MAX77621, }, + { }, +}; +MODULE_DEVICE_TABLE(of, of_max8973_match_tbl); + static int max8973_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -457,6 +471,7 @@ static int max8973_probe(struct i2c_client *client, struct regulator_dev *rdev; struct max8973_chip *max; bool pdata_from_dt = false; + unsigned int chip_id; int ret; pdata = dev_get_platdata(&client->dev); @@ -486,6 +501,27 @@ static int max8973_probe(struct i2c_client *client, return ret; } + if (client->dev.of_node) { + const struct of_device_id *match; + + match = of_match_device(of_match_ptr(of_max8973_match_tbl), + &client->dev); + if (!match) + return -ENODATA; + max->id = (u32)((uintptr_t)match->data); + } else { + max->id = id->driver_data; + } + + ret = regmap_read(max->regmap, MAX8973_CHIPID1, &chip_id); + if (ret < 0) { + dev_err(&client->dev, "register CHIPID1 read failed, %d", ret); + return ret; + } + + dev_info(&client->dev, "CHIP-ID OTP: 0x%02x ID_M: 0x%02x\n", + (chip_id >> 4) & 0xF, (chip_id >> 1) & 0x7); + i2c_set_clientdata(client, max); max->ops = max8973_dcdc_ops; max->dev = &client->dev; @@ -507,14 +543,6 @@ static int max8973_probe(struct i2c_client *client, if (gpio_is_valid(max->enable_gpio)) max->enable_external_control = true; - if (!pdata->enable_ext_control) { - max->desc.enable_reg = MAX8973_VOUT; - max->desc.enable_mask = MAX8973_VOUT_ENABLE; - max->ops.enable = regulator_enable_regmap; - max->ops.disable = regulator_disable_regmap; - max->ops.is_enabled = regulator_is_enabled_regmap; - } - max->lru_index[0] = max->curr_vout_reg; if (gpio_is_valid(max->dvs_gpio)) { @@ -546,6 +574,50 @@ static int max8973_probe(struct i2c_client *client, pdata->reg_init_data = of_get_regulator_init_data(&client->dev, client->dev.of_node, &max->desc); + ridata = pdata->reg_init_data; + switch (max->id) { + case MAX8973: + if (!pdata->enable_ext_control) { + max->desc.enable_reg = MAX8973_VOUT; + max->desc.enable_mask = MAX8973_VOUT_ENABLE; + max->ops.enable = regulator_enable_regmap; + max->ops.disable = regulator_disable_regmap; + max->ops.is_enabled = regulator_is_enabled_regmap; + break; + } + + if (gpio_is_valid(max->enable_gpio)) { + config.ena_gpio_flags = GPIOF_OUT_INIT_LOW; + if (ridata && (ridata->constraints.always_on || + ridata->constraints.boot_on)) + config.ena_gpio_flags = GPIOF_OUT_INIT_HIGH; + config.ena_gpio = max->enable_gpio; + } + break; + + case MAX77621: + if (gpio_is_valid(max->enable_gpio)) { + ret = devm_gpio_request_one(&client->dev, + max->enable_gpio, GPIOF_OUT_INIT_HIGH, + "max8973-en-gpio"); + if (ret) { + dev_err(&client->dev, + "gpio_request for gpio %d failed: %d\n", + max->enable_gpio, ret); + return ret; + } + } + + max->desc.enable_reg = MAX8973_VOUT; + max->desc.enable_mask = MAX8973_VOUT_ENABLE; + max->ops.enable = regulator_enable_regmap; + max->ops.disable = regulator_disable_regmap; + max->ops.is_enabled = regulator_is_enabled_regmap; + break; + default: + break; + } + ret = max8973_init_dcdc(max, pdata); if (ret < 0) { dev_err(max->dev, "Max8973 Init failed, err = %d\n", ret); @@ -558,15 +630,6 @@ static int max8973_probe(struct i2c_client *client, config.of_node = client->dev.of_node; config.regmap = max->regmap; - if (gpio_is_valid(max->enable_gpio)) { - ridata = pdata->reg_init_data; - config.ena_gpio_flags = GPIOF_OUT_INIT_LOW; - if (ridata && (ridata->constraints.always_on || - ridata->constraints.boot_on)) - config.ena_gpio_flags = GPIOF_OUT_INIT_HIGH; - config.ena_gpio = max->enable_gpio; - } - /* Register the regulators */ rdev = devm_regulator_register(&client->dev, &max->desc, &config); if (IS_ERR(rdev)) { @@ -579,15 +642,16 @@ static int max8973_probe(struct i2c_client *client, } static const struct i2c_device_id max8973_id[] = { - {.name = "max8973",}, + {.name = "max8973", .driver_data = MAX8973}, + {.name = "max77621", .driver_data = MAX77621}, {}, }; - MODULE_DEVICE_TABLE(i2c, max8973_id); static struct i2c_driver max8973_i2c_driver = { .driver = { .name = "max8973", + .of_match_table = of_max8973_match_tbl, .owner = THIS_MODULE, }, .probe = max8973_probe, -- cgit v1.2.3 From 6c95ff9c1c4842b1b818fe7c6ce6753c646baf8a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 29 May 2015 11:38:41 -0500 Subject: dt-bindings: Add Marvell PXA1928 USB and HSIC PHY bindings Add PHY binding for Marvell PXA1928 SOC's USB and HSIC PHYs. Signed-off-by: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: devicetree@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/phy/pxa1928-usb-phy.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt b/Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt new file mode 100644 index 000000000000..660a13ca90b3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt @@ -0,0 +1,18 @@ +* Marvell PXA1928 USB and HSIC PHYs + +Required properties: +- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy" +- reg: base address and length of the registers +- clocks - A single clock. From common clock binding. +- #phys-cells: should be 0. From commmon phy binding. +- resets: reference to the reset controller + +Example: + + usbphy: phy@7000 { + compatible = "marvell,pxa1928-usb-phy"; + reg = <0x7000 0xe0>; + clocks = <&apmu_clocks PXA1928_CLK_USB>; + #phy-cells = <0>; + }; + -- cgit v1.2.3 From 9d062b9b416857873bb149e18fbb4230d202d0e8 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 29 May 2015 11:38:44 -0500 Subject: dt-bindings: Consolidate ChipIdea USB ci13xxx bindings Combine the ChipIdea USB binding into a single document to reduce duplication and fragmentation. This marks use of the old PHY bindings as deprecated. Future compatible bindings should use generic PHY binding. Signed-off-by: Rob Herring Cc: Ivan T. Ivanov Cc: Peter Chen Cc: Daniel Tang Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: devicetree@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/ci-hdrc-imx.txt | 35 ---------------------- .../devicetree/bindings/usb/ci-hdrc-qcom.txt | 17 ----------- .../devicetree/bindings/usb/ci-hdrc-usb2.txt | 22 +++++++++++++- .../devicetree/bindings/usb/ci-hdrc-zevio.txt | 17 ----------- 4 files changed, 21 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt delete mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt delete mode 100644 Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt deleted file mode 100644 index 38a548001e3a..000000000000 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Freescale i.MX ci13xxx usb controllers - -Required properties: -- compatible: Should be "fsl,imx27-usb" -- reg: Should contain registers location and length -- interrupts: Should contain controller interrupt -- fsl,usbphy: phandle of usb phy that connects to the port - -Recommended properies: -- phy_type: the type of the phy connected to the core. Should be one - of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this - property the PORTSC register won't be touched -- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" - -Optional properties: -- fsl,usbmisc: phandler of non-core register device, with one argument - that indicate usb controller index -- vbus-supply: regulator for vbus -- disable-over-current: disable over current detect -- external-vbus-divider: enables off-chip resistor divider for Vbus -- maximum-speed: limit the maximum connection speed to "full-speed". -- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts - -Examples: -usb@02184000 { /* USB OTG */ - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 0x04>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - disable-over-current; - external-vbus-divider; - maximum-speed = "full-speed"; - tpl-support; -}; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt deleted file mode 100644 index f2899b550939..000000000000 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt +++ /dev/null @@ -1,17 +0,0 @@ -Qualcomm CI13xxx (Chipidea) USB controllers - -Required properties: -- compatible: should contain "qcom,ci-hdrc" -- reg: offset and length of the register set in the memory map -- interrupts: interrupt-specifier for the controller interrupt. -- usb-phy: phandle for the PHY device -- dr_mode: Should be "peripheral" - -Examples: - gadget@f9a55000 { - compatible = "qcom,ci-hdrc"; - reg = <0xf9a55000 0x400>; - dr_mode = "peripheral"; - interrupts = <0 134 0>; - usb-phy = <&usbphy0>; - }; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index 27f8b1e5ee46..553e2fae3a76 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -1,15 +1,35 @@ * USB2 ChipIdea USB controller for ci13xxx Required properties: -- compatible: should be "chipidea,usb2" +- compatible: should be one of: + "fsl,imx27-usb" + "lsi,zevio-usb" + "qcom,ci-hdrc" + "chipidea,usb2" - reg: base address and length of the registers - interrupts: interrupt for the USB controller +Recommended properies: +- phy_type: the type of the phy connected to the core. Should be one + of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this + property the PORTSC register won't be touched. +- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" + +Deprecated properties: +- usb-phy: phandle for the PHY device. Use "phys" instead. +- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead. + Optional properties: - clocks: reference to the USB clock - phys: reference to the USB PHY - phy-names: should be "usb-phy" - vbus-supply: reference to the VBUS regulator +- maximum-speed: limit the maximum connection speed to "full-speed". +- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts +- fsl,usbmisc: (FSL only) phandler of non-core register device, with one + argument that indicate usb controller index +- disable-over-current: (FSL only) disable over current detect +- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus Example: diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt deleted file mode 100644 index abbcb2aea38c..000000000000 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt +++ /dev/null @@ -1,17 +0,0 @@ -* LSI Zevio USB OTG Controller - -Required properties: -- compatible: Should be "lsi,zevio-usb" -- reg: Should contain registers location and length -- interrupts: Should contain controller interrupt - -Optional properties: -- vbus-supply: regulator for vbus - -Examples: - usb0: usb@b0000000 { - reg = <0xb0000000 0x1000>; - compatible = "lsi,zevio-usb"; - interrupts = <8>; - vbus-supply = <&vbus_reg>; - }; -- cgit v1.2.3 From 2695e66f94cdb7790b2f16c154690aaa366f8417 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 05:21:51 -0300 Subject: [media] DocBook: handle enums on frontend.h In order to be sure that all enum definitions will be documented, let's parse the enum values and add xref links to them. Lots of missing references will be risen as we miss adding id's to those symbols at the documentation. Next patches will fix this. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 46 +++++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index ae9d5a0404aa..226152952f58 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -74,16 +74,26 @@ TYPES = \ $(shell perl -ne 'print "$$1 " if /^typedef\s+.*\s+(\S+)\;/' $(srctree)/include/uapi/linux/dvb/frontend.h) ENUMS = \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/videodev2.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/audio.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/ca.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/dmx.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/frontend.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/net.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/dvb/video.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/media.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/v4l2-mediabus.h) \ - $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/v4l2-subdev.h) + $(shell perl -ne 'print "$$1 " if /^enum\s+([^\s]+)\s+/' \ + $(srctree)/include/uapi/linux/videodev2.h \ + $(srctree)/include/uapi/linux/dvb/audio.h \ + $(srctree)/include/uapi/linux/dvb/ca.h \ + $(srctree)/include/uapi/linux/dvb/dmx.h \ + $(srctree)/include/uapi/linux/dvb/frontend.h \ + $(srctree)/include/uapi/linux/dvb/net.h \ + $(srctree)/include/uapi/linux/dvb/video.h \ + $(srctree)/include/uapi/linux/media.h \ + $(srctree)/include/uapi/linux/v4l2-mediabus.h \ + $(srctree)/include/uapi/linux/v4l2-subdev.h) + +ENUM_DEFS = \ + $(shell perl -e 'while (<>) { if ($$enum) {print "$$1\n" if (/\s*([A-Z]\S+)\b/); } $$enum = 0 if ($enum && /^\}/); $$enum = 1 if(/^\s*enum\s/); }' \ + $(srctree)/include/uapi/linux/dvb/audio.h \ + $(srctree)/include/uapi/linux/dvb/ca.h \ + $(srctree)/include/uapi/linux/dvb/dmx.h \ + $(srctree)/include/uapi/linux/dvb/frontend.h \ + $(srctree)/include/uapi/linux/dvb/net.h \ + $(srctree)/include/uapi/linux/dvb/video.h) STRUCTS = \ $(shell perl -ne 'print "$$1 " if /^struct\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/videodev2.h) \ @@ -252,9 +262,14 @@ $(MEDIA_OBJ_DIR)/frontend.h.xml: $(srctree)/include/uapi/linux/dvb/frontend.h $( @( \ echo "") > $@ @( \ + for ident in $(ENUM_DEFS) ; do \ + entity=`echo $$ident | tr _ -` ; \ + r="$$r s/([^\w\-])$$ident([^\w\-])/\1\&$$entity\;\2/g;";\ + done; \ expand --tabs=8 < $< | \ sed $(ESCAPE) $(DVB_DOCUMENTED) | \ - sed 's/i\.e\./&ie;/') >> $@ + sed 's/i\.e\./&ie;/' | \ + perl -ne "$$r print $$_;") >> $@ @( \ echo "") >> $@ @@ -331,6 +346,15 @@ $(MEDIA_OBJ_DIR)/media-entities.tmpl: $(MEDIA_OBJ_DIR)/v4l2.xml "linkend='$$entity'>$$ident\">" >>$@ ; \ done) @( \ + echo -e "\n") >>$@ + @( \ + for ident in $(ENUM_DEFS) ; do \ + entity=`echo $$ident | tr _ -` ; \ + echo "$$ident\">" \ + >>$@ ; \ + done) + @( \ echo -e "\n") >>$@ @( \ for ident in $(STRUCTS) ; do \ -- cgit v1.2.3 From 85cb78b5647e478d22f3f40199dd739ca3e74f05 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 05:39:03 -0300 Subject: [media] DocBook: Add entry IDs for enum fe_caps enum fe_caps is documented at FE_GET_INFO ioctl. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-get-info.xml | 62 ++++++++++++------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-get-info.xml b/Documentation/DocBook/media/dvb/fe-get-info.xml index 0e0245e45d26..ed0eeb29dd65 100644 --- a/Documentation/DocBook/media/dvb/fe-get-info.xml +++ b/Documentation/DocBook/media/dvb/fe-get-info.xml @@ -135,128 +135,128 @@ driver is not compatible with this specification the ioctl returns an error.
- FE_IS_STUPID + FE_IS_STUPID There's something wrong at the frontend, and it can't report its capabilities - FE_CAN_INVERSION_AUTO + FE_CAN_INVERSION_AUTO The frontend is capable of auto-detecting inversion - FE_CAN_FEC_1_2 + FE_CAN_FEC_1_2 The frontend supports FEC 1/2 - FE_CAN_FEC_2_3 + FE_CAN_FEC_2_3 The frontend supports FEC 2/3 - FE_CAN_FEC_3_4 + FE_CAN_FEC_3_4 The frontend supports FEC 3/4 - FE_CAN_FEC_4_5 + FE_CAN_FEC_4_5 The frontend supports FEC 4/5 - FE_CAN_FEC_5_6 + FE_CAN_FEC_5_6 The frontend supports FEC 5/6 - FE_CAN_FEC_6_7 + FE_CAN_FEC_6_7 The frontend supports FEC 6/7 - FE_CAN_FEC_7_8 + FE_CAN_FEC_7_8 The frontend supports FEC 7/8 - FE_CAN_FEC_8_9 + FE_CAN_FEC_8_9 The frontend supports FEC 8/9 - FE_CAN_FEC_AUTO + FE_CAN_FEC_AUTO The frontend can autodetect FEC. - FE_CAN_QPSK + FE_CAN_QPSK The frontend supports QPSK modulation - FE_CAN_QAM_16 + FE_CAN_QAM_16 The frontend supports 16-QAM modulation - FE_CAN_QAM_32 + FE_CAN_QAM_32 The frontend supports 32-QAM modulation - FE_CAN_QAM_64 + FE_CAN_QAM_64 The frontend supports 64-QAM modulation - FE_CAN_QAM_128 + FE_CAN_QAM_128 The frontend supports 128-QAM modulation - FE_CAN_QAM_256 + FE_CAN_QAM_256 The frontend supports 256-QAM modulation - FE_CAN_QAM_AUTO + FE_CAN_QAM_AUTO The frontend can autodetect modulation - FE_CAN_TRANSMISSION_MODE_AUTO + FE_CAN_TRANSMISSION_MODE_AUTO The frontend can autodetect the transmission mode - FE_CAN_BANDWIDTH_AUTO + FE_CAN_BANDWIDTH_AUTO The frontend can autodetect the bandwidth - FE_CAN_GUARD_INTERVAL_AUTO + FE_CAN_GUARD_INTERVAL_AUTO The frontend can autodetect the guard interval - FE_CAN_HIERARCHY_AUTO + FE_CAN_HIERARCHY_AUTO The frontend can autodetect hierarch - FE_CAN_8VSB + FE_CAN_8VSB The frontend supports 8-VSB modulation - FE_CAN_16VSB + FE_CAN_16VSB The frontend supports 16-VSB modulation - FE_HAS_EXTENDED_CAPS + FE_HAS_EXTENDED_CAPS Currently, unused - FE_CAN_MULTISTREAM + FE_CAN_MULTISTREAM The frontend supports multistream filtering - FE_CAN_TURBO_FEC + FE_CAN_TURBO_FEC The frontend supports turbo FEC modulation - FE_CAN_2G_MODULATION + FE_CAN_2G_MODULATION The frontend supports "2nd generation modulation" (DVB-S2/T2)> - FE_NEEDS_BENDING + FE_NEEDS_BENDING Not supported anymore, don't use it - FE_CAN_RECOVER + FE_CAN_RECOVER The frontend can recover from a cable unplug automatically - FE_CAN_MUTE_TS + FE_CAN_MUTE_TS The frontend can stop spurious TS data output -- cgit v1.2.3 From 764368ceb84ca8ba2c549e1158dbed3a53913d85 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 05:49:51 -0300 Subject: [media] DocBook: add entry IDs for enum fe_sec_mini_cmd enum fe_sec_mini_cmd is documented together with FE_DISEQC_SEND_BURST. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml index 91dd2078a0f4..9f6a68f32de3 100644 --- a/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml +++ b/Documentation/DocBook/media/dvb/fe-diseqc-send-burst.xml @@ -73,11 +73,11 @@ - SEC_MINI_A + SEC_MINI_A Sends a mini-DiSEqC 22kHz '0' Tone Burst to select satellite-A - SEC_MINI_B + SEC_MINI_B Sends a mini-DiSEqC 22kHz '1' Data Burst to select satellite-B -- cgit v1.2.3 From e7852571a4926371b4cbfeaccb82b307518f2c7c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:09:57 -0300 Subject: [media] DocBook: add entry IDs for enum fe_status enum fe_status is documented together with FE_READ_STATUS. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-read-status.xml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-read-status.xml b/Documentation/DocBook/media/dvb/fe-read-status.xml index 3e4c794ceac3..bc0dc2a55f19 100644 --- a/Documentation/DocBook/media/dvb/fe-read-status.xml +++ b/Documentation/DocBook/media/dvb/fe-read-status.xml @@ -78,25 +78,25 @@ pointer to an integer where the status will be written. - FE_HAS_SIGNAL + FE_HAS_SIGNAL The frontend has found something above the noise level - FE_HAS_CARRIER + FE_HAS_CARRIER The frontend has found a DVB signal - FE_HAS_VITERBI + FE_HAS_VITERBI The frontend FEC inner coding (Viterbi, LDPC or other inner code) is stable - FE_HAS_SYNC + FE_HAS_SYNC Synchronization bytes was found - FE_HAS_LOCK + FE_HAS_LOCK The DVB were locked and everything is working - FE_TIMEDOUT + FE_TIMEDOUT no lock within the last about 2 seconds - FE_REINIT + FE_REINIT The frontend was reinitialized, application is recommended to reset DiSEqC, tone and parameters -- cgit v1.2.3 From 81d6f2f8b8843f77c458b4bcfde8f77dd1ee0740 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:10:38 -0300 Subject: [media] DocBook: add entry IDs for enum fe_sec_tone_mode enum fe_sec_tone_mode is documented together with FE_SET_TONE. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-set-tone.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-set-tone.xml b/Documentation/DocBook/media/dvb/fe-set-tone.xml index 12cd4dd3a6ef..62d44e4ccc39 100644 --- a/Documentation/DocBook/media/dvb/fe-set-tone.xml +++ b/Documentation/DocBook/media/dvb/fe-set-tone.xml @@ -76,10 +76,10 @@ - SEC_TONE_ON + SEC_TONE_ON Sends a 22kHz tone burst to the antenna - SEC_TONE_OFF + SEC_TONE_OFF Don't send a 22kHz tone to the antenna (except if the FE_DISEQC_* ioctls are called) -- cgit v1.2.3 From 8de4d9ecb7c9c03c867e60d6f4bb4e6f17f87af1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:12:28 -0300 Subject: [media] Docbook: add entry IDs for enum fe_sec_voltage enum fe_sec_voltage is documented together with FE_SET_VOLTAGE. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/fe-set-voltage.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/fe-set-voltage.xml b/Documentation/DocBook/media/dvb/fe-set-voltage.xml index 73710f89ff1e..053c4cb0f540 100644 --- a/Documentation/DocBook/media/dvb/fe-set-voltage.xml +++ b/Documentation/DocBook/media/dvb/fe-set-voltage.xml @@ -80,13 +80,13 @@ - SEC_VOLTAGE_13 + SEC_VOLTAGE_13 Set DC voltage level to 13V - SEC_VOLTAGE_18 + SEC_VOLTAGE_18 Set DC voltage level to 18V - SEC_VOLTAGE_OFF + SEC_VOLTAGE_OFF Don't send any voltage to the antenna -- cgit v1.2.3 From 00c91dfd7b69cd0682fce937ced62ae8689ecc5c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:20:18 -0300 Subject: [media] DocBook: Add entry IDs for the enums defined at dvbproperty.xml There are lots of enums that are defined at dvbproperty. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 120 ++++++++++++------------ 1 file changed, 60 insertions(+), 60 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 28e306ee5827..816d5ac56164 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -208,46 +208,46 @@ get/set up to 64 properties. The actual meaning of each property is described on - QPSK + QPSK QPSK modulation - QAM_16 + QAM_16 16-QAM modulation - QAM_32 + QAM_32 32-QAM modulation - QAM_64 + QAM_64 64-QAM modulation - QAM_128 + QAM_128 128-QAM modulation - QAM_256 + QAM_256 256-QAM modulation - QAM_AUTO + QAM_AUTO Autodetect QAM modulation - VSB_8 + VSB_8 8-VSB modulation - VSB_16 + VSB_16 16-VSB modulation - PSK_8 + PSK_8 8-PSK modulation - APSK_16 + APSK_16 16-APSK modulation - APSK_32 + APSK_32 32-APSK modulation - DQPSK + DQPSK DQPSK modulation - QAM_4_NR + QAM_4_NR 4-QAM-NR modulation @@ -309,13 +309,13 @@ get/set up to 64 properties. The actual meaning of each property is described on - INVERSION_OFF + INVERSION_OFF Don't do spectral band inversion. - INVERSION_ON + INVERSION_ON Do spectral band inversion. - INVERSION_AUTO + INVERSION_AUTO Autodetect spectral band inversion. @@ -351,48 +351,48 @@ get/set up to 64 properties. The actual meaning of each property is described on - TRANSMISSION_MODE_AUTO + TRANSMISSION_MODE_AUTO Autodetect transmission mode. The hardware will try to find the correct FFT-size (if capable) to fill in the missing parameters. - FEC_NONE + FEC_NONE No Forward Error Correction Code - FEC_AUTO + FEC_AUTO Autodetect Error Correction Code - FEC_1_2 + FEC_1_2 Forward Error Correction Code 1/2 - FEC_2_3 + FEC_2_3 Forward Error Correction Code 2/3 - FEC_3_4 + FEC_3_4 Forward Error Correction Code 3/4 - FEC_4_5 + FEC_4_5 Forward Error Correction Code 4/5 - FEC_5_6 + FEC_5_6 Forward Error Correction Code 5/6 - FEC_6_7 + FEC_6_7 Forward Error Correction Code 6/7 - FEC_7_8 + FEC_7_8 Forward Error Correction Code 7/8 - FEC_8_9 + FEC_8_9 Forward Error Correction Code 8/9 - FEC_9_10 + FEC_9_10 Forward Error Correction Code 9/10 - FEC_2_5 + FEC_2_5 Forward Error Correction Code 2/5 - FEC_3_5 + FEC_3_5 Forward Error Correction Code 3/5 @@ -879,37 +879,37 @@ typedef enum atscmh_sccc_code_mode { - GUARD_INTERVAL_AUTO + GUARD_INTERVAL_AUTO Autodetect the guard interval - GUARD_INTERVAL_1_128 + GUARD_INTERVAL_1_128 Guard interval 1/128 - GUARD_INTERVAL_1_32 + GUARD_INTERVAL_1_32 Guard interval 1/32 - GUARD_INTERVAL_1_16 + GUARD_INTERVAL_1_16 Guard interval 1/16 - GUARD_INTERVAL_1_8 + GUARD_INTERVAL_1_8 Guard interval 1/8 - GUARD_INTERVAL_1_4 + GUARD_INTERVAL_1_4 Guard interval 1/4 - GUARD_INTERVAL_19_128 + GUARD_INTERVAL_19_128 Guard interval 19/128 - GUARD_INTERVAL_19_256 + GUARD_INTERVAL_19_256 Guard interval 19/256 - GUARD_INTERVAL_PN420 + GUARD_INTERVAL_PN420 PN length 420 (1/4) - GUARD_INTERVAL_PN595 + GUARD_INTERVAL_PN595 PN length 595 (1/6) - GUARD_INTERVAL_PN945 + GUARD_INTERVAL_PN945 PN length 945 (1/9) @@ -946,33 +946,33 @@ typedef enum atscmh_sccc_code_mode { - TRANSMISSION_MODE_AUTO + TRANSMISSION_MODE_AUTO Autodetect transmission mode. The hardware will try to find the correct FFT-size (if capable) to fill in the missing parameters. - TRANSMISSION_MODE_1K + TRANSMISSION_MODE_1K Transmission mode 1K - TRANSMISSION_MODE_2K + TRANSMISSION_MODE_2K Transmission mode 2K - TRANSMISSION_MODE_8K + TRANSMISSION_MODE_8K Transmission mode 8K - TRANSMISSION_MODE_4K + TRANSMISSION_MODE_4K Transmission mode 4K - TRANSMISSION_MODE_16K + TRANSMISSION_MODE_16K Transmission mode 16K - TRANSMISSION_MODE_32K + TRANSMISSION_MODE_32K Transmission mode 32K - TRANSMISSION_MODE_C1 + TRANSMISSION_MODE_C1 Single Carrier (C=1) transmission mode (DTMB) - TRANSMISSION_MODE_C3780 + TRANSMISSION_MODE_C3780 Multi Carrier (C=3780) transmission mode (DTMB) @@ -1012,19 +1012,19 @@ typedef enum atscmh_sccc_code_mode { - HIERARCHY_NONE + HIERARCHY_NONE No hierarchy - HIERARCHY_AUTO + HIERARCHY_AUTO Autodetect hierarchy (if supported) - HIERARCHY_1 + HIERARCHY_1 Hierarchy 1 - HIERARCHY_2 + HIERARCHY_2 Hierarchy 2 - HIERARCHY_4 + HIERARCHY_4 Hierarchy 4 @@ -1117,10 +1117,10 @@ enum fe_interleaving { and uvalue is for unsigned values (counters, relative scale)scale - Scale for the value. It can be: - FE_SCALE_NOT_AVAILABLE - The parameter is supported by the frontend, but it was not possible to collect it (could be a transitory or permanent condition) - FE_SCALE_DECIBEL - parameter is a signed value, measured in 1/1000 dB - FE_SCALE_RELATIVE - parameter is a unsigned value, where 0 means 0% and 65535 means 100%. - FE_SCALE_COUNTER - parameter is a unsigned value that counts the occurrence of an event, like bit error, block error, or lapsed time. + FE_SCALE_NOT_AVAILABLE - The parameter is supported by the frontend, but it was not possible to collect it (could be a transitory or permanent condition) + FE_SCALE_DECIBEL - parameter is a signed value, measured in 1/1000 dB + FE_SCALE_RELATIVE - parameter is a unsigned value, where 0 means 0% and 65535 means 100%. + FE_SCALE_COUNTER - parameter is a unsigned value that counts the occurrence of an event, like bit error, block error, or lapsed time. -- cgit v1.2.3 From 3d6d213776f3d22ddbf99c0ae16c4d397e32d434 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:35:20 -0300 Subject: [media] DocBook: Better document DTMB time interleaving The DTMB time interleaving was not properly documented. Add a documentation for it. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 40 +++++++++++++++++++------ 1 file changed, 31 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 816d5ac56164..33f2313aca07 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -1068,15 +1068,37 @@ typedef enum atscmh_sccc_code_mode {
<constant>DTV_INTERLEAVING</constant> - Interleaving mode - -enum fe_interleaving { - INTERLEAVING_NONE, - INTERLEAVING_AUTO, - INTERLEAVING_240, - INTERLEAVING_720, -}; - + +Time interleaving to be used. Currently, used only on DTMB. + +
+ enum fe_interleaving + + &cs-def; + + + ID + Description + + + + + INTERLEAVING_NONE + No interleaving. + + INTERLEAVING_AUTO + Auto-detect interleaving. + + INTERLEAVING_240 + Interleaving of 240 symbols. + + INTERLEAVING_720 + Interleaving of 720 symbols. + + + +
+
<constant>DTV_LNA</constant> -- cgit v1.2.3 From 6a5a402599a4c5ed595567a39183b6c5bd5ecd2c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:37:20 -0300 Subject: [media] DocBook: add IDs for enum fe_bandwidth enum fe_bandwidth is documented at the frontend legacy xml file. Add xrefs for each entry there. This makes the hyperlinks at frontend.h to go directly to the right documentation. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend_legacy_api.xml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index 3005cec58eb0..8523caf91a2c 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -75,25 +75,25 @@ supported via the new FE_GET_PROPERTY/FE_GET_SET - BANDWIDTH_AUTO + BANDWIDTH_AUTO Autodetect bandwidth (if supported) - BANDWIDTH_1_712_MHZ + BANDWIDTH_1_712_MHZ 1.712 MHz - BANDWIDTH_5_MHZ + BANDWIDTH_5_MHZ 5 MHz - BANDWIDTH_6_MHZ + BANDWIDTH_6_MHZ 6 MHz - BANDWIDTH_7_MHZ + BANDWIDTH_7_MHZ 7 MHz - BANDWIDTH_8_MHZ + BANDWIDTH_8_MHZ 8 MHz - BANDWIDTH_10_MHZ + BANDWIDTH_10_MHZ 10 MHz -- cgit v1.2.3 From 2acf9146db2e937b34da62e593ed03e2bebf86f4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 06:54:37 -0300 Subject: [media] DocBook: remove a wrong cut-and-paste data By cut-and-paste mistake, TRANSMISSION_MODE_AUTO were documented twice, one at the wrong place. Remove the wrong one. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 5 ----- 1 file changed, 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 33f2313aca07..7e5147e6c2f2 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -351,11 +351,6 @@ get/set up to 64 properties. The actual meaning of each property is described on - TRANSMISSION_MODE_AUTO - Autodetect transmission mode. The hardware will try to find - the correct FFT-size (if capable) to fill in the missing - parameters. - FEC_NONE No Forward Error Correction Code -- cgit v1.2.3 From b69d5f265b13c445a7294d68e0315d4b3c9234e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 07:14:14 -0300 Subject: [media] DocBook: add placeholders for ATSC M/H properties The ATSC M/H specific properties are not properly documented. This became crearer when converting the existing data into tables and adding cross references. For now, just add placeholders, as a further investigation about the meaning of each parameter is required. Cc: Michael Ira Krufky Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 200 +++++++++++++++--------- 1 file changed, 129 insertions(+), 71 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 7e5147e6c2f2..275788875655 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -726,114 +726,172 @@ typedef enum fe_delivery_system {
<constant>DTV_ATSCMH_RS_FRAME_MODE</constant> - RS frame mode. + Reed Solomon (RS) frame mode. Possible values are: - - -typedef enum atscmh_rs_frame_mode { - ATSCMH_RSFRAME_PRI_ONLY = 0, - ATSCMH_RSFRAME_PRI_SEC = 1, -} atscmh_rs_frame_mode_t; - - + + enum atscmh_rs_frame_mode + + &cs-def; + + + ID + Description + + + + + ATSCMH_RSFRAME_PRI_ONLY + to be documented. + + ATSCMH_RSFRAME_PRI_SEC + to be documented. + + + +
<constant>DTV_ATSCMH_RS_FRAME_ENSEMBLE</constant> RS frame ensemble. Possible values are: - - -typedef enum atscmh_rs_frame_ensemble { - ATSCMH_RSFRAME_ENS_PRI = 0, - ATSCMH_RSFRAME_ENS_SEC = 1, -} atscmh_rs_frame_ensemble_t; - - + + enum atscmh_rs_frame_ensemble + + &cs-def; + + + ID + Description + + + + + ATSCMH_RSFRAME_ENS_PRI + to be documented. + + AATSCMH_RSFRAME_PRI_SEC + to be documented. + + AATSCMH_RSFRAME_RES + to be documented. + + + +
<constant>DTV_ATSCMH_RS_CODE_MODE_PRI</constant> RS code mode (primary). Possible values are: - - -typedef enum atscmh_rs_code_mode { - ATSCMH_RSCODE_211_187 = 0, - ATSCMH_RSCODE_223_187 = 1, - ATSCMH_RSCODE_235_187 = 2, -} atscmh_rs_code_mode_t; - - + + enum atscmh_rs_code_mode + + &cs-def; + + + ID + Description + + + + + ATSCMH_RSCODE_211_187 + to be documented. + + ATSCMH_RSCODE_223_187 + to be documented. + + ATSCMH_RSCODE_235_187 + to be documented. + + ATSCMH_RSCODE_RES + to be documented. + + + +
<constant>DTV_ATSCMH_RS_CODE_MODE_SEC</constant> RS code mode (secondary). - Possible values are: - -typedef enum atscmh_rs_code_mode { - ATSCMH_RSCODE_211_187 = 0, - ATSCMH_RSCODE_223_187 = 1, - ATSCMH_RSCODE_235_187 = 2, -} atscmh_rs_code_mode_t; - + Possible values are the same as documented on + &atscmh-rs-code-mode;:
<constant>DTV_ATSCMH_SCCC_BLOCK_MODE</constant> Series Concatenated Convolutional Code Block Mode. Possible values are: - - -typedef enum atscmh_sccc_block_mode { - ATSCMH_SCCC_BLK_SEP = 0, - ATSCMH_SCCC_BLK_COMB = 1, -} atscmh_sccc_block_mode_t; - - + + enum atscmh_scc_block_mode + + &cs-def; + + + ID + Description + + + + + ATSCMH_SCCC_BLK_SEP + to be documented. + + ATSCMH_SCCC_BLK_COMB + to be documented. + + ATSCMH_SCCC_BLK_RES + to be documented. + + + +
<constant>DTV_ATSCMH_SCCC_CODE_MODE_A</constant> Series Concatenated Convolutional Code Rate. Possible values are: - - -typedef enum atscmh_sccc_code_mode { - ATSCMH_SCCC_CODE_HLF = 0, - ATSCMH_SCCC_CODE_QTR = 1, -} atscmh_sccc_code_mode_t; - - + + enum atscmh_sccc_code_mode + + &cs-def; + + + ID + Description + + + + + ATSCMH_SCCC_CODE_HLF + to be documented. + + ATSCMH_SCCC_CODE_QTR + to be documented. + + ATSCMH_SCCC_CODE_RES + to be documented. + + + +
<constant>DTV_ATSCMH_SCCC_CODE_MODE_B</constant> Series Concatenated Convolutional Code Rate. - Possible values are: - -typedef enum atscmh_sccc_code_mode { - ATSCMH_SCCC_CODE_HLF = 0, - ATSCMH_SCCC_CODE_QTR = 1, -} atscmh_sccc_code_mode_t; - + Possible values are the same as documented on + &atscmh-sccc-code-mode;.
<constant>DTV_ATSCMH_SCCC_CODE_MODE_C</constant> Series Concatenated Convolutional Code Rate. - Possible values are: - -typedef enum atscmh_sccc_code_mode { - ATSCMH_SCCC_CODE_HLF = 0, - ATSCMH_SCCC_CODE_QTR = 1, -} atscmh_sccc_code_mode_t; - + Possible values are the same as documented on + &atscmh-sccc-code-mode;.
<constant>DTV_ATSCMH_SCCC_CODE_MODE_D</constant> Series Concatenated Convolutional Code Rate. - Possible values are: - -typedef enum atscmh_sccc_code_mode { - ATSCMH_SCCC_CODE_HLF = 0, - ATSCMH_SCCC_CODE_QTR = 1, -} atscmh_sccc_code_mode_t; - + Possible values are the same as documented on + &atscmh-sccc-code-mode;.
-- cgit v1.2.3 From 8092cd7fc6b2153c41b24b4ec1d1342d14d12e1f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 10:59:32 -0300 Subject: [media] DocBook: Add documentation for ATSC M/H properties Those data were retrieved by looking at A/153: ATSC Mobile DTV Standard and guessing what makes more sense to each field. Cc: Michael Ira Krufky Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 39 ++++++++++++++----------- 1 file changed, 22 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 275788875655..8d57f0c9b6aa 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -741,10 +741,13 @@ typedef enum fe_delivery_system { ATSCMH_RSFRAME_PRI_ONLY - to be documented. + Single Frame: There is only a primary RS Frame for all + Group Regions. ATSCMH_RSFRAME_PRI_SEC - to be documented. + Dual Frame: There are two separate RS Frames: Primary RS + Frame for Group Region A and B and Secondary RS Frame for Group + Region C and D. @@ -752,7 +755,7 @@ typedef enum fe_delivery_system {
<constant>DTV_ATSCMH_RS_FRAME_ENSEMBLE</constant> - RS frame ensemble. + Reed Solomon(RS) frame ensemble. Possible values are: enum atscmh_rs_frame_ensemble @@ -767,13 +770,13 @@ typedef enum fe_delivery_system { ATSCMH_RSFRAME_ENS_PRI - to be documented. + Primary Ensemble. AATSCMH_RSFRAME_PRI_SEC - to be documented. + Secondary Ensemble. AATSCMH_RSFRAME_RES - to be documented. + Reserved. Shouldn't be used. @@ -781,7 +784,7 @@ typedef enum fe_delivery_system {
<constant>DTV_ATSCMH_RS_CODE_MODE_PRI</constant> - RS code mode (primary). + Reed Solomon (RS) code mode (primary). Possible values are:
enum atscmh_rs_code_mode @@ -796,16 +799,16 @@ typedef enum fe_delivery_system { ATSCMH_RSCODE_211_187 - to be documented. + Reed Solomon code (211,187). ATSCMH_RSCODE_223_187 - to be documented. + Reed Solomon code (223,187). ATSCMH_RSCODE_235_187 - to be documented. + Reed Solomon code (235,187). ATSCMH_RSCODE_RES - to be documented. + Reserved. Shouldn't be used. @@ -813,7 +816,7 @@ typedef enum fe_delivery_system {
<constant>DTV_ATSCMH_RS_CODE_MODE_SEC</constant> - RS code mode (secondary). + Reed Solomon (RS) code mode (secondary). Possible values are the same as documented on &atscmh-rs-code-mode;:
@@ -834,13 +837,15 @@ typedef enum fe_delivery_system { ATSCMH_SCCC_BLK_SEP - to be documented. + Separate SCCC: the SCCC outer code mode shall be set independently + for each Group Region (A, B, C, D) ATSCMH_SCCC_BLK_COMB - to be documented. + Combined SCCC: all four Regions shall have the same SCCC outer + code mode. ATSCMH_SCCC_BLK_RES - to be documented. + Reserved. Shouldn't be used. @@ -863,10 +868,10 @@ typedef enum fe_delivery_system { ATSCMH_SCCC_CODE_HLF - to be documented. + The outer code rate of a SCCC Block is 1/2 rate. ATSCMH_SCCC_CODE_QTR - to be documented. + The outer code rate of a SCCC Block is 1/4 rate. ATSCMH_SCCC_CODE_RES to be documented. -- cgit v1.2.3 From 448bac10318977e2c41548d7e6a1d87f9d48784d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 11:18:16 -0300 Subject: [media] DocBook: document DVB-S2 pilot in a table Putting it into a table allows to comment each possible values, with makes more clear what field means. Also, it allows to do cross-references with the frontend.h. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 31 +++++++++++++++++++------ include/uapi/linux/dvb/frontend.h | 6 +++-- 2 files changed, 28 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index 8d57f0c9b6aa..e31d9457671f 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -417,13 +417,30 @@ get/set up to 64 properties. The actual meaning of each property is described on Sets DVB-S2 pilot
fe_pilot type - -typedef enum fe_pilot { - PILOT_ON, - PILOT_OFF, - PILOT_AUTO, -} fe_pilot_t; - +
+ enum fe_pilot + + &cs-def; + + + ID + Description + + + + + PILOT_ON + Pilot tones enabled + + PILOT_OFF + Pilot tones disabled + + PILOT_AUTO + Autodetect pilot tones + + + +
diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 3a7ff9002654..bb222eb04627 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -399,11 +399,13 @@ struct dvb_frontend_event { #define DTV_MAX_COMMAND DTV_STAT_TOTAL_BLOCK_COUNT -typedef enum fe_pilot { +enum fe_pilot { PILOT_ON, PILOT_OFF, PILOT_AUTO, -} fe_pilot_t; +}; + +typedef enum fe_pilot fe_pilot_t; typedef enum fe_rolloff { ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */ -- cgit v1.2.3 From ff50574c1756fb54dd14a81296dff95c76f09c10 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 11:34:12 -0300 Subject: [media] DocBook: Remove duplicated documentation for SEC_VOLTAGE_* The table were documented at the legacy ioctl call. Move it to the DVBv5 ioctl, and add a cross ref link on the legacy section. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 31 +++++++++++++++++----- Documentation/DocBook/media/dvb/fe-set-voltage.xml | 30 +-------------------- 2 files changed, 26 insertions(+), 35 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index e31d9457671f..e1d1e2469029 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -401,12 +401,31 @@ get/set up to 64 properties. The actual meaning of each property is described on the polarzation (horizontal/vertical). When using DiSEqC epuipment this voltage has to be switched consistently to the DiSEqC commands as described in the DiSEqC spec. - - typedef enum fe_sec_voltage { - SEC_VOLTAGE_13, - SEC_VOLTAGE_18 - } fe_sec_voltage_t; - + + + enum fe_sec_voltage + + &cs-def; + + + ID + Description + + + + + SEC_VOLTAGE_13 + Set DC voltage level to 13V + + SEC_VOLTAGE_18 + Set DC voltage level to 18V + + SEC_VOLTAGE_OFF + Don't send any voltage to the antenna + + + +
<constant>DTV_TONE</constant> diff --git a/Documentation/DocBook/media/dvb/fe-set-voltage.xml b/Documentation/DocBook/media/dvb/fe-set-voltage.xml index 053c4cb0f540..c89a6f79b5af 100644 --- a/Documentation/DocBook/media/dvb/fe-set-voltage.xml +++ b/Documentation/DocBook/media/dvb/fe-set-voltage.xml @@ -39,6 +39,7 @@ voltage pointer to &fe-sec-voltage; + Valid values are described at &fe-sec-voltage;. @@ -65,33 +66,4 @@ &return-value-dvb; - -enum fe_sec_voltage - - - enum fe_status - - &cs-def; - - - ID - Description - - - - - SEC_VOLTAGE_13 - Set DC voltage level to 13V - - SEC_VOLTAGE_18 - Set DC voltage level to 18V - - SEC_VOLTAGE_OFF - Don't send any voltage to the antenna - - - -
- - -- cgit v1.2.3 From b35f6ba97882ef4e00c1faae1d66232f7314fe91 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 11:59:27 -0300 Subject: [media] DocBook: better document the DVB-S2 rolloff factor Instead of using a program listing, use a table and make clearer what each define means. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 35 +++++++++++++++++++------ include/uapi/linux/dvb/frontend.h | 6 +++-- 2 files changed, 31 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index e1d1e2469029..c0aa1ad9eccf 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -468,14 +468,33 @@ get/set up to 64 properties. The actual meaning of each property is described on
fe_rolloff type - -typedef enum fe_rolloff { - ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */ - ROLLOFF_20, - ROLLOFF_25, - ROLLOFF_AUTO, -} fe_rolloff_t; - + + enum fe_rolloff + + &cs-def; + + + ID + Description + + + + + ROLLOFF_35 + Roloff factor: α=35% + + ROLLOFF_20 + Roloff factor: α=20% + + ROLLOFF_25 + Roloff factor: α=25% + + ROLLOFF_AUTO + Auto-detect the roloff factor. + + + +
diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index bb222eb04627..cdd9e2fc030d 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -407,12 +407,14 @@ enum fe_pilot { typedef enum fe_pilot fe_pilot_t; -typedef enum fe_rolloff { +enum fe_rolloff { ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */ ROLLOFF_20, ROLLOFF_25, ROLLOFF_AUTO, -} fe_rolloff_t; +}; + +typedef enum fe_rolloff fe_rolloff_t; typedef enum fe_delivery_system { SYS_UNDEFINED, -- cgit v1.2.3 From d21ddba826d8704525fa637e69cf90b8e034d94a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 14:21:09 -0300 Subject: [media] DocBook: properly document the delivery systems Use a table for the delivery systems. The table is organized by the type (cable, satellite, terrestrial) and shows what standards are not fully implemented. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/dvbproperty.xml | 99 +++++++++++++++++++------ include/uapi/linux/dvb/frontend.h | 6 +- 2 files changed, 79 insertions(+), 26 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/dvbproperty.xml b/Documentation/DocBook/media/dvb/dvbproperty.xml index c0aa1ad9eccf..08227d4e9150 100644 --- a/Documentation/DocBook/media/dvb/dvbproperty.xml +++ b/Documentation/DocBook/media/dvb/dvbproperty.xml @@ -515,31 +515,82 @@ get/set up to 64 properties. The actual meaning of each property is described on
fe_delivery_system type Possible values: - -typedef enum fe_delivery_system { - SYS_UNDEFINED, - SYS_DVBC_ANNEX_A, - SYS_DVBC_ANNEX_B, - SYS_DVBT, - SYS_DSS, - SYS_DVBS, - SYS_DVBS2, - SYS_DVBH, - SYS_ISDBT, - SYS_ISDBS, - SYS_ISDBC, - SYS_ATSC, - SYS_ATSCMH, - SYS_DTMB, - SYS_CMMB, - SYS_DAB, - SYS_DVBT2, - SYS_TURBO, - SYS_DVBC_ANNEX_C, -} fe_delivery_system_t; - -
+ + enum fe_delivery_system + + &cs-def; + + + ID + Description + + + + + SYS_UNDEFINED + Undefined standard. Generally, indicates an error + + SYS_DVBC_ANNEX_A + Cable TV: DVB-C following ITU-T J.83 Annex A spec + + SYS_DVBC_ANNEX_B + Cable TV: DVB-C following ITU-T J.83 Annex B spec (ClearQAM) + + SYS_DVBC_ANNEX_C + Cable TV: DVB-C following ITU-T J.83 Annex C spec + + SYS_ISDBC + Cable TV: ISDB-C (no drivers yet) + + SYS_DVBT + Terrestral TV: DVB-T + + SYS_DVBT2 + Terrestral TV: DVB-T2 + + SYS_ISDBT + Terrestral TV: ISDB-T + + SYS_ATSC + Terrestral TV: ATSC + + SYS_ATSCMH + Terrestral TV (mobile): ATSC-M/H + + SYS_DTMB + Terrestrial TV: DTMB + + SYS_DVBS + Satellite TV: DVB-S + + SYS_DVBS2 + Satellite TV: DVB-S2 + + SYS_TURBO + Satellite TV: DVB-S Turbo + + SYS_ISDBS + Satellite TV: ISDB-S + + SYS_DAB + Digital audio: DAB (not fully supported) + + SYS_DSS + Satellite TV:"DSS (not fully supported) + + SYS_CMMB + Terrestral TV (mobile):CMMB (not fully supported) + + SYS_DVBH + Terrestral TV (mobile): DVB-H (standard deprecated) + + + +
+ + +
<constant>DTV_ISDBT_PARTIAL_RECEPTION</constant> diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index cdd9e2fc030d..66499f238204 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -416,7 +416,7 @@ enum fe_rolloff { typedef enum fe_rolloff fe_rolloff_t; -typedef enum fe_delivery_system { +enum fe_delivery_system { SYS_UNDEFINED, SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_B, @@ -436,7 +436,9 @@ typedef enum fe_delivery_system { SYS_DVBT2, SYS_TURBO, SYS_DVBC_ANNEX_C, -} fe_delivery_system_t; +}; + +typedef enum fe_delivery_system fe_delivery_system_t; /* backward compatibility */ #define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A -- cgit v1.2.3 From fe557e40f576741308d3546906eba7094e940de4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 14:31:13 -0300 Subject: [media] DocBook: add xrefs for enum fe_type The only enum that was missing xrefs at frontend.h is fe_type. Add xrefs for them. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/dvb/frontend_legacy_api.xml | 8 ++++---- include/uapi/linux/dvb/frontend.h | 6 ++++-- 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml index 8523caf91a2c..8fadf3a4ba44 100644 --- a/Documentation/DocBook/media/dvb/frontend_legacy_api.xml +++ b/Documentation/DocBook/media/dvb/frontend_legacy_api.xml @@ -20,22 +20,22 @@ - FE_QPSK + FE_QPSK For DVB-S standard SYS_DVBS - FE_QAM + FE_QAM For DVB-C annex A standard SYS_DVBC_ANNEX_A - FE_OFDM + FE_OFDM For DVB-T standard SYS_DVBT - FE_ATSC + FE_ATSC For ATSC standard (terrestrial) or for DVB-C Annex B (cable) used in US. SYS_ATSC (terrestrial) or SYS_DVBC_ANNEX_B (cable) diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index 66499f238204..a36d802fae0c 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -28,12 +28,14 @@ #include -typedef enum fe_type { +enum fe_type { FE_QPSK, FE_QAM, FE_OFDM, FE_ATSC -} fe_type_t; +}; + +typedef enum fe_type fe_type_t; enum fe_caps { -- cgit v1.2.3 From 429c2024cb7b4e3be50dae9a5976692bf733f08c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 16:17:56 -0300 Subject: [media] DocBook: Remove comments before parsing enum values The comments may affect enum value parsing. Use cpp to remove them. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index 226152952f58..e7d44a0b00d6 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -87,7 +87,7 @@ ENUMS = \ $(srctree)/include/uapi/linux/v4l2-subdev.h) ENUM_DEFS = \ - $(shell perl -e 'while (<>) { if ($$enum) {print "$$1\n" if (/\s*([A-Z]\S+)\b/); } $$enum = 0 if ($enum && /^\}/); $$enum = 1 if(/^\s*enum\s/); }' \ + $(shell perl -e 'open IN,"cat @ARGV| cpp -fpreprocessed |"; while () { if ($$enum) {print "$$1\n" if (/\s*([A-Z]\S+)\b/); } $$enum = 0 if ($$enum && /^\}/); $$enum = 1 if(/^\s*enum\s/); }; close IN;' \ $(srctree)/include/uapi/linux/dvb/audio.h \ $(srctree)/include/uapi/linux/dvb/ca.h \ $(srctree)/include/uapi/linux/dvb/dmx.h \ -- cgit v1.2.3 From 6eab8043f9b91a998dc06ce0b770b9664e51bfc3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 7 Jun 2015 19:29:43 -0300 Subject: [media] DocBook: Change format for enum dmx_output documentation Use a table for the Demux output. No new information added here. They were all merged inside the table. Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/media/Makefile | 13 +++---- Documentation/DocBook/media/dvb/demux.xml | 57 ++++++++++++++++++++----------- include/uapi/linux/dvb/dmx.h | 6 ++-- 3 files changed, 47 insertions(+), 29 deletions(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/media/Makefile b/Documentation/DocBook/media/Makefile index e7d44a0b00d6..23996f88cd58 100644 --- a/Documentation/DocBook/media/Makefile +++ b/Documentation/DocBook/media/Makefile @@ -88,12 +88,8 @@ ENUMS = \ ENUM_DEFS = \ $(shell perl -e 'open IN,"cat @ARGV| cpp -fpreprocessed |"; while () { if ($$enum) {print "$$1\n" if (/\s*([A-Z]\S+)\b/); } $$enum = 0 if ($$enum && /^\}/); $$enum = 1 if(/^\s*enum\s/); }; close IN;' \ - $(srctree)/include/uapi/linux/dvb/audio.h \ - $(srctree)/include/uapi/linux/dvb/ca.h \ $(srctree)/include/uapi/linux/dvb/dmx.h \ - $(srctree)/include/uapi/linux/dvb/frontend.h \ - $(srctree)/include/uapi/linux/dvb/net.h \ - $(srctree)/include/uapi/linux/dvb/video.h) + $(srctree)/include/uapi/linux/dvb/frontend.h) STRUCTS = \ $(shell perl -ne 'print "$$1 " if /^struct\s+([^\s]+)\s+/' $(srctree)/include/uapi/linux/videodev2.h) \ @@ -251,9 +247,14 @@ $(MEDIA_OBJ_DIR)/dmx.h.xml: $(srctree)/include/uapi/linux/dvb/dmx.h $(MEDIA_OBJ_ @( \ echo "") > $@ @( \ + for ident in $(ENUM_DEFS) ; do \ + entity=`echo $$ident | tr _ -` ; \ + r="$$r s/([^\w\-])$$ident([^\w\-])/\1\&$$entity\;\2/g;";\ + done; \ expand --tabs=8 < $< | \ sed $(ESCAPE) $(DVB_DOCUMENTED) | \ - sed 's/i\.e\./&ie;/') >> $@ + sed 's/i\.e\./&ie;/' | \ + perl -ne "$$r print $$_;") >> $@ @( \ echo "") >> $@ diff --git a/Documentation/DocBook/media/dvb/demux.xml b/Documentation/DocBook/media/dvb/demux.xml index 11a831d58643..34f2fb1cd601 100644 --- a/Documentation/DocBook/media/dvb/demux.xml +++ b/Documentation/DocBook/media/dvb/demux.xml @@ -8,26 +8,43 @@ accessed by including linux/dvb/dmx.h in your application. Demux Data Types
-dmx_output_t - -typedef enum -{ - DMX_OUT_DECODER, /⋆ Streaming directly to decoder. ⋆/ - DMX_OUT_TAP, /⋆ Output going to a memory buffer ⋆/ - /⋆ (to be retrieved via the read command).⋆/ - DMX_OUT_TS_TAP, /⋆ Output multiplexed into a new TS ⋆/ - /⋆ (to be retrieved by reading from the ⋆/ - /⋆ logical DVR device). ⋆/ - DMX_OUT_TSDEMUX_TAP /⋆ Like TS_TAP but retrieved from the DMX device ⋆/ -} dmx_output_t; - -DMX_OUT_TAP delivers the stream output to the demux device on which the ioctl is -called. - -DMX_OUT_TS_TAP routes output to the logical DVR device /dev/dvb/adapter?/dvr?, -which delivers a TS multiplexed from all filters for which DMX_OUT_TS_TAP was -specified. - +Output for the demux + + + enum dmx_output + + &cs-def; + + + ID + Description + + + + + DMX_OUT_DECODER + Streaming directly to decoder. + + DMX_OUT_TAP + Output going to a memory buffer (to be retrieved via the + read command). Delivers the stream output to the demux + device on which the ioctl is called. + + DMX_OUT_TS_TAP + Output multiplexed into a new TS (to be retrieved by + reading from the logical DVR device). Routes output to the + logical DVR device /dev/dvb/adapter?/dvr?, + which delivers a TS multiplexed from all filters for which + DMX_OUT_TS_TAP was specified. + + DMX_OUT_TSDEMUX_TAP + Like &DMX-OUT-TS-TAP; but retrieved from the DMX + device. + + + +
+
diff --git a/include/uapi/linux/dvb/dmx.h b/include/uapi/linux/dvb/dmx.h index ece3661a3cac..427e4899ed69 100644 --- a/include/uapi/linux/dvb/dmx.h +++ b/include/uapi/linux/dvb/dmx.h @@ -32,7 +32,7 @@ #define DMX_FILTER_SIZE 16 -typedef enum dmx_output +enum dmx_output { DMX_OUT_DECODER, /* Streaming directly to decoder. */ DMX_OUT_TAP, /* Output going to a memory buffer */ @@ -41,8 +41,9 @@ typedef enum dmx_output /* (to be retrieved by reading from the */ /* logical DVR device). */ DMX_OUT_TSDEMUX_TAP /* Like TS_TAP but retrieved from the DMX device */ -} dmx_output_t; +}; +typedef enum dmx_output dmx_output_t; typedef enum dmx_input { @@ -139,7 +140,6 @@ struct dmx_stc { __u64 stc; /* output: stc in 'base'*90 kHz units */ }; - #define DMX_START _IO('o', 41) #define DMX_STOP _IO('o', 42) #define DMX_SET_FILTER _IOW('o', 43, struct dmx_sct_filter_params) -- cgit v1.2.3 From 5a54cd2a3fa160c338ee147bc2f0ac9e48d9fb27 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 12 May 2015 13:02:09 -0300 Subject: [media] bdisp: add DT bindings documentation This adds DT binding documentation for STMicroelectronics bdisp driver. Signed-off-by: Fabien Dessenne Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/st,stih4xx.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stih4xx.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/media/st,stih4xx.txt b/Documentation/devicetree/bindings/media/st,stih4xx.txt new file mode 100644 index 000000000000..df655cd3a4f8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stih4xx.txt @@ -0,0 +1,32 @@ +STMicroelectronics stih4xx platforms + +bdisp: 2D blitter for STMicroelectronics SoC. + +Required properties: +- compatible: should be "st,stih407-bdisp". +- reg: BDISP physical address location and length. +- interrupts: BDISP interrupt number. +- clocks: from common clock binding: handle hardware IP needed clocks, the + number of clocks may depend on the SoC type. + See ../clocks/clock-bindings.txt for details. +- clock-names: names of the clocks listed in clocks property in the same order. + +Example: + + bdisp0:bdisp@9f10000 { + compatible = "st,stih407-bdisp"; + reg = <0x9f10000 0x1000>; + interrupts = ; + clock-names = "bdisp"; + clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; + }; + +Aliases: +Each BDISP should have a numbered alias in the aliases node, in the form of +bdispN, N = 0 or 1. + +Example: + + aliases { + bdisp0 = &bdisp0; + }; -- cgit v1.2.3 From de983454d6bd1c050679ceeb70189161d569c488 Mon Sep 17 00:00:00 2001 From: Dmitry Eremin-Solenikov Date: Thu, 21 May 2015 15:53:01 -0300 Subject: [media] saa7134: add AverMedia AverTV/505 card support Add AverMedia AverTV/505 card to saa7134 driver. It is a card bearing SAA7130HL chip and FQ1216ME/IH-3 tuner. Working: Composite, TV and IR remote control. Untested: S-Video. [mchehab@osg.samsung.com: fix CodingStyle] Signed-off-by: Dmitry Eremin-Solenikov Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.saa7134 | 1 + drivers/media/pci/saa7134/saa7134-cards.c | 42 +++++++++++++++++++++++++++++- drivers/media/pci/saa7134/saa7134-input.c | 2 ++ drivers/media/pci/saa7134/saa7134.h | 1 + 4 files changed, 45 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/video4linux/CARDLIST.saa7134 b/Documentation/video4linux/CARDLIST.saa7134 index a93d86455233..f4b395bdc090 100644 --- a/Documentation/video4linux/CARDLIST.saa7134 +++ b/Documentation/video4linux/CARDLIST.saa7134 @@ -192,3 +192,4 @@ 191 -> Hawell HW-9004V1 192 -> AverMedia AverTV Satellite Hybrid+FM A706 [1461:2055] 193 -> WIS Voyager or compatible [1905:7007] +194 -> AverMedia AverTV/505 [1461:a10a] diff --git a/drivers/media/pci/saa7134/saa7134-cards.c b/drivers/media/pci/saa7134/saa7134-cards.c index c52032940af6..c7405766609c 100644 --- a/drivers/media/pci/saa7134/saa7134-cards.c +++ b/drivers/media/pci/saa7134/saa7134-cards.c @@ -5851,6 +5851,39 @@ struct saa7134_board saa7134_boards[] = { .amux = LINE1, } }, }, + [SAA7134_BOARD_AVERMEDIA_505] = { + /* much like the "studio" version but without radio + * and another tuner (dbaryshkov@gmail.com) */ + .name = "AverMedia AverTV/505", + .audio_clock = 0x00187de7, + .tuner_type = TUNER_PHILIPS_FQ1216ME, + .radio_type = UNSET, + .tuner_addr = ADDR_UNSET, + .radio_addr = ADDR_UNSET, + .tda9887_conf = TDA9887_PRESENT, + .inputs = {{ + .name = name_tv, + .vmux = 1, + .amux = LINE2, + .tv = 1, + }, { + .name = name_comp1, + .vmux = 0, + .amux = LINE2, + }, { + .name = name_comp2, + .vmux = 3, + .amux = LINE2, + }, { + .name = name_svideo, + .vmux = 8, + .amux = LINE2, + } }, + .mute = { + .name = name_mute, + .amux = LINE1, + }, + }, }; @@ -7109,6 +7142,12 @@ struct pci_device_id saa7134_pci_tbl[] = { .subvendor = 0x1905, /* WIS */ .subdevice = 0x7007, .driver_data = SAA7134_BOARD_WIS_VOYAGER, + }, { + .vendor = PCI_VENDOR_ID_PHILIPS, + .device = PCI_DEVICE_ID_PHILIPS_SAA7130, + .subvendor = 0x1461, /* Avermedia Technologies Inc */ + .subdevice = 0xa10a, + .driver_data = SAA7134_BOARD_AVERMEDIA_505, }, { /* --- boards without eeprom + subsystem ID --- */ .vendor = PCI_VENDOR_ID_PHILIPS, @@ -7449,8 +7488,9 @@ int saa7134_board_init1(struct saa7134_dev *dev) case SAA7134_BOARD_KWORLD_VSTREAM_XPERT: case SAA7134_BOARD_KWORLD_XPERT: case SAA7134_BOARD_AVERMEDIA_STUDIO_305: - case SAA7134_BOARD_AVERMEDIA_STUDIO_505: case SAA7134_BOARD_AVERMEDIA_305: + case SAA7134_BOARD_AVERMEDIA_STUDIO_505: + case SAA7134_BOARD_AVERMEDIA_505: case SAA7134_BOARD_AVERMEDIA_STUDIO_307: case SAA7134_BOARD_AVERMEDIA_307: case SAA7134_BOARD_AVERMEDIA_STUDIO_507: diff --git a/drivers/media/pci/saa7134/saa7134-input.c b/drivers/media/pci/saa7134/saa7134-input.c index e92bcfe9bbcb..11a172000291 100644 --- a/drivers/media/pci/saa7134/saa7134-input.c +++ b/drivers/media/pci/saa7134/saa7134-input.c @@ -485,6 +485,7 @@ static int __saa7134_ir_start(void *priv) case SAA7134_BOARD_KWORLD_VSTREAM_XPERT: case SAA7134_BOARD_AVERMEDIA_305: case SAA7134_BOARD_AVERMEDIA_307: + case SAA7134_BOARD_AVERMEDIA_505: case SAA7134_BOARD_AVERMEDIA_STUDIO_305: case SAA7134_BOARD_AVERMEDIA_STUDIO_505: case SAA7134_BOARD_AVERMEDIA_STUDIO_307: @@ -633,6 +634,7 @@ int saa7134_input_init1(struct saa7134_dev *dev) case SAA7134_BOARD_KWORLD_VSTREAM_XPERT: case SAA7134_BOARD_AVERMEDIA_305: case SAA7134_BOARD_AVERMEDIA_307: + case SAA7134_BOARD_AVERMEDIA_505: case SAA7134_BOARD_AVERMEDIA_STUDIO_305: case SAA7134_BOARD_AVERMEDIA_STUDIO_505: case SAA7134_BOARD_AVERMEDIA_STUDIO_307: diff --git a/drivers/media/pci/saa7134/saa7134.h b/drivers/media/pci/saa7134/saa7134.h index f682ba9b34a7..6b5f6f45d285 100644 --- a/drivers/media/pci/saa7134/saa7134.h +++ b/drivers/media/pci/saa7134/saa7134.h @@ -341,6 +341,7 @@ struct saa7134_card_ir { #define SAA7134_BOARD_HAWELL_HW_9004V1 191 #define SAA7134_BOARD_AVERMEDIA_A706 192 #define SAA7134_BOARD_WIS_VOYAGER 193 +#define SAA7134_BOARD_AVERMEDIA_505 194 #define SAA7134_MAXBOARDS 32 #define SAA7134_INPUT_MAX 8 -- cgit v1.2.3 From bba795fc0e03c653dedd234b11360efaff35a043 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 9 Jun 2015 18:43:47 -0300 Subject: [media] Documentation: update cardlists The card lists at Documentation/video4linux are missing some boards. Add them. Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.cx23885 | 9 ++++++++- Documentation/video4linux/CARDLIST.em28xx | 2 ++ Documentation/video4linux/CARDLIST.saa7164 | 3 +++ 3 files changed, 13 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/video4linux/CARDLIST.cx23885 b/Documentation/video4linux/CARDLIST.cx23885 index 4c84ec853265..44a4cfbfdc40 100644 --- a/Documentation/video4linux/CARDLIST.cx23885 +++ b/Documentation/video4linux/CARDLIST.cx23885 @@ -36,7 +36,7 @@ 35 -> TeVii S471 [d471:9022] 36 -> Hauppauge WinTV-HVR1255 [0070:2259] 37 -> Prof Revolution DVB-S2 8000 [8000:3034] - 38 -> Hauppauge WinTV-HVR4400 [0070:c108,0070:c138,0070:c12a,0070:c1f8] + 38 -> Hauppauge WinTV-HVR4400/HVR5500 [0070:c108,0070:c138,0070:c1f8] 39 -> AVerTV Hybrid Express Slim HC81R [1461:d939] 40 -> TurboSight TBS 6981 [6981:8888] 41 -> TurboSight TBS 6980 [6980:8888] @@ -45,3 +45,10 @@ 44 -> DViCO FusionHDTV DVB-T Dual Express2 [18ac:db98] 45 -> DVBSky T9580 [4254:9580] 46 -> DVBSky T980C [4254:980c] + 47 -> DVBSky S950C [4254:950c] + 48 -> Technotrend TT-budget CT2-4500 CI [13c2:3013] + 49 -> DVBSky S950 [4254:0950] + 50 -> DVBSky S952 [4254:0952] + 51 -> DVBSky T982 [4254:0982] + 52 -> Hauppauge WinTV-HVR5525 [0070:f038] + 53 -> Hauppauge WinTV Starburst [0070:c12a] diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index 3700edb81db2..9e57ce43c4f4 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -94,3 +94,5 @@ 93 -> KWorld USB ATSC TV Stick UB435-Q V3 (em2874) [1b80:e34c] 94 -> PCTV tripleStick (292e) (em28178) 95 -> Leadtek VC100 (em2861) [0413:6f07] + 96 -> Terratec Cinergy T2 Stick HD (em28178) + 97 -> Elgato EyeTV Hybrid 2008 INT (em2884) [0fd9:0018] diff --git a/Documentation/video4linux/CARDLIST.saa7164 b/Documentation/video4linux/CARDLIST.saa7164 index 2205e8d55537..6eb057220474 100644 --- a/Documentation/video4linux/CARDLIST.saa7164 +++ b/Documentation/video4linux/CARDLIST.saa7164 @@ -9,3 +9,6 @@ 8 -> Hauppauge WinTV-HVR2250 [0070:88A1] 9 -> Hauppauge WinTV-HVR2200 [0070:8940] 10 -> Hauppauge WinTV-HVR2200 [0070:8953] + 11 -> Hauppauge WinTV-HVR2255(proto) + 12 -> Hauppauge WinTV-HVR2255 [0070:f111] + 13 -> Hauppauge WinTV-HVR2205 [0070:f123,0070:f120] -- cgit v1.2.3 From 03a740fb682c5ae9bf49ebad284986e9afc63958 Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Tue, 9 Jun 2015 14:23:49 +0530 Subject: devicetree:bindings: add devicetree bindings for ceva ahci adds bindings for CEVA AHCI SATA controller. optional property broken-gen2 is useful incase of hardware speed limitation. Signed-off-by: Suneel Garapati Signed-off-by: Tejun Heo --- Documentation/devicetree/bindings/ata/ahci-ceva.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/ahci-ceva.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt new file mode 100644 index 000000000000..7ca8b976c13a --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt @@ -0,0 +1,20 @@ +Binding for CEVA AHCI SATA Controller + +Required properties: + - reg: Physical base address and size of the controller's register area. + - compatible: Compatibility string. Must be 'ceva,ahci-1v84'. + - clocks: Input clock specifier. Refer to common clock bindings. + - interrupts: Interrupt specifier. Refer to interrupt binding. + +Optional properties: + - ceva,broken-gen2: limit to gen1 speed instead of gen2. + +Examples: + ahci@fd0c0000 { + compatible = "ceva,ahci-1v84"; + reg = <0xfd0c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 133 4>; + clocks = <&clkc SATA_CLK_ID>; + ceva,broken-gen2; + }; -- cgit v1.2.3 From d342571efea8135dcf0a96dcb9e54759adefdb27 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Sat, 6 Jun 2015 22:30:40 +0200 Subject: gpio: add ETRAXFS GPIO driver Add a GPIO driver for the General I/O block on Axis ETRAX FS SoCs. Signed-off-by: Rabin Vincent Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-etraxfs.txt | 21 +++ drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-etraxfs.c | 176 +++++++++++++++++++++ 4 files changed, 206 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt create mode 100644 drivers/gpio/gpio-etraxfs.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt b/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt new file mode 100644 index 000000000000..abf4db736c6e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt @@ -0,0 +1,21 @@ +Axis ETRAX FS General I/O controller bindings + +Required properties: + +- compatible: + - "axis,etraxfs-gio" +- reg: Physical base address and length of the controller's registers. +- #gpio-cells: Should be 3 + - The first cell is the gpio offset number. + - The second cell is reserved and is currently unused. + - The third cell is the port number (hex). +- gpio-controller: Marks the device node as a GPIO controller. + +Example: + + gio: gpio@b001a000 { + compatible = "axis,etraxfs-gio"; + reg = <0xb001a000 0x1000>; + gpio-controller; + #gpio-cells = <3>; + }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d86de6ae0a0e..ab9084648509 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -167,6 +167,14 @@ config GPIO_EP93XX depends on ARCH_EP93XX select GPIO_GENERIC +config GPIO_ETRAXFS + bool "Axis ETRAX FS General I/O" + depends on CRIS || COMPILE_TEST + depends on OF + select GPIO_GENERIC + help + Say yes here to support the GPIO controller on Axis ETRAX FS SoCs. + config GPIO_F7188X tristate "F71869, F71869A, F71882FG and F71889F GPIO support" depends on X86 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 893bbffc313a..f82cd678ce08 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o +obj-$(CONFIG_GPIO_ETRAXFS) += gpio-etraxfs.o obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o diff --git a/drivers/gpio/gpio-etraxfs.c b/drivers/gpio/gpio-etraxfs.c new file mode 100644 index 000000000000..28071f4a5672 --- /dev/null +++ b/drivers/gpio/gpio-etraxfs.c @@ -0,0 +1,176 @@ +#include +#include +#include +#include +#include +#include +#include + +#define ETRAX_FS_rw_pa_dout 0 +#define ETRAX_FS_r_pa_din 4 +#define ETRAX_FS_rw_pa_oe 8 +#define ETRAX_FS_rw_intr_cfg 12 +#define ETRAX_FS_rw_intr_mask 16 +#define ETRAX_FS_rw_ack_intr 20 +#define ETRAX_FS_r_intr 24 +#define ETRAX_FS_rw_pb_dout 32 +#define ETRAX_FS_r_pb_din 36 +#define ETRAX_FS_rw_pb_oe 40 +#define ETRAX_FS_rw_pc_dout 48 +#define ETRAX_FS_r_pc_din 52 +#define ETRAX_FS_rw_pc_oe 56 +#define ETRAX_FS_rw_pd_dout 64 +#define ETRAX_FS_r_pd_din 68 +#define ETRAX_FS_rw_pd_oe 72 +#define ETRAX_FS_rw_pe_dout 80 +#define ETRAX_FS_r_pe_din 84 +#define ETRAX_FS_rw_pe_oe 88 + +struct etraxfs_gpio_port { + const char *label; + unsigned int oe; + unsigned int dout; + unsigned int din; + unsigned int ngpio; +}; + +struct etraxfs_gpio_info { + unsigned int num_ports; + const struct etraxfs_gpio_port *ports; +}; + +static const struct etraxfs_gpio_port etraxfs_gpio_etraxfs_ports[] = { + { + .label = "A", + .ngpio = 8, + .oe = ETRAX_FS_rw_pa_oe, + .dout = ETRAX_FS_rw_pa_dout, + .din = ETRAX_FS_r_pa_din, + }, + { + .label = "B", + .ngpio = 18, + .oe = ETRAX_FS_rw_pb_oe, + .dout = ETRAX_FS_rw_pb_dout, + .din = ETRAX_FS_r_pb_din, + }, + { + .label = "C", + .ngpio = 18, + .oe = ETRAX_FS_rw_pc_oe, + .dout = ETRAX_FS_rw_pc_dout, + .din = ETRAX_FS_r_pc_din, + }, + { + .label = "D", + .ngpio = 18, + .oe = ETRAX_FS_rw_pd_oe, + .dout = ETRAX_FS_rw_pd_dout, + .din = ETRAX_FS_r_pd_din, + }, + { + .label = "E", + .ngpio = 18, + .oe = ETRAX_FS_rw_pe_oe, + .dout = ETRAX_FS_rw_pe_dout, + .din = ETRAX_FS_r_pe_din, + }, +}; + +static const struct etraxfs_gpio_info etraxfs_gpio_etraxfs = { + .num_ports = ARRAY_SIZE(etraxfs_gpio_etraxfs_ports), + .ports = etraxfs_gpio_etraxfs_ports, +}; + +static int etraxfs_gpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + /* + * Port numbers are A to E, and the properties are integers, so we + * specify them as 0xA - 0xE. + */ + if (gc->label[0] - 'A' + 0xA != gpiospec->args[2]) + return -EINVAL; + + return of_gpio_simple_xlate(gc, gpiospec, flags); +} + +static const struct of_device_id etraxfs_gpio_of_table[] = { + { + .compatible = "axis,etraxfs-gio", + .data = &etraxfs_gpio_etraxfs, + }, + {}, +}; + +static int etraxfs_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct etraxfs_gpio_info *info; + const struct of_device_id *match; + struct bgpio_chip *chips; + struct resource *res; + void __iomem *regs; + int ret; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regs = devm_ioremap_resource(dev, res); + if (!regs) + return -ENOMEM; + + match = of_match_node(etraxfs_gpio_of_table, dev->of_node); + if (!match) + return -EINVAL; + + info = match->data; + + chips = devm_kzalloc(dev, sizeof(*chips) * info->num_ports, GFP_KERNEL); + if (!chips) + return -ENOMEM; + + for (i = 0; i < info->num_ports; i++) { + struct bgpio_chip *bgc = &chips[i]; + const struct etraxfs_gpio_port *port = &info->ports[i]; + + ret = bgpio_init(bgc, dev, 4, + regs + port->din, /* dat */ + regs + port->dout, /* set */ + NULL, /* clr */ + regs + port->oe, /* dirout */ + NULL, /* dirin */ + BGPIOF_UNREADABLE_REG_SET); + if (ret) + return ret; + + bgc->gc.ngpio = port->ngpio; + bgc->gc.label = port->label; + + bgc->gc.of_node = dev->of_node; + bgc->gc.of_gpio_n_cells = 3; + bgc->gc.of_xlate = etraxfs_gpio_of_xlate; + + ret = gpiochip_add(&bgc->gc); + if (ret) + dev_err(dev, "Unable to register port %s\n", + bgc->gc.label); + } + + return 0; +} + +static struct platform_driver etraxfs_gpio_driver = { + .driver = { + .name = "etraxfs-gpio", + .of_match_table = of_match_ptr(etraxfs_gpio_of_table), + }, + .probe = etraxfs_gpio_probe, +}; + +static int __init etraxfs_gpio_init(void) +{ + return platform_driver_register(&etraxfs_gpio_driver); +} + +device_initcall(etraxfs_gpio_init); -- cgit v1.2.3 From bdf7a4ae371894b4dc10b5820006b0a82d484929 Mon Sep 17 00:00:00 2001 From: Anurag Kumar Vulisha Date: Thu, 4 Jun 2015 17:40:32 +0530 Subject: gpio: Added support to Zynq Ultrascale+ MPSoC Added support to Zynq Ultrascale+ MPSoC on the existing zynq gpio driver. Signed-off-by: Anurag Kumar Vulisha Acked-by: Michal Simek Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-zynq.txt | 2 +- drivers/gpio/Kconfig | 2 +- drivers/gpio/gpio-zynq.c | 191 ++++++++++++++------- 3 files changed, 127 insertions(+), 68 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt index 986371a4be2c..db4c6a663c03 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt @@ -6,7 +6,7 @@ Required properties: - First cell is the GPIO line number - Second cell is used to specify optional parameters (unused) -- compatible : Should be "xlnx,zynq-gpio-1.0" +- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0" - clocks : Clock specifier (see clock bindings for details) - gpio-controller : Marks the device node as a GPIO controller. - interrupts : Interrupt specifier (see interrupt bindings for diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ab9084648509..8f1fe739c985 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -540,7 +540,7 @@ config GPIO_ZEVIO config GPIO_ZYNQ tristate "Xilinx Zynq GPIO support" - depends on ARCH_ZYNQ + depends on ARCH_ZYNQ || ARCH_ZYNQMP select GPIOLIB_IRQCHIP help Say yes here to support Xilinx Zynq GPIO controller. diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index 0d9663f53834..2e87c4b8da26 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -18,34 +18,47 @@ #include #include #include +#include #define DRIVER_NAME "zynq-gpio" /* Maximum banks */ #define ZYNQ_GPIO_MAX_BANK 4 +#define ZYNQMP_GPIO_MAX_BANK 6 #define ZYNQ_GPIO_BANK0_NGPIO 32 #define ZYNQ_GPIO_BANK1_NGPIO 22 #define ZYNQ_GPIO_BANK2_NGPIO 32 #define ZYNQ_GPIO_BANK3_NGPIO 32 -#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ - ZYNQ_GPIO_BANK1_NGPIO + \ - ZYNQ_GPIO_BANK2_NGPIO + \ - ZYNQ_GPIO_BANK3_NGPIO) - -#define ZYNQ_GPIO_BANK0_PIN_MIN 0 -#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ - ZYNQ_GPIO_BANK0_NGPIO - 1) -#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ - ZYNQ_GPIO_BANK1_NGPIO - 1) -#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ - ZYNQ_GPIO_BANK2_NGPIO - 1) -#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ - ZYNQ_GPIO_BANK3_NGPIO - 1) +#define ZYNQMP_GPIO_BANK0_NGPIO 26 +#define ZYNQMP_GPIO_BANK1_NGPIO 26 +#define ZYNQMP_GPIO_BANK2_NGPIO 26 +#define ZYNQMP_GPIO_BANK3_NGPIO 32 +#define ZYNQMP_GPIO_BANK4_NGPIO 32 +#define ZYNQMP_GPIO_BANK5_NGPIO 32 + +#define ZYNQ_GPIO_NR_GPIOS 118 +#define ZYNQMP_GPIO_NR_GPIOS 174 + +#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 +#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK0_NGPIO - 1) +#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK1_NGPIO - 1) +#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK2_NGPIO - 1) +#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK3_NGPIO - 1) +#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK4_NGPIO - 1) +#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK5_NGPIO - 1) /* Register offsets for the GPIO device */ @@ -89,12 +102,30 @@ * @base_addr: base address of the GPIO device * @clk: clock resource for this controller * @irq: interrupt for the GPIO device + * @p_data: pointer to platform data */ struct zynq_gpio { struct gpio_chip chip; void __iomem *base_addr; struct clk *clk; int irq; + const struct zynq_platform_data *p_data; +}; + +/** + * struct zynq_platform_data - zynq gpio platform data structure + * @label: string to store in gpio->label + * @ngpio: max number of gpio pins + * @max_bank: maximum number of gpio banks + * @bank_min: this array represents bank's min pin + * @bank_max: this array represents bank's max pin +*/ +struct zynq_platform_data { + const char *label; + u16 ngpio; + int max_bank; + int bank_min[ZYNQMP_GPIO_MAX_BANK]; + int bank_max[ZYNQMP_GPIO_MAX_BANK]; }; static struct irq_chip zynq_gpio_level_irqchip; @@ -112,39 +143,26 @@ static struct irq_chip zynq_gpio_edge_irqchip; */ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, unsigned int *bank_num, - unsigned int *bank_pin_num) + unsigned int *bank_pin_num, + struct zynq_gpio *gpio) { - switch (pin_num) { - case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX: - *bank_num = 0; - *bank_pin_num = pin_num; - break; - case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX: - *bank_num = 1; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN; - break; - case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX: - *bank_num = 2; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN; - break; - case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX: - *bank_num = 3; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN; - break; - default: - WARN(true, "invalid GPIO pin number: %u", pin_num); - *bank_num = 0; - *bank_pin_num = 0; - break; + int bank; + + for (bank = 0; bank < gpio->p_data->max_bank; bank++) { + if ((pin_num >= gpio->p_data->bank_min[bank]) && + (pin_num <= gpio->p_data->bank_max[bank])) { + *bank_num = bank; + *bank_pin_num = pin_num - + gpio->p_data->bank_min[bank]; + return; + } } -} -static const unsigned int zynq_gpio_bank_offset[] = { - ZYNQ_GPIO_BANK0_PIN_MIN, - ZYNQ_GPIO_BANK1_PIN_MIN, - ZYNQ_GPIO_BANK2_PIN_MIN, - ZYNQ_GPIO_BANK3_PIN_MIN, -}; + /* default */ + WARN(true, "invalid GPIO pin number: %u", pin_num); + *bank_num = 0; + *bank_pin_num = 0; +} /** * zynq_gpio_get_value - Get the state of the specified pin of GPIO device @@ -161,7 +179,7 @@ static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) unsigned int bank_num, bank_pin_num; struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); data = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); @@ -185,7 +203,7 @@ static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, unsigned int reg_offset, bank_num, bank_pin_num; struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { /* only 16 data bits in bit maskable reg */ @@ -222,7 +240,7 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) unsigned int bank_num, bank_pin_num; struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) @@ -255,7 +273,7 @@ static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, unsigned int bank_num, bank_pin_num; struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip); - zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); /* set the GPIO pin as output */ reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); @@ -286,7 +304,7 @@ static void zynq_gpio_irq_mask(struct irq_data *irq_data) struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); device_pin_num = irq_data->hwirq; - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); writel_relaxed(BIT(bank_pin_num), gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); } @@ -306,7 +324,7 @@ static void zynq_gpio_irq_unmask(struct irq_data *irq_data) struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); device_pin_num = irq_data->hwirq; - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); writel_relaxed(BIT(bank_pin_num), gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); } @@ -325,7 +343,7 @@ static void zynq_gpio_irq_ack(struct irq_data *irq_data) struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); device_pin_num = irq_data->hwirq; - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); writel_relaxed(BIT(bank_pin_num), gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); } @@ -375,7 +393,7 @@ static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data); device_pin_num = irq_data->hwirq; - zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); int_type = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); @@ -470,7 +488,7 @@ static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, unsigned int bank_num, unsigned long pending) { - unsigned int bank_offset = zynq_gpio_bank_offset[bank_num]; + unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; struct irq_domain *irqdomain = gpio->chip.irqdomain; int offset; @@ -505,7 +523,7 @@ static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc) chained_irq_enter(irqchip, desc); - for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) { + for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { int_sts = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); int_enb = readl_relaxed(gpio->base_addr + @@ -582,6 +600,46 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { zynq_gpio_runtime_resume, NULL) }; +static const struct zynq_platform_data zynqmp_gpio_def = { + .label = "zynqmp_gpio", + .ngpio = ZYNQMP_GPIO_NR_GPIOS, + .max_bank = ZYNQMP_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), + .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), + .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), + .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), + .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), +}; + +static const struct zynq_platform_data zynq_gpio_def = { + .label = "zynq_gpio", + .ngpio = ZYNQ_GPIO_NR_GPIOS, + .max_bank = ZYNQ_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), +}; + +static const struct of_device_id zynq_gpio_of_match[] = { + { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def }, + { .compatible = "xlnx,zynqmp-gpio-1.0", + .data = (void *)&zynqmp_gpio_def }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); + /** * zynq_gpio_probe - Initialization method for a zynq_gpio device * @pdev: platform device instance @@ -599,11 +657,18 @@ static int zynq_gpio_probe(struct platform_device *pdev) struct zynq_gpio *gpio; struct gpio_chip *chip; struct resource *res; + const struct of_device_id *match; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) return -ENOMEM; + match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); + if (!match) { + dev_err(&pdev->dev, "of_match_node() failed\n"); + return -EINVAL; + } + gpio->p_data = match->data; platform_set_drvdata(pdev, gpio); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -619,7 +684,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) /* configure the gpio chip */ chip = &gpio->chip; - chip->label = "zynq_gpio"; + chip->label = gpio->p_data->label; chip->owner = THIS_MODULE; chip->dev = &pdev->dev; chip->get = zynq_gpio_get_value; @@ -629,7 +694,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) chip->direction_input = zynq_gpio_dir_in; chip->direction_output = zynq_gpio_dir_out; chip->base = -1; - chip->ngpio = ZYNQ_GPIO_NR_GPIOS; + chip->ngpio = gpio->p_data->ngpio; /* Enable GPIO clock */ gpio->clk = devm_clk_get(&pdev->dev, NULL); @@ -651,7 +716,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) } /* disable interrupts for all banks */ - for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) + for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); @@ -695,12 +760,6 @@ static int zynq_gpio_remove(struct platform_device *pdev) return 0; } -static struct of_device_id zynq_gpio_of_match[] = { - { .compatible = "xlnx,zynq-gpio-1.0", }, - { /* end of table */ } -}; -MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); - static struct platform_driver zynq_gpio_driver = { .driver = { .name = DRIVER_NAME, -- cgit v1.2.3 From 1bb6fad359b147645e47cf826bc20e6b5b4d66b2 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 5 Jun 2015 15:52:24 -0700 Subject: pinctrl: dt-binding: Add DT binding documentation for MSM8660 Signed-off-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,msm8660-pinctrl.txt | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt new file mode 100644 index 000000000000..77aa11790163 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt @@ -0,0 +1,90 @@ +Qualcomm MSM8660 TLMM block + +Required properties: +- compatible: "qcom,msm8660-pinctrl" +- reg: Should be the base address and length of the TLMM block. +- interrupts: Should be the parent IRQ of the TLMM block. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. + The first cell is the gpio pin number and the + second cell is used for optional parameters. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Qualcomm's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + + pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, + output-low, output-high. + +Non-empty subnodes must specify the 'pins' property. + +Valid values for pins are: + gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data + +Valid values for function are: + gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b, + gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, + gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, + gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, + gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, + lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, + usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, + +Example: + + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 0x4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gsbi12_uart>; + + gsbi12_uart: gsbi12-uart { + mux { + pins = "gpio117", "gpio118"; + function = "gsbi12"; + }; + + tx { + pins = "gpio118"; + drive-strength = <8>; + bias-disable; + }; + + rx { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; -- cgit v1.2.3 From 331642fbf24a1c16b2669ca0a6479b5fcd6dd5b2 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:53 +0200 Subject: pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni Cc: # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij --- .../pinctrl/marvell,armada-38x-pinctrl.txt | 38 ++++++++--------- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 49 +++++++++------------- 2 files changed, 39 insertions(+), 48 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index b17c96849fc9..4ac138aaaf87 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -27,15 +27,15 @@ mpp8 8 gpio, ge0(txd1), dev(ad10) mpp9 9 gpio, ge0(txd2), dev(ad11) mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) -mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14) -mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1) -mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1] -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq) +mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) +mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1] -mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts) -mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts) +mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) +mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) @@ -58,23 +58,23 @@ mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout) -mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout) -mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5) -mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd) +mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) +mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] +mpp45 45 gpio, ref(clk_out0), pcie0(rstout) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout) +mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] +mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) -mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6) +mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) -mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3) +mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) mpp57 57 gpio, spi1(sck), sd0(clk) mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828 [2]: only available on 88F6828 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 83bbcc72be1f..11656c7cfab0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -94,37 +94,39 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(13, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6810_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), + MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS)), MPP_MODE(16, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS), @@ -137,13 +139,12 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), + MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), @@ -151,7 +152,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), @@ -277,35 +277,27 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), - MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), - MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -313,18 +305,19 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), MPP_MODE(50, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)), @@ -336,7 +329,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), @@ -352,7 +344,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)), MPP_MODE(55, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -382,7 +374,6 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)), }; -- cgit v1.2.3 From 438881dfddb9107ef0eb30b49368e91e092f0b3e Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:54 +0200 Subject: pinctrl: mvebu: armada-370: fix spi0 pin description Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that. This DT binding change does not affect any of the in-tree users. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370") Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index adda2a8d1d52..e357b020861d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -92,5 +92,5 @@ mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk -mpp64 64 gpio, spi0(miso), spi0-1(cs1) -mpp65 65 gpio, spi0(mosi), spi0-1(cs2) +mpp64 64 gpio, spi0(miso), spi0(cs1) +mpp65 65 gpio, spi0(mosi), spi0(cs2) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 42f930f70de3..8516cadcb9a9 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -370,11 +370,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_MODE(64, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "spi0", "miso"), - MPP_FUNCTION(0x2, "spi0-1", "cs1")), + MPP_FUNCTION(0x2, "spi0", "cs1")), MPP_MODE(65, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "spi0", "mosi"), - MPP_FUNCTION(0x2, "spi0-1", "cs2")), + MPP_FUNCTION(0x2, "spi0", "cs2")), }; static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info; -- cgit v1.2.3 From e5447d26092c72ef3346615ee558c9112ef8063f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:55 +0200 Subject: pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni Cc: # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index 7de0cda4a379..bedbe42c8c0a 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index ca1e7571fedb..e740a420483d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -98,13 +98,11 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ce")), MPP_MODE(9, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "wen"), MPP_FUNCTION(0x2, "spi0", "sck"), MPP_FUNCTION(0x3, "spi1", "sck"), MPP_FUNCTION(0x5, "nand", "we")), MPP_MODE(10, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "ren"), MPP_FUNCTION(0x2, "dram", "vttctrl"), MPP_FUNCTION(0x3, "led", "c1"), MPP_FUNCTION(0x5, "nand", "re"), -- cgit v1.2.3 From bc99357f3690c11817756adfee0ece811a3db2e7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:56 +0200 Subject: pinctrl: mvebu: armada-xp: remove non-existing NAND pins After updating to a more recent version of the Armada XP datasheet, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 373dbccd7ab0..974168d854ba 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -42,8 +42,8 @@ mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) -mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) -mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) +mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) +mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 578db9f033b2..7310c4022ba6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -172,13 +172,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(24, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)), MPP_MODE(26, -- cgit v1.2.3 From 80b3d04feab5e69d51cb2375eb989a7165e43e3b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:57 +0200 Subject: pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions The latest version of the Armada XP datasheet no longer documents the VDD cpu_pd functions, which might indicate they are not working and/or not supported. This commit ensures the pinctrl driver matches the datasheet. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 26 +++++++---------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 33 +++++++--------------- 2 files changed, 20 insertions(+), 39 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 974168d854ba..b347b85aa22e 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -44,13 +44,13 @@ mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) -mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) +mpp26 26 gpio, lcd(clk), tdm(fsync) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) -mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) +mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) -mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) -mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) +mpp31 31 gpio, tdm(int2), sd0(cmd) +mpp32 32 gpio, tdm(int3), sd0(d0) mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) @@ -58,14 +58,11 @@ mpp36 36 gpio, spi(mosi) mpp37 37 gpio, spi(miso) mpp38 38 gpio, spi(sck) mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), - pcie(clkreq0) +mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), - vdd(cpu0-pd) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), - vdd(cpu2-3-pd){1} +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) +mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), mem(bat) mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) @@ -84,9 +81,9 @@ mpp51 51 gpio, dev(ad16) mpp52 52 gpio, dev(ad17) mpp53 53 gpio, dev(ad18) mpp54 54 gpio, dev(ad19) -mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) -mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) -mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} +mpp55 55 gpio, dev(ad20) +mpp56 56 gpio, dev(ad21) +mpp57 57 gpio, dev(ad22) mpp58 58 gpio, dev(ad23) mpp59 59 gpio, dev(ad24) mpp60 60 gpio, dev(ad25) @@ -96,6 +93,3 @@ mpp63 63 gpio, dev(ad28) mpp64 64 gpio, dev(ad29) mpp65 65 gpio, dev(ad30) mpp66 66 gpio, dev(ad31) - -Notes: -* {1} vdd(cpu2-3-pd) only available on mv78460. diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 7310c4022ba6..0301bd22c1d0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -14,10 +14,7 @@ * available: mv78230, mv78260 and mv78460. From a pin muxing * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460 * both have 67 MPP pins (more GPIOs and address lines for the memory - * bus mainly). The only difference between the mv78260 and the - * mv78460 in terms of pin muxing is the addition of two functions on - * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two - * cores, mv78460 has four cores). + * bus mainly). */ #include @@ -182,8 +179,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(26, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)), MPP_MODE(27, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS), @@ -198,8 +194,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)), MPP_MODE(30, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS), @@ -207,13 +202,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(31, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)), MPP_MODE(32, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), @@ -245,7 +238,6 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), MPP_MODE(41, @@ -260,15 +252,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), MPP_MODE(43, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)), + MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), @@ -319,16 +309,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)), MPP_MODE(55, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)), + MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)), MPP_MODE(56, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)), + MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS), - MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)), + MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)), MPP_MODE(58, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)), -- cgit v1.2.3 From ea78b9511a54d0de026e04b5da86b30515072f31 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:46:58 +0200 Subject: pinctrl: mvebu: armada-xp: fix functions of MPP48 There was a mistake in the definition of the functions for MPP48 on Marvell Armada XP. The second function is dev(clkout), and not tclk. Signed-off-by: Thomas Petazzoni Cc: # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index b347b85aa22e..96e7744cab84 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -69,7 +69,7 @@ mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), ref(clkout) -mpp48 48 gpio, tclk, dev(burst/last) +mpp48 48 gpio, dev(clkout), dev(burst/last) * Marvell Armada XP (mv78260 and mv78460 only) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 0301bd22c1d0..d7cdb146f44d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -287,7 +287,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), -- cgit v1.2.3 From 9540cf534429359699ea85df20cb7be307548b89 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:02 +0200 Subject: pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-375-pinctrl.txt | 10 +++++----- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 8 ++++---- .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 2 +- 6 files changed, 23 insertions(+), 23 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index bedbe42c8c0a..e22ec5eadcbd 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -15,8 +15,8 @@ name pins functions ================================================================================ mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) -mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi) -mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk) +mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) +mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) @@ -45,7 +45,7 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) mpp30 30 gpio, ge1(txd0), spi1(cs0) mpp31 31 gpio, ge1(txd1), spi1(mosi) -mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen) +mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) @@ -76,7 +76,7 @@ mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(triggen), led(p2) +mpp63 63 gpio, ptp(trig), led(p2) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) -mpp66 66 gpio, ptp(eventreq), spi1(cs3) +mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4ac138aaaf87..4fe63408b3d0 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -33,8 +33,8 @@ mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(we mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) -mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) +mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) mpp22 22 gpio, spi0(mosi), dev(ad0) @@ -51,9 +51,9 @@ mpp32 32 gpio, ge1(txctl), dev(wen0) mpp33 33 gpio, m(decc_err), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) -mpp36 36 gpio, ptp(trig_gen), dev(a0) +mpp36 36 gpio, ptp(trig), dev(a0) mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) -mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) +mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 5b1a9dc004f4..182a0597b71f 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -24,7 +24,7 @@ mpp6 6 gpio, dev(cs3), xsmi(mdio) mpp7 7 gpio, dev(ad9), xsmi(mdc) mpp8 8 gpio, dev(ad10), ptp(trig) mpp9 9 gpio, dev(ad11), ptp(clk) -mpp10 10 gpio, dev(ad12), ptp(event) +mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 203291bde608..ba0913ac2197 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -51,7 +51,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(2, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad4"), - MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x3, "led", "c0"), MPP_FUNCTION(0x4, "audio", "sdi"), MPP_FUNCTION(0x5, "nand", "io4"), @@ -59,7 +59,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(3, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad5"), - MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x3, "led", "p3"), MPP_FUNCTION(0x4, "audio", "mclk"), MPP_FUNCTION(0x5, "nand", "io5"), @@ -207,7 +207,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "ge1", "txd0"), MPP_FUNCTION(0x3, "spi1", "cs0"), MPP_FUNCTION(0x5, "led", "p3"), - MPP_FUNCTION(0x6, "ptp", "eventreq")), + MPP_FUNCTION(0x6, "ptp", "evreq")), MPP_MODE(31, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd1"), @@ -217,7 +217,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd2"), MPP_FUNCTION(0x3, "spi1", "sck"), - MPP_FUNCTION(0x4, "ptp", "triggen"), + MPP_FUNCTION(0x4, "ptp", "trig"), MPP_FUNCTION(0x5, "led", "c0")), MPP_MODE(33, MPP_FUNCTION(0x0, "gpio", NULL), @@ -290,7 +290,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "p1"), MPP_FUNCTION(0x2, "ge0", "txd1"), MPP_FUNCTION(0x3, "ge1", "txd1"), - MPP_FUNCTION(0x5, "ptp", "triggen"), + MPP_FUNCTION(0x5, "ptp", "trig"), MPP_FUNCTION(0x6, "dev", "ale0")), MPP_MODE(48, MPP_FUNCTION(0x0, "gpio", NULL), @@ -309,7 +309,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "c0"), MPP_FUNCTION(0x2, "ge0", "rxd0"), MPP_FUNCTION(0x3, "ge1", "rxd0"), - MPP_FUNCTION(0x5, "ptp", "eventreq"), + MPP_FUNCTION(0x5, "ptp", "evreq"), MPP_FUNCTION(0x6, "dev", "ad12")), MPP_MODE(51, MPP_FUNCTION(0x0, "gpio", NULL), @@ -377,7 +377,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x6, "dev", "ad15")), MPP_MODE(63, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "ptp", "triggen"), + MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x4, "led", "p2"), MPP_FUNCTION(0x6, "dev", "burst")), MPP_MODE(64, @@ -389,7 +389,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "sata1", "prsnt")), MPP_MODE(66, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "ptp", "eventreq"), + MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x4, "spi1", "cs3"), MPP_FUNCTION(0x5, "pcie0", "rstoutn"), MPP_FUNCTION(0x6, "dev", "cs3")), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index ff411a53b5a4..eb4b0d8dfe58 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -137,13 +137,13 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "trig", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "evreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), @@ -231,7 +231,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)), MPP_MODE(36, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "trig", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ptp", "evreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 2dcf9b41e01e..4cf702447618 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -82,7 +82,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(10, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6920_PLUS), - MPP_VAR_FUNCTION(7, "ptp", "event", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(7, "ptp", "evreq", V_88F6920_PLUS)), MPP_MODE(11, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS), -- cgit v1.2.3 From 100dc5d840951577b26274749dd099d3bf94982b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:03 +0200 Subject: pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 14 +++++++------- .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 14 +++++++------- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 6 +++--- 6 files changed, 36 insertions(+), 36 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4fe63408b3d0..4fb82c1989e1 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -29,9 +29,9 @@ mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(wen1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) @@ -48,7 +48,7 @@ mpp29 29 gpio, ge1(txd1), dev(ale0) mpp30 30 gpio, ge1(txd2), dev(oen) mpp31 31 gpio, ge1(txd3), dev(ale1) mpp32 32 gpio, ge1(txctl), dev(wen0) -mpp33 33 gpio, m(decc_err), dev(ad3) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) mpp36 36 gpio, ptp(trig), dev(a0) @@ -58,20 +58,20 @@ mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) +mpp51 51 gpio, tdm2c(dtx), audio(sdo), dram(deccerr) mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) mpp57 57 gpio, spi1(sck), sd0(clk) mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 182a0597b71f..8271cd21eaae 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -28,9 +28,9 @@ mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd) +mpp14 14 gpio, dram(vttctrl), dev(wen1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda) +mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) @@ -47,7 +47,7 @@ mpp29 29 gpio, dev(ale0), ge(txd1) mpp30 30 gpio, dev(oen), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) mpp32 32 gpio, dev(wen0), ge(txctl) -mpp33 33 gpio, m(decc), dev(ad3) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0) @@ -57,20 +57,20 @@ mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp48 48 gpio, sata0(present) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd) +mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) -mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd) +mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 96e7744cab84..cefca173366e 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -39,7 +39,7 @@ mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) -mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) +mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) @@ -51,7 +51,7 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi(mosi) @@ -64,7 +64,7 @@ mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), - mem(bat) + dram(bat) mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index eb4b0d8dfe58..2b0492395dc6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -109,7 +109,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), @@ -123,7 +123,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), @@ -220,7 +220,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(1, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -275,8 +275,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(43, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), MPP_MODE(44, @@ -302,7 +302,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), @@ -325,7 +325,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), @@ -357,7 +357,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 4cf702447618..7cbc3fb87d48 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -98,7 +98,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(15, @@ -108,7 +108,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)), MPP_MODE(16, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)), MPP_MODE(17, @@ -198,7 +198,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6920_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -251,8 +251,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(43, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6920_PLUS), - MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), @@ -280,7 +280,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS), + MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS), @@ -303,7 +303,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928), - MPP_VAR_FUNCTION(5, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -337,7 +337,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(56, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS), + MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(57, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index d7cdb146f44d..93b0485bc886 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -152,7 +152,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "mem", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -211,7 +211,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS), @@ -264,7 +264,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "mem", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), -- cgit v1.2.3 From 52f83174b3a142a7574f7aa652dcff773c50f5f1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:04 +0200 Subject: pinctrl: mvebu: armada-39x: normalize SATA present functionality naming This commit makes the naming of SATA related MPP functions consistent accross SoCs by adjusting the Armada 39x definition to use "prsnt" instead of "present". Since only the subnames are changed, the DT binding is not modified at all. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../pinctrl/marvell,armada-39x-pinctrl.txt | 16 +++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 24 +++++++++++----------- 2 files changed, 20 insertions(+), 20 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 8271cd21eaae..46f7a5df85c8 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -33,9 +33,9 @@ mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) -mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) -mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) +mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) @@ -58,17 +58,17 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) -mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 7cbc3fb87d48..f6cc7f17f51b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -123,20 +123,20 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)), MPP_MODE(20, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)), MPP_MODE(21, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), @@ -258,8 +258,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -274,12 +274,12 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), @@ -314,16 +314,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata1", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata0", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), -- cgit v1.2.3 From ddf3f19e21ab4472c3ce4aa53dc2d28d4aa07e02 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:05 +0200 Subject: pinctrl: mvebu: armada-39x: normalize SDIO pin naming In order to be consistent with the datasheet and some other SoCs, this commit renames the SDIO pins of the Armada 39x from "sd" to "sd0". While this changes the DT binding, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet (so now is the right time to fix such things). Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../pinctrl/marvell,armada-39x-pinctrl.txt | 40 +++++++++++----------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 40 +++++++++++----------- 2 files changed, 40 insertions(+), 40 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 46f7a5df85c8..d36cb94018de 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -35,14 +35,14 @@ mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) -mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0) -mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1) -mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout) -mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(readyn) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) +mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) mpp30 30 gpio, dev(oen), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) @@ -51,10 +51,10 @@ mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0) -mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk) -mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1) -mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) -mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) +mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) +mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) +mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) +mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) @@ -62,17 +62,17 @@ mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd(d3), ua3(txd) -mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) +mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) +mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) -mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) -mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6928 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index f6cc7f17f51b..fa3042a3a7f2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -137,7 +137,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, @@ -153,31 +153,31 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6920_PLUS)), MPP_MODE(26, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6920_PLUS)), MPP_MODE(27, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txclkout", V_88F6920_PLUS)), MPP_MODE(28, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txd0", V_88F6920_PLUS)), MPP_MODE(29, @@ -212,27 +212,27 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ref", "clk", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)), MPP_MODE(39, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd2", V_88F6920_PLUS)), MPP_MODE(40, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sd", "d2", V_88F6920_PLUS), + MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd3", V_88F6920_PLUS)), MPP_MODE(41, @@ -283,21 +283,21 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d5", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)), MPP_MODE(50, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "cmd", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)), MPP_MODE(51, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -310,7 +310,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d6", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -318,20 +318,20 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), - MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), MPP_MODE(55, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "rxd", V_88F6920_PLUS)), MPP_MODE(56, @@ -343,21 +343,21 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "clk", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(58, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)), MPP_MODE(59, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sd", "d2", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6920_PLUS)), }; static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info; -- cgit v1.2.3 From 7bd6a26db6f9dade7dbd88a73120d17da1ee0e89 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:06 +0200 Subject: pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 6 +++--- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 8 ++++---- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 6 +++--- .../devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 10 +++++----- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 10 +++++----- 8 files changed, 30 insertions(+), 30 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index e357b020861d..183c4723d9c8 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) mpp31 31 gpio, tclk, ge0(txerr) mpp32 32 gpio, spi0(cs0) mpp33 33 gpio, dev(bootcs), spi0(cs0) -mpp34 34 gpo, dev(wen0), spi0(mosi) -mpp35 35 gpo, dev(oen), spi0(sck) +mpp34 34 gpo, dev(we0), spi0(mosi) +mpp35 35 gpo, dev(oe), spi0(sck) mpp36 36 gpo, dev(a1), spi0(miso) mpp37 37 gpo, dev(a0), sata0(prsnt) mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) @@ -88,7 +88,7 @@ mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), audio(sdi) -mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index e22ec5eadcbd..ce1771bd9106 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -26,7 +26,7 @@ mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstoutn), pcie1(rstoutn) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) @@ -59,7 +59,7 @@ mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) -mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0) +mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) @@ -70,13 +70,13 @@ mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) -mpp57 57 gpio, ge0(txctl), ge1(txctl) +mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) mpp58 58 gpio, led(c0) mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(trig), led(p2) +mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4fb82c1989e1..9844773032c5 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -29,7 +29,7 @@ mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) -mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(wen1), pcie3(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) @@ -45,9 +45,9 @@ mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2) mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5) mpp29 29 gpio, ge1(txd1), dev(ale0) -mpp30 30 gpio, ge1(txd2), dev(oen) +mpp30 30 gpio, ge1(txd2), dev(oe) mpp31 31 gpio, ge1(txd3), dev(ale1) -mpp32 32 gpio, ge1(txctl), dev(wen0) +mpp32 32 gpio, ge1(txctl), dev(we0) mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index d36cb94018de..34af69ef321d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -28,7 +28,7 @@ mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, dram(vttctrl), dev(wen1), ua1(txd) +mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) @@ -38,15 +38,15 @@ mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(readyn) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) -mpp30 30 gpio, dev(oen), ge(txd2) +mpp30 30 gpio, dev(oe), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) -mpp32 32 gpio, dev(wen0), ge(txctl) +mpp32 32 gpio, dev(we0), ge(txctl) mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) @@ -55,7 +55,7 @@ mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 8516cadcb9a9..7d2be71f0237 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -207,11 +207,11 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x2, "spi0", "cs0")), MPP_MODE(34, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "dev", "wen0"), + MPP_FUNCTION(0x1, "dev", "we0"), MPP_FUNCTION(0x2, "spi0", "mosi")), MPP_MODE(35, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "dev", "oen"), + MPP_FUNCTION(0x1, "dev", "oe"), MPP_FUNCTION(0x2, "spi0", "sck")), MPP_MODE(36, MPP_FUNCTION(0x0, "gpo", NULL), @@ -352,7 +352,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x5, "audio", "sdi")), MPP_MODE(61, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "dev", "wen1"), + MPP_FUNCTION(0x1, "dev", "we1"), MPP_FUNCTION(0x2, "uart1", "txd"), MPP_FUNCTION(0x5, "audio", "rclk")), MPP_MODE(62, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index ba0913ac2197..6dfe1bfff575 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -120,7 +120,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ale")), MPP_MODE(13, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "dev", "readyn"), + MPP_FUNCTION(0x1, "dev", "ready"), MPP_FUNCTION(0x2, "pcie0", "rstoutn"), MPP_FUNCTION(0x3, "pcie1", "rstoutn"), MPP_FUNCTION(0x5, "nand", "rb"), @@ -284,7 +284,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x1, "led", "p0"), MPP_FUNCTION(0x2, "ge0", "txd0"), MPP_FUNCTION(0x3, "ge1", "txd0"), - MPP_FUNCTION(0x6, "dev", "wen1")), + MPP_FUNCTION(0x6, "dev", "we1")), MPP_MODE(47, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "led", "p1"), @@ -351,7 +351,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge0", "txctl"), MPP_FUNCTION(0x3, "ge1", "txctl"), - MPP_FUNCTION(0x6, "dev", "wen0")), + MPP_FUNCTION(0x6, "dev", "we0")), MPP_MODE(58, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x4, "led", "c0")), @@ -379,7 +379,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ptp", "trig"), MPP_FUNCTION(0x4, "led", "p2"), - MPP_FUNCTION(0x6, "dev", "burst")), + MPP_FUNCTION(0x6, "dev", "burst/last")), MPP_MODE(64, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "dram", "vttctrl"), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 2b0492395dc6..793d0dfec220 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -111,7 +111,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), @@ -209,7 +209,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(30, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6810_PLUS)), MPP_MODE(31, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS), @@ -217,7 +217,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(32, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6810_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index fa3042a3a7f2..a5e362714df8 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -99,7 +99,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -154,7 +154,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6920_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS), @@ -186,7 +186,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)), MPP_MODE(30, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txd2", V_88F6920_PLUS)), MPP_MODE(31, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -194,7 +194,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)), MPP_MODE(32, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)), MPP_MODE(33, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -240,7 +240,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "dev", "burstn", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), MPP_MODE(42, -- cgit v1.2.3 From 5cc0de1faff6ac801286dfab88e4a31392cbb3f0 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:07 +0200 Subject: pinctrl: mvebu: armada-39x: align NAND pin naming All SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions. It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names. While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 34af69ef321d..b6bd9cc09af8 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -55,9 +55,9 @@ mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nd(rbn0), ge(rxctl) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nd(rbn1) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index a5e362714df8..de91b3598653 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -241,7 +241,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6920_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -255,7 +255,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)), + MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), -- cgit v1.2.3 From ed06aeefdac348cfb91a3db5fe1067e3202afd70 Mon Sep 17 00:00:00 2001 From: Christophe Ricard Date: Tue, 9 Jun 2015 22:26:05 +0200 Subject: nfc: st-nci: Rename st21nfcb to st-nci STMicroelectronics NFC NCI chips family is extending with the new ST21NFCC using the AMS AS39230 RF booster. The st21nfcb driver is relevant for this solution and might be with future products. Signed-off-by: Christophe Ricard Signed-off-by: Samuel Ortiz --- .../devicetree/bindings/net/nfc/st-nci.txt | 33 + .../devicetree/bindings/net/nfc/st21nfcb.txt | 33 - drivers/nfc/Kconfig | 2 +- drivers/nfc/Makefile | 2 +- drivers/nfc/st-nci/Kconfig | 23 + drivers/nfc/st-nci/Makefile | 9 + drivers/nfc/st-nci/core.c | 179 ++++++ drivers/nfc/st-nci/i2c.c | 385 +++++++++++ drivers/nfc/st-nci/ndlc.c | 313 +++++++++ drivers/nfc/st-nci/ndlc.h | 60 ++ drivers/nfc/st-nci/st-nci.h | 50 ++ drivers/nfc/st-nci/st-nci_se.c | 714 +++++++++++++++++++++ drivers/nfc/st-nci/st-nci_se.h | 61 ++ drivers/nfc/st21nfcb/Kconfig | 22 - drivers/nfc/st21nfcb/Makefile | 9 - drivers/nfc/st21nfcb/i2c.c | 384 ----------- drivers/nfc/st21nfcb/ndlc.c | 313 --------- drivers/nfc/st21nfcb/ndlc.h | 60 -- drivers/nfc/st21nfcb/st21nfcb.c | 179 ------ drivers/nfc/st21nfcb/st21nfcb.h | 50 -- drivers/nfc/st21nfcb/st21nfcb_se.c | 713 -------------------- drivers/nfc/st21nfcb/st21nfcb_se.h | 61 -- include/linux/platform_data/st-nci.h | 29 + include/linux/platform_data/st21nfcb.h | 29 - include/linux/platform_data/st_nci.h | 29 + 25 files changed, 1887 insertions(+), 1855 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/nfc/st-nci.txt delete mode 100644 Documentation/devicetree/bindings/net/nfc/st21nfcb.txt create mode 100644 drivers/nfc/st-nci/Kconfig create mode 100644 drivers/nfc/st-nci/Makefile create mode 100644 drivers/nfc/st-nci/core.c create mode 100644 drivers/nfc/st-nci/i2c.c create mode 100644 drivers/nfc/st-nci/ndlc.c create mode 100644 drivers/nfc/st-nci/ndlc.h create mode 100644 drivers/nfc/st-nci/st-nci.h create mode 100644 drivers/nfc/st-nci/st-nci_se.c create mode 100644 drivers/nfc/st-nci/st-nci_se.h delete mode 100644 drivers/nfc/st21nfcb/Kconfig delete mode 100644 drivers/nfc/st21nfcb/Makefile delete mode 100644 drivers/nfc/st21nfcb/i2c.c delete mode 100644 drivers/nfc/st21nfcb/ndlc.c delete mode 100644 drivers/nfc/st21nfcb/ndlc.h delete mode 100644 drivers/nfc/st21nfcb/st21nfcb.c delete mode 100644 drivers/nfc/st21nfcb/st21nfcb.h delete mode 100644 drivers/nfc/st21nfcb/st21nfcb_se.c delete mode 100644 drivers/nfc/st21nfcb/st21nfcb_se.h create mode 100644 include/linux/platform_data/st-nci.h delete mode 100644 include/linux/platform_data/st21nfcb.h create mode 100644 include/linux/platform_data/st_nci.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/nfc/st-nci.txt b/Documentation/devicetree/bindings/net/nfc/st-nci.txt new file mode 100644 index 000000000000..d707588ed734 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/st-nci.txt @@ -0,0 +1,33 @@ +* STMicroelectronics SAS. ST NCI NFC Controller + +Required properties: +- compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c". +- clock-frequency: I²C work frequency. +- reg: address on the bus +- interrupt-parent: phandle for the interrupt gpio controller +- interrupts: GPIO interrupt to which the chip is connected +- reset-gpios: Output GPIO pin used to reset the ST21NFCB + +Optional SoC Specific Properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. + +Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): + +&i2c2 { + + status = "okay"; + + st21nfcb: st21nfcb@8 { + + compatible = "st,st21nfcb-i2c"; + + reg = <0x08>; + clock-frequency = <400000>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + + reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt b/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt deleted file mode 100644 index bb237072dbe9..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt +++ /dev/null @@ -1,33 +0,0 @@ -* STMicroelectronics SAS. ST21NFCB NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupt-parent: phandle for the interrupt gpio controller -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): - -&i2c2 { - - status = "okay"; - - st21nfcb: st21nfcb@8 { - - compatible = "st,st21nfcb-i2c"; - - reg = <0x08>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/drivers/nfc/Kconfig b/drivers/nfc/Kconfig index 107714e4405f..722673cb785b 100644 --- a/drivers/nfc/Kconfig +++ b/drivers/nfc/Kconfig @@ -72,6 +72,6 @@ source "drivers/nfc/pn544/Kconfig" source "drivers/nfc/microread/Kconfig" source "drivers/nfc/nfcmrvl/Kconfig" source "drivers/nfc/st21nfca/Kconfig" -source "drivers/nfc/st21nfcb/Kconfig" +source "drivers/nfc/st-nci/Kconfig" source "drivers/nfc/nxp-nci/Kconfig" endmenu diff --git a/drivers/nfc/Makefile b/drivers/nfc/Makefile index 13b648baf175..368b6dfe71b3 100644 --- a/drivers/nfc/Makefile +++ b/drivers/nfc/Makefile @@ -12,5 +12,5 @@ obj-$(CONFIG_NFC_PORT100) += port100.o obj-$(CONFIG_NFC_MRVL) += nfcmrvl/ obj-$(CONFIG_NFC_TRF7970A) += trf7970a.o obj-$(CONFIG_NFC_ST21NFCA) += st21nfca/ -obj-$(CONFIG_NFC_ST21NFCB) += st21nfcb/ +obj-$(CONFIG_NFC_ST_NCI) += st-nci/ obj-$(CONFIG_NFC_NXP_NCI) += nxp-nci/ diff --git a/drivers/nfc/st-nci/Kconfig b/drivers/nfc/st-nci/Kconfig new file mode 100644 index 000000000000..fc3904c946ee --- /dev/null +++ b/drivers/nfc/st-nci/Kconfig @@ -0,0 +1,23 @@ +config NFC_ST_NCI + tristate "STMicroelectronics ST NCI NFC driver" + depends on NFC_NCI + default n + ---help--- + STMicroelectronics NFC NCI chips core driver. It implements the chipset + NCI logic and hooks into the NFC kernel APIs. Physical layers will + register against it. + + To compile this driver as a module, choose m here. The module will + be called st-nci. + Say N if unsure. + +config NFC_ST_NCI_I2C + tristate "NFC ST NCI i2c support" + depends on NFC_ST_NCI && I2C + ---help--- + This module adds support for an I2C interface to the + STMicroelectronics NFC NCI chips familly. + Select this if your platform is using the i2c bus. + + If you choose to build a module, it'll be called st-nci_i2c. + Say N if unsure. diff --git a/drivers/nfc/st-nci/Makefile b/drivers/nfc/st-nci/Makefile new file mode 100644 index 000000000000..0df157df3a94 --- /dev/null +++ b/drivers/nfc/st-nci/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for ST21NFCB NCI based NFC driver +# + +st-nci-objs = ndlc.o core.o st-nci_se.o +obj-$(CONFIG_NFC_ST_NCI) += st-nci.o + +st-nci_i2c-objs = i2c.o +obj-$(CONFIG_NFC_ST_NCI_I2C) += st-nci_i2c.o diff --git a/drivers/nfc/st-nci/core.c b/drivers/nfc/st-nci/core.c new file mode 100644 index 000000000000..c419d3943973 --- /dev/null +++ b/drivers/nfc/st-nci/core.c @@ -0,0 +1,179 @@ +/* + * NCI based Driver for STMicroelectronics NFC Chip + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include "st-nci.h" +#include "st-nci_se.h" + +#define DRIVER_DESC "NCI NFC driver for ST_NCI" + +#define ST_NCI1_X_PROPRIETARY_ISO15693 0x83 + +static int st_nci_init(struct nci_dev *ndev) +{ + struct nci_mode_set_cmd cmd; + + cmd.cmd_type = ST_NCI_SET_NFC_MODE; + cmd.mode = 1; + + return nci_prop_cmd(ndev, ST_NCI_CORE_PROP, + sizeof(struct nci_mode_set_cmd), (__u8 *)&cmd); +} + +static int st_nci_open(struct nci_dev *ndev) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + int r; + + if (test_and_set_bit(ST_NCI_RUNNING, &info->flags)) + return 0; + + r = ndlc_open(info->ndlc); + if (r) + clear_bit(ST_NCI_RUNNING, &info->flags); + + return r; +} + +static int st_nci_close(struct nci_dev *ndev) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + if (!test_bit(ST_NCI_RUNNING, &info->flags)) + return 0; + + ndlc_close(info->ndlc); + + clear_bit(ST_NCI_RUNNING, &info->flags); + + return 0; +} + +static int st_nci_send(struct nci_dev *ndev, struct sk_buff *skb) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + skb->dev = (void *)ndev; + + if (!test_bit(ST_NCI_RUNNING, &info->flags)) + return -EBUSY; + + return ndlc_send(info->ndlc, skb); +} + +static __u32 st_nci_get_rfprotocol(struct nci_dev *ndev, + __u8 rf_protocol) +{ + return rf_protocol == ST_NCI1_X_PROPRIETARY_ISO15693 ? + NFC_PROTO_ISO15693_MASK : 0; +} + +static int st_nci_prop_rsp_packet(struct nci_dev *ndev, + struct sk_buff *skb) +{ + __u8 status = skb->data[0]; + + nci_req_complete(ndev, status); + return 0; +} + +static struct nci_prop_ops st_nci_prop_ops[] = { + { + .opcode = nci_opcode_pack(NCI_GID_PROPRIETARY, + ST_NCI_CORE_PROP), + .rsp = st_nci_prop_rsp_packet, + }, +}; + +static struct nci_ops st_nci_ops = { + .init = st_nci_init, + .open = st_nci_open, + .close = st_nci_close, + .send = st_nci_send, + .get_rfprotocol = st_nci_get_rfprotocol, + .discover_se = st_nci_discover_se, + .enable_se = st_nci_enable_se, + .disable_se = st_nci_disable_se, + .se_io = st_nci_se_io, + .hci_load_session = st_nci_hci_load_session, + .hci_event_received = st_nci_hci_event_received, + .hci_cmd_received = st_nci_hci_cmd_received, + .prop_ops = st_nci_prop_ops, + .n_prop_ops = ARRAY_SIZE(st_nci_prop_ops), +}; + +int st_nci_probe(struct llt_ndlc *ndlc, int phy_headroom, + int phy_tailroom) +{ + struct st_nci_info *info; + int r; + u32 protocols; + + info = devm_kzalloc(ndlc->dev, + sizeof(struct st_nci_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + protocols = NFC_PROTO_JEWEL_MASK + | NFC_PROTO_MIFARE_MASK + | NFC_PROTO_FELICA_MASK + | NFC_PROTO_ISO14443_MASK + | NFC_PROTO_ISO14443_B_MASK + | NFC_PROTO_ISO15693_MASK + | NFC_PROTO_NFC_DEP_MASK; + + ndlc->ndev = nci_allocate_device(&st_nci_ops, protocols, + phy_headroom, phy_tailroom); + if (!ndlc->ndev) { + pr_err("Cannot allocate nfc ndev\n"); + return -ENOMEM; + } + info->ndlc = ndlc; + + nci_set_drvdata(ndlc->ndev, info); + + r = nci_register_device(ndlc->ndev); + if (r) { + pr_err("Cannot register nfc device to nci core\n"); + nci_free_device(ndlc->ndev); + return r; + } + + return st_nci_se_init(ndlc->ndev); +} +EXPORT_SYMBOL_GPL(st_nci_probe); + +void st_nci_remove(struct nci_dev *ndev) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + ndlc_close(info->ndlc); + + nci_unregister_device(ndev); + nci_free_device(ndev); +} +EXPORT_SYMBOL_GPL(st_nci_remove); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/nfc/st-nci/i2c.c b/drivers/nfc/st-nci/i2c.c new file mode 100644 index 000000000000..06175ce769bb --- /dev/null +++ b/drivers/nfc/st-nci/i2c.c @@ -0,0 +1,385 @@ +/* + * I2C Link Layer for ST NCI NFC controller familly based Driver + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ndlc.h" + +#define DRIVER_DESC "NCI NFC driver for ST21NFCB" + +/* ndlc header */ +#define ST21NFCB_FRAME_HEADROOM 1 +#define ST21NFCB_FRAME_TAILROOM 0 + +#define ST_NCI_I2C_MIN_SIZE 4 /* PCB(1) + NCI Packet header(3) */ +#define ST_NCI_I2C_MAX_SIZE 250 /* req 4.2.1 */ + +#define ST_NCI_I2C_DRIVER_NAME "st_nci_i2c" + +static struct i2c_device_id st_nci_i2c_id_table[] = { + {ST_NCI_DRIVER_NAME, 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, st_nci_i2c_id_table); + +struct st_nci_i2c_phy { + struct i2c_client *i2c_dev; + struct llt_ndlc *ndlc; + + unsigned int gpio_reset; + unsigned int irq_polarity; +}; + +#define I2C_DUMP_SKB(info, skb) \ +do { \ + pr_debug("%s:\n", info); \ + print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ + 16, 1, (skb)->data, (skb)->len, 0); \ +} while (0) + +static int st_nci_i2c_enable(void *phy_id) +{ + struct st_nci_i2c_phy *phy = phy_id; + + gpio_set_value(phy->gpio_reset, 0); + usleep_range(10000, 15000); + gpio_set_value(phy->gpio_reset, 1); + usleep_range(80000, 85000); + + if (phy->ndlc->powered == 0) + enable_irq(phy->i2c_dev->irq); + + return 0; +} + +static void st_nci_i2c_disable(void *phy_id) +{ + struct st_nci_i2c_phy *phy = phy_id; + + disable_irq_nosync(phy->i2c_dev->irq); +} + +/* + * Writing a frame must not return the number of written bytes. + * It must return either zero for success, or <0 for error. + * In addition, it must not alter the skb + */ +static int st_nci_i2c_write(void *phy_id, struct sk_buff *skb) +{ + int r = -1; + struct st_nci_i2c_phy *phy = phy_id; + struct i2c_client *client = phy->i2c_dev; + + I2C_DUMP_SKB("st_nci_i2c_write", skb); + + if (phy->ndlc->hard_fault != 0) + return phy->ndlc->hard_fault; + + r = i2c_master_send(client, skb->data, skb->len); + if (r < 0) { /* Retry, chip was in standby */ + usleep_range(1000, 4000); + r = i2c_master_send(client, skb->data, skb->len); + } + + if (r >= 0) { + if (r != skb->len) + r = -EREMOTEIO; + else + r = 0; + } + + return r; +} + +/* + * Reads an ndlc frame and returns it in a newly allocated sk_buff. + * returns: + * frame size : if received frame is complete (find ST21NFCB_SOF_EOF at + * end of read) + * -EAGAIN : if received frame is incomplete (not find ST21NFCB_SOF_EOF + * at end of read) + * -EREMOTEIO : i2c read error (fatal) + * -EBADMSG : frame was incorrect and discarded + * (value returned from st_nci_i2c_repack) + * -EIO : if no ST21NFCB_SOF_EOF is found after reaching + * the read length end sequence + */ +static int st_nci_i2c_read(struct st_nci_i2c_phy *phy, + struct sk_buff **skb) +{ + int r; + u8 len; + u8 buf[ST_NCI_I2C_MAX_SIZE]; + struct i2c_client *client = phy->i2c_dev; + + r = i2c_master_recv(client, buf, ST_NCI_I2C_MIN_SIZE); + if (r < 0) { /* Retry, chip was in standby */ + usleep_range(1000, 4000); + r = i2c_master_recv(client, buf, ST_NCI_I2C_MIN_SIZE); + } + + if (r != ST_NCI_I2C_MIN_SIZE) + return -EREMOTEIO; + + len = be16_to_cpu(*(__be16 *) (buf + 2)); + if (len > ST_NCI_I2C_MAX_SIZE) { + nfc_err(&client->dev, "invalid frame len\n"); + return -EBADMSG; + } + + *skb = alloc_skb(ST_NCI_I2C_MIN_SIZE + len, GFP_KERNEL); + if (*skb == NULL) + return -ENOMEM; + + skb_reserve(*skb, ST_NCI_I2C_MIN_SIZE); + skb_put(*skb, ST_NCI_I2C_MIN_SIZE); + memcpy((*skb)->data, buf, ST_NCI_I2C_MIN_SIZE); + + if (!len) + return 0; + + r = i2c_master_recv(client, buf, len); + if (r != len) { + kfree_skb(*skb); + return -EREMOTEIO; + } + + skb_put(*skb, len); + memcpy((*skb)->data + ST_NCI_I2C_MIN_SIZE, buf, len); + + I2C_DUMP_SKB("i2c frame read", *skb); + + return 0; +} + +/* + * Reads an ndlc frame from the chip. + * + * On ST21NFCB, IRQ goes in idle state when read starts. + */ +static irqreturn_t st_nci_irq_thread_fn(int irq, void *phy_id) +{ + struct st_nci_i2c_phy *phy = phy_id; + struct i2c_client *client; + struct sk_buff *skb = NULL; + int r; + + if (!phy || !phy->ndlc || irq != phy->i2c_dev->irq) { + WARN_ON_ONCE(1); + return IRQ_NONE; + } + + client = phy->i2c_dev; + dev_dbg(&client->dev, "IRQ\n"); + + if (phy->ndlc->hard_fault) + return IRQ_HANDLED; + + if (!phy->ndlc->powered) { + st_nci_i2c_disable(phy); + return IRQ_HANDLED; + } + + r = st_nci_i2c_read(phy, &skb); + if (r == -EREMOTEIO || r == -ENOMEM || r == -EBADMSG) + return IRQ_HANDLED; + + ndlc_recv(phy->ndlc, skb); + + return IRQ_HANDLED; +} + +static struct nfc_phy_ops i2c_phy_ops = { + .write = st_nci_i2c_write, + .enable = st_nci_i2c_enable, + .disable = st_nci_i2c_disable, +}; + +#ifdef CONFIG_OF +static int st_nci_i2c_of_request_resources(struct i2c_client *client) +{ + struct st_nci_i2c_phy *phy = i2c_get_clientdata(client); + struct device_node *pp; + int gpio; + int r; + + pp = client->dev.of_node; + if (!pp) + return -ENODEV; + + /* Get GPIO from device tree */ + gpio = of_get_named_gpio(pp, "reset-gpios", 0); + if (gpio < 0) { + nfc_err(&client->dev, + "Failed to retrieve reset-gpios from device tree\n"); + return gpio; + } + + /* GPIO request and configuration */ + r = devm_gpio_request_one(&client->dev, gpio, + GPIOF_OUT_INIT_HIGH, "clf_reset"); + if (r) { + nfc_err(&client->dev, "Failed to request reset pin\n"); + return r; + } + phy->gpio_reset = gpio; + + phy->irq_polarity = irq_get_trigger_type(client->irq); + + return 0; +} +#else +static int st_nci_i2c_of_request_resources(struct i2c_client *client) +{ + return -ENODEV; +} +#endif + +static int st_nci_i2c_request_resources(struct i2c_client *client) +{ + struct st_nci_nfc_platform_data *pdata; + struct st_nci_i2c_phy *phy = i2c_get_clientdata(client); + int r; + + pdata = client->dev.platform_data; + if (pdata == NULL) { + nfc_err(&client->dev, "No platform data\n"); + return -EINVAL; + } + + /* store for later use */ + phy->gpio_reset = pdata->gpio_reset; + phy->irq_polarity = pdata->irq_polarity; + + r = devm_gpio_request_one(&client->dev, + phy->gpio_reset, GPIOF_OUT_INIT_HIGH, "clf_reset"); + if (r) { + pr_err("%s : reset gpio_request failed\n", __FILE__); + return r; + } + + return 0; +} + +static int st_nci_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct st_nci_i2c_phy *phy; + struct st_nci_nfc_platform_data *pdata; + int r; + + dev_dbg(&client->dev, "%s\n", __func__); + dev_dbg(&client->dev, "IRQ: %d\n", client->irq); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); + return -ENODEV; + } + + phy = devm_kzalloc(&client->dev, sizeof(struct st_nci_i2c_phy), + GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->i2c_dev = client; + + i2c_set_clientdata(client, phy); + + pdata = client->dev.platform_data; + if (!pdata && client->dev.of_node) { + r = st_nci_i2c_of_request_resources(client); + if (r) { + nfc_err(&client->dev, "No platform data\n"); + return r; + } + } else if (pdata) { + r = st_nci_i2c_request_resources(client); + if (r) { + nfc_err(&client->dev, + "Cannot get platform resources\n"); + return r; + } + } else { + nfc_err(&client->dev, + "st21nfcb platform resources not available\n"); + return -ENODEV; + } + + r = ndlc_probe(phy, &i2c_phy_ops, &client->dev, + ST21NFCB_FRAME_HEADROOM, ST21NFCB_FRAME_TAILROOM, + &phy->ndlc); + if (r < 0) { + nfc_err(&client->dev, "Unable to register ndlc layer\n"); + return r; + } + + r = devm_request_threaded_irq(&client->dev, client->irq, NULL, + st_nci_irq_thread_fn, + phy->irq_polarity | IRQF_ONESHOT, + ST_NCI_DRIVER_NAME, phy); + if (r < 0) + nfc_err(&client->dev, "Unable to register IRQ handler\n"); + + return r; +} + +static int st_nci_i2c_remove(struct i2c_client *client) +{ + struct st_nci_i2c_phy *phy = i2c_get_clientdata(client); + + dev_dbg(&client->dev, "%s\n", __func__); + + ndlc_remove(phy->ndlc); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id of_st_nci_i2c_match[] = { + { .compatible = "st,st21nfcb-i2c", }, + { .compatible = "st,st21nfcb_i2c", }, + { .compatible = "st,st21nfcc-i2c", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_st_nci_i2c_match); +#endif + +static struct i2c_driver st_nci_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = ST_NCI_I2C_DRIVER_NAME, + .of_match_table = of_match_ptr(of_st_nci_i2c_match), + }, + .probe = st_nci_i2c_probe, + .id_table = st_nci_i2c_id_table, + .remove = st_nci_i2c_remove, +}; + +module_i2c_driver(st_nci_i2c_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/nfc/st-nci/ndlc.c b/drivers/nfc/st-nci/ndlc.c new file mode 100644 index 000000000000..56c6a4cb4c96 --- /dev/null +++ b/drivers/nfc/st-nci/ndlc.c @@ -0,0 +1,313 @@ +/* + * Low Level Transport (NDLC) Driver for STMicroelectronics NFC Chip + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include + +#include "ndlc.h" +#include "st-nci.h" + +#define NDLC_TIMER_T1 100 +#define NDLC_TIMER_T1_WAIT 400 +#define NDLC_TIMER_T2 1200 + +#define PCB_TYPE_DATAFRAME 0x80 +#define PCB_TYPE_SUPERVISOR 0xc0 +#define PCB_TYPE_MASK PCB_TYPE_SUPERVISOR + +#define PCB_SYNC_ACK 0x20 +#define PCB_SYNC_NACK 0x10 +#define PCB_SYNC_WAIT 0x30 +#define PCB_SYNC_NOINFO 0x00 +#define PCB_SYNC_MASK PCB_SYNC_WAIT + +#define PCB_DATAFRAME_RETRANSMIT_YES 0x00 +#define PCB_DATAFRAME_RETRANSMIT_NO 0x04 +#define PCB_DATAFRAME_RETRANSMIT_MASK PCB_DATAFRAME_RETRANSMIT_NO + +#define PCB_SUPERVISOR_RETRANSMIT_YES 0x00 +#define PCB_SUPERVISOR_RETRANSMIT_NO 0x02 +#define PCB_SUPERVISOR_RETRANSMIT_MASK PCB_SUPERVISOR_RETRANSMIT_NO + +#define PCB_FRAME_CRC_INFO_PRESENT 0x08 +#define PCB_FRAME_CRC_INFO_NOTPRESENT 0x00 +#define PCB_FRAME_CRC_INFO_MASK PCB_FRAME_CRC_INFO_PRESENT + +#define NDLC_DUMP_SKB(info, skb) \ +do { \ + pr_debug("%s:\n", info); \ + print_hex_dump(KERN_DEBUG, "ndlc: ", DUMP_PREFIX_OFFSET, \ + 16, 1, skb->data, skb->len, 0); \ +} while (0) + +int ndlc_open(struct llt_ndlc *ndlc) +{ + /* toggle reset pin */ + ndlc->ops->enable(ndlc->phy_id); + ndlc->powered = 1; + return 0; +} +EXPORT_SYMBOL(ndlc_open); + +void ndlc_close(struct llt_ndlc *ndlc) +{ + struct nci_mode_set_cmd cmd; + + cmd.cmd_type = ST_NCI_SET_NFC_MODE; + cmd.mode = 0; + + /* toggle reset pin */ + ndlc->ops->enable(ndlc->phy_id); + + nci_prop_cmd(ndlc->ndev, ST_NCI_CORE_PROP, + sizeof(struct nci_mode_set_cmd), (__u8 *)&cmd); + + ndlc->powered = 0; + ndlc->ops->disable(ndlc->phy_id); +} +EXPORT_SYMBOL(ndlc_close); + +int ndlc_send(struct llt_ndlc *ndlc, struct sk_buff *skb) +{ + /* add ndlc header */ + u8 pcb = PCB_TYPE_DATAFRAME | PCB_DATAFRAME_RETRANSMIT_NO | + PCB_FRAME_CRC_INFO_NOTPRESENT; + + *skb_push(skb, 1) = pcb; + skb_queue_tail(&ndlc->send_q, skb); + + schedule_work(&ndlc->sm_work); + + return 0; +} +EXPORT_SYMBOL(ndlc_send); + +static void llt_ndlc_send_queue(struct llt_ndlc *ndlc) +{ + struct sk_buff *skb; + int r; + unsigned long time_sent; + + if (ndlc->send_q.qlen) + pr_debug("sendQlen=%d unackQlen=%d\n", + ndlc->send_q.qlen, ndlc->ack_pending_q.qlen); + + while (ndlc->send_q.qlen) { + skb = skb_dequeue(&ndlc->send_q); + NDLC_DUMP_SKB("ndlc frame written", skb); + r = ndlc->ops->write(ndlc->phy_id, skb); + if (r < 0) { + ndlc->hard_fault = r; + break; + } + time_sent = jiffies; + *(unsigned long *)skb->cb = time_sent; + + skb_queue_tail(&ndlc->ack_pending_q, skb); + + /* start timer t1 for ndlc aknowledge */ + ndlc->t1_active = true; + mod_timer(&ndlc->t1_timer, time_sent + + msecs_to_jiffies(NDLC_TIMER_T1)); + /* start timer t2 for chip availability */ + ndlc->t2_active = true; + mod_timer(&ndlc->t2_timer, time_sent + + msecs_to_jiffies(NDLC_TIMER_T2)); + } +} + +static void llt_ndlc_requeue_data_pending(struct llt_ndlc *ndlc) +{ + struct sk_buff *skb; + u8 pcb; + + while ((skb = skb_dequeue_tail(&ndlc->ack_pending_q))) { + pcb = skb->data[0]; + switch (pcb & PCB_TYPE_MASK) { + case PCB_TYPE_SUPERVISOR: + skb->data[0] = (pcb & ~PCB_SUPERVISOR_RETRANSMIT_MASK) | + PCB_SUPERVISOR_RETRANSMIT_YES; + break; + case PCB_TYPE_DATAFRAME: + skb->data[0] = (pcb & ~PCB_DATAFRAME_RETRANSMIT_MASK) | + PCB_DATAFRAME_RETRANSMIT_YES; + break; + default: + pr_err("UNKNOWN Packet Control Byte=%d\n", pcb); + kfree_skb(skb); + continue; + } + skb_queue_head(&ndlc->send_q, skb); + } +} + +static void llt_ndlc_rcv_queue(struct llt_ndlc *ndlc) +{ + struct sk_buff *skb; + u8 pcb; + unsigned long time_sent; + + if (ndlc->rcv_q.qlen) + pr_debug("rcvQlen=%d\n", ndlc->rcv_q.qlen); + + while ((skb = skb_dequeue(&ndlc->rcv_q)) != NULL) { + pcb = skb->data[0]; + skb_pull(skb, 1); + if ((pcb & PCB_TYPE_MASK) == PCB_TYPE_SUPERVISOR) { + switch (pcb & PCB_SYNC_MASK) { + case PCB_SYNC_ACK: + del_timer_sync(&ndlc->t1_timer); + del_timer_sync(&ndlc->t2_timer); + ndlc->t2_active = false; + ndlc->t1_active = false; + break; + case PCB_SYNC_NACK: + llt_ndlc_requeue_data_pending(ndlc); + llt_ndlc_send_queue(ndlc); + /* start timer t1 for ndlc aknowledge */ + time_sent = jiffies; + ndlc->t1_active = true; + mod_timer(&ndlc->t1_timer, time_sent + + msecs_to_jiffies(NDLC_TIMER_T1)); + break; + case PCB_SYNC_WAIT: + time_sent = jiffies; + ndlc->t1_active = true; + mod_timer(&ndlc->t1_timer, time_sent + + msecs_to_jiffies(NDLC_TIMER_T1_WAIT)); + break; + default: + pr_err("UNKNOWN Packet Control Byte=%d\n", pcb); + kfree_skb(skb); + break; + } + } else { + nci_recv_frame(ndlc->ndev, skb); + } + } +} + +static void llt_ndlc_sm_work(struct work_struct *work) +{ + struct llt_ndlc *ndlc = container_of(work, struct llt_ndlc, sm_work); + + llt_ndlc_send_queue(ndlc); + llt_ndlc_rcv_queue(ndlc); + + if (ndlc->t1_active && timer_pending(&ndlc->t1_timer) == 0) { + pr_debug + ("Handle T1(recv SUPERVISOR) elapsed (T1 now inactive)\n"); + ndlc->t1_active = false; + + llt_ndlc_requeue_data_pending(ndlc); + llt_ndlc_send_queue(ndlc); + } + + if (ndlc->t2_active && timer_pending(&ndlc->t2_timer) == 0) { + pr_debug("Handle T2(recv DATA) elapsed (T2 now inactive)\n"); + ndlc->t2_active = false; + ndlc->t1_active = false; + del_timer_sync(&ndlc->t1_timer); + del_timer_sync(&ndlc->t2_timer); + ndlc_close(ndlc); + ndlc->hard_fault = -EREMOTEIO; + } +} + +void ndlc_recv(struct llt_ndlc *ndlc, struct sk_buff *skb) +{ + if (skb == NULL) { + pr_err("NULL Frame -> link is dead\n"); + ndlc->hard_fault = -EREMOTEIO; + ndlc_close(ndlc); + } else { + NDLC_DUMP_SKB("incoming frame", skb); + skb_queue_tail(&ndlc->rcv_q, skb); + } + + schedule_work(&ndlc->sm_work); +} +EXPORT_SYMBOL(ndlc_recv); + +static void ndlc_t1_timeout(unsigned long data) +{ + struct llt_ndlc *ndlc = (struct llt_ndlc *)data; + + pr_debug("\n"); + + schedule_work(&ndlc->sm_work); +} + +static void ndlc_t2_timeout(unsigned long data) +{ + struct llt_ndlc *ndlc = (struct llt_ndlc *)data; + + pr_debug("\n"); + + schedule_work(&ndlc->sm_work); +} + +int ndlc_probe(void *phy_id, struct nfc_phy_ops *phy_ops, struct device *dev, + int phy_headroom, int phy_tailroom, struct llt_ndlc **ndlc_id) +{ + struct llt_ndlc *ndlc; + + ndlc = devm_kzalloc(dev, sizeof(struct llt_ndlc), GFP_KERNEL); + if (!ndlc) + return -ENOMEM; + + ndlc->ops = phy_ops; + ndlc->phy_id = phy_id; + ndlc->dev = dev; + ndlc->powered = 0; + + *ndlc_id = ndlc; + + /* initialize timers */ + init_timer(&ndlc->t1_timer); + ndlc->t1_timer.data = (unsigned long)ndlc; + ndlc->t1_timer.function = ndlc_t1_timeout; + + init_timer(&ndlc->t2_timer); + ndlc->t2_timer.data = (unsigned long)ndlc; + ndlc->t2_timer.function = ndlc_t2_timeout; + + skb_queue_head_init(&ndlc->rcv_q); + skb_queue_head_init(&ndlc->send_q); + skb_queue_head_init(&ndlc->ack_pending_q); + + INIT_WORK(&ndlc->sm_work, llt_ndlc_sm_work); + + return st_nci_probe(ndlc, phy_headroom, phy_tailroom); +} +EXPORT_SYMBOL(ndlc_probe); + +void ndlc_remove(struct llt_ndlc *ndlc) +{ + st_nci_remove(ndlc->ndev); + + /* cancel timers */ + del_timer_sync(&ndlc->t1_timer); + del_timer_sync(&ndlc->t2_timer); + ndlc->t2_active = false; + ndlc->t1_active = false; + + skb_queue_purge(&ndlc->rcv_q); + skb_queue_purge(&ndlc->send_q); +} +EXPORT_SYMBOL(ndlc_remove); diff --git a/drivers/nfc/st-nci/ndlc.h b/drivers/nfc/st-nci/ndlc.h new file mode 100644 index 000000000000..6361005ef003 --- /dev/null +++ b/drivers/nfc/st-nci/ndlc.h @@ -0,0 +1,60 @@ +/* + * NCI based Driver for STMicroelectronics NFC Chip + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef __LOCAL_NDLC_H_ +#define __LOCAL_NDLC_H_ + +#include +#include + +/* Low Level Transport description */ +struct llt_ndlc { + struct nci_dev *ndev; + struct nfc_phy_ops *ops; + void *phy_id; + + struct timer_list t1_timer; + bool t1_active; + + struct timer_list t2_timer; + bool t2_active; + + struct sk_buff_head rcv_q; + struct sk_buff_head send_q; + struct sk_buff_head ack_pending_q; + + struct work_struct sm_work; + + struct device *dev; + + /* + * < 0 if hardware error occurred + * and prevents normal operation. + */ + int hard_fault; + int powered; +}; + +int ndlc_open(struct llt_ndlc *ndlc); +void ndlc_close(struct llt_ndlc *ndlc); +int ndlc_send(struct llt_ndlc *ndlc, struct sk_buff *skb); +void ndlc_recv(struct llt_ndlc *ndlc, struct sk_buff *skb); +int ndlc_probe(void *phy_id, struct nfc_phy_ops *phy_ops, struct device *dev, + int phy_headroom, int phy_tailroom, struct llt_ndlc **ndlc_id); +void ndlc_remove(struct llt_ndlc *ndlc); +#endif /* __LOCAL_NDLC_H__ */ diff --git a/drivers/nfc/st-nci/st-nci.h b/drivers/nfc/st-nci/st-nci.h new file mode 100644 index 000000000000..850a2395deb7 --- /dev/null +++ b/drivers/nfc/st-nci/st-nci.h @@ -0,0 +1,50 @@ +/* + * NCI based Driver for STMicroelectronics NFC Chip + * + * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef __LOCAL_ST_NCI_H_ +#define __LOCAL_ST_NCI_H_ + +#include "st-nci_se.h" +#include "ndlc.h" + +/* Define private flags: */ +#define ST_NCI_RUNNING 1 + +#define ST_NCI_CORE_PROP 0x01 +#define ST_NCI_SET_NFC_MODE 0x02 + +struct nci_mode_set_cmd { + u8 cmd_type; + u8 mode; +} __packed; + +struct nci_mode_set_rsp { + u8 status; +} __packed; + +struct st_nci_info { + struct llt_ndlc *ndlc; + unsigned long flags; + struct st_nci_se_info se_info; +}; + +void st_nci_remove(struct nci_dev *ndev); +int st_nci_probe(struct llt_ndlc *ndlc, int phy_headroom, + int phy_tailroom); + +#endif /* __LOCAL_ST_NCI_H_ */ diff --git a/drivers/nfc/st-nci/st-nci_se.c b/drivers/nfc/st-nci/st-nci_se.c new file mode 100644 index 000000000000..97addfa96c6f --- /dev/null +++ b/drivers/nfc/st-nci/st-nci_se.c @@ -0,0 +1,714 @@ +/* + * Secure Element driver for STMicroelectronics NFC NCI chip + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include +#include +#include + +#include "st-nci.h" +#include "st-nci_se.h" + +struct st_nci_pipe_info { + u8 pipe_state; + u8 src_host_id; + u8 src_gate_id; + u8 dst_host_id; + u8 dst_gate_id; +} __packed; + +/* Hosts */ +#define ST_NCI_HOST_CONTROLLER_ID 0x00 +#define ST_NCI_TERMINAL_HOST_ID 0x01 +#define ST_NCI_UICC_HOST_ID 0x02 +#define ST_NCI_ESE_HOST_ID 0xc0 + +/* Gates */ +#define ST_NCI_DEVICE_MGNT_GATE 0x01 +#define ST_NCI_APDU_READER_GATE 0xf0 +#define ST_NCI_CONNECTIVITY_GATE 0x41 + +/* Pipes */ +#define ST_NCI_DEVICE_MGNT_PIPE 0x02 + +/* Connectivity pipe only */ +#define ST_NCI_SE_COUNT_PIPE_UICC 0x01 +/* Connectivity + APDU Reader pipe */ +#define ST_NCI_SE_COUNT_PIPE_EMBEDDED 0x02 + +#define ST_NCI_SE_TO_HOT_PLUG 1000 /* msecs */ +#define ST_NCI_SE_TO_PIPES 2000 + +#define ST_NCI_EVT_HOT_PLUG_IS_INHIBITED(x) (x->data[0] & 0x80) + +#define NCI_HCI_APDU_PARAM_ATR 0x01 +#define NCI_HCI_ADMIN_PARAM_SESSION_IDENTITY 0x01 +#define NCI_HCI_ADMIN_PARAM_WHITELIST 0x03 +#define NCI_HCI_ADMIN_PARAM_HOST_LIST 0x04 + +#define ST_NCI_EVT_SE_HARD_RESET 0x20 +#define ST_NCI_EVT_TRANSMIT_DATA 0x10 +#define ST_NCI_EVT_WTX_REQUEST 0x11 +#define ST_NCI_EVT_SE_SOFT_RESET 0x11 +#define ST_NCI_EVT_SE_END_OF_APDU_TRANSFER 0x21 +#define ST_NCI_EVT_HOT_PLUG 0x03 + +#define ST_NCI_SE_MODE_OFF 0x00 +#define ST_NCI_SE_MODE_ON 0x01 + +#define ST_NCI_EVT_CONNECTIVITY 0x10 +#define ST_NCI_EVT_TRANSACTION 0x12 + +#define ST_NCI_DM_GETINFO 0x13 +#define ST_NCI_DM_GETINFO_PIPE_LIST 0x02 +#define ST_NCI_DM_GETINFO_PIPE_INFO 0x01 +#define ST_NCI_DM_PIPE_CREATED 0x02 +#define ST_NCI_DM_PIPE_OPEN 0x04 +#define ST_NCI_DM_RF_ACTIVE 0x80 +#define ST_NCI_DM_DISCONNECT 0x30 + +#define ST_NCI_DM_IS_PIPE_OPEN(p) \ + ((p & 0x0f) == (ST_NCI_DM_PIPE_CREATED | ST_NCI_DM_PIPE_OPEN)) + +#define ST_NCI_ATR_DEFAULT_BWI 0x04 + +/* + * WT = 2^BWI/10[s], convert into msecs and add a secure + * room by increasing by 2 this timeout + */ +#define ST_NCI_BWI_TO_TIMEOUT(x) ((1 << x) * 200) +#define ST_NCI_ATR_GET_Y_FROM_TD(x) (x >> 4) + +/* If TA is present bit 0 is set */ +#define ST_NCI_ATR_TA_PRESENT(x) (x & 0x01) +/* If TB is present bit 1 is set */ +#define ST_NCI_ATR_TB_PRESENT(x) (x & 0x02) + +#define ST_NCI_NUM_DEVICES 256 + +static DECLARE_BITMAP(dev_mask, ST_NCI_NUM_DEVICES); + +/* Here are the mandatory pipe for st_nci */ +static struct nci_hci_gate st_nci_gates[] = { + {NCI_HCI_ADMIN_GATE, NCI_HCI_ADMIN_PIPE, + ST_NCI_HOST_CONTROLLER_ID}, + {NCI_HCI_LINK_MGMT_GATE, NCI_HCI_LINK_MGMT_PIPE, + ST_NCI_HOST_CONTROLLER_ID}, + {ST_NCI_DEVICE_MGNT_GATE, ST_NCI_DEVICE_MGNT_PIPE, + ST_NCI_HOST_CONTROLLER_ID}, + + /* Secure element pipes are created by secure element host */ + {ST_NCI_CONNECTIVITY_GATE, NCI_HCI_DO_NOT_OPEN_PIPE, + ST_NCI_HOST_CONTROLLER_ID}, + {ST_NCI_APDU_READER_GATE, NCI_HCI_DO_NOT_OPEN_PIPE, + ST_NCI_HOST_CONTROLLER_ID}, +}; + +static u8 st_nci_se_get_bwi(struct nci_dev *ndev) +{ + int i; + u8 td; + struct st_nci_info *info = nci_get_drvdata(ndev); + + /* Bits 8 to 5 of the first TB for T=1 encode BWI from zero to nine */ + for (i = 1; i < ST_NCI_ESE_MAX_LENGTH; i++) { + td = ST_NCI_ATR_GET_Y_FROM_TD(info->se_info.atr[i]); + if (ST_NCI_ATR_TA_PRESENT(td)) + i++; + if (ST_NCI_ATR_TB_PRESENT(td)) { + i++; + return info->se_info.atr[i] >> 4; + } + } + return ST_NCI_ATR_DEFAULT_BWI; +} + +static void st_nci_se_get_atr(struct nci_dev *ndev) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + int r; + struct sk_buff *skb; + + r = nci_hci_get_param(ndev, ST_NCI_APDU_READER_GATE, + NCI_HCI_APDU_PARAM_ATR, &skb); + if (r < 0) + return; + + if (skb->len <= ST_NCI_ESE_MAX_LENGTH) { + memcpy(info->se_info.atr, skb->data, skb->len); + + info->se_info.wt_timeout = + ST_NCI_BWI_TO_TIMEOUT(st_nci_se_get_bwi(ndev)); + } + kfree_skb(skb); +} + +int st_nci_hci_load_session(struct nci_dev *ndev) +{ + int i, j, r; + struct sk_buff *skb_pipe_list, *skb_pipe_info; + struct st_nci_pipe_info *dm_pipe_info; + u8 pipe_list[] = { ST_NCI_DM_GETINFO_PIPE_LIST, + ST_NCI_TERMINAL_HOST_ID}; + u8 pipe_info[] = { ST_NCI_DM_GETINFO_PIPE_INFO, + ST_NCI_TERMINAL_HOST_ID, 0}; + + /* On ST_NCI device pipes number are dynamics + * If pipes are already created, hci_dev_up will fail. + * Doing a clear all pipe is a bad idea because: + * - It does useless EEPROM cycling + * - It might cause issue for secure elements support + * (such as removing connectivity or APDU reader pipe) + * A better approach on ST_NCI is to: + * - get a pipe list for each host. + * (eg: ST_NCI_HOST_CONTROLLER_ID for now). + * (TODO Later on UICC HOST and eSE HOST) + * - get pipe information + * - match retrieved pipe list in st_nci_gates + * ST_NCI_DEVICE_MGNT_GATE is a proprietary gate + * with ST_NCI_DEVICE_MGNT_PIPE. + * Pipe can be closed and need to be open. + */ + r = nci_hci_connect_gate(ndev, ST_NCI_HOST_CONTROLLER_ID, + ST_NCI_DEVICE_MGNT_GATE, + ST_NCI_DEVICE_MGNT_PIPE); + if (r < 0) + goto free_info; + + /* Get pipe list */ + r = nci_hci_send_cmd(ndev, ST_NCI_DEVICE_MGNT_GATE, + ST_NCI_DM_GETINFO, pipe_list, sizeof(pipe_list), + &skb_pipe_list); + if (r < 0) + goto free_info; + + /* Complete the existing gate_pipe table */ + for (i = 0; i < skb_pipe_list->len; i++) { + pipe_info[2] = skb_pipe_list->data[i]; + r = nci_hci_send_cmd(ndev, ST_NCI_DEVICE_MGNT_GATE, + ST_NCI_DM_GETINFO, pipe_info, + sizeof(pipe_info), &skb_pipe_info); + + if (r) + continue; + + /* + * Match pipe ID and gate ID + * Output format from ST21NFC_DM_GETINFO is: + * - pipe state (1byte) + * - source hid (1byte) + * - source gid (1byte) + * - destination hid (1byte) + * - destination gid (1byte) + */ + dm_pipe_info = (struct st_nci_pipe_info *)skb_pipe_info->data; + if (dm_pipe_info->dst_gate_id == ST_NCI_APDU_READER_GATE && + dm_pipe_info->src_host_id != ST_NCI_ESE_HOST_ID) { + pr_err("Unexpected apdu_reader pipe on host %x\n", + dm_pipe_info->src_host_id); + continue; + } + + for (j = 0; (j < ARRAY_SIZE(st_nci_gates)) && + (st_nci_gates[j].gate != dm_pipe_info->dst_gate_id); j++) + ; + + if (j < ARRAY_SIZE(st_nci_gates) && + st_nci_gates[j].gate == dm_pipe_info->dst_gate_id && + ST_NCI_DM_IS_PIPE_OPEN(dm_pipe_info->pipe_state)) { + st_nci_gates[j].pipe = pipe_info[2]; + + ndev->hci_dev->gate2pipe[st_nci_gates[j].gate] = + st_nci_gates[j].pipe; + ndev->hci_dev->pipes[st_nci_gates[j].pipe].gate = + st_nci_gates[j].gate; + ndev->hci_dev->pipes[st_nci_gates[j].pipe].host = + dm_pipe_info->src_host_id; + } + } + + memcpy(ndev->hci_dev->init_data.gates, st_nci_gates, + sizeof(st_nci_gates)); + +free_info: + kfree_skb(skb_pipe_info); + kfree_skb(skb_pipe_list); + return r; +} +EXPORT_SYMBOL_GPL(st_nci_hci_load_session); + +static void st_nci_hci_admin_event_received(struct nci_dev *ndev, + u8 event, struct sk_buff *skb) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + switch (event) { + case ST_NCI_EVT_HOT_PLUG: + if (info->se_info.se_active) { + if (!ST_NCI_EVT_HOT_PLUG_IS_INHIBITED(skb)) { + del_timer_sync(&info->se_info.se_active_timer); + info->se_info.se_active = false; + complete(&info->se_info.req_completion); + } else { + mod_timer(&info->se_info.se_active_timer, + jiffies + + msecs_to_jiffies(ST_NCI_SE_TO_PIPES)); + } + } + break; + } +} + +static int st_nci_hci_apdu_reader_event_received(struct nci_dev *ndev, + u8 event, + struct sk_buff *skb) +{ + int r = 0; + struct st_nci_info *info = nci_get_drvdata(ndev); + + pr_debug("apdu reader gate event: %x\n", event); + + switch (event) { + case ST_NCI_EVT_TRANSMIT_DATA: + del_timer_sync(&info->se_info.bwi_timer); + info->se_info.bwi_active = false; + info->se_info.cb(info->se_info.cb_context, + skb->data, skb->len, 0); + break; + case ST_NCI_EVT_WTX_REQUEST: + mod_timer(&info->se_info.bwi_timer, jiffies + + msecs_to_jiffies(info->se_info.wt_timeout)); + break; + } + + kfree_skb(skb); + return r; +} + +/* + * Returns: + * <= 0: driver handled the event, skb consumed + * 1: driver does not handle the event, please do standard processing + */ +static int st_nci_hci_connectivity_event_received(struct nci_dev *ndev, + u8 host, u8 event, + struct sk_buff *skb) +{ + int r = 0; + struct device *dev = &ndev->nfc_dev->dev; + struct nfc_evt_transaction *transaction; + + pr_debug("connectivity gate event: %x\n", event); + + switch (event) { + case ST_NCI_EVT_CONNECTIVITY: + + break; + case ST_NCI_EVT_TRANSACTION: + /* According to specification etsi 102 622 + * 11.2.2.4 EVT_TRANSACTION Table 52 + * Description Tag Length + * AID 81 5 to 16 + * PARAMETERS 82 0 to 255 + */ + if (skb->len < NFC_MIN_AID_LENGTH + 2 && + skb->data[0] != NFC_EVT_TRANSACTION_AID_TAG) + return -EPROTO; + + transaction = (struct nfc_evt_transaction *)devm_kzalloc(dev, + skb->len - 2, GFP_KERNEL); + + transaction->aid_len = skb->data[1]; + memcpy(transaction->aid, &skb->data[2], transaction->aid_len); + + /* Check next byte is PARAMETERS tag (82) */ + if (skb->data[transaction->aid_len + 2] != + NFC_EVT_TRANSACTION_PARAMS_TAG) + return -EPROTO; + + transaction->params_len = skb->data[transaction->aid_len + 3]; + memcpy(transaction->params, skb->data + + transaction->aid_len + 4, transaction->params_len); + + r = nfc_se_transaction(ndev->nfc_dev, host, transaction); + break; + default: + return 1; + } + kfree_skb(skb); + return r; +} + +void st_nci_hci_event_received(struct nci_dev *ndev, u8 pipe, + u8 event, struct sk_buff *skb) +{ + u8 gate = ndev->hci_dev->pipes[pipe].gate; + u8 host = ndev->hci_dev->pipes[pipe].host; + + switch (gate) { + case NCI_HCI_ADMIN_GATE: + st_nci_hci_admin_event_received(ndev, event, skb); + break; + case ST_NCI_APDU_READER_GATE: + st_nci_hci_apdu_reader_event_received(ndev, event, skb); + break; + case ST_NCI_CONNECTIVITY_GATE: + st_nci_hci_connectivity_event_received(ndev, host, event, + skb); + break; + } +} +EXPORT_SYMBOL_GPL(st_nci_hci_event_received); + + +void st_nci_hci_cmd_received(struct nci_dev *ndev, u8 pipe, u8 cmd, + struct sk_buff *skb) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + u8 gate = ndev->hci_dev->pipes[pipe].gate; + + pr_debug("cmd: %x\n", cmd); + + switch (cmd) { + case NCI_HCI_ANY_OPEN_PIPE: + if (gate != ST_NCI_APDU_READER_GATE && + ndev->hci_dev->pipes[pipe].host != ST_NCI_UICC_HOST_ID) + ndev->hci_dev->count_pipes++; + + if (ndev->hci_dev->count_pipes == + ndev->hci_dev->expected_pipes) { + del_timer_sync(&info->se_info.se_active_timer); + info->se_info.se_active = false; + ndev->hci_dev->count_pipes = 0; + complete(&info->se_info.req_completion); + } + break; + } +} +EXPORT_SYMBOL_GPL(st_nci_hci_cmd_received); + +/* + * Remarks: On some early st_nci firmware, nci_nfcee_mode_set(0) + * is rejected + */ +static int st_nci_control_se(struct nci_dev *ndev, u8 se_idx, + u8 state) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + int r; + struct sk_buff *sk_host_list; + u8 host_id; + + switch (se_idx) { + case ST_NCI_UICC_HOST_ID: + ndev->hci_dev->count_pipes = 0; + ndev->hci_dev->expected_pipes = ST_NCI_SE_COUNT_PIPE_UICC; + break; + case ST_NCI_ESE_HOST_ID: + ndev->hci_dev->count_pipes = 0; + ndev->hci_dev->expected_pipes = ST_NCI_SE_COUNT_PIPE_EMBEDDED; + break; + default: + return -EINVAL; + } + + /* + * Wait for an EVT_HOT_PLUG in order to + * retrieve a relevant host list. + */ + reinit_completion(&info->se_info.req_completion); + r = nci_nfcee_mode_set(ndev, se_idx, NCI_NFCEE_ENABLE); + if (r != NCI_STATUS_OK) + return r; + + mod_timer(&info->se_info.se_active_timer, jiffies + + msecs_to_jiffies(ST_NCI_SE_TO_HOT_PLUG)); + info->se_info.se_active = true; + + /* Ignore return value and check in any case the host_list */ + wait_for_completion_interruptible(&info->se_info.req_completion); + + /* There might be some "collision" after receiving a HOT_PLUG event + * This may cause the CLF to not answer to the next hci command. + * There is no possible synchronization to prevent this. + * Adding a small delay is the only way to solve the issue. + */ + usleep_range(3000, 5000); + + r = nci_hci_get_param(ndev, NCI_HCI_ADMIN_GATE, + NCI_HCI_ADMIN_PARAM_HOST_LIST, &sk_host_list); + if (r != NCI_HCI_ANY_OK) + return r; + + host_id = sk_host_list->data[sk_host_list->len - 1]; + kfree_skb(sk_host_list); + if (state == ST_NCI_SE_MODE_ON && host_id == se_idx) + return se_idx; + else if (state == ST_NCI_SE_MODE_OFF && host_id != se_idx) + return se_idx; + + return -1; +} + +int st_nci_disable_se(struct nci_dev *ndev, u32 se_idx) +{ + int r; + + pr_debug("st_nci_disable_se\n"); + + if (se_idx == NFC_SE_EMBEDDED) { + r = nci_hci_send_event(ndev, ST_NCI_APDU_READER_GATE, + ST_NCI_EVT_SE_END_OF_APDU_TRANSFER, NULL, 0); + if (r < 0) + return r; + } + + return 0; +} +EXPORT_SYMBOL_GPL(st_nci_disable_se); + +int st_nci_enable_se(struct nci_dev *ndev, u32 se_idx) +{ + int r; + + pr_debug("st_nci_enable_se\n"); + + if (se_idx == ST_NCI_HCI_HOST_ID_ESE) { + r = nci_hci_send_event(ndev, ST_NCI_APDU_READER_GATE, + ST_NCI_EVT_SE_SOFT_RESET, NULL, 0); + if (r < 0) + return r; + } + + return 0; +} +EXPORT_SYMBOL_GPL(st_nci_enable_se); + +static int st_nci_hci_network_init(struct nci_dev *ndev) +{ + struct core_conn_create_dest_spec_params *dest_params; + struct dest_spec_params spec_params; + struct nci_conn_info *conn_info; + int r, dev_num; + + dest_params = + kzalloc(sizeof(struct core_conn_create_dest_spec_params) + + sizeof(struct dest_spec_params), GFP_KERNEL); + if (dest_params == NULL) { + r = -ENOMEM; + goto exit; + } + + dest_params->type = NCI_DESTINATION_SPECIFIC_PARAM_NFCEE_TYPE; + dest_params->length = sizeof(struct dest_spec_params); + spec_params.id = ndev->hci_dev->nfcee_id; + spec_params.protocol = NCI_NFCEE_INTERFACE_HCI_ACCESS; + memcpy(dest_params->value, &spec_params, + sizeof(struct dest_spec_params)); + r = nci_core_conn_create(ndev, NCI_DESTINATION_NFCEE, 1, + sizeof(struct core_conn_create_dest_spec_params) + + sizeof(struct dest_spec_params), + dest_params); + if (r != NCI_STATUS_OK) + goto free_dest_params; + + conn_info = ndev->hci_dev->conn_info; + if (!conn_info) + goto free_dest_params; + + memcpy(ndev->hci_dev->init_data.gates, st_nci_gates, + sizeof(st_nci_gates)); + + /* + * Session id must include the driver name + i2c bus addr + * persistent info to discriminate 2 identical chips + */ + dev_num = find_first_zero_bit(dev_mask, ST_NCI_NUM_DEVICES); + if (dev_num >= ST_NCI_NUM_DEVICES) { + r = -ENODEV; + goto free_dest_params; + } + + scnprintf(ndev->hci_dev->init_data.session_id, + sizeof(ndev->hci_dev->init_data.session_id), + "%s%2x", "ST21BH", dev_num); + + r = nci_hci_dev_session_init(ndev); + if (r != NCI_HCI_ANY_OK) + goto free_dest_params; + + r = nci_nfcee_mode_set(ndev, ndev->hci_dev->conn_info->id, + NCI_NFCEE_ENABLE); + if (r != NCI_STATUS_OK) + goto free_dest_params; + +free_dest_params: + kfree(dest_params); + +exit: + return r; +} + +int st_nci_discover_se(struct nci_dev *ndev) +{ + u8 param[2]; + int r; + int se_count = 0; + + pr_debug("st_nci_discover_se\n"); + + r = st_nci_hci_network_init(ndev); + if (r != 0) + return r; + + param[0] = ST_NCI_UICC_HOST_ID; + param[1] = ST_NCI_HCI_HOST_ID_ESE; + r = nci_hci_set_param(ndev, NCI_HCI_ADMIN_GATE, + NCI_HCI_ADMIN_PARAM_WHITELIST, + param, sizeof(param)); + if (r != NCI_HCI_ANY_OK) + return r; + + r = st_nci_control_se(ndev, ST_NCI_UICC_HOST_ID, + ST_NCI_SE_MODE_ON); + if (r == ST_NCI_UICC_HOST_ID) { + nfc_add_se(ndev->nfc_dev, ST_NCI_UICC_HOST_ID, NFC_SE_UICC); + se_count++; + } + + /* Try to enable eSE in order to check availability */ + r = st_nci_control_se(ndev, ST_NCI_HCI_HOST_ID_ESE, + ST_NCI_SE_MODE_ON); + if (r == ST_NCI_HCI_HOST_ID_ESE) { + nfc_add_se(ndev->nfc_dev, ST_NCI_HCI_HOST_ID_ESE, + NFC_SE_EMBEDDED); + se_count++; + st_nci_se_get_atr(ndev); + } + + return !se_count; +} +EXPORT_SYMBOL_GPL(st_nci_discover_se); + +int st_nci_se_io(struct nci_dev *ndev, u32 se_idx, + u8 *apdu, size_t apdu_length, + se_io_cb_t cb, void *cb_context) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + pr_debug("\n"); + + switch (se_idx) { + case ST_NCI_HCI_HOST_ID_ESE: + info->se_info.cb = cb; + info->se_info.cb_context = cb_context; + mod_timer(&info->se_info.bwi_timer, jiffies + + msecs_to_jiffies(info->se_info.wt_timeout)); + info->se_info.bwi_active = true; + return nci_hci_send_event(ndev, ST_NCI_APDU_READER_GATE, + ST_NCI_EVT_TRANSMIT_DATA, apdu, + apdu_length); + default: + return -ENODEV; + } +} +EXPORT_SYMBOL(st_nci_se_io); + +static void st_nci_se_wt_timeout(unsigned long data) +{ + /* + * No answer from the secure element + * within the defined timeout. + * Let's send a reset request as recovery procedure. + * According to the situation, we first try to send a software reset + * to the secure element. If the next command is still not + * answering in time, we send to the CLF a secure element hardware + * reset request. + */ + /* hardware reset managed through VCC_UICC_OUT power supply */ + u8 param = 0x01; + struct st_nci_info *info = (struct st_nci_info *) data; + + pr_debug("\n"); + + info->se_info.bwi_active = false; + + if (!info->se_info.xch_error) { + info->se_info.xch_error = true; + nci_hci_send_event(info->ndlc->ndev, ST_NCI_APDU_READER_GATE, + ST_NCI_EVT_SE_SOFT_RESET, NULL, 0); + } else { + info->se_info.xch_error = false; + nci_hci_send_event(info->ndlc->ndev, ST_NCI_DEVICE_MGNT_GATE, + ST_NCI_EVT_SE_HARD_RESET, ¶m, 1); + } + info->se_info.cb(info->se_info.cb_context, NULL, 0, -ETIME); +} + +static void st_nci_se_activation_timeout(unsigned long data) +{ + struct st_nci_info *info = (struct st_nci_info *) data; + + pr_debug("\n"); + + info->se_info.se_active = false; + + complete(&info->se_info.req_completion); +} + +int st_nci_se_init(struct nci_dev *ndev) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + init_completion(&info->se_info.req_completion); + /* initialize timers */ + init_timer(&info->se_info.bwi_timer); + info->se_info.bwi_timer.data = (unsigned long)info; + info->se_info.bwi_timer.function = st_nci_se_wt_timeout; + info->se_info.bwi_active = false; + + init_timer(&info->se_info.se_active_timer); + info->se_info.se_active_timer.data = (unsigned long)info; + info->se_info.se_active_timer.function = + st_nci_se_activation_timeout; + info->se_info.se_active = false; + + info->se_info.xch_error = false; + + info->se_info.wt_timeout = + ST_NCI_BWI_TO_TIMEOUT(ST_NCI_ATR_DEFAULT_BWI); + + return 0; +} +EXPORT_SYMBOL(st_nci_se_init); + +void st_nci_se_deinit(struct nci_dev *ndev) +{ + struct st_nci_info *info = nci_get_drvdata(ndev); + + if (info->se_info.bwi_active) + del_timer_sync(&info->se_info.bwi_timer); + if (info->se_info.se_active) + del_timer_sync(&info->se_info.se_active_timer); + + info->se_info.se_active = false; + info->se_info.bwi_active = false; +} +EXPORT_SYMBOL(st_nci_se_deinit); + diff --git a/drivers/nfc/st-nci/st-nci_se.h b/drivers/nfc/st-nci/st-nci_se.h new file mode 100644 index 000000000000..ea66e879d67f --- /dev/null +++ b/drivers/nfc/st-nci/st-nci_se.h @@ -0,0 +1,61 @@ +/* + * Secure Element Driver for STMicroelectronics NFC NCI Chip + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#ifndef __LOCAL_ST_NCI_SE_H_ +#define __LOCAL_ST_NCI_SE_H_ + +/* + * ref ISO7816-3 chap 8.1. the initial character TS is followed by a + * sequence of at most 32 characters. + */ +#define ST_NCI_ESE_MAX_LENGTH 33 +#define ST_NCI_HCI_HOST_ID_ESE 0xc0 + +struct st_nci_se_info { + u8 atr[ST_NCI_ESE_MAX_LENGTH]; + struct completion req_completion; + + struct timer_list bwi_timer; + int wt_timeout; /* in msecs */ + bool bwi_active; + + struct timer_list se_active_timer; + bool se_active; + + bool xch_error; + + se_io_cb_t cb; + void *cb_context; +}; + +int st_nci_se_init(struct nci_dev *ndev); +void st_nci_se_deinit(struct nci_dev *ndev); + +int st_nci_discover_se(struct nci_dev *ndev); +int st_nci_enable_se(struct nci_dev *ndev, u32 se_idx); +int st_nci_disable_se(struct nci_dev *ndev, u32 se_idx); +int st_nci_se_io(struct nci_dev *ndev, u32 se_idx, + u8 *apdu, size_t apdu_length, + se_io_cb_t cb, void *cb_context); +int st_nci_hci_load_session(struct nci_dev *ndev); +void st_nci_hci_event_received(struct nci_dev *ndev, u8 pipe, + u8 event, struct sk_buff *skb); +void st_nci_hci_cmd_received(struct nci_dev *ndev, u8 pipe, u8 cmd, + struct sk_buff *skb); + + +#endif /* __LOCAL_ST_NCI_SE_H_ */ diff --git a/drivers/nfc/st21nfcb/Kconfig b/drivers/nfc/st21nfcb/Kconfig deleted file mode 100644 index e0322dd03a70..000000000000 --- a/drivers/nfc/st21nfcb/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -config NFC_ST21NFCB - tristate "STMicroelectronics ST21NFCB NFC driver" - depends on NFC_NCI - default n - ---help--- - STMicroelectronics ST21NFCB core driver. It implements the chipset - NCI logic and hooks into the NFC kernel APIs. Physical layers will - register against it. - - To compile this driver as a module, choose m here. The module will - be called st21nfcb. - Say N if unsure. - -config NFC_ST21NFCB_I2C - tristate "NFC ST21NFCB i2c support" - depends on NFC_ST21NFCB && I2C - ---help--- - This module adds support for the STMicroelectronics st21nfcb i2c interface. - Select this if your platform is using the i2c bus. - - If you choose to build a module, it'll be called st21nfcb_i2c. - Say N if unsure. diff --git a/drivers/nfc/st21nfcb/Makefile b/drivers/nfc/st21nfcb/Makefile deleted file mode 100644 index ce659a9e5a1a..000000000000 --- a/drivers/nfc/st21nfcb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile for ST21NFCB NCI based NFC driver -# - -st21nfcb_nci-objs = ndlc.o st21nfcb.o st21nfcb_se.o -obj-$(CONFIG_NFC_ST21NFCB) += st21nfcb_nci.o - -st21nfcb_i2c-objs = i2c.o -obj-$(CONFIG_NFC_ST21NFCB_I2C) += st21nfcb_i2c.o diff --git a/drivers/nfc/st21nfcb/i2c.c b/drivers/nfc/st21nfcb/i2c.c deleted file mode 100644 index dbc0dfd8ae85..000000000000 --- a/drivers/nfc/st21nfcb/i2c.c +++ /dev/null @@ -1,384 +0,0 @@ -/* - * I2C Link Layer for ST21NFCB NCI based Driver - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ndlc.h" - -#define DRIVER_DESC "NCI NFC driver for ST21NFCB" - -/* ndlc header */ -#define ST21NFCB_FRAME_HEADROOM 1 -#define ST21NFCB_FRAME_TAILROOM 0 - -#define ST21NFCB_NCI_I2C_MIN_SIZE 4 /* PCB(1) + NCI Packet header(3) */ -#define ST21NFCB_NCI_I2C_MAX_SIZE 250 /* req 4.2.1 */ - -#define ST21NFCB_NCI_I2C_DRIVER_NAME "st21nfcb_nci_i2c" - -static struct i2c_device_id st21nfcb_nci_i2c_id_table[] = { - {ST21NFCB_NCI_DRIVER_NAME, 0}, - {} -}; -MODULE_DEVICE_TABLE(i2c, st21nfcb_nci_i2c_id_table); - -struct st21nfcb_i2c_phy { - struct i2c_client *i2c_dev; - struct llt_ndlc *ndlc; - - unsigned int gpio_reset; - unsigned int irq_polarity; -}; - -#define I2C_DUMP_SKB(info, skb) \ -do { \ - pr_debug("%s:\n", info); \ - print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ - 16, 1, (skb)->data, (skb)->len, 0); \ -} while (0) - -static int st21nfcb_nci_i2c_enable(void *phy_id) -{ - struct st21nfcb_i2c_phy *phy = phy_id; - - gpio_set_value(phy->gpio_reset, 0); - usleep_range(10000, 15000); - gpio_set_value(phy->gpio_reset, 1); - usleep_range(80000, 85000); - - if (phy->ndlc->powered == 0) - enable_irq(phy->i2c_dev->irq); - - return 0; -} - -static void st21nfcb_nci_i2c_disable(void *phy_id) -{ - struct st21nfcb_i2c_phy *phy = phy_id; - - disable_irq_nosync(phy->i2c_dev->irq); -} - -/* - * Writing a frame must not return the number of written bytes. - * It must return either zero for success, or <0 for error. - * In addition, it must not alter the skb - */ -static int st21nfcb_nci_i2c_write(void *phy_id, struct sk_buff *skb) -{ - int r = -1; - struct st21nfcb_i2c_phy *phy = phy_id; - struct i2c_client *client = phy->i2c_dev; - - I2C_DUMP_SKB("st21nfcb_nci_i2c_write", skb); - - if (phy->ndlc->hard_fault != 0) - return phy->ndlc->hard_fault; - - r = i2c_master_send(client, skb->data, skb->len); - if (r < 0) { /* Retry, chip was in standby */ - usleep_range(1000, 4000); - r = i2c_master_send(client, skb->data, skb->len); - } - - if (r >= 0) { - if (r != skb->len) - r = -EREMOTEIO; - else - r = 0; - } - - return r; -} - -/* - * Reads an ndlc frame and returns it in a newly allocated sk_buff. - * returns: - * frame size : if received frame is complete (find ST21NFCB_SOF_EOF at - * end of read) - * -EAGAIN : if received frame is incomplete (not find ST21NFCB_SOF_EOF - * at end of read) - * -EREMOTEIO : i2c read error (fatal) - * -EBADMSG : frame was incorrect and discarded - * (value returned from st21nfcb_nci_i2c_repack) - * -EIO : if no ST21NFCB_SOF_EOF is found after reaching - * the read length end sequence - */ -static int st21nfcb_nci_i2c_read(struct st21nfcb_i2c_phy *phy, - struct sk_buff **skb) -{ - int r; - u8 len; - u8 buf[ST21NFCB_NCI_I2C_MAX_SIZE]; - struct i2c_client *client = phy->i2c_dev; - - r = i2c_master_recv(client, buf, ST21NFCB_NCI_I2C_MIN_SIZE); - if (r < 0) { /* Retry, chip was in standby */ - usleep_range(1000, 4000); - r = i2c_master_recv(client, buf, ST21NFCB_NCI_I2C_MIN_SIZE); - } - - if (r != ST21NFCB_NCI_I2C_MIN_SIZE) - return -EREMOTEIO; - - len = be16_to_cpu(*(__be16 *) (buf + 2)); - if (len > ST21NFCB_NCI_I2C_MAX_SIZE) { - nfc_err(&client->dev, "invalid frame len\n"); - return -EBADMSG; - } - - *skb = alloc_skb(ST21NFCB_NCI_I2C_MIN_SIZE + len, GFP_KERNEL); - if (*skb == NULL) - return -ENOMEM; - - skb_reserve(*skb, ST21NFCB_NCI_I2C_MIN_SIZE); - skb_put(*skb, ST21NFCB_NCI_I2C_MIN_SIZE); - memcpy((*skb)->data, buf, ST21NFCB_NCI_I2C_MIN_SIZE); - - if (!len) - return 0; - - r = i2c_master_recv(client, buf, len); - if (r != len) { - kfree_skb(*skb); - return -EREMOTEIO; - } - - skb_put(*skb, len); - memcpy((*skb)->data + ST21NFCB_NCI_I2C_MIN_SIZE, buf, len); - - I2C_DUMP_SKB("i2c frame read", *skb); - - return 0; -} - -/* - * Reads an ndlc frame from the chip. - * - * On ST21NFCB, IRQ goes in idle state when read starts. - */ -static irqreturn_t st21nfcb_nci_irq_thread_fn(int irq, void *phy_id) -{ - struct st21nfcb_i2c_phy *phy = phy_id; - struct i2c_client *client; - struct sk_buff *skb = NULL; - int r; - - if (!phy || !phy->ndlc || irq != phy->i2c_dev->irq) { - WARN_ON_ONCE(1); - return IRQ_NONE; - } - - client = phy->i2c_dev; - dev_dbg(&client->dev, "IRQ\n"); - - if (phy->ndlc->hard_fault) - return IRQ_HANDLED; - - if (!phy->ndlc->powered) { - st21nfcb_nci_i2c_disable(phy); - return IRQ_HANDLED; - } - - r = st21nfcb_nci_i2c_read(phy, &skb); - if (r == -EREMOTEIO || r == -ENOMEM || r == -EBADMSG) - return IRQ_HANDLED; - - ndlc_recv(phy->ndlc, skb); - - return IRQ_HANDLED; -} - -static struct nfc_phy_ops i2c_phy_ops = { - .write = st21nfcb_nci_i2c_write, - .enable = st21nfcb_nci_i2c_enable, - .disable = st21nfcb_nci_i2c_disable, -}; - -#ifdef CONFIG_OF -static int st21nfcb_nci_i2c_of_request_resources(struct i2c_client *client) -{ - struct st21nfcb_i2c_phy *phy = i2c_get_clientdata(client); - struct device_node *pp; - int gpio; - int r; - - pp = client->dev.of_node; - if (!pp) - return -ENODEV; - - /* Get GPIO from device tree */ - gpio = of_get_named_gpio(pp, "reset-gpios", 0); - if (gpio < 0) { - nfc_err(&client->dev, - "Failed to retrieve reset-gpios from device tree\n"); - return gpio; - } - - /* GPIO request and configuration */ - r = devm_gpio_request_one(&client->dev, gpio, - GPIOF_OUT_INIT_HIGH, "clf_reset"); - if (r) { - nfc_err(&client->dev, "Failed to request reset pin\n"); - return r; - } - phy->gpio_reset = gpio; - - phy->irq_polarity = irq_get_trigger_type(client->irq); - - return 0; -} -#else -static int st21nfcb_nci_i2c_of_request_resources(struct i2c_client *client) -{ - return -ENODEV; -} -#endif - -static int st21nfcb_nci_i2c_request_resources(struct i2c_client *client) -{ - struct st21nfcb_nfc_platform_data *pdata; - struct st21nfcb_i2c_phy *phy = i2c_get_clientdata(client); - int r; - - pdata = client->dev.platform_data; - if (pdata == NULL) { - nfc_err(&client->dev, "No platform data\n"); - return -EINVAL; - } - - /* store for later use */ - phy->gpio_reset = pdata->gpio_reset; - phy->irq_polarity = pdata->irq_polarity; - - r = devm_gpio_request_one(&client->dev, - phy->gpio_reset, GPIOF_OUT_INIT_HIGH, "clf_reset"); - if (r) { - pr_err("%s : reset gpio_request failed\n", __FILE__); - return r; - } - - return 0; -} - -static int st21nfcb_nci_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct st21nfcb_i2c_phy *phy; - struct st21nfcb_nfc_platform_data *pdata; - int r; - - dev_dbg(&client->dev, "%s\n", __func__); - dev_dbg(&client->dev, "IRQ: %d\n", client->irq); - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); - return -ENODEV; - } - - phy = devm_kzalloc(&client->dev, sizeof(struct st21nfcb_i2c_phy), - GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->i2c_dev = client; - - i2c_set_clientdata(client, phy); - - pdata = client->dev.platform_data; - if (!pdata && client->dev.of_node) { - r = st21nfcb_nci_i2c_of_request_resources(client); - if (r) { - nfc_err(&client->dev, "No platform data\n"); - return r; - } - } else if (pdata) { - r = st21nfcb_nci_i2c_request_resources(client); - if (r) { - nfc_err(&client->dev, - "Cannot get platform resources\n"); - return r; - } - } else { - nfc_err(&client->dev, - "st21nfcb platform resources not available\n"); - return -ENODEV; - } - - r = ndlc_probe(phy, &i2c_phy_ops, &client->dev, - ST21NFCB_FRAME_HEADROOM, ST21NFCB_FRAME_TAILROOM, - &phy->ndlc); - if (r < 0) { - nfc_err(&client->dev, "Unable to register ndlc layer\n"); - return r; - } - - r = devm_request_threaded_irq(&client->dev, client->irq, NULL, - st21nfcb_nci_irq_thread_fn, - phy->irq_polarity | IRQF_ONESHOT, - ST21NFCB_NCI_DRIVER_NAME, phy); - if (r < 0) - nfc_err(&client->dev, "Unable to register IRQ handler\n"); - - return r; -} - -static int st21nfcb_nci_i2c_remove(struct i2c_client *client) -{ - struct st21nfcb_i2c_phy *phy = i2c_get_clientdata(client); - - dev_dbg(&client->dev, "%s\n", __func__); - - ndlc_remove(phy->ndlc); - - return 0; -} - -#ifdef CONFIG_OF -static const struct of_device_id of_st21nfcb_i2c_match[] = { - { .compatible = "st,st21nfcb-i2c", }, - { .compatible = "st,st21nfcb_i2c", }, - {} -}; -MODULE_DEVICE_TABLE(of, of_st21nfcb_i2c_match); -#endif - -static struct i2c_driver st21nfcb_nci_i2c_driver = { - .driver = { - .owner = THIS_MODULE, - .name = ST21NFCB_NCI_I2C_DRIVER_NAME, - .of_match_table = of_match_ptr(of_st21nfcb_i2c_match), - }, - .probe = st21nfcb_nci_i2c_probe, - .id_table = st21nfcb_nci_i2c_id_table, - .remove = st21nfcb_nci_i2c_remove, -}; - -module_i2c_driver(st21nfcb_nci_i2c_driver); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/nfc/st21nfcb/ndlc.c b/drivers/nfc/st21nfcb/ndlc.c deleted file mode 100644 index 91e81f37b3a6..000000000000 --- a/drivers/nfc/st21nfcb/ndlc.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Low Level Transport (NDLC) Driver for STMicroelectronics NFC Chip - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#include -#include - -#include "ndlc.h" -#include "st21nfcb.h" - -#define NDLC_TIMER_T1 100 -#define NDLC_TIMER_T1_WAIT 400 -#define NDLC_TIMER_T2 1200 - -#define PCB_TYPE_DATAFRAME 0x80 -#define PCB_TYPE_SUPERVISOR 0xc0 -#define PCB_TYPE_MASK PCB_TYPE_SUPERVISOR - -#define PCB_SYNC_ACK 0x20 -#define PCB_SYNC_NACK 0x10 -#define PCB_SYNC_WAIT 0x30 -#define PCB_SYNC_NOINFO 0x00 -#define PCB_SYNC_MASK PCB_SYNC_WAIT - -#define PCB_DATAFRAME_RETRANSMIT_YES 0x00 -#define PCB_DATAFRAME_RETRANSMIT_NO 0x04 -#define PCB_DATAFRAME_RETRANSMIT_MASK PCB_DATAFRAME_RETRANSMIT_NO - -#define PCB_SUPERVISOR_RETRANSMIT_YES 0x00 -#define PCB_SUPERVISOR_RETRANSMIT_NO 0x02 -#define PCB_SUPERVISOR_RETRANSMIT_MASK PCB_SUPERVISOR_RETRANSMIT_NO - -#define PCB_FRAME_CRC_INFO_PRESENT 0x08 -#define PCB_FRAME_CRC_INFO_NOTPRESENT 0x00 -#define PCB_FRAME_CRC_INFO_MASK PCB_FRAME_CRC_INFO_PRESENT - -#define NDLC_DUMP_SKB(info, skb) \ -do { \ - pr_debug("%s:\n", info); \ - print_hex_dump(KERN_DEBUG, "ndlc: ", DUMP_PREFIX_OFFSET, \ - 16, 1, skb->data, skb->len, 0); \ -} while (0) - -int ndlc_open(struct llt_ndlc *ndlc) -{ - /* toggle reset pin */ - ndlc->ops->enable(ndlc->phy_id); - ndlc->powered = 1; - return 0; -} -EXPORT_SYMBOL(ndlc_open); - -void ndlc_close(struct llt_ndlc *ndlc) -{ - struct nci_mode_set_cmd cmd; - - cmd.cmd_type = ST21NFCB_NCI_SET_NFC_MODE; - cmd.mode = 0; - - /* toggle reset pin */ - ndlc->ops->enable(ndlc->phy_id); - - nci_prop_cmd(ndlc->ndev, ST21NFCB_NCI_CORE_PROP, - sizeof(struct nci_mode_set_cmd), (__u8 *)&cmd); - - ndlc->powered = 0; - ndlc->ops->disable(ndlc->phy_id); -} -EXPORT_SYMBOL(ndlc_close); - -int ndlc_send(struct llt_ndlc *ndlc, struct sk_buff *skb) -{ - /* add ndlc header */ - u8 pcb = PCB_TYPE_DATAFRAME | PCB_DATAFRAME_RETRANSMIT_NO | - PCB_FRAME_CRC_INFO_NOTPRESENT; - - *skb_push(skb, 1) = pcb; - skb_queue_tail(&ndlc->send_q, skb); - - schedule_work(&ndlc->sm_work); - - return 0; -} -EXPORT_SYMBOL(ndlc_send); - -static void llt_ndlc_send_queue(struct llt_ndlc *ndlc) -{ - struct sk_buff *skb; - int r; - unsigned long time_sent; - - if (ndlc->send_q.qlen) - pr_debug("sendQlen=%d unackQlen=%d\n", - ndlc->send_q.qlen, ndlc->ack_pending_q.qlen); - - while (ndlc->send_q.qlen) { - skb = skb_dequeue(&ndlc->send_q); - NDLC_DUMP_SKB("ndlc frame written", skb); - r = ndlc->ops->write(ndlc->phy_id, skb); - if (r < 0) { - ndlc->hard_fault = r; - break; - } - time_sent = jiffies; - *(unsigned long *)skb->cb = time_sent; - - skb_queue_tail(&ndlc->ack_pending_q, skb); - - /* start timer t1 for ndlc aknowledge */ - ndlc->t1_active = true; - mod_timer(&ndlc->t1_timer, time_sent + - msecs_to_jiffies(NDLC_TIMER_T1)); - /* start timer t2 for chip availability */ - ndlc->t2_active = true; - mod_timer(&ndlc->t2_timer, time_sent + - msecs_to_jiffies(NDLC_TIMER_T2)); - } -} - -static void llt_ndlc_requeue_data_pending(struct llt_ndlc *ndlc) -{ - struct sk_buff *skb; - u8 pcb; - - while ((skb = skb_dequeue_tail(&ndlc->ack_pending_q))) { - pcb = skb->data[0]; - switch (pcb & PCB_TYPE_MASK) { - case PCB_TYPE_SUPERVISOR: - skb->data[0] = (pcb & ~PCB_SUPERVISOR_RETRANSMIT_MASK) | - PCB_SUPERVISOR_RETRANSMIT_YES; - break; - case PCB_TYPE_DATAFRAME: - skb->data[0] = (pcb & ~PCB_DATAFRAME_RETRANSMIT_MASK) | - PCB_DATAFRAME_RETRANSMIT_YES; - break; - default: - pr_err("UNKNOWN Packet Control Byte=%d\n", pcb); - kfree_skb(skb); - continue; - } - skb_queue_head(&ndlc->send_q, skb); - } -} - -static void llt_ndlc_rcv_queue(struct llt_ndlc *ndlc) -{ - struct sk_buff *skb; - u8 pcb; - unsigned long time_sent; - - if (ndlc->rcv_q.qlen) - pr_debug("rcvQlen=%d\n", ndlc->rcv_q.qlen); - - while ((skb = skb_dequeue(&ndlc->rcv_q)) != NULL) { - pcb = skb->data[0]; - skb_pull(skb, 1); - if ((pcb & PCB_TYPE_MASK) == PCB_TYPE_SUPERVISOR) { - switch (pcb & PCB_SYNC_MASK) { - case PCB_SYNC_ACK: - del_timer_sync(&ndlc->t1_timer); - del_timer_sync(&ndlc->t2_timer); - ndlc->t2_active = false; - ndlc->t1_active = false; - break; - case PCB_SYNC_NACK: - llt_ndlc_requeue_data_pending(ndlc); - llt_ndlc_send_queue(ndlc); - /* start timer t1 for ndlc aknowledge */ - time_sent = jiffies; - ndlc->t1_active = true; - mod_timer(&ndlc->t1_timer, time_sent + - msecs_to_jiffies(NDLC_TIMER_T1)); - break; - case PCB_SYNC_WAIT: - time_sent = jiffies; - ndlc->t1_active = true; - mod_timer(&ndlc->t1_timer, time_sent + - msecs_to_jiffies(NDLC_TIMER_T1_WAIT)); - break; - default: - pr_err("UNKNOWN Packet Control Byte=%d\n", pcb); - kfree_skb(skb); - break; - } - } else { - nci_recv_frame(ndlc->ndev, skb); - } - } -} - -static void llt_ndlc_sm_work(struct work_struct *work) -{ - struct llt_ndlc *ndlc = container_of(work, struct llt_ndlc, sm_work); - - llt_ndlc_send_queue(ndlc); - llt_ndlc_rcv_queue(ndlc); - - if (ndlc->t1_active && timer_pending(&ndlc->t1_timer) == 0) { - pr_debug - ("Handle T1(recv SUPERVISOR) elapsed (T1 now inactive)\n"); - ndlc->t1_active = false; - - llt_ndlc_requeue_data_pending(ndlc); - llt_ndlc_send_queue(ndlc); - } - - if (ndlc->t2_active && timer_pending(&ndlc->t2_timer) == 0) { - pr_debug("Handle T2(recv DATA) elapsed (T2 now inactive)\n"); - ndlc->t2_active = false; - ndlc->t1_active = false; - del_timer_sync(&ndlc->t1_timer); - del_timer_sync(&ndlc->t2_timer); - ndlc_close(ndlc); - ndlc->hard_fault = -EREMOTEIO; - } -} - -void ndlc_recv(struct llt_ndlc *ndlc, struct sk_buff *skb) -{ - if (skb == NULL) { - pr_err("NULL Frame -> link is dead\n"); - ndlc->hard_fault = -EREMOTEIO; - ndlc_close(ndlc); - } else { - NDLC_DUMP_SKB("incoming frame", skb); - skb_queue_tail(&ndlc->rcv_q, skb); - } - - schedule_work(&ndlc->sm_work); -} -EXPORT_SYMBOL(ndlc_recv); - -static void ndlc_t1_timeout(unsigned long data) -{ - struct llt_ndlc *ndlc = (struct llt_ndlc *)data; - - pr_debug("\n"); - - schedule_work(&ndlc->sm_work); -} - -static void ndlc_t2_timeout(unsigned long data) -{ - struct llt_ndlc *ndlc = (struct llt_ndlc *)data; - - pr_debug("\n"); - - schedule_work(&ndlc->sm_work); -} - -int ndlc_probe(void *phy_id, struct nfc_phy_ops *phy_ops, struct device *dev, - int phy_headroom, int phy_tailroom, struct llt_ndlc **ndlc_id) -{ - struct llt_ndlc *ndlc; - - ndlc = devm_kzalloc(dev, sizeof(struct llt_ndlc), GFP_KERNEL); - if (!ndlc) - return -ENOMEM; - - ndlc->ops = phy_ops; - ndlc->phy_id = phy_id; - ndlc->dev = dev; - ndlc->powered = 0; - - *ndlc_id = ndlc; - - /* initialize timers */ - init_timer(&ndlc->t1_timer); - ndlc->t1_timer.data = (unsigned long)ndlc; - ndlc->t1_timer.function = ndlc_t1_timeout; - - init_timer(&ndlc->t2_timer); - ndlc->t2_timer.data = (unsigned long)ndlc; - ndlc->t2_timer.function = ndlc_t2_timeout; - - skb_queue_head_init(&ndlc->rcv_q); - skb_queue_head_init(&ndlc->send_q); - skb_queue_head_init(&ndlc->ack_pending_q); - - INIT_WORK(&ndlc->sm_work, llt_ndlc_sm_work); - - return st21nfcb_nci_probe(ndlc, phy_headroom, phy_tailroom); -} -EXPORT_SYMBOL(ndlc_probe); - -void ndlc_remove(struct llt_ndlc *ndlc) -{ - st21nfcb_nci_remove(ndlc->ndev); - - /* cancel timers */ - del_timer_sync(&ndlc->t1_timer); - del_timer_sync(&ndlc->t2_timer); - ndlc->t2_active = false; - ndlc->t1_active = false; - - skb_queue_purge(&ndlc->rcv_q); - skb_queue_purge(&ndlc->send_q); -} -EXPORT_SYMBOL(ndlc_remove); diff --git a/drivers/nfc/st21nfcb/ndlc.h b/drivers/nfc/st21nfcb/ndlc.h deleted file mode 100644 index cf6a9d9f2983..000000000000 --- a/drivers/nfc/st21nfcb/ndlc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * NCI based Driver for STMicroelectronics NFC Chip - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef __LOCAL_NDLC_H_ -#define __LOCAL_NDLC_H_ - -#include -#include - -/* Low Level Transport description */ -struct llt_ndlc { - struct nci_dev *ndev; - struct nfc_phy_ops *ops; - void *phy_id; - - struct timer_list t1_timer; - bool t1_active; - - struct timer_list t2_timer; - bool t2_active; - - struct sk_buff_head rcv_q; - struct sk_buff_head send_q; - struct sk_buff_head ack_pending_q; - - struct work_struct sm_work; - - struct device *dev; - - /* - * < 0 if hardware error occured - * and prevents normal operation. - */ - int hard_fault; - int powered; -}; - -int ndlc_open(struct llt_ndlc *ndlc); -void ndlc_close(struct llt_ndlc *ndlc); -int ndlc_send(struct llt_ndlc *ndlc, struct sk_buff *skb); -void ndlc_recv(struct llt_ndlc *ndlc, struct sk_buff *skb); -int ndlc_probe(void *phy_id, struct nfc_phy_ops *phy_ops, struct device *dev, - int phy_headroom, int phy_tailroom, struct llt_ndlc **ndlc_id); -void ndlc_remove(struct llt_ndlc *ndlc); -#endif /* __LOCAL_NDLC_H__ */ diff --git a/drivers/nfc/st21nfcb/st21nfcb.c b/drivers/nfc/st21nfcb/st21nfcb.c deleted file mode 100644 index a16c3a3d3fff..000000000000 --- a/drivers/nfc/st21nfcb/st21nfcb.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * NCI based Driver for STMicroelectronics NFC Chip - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#include -#include -#include -#include -#include -#include - -#include "st21nfcb.h" -#include "st21nfcb_se.h" - -#define DRIVER_DESC "NCI NFC driver for ST21NFCB" - -#define ST21NFCB_NCI1_X_PROPRIETARY_ISO15693 0x83 - -static int st21nfcb_nci_init(struct nci_dev *ndev) -{ - struct nci_mode_set_cmd cmd; - - cmd.cmd_type = ST21NFCB_NCI_SET_NFC_MODE; - cmd.mode = 1; - - return nci_prop_cmd(ndev, ST21NFCB_NCI_CORE_PROP, - sizeof(struct nci_mode_set_cmd), (__u8 *)&cmd); -} - -static int st21nfcb_nci_open(struct nci_dev *ndev) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - int r; - - if (test_and_set_bit(ST21NFCB_NCI_RUNNING, &info->flags)) - return 0; - - r = ndlc_open(info->ndlc); - if (r) - clear_bit(ST21NFCB_NCI_RUNNING, &info->flags); - - return r; -} - -static int st21nfcb_nci_close(struct nci_dev *ndev) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - if (!test_bit(ST21NFCB_NCI_RUNNING, &info->flags)) - return 0; - - ndlc_close(info->ndlc); - - clear_bit(ST21NFCB_NCI_RUNNING, &info->flags); - - return 0; -} - -static int st21nfcb_nci_send(struct nci_dev *ndev, struct sk_buff *skb) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - skb->dev = (void *)ndev; - - if (!test_bit(ST21NFCB_NCI_RUNNING, &info->flags)) - return -EBUSY; - - return ndlc_send(info->ndlc, skb); -} - -static __u32 st21nfcb_nci_get_rfprotocol(struct nci_dev *ndev, - __u8 rf_protocol) -{ - return rf_protocol == ST21NFCB_NCI1_X_PROPRIETARY_ISO15693 ? - NFC_PROTO_ISO15693_MASK : 0; -} - -static int st21nfcb_nci_prop_rsp_packet(struct nci_dev *ndev, - struct sk_buff *skb) -{ - __u8 status = skb->data[0]; - - nci_req_complete(ndev, status); - return 0; -} - -static struct nci_prop_ops st21nfcb_nci_prop_ops[] = { - { - .opcode = nci_opcode_pack(NCI_GID_PROPRIETARY, - ST21NFCB_NCI_CORE_PROP), - .rsp = st21nfcb_nci_prop_rsp_packet, - }, -}; - -static struct nci_ops st21nfcb_nci_ops = { - .init = st21nfcb_nci_init, - .open = st21nfcb_nci_open, - .close = st21nfcb_nci_close, - .send = st21nfcb_nci_send, - .get_rfprotocol = st21nfcb_nci_get_rfprotocol, - .discover_se = st21nfcb_nci_discover_se, - .enable_se = st21nfcb_nci_enable_se, - .disable_se = st21nfcb_nci_disable_se, - .se_io = st21nfcb_nci_se_io, - .hci_load_session = st21nfcb_hci_load_session, - .hci_event_received = st21nfcb_hci_event_received, - .hci_cmd_received = st21nfcb_hci_cmd_received, - .prop_ops = st21nfcb_nci_prop_ops, - .n_prop_ops = ARRAY_SIZE(st21nfcb_nci_prop_ops), -}; - -int st21nfcb_nci_probe(struct llt_ndlc *ndlc, int phy_headroom, - int phy_tailroom) -{ - struct st21nfcb_nci_info *info; - int r; - u32 protocols; - - info = devm_kzalloc(ndlc->dev, - sizeof(struct st21nfcb_nci_info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - protocols = NFC_PROTO_JEWEL_MASK - | NFC_PROTO_MIFARE_MASK - | NFC_PROTO_FELICA_MASK - | NFC_PROTO_ISO14443_MASK - | NFC_PROTO_ISO14443_B_MASK - | NFC_PROTO_ISO15693_MASK - | NFC_PROTO_NFC_DEP_MASK; - - ndlc->ndev = nci_allocate_device(&st21nfcb_nci_ops, protocols, - phy_headroom, phy_tailroom); - if (!ndlc->ndev) { - pr_err("Cannot allocate nfc ndev\n"); - return -ENOMEM; - } - info->ndlc = ndlc; - - nci_set_drvdata(ndlc->ndev, info); - - r = nci_register_device(ndlc->ndev); - if (r) { - pr_err("Cannot register nfc device to nci core\n"); - nci_free_device(ndlc->ndev); - return r; - } - - return st21nfcb_se_init(ndlc->ndev); -} -EXPORT_SYMBOL_GPL(st21nfcb_nci_probe); - -void st21nfcb_nci_remove(struct nci_dev *ndev) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - ndlc_close(info->ndlc); - - nci_unregister_device(ndev); - nci_free_device(ndev); -} -EXPORT_SYMBOL_GPL(st21nfcb_nci_remove); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/nfc/st21nfcb/st21nfcb.h b/drivers/nfc/st21nfcb/st21nfcb.h deleted file mode 100644 index 710636325c1f..000000000000 --- a/drivers/nfc/st21nfcb/st21nfcb.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * NCI based Driver for STMicroelectronics NFC Chip - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef __LOCAL_ST21NFCB_H_ -#define __LOCAL_ST21NFCB_H_ - -#include "st21nfcb_se.h" -#include "ndlc.h" - -/* Define private flags: */ -#define ST21NFCB_NCI_RUNNING 1 - -#define ST21NFCB_NCI_CORE_PROP 0x01 -#define ST21NFCB_NCI_SET_NFC_MODE 0x02 - -struct nci_mode_set_cmd { - u8 cmd_type; - u8 mode; -} __packed; - -struct nci_mode_set_rsp { - u8 status; -} __packed; - -struct st21nfcb_nci_info { - struct llt_ndlc *ndlc; - unsigned long flags; - struct st21nfcb_se_info se_info; -}; - -void st21nfcb_nci_remove(struct nci_dev *ndev); -int st21nfcb_nci_probe(struct llt_ndlc *ndlc, int phy_headroom, - int phy_tailroom); - -#endif /* __LOCAL_ST21NFCB_H_ */ diff --git a/drivers/nfc/st21nfcb/st21nfcb_se.c b/drivers/nfc/st21nfcb/st21nfcb_se.c deleted file mode 100644 index 24862a525fb5..000000000000 --- a/drivers/nfc/st21nfcb/st21nfcb_se.c +++ /dev/null @@ -1,713 +0,0 @@ -/* - * NCI based Driver for STMicroelectronics NFC Chip - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#include -#include -#include -#include -#include - -#include "st21nfcb.h" -#include "st21nfcb_se.h" - -struct st21nfcb_pipe_info { - u8 pipe_state; - u8 src_host_id; - u8 src_gate_id; - u8 dst_host_id; - u8 dst_gate_id; -} __packed; - -/* Hosts */ -#define ST21NFCB_HOST_CONTROLLER_ID 0x00 -#define ST21NFCB_TERMINAL_HOST_ID 0x01 -#define ST21NFCB_UICC_HOST_ID 0x02 -#define ST21NFCB_ESE_HOST_ID 0xc0 - -/* Gates */ -#define ST21NFCB_DEVICE_MGNT_GATE 0x01 -#define ST21NFCB_APDU_READER_GATE 0xf0 -#define ST21NFCB_CONNECTIVITY_GATE 0x41 - -/* Pipes */ -#define ST21NFCB_DEVICE_MGNT_PIPE 0x02 - -/* Connectivity pipe only */ -#define ST21NFCB_SE_COUNT_PIPE_UICC 0x01 -/* Connectivity + APDU Reader pipe */ -#define ST21NFCB_SE_COUNT_PIPE_EMBEDDED 0x02 - -#define ST21NFCB_SE_TO_HOT_PLUG 1000 /* msecs */ -#define ST21NFCB_SE_TO_PIPES 2000 - -#define ST21NFCB_EVT_HOT_PLUG_IS_INHIBITED(x) (x->data[0] & 0x80) - -#define NCI_HCI_APDU_PARAM_ATR 0x01 -#define NCI_HCI_ADMIN_PARAM_SESSION_IDENTITY 0x01 -#define NCI_HCI_ADMIN_PARAM_WHITELIST 0x03 -#define NCI_HCI_ADMIN_PARAM_HOST_LIST 0x04 - -#define ST21NFCB_EVT_SE_HARD_RESET 0x20 -#define ST21NFCB_EVT_TRANSMIT_DATA 0x10 -#define ST21NFCB_EVT_WTX_REQUEST 0x11 -#define ST21NFCB_EVT_SE_SOFT_RESET 0x11 -#define ST21NFCB_EVT_SE_END_OF_APDU_TRANSFER 0x21 -#define ST21NFCB_EVT_HOT_PLUG 0x03 - -#define ST21NFCB_SE_MODE_OFF 0x00 -#define ST21NFCB_SE_MODE_ON 0x01 - -#define ST21NFCB_EVT_CONNECTIVITY 0x10 -#define ST21NFCB_EVT_TRANSACTION 0x12 - -#define ST21NFCB_DM_GETINFO 0x13 -#define ST21NFCB_DM_GETINFO_PIPE_LIST 0x02 -#define ST21NFCB_DM_GETINFO_PIPE_INFO 0x01 -#define ST21NFCB_DM_PIPE_CREATED 0x02 -#define ST21NFCB_DM_PIPE_OPEN 0x04 -#define ST21NFCB_DM_RF_ACTIVE 0x80 -#define ST21NFCB_DM_DISCONNECT 0x30 - -#define ST21NFCB_DM_IS_PIPE_OPEN(p) \ - ((p & 0x0f) == (ST21NFCB_DM_PIPE_CREATED | ST21NFCB_DM_PIPE_OPEN)) - -#define ST21NFCB_ATR_DEFAULT_BWI 0x04 - -/* - * WT = 2^BWI/10[s], convert into msecs and add a secure - * room by increasing by 2 this timeout - */ -#define ST21NFCB_BWI_TO_TIMEOUT(x) ((1 << x) * 200) -#define ST21NFCB_ATR_GET_Y_FROM_TD(x) (x >> 4) - -/* If TA is present bit 0 is set */ -#define ST21NFCB_ATR_TA_PRESENT(x) (x & 0x01) -/* If TB is present bit 1 is set */ -#define ST21NFCB_ATR_TB_PRESENT(x) (x & 0x02) - -#define ST21NFCB_NUM_DEVICES 256 - -static DECLARE_BITMAP(dev_mask, ST21NFCB_NUM_DEVICES); - -/* Here are the mandatory pipe for st21nfcb */ -static struct nci_hci_gate st21nfcb_gates[] = { - {NCI_HCI_ADMIN_GATE, NCI_HCI_ADMIN_PIPE, - ST21NFCB_HOST_CONTROLLER_ID}, - {NCI_HCI_LINK_MGMT_GATE, NCI_HCI_LINK_MGMT_PIPE, - ST21NFCB_HOST_CONTROLLER_ID}, - {ST21NFCB_DEVICE_MGNT_GATE, ST21NFCB_DEVICE_MGNT_PIPE, - ST21NFCB_HOST_CONTROLLER_ID}, - - /* Secure element pipes are created by secure element host */ - {ST21NFCB_CONNECTIVITY_GATE, NCI_HCI_DO_NOT_OPEN_PIPE, - ST21NFCB_HOST_CONTROLLER_ID}, - {ST21NFCB_APDU_READER_GATE, NCI_HCI_DO_NOT_OPEN_PIPE, - ST21NFCB_HOST_CONTROLLER_ID}, -}; - -static u8 st21nfcb_se_get_bwi(struct nci_dev *ndev) -{ - int i; - u8 td; - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - /* Bits 8 to 5 of the first TB for T=1 encode BWI from zero to nine */ - for (i = 1; i < ST21NFCB_ESE_MAX_LENGTH; i++) { - td = ST21NFCB_ATR_GET_Y_FROM_TD(info->se_info.atr[i]); - if (ST21NFCB_ATR_TA_PRESENT(td)) - i++; - if (ST21NFCB_ATR_TB_PRESENT(td)) { - i++; - return info->se_info.atr[i] >> 4; - } - } - return ST21NFCB_ATR_DEFAULT_BWI; -} - -static void st21nfcb_se_get_atr(struct nci_dev *ndev) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - int r; - struct sk_buff *skb; - - r = nci_hci_get_param(ndev, ST21NFCB_APDU_READER_GATE, - NCI_HCI_APDU_PARAM_ATR, &skb); - if (r < 0) - return; - - if (skb->len <= ST21NFCB_ESE_MAX_LENGTH) { - memcpy(info->se_info.atr, skb->data, skb->len); - - info->se_info.wt_timeout = - ST21NFCB_BWI_TO_TIMEOUT(st21nfcb_se_get_bwi(ndev)); - } - kfree_skb(skb); -} - -int st21nfcb_hci_load_session(struct nci_dev *ndev) -{ - int i, j, r; - struct sk_buff *skb_pipe_list, *skb_pipe_info; - struct st21nfcb_pipe_info *dm_pipe_info; - u8 pipe_list[] = { ST21NFCB_DM_GETINFO_PIPE_LIST, - ST21NFCB_TERMINAL_HOST_ID}; - u8 pipe_info[] = { ST21NFCB_DM_GETINFO_PIPE_INFO, - ST21NFCB_TERMINAL_HOST_ID, 0}; - - /* On ST21NFCB device pipes number are dynamics - * If pipes are already created, hci_dev_up will fail. - * Doing a clear all pipe is a bad idea because: - * - It does useless EEPROM cycling - * - It might cause issue for secure elements support - * (such as removing connectivity or APDU reader pipe) - * A better approach on ST21NFCB is to: - * - get a pipe list for each host. - * (eg: ST21NFCB_HOST_CONTROLLER_ID for now). - * (TODO Later on UICC HOST and eSE HOST) - * - get pipe information - * - match retrieved pipe list in st21nfcb_gates - * ST21NFCB_DEVICE_MGNT_GATE is a proprietary gate - * with ST21NFCB_DEVICE_MGNT_PIPE. - * Pipe can be closed and need to be open. - */ - r = nci_hci_connect_gate(ndev, ST21NFCB_HOST_CONTROLLER_ID, - ST21NFCB_DEVICE_MGNT_GATE, - ST21NFCB_DEVICE_MGNT_PIPE); - if (r < 0) - goto free_info; - - /* Get pipe list */ - r = nci_hci_send_cmd(ndev, ST21NFCB_DEVICE_MGNT_GATE, - ST21NFCB_DM_GETINFO, pipe_list, sizeof(pipe_list), - &skb_pipe_list); - if (r < 0) - goto free_info; - - /* Complete the existing gate_pipe table */ - for (i = 0; i < skb_pipe_list->len; i++) { - pipe_info[2] = skb_pipe_list->data[i]; - r = nci_hci_send_cmd(ndev, ST21NFCB_DEVICE_MGNT_GATE, - ST21NFCB_DM_GETINFO, pipe_info, - sizeof(pipe_info), &skb_pipe_info); - - if (r) - continue; - - /* - * Match pipe ID and gate ID - * Output format from ST21NFC_DM_GETINFO is: - * - pipe state (1byte) - * - source hid (1byte) - * - source gid (1byte) - * - destination hid (1byte) - * - destination gid (1byte) - */ - dm_pipe_info = (struct st21nfcb_pipe_info *)skb_pipe_info->data; - if (dm_pipe_info->dst_gate_id == ST21NFCB_APDU_READER_GATE && - dm_pipe_info->src_host_id != ST21NFCB_ESE_HOST_ID) { - pr_err("Unexpected apdu_reader pipe on host %x\n", - dm_pipe_info->src_host_id); - continue; - } - - for (j = 0; (j < ARRAY_SIZE(st21nfcb_gates)) && - (st21nfcb_gates[j].gate != dm_pipe_info->dst_gate_id); j++) - ; - - if (j < ARRAY_SIZE(st21nfcb_gates) && - st21nfcb_gates[j].gate == dm_pipe_info->dst_gate_id && - ST21NFCB_DM_IS_PIPE_OPEN(dm_pipe_info->pipe_state)) { - st21nfcb_gates[j].pipe = pipe_info[2]; - - ndev->hci_dev->gate2pipe[st21nfcb_gates[j].gate] = - st21nfcb_gates[j].pipe; - ndev->hci_dev->pipes[st21nfcb_gates[j].pipe].gate = - st21nfcb_gates[j].gate; - ndev->hci_dev->pipes[st21nfcb_gates[j].pipe].host = - dm_pipe_info->src_host_id; - } - } - - memcpy(ndev->hci_dev->init_data.gates, st21nfcb_gates, - sizeof(st21nfcb_gates)); - -free_info: - kfree_skb(skb_pipe_info); - kfree_skb(skb_pipe_list); - return r; -} -EXPORT_SYMBOL_GPL(st21nfcb_hci_load_session); - -static void st21nfcb_hci_admin_event_received(struct nci_dev *ndev, - u8 event, struct sk_buff *skb) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - switch (event) { - case ST21NFCB_EVT_HOT_PLUG: - if (info->se_info.se_active) { - if (!ST21NFCB_EVT_HOT_PLUG_IS_INHIBITED(skb)) { - del_timer_sync(&info->se_info.se_active_timer); - info->se_info.se_active = false; - complete(&info->se_info.req_completion); - } else { - mod_timer(&info->se_info.se_active_timer, - jiffies + - msecs_to_jiffies(ST21NFCB_SE_TO_PIPES)); - } - } - break; - } -} - -static int st21nfcb_hci_apdu_reader_event_received(struct nci_dev *ndev, - u8 event, - struct sk_buff *skb) -{ - int r = 0; - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - pr_debug("apdu reader gate event: %x\n", event); - - switch (event) { - case ST21NFCB_EVT_TRANSMIT_DATA: - del_timer_sync(&info->se_info.bwi_timer); - info->se_info.bwi_active = false; - info->se_info.cb(info->se_info.cb_context, - skb->data, skb->len, 0); - break; - case ST21NFCB_EVT_WTX_REQUEST: - mod_timer(&info->se_info.bwi_timer, jiffies + - msecs_to_jiffies(info->se_info.wt_timeout)); - break; - } - - kfree_skb(skb); - return r; -} - -/* - * Returns: - * <= 0: driver handled the event, skb consumed - * 1: driver does not handle the event, please do standard processing - */ -static int st21nfcb_hci_connectivity_event_received(struct nci_dev *ndev, - u8 host, u8 event, - struct sk_buff *skb) -{ - int r = 0; - struct device *dev = &ndev->nfc_dev->dev; - struct nfc_evt_transaction *transaction; - - pr_debug("connectivity gate event: %x\n", event); - - switch (event) { - case ST21NFCB_EVT_CONNECTIVITY: - - break; - case ST21NFCB_EVT_TRANSACTION: - /* According to specification etsi 102 622 - * 11.2.2.4 EVT_TRANSACTION Table 52 - * Description Tag Length - * AID 81 5 to 16 - * PARAMETERS 82 0 to 255 - */ - if (skb->len < NFC_MIN_AID_LENGTH + 2 && - skb->data[0] != NFC_EVT_TRANSACTION_AID_TAG) - return -EPROTO; - - transaction = (struct nfc_evt_transaction *)devm_kzalloc(dev, - skb->len - 2, GFP_KERNEL); - - transaction->aid_len = skb->data[1]; - memcpy(transaction->aid, &skb->data[2], transaction->aid_len); - - /* Check next byte is PARAMETERS tag (82) */ - if (skb->data[transaction->aid_len + 2] != - NFC_EVT_TRANSACTION_PARAMS_TAG) - return -EPROTO; - - transaction->params_len = skb->data[transaction->aid_len + 3]; - memcpy(transaction->params, skb->data + - transaction->aid_len + 4, transaction->params_len); - - r = nfc_se_transaction(ndev->nfc_dev, host, transaction); - break; - default: - return 1; - } - kfree_skb(skb); - return r; -} - -void st21nfcb_hci_event_received(struct nci_dev *ndev, u8 pipe, - u8 event, struct sk_buff *skb) -{ - u8 gate = ndev->hci_dev->pipes[pipe].gate; - u8 host = ndev->hci_dev->pipes[pipe].host; - - switch (gate) { - case NCI_HCI_ADMIN_GATE: - st21nfcb_hci_admin_event_received(ndev, event, skb); - break; - case ST21NFCB_APDU_READER_GATE: - st21nfcb_hci_apdu_reader_event_received(ndev, event, skb); - break; - case ST21NFCB_CONNECTIVITY_GATE: - st21nfcb_hci_connectivity_event_received(ndev, host, event, - skb); - break; - } -} -EXPORT_SYMBOL_GPL(st21nfcb_hci_event_received); - - -void st21nfcb_hci_cmd_received(struct nci_dev *ndev, u8 pipe, u8 cmd, - struct sk_buff *skb) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - u8 gate = ndev->hci_dev->pipes[pipe].gate; - - pr_debug("cmd: %x\n", cmd); - - switch (cmd) { - case NCI_HCI_ANY_OPEN_PIPE: - if (gate != ST21NFCB_APDU_READER_GATE && - ndev->hci_dev->pipes[pipe].host != ST21NFCB_UICC_HOST_ID) - ndev->hci_dev->count_pipes++; - - if (ndev->hci_dev->count_pipes == - ndev->hci_dev->expected_pipes) { - del_timer_sync(&info->se_info.se_active_timer); - info->se_info.se_active = false; - ndev->hci_dev->count_pipes = 0; - complete(&info->se_info.req_completion); - } - break; - } -} -EXPORT_SYMBOL_GPL(st21nfcb_hci_cmd_received); - -/* - * Remarks: On some early st21nfcb firmware, nci_nfcee_mode_set(0) - * is rejected - */ -static int st21nfcb_nci_control_se(struct nci_dev *ndev, u8 se_idx, - u8 state) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - int r; - struct sk_buff *sk_host_list; - u8 host_id; - - switch (se_idx) { - case ST21NFCB_UICC_HOST_ID: - ndev->hci_dev->count_pipes = 0; - ndev->hci_dev->expected_pipes = ST21NFCB_SE_COUNT_PIPE_UICC; - break; - case ST21NFCB_ESE_HOST_ID: - ndev->hci_dev->count_pipes = 0; - ndev->hci_dev->expected_pipes = ST21NFCB_SE_COUNT_PIPE_EMBEDDED; - break; - default: - return -EINVAL; - } - - /* - * Wait for an EVT_HOT_PLUG in order to - * retrieve a relevant host list. - */ - reinit_completion(&info->se_info.req_completion); - r = nci_nfcee_mode_set(ndev, se_idx, NCI_NFCEE_ENABLE); - if (r != NCI_STATUS_OK) - return r; - - mod_timer(&info->se_info.se_active_timer, jiffies + - msecs_to_jiffies(ST21NFCB_SE_TO_HOT_PLUG)); - info->se_info.se_active = true; - - /* Ignore return value and check in any case the host_list */ - wait_for_completion_interruptible(&info->se_info.req_completion); - - /* There might be some "collision" after receiving a HOT_PLUG event - * This may cause the CLF to not answer to the next hci command. - * There is no possible synchronization to prevent this. - * Adding a small delay is the only way to solve the issue. - */ - usleep_range(3000, 5000); - - r = nci_hci_get_param(ndev, NCI_HCI_ADMIN_GATE, - NCI_HCI_ADMIN_PARAM_HOST_LIST, &sk_host_list); - if (r != NCI_HCI_ANY_OK) - return r; - - host_id = sk_host_list->data[sk_host_list->len - 1]; - kfree_skb(sk_host_list); - if (state == ST21NFCB_SE_MODE_ON && host_id == se_idx) - return se_idx; - else if (state == ST21NFCB_SE_MODE_OFF && host_id != se_idx) - return se_idx; - - return -1; -} - -int st21nfcb_nci_disable_se(struct nci_dev *ndev, u32 se_idx) -{ - int r; - - pr_debug("st21nfcb_nci_disable_se\n"); - - if (se_idx == NFC_SE_EMBEDDED) { - r = nci_hci_send_event(ndev, ST21NFCB_APDU_READER_GATE, - ST21NFCB_EVT_SE_END_OF_APDU_TRANSFER, NULL, 0); - if (r < 0) - return r; - } - - return 0; -} -EXPORT_SYMBOL_GPL(st21nfcb_nci_disable_se); - -int st21nfcb_nci_enable_se(struct nci_dev *ndev, u32 se_idx) -{ - int r; - - pr_debug("st21nfcb_nci_enable_se\n"); - - if (se_idx == ST21NFCB_HCI_HOST_ID_ESE) { - r = nci_hci_send_event(ndev, ST21NFCB_APDU_READER_GATE, - ST21NFCB_EVT_SE_SOFT_RESET, NULL, 0); - if (r < 0) - return r; - } - - return 0; -} -EXPORT_SYMBOL_GPL(st21nfcb_nci_enable_se); - -static int st21nfcb_hci_network_init(struct nci_dev *ndev) -{ - struct core_conn_create_dest_spec_params *dest_params; - struct dest_spec_params spec_params; - struct nci_conn_info *conn_info; - int r, dev_num; - - dest_params = - kzalloc(sizeof(struct core_conn_create_dest_spec_params) + - sizeof(struct dest_spec_params), GFP_KERNEL); - if (dest_params == NULL) { - r = -ENOMEM; - goto exit; - } - - dest_params->type = NCI_DESTINATION_SPECIFIC_PARAM_NFCEE_TYPE; - dest_params->length = sizeof(struct dest_spec_params); - spec_params.id = ndev->hci_dev->nfcee_id; - spec_params.protocol = NCI_NFCEE_INTERFACE_HCI_ACCESS; - memcpy(dest_params->value, &spec_params, sizeof(struct dest_spec_params)); - r = nci_core_conn_create(ndev, NCI_DESTINATION_NFCEE, 1, - sizeof(struct core_conn_create_dest_spec_params) + - sizeof(struct dest_spec_params), - dest_params); - if (r != NCI_STATUS_OK) - goto free_dest_params; - - conn_info = ndev->hci_dev->conn_info; - if (!conn_info) - goto free_dest_params; - - memcpy(ndev->hci_dev->init_data.gates, st21nfcb_gates, - sizeof(st21nfcb_gates)); - - /* - * Session id must include the driver name + i2c bus addr - * persistent info to discriminate 2 identical chips - */ - dev_num = find_first_zero_bit(dev_mask, ST21NFCB_NUM_DEVICES); - if (dev_num >= ST21NFCB_NUM_DEVICES) { - r = -ENODEV; - goto free_dest_params; - } - - scnprintf(ndev->hci_dev->init_data.session_id, - sizeof(ndev->hci_dev->init_data.session_id), - "%s%2x", "ST21BH", dev_num); - - r = nci_hci_dev_session_init(ndev); - if (r != NCI_HCI_ANY_OK) - goto free_dest_params; - - r = nci_nfcee_mode_set(ndev, ndev->hci_dev->conn_info->id, - NCI_NFCEE_ENABLE); - if (r != NCI_STATUS_OK) - goto free_dest_params; - -free_dest_params: - kfree(dest_params); - -exit: - return r; -} - -int st21nfcb_nci_discover_se(struct nci_dev *ndev) -{ - u8 param[2]; - int r; - int se_count = 0; - - pr_debug("st21nfcb_nci_discover_se\n"); - - r = st21nfcb_hci_network_init(ndev); - if (r != 0) - return r; - - param[0] = ST21NFCB_UICC_HOST_ID; - param[1] = ST21NFCB_HCI_HOST_ID_ESE; - r = nci_hci_set_param(ndev, NCI_HCI_ADMIN_GATE, - NCI_HCI_ADMIN_PARAM_WHITELIST, - param, sizeof(param)); - if (r != NCI_HCI_ANY_OK) - return r; - - r = st21nfcb_nci_control_se(ndev, ST21NFCB_UICC_HOST_ID, - ST21NFCB_SE_MODE_ON); - if (r == ST21NFCB_UICC_HOST_ID) { - nfc_add_se(ndev->nfc_dev, ST21NFCB_UICC_HOST_ID, NFC_SE_UICC); - se_count++; - } - - /* Try to enable eSE in order to check availability */ - r = st21nfcb_nci_control_se(ndev, ST21NFCB_HCI_HOST_ID_ESE, - ST21NFCB_SE_MODE_ON); - if (r == ST21NFCB_HCI_HOST_ID_ESE) { - nfc_add_se(ndev->nfc_dev, ST21NFCB_HCI_HOST_ID_ESE, - NFC_SE_EMBEDDED); - se_count++; - st21nfcb_se_get_atr(ndev); - } - - return !se_count; -} -EXPORT_SYMBOL_GPL(st21nfcb_nci_discover_se); - -int st21nfcb_nci_se_io(struct nci_dev *ndev, u32 se_idx, - u8 *apdu, size_t apdu_length, - se_io_cb_t cb, void *cb_context) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - pr_debug("\n"); - - switch (se_idx) { - case ST21NFCB_HCI_HOST_ID_ESE: - info->se_info.cb = cb; - info->se_info.cb_context = cb_context; - mod_timer(&info->se_info.bwi_timer, jiffies + - msecs_to_jiffies(info->se_info.wt_timeout)); - info->se_info.bwi_active = true; - return nci_hci_send_event(ndev, ST21NFCB_APDU_READER_GATE, - ST21NFCB_EVT_TRANSMIT_DATA, apdu, - apdu_length); - default: - return -ENODEV; - } -} -EXPORT_SYMBOL(st21nfcb_nci_se_io); - -static void st21nfcb_se_wt_timeout(unsigned long data) -{ - /* - * No answer from the secure element - * within the defined timeout. - * Let's send a reset request as recovery procedure. - * According to the situation, we first try to send a software reset - * to the secure element. If the next command is still not - * answering in time, we send to the CLF a secure element hardware - * reset request. - */ - /* hardware reset managed through VCC_UICC_OUT power supply */ - u8 param = 0x01; - struct st21nfcb_nci_info *info = (struct st21nfcb_nci_info *) data; - - pr_debug("\n"); - - info->se_info.bwi_active = false; - - if (!info->se_info.xch_error) { - info->se_info.xch_error = true; - nci_hci_send_event(info->ndlc->ndev, ST21NFCB_APDU_READER_GATE, - ST21NFCB_EVT_SE_SOFT_RESET, NULL, 0); - } else { - info->se_info.xch_error = false; - nci_hci_send_event(info->ndlc->ndev, ST21NFCB_DEVICE_MGNT_GATE, - ST21NFCB_EVT_SE_HARD_RESET, ¶m, 1); - } - info->se_info.cb(info->se_info.cb_context, NULL, 0, -ETIME); -} - -static void st21nfcb_se_activation_timeout(unsigned long data) -{ - struct st21nfcb_nci_info *info = (struct st21nfcb_nci_info *) data; - - pr_debug("\n"); - - info->se_info.se_active = false; - - complete(&info->se_info.req_completion); -} - -int st21nfcb_se_init(struct nci_dev *ndev) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - init_completion(&info->se_info.req_completion); - /* initialize timers */ - init_timer(&info->se_info.bwi_timer); - info->se_info.bwi_timer.data = (unsigned long)info; - info->se_info.bwi_timer.function = st21nfcb_se_wt_timeout; - info->se_info.bwi_active = false; - - init_timer(&info->se_info.se_active_timer); - info->se_info.se_active_timer.data = (unsigned long)info; - info->se_info.se_active_timer.function = - st21nfcb_se_activation_timeout; - info->se_info.se_active = false; - - info->se_info.xch_error = false; - - info->se_info.wt_timeout = - ST21NFCB_BWI_TO_TIMEOUT(ST21NFCB_ATR_DEFAULT_BWI); - - return 0; -} -EXPORT_SYMBOL(st21nfcb_se_init); - -void st21nfcb_se_deinit(struct nci_dev *ndev) -{ - struct st21nfcb_nci_info *info = nci_get_drvdata(ndev); - - if (info->se_info.bwi_active) - del_timer_sync(&info->se_info.bwi_timer); - if (info->se_info.se_active) - del_timer_sync(&info->se_info.se_active_timer); - - info->se_info.se_active = false; - info->se_info.bwi_active = false; -} -EXPORT_SYMBOL(st21nfcb_se_deinit); - diff --git a/drivers/nfc/st21nfcb/st21nfcb_se.h b/drivers/nfc/st21nfcb/st21nfcb_se.h deleted file mode 100644 index 52a323872bea..000000000000 --- a/drivers/nfc/st21nfcb/st21nfcb_se.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * NCI based Driver for STMicroelectronics NFC Chip - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ -#ifndef __LOCAL_ST21NFCB_SE_H_ -#define __LOCAL_ST21NFCB_SE_H_ - -/* - * ref ISO7816-3 chap 8.1. the initial character TS is followed by a - * sequence of at most 32 characters. - */ -#define ST21NFCB_ESE_MAX_LENGTH 33 -#define ST21NFCB_HCI_HOST_ID_ESE 0xc0 - -struct st21nfcb_se_info { - u8 atr[ST21NFCB_ESE_MAX_LENGTH]; - struct completion req_completion; - - struct timer_list bwi_timer; - int wt_timeout; /* in msecs */ - bool bwi_active; - - struct timer_list se_active_timer; - bool se_active; - - bool xch_error; - - se_io_cb_t cb; - void *cb_context; -}; - -int st21nfcb_se_init(struct nci_dev *ndev); -void st21nfcb_se_deinit(struct nci_dev *ndev); - -int st21nfcb_nci_discover_se(struct nci_dev *ndev); -int st21nfcb_nci_enable_se(struct nci_dev *ndev, u32 se_idx); -int st21nfcb_nci_disable_se(struct nci_dev *ndev, u32 se_idx); -int st21nfcb_nci_se_io(struct nci_dev *ndev, u32 se_idx, - u8 *apdu, size_t apdu_length, - se_io_cb_t cb, void *cb_context); -int st21nfcb_hci_load_session(struct nci_dev *ndev); -void st21nfcb_hci_event_received(struct nci_dev *ndev, u8 pipe, - u8 event, struct sk_buff *skb); -void st21nfcb_hci_cmd_received(struct nci_dev *ndev, u8 pipe, u8 cmd, - struct sk_buff *skb); - - -#endif /* __LOCAL_ST21NFCB_NCI_H_ */ diff --git a/include/linux/platform_data/st-nci.h b/include/linux/platform_data/st-nci.h new file mode 100644 index 000000000000..d9d400a297bd --- /dev/null +++ b/include/linux/platform_data/st-nci.h @@ -0,0 +1,29 @@ +/* + * Driver include for ST NCI NFC chip family. + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef _ST_NCI_H_ +#define _ST_NCI_H_ + +#define ST_NCI_DRIVER_NAME "st_nci" + +struct st_nci_nfc_platform_data { + unsigned int gpio_reset; + unsigned int irq_polarity; +}; + +#endif /* _ST_NCI_H_ */ diff --git a/include/linux/platform_data/st21nfcb.h b/include/linux/platform_data/st21nfcb.h deleted file mode 100644 index b023373d9874..000000000000 --- a/include/linux/platform_data/st21nfcb.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Driver include for the ST21NFCB NFC chip. - * - * Copyright (C) 2014 STMicroelectronics SAS. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef _ST21NFCB_NCI_H_ -#define _ST21NFCB_NCI_H_ - -#define ST21NFCB_NCI_DRIVER_NAME "st21nfcb_nci" - -struct st21nfcb_nfc_platform_data { - unsigned int gpio_reset; - unsigned int irq_polarity; -}; - -#endif /* _ST21NFCB_NCI_H_ */ diff --git a/include/linux/platform_data/st_nci.h b/include/linux/platform_data/st_nci.h new file mode 100644 index 000000000000..d9d400a297bd --- /dev/null +++ b/include/linux/platform_data/st_nci.h @@ -0,0 +1,29 @@ +/* + * Driver include for ST NCI NFC chip family. + * + * Copyright (C) 2014-2015 STMicroelectronics SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef _ST_NCI_H_ +#define _ST_NCI_H_ + +#define ST_NCI_DRIVER_NAME "st_nci" + +struct st_nci_nfc_platform_data { + unsigned int gpio_reset; + unsigned int irq_polarity; +}; + +#endif /* _ST_NCI_H_ */ -- cgit v1.2.3 From dae5597f253ae2d44432c8648d9a9205de057ddf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:08 +0200 Subject: pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../bindings/pinctrl/marvell,armada-375-pinctrl.txt | 6 +++--- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 12 ++++++------ .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 4 ++-- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 12 ++++++------ drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +- 10 files changed, 26 insertions(+), 26 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 183c4723d9c8..e6dce5d7ef8d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -20,7 +20,7 @@ mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, cpu_pd(vdd) mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) -mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk) +mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index ce1771bd9106..314032481ccf 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -31,8 +31,8 @@ mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) mpp17 17 gpio, uart0(rxd) -mpp18 18 gpio, tdm(intn) -mpp19 19 gpio, tdm(rstn) +mpp18 18 gpio, tdm(int) +mpp19 19 gpio, tdm(rst) mpp20 20 gpio, tdm(pclk) mpp21 21 gpio, tdm(fsync) mpp22 22 gpio, tdm(drx) @@ -50,7 +50,7 @@ mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) mpp36 36 gpio, pcie0(clkreq) -mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc) +mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) mpp38 38 gpio, pcie1(clkreq), ge(mdio) mpp39 39 gpio, ref(clkout) mpp40 40 gpio, uart1(txd) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 9844773032c5..203220d2392f 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -63,12 +63,12 @@ mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3 mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) -mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), dram(deccerr) -mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index b6bd9cc09af8..1dd76e953725 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -66,8 +66,8 @@ mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rstn) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [1], audio(bclk) [1], sd0(d7), i2c3(sda) mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index cefca173366e..561e5190f5ac 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -61,7 +61,7 @@ mpp39 39 gpio, spi(cs0) mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), dram(bat) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 7d2be71f0237..fe5cfd11ed66 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -68,7 +68,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_MODE(7, MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txd1"), - MPP_FUNCTION(0x4, "tdm", "tdx"), + MPP_FUNCTION(0x4, "tdm", "dtx"), MPP_FUNCTION(0x5, "audio", "lrclk")), MPP_MODE(8, MPP_FUNCTION(0x0, "gpio", NULL), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 6dfe1bfff575..c41dd19f321a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -141,10 +141,10 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "uart0", "rxd")), MPP_MODE(18, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "tdm", "intn")), + MPP_FUNCTION(0x2, "tdm", "int")), MPP_MODE(19, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x2, "tdm", "rstn")), + MPP_FUNCTION(0x2, "tdm", "rst")), MPP_MODE(20, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "tdm", "pclk")), @@ -242,7 +242,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(37, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "pcie0", "clkreq"), - MPP_FUNCTION(0x2, "tdm", "intn"), + MPP_FUNCTION(0x2, "tdm", "int"), MPP_FUNCTION(0x4, "ge", "mdc")), MPP_MODE(38, MPP_FUNCTION(0x0, "gpio", NULL), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 793d0dfec220..b5006f769d59 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -303,7 +303,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)), @@ -311,32 +311,32 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), - MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS), MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), MPP_MODE(50, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)), MPP_MODE(51, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS), - MPP_VAR_FUNCTION(3, "tdm2c", "rstn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)), MPP_MODE(54, diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index de91b3598653..433291a1540a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -308,7 +308,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928), + MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), @@ -316,7 +316,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928), + MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 93b0485bc886..9a8b71417620 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -252,7 +252,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)), MPP_MODE(43, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), -- cgit v1.2.3 From d4974c16ed22f6b19b67d95d63c7244dbe87d95b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:09 +0200 Subject: pinctrl: mvebu: armada-{370,375}: normalize PCIe pins This commit normalizes the naming of PCIe pins to use 'rstout' instead of 'rstoutn' or 'rst-out'. Since only the subnames are changed, DT compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../bindings/pinctrl/marvell,armada-375-pinctrl.txt | 8 ++++---- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 14 +++++++------- 4 files changed, 13 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index e6dce5d7ef8d..24a745008a33 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -86,7 +86,7 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), uart0(rts) mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) -mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), +mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index 314032481ccf..f942a006a814 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -26,7 +26,7 @@ mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(ready), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) @@ -58,7 +58,7 @@ mpp41 41 gpio, uart1(rxd) mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) -mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) +mpp45 45 gpio, spi0(cs2), pcie0(rstout) mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) @@ -66,8 +66,8 @@ mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) -mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) -mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) +mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) +mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index fe5cfd11ed66..6ecec9071276 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -348,7 +348,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x1, "dev", "ale1"), MPP_FUNCTION(0x2, "uart1", "rxd"), MPP_FUNCTION(0x3, "sata0", "prsnt"), - MPP_FUNCTION(0x4, "pcie", "rst-out"), + MPP_FUNCTION(0x4, "pcie", "rstout"), MPP_FUNCTION(0x5, "audio", "sdi")), MPP_MODE(61, MPP_FUNCTION(0x0, "gpo", NULL), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index c41dd19f321a..4d3e23517bed 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -121,8 +121,8 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(13, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ready"), - MPP_FUNCTION(0x2, "pcie0", "rstoutn"), - MPP_FUNCTION(0x3, "pcie1", "rstoutn"), + MPP_FUNCTION(0x2, "pcie0", "rstout"), + MPP_FUNCTION(0x3, "pcie1", "rstout"), MPP_FUNCTION(0x5, "nand", "rb"), MPP_FUNCTION(0x6, "spi1", "mosi")), MPP_MODE(14, @@ -201,7 +201,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x2, "ge1", "rxclk"), MPP_FUNCTION(0x3, "sd", "d3"), MPP_FUNCTION(0x5, "spi0", "sck"), - MPP_FUNCTION(0x6, "pcie0", "rstoutn")), + MPP_FUNCTION(0x6, "pcie0", "rstout")), MPP_MODE(30, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ge1", "txd0"), @@ -276,7 +276,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(45, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "spi0", "cs2"), - MPP_FUNCTION(0x4, "pcie0", "rstoutn"), + MPP_FUNCTION(0x4, "pcie0", "rstout"), MPP_FUNCTION(0x5, "led", "c2"), MPP_FUNCTION(0x6, "spi1", "cs2")), MPP_MODE(46, @@ -326,14 +326,14 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x6, "dev", "ad9")), MPP_MODE(53, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "pcie1", "rstoutn"), + MPP_FUNCTION(0x1, "pcie1", "rstout"), MPP_FUNCTION(0x2, "ge0", "rxd3"), MPP_FUNCTION(0x3, "ge1", "rxd3"), MPP_FUNCTION(0x5, "i2c0", "sck"), MPP_FUNCTION(0x6, "dev", "ad10")), MPP_MODE(54, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "pcie0", "rstoutn"), + MPP_FUNCTION(0x1, "pcie0", "rstout"), MPP_FUNCTION(0x2, "ge0", "rxctl"), MPP_FUNCTION(0x3, "ge1", "rxctl"), MPP_FUNCTION(0x6, "dev", "ad11")), @@ -391,7 +391,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x2, "ptp", "evreq"), MPP_FUNCTION(0x4, "spi1", "cs3"), - MPP_FUNCTION(0x5, "pcie0", "rstoutn"), + MPP_FUNCTION(0x5, "pcie0", "rstout"), MPP_FUNCTION(0x6, "dev", "cs3")), }; -- cgit v1.2.3 From f32f01e1ba6bca9611c835eb357ce926038128e8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:10 +0200 Subject: pinctrl: mvebu: armada-{370,375}: normalize audio pins This commit aligns the naming of the audio 'lrclk' pin accross Marvell SoCs. Since only the subname is changed, the DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 24a745008a33..cc0be9df7082 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -88,7 +88,7 @@ mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) -mpp61 61 gpo, dev(we1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index f942a006a814..06e5bb0367f5 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -19,7 +19,7 @@ mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) -mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) +mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 6ecec9071276..54fec8cc608c 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -354,7 +354,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "dev", "we1"), MPP_FUNCTION(0x2, "uart1", "txd"), - MPP_FUNCTION(0x5, "audio", "rclk")), + MPP_FUNCTION(0x5, "audio", "lrclk")), MPP_MODE(62, MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "a2"), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 4d3e23517bed..54e9fbd0121f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -81,7 +81,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x0, "gpio", NULL), MPP_FUNCTION(0x1, "dev", "ad0"), MPP_FUNCTION(0x3, "led", "p1"), - MPP_FUNCTION(0x4, "audio", "rclk"), + MPP_FUNCTION(0x4, "audio", "lrclk"), MPP_FUNCTION(0x5, "nand", "io0")), MPP_MODE(7, MPP_FUNCTION(0x0, "gpio", NULL), -- cgit v1.2.3 From a361cbc575d6ea778fe3fa6f13246bf34d995519 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:11 +0200 Subject: pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins This commit normalizes the naming of the Ethernet txclkout pin to be the same accross Marvell SoCs. It is worth mentioning that the DT binding documentation of the Armada XP was wrong for MPP12: it said the function was ge1(txd0), while it is in fact ge1(txclkout). It is however not really a fix worth sending to stable since it does not change the behavior, and the driver itself was correct. Since only the subnames are changed, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index cc0be9df7082..44aedd5351c5 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, cpu_pd(vdd) -mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 561e5190f5ac..0bd7d2f662be 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -18,7 +18,7 @@ only for more detailed description in this document. name pins functions ================================================================================ -mpp0 0 gpio, ge0(txclko), lcd(d0) +mpp0 0 gpio, ge0(txclkout), lcd(d0) mpp1 1 gpio, ge0(txd0), lcd(d1) mpp2 2 gpio, ge0(txd1), lcd(d2) mpp3 3 gpio, ge0(txd2), lcd(d3) @@ -30,7 +30,7 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8) mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) -mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12) +mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 54fec8cc608c..cabf188a1d17 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -55,7 +55,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x1, "cpu_pd", "vdd")), MPP_MODE(5, MPP_FUNCTION(0x0, "gpo", NULL), - MPP_FUNCTION(0x1, "ge0", "txclko"), + MPP_FUNCTION(0x1, "ge0", "txclkout"), MPP_FUNCTION(0x2, "uart1", "txd"), MPP_FUNCTION(0x4, "spi1", "clk"), MPP_FUNCTION(0x5, "audio", "mclk")), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 9a8b71417620..fb5ffa57d90d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -54,7 +54,7 @@ enum armada_xp_variant { static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(0, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "ge0", "txclko", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)), MPP_MODE(1, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -103,7 +103,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(12, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "ge1", "clkout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)), MPP_MODE(13, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), -- cgit v1.2.3 From f1b2db90d0f1bd5227a48ffc479bbd65e97e4327 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:12 +0200 Subject: pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins There was an off-by-one in the documentation of the ge1(txd[0-3]) pins, which is fixed by this commit. Since the driver was correct, and the subnames are anyway not used in the DT binding itself, there is no need to push this documentation fix for stable. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 0bd7d2f662be..f2d2d40487bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -31,9 +31,9 @@ mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) -mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) +mpp13 13 gpio, ge0(txd5), ge1(txd0), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), lcd(d15) +mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) -- cgit v1.2.3 From bfacb5669474e3e17d732eafd2f6965a7ad728ff Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:13 +0200 Subject: pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet For consistency with the datasheet, this commit renames the VDD function of the MPP4 pin. While this changes the DT compatibility, it is not considered to be a problem since this pin is unlikely to be used for anything but debugging purposes. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 44aedd5351c5..3a7dc0e6c94c 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -17,7 +17,7 @@ mpp0 0 gpio, uart0(rxd) mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) -mpp4 4 gpio, cpu_pd(vdd) +mpp4 4 gpio, vdd(cpu-pd) mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index cabf188a1d17..fc16ef6e2435 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -52,7 +52,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x2, "uart0", "rxd")), MPP_MODE(4, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "cpu_pd", "vdd")), + MPP_FUNCTION(0x1, "vdd", "cpu-pd")), MPP_MODE(5, MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txclkout"), -- cgit v1.2.3 From 9e05db29e2ac7f1fec1a4d15db8c419634290535 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:14 +0200 Subject: pinctrl: mvebu: armada-370: align spi1 clock pin naming Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the 'sck' subname and not 'clk', so this commit adjusts the code and documentation accordingly. Since this commit only changes the subname, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-370.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt index 3a7dc0e6c94c..add7c38ec7d8 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -18,7 +18,7 @@ mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) mpp4 4 gpio, vdd(cpu-pd) -mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index fc16ef6e2435..c2e5e4de49c3 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -57,7 +57,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_FUNCTION(0x0, "gpo", NULL), MPP_FUNCTION(0x1, "ge0", "txclkout"), MPP_FUNCTION(0x2, "uart1", "txd"), - MPP_FUNCTION(0x4, "spi1", "clk"), + MPP_FUNCTION(0x4, "spi1", "sck"), MPP_FUNCTION(0x5, "audio", "mclk")), MPP_MODE(6, MPP_FUNCTION(0x0, "gpio", NULL), -- cgit v1.2.3 From 50a7d13d241081838c6cd12b1fdabc36838f9b4c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:15 +0200 Subject: pinctrl: mvebu: armada-xp: rename spi to spi0 After updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'. In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'. This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 22 +++++++++++----------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 22 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index f2d2d40487bb..e8e0a279d700 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -54,20 +54,20 @@ mpp32 32 gpio, tdm(int3), sd0(d0) mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) -mpp36 36 gpio, spi(mosi) -mpp37 37 gpio, spi(miso) -mpp38 38 gpio, spi(sck) -mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) -mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), +mpp36 36 gpio, spi0(mosi) +mpp37 37 gpio, spi0(miso) +mpp38 38 gpio, spi0(sck) +mpp39 39 gpio, spi0(cs0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) +mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), pcie(clkreq1) mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) -mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout) +mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) -mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt) +mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), ref(clkout) mpp48 48 gpio, dev(clkout), dev(burst/last) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index fb5ffa57d90d..74ff2118a9ed 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -224,25 +224,25 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)), MPP_MODE(36, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)), MPP_MODE(39, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)), MPP_MODE(40, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), @@ -257,32 +257,32 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), MPP_MODE(48, -- cgit v1.2.3 From 88b355f1e4e517b636bc5c4b2fb53ec55ccc578d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:17 +0200 Subject: pinctrl: mvebu: armada-xp: add spi1 function The latest Armada XP datasheet documents that some of the MPP pins can be used to access the second SPI bus, labelled 'spi1'. This commit adds the corresponding pins in the pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 26 +++++++++++++--------- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 25 +++++++++++++++------ 2 files changed, 33 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index e8e0a279d700..5f64ee1dd968 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -31,11 +31,11 @@ mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd0), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd1), lcd(d15) +mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) -mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) -mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) +mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) +mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) @@ -58,17 +58,21 @@ mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso) mpp38 38 gpio, spi0(sck) mpp39 39 gpio, spi0(cs0) -mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), + spi1(cs1) mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), - pcie(clkreq1) + pcie(clkreq1), spi1(cs2) mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) -mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout) +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), + spi1(cs3) mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), - dram(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt) + dram(bat), spi1(cs4) +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), + spi1(cs5) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), + spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), - ref(clkout) + ref(clkout), spi1(cs7) mpp48 48 gpio, dev(clkout), dev(burst/last) * Marvell Armada XP (mv78260 and mv78460 only) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 74ff2118a9ed..467446220c98 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -109,11 +109,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -124,11 +126,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -239,14 +243,16 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), @@ -258,33 +264,38 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), -- cgit v1.2.3 From fb53b61d77684b268e71246a3042a5f28ed14eb6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:18 +0200 Subject: pinctrl: mvebu: armada-xp: add nand rb function The latest version of the Armada XP datasheet documents a new NAND-related MPP function on MPP48, for which this commit adds support. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 5f64ee1dd968..bd8af477cd4a 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -73,7 +73,7 @@ mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), ref(clkout), spi1(cs7) -mpp48 48 gpio, dev(clkout), dev(burst/last) +mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) * Marvell Armada XP (mv78260 and mv78460 only) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 467446220c98..937d868007c1 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -299,7 +299,8 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "nand", "rb", V_MV78230_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)), -- cgit v1.2.3 From b19bf379767943f0c094490c52f3d75f9397b503 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:19 +0200 Subject: pinctrl: mvebu: armada-xp: add dram functions The latest Armada XP datasheet documents several new DRAM related functions on various MPPs. This commit adds the description of these new functions in the Armada XP pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 7 +++++-- 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt index bd8af477cd4a..76da7222ff92 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -51,8 +51,8 @@ mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) mpp31 31 gpio, tdm(int2), sd0(cmd) mpp32 32 gpio, tdm(int3), sd0(d0) -mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat) -mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) +mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) mpp36 36 gpio, spi0(mosi) mpp37 37 gpio, spi0(miso) @@ -68,7 +68,7 @@ mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), dram(bat), spi1(cs4) mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), - spi1(cs5) + spi1(cs5), dram(vttctrl) mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), spi1(cs6) mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 937d868007c1..bf70e0953576 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -215,12 +215,14 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)), MPP_MODE(34, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "dram", "deccerr", V_MV78230_PLUS)), MPP_MODE(35, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS), @@ -280,6 +282,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), -- cgit v1.2.3 From 503cfd9f8adc1cb886f06b700c2edc794fe14d50 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:20 +0200 Subject: pinctrl: mvebu: armada-38x: add sata functions The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 203220d2392f..066e26a42994 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -32,11 +32,11 @@ mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(c mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] -mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) +mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt) mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) -mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) +mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index b5006f769d59..8b401b5ad13f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -133,7 +133,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6810_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), @@ -161,7 +162,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6810_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS), -- cgit v1.2.3 From 9ce28fccb0e69e85e0432e4f416f4d1afebb4dba Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:21 +0200 Subject: pinctrl: mvebu: armada-38x: add nand functions The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 066e26a42994..278887d204b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -56,9 +56,9 @@ mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) -mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) +mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] mpp45 45 gpio, ref(clk_out0), pcie0(rstout) mpp46 46 gpio, ref(clk_out1), pcie0(rstout) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 8b401b5ad13f..ac8f2973374b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -268,7 +268,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6810_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS), @@ -280,7 +281,8 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6810_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), -- cgit v1.2.3 From f7ad5b29ce7272da9589aabfa4d94502881b9556 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:22 +0200 Subject: pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 12 ++++++------ drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 18 ++++++++++++------ 2 files changed, 18 insertions(+), 12 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 278887d204b5..4330676f890d 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -60,8 +60,8 @@ mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burs mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] -mpp45 45 gpio, ref(clk_out0), pcie0(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout) +mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd) mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) @@ -70,10 +70,10 @@ mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) -mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi) -mpp57 57 gpio, spi1(sck), sd0(clk) -mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) +mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index ac8f2973374b..370c73b52ea0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -292,11 +292,13 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), @@ -356,24 +358,28 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(56, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS), - MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(57, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), MPP_MODE(58, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS), MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), MPP_MODE(59, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), -- cgit v1.2.3 From f9dbbe011cce41905db77b97e38928b30b1792d5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:23 +0200 Subject: pinctrl: mvebu: armada-38x: add ptp functions The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 6 +++--- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 9 ++++++--- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt index 4330676f890d..54ec4c0a0d0e 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -66,9 +66,9 @@ mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3 mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr) -mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq) mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 370c73b52ea0..6ec82c62dff7 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -331,20 +331,23 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "trig", V_88F6810_PLUS)), MPP_MODE(52, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "clk", V_88F6810_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS), MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS), - MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)), + MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ptp", "evreq", V_88F6810_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), -- cgit v1.2.3 From c0adb877a2491669c58afbf79e1b921d8e2b79b9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:24 +0200 Subject: pinctrl: mvebu: armada-39x: add missing PCIe functions The latest version of the Armada 39x datasheet documents several new PCIe related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 1dd76e953725..2e4725fbef73 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -27,10 +27,10 @@ mpp9 9 gpio, dev(ad11), ptp(clk) mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) -mpp13 13 gpio, dev(ad15), led(data) +mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, dram(deccerr), spi0(miso), i2c1(sda) +mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index 08ee427d5015..afab0c1a886a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -95,6 +95,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_MODE(13, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -110,6 +111,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), -- cgit v1.2.3 From 6afc0c0f5bcffd3d0c47d464b02030d54aac91bf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:25 +0200 Subject: pinctrl: mvebu: armada-39x: add missing SATA functions The latest version of the Armada 39x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,armada-39x-pinctrl.txt | 14 +++++++++----- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 9 +++++++++ 2 files changed, 18 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 2e4725fbef73..bceb6c59a649 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -31,11 +31,12 @@ mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) -mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) +mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), ge(rxd0) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), + sata1(prsnt) [1], ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) @@ -58,12 +59,15 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], + sata3(prsnt) [1], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], led(data) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], + sata3(prsnt) [1], led(data) mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd0(d5), ua2(rxd) +mpp49 49 gpio, sata2(prsnt) [1], sata3(prsnt) [1], tdm(fsync) [1], + audio(lrclk) [1], sd0(d5), ua2(rxd) mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index afab0c1a886a..bae1199486f3 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -117,6 +117,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -141,6 +143,7 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6928), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -262,6 +265,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -278,6 +283,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -290,6 +297,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)), MPP_MODE(49, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), + MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS), -- cgit v1.2.3 From e73ac02dc132dcef1add62a1fac3e77a7ce17371 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 9 Jun 2015 18:47:26 +0200 Subject: pinctrl: mvebu: armada-39x: add support for Armada 395 variant The Armada 39x SoC family has grown a new variant, the Armada 395, which sits between the Armada 390 and Armada 398 in terms of features. This commit adds support for this additional variant to the Armada 39x pinctrl driver. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- .../pinctrl/marvell,armada-39x-pinctrl.txt | 30 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 40 +++++++++++++--------- 2 files changed, 39 insertions(+), 31 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt index bceb6c59a649..a40b60f1ca4c 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -4,8 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl" - depending on the specific variant of the SoC being used. +- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or + "marvell,88f6928-pinctrl" depending on the specific variant of the + SoC being used. - reg: register specifier of MPP registers Available mpp pins/groups and functions: @@ -59,19 +60,19 @@ mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) -mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], - sata3(prsnt) [1], led(clk) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [1], - sata3(prsnt) [1], led(data) -mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [1], audio(mclk) [1], sd0(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, sata2(prsnt) [1], sata3(prsnt) [1], tdm(fsync) [1], - audio(lrclk) [1], sd0(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd0(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], dram(deccerr), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(int) [1], audio(sdi) [1], sd0(d6), i2c3(sck) -mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [1], audio(bclk) [1], sd0(d7), i2c3(sda) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2], + audio(lrclk) [2], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd) +mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd) +mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda) mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) @@ -79,4 +80,5 @@ mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) -[1]: only available on 88F6928 +[1]: only available on 88F6925/88F6928 +[2]: only available on 88F6928 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index bae1199486f3..fcfe9b478a2e 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -36,8 +36,10 @@ static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config) enum { V_88F6920 = BIT(0), - V_88F6928 = BIT(1), - V_88F6920_PLUS = (V_88F6920 | V_88F6928), + V_88F6925 = BIT(1), + V_88F6928 = BIT(2), + V_88F6920_PLUS = (V_88F6920 | V_88F6925 | V_88F6928), + V_88F6925_PLUS = (V_88F6925 | V_88F6928), }; static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { @@ -117,8 +119,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS), - MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -127,23 +129,23 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)), MPP_MODE(19, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)), MPP_MODE(20, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS), MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)), MPP_MODE(21, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS), - MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS), - MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), @@ -263,8 +265,8 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)), @@ -281,14 +283,14 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928), MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928), MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS), MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928), @@ -325,16 +327,16 @@ static struct mvebu_mpp_mode armada_39x_mpp_modes[] = { MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)), MPP_MODE(53, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6928), MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928), MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)), MPP_MODE(54, MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS), - MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6928), - MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6928), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS), MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS), MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6920_PLUS), MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)), @@ -378,6 +380,10 @@ static const struct of_device_id armada_39x_pinctrl_of_match[] = { .compatible = "marvell,mv88f6920-pinctrl", .data = (void *) V_88F6920, }, + { + .compatible = "marvell,mv88f6925-pinctrl", + .data = (void *) V_88F6925, + }, { .compatible = "marvell,mv88f6928-pinctrl", .data = (void *) V_88F6928, -- cgit v1.2.3 From 0ba82c955749937ea9dc09b62b8414eb4f0755e7 Mon Sep 17 00:00:00 2001 From: Cyrille Pitchen Date: Tue, 9 Jun 2015 18:22:16 +0200 Subject: i2c: at91: update documentation for DT bindings add a new value "atmel,sama5d2-i2c" for the "compatible" property. add a new optional property "atmel,fifo-size" to enable FIFO support when available. add missing optional properties "dmas" and "dma-names". Signed-off-by: Cyrille Pitchen Acked-by: Ludovic Desroches Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-at91.txt | 30 ++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index 388f0a275fba..6e81dc153f3b 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -2,8 +2,8 @@ I2C for Atmel platforms Required properties : - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", - "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c" - or "atmel,at91sam9x5-i2c" + "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", + "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c" - reg: physical base address of the controller and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -13,6 +13,10 @@ Required properties : Optional properties: - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 +- dmas: A list of two dma specifiers, one for each entry in dma-names. +- dma-names: should contain "tx" and "rx". +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO + capable I2C controllers. - Child nodes conforming to i2c bus binding Examples : @@ -32,3 +36,25 @@ i2c0: i2c@fff84000 { pagesize = <128>; } } + +i2c0: i2c@f8034600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8034600 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(11)>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(12)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0>; + atmel,fifo-size = <16>; + + wm8731: wm8731@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; +}; -- cgit v1.2.3 From dd1aa2524bc55345ede0b13853c54e1b0be22b9f Mon Sep 17 00:00:00 2001 From: Kamal Dasu Date: Tue, 9 Jun 2015 15:36:20 -0400 Subject: i2c: brcmstb: Add Broadcom settop SoC i2c controller driver Adding support for i2c controller driver for Broadcom settop SoCs. Signed-off-by: Kamal Dasu [wsa: removed superfluous owner in platform_driver] Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-brcmstb.txt | 28 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-brcmstb.c | 694 +++++++++++++++++++++ 4 files changed, 733 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt create mode 100644 drivers/i2c/busses/i2c-brcmstb.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt new file mode 100644 index 000000000000..d6f724efdcf2 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt @@ -0,0 +1,28 @@ +Broadcom stb bsc iic master controller + +Required properties: + +- compatible: should be "brcm,brcmstb-i2c" +- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz + valid values are 375000, 390000, 187500, 200000 + 93750, 97500, 46875 and 50000 +- reg: specifies the base physical address and size of the registers + +Optional properties : + +- interrupt-parent: specifies the phandle to the parent interrupt controller + this one is cascaded from +- interrupts: specifies the interrupt number, the irq line to be used +- interrupt-names: Interrupt name string + +Example: + +bsca: i2c@f0406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&irq0_intc>; + reg = <0xf0406200 0x58>; + interrupts = <0x18>; + interrupt-names = "upg_bsca"; +}; + diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 8a639dce5173..b8c3d6b53861 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -392,6 +392,16 @@ config I2C_BCM_KONA If you do not need KONA I2C interface, say N. +config I2C_BRCMSTB + tristate "BRCM Settop I2C controller" + depends on ARCH_BRCMSTB || COMPILE_TEST + default y + help + If you say yes to this option, support will be included for the + I2C interface on the Broadcom Settop SoCs. + + If you do not need I2C interface, say N. + config I2C_BLACKFIN_TWI tristate "Blackfin TWI I2C support" depends on BLACKFIN diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 65995423c680..e5f537c80da0 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o # Other I2C/SMBus bus drivers obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o +obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o obj-$(CONFIG_I2C_OPAL) += i2c-opal.o diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c new file mode 100644 index 000000000000..8e9637eea512 --- /dev/null +++ b/drivers/i2c/busses/i2c-brcmstb.c @@ -0,0 +1,694 @@ +/* + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define N_DATA_REGS 8 +#define N_DATA_BYTES (N_DATA_REGS * 4) + +/* BSC count register field definitions */ +#define BSC_CNT_REG1_MASK 0x0000003f +#define BSC_CNT_REG1_SHIFT 0 +#define BSC_CNT_REG2_MASK 0x00000fc0 +#define BSC_CNT_REG2_SHIFT 6 + +/* BSC CTL register field definitions */ +#define BSC_CTL_REG_DTF_MASK 0x00000003 +#define BSC_CTL_REG_SCL_SEL_MASK 0x00000030 +#define BSC_CTL_REG_SCL_SEL_SHIFT 4 +#define BSC_CTL_REG_INT_EN_MASK 0x00000040 +#define BSC_CTL_REG_INT_EN_SHIFT 6 +#define BSC_CTL_REG_DIV_CLK_MASK 0x00000080 + +/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */ +#define BSC_IIC_EN_RESTART_MASK 0x00000040 +#define BSC_IIC_EN_NOSTART_MASK 0x00000020 +#define BSC_IIC_EN_NOSTOP_MASK 0x00000010 +#define BSC_IIC_EN_NOACK_MASK 0x00000004 +#define BSC_IIC_EN_INTRP_MASK 0x00000002 +#define BSC_IIC_EN_ENABLE_MASK 0x00000001 + +/* BSC_CTLHI control register field definitions */ +#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080 +#define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040 +#define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 +#define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001 + +#define I2C_TIMEOUT 100 /* msecs */ + +/* Condition mask used for non combined transfer */ +#define COND_RESTART BSC_IIC_EN_RESTART_MASK +#define COND_NOSTART BSC_IIC_EN_NOSTART_MASK +#define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK +#define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP) + +/* BSC data transfer direction */ +#define DTF_WR_MASK 0x00000000 +#define DTF_RD_MASK 0x00000001 +/* BSC data transfer direction combined format */ +#define DTF_RD_WR_MASK 0x00000002 +#define DTF_WR_RD_MASK 0x00000003 + +#define INT_ENABLE true +#define INT_DISABLE false + +/* BSC block register map structure to cache fields to be written */ +struct bsc_regs { + u32 chip_address; /* slave address */ + u32 data_in[N_DATA_REGS]; /* tx data buffer*/ + u32 cnt_reg; /* rx/tx data length */ + u32 ctl_reg; /* control register */ + u32 iic_enable; /* xfer enable and status */ + u32 data_out[N_DATA_REGS]; /* rx data buffer */ + u32 ctlhi_reg; /* more control fields */ + u32 scl_param; /* reserved */ +}; + +struct bsc_clk_param { + u32 hz; + u32 scl_mask; + u32 div_mask; +}; + +enum bsc_xfer_cmd { + CMD_WR, + CMD_RD, + CMD_WR_NOACK, + CMD_RD_NOACK, +}; + +static char const *cmd_string[] = { + [CMD_WR] = "WR", + [CMD_RD] = "RD", + [CMD_WR_NOACK] = "WR NOACK", + [CMD_RD_NOACK] = "RD NOACK", +}; + +enum bus_speeds { + SPD_375K, + SPD_390K, + SPD_187K, + SPD_200K, + SPD_93K, + SPD_97K, + SPD_46K, + SPD_50K +}; + +static const struct bsc_clk_param bsc_clk[] = { + [SPD_375K] = { + .hz = 375000, + .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = 0 + }, + [SPD_390K] = { + .hz = 390000, + .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = 0 + }, + [SPD_187K] = { + .hz = 187500, + .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = 0 + }, + [SPD_200K] = { + .hz = 200000, + .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = 0 + }, + [SPD_93K] = { + .hz = 93750, + .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = BSC_CTL_REG_DIV_CLK_MASK + }, + [SPD_97K] = { + .hz = 97500, + .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = BSC_CTL_REG_DIV_CLK_MASK + }, + [SPD_46K] = { + .hz = 46875, + .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = BSC_CTL_REG_DIV_CLK_MASK + }, + [SPD_50K] = { + .hz = 50000, + .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, + .div_mask = BSC_CTL_REG_DIV_CLK_MASK + } +}; + +struct brcmstb_i2c_dev { + struct device *device; + void __iomem *base; + void __iomem *irq_base; + int irq; + struct bsc_regs *bsc_regmap; + struct i2c_adapter adapter; + struct completion done; + bool is_suspended; + u32 clk_freq_hz; +}; + +/* register accessors for both be and le cpu arch */ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define __bsc_readl(_reg) ioread32be(_reg) +#define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) +#else +#define __bsc_readl(_reg) ioread32(_reg) +#define __bsc_writel(_val, _reg) iowrite32(_val, _reg) +#endif + +#define bsc_readl(_dev, _reg) \ + __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) + +#define bsc_writel(_dev, _val, _reg) \ + __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) + +static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev, + bool int_en) +{ + + if (int_en) + /* Enable BSC CTL interrupt line */ + dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; + else + /* Disable BSC CTL interrupt line */ + dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK; + + barrier(); + bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); +} + +static irqreturn_t brcmstb_i2c_isr(int irq, void *devid) +{ + struct brcmstb_i2c_dev *dev = devid; + u32 status_bsc_ctl = bsc_readl(dev, ctl_reg); + u32 status_iic_intrp = bsc_readl(dev, iic_enable); + + dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n", + status_bsc_ctl, status_iic_intrp); + + if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK)) + return IRQ_NONE; + + brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); + complete_all(&dev->done); + + dev_dbg(dev->device, "isr handled"); + return IRQ_HANDLED; +} + +/* Wait for device to be ready */ +static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); + + while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) { + if (time_after(jiffies, timeout)) + return -ETIMEDOUT; + cpu_relax(); + } + return 0; +} + +/* i2c xfer completion function, handles both irq and polling mode */ +static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev) +{ + int ret = 0; + unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT); + + if (dev->irq >= 0) { + if (!wait_for_completion_timeout(&dev->done, timeout)) + ret = -ETIMEDOUT; + } else { + /* we are in polling mode */ + u32 bsc_intrp; + unsigned long time_left = jiffies + timeout; + + do { + bsc_intrp = bsc_readl(dev, iic_enable) & + BSC_IIC_EN_INTRP_MASK; + if (time_after(jiffies, time_left)) { + ret = -ETIMEDOUT; + break; + } + cpu_relax(); + } while (!bsc_intrp); + } + + if (dev->irq < 0 || ret == -ETIMEDOUT) + brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); + + return ret; +} + +/* Set xfer START/STOP conditions for subsequent transfer */ +static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev, + u32 cond_flag) +{ + u32 regval = dev->bsc_regmap->iic_enable; + + dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag; +} + +/* Send I2C request check completion */ +static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev, + enum bsc_xfer_cmd cmd) +{ + int rc = 0; + struct bsc_regs *pi2creg = dev->bsc_regmap; + + /* Make sure the hardware is ready */ + rc = brcmstb_i2c_wait_if_busy(dev); + if (rc < 0) + return rc; + + /* only if we are in interrupt mode */ + if (dev->irq >= 0) + reinit_completion(&dev->done); + + /* enable BSC CTL interrupt line */ + brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE); + + /* initiate transfer by setting iic_enable */ + pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK; + bsc_writel(dev, pi2creg->iic_enable, iic_enable); + + /* Wait for transaction to finish or timeout */ + rc = brcmstb_i2c_wait_for_completion(dev); + if (rc) { + dev_dbg(dev->device, "intr timeout for cmd %s\n", + cmd_string[cmd]); + goto cmd_out; + } + + if ((CMD_RD || CMD_WR) && + bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) { + rc = -EREMOTEIO; + dev_dbg(dev->device, "controller received NOACK intr for %s\n", + cmd_string[cmd]); + } + +cmd_out: + bsc_writel(dev, 0, cnt_reg); + bsc_writel(dev, 0, iic_enable); + + return rc; +} + +/* Actual data transfer through the BSC master */ +static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, + u8 *buf, unsigned int len, + struct i2c_msg *pmsg) +{ + int cnt, byte, rc; + enum bsc_xfer_cmd cmd; + u32 ctl_reg; + struct bsc_regs *pi2creg = dev->bsc_regmap; + int no_ack = pmsg->flags & I2C_M_IGNORE_NAK; + + /* see if the transaction needs to check NACK conditions */ + if (no_ack || len <= N_DATA_BYTES) { + cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK + : CMD_WR_NOACK; + pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK; + } else { + cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR; + pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK; + } + bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg); + + /* set data transfer direction */ + ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK; + if (cmd == CMD_WR || cmd == CMD_WR_NOACK) + pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK; + else + pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; + + /* set the read/write length */ + bsc_writel(dev, BSC_CNT_REG1_MASK & (len << BSC_CNT_REG1_SHIFT), + cnt_reg); + + /* Write data into data_in register */ + if (cmd == CMD_WR || cmd == CMD_WR_NOACK) { + for (cnt = 0; cnt < len; cnt += 4) { + u32 word = 0; + + for (byte = 0; byte < 4; byte++) { + word >>= 8; + if ((cnt + byte) < len) + word |= buf[cnt + byte] << 24; + } + bsc_writel(dev, word, data_in[cnt >> 2]); + } + } + + /* Initiate xfer, the function will return on completion */ + rc = brcmstb_send_i2c_cmd(dev, cmd); + + if (rc != 0) { + dev_dbg(dev->device, "%s failure", cmd_string[cmd]); + return rc; + } + + if (cmd == CMD_RD || cmd == CMD_RD_NOACK) { + for (cnt = 0; cnt < len; cnt += 4) { + u32 data = bsc_readl(dev, data_out[cnt >> 2]); + + for (byte = 0; byte < 4 && + (byte + cnt) < len; byte++) { + buf[cnt + byte] = data & 0xff; + data >>= 8; + } + } + } + + return 0; +} + +/* Write a single byte of data to the i2c bus */ +static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev, + u8 *buf, unsigned int nak_expected) +{ + enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK; + + bsc_writel(dev, 1, cnt_reg); + bsc_writel(dev, *buf, data_in); + + return brcmstb_send_i2c_cmd(dev, cmd); +} + +/* Send i2c address */ +static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned char addr; + + if (msg->flags & I2C_M_TEN) { + /* First byte is 11110XX0 where XX is upper 2 bits */ + addr = 0xF0 | ((msg->addr & 0x300) >> 7); + bsc_writel(dev, addr, chip_address); + + /* Second byte is the remaining 8 bits */ + addr = msg->addr & 0xFF; + if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) + return -EREMOTEIO; + + if (msg->flags & I2C_M_RD) { + /* For read, send restart without stop condition */ + brcmstb_set_i2c_start_stop(dev, COND_RESTART + | COND_NOSTOP); + /* Then re-send the first byte with the read bit set */ + addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; + if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) + return -EREMOTEIO; + + } + } else { + addr = msg->addr << 1; + if (msg->flags & I2C_M_RD) + addr |= 1; + + bsc_writel(dev, addr, chip_address); + } + + return 0; +} + +/* Master transfer function */ +static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, + struct i2c_msg msgs[], int num) +{ + struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter); + struct i2c_msg *pmsg; + int rc = 0; + int i; + int bytes_to_xfer; + u8 *tmp_buf; + int len = 0; + + if (dev->is_suspended) + return -EBUSY; + + /* Loop through all messages */ + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + len = pmsg->len; + tmp_buf = pmsg->buf; + + dev_dbg(dev->device, + "msg# %d/%d flg %x buf %x len %d\n", i, + num - 1, pmsg->flags, + pmsg->buf ? pmsg->buf[0] : '0', pmsg->len); + + if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART)) + brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP)); + else + brcmstb_set_i2c_start_stop(dev, + COND_RESTART | COND_NOSTOP); + + /* Send slave address */ + if (!(pmsg->flags & I2C_M_NOSTART)) { + rc = brcmstb_i2c_do_addr(dev, pmsg); + if (rc < 0) { + dev_dbg(dev->device, + "NACK for addr %2.2x msg#%d rc = %d\n", + pmsg->addr, i, rc); + goto out; + } + } + + /* Perform data transfer */ + while (len) { + bytes_to_xfer = min(len, N_DATA_BYTES); + + if (len <= N_DATA_BYTES && i == (num - 1)) + brcmstb_set_i2c_start_stop(dev, + ~(COND_START_STOP)); + + rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf, + bytes_to_xfer, pmsg); + if (rc < 0) + goto out; + + len -= bytes_to_xfer; + tmp_buf += bytes_to_xfer; + } + } + + rc = num; +out: + return rc; + +} + +static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR + | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING; +} + +static const struct i2c_algorithm brcmstb_i2c_algo = { + .master_xfer = brcmstb_i2c_xfer, + .functionality = brcmstb_i2c_functionality, +}; + +static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev) +{ + int i = 0, num_speeds = ARRAY_SIZE(bsc_clk); + u32 clk_freq_hz = dev->clk_freq_hz; + + for (i = 0; i < num_speeds; i++) { + if (bsc_clk[i].hz == clk_freq_hz) { + dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK + | BSC_CTL_REG_DIV_CLK_MASK); + dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask | + bsc_clk[i].div_mask); + bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); + break; + } + } + + /* in case we did not get find a valid speed */ + if (i == num_speeds) { + i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >> + BSC_CTL_REG_SCL_SEL_SHIFT; + dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n", + bsc_clk[i].hz); + } +} + +static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev) +{ + /* 4 byte data register */ + dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; + bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg); + /* set bus speed */ + brcmstb_i2c_set_bus_speed(dev); +} + +static int brcmstb_i2c_probe(struct platform_device *pdev) +{ + int rc = 0; + struct brcmstb_i2c_dev *dev; + struct i2c_adapter *adap; + struct resource *iomem; + const char *int_name; + + /* Allocate memory for private data structure */ + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(struct bsc_regs *), + GFP_KERNEL); + if (!dev->bsc_regmap) + return -ENOMEM; + + platform_set_drvdata(pdev, dev); + dev->device = &pdev->dev; + init_completion(&dev->done); + + /* Map hardware registers */ + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dev->base = devm_ioremap_resource(dev->device, iomem); + if (IS_ERR(dev->base)) { + rc = -ENOMEM; + goto probe_errorout; + } + + rc = of_property_read_string(dev->device->of_node, "interrupt-names", + &int_name); + if (rc < 0) + int_name = NULL; + + /* Get the interrupt number */ + dev->irq = platform_get_irq(pdev, 0); + + /* disable the bsc interrupt line */ + brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); + + /* register the ISR handler */ + rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr, + IRQF_SHARED, + int_name ? int_name : pdev->name, + dev); + + if (rc) { + dev_dbg(dev->device, "falling back to polling mode"); + dev->irq = -1; + } + + if (of_property_read_u32(dev->device->of_node, + "clock-frequency", &dev->clk_freq_hz)) { + dev_warn(dev->device, "setting clock-frequency@%dHz\n", + bsc_clk[0].hz); + dev->clk_freq_hz = bsc_clk[0].hz; + } + + brcmstb_i2c_set_bsc_reg_defaults(dev); + + /* Add the i2c adapter */ + adap = &dev->adapter; + i2c_set_adapdata(adap, dev); + adap->owner = THIS_MODULE; + strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name)); + if (int_name) + strlcat(adap->name, int_name, sizeof(adap->name)); + adap->algo = &brcmstb_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; + rc = i2c_add_adapter(adap); + if (rc) { + dev_err(dev->device, "failed to add adapter\n"); + goto probe_errorout; + } + + dev_info(dev->device, "%s@%dhz registered in %s mode\n", + int_name ? int_name : " ", dev->clk_freq_hz, + (dev->irq >= 0) ? "interrupt" : "polling"); + + return 0; + +probe_errorout: + return rc; +} + +static int brcmstb_i2c_remove(struct platform_device *pdev) +{ + struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&dev->adapter); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int brcmstb_i2c_suspend(struct device *dev) +{ + struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); + + i2c_lock_adapter(&i2c_dev->adapter); + i2c_dev->is_suspended = true; + i2c_unlock_adapter(&i2c_dev->adapter); + + return 0; +} + +static int brcmstb_i2c_resume(struct device *dev) +{ + struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); + + i2c_lock_adapter(&i2c_dev->adapter); + brcmstb_i2c_set_bsc_reg_defaults(i2c_dev); + i2c_dev->is_suspended = false; + i2c_unlock_adapter(&i2c_dev->adapter); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend, + brcmstb_i2c_resume); + +static const struct of_device_id brcmstb_i2c_of_match[] = { + {.compatible = "brcm,brcmstb-i2c"}, + {}, +}; +MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match); + +static struct platform_driver brcmstb_i2c_driver = { + .driver = { + .name = "brcmstb-i2c", + .of_match_table = brcmstb_i2c_of_match, + .pm = &brcmstb_i2c_pm, + }, + .probe = brcmstb_i2c_probe, + .remove = brcmstb_i2c_remove, +}; +module_platform_driver(brcmstb_i2c_driver); + +MODULE_AUTHOR("Kamal Dasu "); +MODULE_DESCRIPTION("Broadcom Settop I2C Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From a6e6b63ee2798f18e0e786feb407cc7846077ea3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Jun 2015 10:11:38 +0900 Subject: power_supply: max17042: Add OF support for setting thresholds The commit edd4ab055931 ("power: max17042_battery: add HEALTH and TEMP_* properties support") added support for setting voltage and temperature thresholds with platform data. For DeviceTree default of 0 was always used. This caused reporting battery health always as over voltage or over heated. Signed-off-by: Krzysztof Kozlowski Fixes: edd4ab055931 ("power: max17042_battery: add HEALTH and TEMP_* properties support") Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power_supply/max17042_battery.txt | 13 +++++++++++++ drivers/power/max17042_battery.c | 9 +++++++++ 2 files changed, 22 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power_supply/max17042_battery.txt b/Documentation/devicetree/bindings/power_supply/max17042_battery.txt index 5bc9b685cf8a..3f3894aaeebc 100644 --- a/Documentation/devicetree/bindings/power_supply/max17042_battery.txt +++ b/Documentation/devicetree/bindings/power_supply/max17042_battery.txt @@ -9,10 +9,23 @@ Optional properties : (datasheet-recommended value is 10000). Defining this property enables current-sense functionality. +Optional threshold properties : + If skipped the condition won't be reported. + - maxim,cold-temp : Temperature threshold to report battery + as cold (in tenths of degree Celsius). + - maxim,over-heat-temp : Temperature threshold to report battery + as over heated (in tenths of degree Celsius). + - maxim,dead-volt : Voltage threshold to report battery + as dead (in mV). + - maxim,over-volt : Voltage threshold to report battery + as over voltage (in mV). + Example: battery-charger@36 { compatible = "maxim,max17042"; reg = <0x36>; maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4300>; }; diff --git a/drivers/power/max17042_battery.c b/drivers/power/max17042_battery.c index 748d9762e89b..e89255764745 100644 --- a/drivers/power/max17042_battery.c +++ b/drivers/power/max17042_battery.c @@ -809,6 +809,15 @@ max17042_get_pdata(struct device *dev) pdata->enable_current_sense = true; } + if (of_property_read_s32(np, "maxim,cold-temp", &pdata->temp_min)) + pdata->temp_min = INT_MIN; + if (of_property_read_s32(np, "maxim,over-heat-temp", &pdata->temp_max)) + pdata->temp_max = INT_MAX; + if (of_property_read_s32(np, "maxim,dead-volt", &pdata->vmin)) + pdata->vmin = INT_MIN; + if (of_property_read_s32(np, "maxim,over-volt", &pdata->vmax)) + pdata->vmax = INT_MAX; + return pdata; } #else -- cgit v1.2.3 From 6f166312c6ea2c010c6425c48506d2bbad491c03 Mon Sep 17 00:00:00 2001 From: Lior Amsalem Date: Tue, 26 May 2015 15:07:34 +0200 Subject: dmaengine: mv_xor: add support for a38x command in descriptor mode The Marvell Armada 38x SoC introduce new features to the XOR engine, especially the fact that the engine mode (MEMCPY/XOR/PQ/etc) can be part of the descriptor and not set through the controller registers. This new feature allows mixing of different commands (even PQ) on the same channel/chain without the need to stop the engine to reconfigure the engine mode. Refactor the driver to be able to use that new feature on the Armada 38x, while keeping the old behaviour on the older SoCs. Signed-off-by: Lior Amsalem Reviewed-by: Ofer Heifetz Signed-off-by: Maxime Ripard Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/mv-xor.txt | 2 +- drivers/dma/mv_xor.c | 82 ++++++++++++++++++++---- drivers/dma/mv_xor.h | 7 ++ 3 files changed, 76 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/dma/mv-xor.txt b/Documentation/devicetree/bindings/dma/mv-xor.txt index 7c6cb7fcecd2..cc29c35266e2 100644 --- a/Documentation/devicetree/bindings/dma/mv-xor.txt +++ b/Documentation/devicetree/bindings/dma/mv-xor.txt @@ -1,7 +1,7 @@ * Marvell XOR engines Required properties: -- compatible: Should be "marvell,orion-xor" +- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor" - reg: Should contain registers location and length (two sets) the first set is the low registers, the second set the high registers for the XOR engine. diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 51433c4020fe..669d0b5029d1 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -30,6 +31,11 @@ #include "dmaengine.h" #include "mv_xor.h" +enum mv_xor_mode { + XOR_MODE_IN_REG, + XOR_MODE_IN_DESC, +}; + static void mv_xor_issue_pending(struct dma_chan *chan); #define to_mv_xor_chan(chan) \ @@ -56,6 +62,24 @@ static void mv_desc_init(struct mv_xor_desc_slot *desc, hw_desc->byte_count = byte_count; } +static void mv_desc_set_mode(struct mv_xor_desc_slot *desc) +{ + struct mv_xor_desc *hw_desc = desc->hw_desc; + + switch (desc->type) { + case DMA_XOR: + case DMA_INTERRUPT: + hw_desc->desc_command |= XOR_DESC_OPERATION_XOR; + break; + case DMA_MEMCPY: + hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY; + break; + default: + BUG(); + return; + } +} + static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, u32 next_desc_addr) { @@ -144,6 +168,25 @@ static void mv_chan_set_mode(struct mv_xor_chan *chan, config &= ~0x7; config |= op_mode; + if (IS_ENABLED(__BIG_ENDIAN)) + config |= XOR_DESCRIPTOR_SWAP; + else + config &= ~XOR_DESCRIPTOR_SWAP; + + writel_relaxed(config, XOR_CONFIG(chan)); + chan->current_type = type; +} + +static void mv_chan_set_mode_to_desc(struct mv_xor_chan *chan) +{ + u32 op_mode; + u32 config = readl_relaxed(XOR_CONFIG(chan)); + + op_mode = XOR_OPERATION_MODE_IN_DESC; + + config &= ~0x7; + config |= op_mode; + #if defined(__BIG_ENDIAN) config |= XOR_DESCRIPTOR_SWAP; #else @@ -151,7 +194,6 @@ static void mv_chan_set_mode(struct mv_xor_chan *chan, #endif writel_relaxed(config, XOR_CONFIG(chan)); - chan->current_type = type; } static void mv_chan_activate(struct mv_xor_chan *chan) @@ -530,6 +572,8 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, sw_desc->type = DMA_XOR; sw_desc->async_tx.flags = flags; mv_desc_init(sw_desc, dest, len, flags); + if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) + mv_desc_set_mode(sw_desc); while (src_cnt--) mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); } @@ -972,7 +1016,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) static struct mv_xor_chan * mv_xor_channel_add(struct mv_xor_device *xordev, struct platform_device *pdev, - int idx, dma_cap_mask_t cap_mask, int irq) + int idx, dma_cap_mask_t cap_mask, int irq, int op_in_desc) { int ret = 0; struct mv_xor_chan *mv_chan; @@ -984,6 +1028,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev, mv_chan->idx = idx; mv_chan->irq = irq; + mv_chan->op_in_desc = op_in_desc; dma_dev = &mv_chan->dmadev; @@ -1044,7 +1089,10 @@ mv_xor_channel_add(struct mv_xor_device *xordev, mv_chan_unmask_interrupts(mv_chan); - mv_chan_set_mode(mv_chan, DMA_XOR); + if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) + mv_chan_set_mode_to_desc(mv_chan); + else + mv_chan_set_mode(mv_chan, DMA_XOR); spin_lock_init(&mv_chan->lock); INIT_LIST_HEAD(&mv_chan->chain); @@ -1069,7 +1117,8 @@ mv_xor_channel_add(struct mv_xor_device *xordev, goto err_free_irq; } - dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", + dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n", + mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode", dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); @@ -1118,6 +1167,13 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, writel(0, base + WINDOW_OVERRIDE_CTRL(1)); } +static const struct of_device_id mv_xor_dt_ids[] = { + { .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG }, + { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC }, + {}, +}; +MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); + static int mv_xor_probe(struct platform_device *pdev) { const struct mbus_dram_target_info *dram; @@ -1125,6 +1181,7 @@ static int mv_xor_probe(struct platform_device *pdev) struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); struct resource *res; int i, ret; + int op_in_desc; dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); @@ -1169,11 +1226,15 @@ static int mv_xor_probe(struct platform_device *pdev) if (pdev->dev.of_node) { struct device_node *np; int i = 0; + const struct of_device_id *of_id = + of_match_device(mv_xor_dt_ids, + &pdev->dev); for_each_child_of_node(pdev->dev.of_node, np) { struct mv_xor_chan *chan; dma_cap_mask_t cap_mask; int irq; + op_in_desc = (int)of_id->data; dma_cap_zero(cap_mask); if (of_property_read_bool(np, "dmacap,memcpy")) @@ -1190,7 +1251,7 @@ static int mv_xor_probe(struct platform_device *pdev) } chan = mv_xor_channel_add(xordev, pdev, i, - cap_mask, irq); + cap_mask, irq, op_in_desc); if (IS_ERR(chan)) { ret = PTR_ERR(chan); irq_dispose_mapping(irq); @@ -1219,7 +1280,8 @@ static int mv_xor_probe(struct platform_device *pdev) } chan = mv_xor_channel_add(xordev, pdev, i, - cd->cap_mask, irq); + cd->cap_mask, irq, + XOR_MODE_IN_REG); if (IS_ERR(chan)) { ret = PTR_ERR(chan); goto err_channel_add; @@ -1265,14 +1327,6 @@ static int mv_xor_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_OF -static const struct of_device_id mv_xor_dt_ids[] = { - { .compatible = "marvell,orion-xor", }, - {}, -}; -MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); -#endif - static struct platform_driver mv_xor_driver = { .probe = mv_xor_probe, .remove = mv_xor_remove, diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h index 0e302b3a33ad..ac1ce87935de 100644 --- a/drivers/dma/mv_xor.h +++ b/drivers/dma/mv_xor.h @@ -30,9 +30,14 @@ /* Values for the XOR_CONFIG register */ #define XOR_OPERATION_MODE_XOR 0 #define XOR_OPERATION_MODE_MEMCPY 2 +#define XOR_OPERATION_MODE_IN_DESC 7 #define XOR_DESCRIPTOR_SWAP BIT(14) #define XOR_DESC_SUCCESS 0x40000000 +#define XOR_DESC_OPERATION_XOR (0 << 24) +#define XOR_DESC_OPERATION_CRC32C (1 << 24) +#define XOR_DESC_OPERATION_MEMCPY (2 << 24) + #define XOR_DESC_DMA_OWNED BIT(31) #define XOR_DESC_EOD_INT_EN BIT(31) @@ -96,6 +101,7 @@ struct mv_xor_device { * @all_slots: complete domain of slots usable by the channel * @slots_allocated: records the actual size of the descriptor slot pool * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs + * @op_in_desc: new mode of driver, each op is writen to descriptor. */ struct mv_xor_chan { int pending; @@ -116,6 +122,7 @@ struct mv_xor_chan { struct list_head all_slots; int slots_allocated; struct tasklet_struct irq_tasklet; + int op_in_desc; char dummy_src[MV_XOR_MIN_BYTE_COUNT]; char dummy_dst[MV_XOR_MIN_BYTE_COUNT]; dma_addr_t dummy_src_addr, dummy_dst_addr; -- cgit v1.2.3 From 4acf6d7f6837c12551c37e8c9bfc129d686a18c6 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 10 Jun 2015 13:15:44 +0100 Subject: ASoC: qcom: document apq8016 sbc machine driver bindings This patch adds bindings for apq8016 sbc machine driver. APQ8016 has 4 MI2S which can be configured to different sinks like internal codec/external codec, this connection and various parameters are controlled via 2 iomux registers. Acked-by: Kenneth Westfield Signed-off-by: Srinivas Kandagatla Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/qcom,apq8016-sbc.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt new file mode 100644 index 000000000000..48129368d4d9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt @@ -0,0 +1,60 @@ +* Qualcomm Technologies APQ8016 SBC ASoC machine driver + +This node models the Qualcomm Technologies APQ8016 SBC ASoC machine driver + +Required properties: + +- compatible : "qcom,apq8016-sbc-sndcard" + +- pinctrl-N : One property must exist for each entry in + pinctrl-names. See ../pinctrl/pinctrl-bindings.txt + for details of the property values. +- pinctrl-names : Must contain a "default" entry. +- reg : Must contain an address for each entry in reg-names. +- reg-names : A list which must include the following entries: + * "mic-iomux" + * "spkr-iomux" +- qcom,model : Name of the sound card. + +Dai-link subnode properties and subnodes: + +Required dai-link subnodes: + +- cpu : CPU sub-node +- codec : CODEC sub-node + +Required CPU/CODEC subnodes properties: + +-link-name : Name of the dai link. +-sound-dai : phandle and port of CPU/CODEC +-capture-dai : phandle and port of CPU/CODEC + +Example: + +sound: sound { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + qcom,model = "DB410c"; + + /* I2S - Internal codec */ + internal-dai-link@0 { + cpu { /* PRIMARY */ + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&wcd_codec 0>; + }; + }; + + /* External Primary or External Secondary -ADV7533 HDMI */ + external-dai-link@0 { + link-name = "ADV7533"; + cpu { /* QUAT */ + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; +}; -- cgit v1.2.3 From fb5ab0e7473d41e2a9db0fcb569faf337d595838 Mon Sep 17 00:00:00 2001 From: Oder Chiou Date: Wed, 10 Jun 2015 14:27:58 +0800 Subject: ASoC: rt5645: add device tree support Modify the RT5645 driver to parse platform data from device tree. Write a DT binding document to describe those properties. Signed-off-by: Bard Liao Signed-off-by: Oder Chiou Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5645.txt | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rt5645.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/rt5645.txt b/Documentation/devicetree/bindings/sound/rt5645.txt new file mode 100644 index 000000000000..7cee1f518f59 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt5645.txt @@ -0,0 +1,72 @@ +RT5650/RT5645 audio CODEC + +This device supports I2C only. + +Required properties: + +- compatible : One of "realtek,rt5645" or "realtek,rt5650". + +- reg : The I2C address of the device. + +- interrupts : The CODEC's interrupt output. + +Optional properties: + +- hp-detect-gpios: + a GPIO spec for the external headphone detect pin. If jd-mode = 0, + we will get the JD status by getting the value of hp-detect-gpios. + +- realtek,in2-differential + Boolean. Indicate MIC2 input are differential, rather than single-ended. + +- realtek,dmic1-data-pin + 0: dmic1 is not used + 1: using IN2P pin as dmic1 data pin + 2: using GPIO6 pin as dmic1 data pin + 3: using GPIO10 pin as dmic1 data pin + 4: using GPIO12 pin as dmic1 data pin + +- realtek,dmic2-data-pin + 0: dmic2 is not used + 1: using IN2N pin as dmic2 data pin + 2: using GPIO5 pin as dmic2 data pin + 3: using GPIO11 pin as dmic2 data pin + +-- realtek,jd-mode : The JD mode of rt5645/rt5650 + 0 : rt5645/rt5650 JD function is not used + 1 : Mode-0 (VDD=3.3V), two port jack detection + 2 : Mode-1 (VDD=3.3V), one port jack detection + 3 : Mode-2 (VDD=1.8V), one port jack detection + +Pins on the device (for linking into audio routes) for RT5645/RT5650: + + * DMIC L1 + * DMIC R1 + * DMIC L2 + * DMIC R2 + * IN1P + * IN1N + * IN2P + * IN2N + * Haptic Generator + * HPOL + * HPOR + * LOUTL + * LOUTR + * PDM1L + * PDM1R + * SPOL + * SPOR + +Example: + +codec: rt5650@1a { + compatible = "realtek,rt5650"; + reg = <0x1a>; + hp-detect-gpios = <&gpio 19 0>; + interrupt-parent = <&gpio>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + realtek,dmic-en = "true"; + realtek,en-jd-func = "true"; + realtek,jd-mode = <3>; +}; \ No newline at end of file -- cgit v1.2.3 From aaf2cbca46a569b1ec4c292b03fbe2a0a1217e2f Mon Sep 17 00:00:00 2001 From: Jacek Anaszewski Date: Mon, 8 Jun 2015 02:02:18 -0700 Subject: Documentation: leds: Add description of v4l2-flash sub-device This patch extends LED Flash class documention by the description of interactions with v4l2-flash sub-device. Signed-off-by: Jacek Anaszewski Acked-by: Kyungmin Park Cc: Richard Purdie Acked-by: Sakari Ailus Signed-off-by: Bryan Wu --- Documentation/leds/leds-class-flash.txt | 51 +++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'Documentation') diff --git a/Documentation/leds/leds-class-flash.txt b/Documentation/leds/leds-class-flash.txt index 19bb67355424..8da3c6f4b60b 100644 --- a/Documentation/leds/leds-class-flash.txt +++ b/Documentation/leds/leds-class-flash.txt @@ -20,3 +20,54 @@ Following sysfs attributes are exposed for controlling flash LED devices: - max_flash_timeout - flash_strobe - flash_fault + + +V4L2 flash wrapper for flash LEDs +================================= + +A LED subsystem driver can be controlled also from the level of VideoForLinux2 +subsystem. In order to enable this CONFIG_V4L2_FLASH_LED_CLASS symbol has to +be defined in the kernel config. + +The driver must call the v4l2_flash_init function to get registered in the +V4L2 subsystem. The function takes six arguments: +- dev : flash device, e.g. an I2C device +- of_node : of_node of the LED, may be NULL if the same as device's +- fled_cdev : LED flash class device to wrap +- iled_cdev : LED flash class device representing indicator LED associated with + fled_cdev, may be NULL +- ops : V4L2 specific ops + * external_strobe_set - defines the source of the flash LED strobe - + V4L2_CID_FLASH_STROBE control or external source, typically + a sensor, which makes it possible to synchronise the flash + strobe start with exposure start, + * intensity_to_led_brightness and led_brightness_to_intensity - perform + enum led_brightness <-> V4L2 intensity conversion in a device + specific manner - they can be used for devices with non-linear + LED current scale. +- config : configuration for V4L2 Flash sub-device + * dev_name - the name of the media entity, unique in the system, + * flash_faults - bitmask of flash faults that the LED flash class + device can report; corresponding LED_FAULT* bit definitions are + available in , + * torch_intensity - constraints for the LED in TORCH mode + in microamperes, + * indicator_intensity - constraints for the indicator LED + in microamperes, + * has_external_strobe - determines whether the flash strobe source + can be switched to external, + +On remove the v4l2_flash_release function has to be called, which takes one +argument - struct v4l2_flash pointer returned previously by v4l2_flash_init. +This function can be safely called with NULL or error pointer argument. + +Please refer to drivers/leds/leds-max77693.c for an exemplary usage of the +v4l2 flash wrapper. + +Once the V4L2 sub-device is registered by the driver which created the Media +controller device, the sub-device node acts just as a node of a native V4L2 +flash API device would. The calls are simply routed to the LED flash API. + +Opening the V4L2 flash sub-device makes the LED subsystem sysfs interface +unavailable. The interface is re-enabled after the V4L2 flash sub-device +is closed. -- cgit v1.2.3 From ec3bd0e68a679a7af2c46af1ddc9af8b534a8b0e Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Wed, 10 Jun 2015 20:23:24 +0100 Subject: ARM: 8391/1: l2c: add options to overwrite prefetching behavior These options make it possible to overwrites the data and instruction prefetching behavior of the arm pl310 cache controller. Signed-off-by: Hauke Mehrtens Acked-by: Florian Fainelli Signed-off-by: Russell King --- Documentation/devicetree/bindings/arm/l2cc.txt | 5 +++++ arch/arm/mm/cache-l2x0.c | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 0dbabe9a6b0a..2251dccb141e 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -67,6 +67,11 @@ Optional properties: disable if zero. - arm,prefetch-offset : Override prefetch offset value. Valid values are 0-7, 15, 23, and 31. +- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> + (forcibly enable), property absent (retain settings set by firmware) +- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) Example: diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 90599f60ff02..71b3d3309024 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1221,6 +1221,26 @@ static void __init l2c310_of_parse(const struct device_node *np, pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n"); } + ret = of_property_read_u32(np, "prefetch-data", &val); + if (ret == 0) { + if (val) + prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; + else + prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + } else if (ret != -EINVAL) { + pr_err("L2C-310 OF prefetch-data property value is missing\n"); + } + + ret = of_property_read_u32(np, "prefetch-instr", &val); + if (ret == 0) { + if (val) + prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; + else + prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + } else if (ret != -EINVAL) { + pr_err("L2C-310 OF prefetch-instr property value is missing\n"); + } + l2x0_saved_regs.prefetch_ctrl = prefetch; } -- cgit v1.2.3 From 2157e7b82f3b81f57bd80cd67cef09ef26e5f74c Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Fri, 5 Jun 2015 16:35:25 +1000 Subject: vfio: powerpc/spapr: Register memory and define IOMMU v2 The existing implementation accounts the whole DMA window in the locked_vm counter. This is going to be worse with multiple containers and huge DMA windows. Also, real-time accounting would requite additional tracking of accounted pages due to the page size difference - IOMMU uses 4K pages and system uses 4K or 64K pages. Another issue is that actual pages pinning/unpinning happens on every DMA map/unmap request. This does not affect the performance much now as we spend way too much time now on switching context between guest/userspace/host but this will start to matter when we add in-kernel DMA map/unmap acceleration. This introduces a new IOMMU type for SPAPR - VFIO_SPAPR_TCE_v2_IOMMU. New IOMMU deprecates VFIO_IOMMU_ENABLE/VFIO_IOMMU_DISABLE and introduces 2 new ioctls to register/unregister DMA memory - VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY - which receive user space address and size of a memory region which needs to be pinned/unpinned and counted in locked_vm. New IOMMU splits physical pages pinning and TCE table update into 2 different operations. It requires: 1) guest pages to be registered first 2) consequent map/unmap requests to work only with pre-registered memory. For the default single window case this means that the entire guest (instead of 2GB) needs to be pinned before using VFIO. When a huge DMA window is added, no additional pinning will be required, otherwise it would be guest RAM + 2GB. The new memory registration ioctls are not supported by VFIO_SPAPR_TCE_IOMMU. Dynamic DMA window and in-kernel acceleration will require memory to be preregistered in order to work. The accounting is done per the user process. This advertises v2 SPAPR TCE IOMMU and restricts what the userspace can do with v1 or v2 IOMMUs. In order to support memory pre-registration, we need a way to track the use of every registered memory region and only allow unregistration if a region is not in use anymore. So we need a way to tell from what region the just cleared TCE was from. This adds a userspace view of the TCE table into iommu_table struct. It contains userspace address, one per TCE entry. The table is only allocated when the ownership over an IOMMU group is taken which means it is only used from outside of the powernv code (such as VFIO). As v2 IOMMU supports IODA2 and pre-IODA2 IOMMUs (which do not support DDW API), this creates a default DMA window for IODA2 for consistency. Signed-off-by: Alexey Kardashevskiy [aw: for the vfio related changes] Acked-by: Alex Williamson Reviewed-by: David Gibson Signed-off-by: Michael Ellerman --- Documentation/vfio.txt | 31 ++- arch/powerpc/include/asm/iommu.h | 6 + drivers/vfio/vfio_iommu_spapr_tce.c | 501 ++++++++++++++++++++++++++++++------ include/uapi/linux/vfio.h | 27 ++ 4 files changed, 482 insertions(+), 83 deletions(-) (limited to 'Documentation') diff --git a/Documentation/vfio.txt b/Documentation/vfio.txt index 4c746a7e717a..dcc37e109c68 100644 --- a/Documentation/vfio.txt +++ b/Documentation/vfio.txt @@ -289,10 +289,12 @@ PPC64 sPAPR implementation note This implementation has some specifics: -1) Only one IOMMU group per container is supported as an IOMMU group -represents the minimal entity which isolation can be guaranteed for and -groups are allocated statically, one per a Partitionable Endpoint (PE) +1) On older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per +container is supported as an IOMMU table is allocated at the boot time, +one table per a IOMMU group which is a Partitionable Endpoint (PE) (PE is often a PCI domain but not always). +Newer systems (POWER8 with IODA2) have improved hardware design which allows +to remove this limitation and have multiple IOMMU groups per a VFIO container. 2) The hardware supports so called DMA windows - the PCI address range within which DMA transfer is allowed, any attempt to access address space @@ -439,6 +441,29 @@ The code flow from the example above should be slightly changed: .... +5) There is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/ +VFIO_IOMMU_DISABLE and implements 2 new ioctls: +VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY +(which are unsupported in v1 IOMMU). + +PPC64 paravirtualized guests generate a lot of map/unmap requests, +and the handling of those includes pinning/unpinning pages and updating +mm::locked_vm counter to make sure we do not exceed the rlimit. +The v2 IOMMU splits accounting and pinning into separate operations: + +- VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls +receive a user space address and size of the block to be pinned. +Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to +be called with the exact address and size used for registering +the memory block. The userspace is not expected to call these often. +The ranges are stored in a linked list in a VFIO container. + +- VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual +IOMMU table and do not do pinning; instead these check that the userspace +address is from pre-registered range. + +This separation helps in optimizing DMA for guests. + ------------------------------------------------------------------------------- [1] VFIO was originally an acronym for "Virtual Function I/O" in its diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h index 9d3749287689..f9957eb4c659 100644 --- a/arch/powerpc/include/asm/iommu.h +++ b/arch/powerpc/include/asm/iommu.h @@ -112,9 +112,15 @@ struct iommu_table { unsigned long *it_map; /* A simple allocation bitmap for now */ unsigned long it_page_shift;/* table iommu page size */ struct list_head it_group_list;/* List of iommu_table_group_link */ + unsigned long *it_userspace; /* userspace view of the table */ struct iommu_table_ops *it_ops; }; +#define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \ + ((tbl)->it_userspace ? \ + &((tbl)->it_userspace[(entry) - (tbl)->it_offset]) : \ + NULL) + /* Pure 2^n version of get_order */ static inline __attribute_const__ int get_iommu_order(unsigned long size, struct iommu_table *tbl) diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c b/drivers/vfio/vfio_iommu_spapr_tce.c index 203caacf2242..91a32239bd0a 100644 --- a/drivers/vfio/vfio_iommu_spapr_tce.c +++ b/drivers/vfio/vfio_iommu_spapr_tce.c @@ -19,8 +19,10 @@ #include #include #include +#include #include #include +#include #define DRIVER_VERSION "0.1" #define DRIVER_AUTHOR "aik@ozlabs.ru" @@ -81,6 +83,11 @@ static void decrement_locked_vm(long npages) * into DMA'ble space using the IOMMU */ +struct tce_iommu_group { + struct list_head next; + struct iommu_group *grp; +}; + /* * The container descriptor supports only a single group per container. * Required by the API as the container is not supplied with the IOMMU group @@ -88,11 +95,84 @@ static void decrement_locked_vm(long npages) */ struct tce_container { struct mutex lock; - struct iommu_group *grp; bool enabled; + bool v2; unsigned long locked_pages; + struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES]; + struct list_head group_list; }; +static long tce_iommu_unregister_pages(struct tce_container *container, + __u64 vaddr, __u64 size) +{ + struct mm_iommu_table_group_mem_t *mem; + + if ((vaddr & ~PAGE_MASK) || (size & ~PAGE_MASK)) + return -EINVAL; + + mem = mm_iommu_find(vaddr, size >> PAGE_SHIFT); + if (!mem) + return -ENOENT; + + return mm_iommu_put(mem); +} + +static long tce_iommu_register_pages(struct tce_container *container, + __u64 vaddr, __u64 size) +{ + long ret = 0; + struct mm_iommu_table_group_mem_t *mem = NULL; + unsigned long entries = size >> PAGE_SHIFT; + + if ((vaddr & ~PAGE_MASK) || (size & ~PAGE_MASK) || + ((vaddr + size) < vaddr)) + return -EINVAL; + + ret = mm_iommu_get(vaddr, entries, &mem); + if (ret) + return ret; + + container->enabled = true; + + return 0; +} + +static long tce_iommu_userspace_view_alloc(struct iommu_table *tbl) +{ + unsigned long cb = _ALIGN_UP(sizeof(tbl->it_userspace[0]) * + tbl->it_size, PAGE_SIZE); + unsigned long *uas; + long ret; + + BUG_ON(tbl->it_userspace); + + ret = try_increment_locked_vm(cb >> PAGE_SHIFT); + if (ret) + return ret; + + uas = vzalloc(cb); + if (!uas) { + decrement_locked_vm(cb >> PAGE_SHIFT); + return -ENOMEM; + } + tbl->it_userspace = uas; + + return 0; +} + +static void tce_iommu_userspace_view_free(struct iommu_table *tbl) +{ + unsigned long cb = _ALIGN_UP(sizeof(tbl->it_userspace[0]) * + tbl->it_size, PAGE_SIZE); + + if (!tbl->it_userspace) + return; + + vfree(tbl->it_userspace); + tbl->it_userspace = NULL; + decrement_locked_vm(cb >> PAGE_SHIFT); +} + static bool tce_page_is_contained(struct page *page, unsigned page_shift) { /* @@ -103,18 +183,18 @@ static bool tce_page_is_contained(struct page *page, unsigned page_shift) return (PAGE_SHIFT + compound_order(compound_head(page))) >= page_shift; } +static inline bool tce_groups_attached(struct tce_container *container) +{ + return !list_empty(&container->group_list); +} + static long tce_iommu_find_table(struct tce_container *container, phys_addr_t ioba, struct iommu_table **ptbl) { long i; - struct iommu_table_group *table_group; - - table_group = iommu_group_get_iommudata(container->grp); - if (!table_group) - return -1; for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { - struct iommu_table *tbl = table_group->tables[i]; + struct iommu_table *tbl = container->tables[i]; if (tbl) { unsigned long entry = ioba >> tbl->it_page_shift; @@ -136,9 +216,7 @@ static int tce_iommu_enable(struct tce_container *container) int ret = 0; unsigned long locked; struct iommu_table_group *table_group; - - if (!container->grp) - return -ENXIO; + struct tce_iommu_group *tcegrp; if (!current->mm) return -ESRCH; /* process exited */ @@ -175,7 +253,12 @@ static int tce_iommu_enable(struct tce_container *container) * as there is no way to know how much we should increment * the locked_vm counter. */ - table_group = iommu_group_get_iommudata(container->grp); + if (!tce_groups_attached(container)) + return -ENODEV; + + tcegrp = list_first_entry(&container->group_list, + struct tce_iommu_group, next); + table_group = iommu_group_get_iommudata(tcegrp->grp); if (!table_group) return -ENODEV; @@ -211,7 +294,7 @@ static void *tce_iommu_open(unsigned long arg) { struct tce_container *container; - if (arg != VFIO_SPAPR_TCE_IOMMU) { + if ((arg != VFIO_SPAPR_TCE_IOMMU) && (arg != VFIO_SPAPR_TCE_v2_IOMMU)) { pr_err("tce_vfio: Wrong IOMMU type\n"); return ERR_PTR(-EINVAL); } @@ -221,18 +304,45 @@ static void *tce_iommu_open(unsigned long arg) return ERR_PTR(-ENOMEM); mutex_init(&container->lock); + INIT_LIST_HEAD_RCU(&container->group_list); + + container->v2 = arg == VFIO_SPAPR_TCE_v2_IOMMU; return container; } +static int tce_iommu_clear(struct tce_container *container, + struct iommu_table *tbl, + unsigned long entry, unsigned long pages); +static void tce_iommu_free_table(struct iommu_table *tbl); + static void tce_iommu_release(void *iommu_data) { struct tce_container *container = iommu_data; + struct iommu_table_group *table_group; + struct tce_iommu_group *tcegrp; + long i; - WARN_ON(container->grp); + while (tce_groups_attached(container)) { + tcegrp = list_first_entry(&container->group_list, + struct tce_iommu_group, next); + table_group = iommu_group_get_iommudata(tcegrp->grp); + tce_iommu_detach_group(iommu_data, tcegrp->grp); + } - if (container->grp) - tce_iommu_detach_group(iommu_data, container->grp); + /* + * If VFIO created a table, it was not disposed + * by tce_iommu_detach_group() so do it now. + */ + for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { + struct iommu_table *tbl = container->tables[i]; + + if (!tbl) + continue; + + tce_iommu_clear(container, tbl, tbl->it_offset, tbl->it_size); + tce_iommu_free_table(tbl); + } tce_iommu_disable(container); mutex_destroy(&container->lock); @@ -249,6 +359,47 @@ static void tce_iommu_unuse_page(struct tce_container *container, put_page(page); } +static int tce_iommu_prereg_ua_to_hpa(unsigned long tce, unsigned long size, + unsigned long *phpa, struct mm_iommu_table_group_mem_t **pmem) +{ + long ret = 0; + struct mm_iommu_table_group_mem_t *mem; + + mem = mm_iommu_lookup(tce, size); + if (!mem) + return -EINVAL; + + ret = mm_iommu_ua_to_hpa(mem, tce, phpa); + if (ret) + return -EINVAL; + + *pmem = mem; + + return 0; +} + +static void tce_iommu_unuse_page_v2(struct iommu_table *tbl, + unsigned long entry) +{ + struct mm_iommu_table_group_mem_t *mem = NULL; + int ret; + unsigned long hpa = 0; + unsigned long *pua = IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry); + + if (!pua || !current || !current->mm) + return; + + ret = tce_iommu_prereg_ua_to_hpa(*pua, IOMMU_PAGE_SIZE(tbl), + &hpa, &mem); + if (ret) + pr_debug("%s: tce %lx at #%lx was not cached, ret=%d\n", + __func__, *pua, entry, ret); + if (mem) + mm_iommu_mapped_dec(mem); + + *pua = 0; +} + static int tce_iommu_clear(struct tce_container *container, struct iommu_table *tbl, unsigned long entry, unsigned long pages) @@ -267,6 +418,11 @@ static int tce_iommu_clear(struct tce_container *container, if (direction == DMA_NONE) continue; + if (container->v2) { + tce_iommu_unuse_page_v2(tbl, entry); + continue; + } + tce_iommu_unuse_page(container, oldhpa); } @@ -333,6 +489,64 @@ static long tce_iommu_build(struct tce_container *container, return ret; } +static long tce_iommu_build_v2(struct tce_container *container, + struct iommu_table *tbl, + unsigned long entry, unsigned long tce, unsigned long pages, + enum dma_data_direction direction) +{ + long i, ret = 0; + struct page *page; + unsigned long hpa; + enum dma_data_direction dirtmp; + + for (i = 0; i < pages; ++i) { + struct mm_iommu_table_group_mem_t *mem = NULL; + unsigned long *pua = IOMMU_TABLE_USERSPACE_ENTRY(tbl, + entry + i); + + ret = tce_iommu_prereg_ua_to_hpa(tce, IOMMU_PAGE_SIZE(tbl), + &hpa, &mem); + if (ret) + break; + + page = pfn_to_page(hpa >> PAGE_SHIFT); + if (!tce_page_is_contained(page, tbl->it_page_shift)) { + ret = -EPERM; + break; + } + + /* Preserve offset within IOMMU page */ + hpa |= tce & IOMMU_PAGE_MASK(tbl) & ~PAGE_MASK; + dirtmp = direction; + + /* The registered region is being unregistered */ + if (mm_iommu_mapped_inc(mem)) + break; + + ret = iommu_tce_xchg(tbl, entry + i, &hpa, &dirtmp); + if (ret) { + /* dirtmp cannot be DMA_NONE here */ + tce_iommu_unuse_page_v2(tbl, entry + i); + pr_err("iommu_tce: %s failed ioba=%lx, tce=%lx, ret=%ld\n", + __func__, entry << tbl->it_page_shift, + tce, ret); + break; + } + + if (dirtmp != DMA_NONE) + tce_iommu_unuse_page_v2(tbl, entry + i); + + *pua = tce; + + tce += IOMMU_PAGE_SIZE(tbl); + } + + if (ret) + tce_iommu_clear(container, tbl, entry, i); + + return ret; +} + static long tce_iommu_create_table(struct tce_container *container, struct iommu_table_group *table_group, int num, @@ -358,6 +572,12 @@ static long tce_iommu_create_table(struct tce_container *container, WARN_ON(!ret && !(*ptbl)->it_ops->free); WARN_ON(!ret && ((*ptbl)->it_allocated_size != table_size)); + if (!ret && container->v2) { + ret = tce_iommu_userspace_view_alloc(*ptbl); + if (ret) + (*ptbl)->it_ops->free(*ptbl); + } + if (ret) decrement_locked_vm(table_size >> PAGE_SHIFT); @@ -368,6 +588,7 @@ static void tce_iommu_free_table(struct iommu_table *tbl) { unsigned long pages = tbl->it_allocated_size >> PAGE_SHIFT; + tce_iommu_userspace_view_free(tbl); tbl->it_ops->free(tbl); decrement_locked_vm(pages); } @@ -383,6 +604,7 @@ static long tce_iommu_ioctl(void *iommu_data, case VFIO_CHECK_EXTENSION: switch (arg) { case VFIO_SPAPR_TCE_IOMMU: + case VFIO_SPAPR_TCE_v2_IOMMU: ret = 1; break; default: @@ -394,12 +616,15 @@ static long tce_iommu_ioctl(void *iommu_data, case VFIO_IOMMU_SPAPR_TCE_GET_INFO: { struct vfio_iommu_spapr_tce_info info; + struct tce_iommu_group *tcegrp; struct iommu_table_group *table_group; - if (WARN_ON(!container->grp)) + if (!tce_groups_attached(container)) return -ENXIO; - table_group = iommu_group_get_iommudata(container->grp); + tcegrp = list_first_entry(&container->group_list, + struct tce_iommu_group, next); + table_group = iommu_group_get_iommudata(tcegrp->grp); if (!table_group) return -ENXIO; @@ -468,11 +693,18 @@ static long tce_iommu_ioctl(void *iommu_data, if (ret) return ret; - ret = tce_iommu_build(container, tbl, - param.iova >> tbl->it_page_shift, - param.vaddr, - param.size >> tbl->it_page_shift, - direction); + if (container->v2) + ret = tce_iommu_build_v2(container, tbl, + param.iova >> tbl->it_page_shift, + param.vaddr, + param.size >> tbl->it_page_shift, + direction); + else + ret = tce_iommu_build(container, tbl, + param.iova >> tbl->it_page_shift, + param.vaddr, + param.size >> tbl->it_page_shift, + direction); iommu_flush_tce(tbl); @@ -518,7 +750,62 @@ static long tce_iommu_ioctl(void *iommu_data, return ret; } + case VFIO_IOMMU_SPAPR_REGISTER_MEMORY: { + struct vfio_iommu_spapr_register_memory param; + + if (!container->v2) + break; + + minsz = offsetofend(struct vfio_iommu_spapr_register_memory, + size); + + if (copy_from_user(¶m, (void __user *)arg, minsz)) + return -EFAULT; + + if (param.argsz < minsz) + return -EINVAL; + + /* No flag is supported now */ + if (param.flags) + return -EINVAL; + + mutex_lock(&container->lock); + ret = tce_iommu_register_pages(container, param.vaddr, + param.size); + mutex_unlock(&container->lock); + + return ret; + } + case VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY: { + struct vfio_iommu_spapr_register_memory param; + + if (!container->v2) + break; + + minsz = offsetofend(struct vfio_iommu_spapr_register_memory, + size); + + if (copy_from_user(¶m, (void __user *)arg, minsz)) + return -EFAULT; + + if (param.argsz < minsz) + return -EINVAL; + + /* No flag is supported now */ + if (param.flags) + return -EINVAL; + + mutex_lock(&container->lock); + ret = tce_iommu_unregister_pages(container, param.vaddr, + param.size); + mutex_unlock(&container->lock); + + return ret; + } case VFIO_IOMMU_ENABLE: + if (container->v2) + break; + mutex_lock(&container->lock); ret = tce_iommu_enable(container); mutex_unlock(&container->lock); @@ -526,16 +813,27 @@ static long tce_iommu_ioctl(void *iommu_data, case VFIO_IOMMU_DISABLE: + if (container->v2) + break; + mutex_lock(&container->lock); tce_iommu_disable(container); mutex_unlock(&container->lock); return 0; - case VFIO_EEH_PE_OP: - if (!container->grp) - return -ENODEV; - return vfio_spapr_iommu_eeh_ioctl(container->grp, - cmd, arg); + case VFIO_EEH_PE_OP: { + struct tce_iommu_group *tcegrp; + + ret = 0; + list_for_each_entry(tcegrp, &container->group_list, next) { + ret = vfio_spapr_iommu_eeh_ioctl(tcegrp->grp, + cmd, arg); + if (ret) + return ret; + } + return ret; + } + } return -ENOTTY; @@ -547,14 +845,17 @@ static void tce_iommu_release_ownership(struct tce_container *container, int i; for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { - struct iommu_table *tbl = table_group->tables[i]; + struct iommu_table *tbl = container->tables[i]; if (!tbl) continue; tce_iommu_clear(container, tbl, tbl->it_offset, tbl->it_size); + tce_iommu_userspace_view_free(tbl); if (tbl->it_map) iommu_release_ownership(tbl); + + container->tables[i] = NULL; } } @@ -569,7 +870,10 @@ static int tce_iommu_take_ownership(struct tce_container *container, if (!tbl || !tbl->it_map) continue; - rc = iommu_take_ownership(tbl); + rc = tce_iommu_userspace_view_alloc(tbl); + if (!rc) + rc = iommu_take_ownership(tbl); + if (rc) { for (j = 0; j < i; ++j) iommu_release_ownership( @@ -579,6 +883,9 @@ static int tce_iommu_take_ownership(struct tce_container *container, } } + for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) + container->tables[i] = table_group->tables[i]; + return 0; } @@ -592,18 +899,8 @@ static void tce_iommu_release_ownership_ddw(struct tce_container *container, return; } - for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { - /* Store table pointer as unset_window resets it */ - struct iommu_table *tbl = table_group->tables[i]; - - if (!tbl) - continue; - + for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) table_group->ops->unset_window(table_group, i); - tce_iommu_clear(container, tbl, - tbl->it_offset, tbl->it_size); - tce_iommu_free_table(tbl); - } table_group->ops->release_ownership(table_group); } @@ -611,7 +908,7 @@ static void tce_iommu_release_ownership_ddw(struct tce_container *container, static long tce_iommu_take_ownership_ddw(struct tce_container *container, struct iommu_table_group *table_group) { - long ret; + long i, ret = 0; struct iommu_table *tbl = NULL; if (!table_group->ops->create_table || !table_group->ops->set_window || @@ -622,23 +919,45 @@ static long tce_iommu_take_ownership_ddw(struct tce_container *container, table_group->ops->take_ownership(table_group); - ret = tce_iommu_create_table(container, - table_group, - 0, /* window number */ - IOMMU_PAGE_SHIFT_4K, - table_group->tce32_size, - 1, /* default levels */ - &tbl); - if (!ret) { - ret = table_group->ops->set_window(table_group, 0, tbl); + /* + * If it the first group attached, check if there is + * a default DMA window and create one if none as + * the userspace expects it to exist. + */ + if (!tce_groups_attached(container) && !container->tables[0]) { + ret = tce_iommu_create_table(container, + table_group, + 0, /* window number */ + IOMMU_PAGE_SHIFT_4K, + table_group->tce32_size, + 1, /* default levels */ + &tbl); if (ret) - tce_iommu_free_table(tbl); + goto release_exit; else - table_group->tables[0] = tbl; + container->tables[0] = tbl; } - if (ret) - table_group->ops->release_ownership(table_group); + /* Set all windows to the new group */ + for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { + tbl = container->tables[i]; + + if (!tbl) + continue; + + /* Set the default window to a new group */ + ret = table_group->ops->set_window(table_group, i, tbl); + if (ret) + goto release_exit; + } + + return 0; + +release_exit: + for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) + table_group->ops->unset_window(table_group, i); + + table_group->ops->release_ownership(table_group); return ret; } @@ -649,29 +968,44 @@ static int tce_iommu_attach_group(void *iommu_data, int ret; struct tce_container *container = iommu_data; struct iommu_table_group *table_group; + struct tce_iommu_group *tcegrp = NULL; mutex_lock(&container->lock); /* pr_debug("tce_vfio: Attaching group #%u to iommu %p\n", iommu_group_id(iommu_group), iommu_group); */ - if (container->grp) { - pr_warn("tce_vfio: Only one group per IOMMU container is allowed, existing id=%d, attaching id=%d\n", - iommu_group_id(container->grp), - iommu_group_id(iommu_group)); + table_group = iommu_group_get_iommudata(iommu_group); + + if (tce_groups_attached(container) && (!table_group->ops || + !table_group->ops->take_ownership || + !table_group->ops->release_ownership)) { ret = -EBUSY; goto unlock_exit; } - if (container->enabled) { - pr_err("tce_vfio: attaching group #%u to enabled container\n", - iommu_group_id(iommu_group)); - ret = -EBUSY; - goto unlock_exit; + /* Check if new group has the same iommu_ops (i.e. compatible) */ + list_for_each_entry(tcegrp, &container->group_list, next) { + struct iommu_table_group *table_group_tmp; + + if (tcegrp->grp == iommu_group) { + pr_warn("tce_vfio: Group %d is already attached\n", + iommu_group_id(iommu_group)); + ret = -EBUSY; + goto unlock_exit; + } + table_group_tmp = iommu_group_get_iommudata(tcegrp->grp); + if (table_group_tmp->ops != table_group->ops) { + pr_warn("tce_vfio: Group %d is incompatible with group %d\n", + iommu_group_id(iommu_group), + iommu_group_id(tcegrp->grp)); + ret = -EPERM; + goto unlock_exit; + } } - table_group = iommu_group_get_iommudata(iommu_group); - if (!table_group) { - ret = -ENXIO; + tcegrp = kzalloc(sizeof(*tcegrp), GFP_KERNEL); + if (!tcegrp) { + ret = -ENOMEM; goto unlock_exit; } @@ -681,10 +1015,15 @@ static int tce_iommu_attach_group(void *iommu_data, else ret = tce_iommu_take_ownership_ddw(container, table_group); - if (!ret) - container->grp = iommu_group; + if (!ret) { + tcegrp->grp = iommu_group; + list_add(&tcegrp->next, &container->group_list); + } unlock_exit: + if (ret && tcegrp) + kfree(tcegrp); + mutex_unlock(&container->lock); return ret; @@ -695,24 +1034,26 @@ static void tce_iommu_detach_group(void *iommu_data, { struct tce_container *container = iommu_data; struct iommu_table_group *table_group; + bool found = false; + struct tce_iommu_group *tcegrp; mutex_lock(&container->lock); - if (iommu_group != container->grp) { - pr_warn("tce_vfio: detaching group #%u, expected group is #%u\n", - iommu_group_id(iommu_group), - iommu_group_id(container->grp)); - goto unlock_exit; + + list_for_each_entry(tcegrp, &container->group_list, next) { + if (tcegrp->grp == iommu_group) { + found = true; + break; + } } - if (container->enabled) { - pr_warn("tce_vfio: detaching group #%u from enabled container, forcing disable\n", - iommu_group_id(container->grp)); - tce_iommu_disable(container); + if (!found) { + pr_warn("tce_vfio: detaching unattached group #%u\n", + iommu_group_id(iommu_group)); + goto unlock_exit; } - /* pr_debug("tce_vfio: detaching group #%u from iommu %p\n", - iommu_group_id(iommu_group), iommu_group); */ - container->grp = NULL; + list_del(&tcegrp->next); + kfree(tcegrp); table_group = iommu_group_get_iommudata(iommu_group); BUG_ON(!table_group); diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index e4fa1995f613..fa84391a0d00 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -36,6 +36,8 @@ /* Two-stage IOMMU */ #define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */ +#define VFIO_SPAPR_TCE_v2_IOMMU 7 + /* * The IOCTL interface is designed for extensibility by embedding the * structure length (argsz) and flags into structures passed between @@ -507,6 +509,31 @@ struct vfio_eeh_pe_op { #define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) +/** + * VFIO_IOMMU_SPAPR_REGISTER_MEMORY - _IOW(VFIO_TYPE, VFIO_BASE + 17, struct vfio_iommu_spapr_register_memory) + * + * Registers user space memory where DMA is allowed. It pins + * user pages and does the locked memory accounting so + * subsequent VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA calls + * get faster. + */ +struct vfio_iommu_spapr_register_memory { + __u32 argsz; + __u32 flags; + __u64 vaddr; /* Process virtual address */ + __u64 size; /* Size of mapping (bytes) */ +}; +#define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17) + +/** + * VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY - _IOW(VFIO_TYPE, VFIO_BASE + 18, struct vfio_iommu_spapr_register_memory) + * + * Unregisters user space memory registered with + * VFIO_IOMMU_SPAPR_REGISTER_MEMORY. + * Uses vfio_iommu_spapr_register_memory for parameters. + */ +#define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18) + /* ***************************************************************** */ #endif /* _UAPIVFIO_H */ -- cgit v1.2.3 From e633bc86a922468a82300eef5b9802e17be5e23d Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Fri, 5 Jun 2015 16:35:26 +1000 Subject: vfio: powerpc/spapr: Support Dynamic DMA windows This adds create/remove window ioctls to create and remove DMA windows. sPAPR defines a Dynamic DMA windows capability which allows para-virtualized guests to create additional DMA windows on a PCI bus. The existing linux kernels use this new window to map the entire guest memory and switch to the direct DMA operations saving time on map/unmap requests which would normally happen in a big amounts. This adds 2 ioctl handlers - VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE - to create and remove windows. Up to 2 windows are supported now by the hardware and by this driver. This changes VFIO_IOMMU_SPAPR_TCE_GET_INFO handler to return additional information such as a number of supported windows and maximum number levels of TCE tables. DDW is added as a capability, not as a SPAPR TCE IOMMU v2 unique feature as we still want to support v2 on platforms which cannot do DDW for the sake of TCE acceleration in KVM (coming soon). Signed-off-by: Alexey Kardashevskiy [aw: for the vfio related changes] Acked-by: Alex Williamson Reviewed-by: David Gibson Signed-off-by: Michael Ellerman --- Documentation/vfio.txt | 19 ++++ arch/powerpc/include/asm/iommu.h | 2 +- drivers/vfio/vfio_iommu_spapr_tce.c | 196 +++++++++++++++++++++++++++++++++++- include/uapi/linux/vfio.h | 61 ++++++++++- 4 files changed, 273 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/vfio.txt b/Documentation/vfio.txt index dcc37e109c68..1dd3fddfd3a1 100644 --- a/Documentation/vfio.txt +++ b/Documentation/vfio.txt @@ -464,6 +464,25 @@ address is from pre-registered range. This separation helps in optimizing DMA for guests. +6) sPAPR specification allows guests to have an additional DMA window(s) on +a PCI bus with a variable page size. Two ioctls have been added to support +this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE. +The platform has to support the functionality or error will be returned to +the userspace. The existing hardware supports up to 2 DMA windows, one is +2GB long, uses 4K pages and called "default 32bit window"; the other can +be as big as entire RAM, use different page size, it is optional - guests +create those in run-time if the guest driver supports 64bit DMA. + +VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and +a number of TCE table levels (if a TCE table is going to be big enough and +the kernel may not be able to allocate enough of physically contiguous memory). +It creates a new window in the available slot and returns the bus address where +the new window starts. Due to hardware limitation, the user space cannot choose +the location of DMA windows. + +VFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window +and removes it. + ------------------------------------------------------------------------------- [1] VFIO was originally an acronym for "Virtual Function I/O" in its diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h index f9957eb4c659..ca18cff90900 100644 --- a/arch/powerpc/include/asm/iommu.h +++ b/arch/powerpc/include/asm/iommu.h @@ -149,7 +149,7 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name); */ extern struct iommu_table *iommu_init_table(struct iommu_table * tbl, int nid); -#define IOMMU_TABLE_GROUP_MAX_TABLES 1 +#define IOMMU_TABLE_GROUP_MAX_TABLES 2 struct iommu_table_group; diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c b/drivers/vfio/vfio_iommu_spapr_tce.c index 91a32239bd0a..0582b72ef377 100644 --- a/drivers/vfio/vfio_iommu_spapr_tce.c +++ b/drivers/vfio/vfio_iommu_spapr_tce.c @@ -211,6 +211,18 @@ static long tce_iommu_find_table(struct tce_container *container, return -1; } +static int tce_iommu_find_free_table(struct tce_container *container) +{ + int i; + + for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { + if (!container->tables[i]) + return i; + } + + return -ENOSPC; +} + static int tce_iommu_enable(struct tce_container *container) { int ret = 0; @@ -593,11 +605,115 @@ static void tce_iommu_free_table(struct iommu_table *tbl) decrement_locked_vm(pages); } +static long tce_iommu_create_window(struct tce_container *container, + __u32 page_shift, __u64 window_size, __u32 levels, + __u64 *start_addr) +{ + struct tce_iommu_group *tcegrp; + struct iommu_table_group *table_group; + struct iommu_table *tbl = NULL; + long ret, num; + + num = tce_iommu_find_free_table(container); + if (num < 0) + return num; + + /* Get the first group for ops::create_table */ + tcegrp = list_first_entry(&container->group_list, + struct tce_iommu_group, next); + table_group = iommu_group_get_iommudata(tcegrp->grp); + if (!table_group) + return -EFAULT; + + if (!(table_group->pgsizes & (1ULL << page_shift))) + return -EINVAL; + + if (!table_group->ops->set_window || !table_group->ops->unset_window || + !table_group->ops->get_table_size || + !table_group->ops->create_table) + return -EPERM; + + /* Create TCE table */ + ret = tce_iommu_create_table(container, table_group, num, + page_shift, window_size, levels, &tbl); + if (ret) + return ret; + + BUG_ON(!tbl->it_ops->free); + + /* + * Program the table to every group. + * Groups have been tested for compatibility at the attach time. + */ + list_for_each_entry(tcegrp, &container->group_list, next) { + table_group = iommu_group_get_iommudata(tcegrp->grp); + + ret = table_group->ops->set_window(table_group, num, tbl); + if (ret) + goto unset_exit; + } + + container->tables[num] = tbl; + + /* Return start address assigned by platform in create_table() */ + *start_addr = tbl->it_offset << tbl->it_page_shift; + + return 0; + +unset_exit: + list_for_each_entry(tcegrp, &container->group_list, next) { + table_group = iommu_group_get_iommudata(tcegrp->grp); + table_group->ops->unset_window(table_group, num); + } + tce_iommu_free_table(tbl); + + return ret; +} + +static long tce_iommu_remove_window(struct tce_container *container, + __u64 start_addr) +{ + struct iommu_table_group *table_group = NULL; + struct iommu_table *tbl; + struct tce_iommu_group *tcegrp; + int num; + + num = tce_iommu_find_table(container, start_addr, &tbl); + if (num < 0) + return -EINVAL; + + BUG_ON(!tbl->it_size); + + /* Detach groups from IOMMUs */ + list_for_each_entry(tcegrp, &container->group_list, next) { + table_group = iommu_group_get_iommudata(tcegrp->grp); + + /* + * SPAPR TCE IOMMU exposes the default DMA window to + * the guest via dma32_window_start/size of + * VFIO_IOMMU_SPAPR_TCE_GET_INFO. Some platforms allow + * the userspace to remove this window, some do not so + * here we check for the platform capability. + */ + if (!table_group->ops || !table_group->ops->unset_window) + return -EPERM; + + table_group->ops->unset_window(table_group, num); + } + + /* Free table */ + tce_iommu_clear(container, tbl, tbl->it_offset, tbl->it_size); + tce_iommu_free_table(tbl); + container->tables[num] = NULL; + + return 0; +} + static long tce_iommu_ioctl(void *iommu_data, unsigned int cmd, unsigned long arg) { struct tce_container *container = iommu_data; - unsigned long minsz; + unsigned long minsz, ddwsz; long ret; switch (cmd) { @@ -641,6 +757,21 @@ static long tce_iommu_ioctl(void *iommu_data, info.dma32_window_start = table_group->tce32_start; info.dma32_window_size = table_group->tce32_size; info.flags = 0; + memset(&info.ddw, 0, sizeof(info.ddw)); + + if (table_group->max_dynamic_windows_supported && + container->v2) { + info.flags |= VFIO_IOMMU_SPAPR_INFO_DDW; + info.ddw.pgsizes = table_group->pgsizes; + info.ddw.max_dynamic_windows_supported = + table_group->max_dynamic_windows_supported; + info.ddw.levels = table_group->max_levels; + } + + ddwsz = offsetofend(struct vfio_iommu_spapr_tce_info, ddw); + + if (info.argsz >= ddwsz) + minsz = ddwsz; if (copy_to_user((void __user *)arg, &info, minsz)) return -EFAULT; @@ -834,6 +965,69 @@ static long tce_iommu_ioctl(void *iommu_data, return ret; } + case VFIO_IOMMU_SPAPR_TCE_CREATE: { + struct vfio_iommu_spapr_tce_create create; + + if (!container->v2) + break; + + if (!tce_groups_attached(container)) + return -ENXIO; + + minsz = offsetofend(struct vfio_iommu_spapr_tce_create, + start_addr); + + if (copy_from_user(&create, (void __user *)arg, minsz)) + return -EFAULT; + + if (create.argsz < minsz) + return -EINVAL; + + if (create.flags) + return -EINVAL; + + mutex_lock(&container->lock); + + ret = tce_iommu_create_window(container, create.page_shift, + create.window_size, create.levels, + &create.start_addr); + + mutex_unlock(&container->lock); + + if (!ret && copy_to_user((void __user *)arg, &create, minsz)) + ret = -EFAULT; + + return ret; + } + case VFIO_IOMMU_SPAPR_TCE_REMOVE: { + struct vfio_iommu_spapr_tce_remove remove; + + if (!container->v2) + break; + + if (!tce_groups_attached(container)) + return -ENXIO; + + minsz = offsetofend(struct vfio_iommu_spapr_tce_remove, + start_addr); + + if (copy_from_user(&remove, (void __user *)arg, minsz)) + return -EFAULT; + + if (remove.argsz < minsz) + return -EINVAL; + + if (remove.flags) + return -EINVAL; + + mutex_lock(&container->lock); + + ret = tce_iommu_remove_window(container, remove.start_addr); + + mutex_unlock(&container->lock); + + return ret; + } } return -ENOTTY; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index fa84391a0d00..9fd7b5d8df2f 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -444,6 +444,23 @@ struct vfio_iommu_type1_dma_unmap { /* -------- Additional API for SPAPR TCE (Server POWERPC) IOMMU -------- */ +/* + * The SPAPR TCE DDW info struct provides the information about + * the details of Dynamic DMA window capability. + * + * @pgsizes contains a page size bitmask, 4K/64K/16M are supported. + * @max_dynamic_windows_supported tells the maximum number of windows + * which the platform can create. + * @levels tells the maximum number of levels in multi-level IOMMU tables; + * this allows splitting a table into smaller chunks which reduces + * the amount of physically contiguous memory required for the table. + */ +struct vfio_iommu_spapr_tce_ddw_info { + __u64 pgsizes; /* Bitmap of supported page sizes */ + __u32 max_dynamic_windows_supported; + __u32 levels; +}; + /* * The SPAPR TCE info struct provides the information about the PCI bus * address ranges available for DMA, these values are programmed into @@ -454,14 +471,17 @@ struct vfio_iommu_type1_dma_unmap { * addresses too so the window works as a filter rather than an offset * for IOVA addresses. * - * A flag will need to be added if other page sizes are supported, - * so as defined here, it is always 4k. + * Flags supported: + * - VFIO_IOMMU_SPAPR_INFO_DDW: informs the userspace that dynamic DMA windows + * (DDW) support is present. @ddw is only supported when DDW is present. */ struct vfio_iommu_spapr_tce_info { __u32 argsz; - __u32 flags; /* reserved for future use */ + __u32 flags; +#define VFIO_IOMMU_SPAPR_INFO_DDW (1 << 0) /* DDW supported */ __u32 dma32_window_start; /* 32 bit window start (bytes) */ __u32 dma32_window_size; /* 32 bit window size (bytes) */ + struct vfio_iommu_spapr_tce_ddw_info ddw; }; #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) @@ -534,6 +554,41 @@ struct vfio_iommu_spapr_register_memory { */ #define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18) +/** + * VFIO_IOMMU_SPAPR_TCE_CREATE - _IOWR(VFIO_TYPE, VFIO_BASE + 19, struct vfio_iommu_spapr_tce_create) + * + * Creates an additional TCE table and programs it (sets a new DMA window) + * to every IOMMU group in the container. It receives page shift, window + * size and number of levels in the TCE table being created. + * + * It allocates and returns an offset on a PCI bus of the new DMA window. + */ +struct vfio_iommu_spapr_tce_create { + __u32 argsz; + __u32 flags; + /* in */ + __u32 page_shift; + __u64 window_size; + __u32 levels; + /* out */ + __u64 start_addr; +}; +#define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19) + +/** + * VFIO_IOMMU_SPAPR_TCE_REMOVE - _IOW(VFIO_TYPE, VFIO_BASE + 20, struct vfio_iommu_spapr_tce_remove) + * + * Unprograms a TCE table from all groups in the container and destroys it. + * It receives a PCI bus offset as a window id. + */ +struct vfio_iommu_spapr_tce_remove { + __u32 argsz; + __u32 flags; + /* in */ + __u64 start_addr; +}; +#define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20) + /* ***************************************************************** */ #endif /* _UAPIVFIO_H */ -- cgit v1.2.3 From c156633f1353264634135dea86ffcae74f2122fc Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 11 Jun 2015 01:01:43 +0300 Subject: Renesas Ethernet AVB driver proper Ethernet AVB includes an Gigabit Ethernet controller (E-MAC) that is basically compatible with SuperH Gigabit Ethernet E-MAC. Ethernet AVB has a dedicated direct memory access controller (AVB-DMAC) that is a new design compared to the SuperH E-DMAC. The AVB-DMAC is compliant with 3 standards formulated for IEEE 802.1BA: IEEE 802.1AS timing and synchronization protocol, IEEE 802.1Qav real- time transfer, and the IEEE 802.1Qat stream reservation protocol. The driver only supports device tree probing, so the binding document is included in this patch. Based on the original patches by Mitsuhiro Kimura. Signed-off-by: Mitsuhiro Kimura Signed-off-by: Sergei Shtylyov Signed-off-by: David S. Miller --- .../devicetree/bindings/net/renesas,ravb.txt | 48 + drivers/net/ethernet/renesas/Kconfig | 31 + drivers/net/ethernet/renesas/Makefile | 1 + drivers/net/ethernet/renesas/ravb.c | 1801 ++++++++++++++++++++ drivers/net/ethernet/renesas/ravb.h | 806 +++++++++ 5 files changed, 2687 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/renesas,ravb.txt create mode 100644 drivers/net/ethernet/renesas/ravb.c create mode 100644 drivers/net/ethernet/renesas/ravb.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt new file mode 100644 index 000000000000..1fd8831437bf --- /dev/null +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -0,0 +1,48 @@ +* Renesas Electronics Ethernet AVB + +This file provides information on what the device node for the Ethernet AVB +interface contains. + +Required properties: +- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC. + "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC. +- reg: offset and length of (1) the register block and (2) the stream buffer. +- interrupts: interrupt specifier for the sole interrupt. +- phy-mode: see ethernet.txt file in the same directory. +- phy-handle: see ethernet.txt file in the same directory. +- #address-cells: number of address cells for the MDIO bus, must be equal to 1. +- #size-cells: number of size cells on the MDIO bus, must be equal to 0. +- clocks: clock phandle and specifier pair. +- pinctrl-0: phandle, referring to a default pin configuration node. + +Optional properties: +- interrupt-parent: the phandle for the interrupt controller that services + interrupts for this device. +- pinctrl-names: pin configuration state name ("default"). +- renesas,no-ether-link: boolean, specify when a board does not provide a proper + AVB_LINK signal. +- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is + active-low instead of normal active-high. + +Example: + + ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupt-parent = <&gic>; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig index 196e98a2d93b..8e8031a1c6c7 100644 --- a/drivers/net/ethernet/renesas/Kconfig +++ b/drivers/net/ethernet/renesas/Kconfig @@ -2,6 +2,21 @@ # Renesas device configuration # +config NET_VENDOR_RENESAS + bool "Renesas devices" + default y + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from + . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Renesas devices. If you say Y, you will be asked + for your specific device in the following questions. + +if NET_VENDOR_RENESAS + config SH_ETH tristate "Renesas SuperH Ethernet support" depends on HAS_DMA @@ -15,3 +30,19 @@ config SH_ETH This driver supporting CPUs are: - SH7619, SH7710, SH7712, SH7724, SH7734, SH7763, SH7757, R8A7740, R8A777x and R8A779x. + +config RAVB + tristate "Renesas Ethernet AVB support" + depends on HAS_DMA + depends on ARCH_SHMOBILE || COMPILE_TEST + select CRC32 + select MII + select MDIO_BITBANG + select PHYLIB + select PTP_1588_CLOCK + help + Renesas Ethernet AVB device driver. + This driver supports the following SoCs: + - R8A779x. + +endif # NET_VENDOR_RENESAS diff --git a/drivers/net/ethernet/renesas/Makefile b/drivers/net/ethernet/renesas/Makefile index 1c278a8e066a..aa354a666fac 100644 --- a/drivers/net/ethernet/renesas/Makefile +++ b/drivers/net/ethernet/renesas/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_SH_ETH) += sh_eth.o +obj-$(CONFIG_RAVB) += ravb.o diff --git a/drivers/net/ethernet/renesas/ravb.c b/drivers/net/ethernet/renesas/ravb.c new file mode 100644 index 000000000000..1fa9be203790 --- /dev/null +++ b/drivers/net/ethernet/renesas/ravb.c @@ -0,0 +1,1801 @@ +/* Renesas Ethernet AVB device driver + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + * Copyright (C) 2015 Renesas Solutions Corp. + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * Based on the SuperH Ethernet driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License version 2, + * as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ravb.h" + +#define RAVB_DEF_MSG_ENABLE \ + (NETIF_MSG_LINK | \ + NETIF_MSG_TIMER | \ + NETIF_MSG_RX_ERR | \ + NETIF_MSG_TX_ERR) + +static int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, + u32 value) +{ + int i; + + for (i = 0; i < 10000; i++) { + if ((ravb_read(ndev, reg) & mask) == value) + return 0; + udelay(10); + } + return -ETIMEDOUT; +} + +static int ravb_config(struct net_device *ndev) +{ + int error; + + /* Set config mode */ + ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, + CCC); + /* Check if the operating mode is changed to the config mode */ + error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); + if (error) + netdev_err(ndev, "failed to switch device to config mode\n"); + + return error; +} + +static void ravb_set_duplex(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + u32 ecmr = ravb_read(ndev, ECMR); + + if (priv->duplex) /* Full */ + ecmr |= ECMR_DM; + else /* Half */ + ecmr &= ~ECMR_DM; + ravb_write(ndev, ecmr, ECMR); +} + +static void ravb_set_rate(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + + switch (priv->speed) { + case 100: /* 100BASE */ + ravb_write(ndev, GECMR_SPEED_100, GECMR); + break; + case 1000: /* 1000BASE */ + ravb_write(ndev, GECMR_SPEED_1000, GECMR); + break; + default: + break; + } +} + +static void ravb_set_buffer_align(struct sk_buff *skb) +{ + u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); + + if (reserve) + skb_reserve(skb, RAVB_ALIGN - reserve); +} + +/* Get MAC address from the MAC address registers + * + * Ethernet AVB device doesn't have ROM for MAC address. + * This function gets the MAC address that was used by a bootloader. + */ +static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) +{ + if (mac) { + ether_addr_copy(ndev->dev_addr, mac); + } else { + ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24); + ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF; + ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF; + ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF; + ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF; + ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF; + } +} + +static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) +{ + struct ravb_private *priv = container_of(ctrl, struct ravb_private, + mdiobb); + u32 pir = ravb_read(priv->ndev, PIR); + + if (set) + pir |= mask; + else + pir &= ~mask; + ravb_write(priv->ndev, pir, PIR); +} + +/* MDC pin control */ +static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) +{ + ravb_mdio_ctrl(ctrl, PIR_MDC, level); +} + +/* Data I/O pin control */ +static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) +{ + ravb_mdio_ctrl(ctrl, PIR_MMD, output); +} + +/* Set data bit */ +static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) +{ + ravb_mdio_ctrl(ctrl, PIR_MDO, value); +} + +/* Get data bit */ +static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) +{ + struct ravb_private *priv = container_of(ctrl, struct ravb_private, + mdiobb); + + return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; +} + +/* MDIO bus control struct */ +static struct mdiobb_ops bb_ops = { + .owner = THIS_MODULE, + .set_mdc = ravb_set_mdc, + .set_mdio_dir = ravb_set_mdio_dir, + .set_mdio_data = ravb_set_mdio_data, + .get_mdio_data = ravb_get_mdio_data, +}; + +/* Free skb's and DMA buffers for Ethernet AVB */ +static void ravb_ring_free(struct net_device *ndev, int q) +{ + struct ravb_private *priv = netdev_priv(ndev); + int ring_size; + int i; + + /* Free RX skb ringbuffer */ + if (priv->rx_skb[q]) { + for (i = 0; i < priv->num_rx_ring[q]; i++) + dev_kfree_skb(priv->rx_skb[q][i]); + } + kfree(priv->rx_skb[q]); + priv->rx_skb[q] = NULL; + + /* Free TX skb ringbuffer */ + if (priv->tx_skb[q]) { + for (i = 0; i < priv->num_tx_ring[q]; i++) + dev_kfree_skb(priv->tx_skb[q][i]); + } + kfree(priv->tx_skb[q]); + priv->tx_skb[q] = NULL; + + /* Free aligned TX buffers */ + if (priv->tx_buffers[q]) { + for (i = 0; i < priv->num_tx_ring[q]; i++) + kfree(priv->tx_buffers[q][i]); + } + kfree(priv->tx_buffers[q]); + priv->tx_buffers[q] = NULL; + + if (priv->rx_ring[q]) { + ring_size = sizeof(struct ravb_ex_rx_desc) * + (priv->num_rx_ring[q] + 1); + dma_free_coherent(NULL, ring_size, priv->rx_ring[q], + priv->rx_desc_dma[q]); + priv->rx_ring[q] = NULL; + } + + if (priv->tx_ring[q]) { + ring_size = sizeof(struct ravb_tx_desc) * + (priv->num_tx_ring[q] + 1); + dma_free_coherent(NULL, ring_size, priv->tx_ring[q], + priv->tx_desc_dma[q]); + priv->tx_ring[q] = NULL; + } +} + +/* Format skb and descriptor buffer for Ethernet AVB */ +static void ravb_ring_format(struct net_device *ndev, int q) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct ravb_ex_rx_desc *rx_desc = NULL; + struct ravb_tx_desc *tx_desc = NULL; + struct ravb_desc *desc = NULL; + int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; + int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q]; + struct sk_buff *skb; + dma_addr_t dma_addr; + void *buffer; + int i; + + priv->cur_rx[q] = 0; + priv->cur_tx[q] = 0; + priv->dirty_rx[q] = 0; + priv->dirty_tx[q] = 0; + + memset(priv->rx_ring[q], 0, rx_ring_size); + /* Build RX ring buffer */ + for (i = 0; i < priv->num_rx_ring[q]; i++) { + priv->rx_skb[q][i] = NULL; + skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); + if (!skb) + break; + ravb_set_buffer_align(skb); + /* RX descriptor */ + rx_desc = &priv->rx_ring[q][i]; + /* The size of the buffer should be on 16-byte boundary. */ + rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); + dma_addr = dma_map_single(&ndev->dev, skb->data, + ALIGN(PKT_BUF_SZ, 16), + DMA_FROM_DEVICE); + if (dma_mapping_error(&ndev->dev, dma_addr)) { + dev_kfree_skb(skb); + break; + } + priv->rx_skb[q][i] = skb; + rx_desc->dptr = cpu_to_le32(dma_addr); + rx_desc->die_dt = DT_FEMPTY; + } + rx_desc = &priv->rx_ring[q][i]; + rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); + rx_desc->die_dt = DT_LINKFIX; /* type */ + priv->dirty_rx[q] = (u32)(i - priv->num_rx_ring[q]); + + memset(priv->tx_ring[q], 0, tx_ring_size); + /* Build TX ring buffer */ + for (i = 0; i < priv->num_tx_ring[q]; i++) { + priv->tx_skb[q][i] = NULL; + priv->tx_buffers[q][i] = NULL; + buffer = kmalloc(PKT_BUF_SZ + RAVB_ALIGN - 1, GFP_KERNEL); + if (!buffer) + break; + /* Aligned TX buffer */ + priv->tx_buffers[q][i] = buffer; + tx_desc = &priv->tx_ring[q][i]; + tx_desc->die_dt = DT_EEMPTY; + } + tx_desc = &priv->tx_ring[q][i]; + tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); + tx_desc->die_dt = DT_LINKFIX; /* type */ + + /* RX descriptor base address for best effort */ + desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; + desc->die_dt = DT_LINKFIX; /* type */ + desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); + + /* TX descriptor base address for best effort */ + desc = &priv->desc_bat[q]; + desc->die_dt = DT_LINKFIX; /* type */ + desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); +} + +/* Init skb and descriptor buffer for Ethernet AVB */ +static int ravb_ring_init(struct net_device *ndev, int q) +{ + struct ravb_private *priv = netdev_priv(ndev); + int ring_size; + + /* Allocate RX and TX skb rings */ + priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], + sizeof(*priv->rx_skb[q]), GFP_KERNEL); + priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], + sizeof(*priv->tx_skb[q]), GFP_KERNEL); + if (!priv->rx_skb[q] || !priv->tx_skb[q]) + goto error; + + /* Allocate rings for the aligned buffers */ + priv->tx_buffers[q] = kcalloc(priv->num_tx_ring[q], + sizeof(*priv->tx_buffers[q]), GFP_KERNEL); + if (!priv->tx_buffers[q]) + goto error; + + /* Allocate all RX descriptors. */ + ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); + priv->rx_ring[q] = dma_alloc_coherent(NULL, ring_size, + &priv->rx_desc_dma[q], + GFP_KERNEL); + if (!priv->rx_ring[q]) + goto error; + + priv->dirty_rx[q] = 0; + + /* Allocate all TX descriptors. */ + ring_size = sizeof(struct ravb_tx_desc) * (priv->num_tx_ring[q] + 1); + priv->tx_ring[q] = dma_alloc_coherent(NULL, ring_size, + &priv->tx_desc_dma[q], + GFP_KERNEL); + if (!priv->tx_ring[q]) + goto error; + + return 0; + +error: + ravb_ring_free(ndev, q); + + return -ENOMEM; +} + +/* E-MAC init function */ +static void ravb_emac_init(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + u32 ecmr; + + /* Receive frame limit set register */ + ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); + + /* PAUSE prohibition */ + ecmr = ravb_read(ndev, ECMR); + ecmr &= ECMR_DM; + ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; + ravb_write(ndev, ecmr, ECMR); + + ravb_set_rate(ndev); + + /* Set MAC address */ + ravb_write(ndev, + (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | + (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); + ravb_write(ndev, + (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); + + ravb_write(ndev, 1, MPR); + + /* E-MAC status register clear */ + ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); + + /* E-MAC interrupt enable register */ + ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); +} + +/* Device init function for Ethernet AVB */ +static int ravb_dmac_init(struct net_device *ndev) +{ + int error; + + /* Set CONFIG mode */ + error = ravb_config(ndev); + if (error) + return error; + + error = ravb_ring_init(ndev, RAVB_BE); + if (error) + return error; + error = ravb_ring_init(ndev, RAVB_NC); + if (error) { + ravb_ring_free(ndev, RAVB_BE); + return error; + } + + /* Descriptor format */ + ravb_ring_format(ndev, RAVB_BE); + ravb_ring_format(ndev, RAVB_NC); + +#if defined(__LITTLE_ENDIAN) + ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC); +#else + ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC); +#endif + + /* Set AVB RX */ + ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR); + + /* Set FIFO size */ + ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); + + /* Timestamp enable */ + ravb_write(ndev, TCCR_TFEN, TCCR); + + /* Interrupt enable: */ + /* Frame receive */ + ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); + /* Receive FIFO full warning */ + ravb_write(ndev, RIC1_RFWE, RIC1); + /* Receive FIFO full error, descriptor empty */ + ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); + /* Frame transmitted, timestamp FIFO updated */ + ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); + + /* Setting the control will start the AVB-DMAC process. */ + ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION, + CCC); + + return 0; +} + +/* Free TX skb function for AVB-IP */ +static int ravb_tx_free(struct net_device *ndev, int q) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct net_device_stats *stats = &priv->stats[q]; + struct ravb_tx_desc *desc; + int free_num = 0; + int entry = 0; + u32 size; + + for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { + entry = priv->dirty_tx[q] % priv->num_tx_ring[q]; + desc = &priv->tx_ring[q][entry]; + if (desc->die_dt != DT_FEMPTY) + break; + /* Descriptor type must be checked before all other reads */ + dma_rmb(); + size = le16_to_cpu(desc->ds_tagl) & TX_DS; + /* Free the original skb. */ + if (priv->tx_skb[q][entry]) { + dma_unmap_single(&ndev->dev, le32_to_cpu(desc->dptr), + size, DMA_TO_DEVICE); + dev_kfree_skb_any(priv->tx_skb[q][entry]); + priv->tx_skb[q][entry] = NULL; + free_num++; + } + stats->tx_packets++; + stats->tx_bytes += size; + desc->die_dt = DT_EEMPTY; + } + return free_num; +} + +static void ravb_get_tx_tstamp(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct ravb_tstamp_skb *ts_skb, *ts_skb2; + struct skb_shared_hwtstamps shhwtstamps; + struct sk_buff *skb; + struct timespec64 ts; + u16 tag, tfa_tag; + int count; + u32 tfa2; + + count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; + while (count--) { + tfa2 = ravb_read(ndev, TFA2); + tfa_tag = (tfa2 & TFA2_TST) >> 16; + ts.tv_nsec = (u64)ravb_read(ndev, TFA0); + ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | + ravb_read(ndev, TFA1); + memset(&shhwtstamps, 0, sizeof(shhwtstamps)); + shhwtstamps.hwtstamp = timespec64_to_ktime(ts); + list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, + list) { + skb = ts_skb->skb; + tag = ts_skb->tag; + list_del(&ts_skb->list); + kfree(ts_skb); + if (tag == tfa_tag) { + skb_tstamp_tx(skb, &shhwtstamps); + break; + } + } + ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR); + } +} + +/* Packet receive function for Ethernet AVB */ +static bool ravb_rx(struct net_device *ndev, int *quota, int q) +{ + struct ravb_private *priv = netdev_priv(ndev); + int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; + int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - + priv->cur_rx[q]; + struct net_device_stats *stats = &priv->stats[q]; + struct ravb_ex_rx_desc *desc; + struct sk_buff *skb; + dma_addr_t dma_addr; + struct timespec64 ts; + u16 pkt_len = 0; + u8 desc_status; + int limit; + + boguscnt = min(boguscnt, *quota); + limit = boguscnt; + desc = &priv->rx_ring[q][entry]; + while (desc->die_dt != DT_FEMPTY) { + /* Descriptor type must be checked before all other reads */ + dma_rmb(); + desc_status = desc->msc; + pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; + + if (--boguscnt < 0) + break; + + if (desc_status & MSC_MC) + stats->multicast++; + + if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | + MSC_CEEF)) { + stats->rx_errors++; + if (desc_status & MSC_CRC) + stats->rx_crc_errors++; + if (desc_status & MSC_RFE) + stats->rx_frame_errors++; + if (desc_status & (MSC_RTLF | MSC_RTSF)) + stats->rx_length_errors++; + if (desc_status & MSC_CEEF) + stats->rx_missed_errors++; + } else { + u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; + + skb = priv->rx_skb[q][entry]; + priv->rx_skb[q][entry] = NULL; + dma_sync_single_for_cpu(&ndev->dev, + le32_to_cpu(desc->dptr), + ALIGN(PKT_BUF_SZ, 16), + DMA_FROM_DEVICE); + get_ts &= (q == RAVB_NC) ? + RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : + ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; + if (get_ts) { + struct skb_shared_hwtstamps *shhwtstamps; + + shhwtstamps = skb_hwtstamps(skb); + memset(shhwtstamps, 0, sizeof(*shhwtstamps)); + ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << + 32) | le32_to_cpu(desc->ts_sl); + ts.tv_nsec = le32_to_cpu(desc->ts_n); + shhwtstamps->hwtstamp = timespec64_to_ktime(ts); + } + skb_put(skb, pkt_len); + skb->protocol = eth_type_trans(skb, ndev); + napi_gro_receive(&priv->napi[q], skb); + stats->rx_packets++; + stats->rx_bytes += pkt_len; + } + + entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; + desc = &priv->rx_ring[q][entry]; + } + + /* Refill the RX ring buffers. */ + for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { + entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; + desc = &priv->rx_ring[q][entry]; + /* The size of the buffer should be on 16-byte boundary. */ + desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); + + if (!priv->rx_skb[q][entry]) { + skb = netdev_alloc_skb(ndev, + PKT_BUF_SZ + RAVB_ALIGN - 1); + if (!skb) + break; /* Better luck next round. */ + ravb_set_buffer_align(skb); + dma_unmap_single(&ndev->dev, le32_to_cpu(desc->dptr), + ALIGN(PKT_BUF_SZ, 16), + DMA_FROM_DEVICE); + dma_addr = dma_map_single(&ndev->dev, skb->data, + le16_to_cpu(desc->ds_cc), + DMA_FROM_DEVICE); + skb_checksum_none_assert(skb); + if (dma_mapping_error(&ndev->dev, dma_addr)) { + dev_kfree_skb_any(skb); + break; + } + desc->dptr = cpu_to_le32(dma_addr); + priv->rx_skb[q][entry] = skb; + } + /* Descriptor type must be set after all the above writes */ + dma_wmb(); + desc->die_dt = DT_FEMPTY; + } + + *quota -= limit - (++boguscnt); + + return boguscnt <= 0; +} + +static void ravb_rcv_snd_disable(struct net_device *ndev) +{ + /* Disable TX and RX */ + ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR); +} + +static void ravb_rcv_snd_enable(struct net_device *ndev) +{ + /* Enable TX and RX */ + ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR); +} + +/* function for waiting dma process finished */ +static int ravb_stop_dma(struct net_device *ndev) +{ + int error; + + /* Wait for stopping the hardware TX process */ + error = ravb_wait(ndev, TCCR, + TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); + if (error) + return error; + + error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, + 0); + if (error) + return error; + + /* Stop the E-MAC's RX/TX processes. */ + ravb_rcv_snd_disable(ndev); + + /* Wait for stopping the RX DMA process */ + error = ravb_wait(ndev, CSR, CSR_RPO, 0); + if (error) + return error; + + /* Stop AVB-DMAC process */ + return ravb_config(ndev); +} + +/* E-MAC interrupt handler */ +static void ravb_emac_interrupt(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + u32 ecsr, psr; + + ecsr = ravb_read(ndev, ECSR); + ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ + if (ecsr & ECSR_ICD) + ndev->stats.tx_carrier_errors++; + if (ecsr & ECSR_LCHNG) { + /* Link changed */ + if (priv->no_avb_link) + return; + psr = ravb_read(ndev, PSR); + if (priv->avb_link_active_low) + psr ^= PSR_LMON; + if (!(psr & PSR_LMON)) { + /* DIsable RX and TX */ + ravb_rcv_snd_disable(ndev); + } else { + /* Enable RX and TX */ + ravb_rcv_snd_enable(ndev); + } + } +} + +/* Error interrupt handler */ +static void ravb_error_interrupt(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + u32 eis, ris2; + + eis = ravb_read(ndev, EIS); + ravb_write(ndev, ~EIS_QFS, EIS); + if (eis & EIS_QFS) { + ris2 = ravb_read(ndev, RIS2); + ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); + + /* Receive Descriptor Empty int */ + if (ris2 & RIS2_QFF0) + priv->stats[RAVB_BE].rx_over_errors++; + + /* Receive Descriptor Empty int */ + if (ris2 & RIS2_QFF1) + priv->stats[RAVB_NC].rx_over_errors++; + + /* Receive FIFO Overflow int */ + if (ris2 & RIS2_RFFF) + priv->rx_fifo_errors++; + } +} + +static irqreturn_t ravb_interrupt(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct ravb_private *priv = netdev_priv(ndev); + irqreturn_t result = IRQ_NONE; + u32 iss; + + spin_lock(&priv->lock); + /* Get interrupt status */ + iss = ravb_read(ndev, ISS); + + /* Received and transmitted interrupts */ + if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { + u32 ris0 = ravb_read(ndev, RIS0); + u32 ric0 = ravb_read(ndev, RIC0); + u32 tis = ravb_read(ndev, TIS); + u32 tic = ravb_read(ndev, TIC); + int q; + + /* Timestamp updated */ + if (tis & TIS_TFUF) { + ravb_write(ndev, ~TIS_TFUF, TIS); + ravb_get_tx_tstamp(ndev); + result = IRQ_HANDLED; + } + + /* Network control and best effort queue RX/TX */ + for (q = RAVB_NC; q >= RAVB_BE; q--) { + if (((ris0 & ric0) & BIT(q)) || + ((tis & tic) & BIT(q))) { + if (napi_schedule_prep(&priv->napi[q])) { + /* Mask RX and TX interrupts */ + ravb_write(ndev, ric0 & ~BIT(q), RIC0); + ravb_write(ndev, tic & ~BIT(q), TIC); + __napi_schedule(&priv->napi[q]); + } else { + netdev_warn(ndev, + "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", + ris0, ric0); + netdev_warn(ndev, + " tx status 0x%08x, tx mask 0x%08x.\n", + tis, tic); + } + result = IRQ_HANDLED; + } + } + } + + /* E-MAC status summary */ + if (iss & ISS_MS) { + ravb_emac_interrupt(ndev); + result = IRQ_HANDLED; + } + + /* Error status summary */ + if (iss & ISS_ES) { + ravb_error_interrupt(ndev); + result = IRQ_HANDLED; + } + + mmiowb(); + spin_unlock(&priv->lock); + return result; +} + +static int ravb_poll(struct napi_struct *napi, int budget) +{ + struct net_device *ndev = napi->dev; + struct ravb_private *priv = netdev_priv(ndev); + unsigned long flags; + int q = napi - priv->napi; + int mask = BIT(q); + int quota = budget; + u32 ris0, tis; + + for (;;) { + tis = ravb_read(ndev, TIS); + ris0 = ravb_read(ndev, RIS0); + if (!((ris0 & mask) || (tis & mask))) + break; + + /* Processing RX Descriptor Ring */ + if (ris0 & mask) { + /* Clear RX interrupt */ + ravb_write(ndev, ~mask, RIS0); + if (ravb_rx(ndev, "a, q)) + goto out; + } + /* Processing TX Descriptor Ring */ + if (tis & mask) { + spin_lock_irqsave(&priv->lock, flags); + /* Clear TX interrupt */ + ravb_write(ndev, ~mask, TIS); + ravb_tx_free(ndev, q); + netif_wake_subqueue(ndev, q); + mmiowb(); + spin_unlock_irqrestore(&priv->lock, flags); + } + } + + napi_complete(napi); + + /* Re-enable RX/TX interrupts */ + spin_lock_irqsave(&priv->lock, flags); + ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0); + ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC); + mmiowb(); + spin_unlock_irqrestore(&priv->lock, flags); + + /* Receive error message handling */ + priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; + priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; + if (priv->rx_over_errors != ndev->stats.rx_over_errors) { + ndev->stats.rx_over_errors = priv->rx_over_errors; + netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); + } + if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { + ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; + netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); + } +out: + return budget - quota; +} + +/* PHY state control function */ +static void ravb_adjust_link(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->phydev; + bool new_state = false; + + if (phydev->link) { + if (phydev->duplex != priv->duplex) { + new_state = true; + priv->duplex = phydev->duplex; + ravb_set_duplex(ndev); + } + + if (phydev->speed != priv->speed) { + new_state = true; + priv->speed = phydev->speed; + ravb_set_rate(ndev); + } + if (!priv->link) { + ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF, + ECMR); + new_state = true; + priv->link = phydev->link; + if (priv->no_avb_link) + ravb_rcv_snd_enable(ndev); + } + } else if (priv->link) { + new_state = true; + priv->link = 0; + priv->speed = 0; + priv->duplex = -1; + if (priv->no_avb_link) + ravb_rcv_snd_disable(ndev); + } + + if (new_state && netif_msg_link(priv)) + phy_print_status(phydev); +} + +/* PHY init function */ +static int ravb_phy_init(struct net_device *ndev) +{ + struct device_node *np = ndev->dev.parent->of_node; + struct ravb_private *priv = netdev_priv(ndev); + struct phy_device *phydev; + struct device_node *pn; + + priv->link = 0; + priv->speed = 0; + priv->duplex = -1; + + /* Try connecting to PHY */ + pn = of_parse_phandle(np, "phy-handle", 0); + phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, + priv->phy_interface); + if (!phydev) { + netdev_err(ndev, "failed to connect PHY\n"); + return -ENOENT; + } + + netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n", + phydev->addr, phydev->irq, phydev->drv->name); + + priv->phydev = phydev; + + return 0; +} + +/* PHY control start function */ +static int ravb_phy_start(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + int error; + + error = ravb_phy_init(ndev); + if (error) + return error; + + phy_start(priv->phydev); + + return 0; +} + +static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) +{ + struct ravb_private *priv = netdev_priv(ndev); + int error = -ENODEV; + unsigned long flags; + + if (priv->phydev) { + spin_lock_irqsave(&priv->lock, flags); + error = phy_ethtool_gset(priv->phydev, ecmd); + spin_unlock_irqrestore(&priv->lock, flags); + } + + return error; +} + +static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) +{ + struct ravb_private *priv = netdev_priv(ndev); + unsigned long flags; + int error; + + if (!priv->phydev) + return -ENODEV; + + spin_lock_irqsave(&priv->lock, flags); + + /* Disable TX and RX */ + ravb_rcv_snd_disable(ndev); + + error = phy_ethtool_sset(priv->phydev, ecmd); + if (error) + goto error_exit; + + if (ecmd->duplex == DUPLEX_FULL) + priv->duplex = 1; + else + priv->duplex = 0; + + ravb_set_duplex(ndev); + +error_exit: + mdelay(1); + + /* Enable TX and RX */ + ravb_rcv_snd_enable(ndev); + + mmiowb(); + spin_unlock_irqrestore(&priv->lock, flags); + + return error; +} + +static int ravb_nway_reset(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + int error = -ENODEV; + unsigned long flags; + + if (priv->phydev) { + spin_lock_irqsave(&priv->lock, flags); + error = phy_start_aneg(priv->phydev); + spin_unlock_irqrestore(&priv->lock, flags); + } + + return error; +} + +static u32 ravb_get_msglevel(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + + return priv->msg_enable; +} + +static void ravb_set_msglevel(struct net_device *ndev, u32 value) +{ + struct ravb_private *priv = netdev_priv(ndev); + + priv->msg_enable = value; +} + +static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { + "rx_queue_0_current", + "tx_queue_0_current", + "rx_queue_0_dirty", + "tx_queue_0_dirty", + "rx_queue_0_packets", + "tx_queue_0_packets", + "rx_queue_0_bytes", + "tx_queue_0_bytes", + "rx_queue_0_mcast_packets", + "rx_queue_0_errors", + "rx_queue_0_crc_errors", + "rx_queue_0_frame_errors", + "rx_queue_0_length_errors", + "rx_queue_0_missed_errors", + "rx_queue_0_over_errors", + + "rx_queue_1_current", + "tx_queue_1_current", + "rx_queue_1_dirty", + "tx_queue_1_dirty", + "rx_queue_1_packets", + "tx_queue_1_packets", + "rx_queue_1_bytes", + "tx_queue_1_bytes", + "rx_queue_1_mcast_packets", + "rx_queue_1_errors", + "rx_queue_1_crc_errors", + "rx_queue_1_frame_errors_", + "rx_queue_1_length_errors", + "rx_queue_1_missed_errors", + "rx_queue_1_over_errors", +}; + +#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) + +static int ravb_get_sset_count(struct net_device *netdev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return RAVB_STATS_LEN; + default: + return -EOPNOTSUPP; + } +} + +static void ravb_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + struct ravb_private *priv = netdev_priv(ndev); + int i = 0; + int q; + + /* Device-specific stats */ + for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { + struct net_device_stats *stats = &priv->stats[q]; + + data[i++] = priv->cur_rx[q]; + data[i++] = priv->cur_tx[q]; + data[i++] = priv->dirty_rx[q]; + data[i++] = priv->dirty_tx[q]; + data[i++] = stats->rx_packets; + data[i++] = stats->tx_packets; + data[i++] = stats->rx_bytes; + data[i++] = stats->tx_bytes; + data[i++] = stats->multicast; + data[i++] = stats->rx_errors; + data[i++] = stats->rx_crc_errors; + data[i++] = stats->rx_frame_errors; + data[i++] = stats->rx_length_errors; + data[i++] = stats->rx_missed_errors; + data[i++] = stats->rx_over_errors; + } +} + +static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) +{ + switch (stringset) { + case ETH_SS_STATS: + memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); + break; + } +} + +static void ravb_get_ringparam(struct net_device *ndev, + struct ethtool_ringparam *ring) +{ + struct ravb_private *priv = netdev_priv(ndev); + + ring->rx_max_pending = BE_RX_RING_MAX; + ring->tx_max_pending = BE_TX_RING_MAX; + ring->rx_pending = priv->num_rx_ring[RAVB_BE]; + ring->tx_pending = priv->num_tx_ring[RAVB_BE]; +} + +static int ravb_set_ringparam(struct net_device *ndev, + struct ethtool_ringparam *ring) +{ + struct ravb_private *priv = netdev_priv(ndev); + int error; + + if (ring->tx_pending > BE_TX_RING_MAX || + ring->rx_pending > BE_RX_RING_MAX || + ring->tx_pending < BE_TX_RING_MIN || + ring->rx_pending < BE_RX_RING_MIN) + return -EINVAL; + if (ring->rx_mini_pending || ring->rx_jumbo_pending) + return -EINVAL; + + if (netif_running(ndev)) { + netif_device_detach(ndev); + /* Wait for DMA stopping */ + error = ravb_stop_dma(ndev); + if (error) { + netdev_err(ndev, + "cannot set ringparam! Any AVB processes are still running?\n"); + return error; + } + synchronize_irq(ndev->irq); + + /* Free all the skb's in the RX queue and the DMA buffers. */ + ravb_ring_free(ndev, RAVB_BE); + ravb_ring_free(ndev, RAVB_NC); + } + + /* Set new parameters */ + priv->num_rx_ring[RAVB_BE] = ring->rx_pending; + priv->num_tx_ring[RAVB_BE] = ring->tx_pending; + + if (netif_running(ndev)) { + error = ravb_dmac_init(ndev); + if (error) { + netdev_err(ndev, + "%s: ravb_dmac_init() failed, error %d\n", + __func__, error); + return error; + } + + ravb_emac_init(ndev); + + netif_device_attach(ndev); + } + + return 0; +} + +static int ravb_get_ts_info(struct net_device *ndev, + struct ethtool_ts_info *info) +{ + info->so_timestamping = + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE | + SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); + info->rx_filters = + (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | + (1 << HWTSTAMP_FILTER_ALL); + info->phc_index = -1; + + return 0; +} + +static const struct ethtool_ops ravb_ethtool_ops = { + .get_settings = ravb_get_settings, + .set_settings = ravb_set_settings, + .nway_reset = ravb_nway_reset, + .get_msglevel = ravb_get_msglevel, + .set_msglevel = ravb_set_msglevel, + .get_link = ethtool_op_get_link, + .get_strings = ravb_get_strings, + .get_ethtool_stats = ravb_get_ethtool_stats, + .get_sset_count = ravb_get_sset_count, + .get_ringparam = ravb_get_ringparam, + .set_ringparam = ravb_set_ringparam, + .get_ts_info = ravb_get_ts_info, +}; + +/* Network device open function for Ethernet AVB */ +static int ravb_open(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + int error; + + napi_enable(&priv->napi[RAVB_BE]); + napi_enable(&priv->napi[RAVB_NC]); + + error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name, + ndev); + if (error) { + netdev_err(ndev, "cannot request IRQ\n"); + goto out_napi_off; + } + + /* Device init */ + error = ravb_dmac_init(ndev); + if (error) + goto out_free_irq; + ravb_emac_init(ndev); + + netif_tx_start_all_queues(ndev); + + /* PHY control start */ + error = ravb_phy_start(ndev); + if (error) + goto out_free_irq; + + return 0; + +out_free_irq: + free_irq(ndev->irq, ndev); +out_napi_off: + napi_disable(&priv->napi[RAVB_NC]); + napi_disable(&priv->napi[RAVB_BE]); + return error; +} + +/* Timeout function for Ethernet AVB */ +static void ravb_tx_timeout(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + + netif_err(priv, tx_err, ndev, + "transmit timed out, status %08x, resetting...\n", + ravb_read(ndev, ISS)); + + /* tx_errors count up */ + ndev->stats.tx_errors++; + + schedule_work(&priv->work); +} + +static void ravb_tx_timeout_work(struct work_struct *work) +{ + struct ravb_private *priv = container_of(work, struct ravb_private, + work); + struct net_device *ndev = priv->ndev; + + netif_tx_stop_all_queues(ndev); + + /* Wait for DMA stopping */ + ravb_stop_dma(ndev); + + ravb_ring_free(ndev, RAVB_BE); + ravb_ring_free(ndev, RAVB_NC); + + /* Device init */ + ravb_dmac_init(ndev); + ravb_emac_init(ndev); + + netif_tx_start_all_queues(ndev); +} + +/* Packet transmit function for Ethernet AVB */ +static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct ravb_tstamp_skb *ts_skb = NULL; + u16 q = skb_get_queue_mapping(skb); + struct ravb_tx_desc *desc; + unsigned long flags; + u32 dma_addr; + void *buffer; + u32 entry; + u32 tccr; + + spin_lock_irqsave(&priv->lock, flags); + if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q]) { + netif_err(priv, tx_queued, ndev, + "still transmitting with the full ring!\n"); + netif_stop_subqueue(ndev, q); + spin_unlock_irqrestore(&priv->lock, flags); + return NETDEV_TX_BUSY; + } + entry = priv->cur_tx[q] % priv->num_tx_ring[q]; + priv->tx_skb[q][entry] = skb; + + if (skb_put_padto(skb, ETH_ZLEN)) + goto drop; + + buffer = PTR_ALIGN(priv->tx_buffers[q][entry], RAVB_ALIGN); + memcpy(buffer, skb->data, skb->len); + desc = &priv->tx_ring[q][entry]; + desc->ds_tagl = cpu_to_le16(skb->len); + dma_addr = dma_map_single(&ndev->dev, buffer, skb->len, DMA_TO_DEVICE); + if (dma_mapping_error(&ndev->dev, dma_addr)) + goto drop; + desc->dptr = cpu_to_le32(dma_addr); + + /* TX timestamp required */ + if (q == RAVB_NC) { + ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); + if (!ts_skb) { + dma_unmap_single(&ndev->dev, dma_addr, skb->len, + DMA_TO_DEVICE); + goto drop; + } + ts_skb->skb = skb; + ts_skb->tag = priv->ts_skb_tag++; + priv->ts_skb_tag &= 0x3ff; + list_add_tail(&ts_skb->list, &priv->ts_skb_list); + + /* TAG and timestamp required flag */ + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + skb_tx_timestamp(skb); + desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; + desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); + } + + /* Descriptor type must be set after all the above writes */ + dma_wmb(); + desc->die_dt = DT_FSINGLE; + + tccr = ravb_read(ndev, TCCR); + if (!(tccr & (TCCR_TSRQ0 << q))) + ravb_write(ndev, tccr | (TCCR_TSRQ0 << q), TCCR); + + priv->cur_tx[q]++; + if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q] && + !ravb_tx_free(ndev, q)) + netif_stop_subqueue(ndev, q); + +exit: + mmiowb(); + spin_unlock_irqrestore(&priv->lock, flags); + return NETDEV_TX_OK; + +drop: + dev_kfree_skb_any(skb); + priv->tx_skb[q][entry] = NULL; + goto exit; +} + +static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, + void *accel_priv, select_queue_fallback_t fallback) +{ + /* If skb needs TX timestamp, it is handled in network control queue */ + return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : + RAVB_BE; + +} + +static struct net_device_stats *ravb_get_stats(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct net_device_stats *nstats, *stats0, *stats1; + + nstats = &ndev->stats; + stats0 = &priv->stats[RAVB_BE]; + stats1 = &priv->stats[RAVB_NC]; + + nstats->tx_dropped += ravb_read(ndev, TROCR); + ravb_write(ndev, 0, TROCR); /* (write clear) */ + nstats->collisions += ravb_read(ndev, CDCR); + ravb_write(ndev, 0, CDCR); /* (write clear) */ + nstats->tx_carrier_errors += ravb_read(ndev, LCCR); + ravb_write(ndev, 0, LCCR); /* (write clear) */ + + nstats->tx_carrier_errors += ravb_read(ndev, CERCR); + ravb_write(ndev, 0, CERCR); /* (write clear) */ + nstats->tx_carrier_errors += ravb_read(ndev, CEECR); + ravb_write(ndev, 0, CEECR); /* (write clear) */ + + nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; + nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; + nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; + nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; + nstats->multicast = stats0->multicast + stats1->multicast; + nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; + nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; + nstats->rx_frame_errors = + stats0->rx_frame_errors + stats1->rx_frame_errors; + nstats->rx_length_errors = + stats0->rx_length_errors + stats1->rx_length_errors; + nstats->rx_missed_errors = + stats0->rx_missed_errors + stats1->rx_missed_errors; + nstats->rx_over_errors = + stats0->rx_over_errors + stats1->rx_over_errors; + + return nstats; +} + +/* Update promiscuous bit */ +static void ravb_set_rx_mode(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + unsigned long flags; + u32 ecmr; + + spin_lock_irqsave(&priv->lock, flags); + ecmr = ravb_read(ndev, ECMR); + if (ndev->flags & IFF_PROMISC) + ecmr |= ECMR_PRM; + else + ecmr &= ~ECMR_PRM; + ravb_write(ndev, ecmr, ECMR); + mmiowb(); + spin_unlock_irqrestore(&priv->lock, flags); +} + +/* Device close function for Ethernet AVB */ +static int ravb_close(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct ravb_tstamp_skb *ts_skb, *ts_skb2; + + netif_tx_stop_all_queues(ndev); + + /* Disable interrupts by clearing the interrupt masks. */ + ravb_write(ndev, 0, RIC0); + ravb_write(ndev, 0, RIC1); + ravb_write(ndev, 0, RIC2); + ravb_write(ndev, 0, TIC); + + /* Set the config mode to stop the AVB-DMAC's processes */ + if (ravb_stop_dma(ndev) < 0) + netdev_err(ndev, + "device will be stopped after h/w processes are done.\n"); + + /* Clear the timestamp list */ + list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { + list_del(&ts_skb->list); + kfree(ts_skb); + } + + /* PHY disconnect */ + if (priv->phydev) { + phy_stop(priv->phydev); + phy_disconnect(priv->phydev); + priv->phydev = NULL; + } + + free_irq(ndev->irq, ndev); + + napi_disable(&priv->napi[RAVB_NC]); + napi_disable(&priv->napi[RAVB_BE]); + + /* Free all the skb's in the RX queue and the DMA buffers. */ + ravb_ring_free(ndev, RAVB_BE); + ravb_ring_free(ndev, RAVB_NC); + + return 0; +} + +static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct hwtstamp_config config; + + config.flags = 0; + config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : + HWTSTAMP_TX_OFF; + if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) + config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; + else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) + config.rx_filter = HWTSTAMP_FILTER_ALL; + else + config.rx_filter = HWTSTAMP_FILTER_NONE; + + return copy_to_user(req->ifr_data, &config, sizeof(config)) ? + -EFAULT : 0; +} + +/* Control hardware time stamping */ +static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct hwtstamp_config config; + u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; + u32 tstamp_tx_ctrl; + + if (copy_from_user(&config, req->ifr_data, sizeof(config))) + return -EFAULT; + + /* Reserved for future extensions */ + if (config.flags) + return -EINVAL; + + switch (config.tx_type) { + case HWTSTAMP_TX_OFF: + tstamp_tx_ctrl = 0; + break; + case HWTSTAMP_TX_ON: + tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; + break; + default: + return -ERANGE; + } + + switch (config.rx_filter) { + case HWTSTAMP_FILTER_NONE: + tstamp_rx_ctrl = 0; + break; + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: + tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; + break; + default: + config.rx_filter = HWTSTAMP_FILTER_ALL; + tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; + } + + priv->tstamp_tx_ctrl = tstamp_tx_ctrl; + priv->tstamp_rx_ctrl = tstamp_rx_ctrl; + + return copy_to_user(req->ifr_data, &config, sizeof(config)) ? + -EFAULT : 0; +} + +/* ioctl to device function */ +static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) +{ + struct ravb_private *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->phydev; + + if (!netif_running(ndev)) + return -EINVAL; + + if (!phydev) + return -ENODEV; + + switch (cmd) { + case SIOCGHWTSTAMP: + return ravb_hwtstamp_get(ndev, req); + case SIOCSHWTSTAMP: + return ravb_hwtstamp_set(ndev, req); + } + + return phy_mii_ioctl(phydev, req, cmd); +} + +static const struct net_device_ops ravb_netdev_ops = { + .ndo_open = ravb_open, + .ndo_stop = ravb_close, + .ndo_start_xmit = ravb_start_xmit, + .ndo_select_queue = ravb_select_queue, + .ndo_get_stats = ravb_get_stats, + .ndo_set_rx_mode = ravb_set_rx_mode, + .ndo_tx_timeout = ravb_tx_timeout, + .ndo_do_ioctl = ravb_do_ioctl, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = eth_mac_addr, + .ndo_change_mtu = eth_change_mtu, +}; + +/* MDIO bus init function */ +static int ravb_mdio_init(struct ravb_private *priv) +{ + struct platform_device *pdev = priv->pdev; + struct device *dev = &pdev->dev; + int error; + + /* Bitbang init */ + priv->mdiobb.ops = &bb_ops; + + /* MII controller setting */ + priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); + if (!priv->mii_bus) + return -ENOMEM; + + /* Hook up MII support for ethtool */ + priv->mii_bus->name = "ravb_mii"; + priv->mii_bus->parent = dev; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + pdev->name, pdev->id); + + /* Register MDIO bus */ + error = of_mdiobus_register(priv->mii_bus, dev->of_node); + if (error) + goto out_free_bus; + + return 0; + +out_free_bus: + free_mdio_bitbang(priv->mii_bus); + return error; +} + +/* MDIO bus release function */ +static int ravb_mdio_release(struct ravb_private *priv) +{ + /* Unregister mdio bus */ + mdiobus_unregister(priv->mii_bus); + + /* Free bitbang info */ + free_mdio_bitbang(priv->mii_bus); + + return 0; +} + +static int ravb_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct ravb_private *priv; + struct net_device *ndev; + int error, irq, q; + struct resource *res; + + if (!np) { + dev_err(&pdev->dev, + "this driver is required to be instantiated from device tree\n"); + return -EINVAL; + } + + /* Get base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "invalid resource\n"); + return -EINVAL; + } + + ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), + NUM_TX_QUEUE, NUM_RX_QUEUE); + if (!ndev) + return -ENOMEM; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + /* The Ether-specific entries in the device structure. */ + ndev->base_addr = res->start; + ndev->dma = -1; + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + error = -ENODEV; + goto out_release; + } + ndev->irq = irq; + + SET_NETDEV_DEV(ndev, &pdev->dev); + + priv = netdev_priv(ndev); + priv->ndev = ndev; + priv->pdev = pdev; + priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; + priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; + priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; + priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; + priv->addr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->addr)) { + error = PTR_ERR(priv->addr); + goto out_release; + } + + spin_lock_init(&priv->lock); + INIT_WORK(&priv->work, ravb_tx_timeout_work); + + priv->phy_interface = of_get_phy_mode(np); + + priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); + priv->avb_link_active_low = + of_property_read_bool(np, "renesas,ether-link-active-low"); + + /* Set function */ + ndev->netdev_ops = &ravb_netdev_ops; + ndev->ethtool_ops = &ravb_ethtool_ops; + + /* Set AVB config mode */ + ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, + CCC); + + /* Set CSEL value */ + ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB, + CCC); + + /* Set GTI value */ + ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI); + + /* Request GTI loading */ + ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR); + + /* Allocate descriptor base address table */ + priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; + priv->desc_bat = dma_alloc_coherent(NULL, priv->desc_bat_size, + &priv->desc_bat_dma, GFP_KERNEL); + if (!priv->desc_bat) { + dev_err(&ndev->dev, + "Cannot allocate desc base address table (size %d bytes)\n", + priv->desc_bat_size); + error = -ENOMEM; + goto out_release; + } + for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) + priv->desc_bat[q].die_dt = DT_EOS; + ravb_write(ndev, priv->desc_bat_dma, DBAT); + + /* Initialise HW timestamp list */ + INIT_LIST_HEAD(&priv->ts_skb_list); + + /* Debug message level */ + priv->msg_enable = RAVB_DEF_MSG_ENABLE; + + /* Read and set MAC address */ + ravb_read_mac_address(ndev, of_get_mac_address(np)); + if (!is_valid_ether_addr(ndev->dev_addr)) { + dev_warn(&pdev->dev, + "no valid MAC address supplied, using a random one\n"); + eth_hw_addr_random(ndev); + } + + /* MDIO bus init */ + error = ravb_mdio_init(priv); + if (error) { + dev_err(&ndev->dev, "failed to initialize MDIO\n"); + goto out_dma_free; + } + + netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); + netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); + + /* Network device register */ + error = register_netdev(ndev); + if (error) + goto out_napi_del; + + /* Print device information */ + netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", + (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); + + platform_set_drvdata(pdev, ndev); + + return 0; + +out_napi_del: + netif_napi_del(&priv->napi[RAVB_NC]); + netif_napi_del(&priv->napi[RAVB_BE]); + ravb_mdio_release(priv); +out_dma_free: + dma_free_coherent(NULL, priv->desc_bat_size, priv->desc_bat, + priv->desc_bat_dma); +out_release: + if (ndev) + free_netdev(ndev); + + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + return error; +} + +static int ravb_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct ravb_private *priv = netdev_priv(ndev); + + dma_free_coherent(NULL, priv->desc_bat_size, priv->desc_bat, + priv->desc_bat_dma); + /* Set reset mode */ + ravb_write(ndev, CCC_OPC_RESET, CCC); + pm_runtime_put_sync(&pdev->dev); + unregister_netdev(ndev); + netif_napi_del(&priv->napi[RAVB_NC]); + netif_napi_del(&priv->napi[RAVB_BE]); + ravb_mdio_release(priv); + pm_runtime_disable(&pdev->dev); + free_netdev(ndev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int ravb_runtime_nop(struct device *dev) +{ + /* Runtime PM callback shared between ->runtime_suspend() + * and ->runtime_resume(). Simply returns success. + * + * This driver re-initializes all registers after + * pm_runtime_get_sync() anyway so there is no need + * to save and restore registers here. + */ + return 0; +} + +static const struct dev_pm_ops ravb_dev_pm_ops = { + .runtime_suspend = ravb_runtime_nop, + .runtime_resume = ravb_runtime_nop, +}; + +#define RAVB_PM_OPS (&ravb_dev_pm_ops) +#else +#define RAVB_PM_OPS NULL +#endif + +static const struct of_device_id ravb_match_table[] = { + { .compatible = "renesas,etheravb-r8a7790" }, + { .compatible = "renesas,etheravb-r8a7794" }, + { } +}; +MODULE_DEVICE_TABLE(of, ravb_match_table); + +static struct platform_driver ravb_driver = { + .probe = ravb_probe, + .remove = ravb_remove, + .driver = { + .name = "ravb", + .pm = RAVB_PM_OPS, + .of_match_table = ravb_match_table, + }, +}; + +module_platform_driver(ravb_driver); + +MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); +MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h new file mode 100644 index 000000000000..f2656ebba084 --- /dev/null +++ b/drivers/net/ethernet/renesas/ravb.h @@ -0,0 +1,806 @@ +/* Renesas Ethernet AVB device driver + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + * Copyright (C) 2015 Renesas Solutions Corp. + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * Based on the SuperH Ethernet driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License version 2, + * as published by the Free Software Foundation. + */ + +#ifndef __RAVB_H__ +#define __RAVB_H__ + +#include +#include +#include +#include +#include +#include + +#define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */ +#define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */ +#define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */ +#define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */ +#define BE_TX_RING_MIN 64 +#define BE_RX_RING_MIN 64 +#define BE_TX_RING_MAX 1024 +#define BE_RX_RING_MAX 2048 + +#define PKT_BUF_SZ 1538 + +/* Driver's parameters */ +#define RAVB_ALIGN 128 + +/* Hardware time stamp */ +#define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */ +#define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */ + +#define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */ +#define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */ +#define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002 +#define RAVB_RXTSTAMP_TYPE_ALL 0x00000006 +#define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */ + +enum ravb_reg { + /* AVB-DMAC registers */ + CCC = 0x0000, + DBAT = 0x0004, + DLR = 0x0008, + CSR = 0x000C, + CDAR0 = 0x0010, + CDAR1 = 0x0014, + CDAR2 = 0x0018, + CDAR3 = 0x001C, + CDAR4 = 0x0020, + CDAR5 = 0x0024, + CDAR6 = 0x0028, + CDAR7 = 0x002C, + CDAR8 = 0x0030, + CDAR9 = 0x0034, + CDAR10 = 0x0038, + CDAR11 = 0x003C, + CDAR12 = 0x0040, + CDAR13 = 0x0044, + CDAR14 = 0x0048, + CDAR15 = 0x004C, + CDAR16 = 0x0050, + CDAR17 = 0x0054, + CDAR18 = 0x0058, + CDAR19 = 0x005C, + CDAR20 = 0x0060, + CDAR21 = 0x0064, + ESR = 0x0088, + RCR = 0x0090, + RQC0 = 0x0094, + RQC1 = 0x0098, + RQC2 = 0x009C, + RQC3 = 0x00A0, + RQC4 = 0x00A4, + RPC = 0x00B0, + UFCW = 0x00BC, + UFCS = 0x00C0, + UFCV0 = 0x00C4, + UFCV1 = 0x00C8, + UFCV2 = 0x00CC, + UFCV3 = 0x00D0, + UFCV4 = 0x00D4, + UFCD0 = 0x00E0, + UFCD1 = 0x00E4, + UFCD2 = 0x00E8, + UFCD3 = 0x00EC, + UFCD4 = 0x00F0, + SFO = 0x00FC, + SFP0 = 0x0100, + SFP1 = 0x0104, + SFP2 = 0x0108, + SFP3 = 0x010C, + SFP4 = 0x0110, + SFP5 = 0x0114, + SFP6 = 0x0118, + SFP7 = 0x011C, + SFP8 = 0x0120, + SFP9 = 0x0124, + SFP10 = 0x0128, + SFP11 = 0x012C, + SFP12 = 0x0130, + SFP13 = 0x0134, + SFP14 = 0x0138, + SFP15 = 0x013C, + SFP16 = 0x0140, + SFP17 = 0x0144, + SFP18 = 0x0148, + SFP19 = 0x014C, + SFP20 = 0x0150, + SFP21 = 0x0154, + SFP22 = 0x0158, + SFP23 = 0x015C, + SFP24 = 0x0160, + SFP25 = 0x0164, + SFP26 = 0x0168, + SFP27 = 0x016C, + SFP28 = 0x0170, + SFP29 = 0x0174, + SFP30 = 0x0178, + SFP31 = 0x017C, + SFM0 = 0x01C0, + SFM1 = 0x01C4, + TGC = 0x0300, + TCCR = 0x0304, + TSR = 0x0308, + TFA0 = 0x0310, + TFA1 = 0x0314, + TFA2 = 0x0318, + CIVR0 = 0x0320, + CIVR1 = 0x0324, + CDVR0 = 0x0328, + CDVR1 = 0x032C, + CUL0 = 0x0330, + CUL1 = 0x0334, + CLL0 = 0x0338, + CLL1 = 0x033C, + DIC = 0x0350, + DIS = 0x0354, + EIC = 0x0358, + EIS = 0x035C, + RIC0 = 0x0360, + RIS0 = 0x0364, + RIC1 = 0x0368, + RIS1 = 0x036C, + RIC2 = 0x0370, + RIS2 = 0x0374, + TIC = 0x0378, + TIS = 0x037C, + ISS = 0x0380, + GCCR = 0x0390, + GMTT = 0x0394, + GPTC = 0x0398, + GTI = 0x039C, + GTO0 = 0x03A0, + GTO1 = 0x03A4, + GTO2 = 0x03A8, + GIC = 0x03AC, + GIS = 0x03B0, + GCPT = 0x03B4, /* Undocumented? */ + GCT0 = 0x03B8, + GCT1 = 0x03BC, + GCT2 = 0x03C0, + + /* E-MAC registers */ + ECMR = 0x0500, + RFLR = 0x0508, + ECSR = 0x0510, + ECSIPR = 0x0518, + PIR = 0x0520, + PSR = 0x0528, + PIPR = 0x052c, + MPR = 0x0558, + PFTCR = 0x055c, + PFRCR = 0x0560, + GECMR = 0x05b0, + MAHR = 0x05c0, + MALR = 0x05c8, + TROCR = 0x0700, /* Undocumented? */ + CDCR = 0x0708, /* Undocumented? */ + LCCR = 0x0710, /* Undocumented? */ + CEFCR = 0x0740, + FRECR = 0x0748, + TSFRCR = 0x0750, + TLFRCR = 0x0758, + RFCR = 0x0760, + CERCR = 0x0768, /* Undocumented? */ + CEECR = 0x0770, /* Undocumented? */ + MAFCR = 0x0778, +}; + + +/* Register bits of the Ethernet AVB */ +/* CCC */ +enum CCC_BIT { + CCC_OPC = 0x00000003, + CCC_OPC_RESET = 0x00000000, + CCC_OPC_CONFIG = 0x00000001, + CCC_OPC_OPERATION = 0x00000002, + CCC_DTSR = 0x00000100, + CCC_CSEL = 0x00030000, + CCC_CSEL_HPB = 0x00010000, + CCC_CSEL_ETH_TX = 0x00020000, + CCC_CSEL_GMII_REF = 0x00030000, + CCC_BOC = 0x00100000, /* Undocumented? */ + CCC_LBME = 0x01000000, +}; + +/* CSR */ +enum CSR_BIT { + CSR_OPS = 0x0000000F, + CSR_OPS_RESET = 0x00000001, + CSR_OPS_CONFIG = 0x00000002, + CSR_OPS_OPERATION = 0x00000004, + CSR_OPS_STANDBY = 0x00000008, /* Undocumented? */ + CSR_DTS = 0x00000100, + CSR_TPO0 = 0x00010000, + CSR_TPO1 = 0x00020000, + CSR_TPO2 = 0x00040000, + CSR_TPO3 = 0x00080000, + CSR_RPO = 0x00100000, +}; + +/* ESR */ +enum ESR_BIT { + ESR_EQN = 0x0000001F, + ESR_ET = 0x00000F00, + ESR_EIL = 0x00001000, +}; + +/* RCR */ +enum RCR_BIT { + RCR_EFFS = 0x00000001, + RCR_ENCF = 0x00000002, + RCR_ESF = 0x0000000C, + RCR_ETS0 = 0x00000010, + RCR_ETS2 = 0x00000020, + RCR_RFCL = 0x1FFF0000, +}; + +/* RQC0/1/2/3/4 */ +enum RQC_BIT { + RQC_RSM0 = 0x00000003, + RQC_UFCC0 = 0x00000030, + RQC_RSM1 = 0x00000300, + RQC_UFCC1 = 0x00003000, + RQC_RSM2 = 0x00030000, + RQC_UFCC2 = 0x00300000, + RQC_RSM3 = 0x03000000, + RQC_UFCC3 = 0x30000000, +}; + +/* RPC */ +enum RPC_BIT { + RPC_PCNT = 0x00000700, + RPC_DCNT = 0x00FF0000, +}; + +/* UFCW */ +enum UFCW_BIT { + UFCW_WL0 = 0x0000003F, + UFCW_WL1 = 0x00003F00, + UFCW_WL2 = 0x003F0000, + UFCW_WL3 = 0x3F000000, +}; + +/* UFCS */ +enum UFCS_BIT { + UFCS_SL0 = 0x0000003F, + UFCS_SL1 = 0x00003F00, + UFCS_SL2 = 0x003F0000, + UFCS_SL3 = 0x3F000000, +}; + +/* UFCV0/1/2/3/4 */ +enum UFCV_BIT { + UFCV_CV0 = 0x0000003F, + UFCV_CV1 = 0x00003F00, + UFCV_CV2 = 0x003F0000, + UFCV_CV3 = 0x3F000000, +}; + +/* UFCD0/1/2/3/4 */ +enum UFCD_BIT { + UFCD_DV0 = 0x0000003F, + UFCD_DV1 = 0x00003F00, + UFCD_DV2 = 0x003F0000, + UFCD_DV3 = 0x3F000000, +}; + +/* SFO */ +enum SFO_BIT { + SFO_FPB = 0x0000003F, +}; + +/* RTC */ +enum RTC_BIT { + RTC_MFL0 = 0x00000FFF, + RTC_MFL1 = 0x0FFF0000, +}; + +/* TGC */ +enum TGC_BIT { + TGC_TSM0 = 0x00000001, + TGC_TSM1 = 0x00000002, + TGC_TSM2 = 0x00000004, + TGC_TSM3 = 0x00000008, + TGC_TQP = 0x00000030, + TGC_TQP_NONAVB = 0x00000000, + TGC_TQP_AVBMODE1 = 0x00000010, + TGC_TQP_AVBMODE2 = 0x00000030, + TGC_TBD0 = 0x00000300, + TGC_TBD1 = 0x00003000, + TGC_TBD2 = 0x00030000, + TGC_TBD3 = 0x00300000, +}; + +/* TCCR */ +enum TCCR_BIT { + TCCR_TSRQ0 = 0x00000001, + TCCR_TSRQ1 = 0x00000002, + TCCR_TSRQ2 = 0x00000004, + TCCR_TSRQ3 = 0x00000008, + TCCR_TFEN = 0x00000100, + TCCR_TFR = 0x00000200, +}; + +/* TSR */ +enum TSR_BIT { + TSR_CCS0 = 0x00000003, + TSR_CCS1 = 0x0000000C, + TSR_TFFL = 0x00000700, +}; + +/* TFA2 */ +enum TFA2_BIT { + TFA2_TSV = 0x0000FFFF, + TFA2_TST = 0x03FF0000, +}; + +/* DIC */ +enum DIC_BIT { + DIC_DPE1 = 0x00000002, + DIC_DPE2 = 0x00000004, + DIC_DPE3 = 0x00000008, + DIC_DPE4 = 0x00000010, + DIC_DPE5 = 0x00000020, + DIC_DPE6 = 0x00000040, + DIC_DPE7 = 0x00000080, + DIC_DPE8 = 0x00000100, + DIC_DPE9 = 0x00000200, + DIC_DPE10 = 0x00000400, + DIC_DPE11 = 0x00000800, + DIC_DPE12 = 0x00001000, + DIC_DPE13 = 0x00002000, + DIC_DPE14 = 0x00004000, + DIC_DPE15 = 0x00008000, +}; + +/* DIS */ +enum DIS_BIT { + DIS_DPF1 = 0x00000002, + DIS_DPF2 = 0x00000004, + DIS_DPF3 = 0x00000008, + DIS_DPF4 = 0x00000010, + DIS_DPF5 = 0x00000020, + DIS_DPF6 = 0x00000040, + DIS_DPF7 = 0x00000080, + DIS_DPF8 = 0x00000100, + DIS_DPF9 = 0x00000200, + DIS_DPF10 = 0x00000400, + DIS_DPF11 = 0x00000800, + DIS_DPF12 = 0x00001000, + DIS_DPF13 = 0x00002000, + DIS_DPF14 = 0x00004000, + DIS_DPF15 = 0x00008000, +}; + +/* EIC */ +enum EIC_BIT { + EIC_MREE = 0x00000001, + EIC_MTEE = 0x00000002, + EIC_QEE = 0x00000004, + EIC_SEE = 0x00000008, + EIC_CLLE0 = 0x00000010, + EIC_CLLE1 = 0x00000020, + EIC_CULE0 = 0x00000040, + EIC_CULE1 = 0x00000080, + EIC_TFFE = 0x00000100, +}; + +/* EIS */ +enum EIS_BIT { + EIS_MREF = 0x00000001, + EIS_MTEF = 0x00000002, + EIS_QEF = 0x00000004, + EIS_SEF = 0x00000008, + EIS_CLLF0 = 0x00000010, + EIS_CLLF1 = 0x00000020, + EIS_CULF0 = 0x00000040, + EIS_CULF1 = 0x00000080, + EIS_TFFF = 0x00000100, + EIS_QFS = 0x00010000, +}; + +/* RIC0 */ +enum RIC0_BIT { + RIC0_FRE0 = 0x00000001, + RIC0_FRE1 = 0x00000002, + RIC0_FRE2 = 0x00000004, + RIC0_FRE3 = 0x00000008, + RIC0_FRE4 = 0x00000010, + RIC0_FRE5 = 0x00000020, + RIC0_FRE6 = 0x00000040, + RIC0_FRE7 = 0x00000080, + RIC0_FRE8 = 0x00000100, + RIC0_FRE9 = 0x00000200, + RIC0_FRE10 = 0x00000400, + RIC0_FRE11 = 0x00000800, + RIC0_FRE12 = 0x00001000, + RIC0_FRE13 = 0x00002000, + RIC0_FRE14 = 0x00004000, + RIC0_FRE15 = 0x00008000, + RIC0_FRE16 = 0x00010000, + RIC0_FRE17 = 0x00020000, +}; + +/* RIC0 */ +enum RIS0_BIT { + RIS0_FRF0 = 0x00000001, + RIS0_FRF1 = 0x00000002, + RIS0_FRF2 = 0x00000004, + RIS0_FRF3 = 0x00000008, + RIS0_FRF4 = 0x00000010, + RIS0_FRF5 = 0x00000020, + RIS0_FRF6 = 0x00000040, + RIS0_FRF7 = 0x00000080, + RIS0_FRF8 = 0x00000100, + RIS0_FRF9 = 0x00000200, + RIS0_FRF10 = 0x00000400, + RIS0_FRF11 = 0x00000800, + RIS0_FRF12 = 0x00001000, + RIS0_FRF13 = 0x00002000, + RIS0_FRF14 = 0x00004000, + RIS0_FRF15 = 0x00008000, + RIS0_FRF16 = 0x00010000, + RIS0_FRF17 = 0x00020000, +}; + +/* RIC1 */ +enum RIC1_BIT { + RIC1_RFWE = 0x80000000, +}; + +/* RIS1 */ +enum RIS1_BIT { + RIS1_RFWF = 0x80000000, +}; + +/* RIC2 */ +enum RIC2_BIT { + RIC2_QFE0 = 0x00000001, + RIC2_QFE1 = 0x00000002, + RIC2_QFE2 = 0x00000004, + RIC2_QFE3 = 0x00000008, + RIC2_QFE4 = 0x00000010, + RIC2_QFE5 = 0x00000020, + RIC2_QFE6 = 0x00000040, + RIC2_QFE7 = 0x00000080, + RIC2_QFE8 = 0x00000100, + RIC2_QFE9 = 0x00000200, + RIC2_QFE10 = 0x00000400, + RIC2_QFE11 = 0x00000800, + RIC2_QFE12 = 0x00001000, + RIC2_QFE13 = 0x00002000, + RIC2_QFE14 = 0x00004000, + RIC2_QFE15 = 0x00008000, + RIC2_QFE16 = 0x00010000, + RIC2_QFE17 = 0x00020000, + RIC2_RFFE = 0x80000000, +}; + +/* RIS2 */ +enum RIS2_BIT { + RIS2_QFF0 = 0x00000001, + RIS2_QFF1 = 0x00000002, + RIS2_QFF2 = 0x00000004, + RIS2_QFF3 = 0x00000008, + RIS2_QFF4 = 0x00000010, + RIS2_QFF5 = 0x00000020, + RIS2_QFF6 = 0x00000040, + RIS2_QFF7 = 0x00000080, + RIS2_QFF8 = 0x00000100, + RIS2_QFF9 = 0x00000200, + RIS2_QFF10 = 0x00000400, + RIS2_QFF11 = 0x00000800, + RIS2_QFF12 = 0x00001000, + RIS2_QFF13 = 0x00002000, + RIS2_QFF14 = 0x00004000, + RIS2_QFF15 = 0x00008000, + RIS2_QFF16 = 0x00010000, + RIS2_QFF17 = 0x00020000, + RIS2_RFFF = 0x80000000, +}; + +/* TIC */ +enum TIC_BIT { + TIC_FTE0 = 0x00000001, /* Undocumented? */ + TIC_FTE1 = 0x00000002, /* Undocumented? */ + TIC_TFUE = 0x00000100, + TIC_TFWE = 0x00000200, +}; + +/* TIS */ +enum TIS_BIT { + TIS_FTF0 = 0x00000001, /* Undocumented? */ + TIS_FTF1 = 0x00000002, /* Undocumented? */ + TIS_TFUF = 0x00000100, + TIS_TFWF = 0x00000200, +}; + +/* ISS */ +enum ISS_BIT { + ISS_FRS = 0x00000001, /* Undocumented? */ + ISS_FTS = 0x00000004, /* Undocumented? */ + ISS_ES = 0x00000040, + ISS_MS = 0x00000080, + ISS_TFUS = 0x00000100, + ISS_TFWS = 0x00000200, + ISS_RFWS = 0x00001000, + ISS_CGIS = 0x00002000, + ISS_DPS1 = 0x00020000, + ISS_DPS2 = 0x00040000, + ISS_DPS3 = 0x00080000, + ISS_DPS4 = 0x00100000, + ISS_DPS5 = 0x00200000, + ISS_DPS6 = 0x00400000, + ISS_DPS7 = 0x00800000, + ISS_DPS8 = 0x01000000, + ISS_DPS9 = 0x02000000, + ISS_DPS10 = 0x04000000, + ISS_DPS11 = 0x08000000, + ISS_DPS12 = 0x10000000, + ISS_DPS13 = 0x20000000, + ISS_DPS14 = 0x40000000, + ISS_DPS15 = 0x80000000, +}; + +/* GCCR */ +enum GCCR_BIT { + GCCR_TCR = 0x00000003, + GCCR_TCR_NOREQ = 0x00000000, /* No request */ + GCCR_TCR_RESET = 0x00000001, /* gPTP/AVTP presentation timer reset */ + GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */ + GCCR_LTO = 0x00000004, + GCCR_LTI = 0x00000008, + GCCR_LPTC = 0x00000010, + GCCR_LMTT = 0x00000020, + GCCR_TCSS = 0x00000300, + GCCR_TCSS_GPTP = 0x00000000, /* gPTP timer value */ + GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */ + GCCR_TCSS_AVTP = 0x00000200, /* AVTP presentation time value */ +}; + +/* GTI */ +enum GTI_BIT { + GTI_TIV = 0x0FFFFFFF, +}; + +/* GIC */ +enum GIC_BIT { + GIC_PTCE = 0x00000001, /* Undocumented? */ + GIC_PTME = 0x00000004, +}; + +/* GIS */ +enum GIS_BIT { + GIS_PTCF = 0x00000001, /* Undocumented? */ + GIS_PTMF = 0x00000004, +}; + +/* ECMR */ +enum ECMR_BIT { + ECMR_PRM = 0x00000001, + ECMR_DM = 0x00000002, + ECMR_TE = 0x00000020, + ECMR_RE = 0x00000040, + ECMR_MPDE = 0x00000200, + ECMR_TXF = 0x00010000, /* Undocumented? */ + ECMR_RXF = 0x00020000, + ECMR_PFR = 0x00040000, + ECMR_ZPF = 0x00080000, /* Undocumented? */ + ECMR_RZPF = 0x00100000, + ECMR_DPAD = 0x00200000, + ECMR_RCSC = 0x00800000, + ECMR_TRCCM = 0x04000000, +}; + +/* ECSR */ +enum ECSR_BIT { + ECSR_ICD = 0x00000001, + ECSR_MPD = 0x00000002, + ECSR_LCHNG = 0x00000004, + ECSR_PHYI = 0x00000008, +}; + +/* ECSIPR */ +enum ECSIPR_BIT { + ECSIPR_ICDIP = 0x00000001, + ECSIPR_MPDIP = 0x00000002, + ECSIPR_LCHNGIP = 0x00000004, /* Undocumented? */ +}; + +/* PIR */ +enum PIR_BIT { + PIR_MDC = 0x00000001, + PIR_MMD = 0x00000002, + PIR_MDO = 0x00000004, + PIR_MDI = 0x00000008, +}; + +/* PSR */ +enum PSR_BIT { + PSR_LMON = 0x00000001, +}; + +/* PIPR */ +enum PIPR_BIT { + PIPR_PHYIP = 0x00000001, +}; + +/* MPR */ +enum MPR_BIT { + MPR_MP = 0x0000ffff, +}; + +/* GECMR */ +enum GECMR_BIT { + GECMR_SPEED = 0x00000001, + GECMR_SPEED_100 = 0x00000000, + GECMR_SPEED_1000 = 0x00000001, +}; + +/* The Ethernet AVB descriptor definitions. */ +struct ravb_desc { + __le16 ds; /* Descriptor size */ + u8 cc; /* Content control MSBs (reserved) */ + u8 die_dt; /* Descriptor interrupt enable and type */ + __le32 dptr; /* Descriptor pointer */ +}; + +enum DIE_DT { + /* Frame data */ + DT_FMID = 0x40, + DT_FSTART = 0x50, + DT_FEND = 0x60, + DT_FSINGLE = 0x70, + /* Chain control */ + DT_LINK = 0x80, + DT_LINKFIX = 0x90, + DT_EOS = 0xa0, + /* HW/SW arbitration */ + DT_FEMPTY = 0xc0, + DT_FEMPTY_IS = 0xd0, + DT_FEMPTY_IC = 0xe0, + DT_FEMPTY_ND = 0xf0, + DT_LEMPTY = 0x20, + DT_EEMPTY = 0x30, +}; + +struct ravb_rx_desc { + __le16 ds_cc; /* Descriptor size and content control LSBs */ + u8 msc; /* MAC status code */ + u8 die_dt; /* Descriptor interrupt enable and type */ + __le32 dptr; /* Descpriptor pointer */ +}; + +struct ravb_ex_rx_desc { + __le16 ds_cc; /* Descriptor size and content control lower bits */ + u8 msc; /* MAC status code */ + u8 die_dt; /* Descriptor interrupt enable and type */ + __le32 dptr; /* Descpriptor pointer */ + __le32 ts_n; /* Timestampe nsec */ + __le32 ts_sl; /* Timestamp low */ + __le16 ts_sh; /* Timestamp high */ + __le16 res; /* Reserved bits */ +}; + +enum RX_DS_CC_BIT { + RX_DS = 0x0fff, /* Data size */ + RX_TR = 0x1000, /* Truncation indication */ + RX_EI = 0x2000, /* Error indication */ + RX_PS = 0xc000, /* Padding selection */ +}; + +/* E-MAC status code */ +enum MSC_BIT { + MSC_CRC = 0x01, /* Frame CRC error */ + MSC_RFE = 0x02, /* Frame reception error (flagged by PHY) */ + MSC_RTSF = 0x04, /* Frame length error (frame too short) */ + MSC_RTLF = 0x08, /* Frame length error (frame too long) */ + MSC_FRE = 0x10, /* Fraction error (not a multiple of 8 bits) */ + MSC_CRL = 0x20, /* Carrier lost */ + MSC_CEEF = 0x40, /* Carrier extension error */ + MSC_MC = 0x80, /* Multicast frame reception */ +}; + +struct ravb_tx_desc { + __le16 ds_tagl; /* Descriptor size and frame tag LSBs */ + u8 tagh_tsr; /* Frame tag MSBs and timestamp storage request bit */ + u8 die_dt; /* Descriptor interrupt enable and type */ + __le32 dptr; /* Descpriptor pointer */ +}; + +enum TX_DS_TAGL_BIT { + TX_DS = 0x0fff, /* Data size */ + TX_TAGL = 0xf000, /* Frame tag LSBs */ +}; + +enum TX_TAGH_TSR_BIT { + TX_TAGH = 0x3f, /* Frame tag MSBs */ + TX_TSR = 0x40, /* Timestamp storage request */ +}; +enum RAVB_QUEUE { + RAVB_BE = 0, /* Best Effort Queue */ + RAVB_NC, /* Network Control Queue */ +}; + +#define DBAT_ENTRY_NUM 22 +#define RX_QUEUE_OFFSET 4 +#define NUM_RX_QUEUE 2 +#define NUM_TX_QUEUE 2 + +struct ravb_tstamp_skb { + struct list_head list; + struct sk_buff *skb; + u16 tag; +}; + +struct ravb_private { + struct net_device *ndev; + struct platform_device *pdev; + void __iomem *addr; + struct mdiobb_ctrl mdiobb; + u32 num_rx_ring[NUM_RX_QUEUE]; + u32 num_tx_ring[NUM_TX_QUEUE]; + u32 desc_bat_size; + dma_addr_t desc_bat_dma; + struct ravb_desc *desc_bat; + dma_addr_t rx_desc_dma[NUM_RX_QUEUE]; + dma_addr_t tx_desc_dma[NUM_TX_QUEUE]; + struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE]; + struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE]; + struct sk_buff **rx_skb[NUM_RX_QUEUE]; + struct sk_buff **tx_skb[NUM_TX_QUEUE]; + void **tx_buffers[NUM_TX_QUEUE]; + u32 rx_over_errors; + u32 rx_fifo_errors; + struct net_device_stats stats[NUM_RX_QUEUE]; + u32 tstamp_tx_ctrl; + u32 tstamp_rx_ctrl; + struct list_head ts_skb_list; + u32 ts_skb_tag; + spinlock_t lock; /* Register access lock */ + u32 cur_rx[NUM_RX_QUEUE]; /* Consumer ring indices */ + u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */ + u32 cur_tx[NUM_TX_QUEUE]; + u32 dirty_tx[NUM_TX_QUEUE]; + struct napi_struct napi[NUM_RX_QUEUE]; + struct work_struct work; + /* MII transceiver section. */ + struct mii_bus *mii_bus; /* MDIO bus control */ + struct phy_device *phydev; /* PHY device control */ + int link; + phy_interface_t phy_interface; + int msg_enable; + int speed; + int duplex; + + unsigned no_avb_link:1; + unsigned avb_link_active_low:1; +}; + +static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) +{ + struct ravb_private *priv = netdev_priv(ndev); + + return ioread32(priv->addr + reg); +} + +static inline void ravb_write(struct net_device *ndev, u32 data, + enum ravb_reg reg) +{ + struct ravb_private *priv = netdev_priv(ndev); + + iowrite32(data, priv->addr + reg); +} + +#endif /* #ifndef __RAVB_H__ */ -- cgit v1.2.3 From 07a7dba17132d7ebc5d9f34a06baedf2308ccc01 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 11 May 2015 17:08:51 +0100 Subject: dt: mailbox: Remove 'mbox-names property is discouraged' message from binding A new API call has been introduced which allows channels to be requested by name. This new call uses the 'mbox-names' property, so users need no further discouragement from supplying it. Signed-off-by: Lee Jones Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/mailbox.txt | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Documentation/devicetree/bindings/mailbox/mailbox.txt index 1a2cd3d266db..be05b9746c69 100644 --- a/Documentation/devicetree/bindings/mailbox/mailbox.txt +++ b/Documentation/devicetree/bindings/mailbox/mailbox.txt @@ -22,17 +22,11 @@ Required property: - mboxes: List of phandle and mailbox channel specifiers. Optional property: -- mbox-names: List of identifier strings for each mailbox channel - required by the client. The use of this property - is discouraged in favor of using index in list of - 'mboxes' while requesting a mailbox. Instead the - platforms may define channel indices, in DT headers, - to something legible. +- mbox-names: List of identifier strings for each mailbox channel. Example: pwr_cntrl: power { ... mbox-names = "pwr-ctrl", "rpc"; - mboxes = <&mailbox 0 - &mailbox 1>; + mboxes = <&mailbox 0 &mailbox 1>; }; -- cgit v1.2.3 From 028ae9f76f2935e8cf9974bff9a4587e3a995ff3 Mon Sep 17 00:00:00 2001 From: Joe Thornber Date: Wed, 22 Apr 2015 16:42:35 -0400 Subject: dm cache: add fail io mode and needs_check flag If a cache metadata operation fails (e.g. transaction commit) the cache's metadata device will abort the current transaction, set a new needs_check flag, and the cache will transition to "read-only" mode. If aborting the transaction or setting the needs_check flag fails the cache will transition to "fail-io" mode. Once needs_check is set the cache device will not be allowed to activate. Activation requires write access to metadata. Future work is needed to add proper support for running the cache in read-only mode. Once in fail-io mode the cache will report a status of "Fail". Also, add commit() wrapper that will disallow commits if in read_only or fail mode. Signed-off-by: Joe Thornber Signed-off-by: Mike Snitzer --- Documentation/device-mapper/cache.txt | 9 +- drivers/md/dm-cache-metadata.c | 133 ++++++++++++++++++---- drivers/md/dm-cache-metadata.h | 10 ++ drivers/md/dm-cache-policy-internal.h | 10 +- drivers/md/dm-cache-policy-mq.c | 8 +- drivers/md/dm-cache-policy.h | 4 +- drivers/md/dm-cache-target.c | 204 +++++++++++++++++++++++++++++----- 7 files changed, 320 insertions(+), 58 deletions(-) (limited to 'Documentation') diff --git a/Documentation/device-mapper/cache.txt b/Documentation/device-mapper/cache.txt index 68c0f517c60e..82960cffbad3 100644 --- a/Documentation/device-mapper/cache.txt +++ b/Documentation/device-mapper/cache.txt @@ -221,6 +221,7 @@ Status <#read hits> <#read misses> <#write hits> <#write misses> <#demotions> <#promotions> <#dirty> <#features> * <#core args> * <#policy args> * + metadata block size : Fixed block size for each metadata block in sectors @@ -251,8 +252,12 @@ core args : Key/value pairs for tuning the core e.g. migration_threshold policy name : Name of the policy #policy args : Number of policy arguments to follow (must be even) -policy args : Key/value pairs - e.g. sequential_threshold +policy args : Key/value pairs e.g. sequential_threshold +cache metadata mode : ro if read-only, rw if read-write + In serious cases where even a read-only mode is deemed unsafe + no further I/O will be permitted and the status will just + contain the string 'Fail'. The userspace recovery tools + should then be used. Messages -------- diff --git a/drivers/md/dm-cache-metadata.c b/drivers/md/dm-cache-metadata.c index c1c010498a21..20cc36b01b77 100644 --- a/drivers/md/dm-cache-metadata.c +++ b/drivers/md/dm-cache-metadata.c @@ -39,6 +39,8 @@ enum superblock_flag_bits { /* for spotting crashes that would invalidate the dirty bitset */ CLEAN_SHUTDOWN, + /* metadata must be checked using the tools */ + NEEDS_CHECK, }; /* @@ -107,6 +109,7 @@ struct dm_cache_metadata { struct dm_disk_bitset discard_info; struct rw_semaphore root_lock; + unsigned long flags; dm_block_t root; dm_block_t hint_root; dm_block_t discard_root; @@ -129,6 +132,14 @@ struct dm_cache_metadata { * buffer before the superblock is locked and updated. */ __u8 metadata_space_map_root[SPACE_MAP_ROOT_SIZE]; + + /* + * Set if a transaction has to be aborted but the attempt to roll + * back to the previous (good) transaction failed. The only + * metadata operation permissible in this state is the closing of + * the device. + */ + bool fail_io:1; }; /*------------------------------------------------------------------- @@ -527,6 +538,7 @@ static unsigned long clear_clean_shutdown(unsigned long flags) static void read_superblock_fields(struct dm_cache_metadata *cmd, struct cache_disk_superblock *disk_super) { + cmd->flags = le32_to_cpu(disk_super->flags); cmd->root = le64_to_cpu(disk_super->mapping_root); cmd->hint_root = le64_to_cpu(disk_super->hint_root); cmd->discard_root = le64_to_cpu(disk_super->discard_root); @@ -625,6 +637,7 @@ static int __commit_transaction(struct dm_cache_metadata *cmd, if (mutator) update_flags(disk_super, mutator); + disk_super->flags = cpu_to_le32(cmd->flags); disk_super->mapping_root = cpu_to_le64(cmd->root); disk_super->hint_root = cpu_to_le64(cmd->hint_root); disk_super->discard_root = cpu_to_le64(cmd->discard_root); @@ -693,6 +706,7 @@ static struct dm_cache_metadata *metadata_open(struct block_device *bdev, cmd->cache_blocks = 0; cmd->policy_hint_size = policy_hint_size; cmd->changed = true; + cmd->fail_io = false; r = __create_persistent_data_objects(cmd, may_format_device); if (r) { @@ -796,7 +810,8 @@ void dm_cache_metadata_close(struct dm_cache_metadata *cmd) list_del(&cmd->list); mutex_unlock(&table_lock); - __destroy_persistent_data_objects(cmd); + if (!cmd->fail_io) + __destroy_persistent_data_objects(cmd); kfree(cmd); } } @@ -848,13 +863,26 @@ static int blocks_are_unmapped_or_clean(struct dm_cache_metadata *cmd, return 0; } +#define WRITE_LOCK(cmd) \ + if (cmd->fail_io || dm_bm_is_read_only(cmd->bm)) \ + return -EINVAL; \ + down_write(&cmd->root_lock) + +#define WRITE_LOCK_VOID(cmd) \ + if (cmd->fail_io || dm_bm_is_read_only(cmd->bm)) \ + return; \ + down_write(&cmd->root_lock) + +#define WRITE_UNLOCK(cmd) \ + up_write(&cmd->root_lock) + int dm_cache_resize(struct dm_cache_metadata *cmd, dm_cblock_t new_cache_size) { int r; bool clean; __le64 null_mapping = pack_value(0, 0); - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); __dm_bless_for_disk(&null_mapping); if (from_cblock(new_cache_size) < from_cblock(cmd->cache_blocks)) { @@ -880,7 +908,7 @@ int dm_cache_resize(struct dm_cache_metadata *cmd, dm_cblock_t new_cache_size) cmd->changed = true; out: - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -891,7 +919,7 @@ int dm_cache_discard_bitset_resize(struct dm_cache_metadata *cmd, { int r; - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = dm_bitset_resize(&cmd->discard_info, cmd->discard_root, from_dblock(cmd->discard_nr_blocks), @@ -903,7 +931,7 @@ int dm_cache_discard_bitset_resize(struct dm_cache_metadata *cmd, } cmd->changed = true; - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -946,9 +974,9 @@ int dm_cache_set_discard(struct dm_cache_metadata *cmd, { int r; - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = __discard(cmd, dblock, discard); - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -1020,9 +1048,9 @@ int dm_cache_remove_mapping(struct dm_cache_metadata *cmd, dm_cblock_t cblock) { int r; - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = __remove(cmd, cblock); - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -1048,9 +1076,9 @@ int dm_cache_insert_mapping(struct dm_cache_metadata *cmd, { int r; - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = __insert(cmd, cblock, oblock); - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -1234,9 +1262,9 @@ int dm_cache_set_dirty(struct dm_cache_metadata *cmd, { int r; - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = __dirty(cmd, cblock, dirty); - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -1252,9 +1280,9 @@ void dm_cache_metadata_get_stats(struct dm_cache_metadata *cmd, void dm_cache_metadata_set_stats(struct dm_cache_metadata *cmd, struct dm_cache_statistics *stats) { - down_write(&cmd->root_lock); + WRITE_LOCK_VOID(cmd); cmd->stats = *stats; - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); } int dm_cache_commit(struct dm_cache_metadata *cmd, bool clean_shutdown) @@ -1263,7 +1291,7 @@ int dm_cache_commit(struct dm_cache_metadata *cmd, bool clean_shutdown) flags_mutator mutator = (clean_shutdown ? set_clean_shutdown : clear_clean_shutdown); - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = __commit_transaction(cmd, mutator); if (r) goto out; @@ -1271,7 +1299,7 @@ int dm_cache_commit(struct dm_cache_metadata *cmd, bool clean_shutdown) r = __begin_transaction(cmd); out: - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -1376,9 +1404,9 @@ int dm_cache_write_hints(struct dm_cache_metadata *cmd, struct dm_cache_policy * { int r; - down_write(&cmd->root_lock); + WRITE_LOCK(cmd); r = write_hints(cmd, policy); - up_write(&cmd->root_lock); + WRITE_UNLOCK(cmd); return r; } @@ -1387,3 +1415,70 @@ int dm_cache_metadata_all_clean(struct dm_cache_metadata *cmd, bool *result) { return blocks_are_unmapped_or_clean(cmd, 0, cmd->cache_blocks, result); } + +void dm_cache_metadata_set_read_only(struct dm_cache_metadata *cmd) +{ + WRITE_LOCK_VOID(cmd); + dm_bm_set_read_only(cmd->bm); + WRITE_UNLOCK(cmd); +} + +void dm_cache_metadata_set_read_write(struct dm_cache_metadata *cmd) +{ + WRITE_LOCK_VOID(cmd); + dm_bm_set_read_write(cmd->bm); + WRITE_UNLOCK(cmd); +} + +int dm_cache_metadata_set_needs_check(struct dm_cache_metadata *cmd) +{ + int r; + struct dm_block *sblock; + struct cache_disk_superblock *disk_super; + + /* + * We ignore fail_io for this function. + */ + down_write(&cmd->root_lock); + set_bit(NEEDS_CHECK, &cmd->flags); + + r = superblock_lock(cmd, &sblock); + if (r) { + DMERR("couldn't read superblock"); + goto out; + } + + disk_super = dm_block_data(sblock); + disk_super->flags = cpu_to_le32(cmd->flags); + + dm_bm_unlock(sblock); + +out: + up_write(&cmd->root_lock); + return r; +} + +bool dm_cache_metadata_needs_check(struct dm_cache_metadata *cmd) +{ + bool needs_check; + + down_read(&cmd->root_lock); + needs_check = !!test_bit(NEEDS_CHECK, &cmd->flags); + up_read(&cmd->root_lock); + + return needs_check; +} + +int dm_cache_metadata_abort(struct dm_cache_metadata *cmd) +{ + int r; + + WRITE_LOCK(cmd); + __destroy_persistent_data_objects(cmd); + r = __create_persistent_data_objects(cmd, false); + if (r) + cmd->fail_io = true; + WRITE_UNLOCK(cmd); + + return r; +} diff --git a/drivers/md/dm-cache-metadata.h b/drivers/md/dm-cache-metadata.h index 4ecc403be283..2ffee21f318d 100644 --- a/drivers/md/dm-cache-metadata.h +++ b/drivers/md/dm-cache-metadata.h @@ -102,6 +102,10 @@ struct dm_cache_statistics { void dm_cache_metadata_get_stats(struct dm_cache_metadata *cmd, struct dm_cache_statistics *stats); + +/* + * 'void' because it's no big deal if it fails. + */ void dm_cache_metadata_set_stats(struct dm_cache_metadata *cmd, struct dm_cache_statistics *stats); @@ -133,6 +137,12 @@ int dm_cache_write_hints(struct dm_cache_metadata *cmd, struct dm_cache_policy * */ int dm_cache_metadata_all_clean(struct dm_cache_metadata *cmd, bool *result); +bool dm_cache_metadata_needs_check(struct dm_cache_metadata *cmd); +int dm_cache_metadata_set_needs_check(struct dm_cache_metadata *cmd); +void dm_cache_metadata_set_read_only(struct dm_cache_metadata *cmd); +void dm_cache_metadata_set_read_write(struct dm_cache_metadata *cmd); +int dm_cache_metadata_abort(struct dm_cache_metadata *cmd); + /*----------------------------------------------------------------*/ #endif /* DM_CACHE_METADATA_H */ diff --git a/drivers/md/dm-cache-policy-internal.h b/drivers/md/dm-cache-policy-internal.h index 9dc05a52369e..ccbe852d5362 100644 --- a/drivers/md/dm-cache-policy-internal.h +++ b/drivers/md/dm-cache-policy-internal.h @@ -89,13 +89,15 @@ static inline void policy_tick(struct dm_cache_policy *p) return p->tick(p); } -static inline int policy_emit_config_values(struct dm_cache_policy *p, char *result, unsigned maxlen) +static inline int policy_emit_config_values(struct dm_cache_policy *p, char *result, + unsigned maxlen, ssize_t *sz_ptr) { - ssize_t sz = 0; + ssize_t sz = *sz_ptr; if (p->emit_config_values) - return p->emit_config_values(p, result, maxlen); + return p->emit_config_values(p, result, maxlen, sz_ptr); - DMEMIT("0"); + DMEMIT("0 "); + *sz_ptr = sz; return 0; } diff --git a/drivers/md/dm-cache-policy-mq.c b/drivers/md/dm-cache-policy-mq.c index 7cbae125879c..084eec653321 100644 --- a/drivers/md/dm-cache-policy-mq.c +++ b/drivers/md/dm-cache-policy-mq.c @@ -1323,22 +1323,24 @@ static int mq_set_config_value(struct dm_cache_policy *p, return 0; } -static int mq_emit_config_values(struct dm_cache_policy *p, char *result, unsigned maxlen) +static int mq_emit_config_values(struct dm_cache_policy *p, char *result, + unsigned maxlen, ssize_t *sz_ptr) { - ssize_t sz = 0; + ssize_t sz = *sz_ptr; struct mq_policy *mq = to_mq_policy(p); DMEMIT("10 random_threshold %u " "sequential_threshold %u " "discard_promote_adjustment %u " "read_promote_adjustment %u " - "write_promote_adjustment %u", + "write_promote_adjustment %u ", mq->tracker.thresholds[PATTERN_RANDOM], mq->tracker.thresholds[PATTERN_SEQUENTIAL], mq->discard_promote_adjustment, mq->read_promote_adjustment, mq->write_promote_adjustment); + *sz_ptr = sz; return 0; } diff --git a/drivers/md/dm-cache-policy.h b/drivers/md/dm-cache-policy.h index 6106ca3aa350..74709129d856 100644 --- a/drivers/md/dm-cache-policy.h +++ b/drivers/md/dm-cache-policy.h @@ -208,8 +208,8 @@ struct dm_cache_policy { /* * Configuration. */ - int (*emit_config_values)(struct dm_cache_policy *p, - char *result, unsigned maxlen); + int (*emit_config_values)(struct dm_cache_policy *p, char *result, + unsigned maxlen, ssize_t *sz_ptr); int (*set_config_value)(struct dm_cache_policy *p, const char *key, const char *value); diff --git a/drivers/md/dm-cache-target.c b/drivers/md/dm-cache-target.c index 6d36ed3c46a0..dae0321ebfa9 100644 --- a/drivers/md/dm-cache-target.c +++ b/drivers/md/dm-cache-target.c @@ -150,12 +150,10 @@ static void dm_unhook_bio(struct dm_hook_info *h, struct bio *bio) #define DATA_DEV_BLOCK_SIZE_MIN_SECTORS (32 * 1024 >> SECTOR_SHIFT) #define DATA_DEV_BLOCK_SIZE_MAX_SECTORS (1024 * 1024 * 1024 >> SECTOR_SHIFT) -/* - * FIXME: the cache is read/write for the time being. - */ enum cache_metadata_mode { CM_WRITE, /* metadata may be changed */ CM_READ_ONLY, /* metadata may not be changed */ + CM_FAIL }; enum cache_io_mode { @@ -385,6 +383,8 @@ struct prealloc { struct dm_bio_prison_cell *cell2; }; +static enum cache_metadata_mode get_cache_mode(struct cache *cache); + static void wake_worker(struct cache *cache) { queue_work(cache->wq, &cache->worker); @@ -699,6 +699,9 @@ static void save_stats(struct cache *cache) { struct dm_cache_statistics stats; + if (get_cache_mode(cache) >= CM_READ_ONLY) + return; + stats.read_hits = atomic_read(&cache->stats.read_hit); stats.read_misses = atomic_read(&cache->stats.read_miss); stats.write_hits = atomic_read(&cache->stats.write_hit); @@ -957,6 +960,84 @@ static void remap_to_origin_then_cache(struct cache *cache, struct bio *bio, remap_to_origin_clear_discard(pb->cache, bio, oblock); } +/*---------------------------------------------------------------- + * Failure modes + *--------------------------------------------------------------*/ +static enum cache_metadata_mode get_cache_mode(struct cache *cache) +{ + return cache->features.mode; +} + +static void notify_mode_switch(struct cache *cache, enum cache_metadata_mode mode) +{ + const char *descs[] = { + "write", + "read-only", + "fail" + }; + + dm_table_event(cache->ti->table); + DMINFO("switching cache to %s mode", descs[(int)mode]); +} + +static void set_cache_mode(struct cache *cache, enum cache_metadata_mode new_mode) +{ + bool needs_check = dm_cache_metadata_needs_check(cache->cmd); + enum cache_metadata_mode old_mode = get_cache_mode(cache); + + if (new_mode == CM_WRITE && needs_check) { + DMERR("unable to switch cache to write mode until repaired."); + if (old_mode != new_mode) + new_mode = old_mode; + else + new_mode = CM_READ_ONLY; + } + + /* Never move out of fail mode */ + if (old_mode == CM_FAIL) + new_mode = CM_FAIL; + + switch (new_mode) { + case CM_FAIL: + case CM_READ_ONLY: + dm_cache_metadata_set_read_only(cache->cmd); + break; + + case CM_WRITE: + dm_cache_metadata_set_read_write(cache->cmd); + break; + } + + cache->features.mode = new_mode; + + if (new_mode != old_mode) + notify_mode_switch(cache, new_mode); +} + +static void abort_transaction(struct cache *cache) +{ + if (get_cache_mode(cache) >= CM_READ_ONLY) + return; + + if (dm_cache_metadata_set_needs_check(cache->cmd)) { + DMERR("failed to set 'needs_check' flag in metadata"); + set_cache_mode(cache, CM_FAIL); + } + + DMERR_LIMIT("aborting current metadata transaction"); + if (dm_cache_metadata_abort(cache->cmd)) { + DMERR("failed to abort metadata transaction"); + set_cache_mode(cache, CM_FAIL); + } +} + +static void metadata_operation_failed(struct cache *cache, const char *op, int r) +{ + DMERR_LIMIT("metadata operation '%s' failed: error = %d", op, r); + abort_transaction(cache); + set_cache_mode(cache, CM_READ_ONLY); +} + /*---------------------------------------------------------------- * Migration processing * @@ -1063,6 +1144,7 @@ static void migration_failure(struct dm_cache_migration *mg) static void migration_success_pre_commit(struct dm_cache_migration *mg) { + int r; unsigned long flags; struct cache *cache = mg->cache; @@ -1073,8 +1155,10 @@ static void migration_success_pre_commit(struct dm_cache_migration *mg) return; } else if (mg->demote) { - if (dm_cache_remove_mapping(cache->cmd, mg->cblock)) { + r = dm_cache_remove_mapping(cache->cmd, mg->cblock); + if (r) { DMWARN_LIMIT("demotion failed; couldn't update on disk metadata"); + metadata_operation_failed(cache, "dm_cache_remove_mapping", r); policy_force_mapping(cache->policy, mg->new_oblock, mg->old_oblock); if (mg->promote) @@ -1083,8 +1167,10 @@ static void migration_success_pre_commit(struct dm_cache_migration *mg) return; } } else { - if (dm_cache_insert_mapping(cache->cmd, mg->cblock, mg->new_oblock)) { + r = dm_cache_insert_mapping(cache->cmd, mg->cblock, mg->new_oblock); + if (r) { DMWARN_LIMIT("promotion failed; couldn't update on disk metadata"); + metadata_operation_failed(cache, "dm_cache_insert_mapping", r); policy_remove_mapping(cache->policy, mg->new_oblock); free_io_migration(mg); return; @@ -1812,15 +1898,32 @@ static int need_commit_due_to_time(struct cache *cache) jiffies > cache->last_commit_jiffies + COMMIT_PERIOD; } +/* + * A non-zero return indicates read_only or fail_io mode. + */ +static int commit(struct cache *cache, bool clean_shutdown) +{ + int r; + + if (get_cache_mode(cache) >= CM_READ_ONLY) + return -EINVAL; + + atomic_inc(&cache->stats.commit_count); + r = dm_cache_commit(cache->cmd, clean_shutdown); + if (r) + metadata_operation_failed(cache, "dm_cache_commit", r); + + return r; +} + static int commit_if_needed(struct cache *cache) { int r = 0; if ((cache->commit_requested || need_commit_due_to_time(cache)) && dm_cache_changed_this_transaction(cache->cmd)) { - atomic_inc(&cache->stats.commit_count); + r = commit(cache, false); cache->commit_requested = false; - r = dm_cache_commit(cache->cmd, false); cache->last_commit_jiffies = jiffies; } @@ -1988,8 +2091,10 @@ static void process_invalidation_request(struct cache *cache, struct invalidatio r = policy_remove_cblock(cache->policy, to_cblock(begin)); if (!r) { r = dm_cache_remove_mapping(cache->cmd, to_cblock(begin)); - if (r) + if (r) { + metadata_operation_failed(cache, "dm_cache_remove_mapping", r); break; + } } else if (r == -ENODATA) { /* harmless, already unmapped */ @@ -2133,12 +2238,6 @@ static void do_worker(struct work_struct *ws) if (commit_if_needed(cache)) { process_deferred_flush_bios(cache, false); process_migrations(cache, &cache->need_commit_migrations, migration_failure); - - /* - * FIXME: rollback metadata or just go into a - * failure mode and error everything - */ - } else { process_deferred_flush_bios(cache, true); process_migrations(cache, &cache->need_commit_migrations, @@ -2711,6 +2810,12 @@ static int cache_create(struct cache_args *ca, struct cache **result) goto bad; } cache->cmd = cmd; + set_cache_mode(cache, CM_WRITE); + if (get_cache_mode(cache) != CM_WRITE) { + *error = "Unable to get write access to metadata, please check/repair metadata."; + r = -EINVAL; + goto bad; + } if (passthrough_mode(&cache->features)) { bool all_clean; @@ -3043,11 +3148,16 @@ static int write_dirty_bitset(struct cache *cache) { unsigned i, r; + if (get_cache_mode(cache) >= CM_READ_ONLY) + return -EINVAL; + for (i = 0; i < from_cblock(cache->cache_size); i++) { r = dm_cache_set_dirty(cache->cmd, to_cblock(i), is_dirty(cache, to_cblock(i))); - if (r) + if (r) { + metadata_operation_failed(cache, "dm_cache_set_dirty", r); return r; + } } return 0; @@ -3057,18 +3167,40 @@ static int write_discard_bitset(struct cache *cache) { unsigned i, r; + if (get_cache_mode(cache) >= CM_READ_ONLY) + return -EINVAL; + r = dm_cache_discard_bitset_resize(cache->cmd, cache->discard_block_size, cache->discard_nr_blocks); if (r) { DMERR("could not resize on-disk discard bitset"); + metadata_operation_failed(cache, "dm_cache_discard_bitset_resize", r); return r; } for (i = 0; i < from_dblock(cache->discard_nr_blocks); i++) { r = dm_cache_set_discard(cache->cmd, to_dblock(i), is_discarded(cache, to_dblock(i))); - if (r) + if (r) { + metadata_operation_failed(cache, "dm_cache_set_discard", r); return r; + } + } + + return 0; +} + +static int write_hints(struct cache *cache) +{ + int r; + + if (get_cache_mode(cache) >= CM_READ_ONLY) + return -EINVAL; + + r = dm_cache_write_hints(cache->cmd, cache->policy); + if (r) { + metadata_operation_failed(cache, "dm_cache_write_hints", r); + return r; } return 0; @@ -3091,7 +3223,7 @@ static bool sync_metadata(struct cache *cache) save_stats(cache); - r3 = dm_cache_write_hints(cache->cmd, cache->policy); + r3 = write_hints(cache); if (r3) DMERR("could not write hints"); @@ -3100,9 +3232,9 @@ static bool sync_metadata(struct cache *cache) * set the clean shutdown flag. This will effectively force every * dirty bit to be set on reload. */ - r4 = dm_cache_commit(cache->cmd, !r1 && !r2 && !r3); + r4 = commit(cache, !r1 && !r2 && !r3); if (r4) - DMERR("could not write cache metadata. Data loss may occur."); + DMERR("could not write cache metadata."); return !r1 && !r2 && !r3 && !r4; } @@ -3118,7 +3250,8 @@ static void cache_postsuspend(struct dm_target *ti) requeue_deferred_cells(cache); stop_quiescing(cache); - (void) sync_metadata(cache); + if (get_cache_mode(cache) == CM_WRITE) + (void) sync_metadata(cache); } static int load_mapping(void *context, dm_oblock_t oblock, dm_cblock_t cblock, @@ -3257,6 +3390,7 @@ static int resize_cache_dev(struct cache *cache, dm_cblock_t new_size) r = dm_cache_resize(cache->cmd, new_size); if (r) { DMERR("could not resize cache metadata"); + metadata_operation_failed(cache, "dm_cache_resize", r); return r; } @@ -3295,6 +3429,7 @@ static int cache_preresume(struct dm_target *ti) load_mapping, cache); if (r) { DMERR("could not load cache mappings"); + metadata_operation_failed(cache, "dm_cache_load_mappings", r); return r; } @@ -3315,6 +3450,7 @@ static int cache_preresume(struct dm_target *ti) r = dm_cache_load_discards(cache->cmd, load_discard, &li); if (r) { DMERR("could not load origin discards"); + metadata_operation_failed(cache, "dm_cache_load_discards", r); return r; } set_discard_range(&li); @@ -3342,7 +3478,7 @@ static void cache_resume(struct dm_target *ti) * <#demotions> <#promotions> <#dirty> * <#features> * * <#core args> - * <#policy args> * + * <#policy args> * */ static void cache_status(struct dm_target *ti, status_type_t type, unsigned status_flags, char *result, unsigned maxlen) @@ -3358,13 +3494,15 @@ static void cache_status(struct dm_target *ti, status_type_t type, switch (type) { case STATUSTYPE_INFO: - /* Commit to ensure statistics aren't out-of-date */ - if (!(status_flags & DM_STATUS_NOFLUSH_FLAG) && !dm_suspended(ti)) { - r = dm_cache_commit(cache->cmd, false); - if (r) - DMERR("could not commit metadata for accurate status"); + if (get_cache_mode(cache) == CM_FAIL) { + DMEMIT("Fail"); + break; } + /* Commit to ensure statistics aren't out-of-date */ + if (!(status_flags & DM_STATUS_NOFLUSH_FLAG) && !dm_suspended(ti)) + (void) commit(cache, false); + r = dm_cache_get_free_metadata_block_count(cache->cmd, &nr_free_blocks_metadata); if (r) { @@ -3413,11 +3551,16 @@ static void cache_status(struct dm_target *ti, status_type_t type, DMEMIT("%s ", dm_cache_policy_get_name(cache->policy)); if (sz < maxlen) { - r = policy_emit_config_values(cache->policy, result + sz, maxlen - sz); + r = policy_emit_config_values(cache->policy, result, maxlen, &sz); if (r) DMERR("policy_emit_config_values returned %d", r); } + if (get_cache_mode(cache) == CM_READ_ONLY) + DMEMIT("ro "); + else + DMEMIT("rw "); + break; case STATUSTYPE_TABLE: @@ -3573,6 +3716,11 @@ static int cache_message(struct dm_target *ti, unsigned argc, char **argv) if (!argc) return -EINVAL; + if (get_cache_mode(cache) >= CM_READ_ONLY) { + DMERR("unable to service cache target messages in READ_ONLY or FAIL mode"); + return -EOPNOTSUPP; + } + if (!strcasecmp(argv[0], "invalidate_cblocks")) return process_invalidate_cblocks_message(cache, argc - 1, (const char **) argv + 1); @@ -3646,7 +3794,7 @@ static void cache_io_hints(struct dm_target *ti, struct queue_limits *limits) static struct target_type cache_target = { .name = "cache", - .version = {1, 6, 0}, + .version = {1, 7, 0}, .module = THIS_MODULE, .ctr = cache_ctr, .dtr = cache_dtr, -- cgit v1.2.3 From e097dc624f784debbde49701a493bf920bc422c7 Mon Sep 17 00:00:00 2001 From: Vincent Cuissard Date: Thu, 11 Jun 2015 14:00:20 +0200 Subject: NFC: nfcmrvl: add UART driver Add support of Marvell NFC chip controlled over UART Signed-off-by: Vincent Cuissard Signed-off-by: Samuel Ortiz --- .../devicetree/bindings/net/nfc/nfcmrvl.txt | 29 +++ drivers/nfc/nfcmrvl/Kconfig | 11 + drivers/nfc/nfcmrvl/Makefile | 3 + drivers/nfc/nfcmrvl/nfcmrvl.h | 7 + drivers/nfc/nfcmrvl/uart.c | 225 +++++++++++++++++++++ include/linux/platform_data/nfcmrvl.h | 9 + net/nfc/nci/uart.c | 1 - 7 files changed, 284 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt create mode 100644 drivers/nfc/nfcmrvl/uart.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt b/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt new file mode 100644 index 000000000000..7c4a0cc370cf --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt @@ -0,0 +1,29 @@ +* Marvell International Ltd. NCI NFC Controller + +Required properties: +- compatible: Should be "mrvl,nfc-uart". + +Optional SoC specific properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. +- reset-n-io: Output GPIO pin used to reset the chip (active low). +- hci-muxed: Specifies that the chip is muxing NCI over HCI frames. + +Optional UART-based chip specific properties: +- flow-control: Specifies that the chip is using RTS/CTS. +- break-control: Specifies that the chip needs specific break management. + +Example (for ARM-based BeagleBoard Black with 88W8887 on UART5): + +&uart5 { + status = "okay"; + + nfcmrvluart: nfcmrvluart@5 { + compatible = "mrvl,nfc-uart"; + + reset-n-io = <&gpio3 16 0>; + + hci-muxed; + flow-control; + } +}; diff --git a/drivers/nfc/nfcmrvl/Kconfig b/drivers/nfc/nfcmrvl/Kconfig index 5e18afd9abe2..796be2411440 100644 --- a/drivers/nfc/nfcmrvl/Kconfig +++ b/drivers/nfc/nfcmrvl/Kconfig @@ -21,3 +21,14 @@ config NFC_MRVL_USB Say Y here to compile support for Marvell NFC-over-USB driver into the kernel or say M to compile it as module. + +config NFC_MRVL_UART + tristate "Marvell NFC-over-UART driver" + depends on NFC_MRVL && NFC_NCI_UART + help + Marvell NFC-over-UART driver. + + This driver provides support for Marvell NFC-over-UART devices + + Say Y here to compile support for Marvell NFC-over-UART driver + into the kernel or say M to compile it as module. diff --git a/drivers/nfc/nfcmrvl/Makefile b/drivers/nfc/nfcmrvl/Makefile index 97a0de72dc01..775196274d1f 100644 --- a/drivers/nfc/nfcmrvl/Makefile +++ b/drivers/nfc/nfcmrvl/Makefile @@ -7,3 +7,6 @@ obj-$(CONFIG_NFC_MRVL) += nfcmrvl.o nfcmrvl_usb-y += usb.o obj-$(CONFIG_NFC_MRVL_USB) += nfcmrvl_usb.o + +nfcmrvl_uart-y += uart.o +obj-$(CONFIG_NFC_MRVL_UART) += nfcmrvl_uart.o diff --git a/drivers/nfc/nfcmrvl/nfcmrvl.h b/drivers/nfc/nfcmrvl/nfcmrvl.h index 214412bd6110..09780d57c9b8 100644 --- a/drivers/nfc/nfcmrvl/nfcmrvl.h +++ b/drivers/nfc/nfcmrvl/nfcmrvl.h @@ -43,6 +43,11 @@ #define NFCMRVL_HCI_OGF 0x81 #define NFCMRVL_HCI_OCF 0xFE +enum nfcmrvl_phy { + NFCMRVL_PHY_USB = 0, + NFCMRVL_PHY_UART = 1, +}; + struct nfcmrvl_private { @@ -61,6 +66,8 @@ struct nfcmrvl_private { void *drv_data; /* PHY device */ struct device *dev; + /* PHY type */ + enum nfcmrvl_phy phy; /* Low level driver ops */ struct nfcmrvl_if_ops *if_ops; }; diff --git a/drivers/nfc/nfcmrvl/uart.c b/drivers/nfc/nfcmrvl/uart.c new file mode 100644 index 000000000000..61442d6528a6 --- /dev/null +++ b/drivers/nfc/nfcmrvl/uart.c @@ -0,0 +1,225 @@ +/** + * Marvell NFC-over-UART driver + * + * Copyright (C) 2015, Marvell International Ltd. + * + * This software file (the "File") is distributed by Marvell International + * Ltd. under the terms of the GNU General Public License Version 2, June 1991 + * (the "License"). You may use, redistribute and/or modify this File in + * accordance with the terms and conditions of the License, a copy of which + * is available on the worldwide web at + * http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. + * + * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE + * ARE EXPRESSLY DISCLAIMED. The License provides additional details about + * this warranty disclaimer. + */ + +#include +#include +#include +#include +#include +#include "nfcmrvl.h" + +static unsigned int hci_muxed; +static unsigned int flow_control; +static unsigned int break_control; +static unsigned int reset_n_io; + +/* +** NFCMRVL NCI OPS +*/ + +static int nfcmrvl_uart_nci_open(struct nfcmrvl_private *priv) +{ + return 0; +} + +static int nfcmrvl_uart_nci_close(struct nfcmrvl_private *priv) +{ + return 0; +} + +static int nfcmrvl_uart_nci_send(struct nfcmrvl_private *priv, + struct sk_buff *skb) +{ + struct nci_uart *nu = priv->drv_data; + + return nu->ops.send(nu, skb); +} + +static struct nfcmrvl_if_ops uart_ops = { + .nci_open = nfcmrvl_uart_nci_open, + .nci_close = nfcmrvl_uart_nci_close, + .nci_send = nfcmrvl_uart_nci_send, +}; + +#ifdef CONFIG_OF + +static int nfcmrvl_uart_parse_dt(struct device_node *node, + struct nfcmrvl_platform_data *pdata) +{ + struct device_node *matched_node; + int ret; + + matched_node = of_find_compatible_node(node, NULL, "mrvl,nfc-uart"); + if (!matched_node) + return -ENODEV; + + ret = nfcmrvl_parse_dt(matched_node, pdata); + if (ret < 0) { + pr_err("Failed to get generic entries\n"); + return ret; + } + + if (of_find_property(matched_node, "flow-control", NULL)) + pdata->flow_control = 1; + else + pdata->flow_control = 0; + + if (of_find_property(matched_node, "break-control", NULL)) + pdata->break_control = 1; + else + pdata->break_control = 0; + + return 0; +} + +#else + +static int nfcmrvl_uart_parse_dt(struct device_node *node, + struct nfcmrvl_platform_data *pdata) +{ + return -ENODEV; +} + +#endif + +/* +** NCI UART OPS +*/ + +static int nfcmrvl_nci_uart_open(struct nci_uart *nu) +{ + struct nfcmrvl_private *priv; + struct nfcmrvl_platform_data *pdata = NULL; + struct nfcmrvl_platform_data config; + + /* + * Platform data cannot be used here since usually it is already used + * by low level serial driver. We can try to retrieve serial device + * and check if DT entries were added. + */ + + if (nu->tty->dev->parent && nu->tty->dev->parent->of_node) + if (nfcmrvl_uart_parse_dt(nu->tty->dev->parent->of_node, + &config) == 0) + pdata = &config; + + if (!pdata) { + pr_info("No platform data / DT -> fallback to module params\n"); + config.hci_muxed = hci_muxed; + config.reset_n_io = reset_n_io; + config.flow_control = flow_control; + config.break_control = break_control; + pdata = &config; + } + + priv = nfcmrvl_nci_register_dev(nu, &uart_ops, nu->tty->dev, pdata); + if (IS_ERR(priv)) + return PTR_ERR(priv); + + priv->phy = NFCMRVL_PHY_UART; + + nu->drv_data = priv; + nu->ndev = priv->ndev; + + /* Set BREAK */ + if (priv->config.break_control && nu->tty->ops->break_ctl) + nu->tty->ops->break_ctl(nu->tty, -1); + + return 0; +} + +static void nfcmrvl_nci_uart_close(struct nci_uart *nu) +{ + nfcmrvl_nci_unregister_dev((struct nfcmrvl_private *)nu->drv_data); +} + +static int nfcmrvl_nci_uart_recv(struct nci_uart *nu, struct sk_buff *skb) +{ + return nfcmrvl_nci_recv_frame((struct nfcmrvl_private *)nu->drv_data, + skb); +} + +static void nfcmrvl_nci_uart_tx_start(struct nci_uart *nu) +{ + struct nfcmrvl_private *priv = (struct nfcmrvl_private *)nu->drv_data; + + /* Remove BREAK to wake up the NFCC */ + if (priv->config.break_control && nu->tty->ops->break_ctl) { + nu->tty->ops->break_ctl(nu->tty, 0); + usleep_range(3000, 5000); + } +} + +static void nfcmrvl_nci_uart_tx_done(struct nci_uart *nu) +{ + struct nfcmrvl_private *priv = (struct nfcmrvl_private *)nu->drv_data; + + /* + ** To ensure that if the NFCC goes in DEEP SLEEP sate we can wake him + ** up. we set BREAK. Once we will be ready to send again we will remove + ** it. + */ + if (priv->config.break_control && nu->tty->ops->break_ctl) + nu->tty->ops->break_ctl(nu->tty, -1); +} + +static struct nci_uart nfcmrvl_nci_uart = { + .owner = THIS_MODULE, + .name = "nfcmrvl_uart", + .driver = NCI_UART_DRIVER_MARVELL, + .ops = { + .open = nfcmrvl_nci_uart_open, + .close = nfcmrvl_nci_uart_close, + .recv = nfcmrvl_nci_uart_recv, + .tx_start = nfcmrvl_nci_uart_tx_start, + .tx_done = nfcmrvl_nci_uart_tx_done, + } +}; + +/* +** Module init +*/ + +static int nfcmrvl_uart_init_module(void) +{ + return nci_uart_register(&nfcmrvl_nci_uart); +} + +static void nfcmrvl_uart_exit_module(void) +{ + nci_uart_unregister(&nfcmrvl_nci_uart); +} + +module_init(nfcmrvl_uart_init_module); +module_exit(nfcmrvl_uart_exit_module); + +MODULE_AUTHOR("Marvell International Ltd."); +MODULE_DESCRIPTION("Marvell NFC-over-UART"); +MODULE_LICENSE("GPL v2"); + +module_param(flow_control, uint, 0); +MODULE_PARM_DESC(flow_control, "Tell if UART needs flow control at init."); + +module_param(break_control, uint, 0); +MODULE_PARM_DESC(break_control, "Tell if UART driver must drive break signal."); + +module_param(hci_muxed, uint, 0); +MODULE_PARM_DESC(hci_muxed, "Tell if transport is muxed in HCI one."); + +module_param(reset_n_io, uint, 0); +MODULE_PARM_DESC(reset_n_io, "GPIO that is wired to RESET_N signal."); diff --git a/include/linux/platform_data/nfcmrvl.h b/include/linux/platform_data/nfcmrvl.h index 106cfe5ed589..ac91707dabcb 100644 --- a/include/linux/platform_data/nfcmrvl.h +++ b/include/linux/platform_data/nfcmrvl.h @@ -26,6 +26,15 @@ struct nfcmrvl_platform_data { unsigned int reset_n_io; /* Tell if transport is muxed in HCI one */ unsigned int hci_muxed; + + /* + * UART specific + */ + + /* Tell if UART needs flow control at init */ + unsigned int flow_control; + /* Tell if firmware supports break control for power management */ + unsigned int break_control; }; #endif /* _NFCMRVL_PTF_H_ */ diff --git a/net/nfc/nci/uart.c b/net/nfc/nci/uart.c index 70c279543074..2c48810af5bb 100644 --- a/net/nfc/nci/uart.c +++ b/net/nfc/nci/uart.c @@ -12,7 +12,6 @@ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE * ARE EXPRESSLY DISCLAIMED. The License provides additional details about * this warranty disclaimer. - */ /* Inspired (hugely) by HCI LDISC implementation in Bluetooth. -- cgit v1.2.3 From d5553cb05a041d7c31e4e70950ecbb4ee52049cb Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Thu, 4 Jun 2015 11:21:02 +0800 Subject: ARM: dts: zx: add an initial zx296702 dts and doc Add initial dts file and document for ZX296702 and board ZX296702-AD1. More peripherals will be added later. Signed-off-by: Jun Nie Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/zte.txt | 15 +++ .../devicetree/bindings/clock/zx296702-clk.txt | 35 ++++++ Documentation/devicetree/bindings/serial/pl011.txt | 2 +- .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zx296702-ad1.dts | 48 +++++++ arch/arm/boot/dts/zx296702.dtsi | 139 +++++++++++++++++++++ 7 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/zte.txt create mode 100644 Documentation/devicetree/bindings/clock/zx296702-clk.txt create mode 100644 arch/arm/boot/dts/zx296702-ad1.dts create mode 100644 arch/arm/boot/dts/zx296702.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt new file mode 100644 index 000000000000..3ff5c9e85c1c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.txt @@ -0,0 +1,15 @@ +ZTE platforms device tree bindings +--------------------------------------- + +- ZX296702 board: + Required root node properties: + - compatible = "zte,zx296702-ad1", "zte,zx296702" + +System management required properties: + - compatible = "zte,sysctrl" + +Low power management required properties: + - compatible = "zte,zx296702-pcu" + +Bus matrix required properties: + - compatible = "zte,zx-bus-matrix" diff --git a/Documentation/devicetree/bindings/clock/zx296702-clk.txt b/Documentation/devicetree/bindings/clock/zx296702-clk.txt new file mode 100644 index 000000000000..750442b65505 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zx296702-clk.txt @@ -0,0 +1,35 @@ +Device Tree Clock bindings for ZTE zx296702 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "zte,zx296702-topcrm-clk": + zx296702 top clock selection, divider and gating + + "zte,zx296702-lsp0crpm-clk" and + "zte,zx296702-lsp1crpm-clk": + zx296702 device level clock selection and gating + +- reg: Address and length of the register set + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h +for the full list of zx296702 clock IDs. + + +topclk: topcrm@0x09800000 { + compatible = "zte,zx296702-topcrm-clk"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; +}; + +uart0: serial@0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART0_PCLK>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8cb5a1..cbae3d9a0278 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,7 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be "arm,primecell", "arm,pl011" +- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart" - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..717ffd5a3563 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -211,3 +211,4 @@ xillybus Xillybus Ltd. xlnx Xilinx zyxel ZyXEL Communications Corp. zarlink Zarlink Semiconductor +zte ZTE Corp. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 86217db2937a..4814c6b96b67 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -660,6 +660,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6592-evb.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb endif always := $(dtb-y) diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts new file mode 100644 index 000000000000..081f980cfbe6 --- /dev/null +++ b/arch/arm/boot/dts/zx296702-ad1.dts @@ -0,0 +1,48 @@ + +/dts-v1/; + +#include "zx296702.dtsi" + +/ { + model = "ZTE ZX296702 AD1 Board"; + compatible = "zte,zx296702-ad1", "zte,zx296702"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory { + reg = <0x50000000 0x20000000>; + }; +}; + +&mmc0 { + num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&mmc1 { + num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi new file mode 100644 index 000000000000..d45c8fcd7ab4 --- /dev/null +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -0,0 +1,139 @@ + +#include "skeleton.dtsi" +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "zte,zx296702-smp"; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2cc>; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2cc>; + reg = <1>; + }; + }; + + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + matrix: bus-matrix@400000 { + compatible = "zte,zx-bus-matrix"; + reg = <0x00400000 0x1000>; + }; + + intc: interrupt-controller@00801000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00801000 0x1000>, + <0x00800100 0x100>; + }; + + global_timer: timer@008000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x00800200 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&topclk ZX296702_A9_PERIPHCLK>; + }; + + l2cc: l2-cache-controller@0x00c00000 { + compatible = "arm,pl310-cache"; + reg = <0x00c00000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + }; + + pcu: pcu@0xa0008000 { + compatible = "zte,zx296702-pcu"; + reg = <0xa0008000 0x1000>; + }; + + topclk: topclk@0x09800000 { + compatible = "zte,zx296702-topcrm-clk"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; + }; + + lsp1clk: lsp1clk@0x09400000 { + compatible = "zte,zx296702-lsp1crpm-clk"; + reg = <0x09400000 0x1000>; + #clock-cells = <1>; + }; + + lsp0clk: lsp0clk@0x0b000000 { + compatible = "zte,zx296702-lsp0crpm-clk"; + reg = <0x0b000000 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART0_WCLK>; + status = "disabled"; + }; + + uart1: serial@0x09406000 { + compatible = "zte,zx296702-uart"; + reg = <0x09406000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART1_WCLK>; + status = "disabled"; + }; + + mmc0: mmc@0x09408000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x09408000 0x1000>; + interrupts = ; + fifo-depth = <32>; + clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>, + <&lsp1clk ZX296702_SDMMC0_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + mmc1: mmc@0x0b003000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0b003000 0x1000>; + interrupts = ; + fifo-depth = <32>; + clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>, + <&lsp0clk ZX296702_SDMMC1_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + sysctrl: sysctrl@0xa0007000 { + compatible = "zte,sysctrl", "syscon"; + reg = <0xa0007000 0x1000>; + }; + }; +}; -- cgit v1.2.3 From f60c8ba77dcea80af8facfd786a0d2c3ace86f3d Mon Sep 17 00:00:00 2001 From: Samuel Thibault Date: Mon, 16 Mar 2015 21:19:56 -0700 Subject: Input: export LEDs as class devices in sysfs This change creates a new input handler called "leds" that exports LEDs on input devices as standard LED class devices in sysfs and allows controlling their state via sysfs or via any of the standard LED triggers. This allows to re-purpose and reassign LDEs on the keyboards to represent states other than the standard keyboard states (CapsLock, NumLock, etc). The old API of controlling input LEDs by writing into /dev/input/eventX devices is still present and will take precedence over accessing via LEDs subsystem (i.e. it may override state set by a trigger). If input device is "grabbed" then requests coming through LED subsystem will be ignored. Signed-off-by: Samuel Thibault Tested-by: Pavel Machek Acked-by: Pavel Machek Signed-off-by: Dmitry Torokhov --- Documentation/leds/leds-class.txt | 3 - drivers/input/Kconfig | 13 +++ drivers/input/Makefile | 1 + drivers/input/input-leds.c | 212 ++++++++++++++++++++++++++++++++++++++ drivers/leds/Kconfig | 3 - 5 files changed, 226 insertions(+), 6 deletions(-) create mode 100644 drivers/input/input-leds.c (limited to 'Documentation') diff --git a/Documentation/leds/leds-class.txt b/Documentation/leds/leds-class.txt index 79699c200766..62261c04060a 100644 --- a/Documentation/leds/leds-class.txt +++ b/Documentation/leds/leds-class.txt @@ -2,9 +2,6 @@ LED handling under Linux ======================== -If you're reading this and thinking about keyboard leds, these are -handled by the input subsystem and the led class is *not* needed. - In its simplest form, the LED class just allows control of LEDs from userspace. LEDs appear in /sys/class/leds/. The maximum brightness of the LED is defined in max_brightness file. The brightness file will set the brightness diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index a11ff74a5127..a35532ec00e4 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -25,6 +25,19 @@ config INPUT if INPUT +config INPUT_LEDS + tristate "Export input device LEDs in sysfs" + depends on LEDS_CLASS + default INPUT + help + Say Y here if you would like to export LEDs on input devices + as standard LED class devices in sysfs. + + If unsure, say Y. + + To compile this driver as a module, choose M here: the + module will be called input-leds. + config INPUT_FF_MEMLESS tristate "Support for memoryless force-feedback devices" help diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 5ca3f631497f..0c9302ca9954 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_INPUT_POLLDEV) += input-polldev.o obj-$(CONFIG_INPUT_SPARSEKMAP) += sparse-keymap.o obj-$(CONFIG_INPUT_MATRIXKMAP) += matrix-keymap.o +obj-$(CONFIG_INPUT_LEDS) += input-leds.o obj-$(CONFIG_INPUT_MOUSEDEV) += mousedev.o obj-$(CONFIG_INPUT_JOYDEV) += joydev.o obj-$(CONFIG_INPUT_EVDEV) += evdev.o diff --git a/drivers/input/input-leds.c b/drivers/input/input-leds.c new file mode 100644 index 000000000000..074a65ed17bb --- /dev/null +++ b/drivers/input/input-leds.c @@ -0,0 +1,212 @@ +/* + * LED support for the input layer + * + * Copyright 2010-2015 Samuel Thibault + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_VT) +#define VT_TRIGGER(_name) .trigger = _name +#else +#define VT_TRIGGER(_name) .trigger = NULL +#endif + +static const struct { + const char *name; + const char *trigger; +} input_led_info[LED_CNT] = { + [LED_NUML] = { "numlock", VT_TRIGGER("kbd-numlock") }, + [LED_CAPSL] = { "capslock", VT_TRIGGER("kbd-capslock") }, + [LED_SCROLLL] = { "scrolllock", VT_TRIGGER("kbd-scrolllock") }, + [LED_COMPOSE] = { "compose" }, + [LED_KANA] = { "kana", VT_TRIGGER("kbd-kanalock") }, + [LED_SLEEP] = { "sleep" } , + [LED_SUSPEND] = { "suspend" }, + [LED_MUTE] = { "mute" }, + [LED_MISC] = { "misc" }, + [LED_MAIL] = { "mail" }, + [LED_CHARGING] = { "charging" }, +}; + +struct input_led { + struct led_classdev cdev; + struct input_handle *handle; + unsigned int code; /* One of LED_* constants */ +}; + +struct input_leds { + struct input_handle handle; + unsigned int num_leds; + struct input_led leds[]; +}; + +static enum led_brightness input_leds_brightness_get(struct led_classdev *cdev) +{ + struct input_led *led = container_of(cdev, struct input_led, cdev); + struct input_dev *input = led->handle->dev; + + return test_bit(led->code, input->led) ? cdev->max_brightness : 0; +} + +static void input_leds_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + struct input_led *led = container_of(cdev, struct input_led, cdev); + + input_inject_event(led->handle, EV_LED, led->code, !!brightness); +} + +static void input_leds_event(struct input_handle *handle, unsigned int type, + unsigned int code, int value) +{ +} + +static int input_leds_connect(struct input_handler *handler, + struct input_dev *dev, + const struct input_device_id *id) +{ + struct input_leds *leds; + unsigned int num_leds; + unsigned int led_code; + int led_no; + int error; + + num_leds = bitmap_weight(dev->ledbit, LED_CNT); + if (!num_leds) + return -ENXIO; + + leds = kzalloc(sizeof(*leds) + num_leds * sizeof(*leds->leds), + GFP_KERNEL); + if (!leds) + return -ENOMEM; + + leds->num_leds = num_leds; + + leds->handle.dev = dev; + leds->handle.handler = handler; + leds->handle.name = "leds"; + leds->handle.private = leds; + + error = input_register_handle(&leds->handle); + if (error) + goto err_free_mem; + + error = input_open_device(&leds->handle); + if (error) + goto err_unregister_handle; + + led_no = 0; + for_each_set_bit(led_code, dev->ledbit, LED_CNT) { + struct input_led *led = &leds->leds[led_no]; + + led->handle = &leds->handle; + led->code = led_code; + + if (WARN_ON(!input_led_info[led_code].name)) + continue; + + led->cdev.name = kasprintf(GFP_KERNEL, "%s::%s", + dev_name(&dev->dev), + input_led_info[led_code].name); + if (!led->cdev.name) { + error = -ENOMEM; + goto err_unregister_leds; + } + + led->cdev.max_brightness = 1; + led->cdev.brightness_get = input_leds_brightness_get; + led->cdev.brightness_set = input_leds_brightness_set; + led->cdev.default_trigger = input_led_info[led_code].trigger; + + error = led_classdev_register(&dev->dev, &led->cdev); + if (error) { + dev_err(&dev->dev, "failed to register LED %s: %d\n", + led->cdev.name, error); + kfree(led->cdev.name); + goto err_unregister_leds; + } + + led_no++; + } + + return 0; + +err_unregister_leds: + while (--led_no >= 0) { + struct input_led *led = &leds->leds[led_no]; + + led_classdev_unregister(&led->cdev); + kfree(led->cdev.name); + } + + input_close_device(&leds->handle); + +err_unregister_handle: + input_unregister_handle(&leds->handle); + +err_free_mem: + kfree(leds); + return error; +} + +static void input_leds_disconnect(struct input_handle *handle) +{ + struct input_leds *leds = handle->private; + int i; + + for (i = 0; i < leds->num_leds; i++) { + struct input_led *led = &leds->leds[i]; + + led_classdev_unregister(&led->cdev); + kfree(led->cdev.name); + } + + input_close_device(handle); + input_unregister_handle(handle); + + kfree(leds); +} + +static const struct input_device_id input_leds_ids[] = { + { + .flags = INPUT_DEVICE_ID_MATCH_EVBIT, + .evbit = { BIT_MASK(EV_LED) }, + }, + { }, +}; +MODULE_DEVICE_TABLE(input, input_leds_ids); + +static struct input_handler input_leds_handler = { + .event = input_leds_event, + .connect = input_leds_connect, + .disconnect = input_leds_disconnect, + .name = "leds", + .id_table = input_leds_ids, +}; + +static int __init input_leds_init(void) +{ + return input_register_handler(&input_leds_handler); +} +module_init(input_leds_init); + +static void __exit input_leds_exit(void) +{ + input_unregister_handler(&input_leds_handler); +} +module_exit(input_leds_exit); + +MODULE_AUTHOR("Samuel Thibault "); +MODULE_AUTHOR("Dmitry Torokhov "); +MODULE_DESCRIPTION("Input -> LEDs Bridge"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 25b320d64e26..95029dfd311a 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -11,9 +11,6 @@ menuconfig NEW_LEDS Say Y to enable Linux LED support. This allows control of supported LEDs from both userspace and optionally, by kernel events (triggers). - This is not related to standard keyboard LEDs which are controlled - via the input system. - if NEW_LEDS config LEDS_CLASS -- cgit v1.2.3 From b97cadee805e49e823ffd5ad692bb4a9bbda248e Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Tue, 26 May 2015 08:28:30 +0000 Subject: DT: hwspinlock: add the CSR atlas7 hwspinlock bindings document The Hardware Spinlock device on atlas7 provides hardware assistance for synchronization between the multiple processors in the system (dual Cortex-A7, CAN bus Cortex-M3 and audio DSP). This patch adds the DT bindings information for this hwspinlock module. Reviewed-by: Suman Anna Reviewed-by: Bjorn Andersson Signed-off-by: Wei Chen Signed-off-by: Barry Song Signed-off-by: Ohad Ben-Cohen --- .../devicetree/bindings/hwlock/sirf,hwspinlock.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt new file mode 100644 index 000000000000..9bb1240a68e0 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/sirf,hwspinlock.txt @@ -0,0 +1,28 @@ +SIRF Hardware spinlock device Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "sirf,hwspinlock" + +- reg : the register address of hwspinlock + +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwlock { + compatible = "sirf,hwspinlock"; + reg = <0x13240000 0x00010000>; + #hwlock-cells = <1>; + }; + +Example of hwlock users: + node { + ... + hwlocks = <&hwlock 2>; + ... + }; -- cgit v1.2.3 From c83b2f20fdde578bded3dfc4405c5db7a039c694 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Fri, 12 Jun 2015 10:15:49 +0100 Subject: iommu/vt-d: Only enable extended context tables if PASID is supported Although the extended tables are theoretically a completely orthogonal feature to PASID and anything else that *uses* the newly-available bits, some of the early hardware has problems even when all we do is enable them and use only the same bits that were in the old context tables. For now, there's no motivation to support extended tables unless we're going to use PASID support to do SVM. So just don't use them unless PASID support is advertised too. Also add a command-line bailout just in case later chips also have issues. The equivalent problem for PASID support has already been fixed with the upcoming VT-d spec update and commit bd00c606a ("iommu/vt-d: Change PASID support to bit 40 of Extended Capability Register"), because the problematic platforms use the old definition of the PASID-capable bit, which is now marked as reserved and meaningless. So with this change, we'll magically start using ECS again only when we see the new hardware advertising "hey, we have PASID support and we actually tested it this time" on bit 40. The VT-d hardware architect has promised that we are not going to have any reason to support ECS *without* PASID any time soon, and he'll make sure he checks with us before changing that. In the future, if hypothetical new features also use new bits in the context tables and can be seen on implementations *without* PASID support, we might need to add their feature bits to the ecs_enabled() macro. Signed-off-by: David Woodhouse --- Documentation/kernel-parameters.txt | 6 ++++++ drivers/iommu/intel-iommu.c | 18 +++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index f6befa9855c1..491bb15620fc 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1481,6 +1481,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. By default, super page will be supported if Intel IOMMU has the capability. With this option, super page will not be supported. + ecs_off [Default Off] + By default, extended context tables will be supported if + the hardware advertises that it has support both for the + extended tables themselves, and also PASID support. With + this option set, extended tables will not be used even + on hardware which claims to support them. intel_idle.max_cstate= [KNL,HW,ACPI,X86] 0 disables intel_idle and fall back on acpi_idle. diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 2ffe58969944..5ecfaf29933a 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -422,6 +422,14 @@ static int dmar_map_gfx = 1; static int dmar_forcedac; static int intel_iommu_strict; static int intel_iommu_superpage = 1; +static int intel_iommu_ecs = 1; + +/* We only actually use ECS when PASID support (on the new bit 40) + * is also advertised. Some early implementations — the ones with + * PASID support on bit 28 — have issues even when we *only* use + * extended root/context tables. */ +#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \ + ecap_pasid(iommu->ecap)) int intel_iommu_gfx_mapped; EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); @@ -465,6 +473,10 @@ static int __init intel_iommu_setup(char *str) printk(KERN_INFO "Intel-IOMMU: disable supported super page\n"); intel_iommu_superpage = 0; + } else if (!strncmp(str, "ecs_off", 7)) { + printk(KERN_INFO + "Intel-IOMMU: disable extended context table support\n"); + intel_iommu_ecs = 0; } str += strcspn(str, ","); @@ -669,7 +681,7 @@ static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu struct context_entry *context; u64 *entry; - if (ecap_ecs(iommu->ecap)) { + if (ecs_enabled(iommu)) { if (devfn >= 0x80) { devfn -= 0x80; entry = &root->hi; @@ -806,7 +818,7 @@ static void free_context_table(struct intel_iommu *iommu) if (context) free_pgtable_page(context); - if (!ecap_ecs(iommu->ecap)) + if (!ecs_enabled(iommu)) continue; context = iommu_context_addr(iommu, i, 0x80, 0); @@ -1141,7 +1153,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu) unsigned long flag; addr = virt_to_phys(iommu->root_entry); - if (ecap_ecs(iommu->ecap)) + if (ecs_enabled(iommu)) addr |= DMA_RTADDR_RTT; raw_spin_lock_irqsave(&iommu->register_lock, flag); -- cgit v1.2.3 From 85a4bfd895778960dc2d655087ac7ff442b6ab9e Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Fri, 5 Jun 2015 10:19:05 +0200 Subject: ASoC: simple card: Add mclk-fs property in dai-link Add mclk-fs ratio property per dai-link sub node. This will allow to manage several codecs with different ratio. Signed-off-by: Arnaud Pouliquen Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/simple-card.txt | 6 +++++- sound/soc/generic/simple-card.c | 18 +++++++++++++++--- 2 files changed, 20 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt index 73bf314f7240..cf3979eb3578 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-card.txt @@ -16,7 +16,8 @@ Optional properties: connection's sink, the second being the connection's source. - simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec - mclk. + mclk. When defined, mclk-fs property defined in + dai-link sub nodes are ignored. - simple-audio-card,hp-det-gpio : Reference to GPIO that signals when headphones are attached. - simple-audio-card,mic-det-gpio : Reference to GPIO that signals when @@ -55,6 +56,9 @@ Optional dai-link subnode properties: dai-link uses bit clock inversion. - frame-inversion : bool property. Add this if the dai-link uses frame clock inversion. +- mclk-fs : Multiplication factor between stream + rate and codec mclk, applied only for + the dai-link. For backward compatibility the frame-master and bitclock-master properties can be used as booleans in codec subnode to indicate if the diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index c87e58504a62..d5554939146e 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -26,6 +26,7 @@ struct simple_card_data { struct simple_dai_props { struct asoc_simple_dai cpu_dai; struct asoc_simple_dai codec_dai; + unsigned int mclk_fs; } *dai_props; unsigned int mclk_fs; int gpio_hp_det; @@ -76,11 +77,18 @@ static int asoc_simple_card_hw_params(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct simple_card_data *priv = snd_soc_card_get_drvdata(rtd->card); - unsigned int mclk; + struct simple_dai_props *dai_props = + &priv->dai_props[rtd - rtd->card->rtd]; + unsigned int mclk, mclk_fs = 0; int ret = 0; - if (priv->mclk_fs) { - mclk = params_rate(params) * priv->mclk_fs; + if (priv->mclk_fs) + mclk_fs = priv->mclk_fs; + else if (dai_props->mclk_fs) + mclk_fs = dai_props->mclk_fs; + + if (mclk_fs) { + mclk = params_rate(params) * mclk_fs; ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN); } @@ -313,6 +321,7 @@ static int asoc_simple_card_dai_link_of(struct device_node *node, char prop[128]; char *prefix = ""; int ret, cpu_args; + u32 val; /* For single DAI link & old style of DT node */ if (is_top_level_node) @@ -338,6 +347,9 @@ static int asoc_simple_card_dai_link_of(struct device_node *node, if (ret < 0) goto dai_link_of_err; + if (!of_property_read_u32(node, "mclk-fs", &val)) + dai_props->mclk_fs = val; + ret = asoc_simple_card_sub_parse_of(cpu, &dai_props->cpu_dai, &dai_link->cpu_of_node, &dai_link->cpu_dai_name, -- cgit v1.2.3 From 22a10bca280073f81e9e2d9fed6f90a3bcf00236 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 11 Jun 2015 17:37:03 -0700 Subject: regulator: Add system_load constraint Some regulators have a fixed load that isn't captured by consumers that the kernel knows about. Add a constraint to support this. Signed-off-by: Stephen Boyd Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 2 ++ drivers/regulator/core.c | 2 ++ drivers/regulator/of_regulator.c | 3 +++ include/linux/regulator/machine.h | 3 +++ 4 files changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index abb26b58c83e..553d2d0fe6d9 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -37,6 +37,8 @@ Optional properties: - regulator-initial-mode: initial operating mode. The set of possible operating modes depends on the capabilities of every hardware so each device binding documentation explains which values the regulator supports. +- regulator-system-load: Load in uA present on regulator that is not captured by + any consumer request. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 443eaab933fc..c8d5e2b05fdf 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -678,6 +678,8 @@ static int drms_uA_update(struct regulator_dev *rdev) list_for_each_entry(sibling, &rdev->consumer_list, list) current_uA += sibling->uA_load; + current_uA += rdev->constraints->system_load; + if (rdev->desc->ops->set_load) { /* set the optimum mode for our new total regulator load */ err = rdev->desc->ops->set_load(rdev, current_uA); diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c index 24e812c48d93..482a86f90839 100644 --- a/drivers/regulator/of_regulator.c +++ b/drivers/regulator/of_regulator.c @@ -95,6 +95,9 @@ static void of_get_regulation_constraints(struct device_node *np, } } + if (!of_property_read_u32(np, "regulator-system-load", &pval)) + constraints->system_load = pval; + for (i = 0; i < ARRAY_SIZE(regulator_states); i++) { switch (i) { case PM_SUSPEND_MEM: diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h index b07562e082c4..01526559c8c3 100644 --- a/include/linux/regulator/machine.h +++ b/include/linux/regulator/machine.h @@ -75,6 +75,7 @@ struct regulator_state { * * @min_uA: Smallest current consumers may set. * @max_uA: Largest current consumers may set. + * @system_load: Load that isn't captured by any consumer requests. * * @valid_modes_mask: Mask of modes which may be configured by consumers. * @valid_ops_mask: Operations which may be performed by consumers. @@ -112,6 +113,8 @@ struct regulation_constraints { int min_uA; int max_uA; + int system_load; + /* valid regulator operating modes for this machine */ unsigned int valid_modes_mask; -- cgit v1.2.3 From 23c779b9f9161d6568d3b2fca06e70ad182c480c Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 11 Jun 2015 17:37:04 -0700 Subject: regulator: Add pull down support Some regulators need to be configured to pull down a resistor when the regulator is disabled. Add an op (set_pull_down) and a DT property + constraint to support this. Signed-off-by: Stephen Boyd Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 1 + drivers/regulator/core.c | 8 ++++++++ drivers/regulator/of_regulator.c | 2 ++ include/linux/regulator/driver.h | 5 +++++ include/linux/regulator/machine.h | 2 ++ 5 files changed, 18 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index 553d2d0fe6d9..6c79fd70ab5a 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -39,6 +39,7 @@ Optional properties: documentation explains which values the regulator supports. - regulator-system-load: Load in uA present on regulator that is not captured by any consumer request. +- regulator-pull-down: Enable pull down resistor when the regulator is disabled. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index c8d5e2b05fdf..60fcfba52592 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1051,6 +1051,14 @@ static int set_machine_constraints(struct regulator_dev *rdev, } } + if (rdev->constraints->pull_down && ops->set_pull_down) { + ret = ops->set_pull_down(rdev); + if (ret < 0) { + rdev_err(rdev, "failed to set pull down\n"); + goto out; + } + } + print_constraints(rdev); return 0; out: diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c index 482a86f90839..c3433db0acda 100644 --- a/drivers/regulator/of_regulator.c +++ b/drivers/regulator/of_regulator.c @@ -67,6 +67,8 @@ static void of_get_regulation_constraints(struct device_node *np, if (!constraints->always_on) /* status change should be possible. */ constraints->valid_ops_mask |= REGULATOR_CHANGE_STATUS; + constraints->pull_down = of_property_read_bool(np, "regulator-pull-down"); + if (of_property_read_bool(np, "regulator-allow-bypass")) constraints->valid_ops_mask |= REGULATOR_CHANGE_BYPASS; diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index fffa688ac3a7..76144a337ff7 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -121,6 +121,9 @@ struct regulator_linear_range { * @set_suspend_mode: Set the operating mode for the regulator when the * system is suspended. * + * @set_pull_down: Configure the regulator to pull down when the regulator + * is disabled. + * * This struct describes regulator operations which can be implemented by * regulator chip drivers. */ @@ -187,6 +190,8 @@ struct regulator_ops { /* set regulator suspend operating mode (defined in consumer.h) */ int (*set_suspend_mode) (struct regulator_dev *, unsigned int mode); + + int (*set_pull_down) (struct regulator_dev *); }; /* diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h index 01526559c8c3..8ffb0619a03c 100644 --- a/include/linux/regulator/machine.h +++ b/include/linux/regulator/machine.h @@ -87,6 +87,7 @@ struct regulator_state { * applied. * @apply_uV: Apply the voltage constraint when initialising. * @ramp_disable: Disable ramp delay when initialising or when setting voltage. + * @pull_down: Enable pull down when regulator is disabled. * * @input_uV: Input voltage for regulator when supplied by another regulator. * @@ -141,6 +142,7 @@ struct regulation_constraints { unsigned boot_on:1; /* bootloader/firmware enabled regulator */ unsigned apply_uV:1; /* apply uV constraint if min == max */ unsigned ramp_disable:1; /* disable ramp delay */ + unsigned pull_down:1; /* pull down resistor when regulator off */ }; /** -- cgit v1.2.3 From 57f66b78860968fc7eddc9ce25f8e57f7e5000bd Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 11 Jun 2015 17:37:05 -0700 Subject: regulator: Add soft start support Some regulators support a "soft start" feature where the voltage ramps up slowly when the regulator is enabled. Add an op (set_soft_start) and a DT property + constraint to support this. Signed-off-by: Stephen Boyd Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 1 + drivers/regulator/core.c | 8 ++++++++ drivers/regulator/of_regulator.c | 3 +++ include/linux/regulator/driver.h | 2 ++ include/linux/regulator/machine.h | 1 + 5 files changed, 15 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index 6c79fd70ab5a..4b1df61ccbd7 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -19,6 +19,7 @@ Optional properties: design requires. This property describes the total system ramp time required due to the combination of internal ramping of the regulator itself, and board design issues such as trace capacitance and load on the supply. +- regulator-soft-start: Enable soft start so that voltage ramps slowly - regulator-state-mem sub-root node for Suspend-to-RAM mode : suspend to memory, the device goes to sleep, but all data stored in memory, only some external interrupt can wake the device. diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 60fcfba52592..6dfb2d6c19ae 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1059,6 +1059,14 @@ static int set_machine_constraints(struct regulator_dev *rdev, } } + if (rdev->constraints->soft_start && ops->set_soft_start) { + ret = ops->set_soft_start(rdev); + if (ret < 0) { + rdev_err(rdev, "failed to set soft start\n"); + goto out; + } + } + print_constraints(rdev); return 0; out: diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c index c3433db0acda..207da037cd2d 100644 --- a/drivers/regulator/of_regulator.c +++ b/drivers/regulator/of_regulator.c @@ -84,6 +84,9 @@ static void of_get_regulation_constraints(struct device_node *np, if (!ret) constraints->enable_time = pval; + constraints->soft_start = of_property_read_bool(np, + "regulator-soft-start"); + if (!of_property_read_u32(np, "regulator-initial-mode", &pval)) { if (desc && desc->of_map_mode) { ret = desc->of_map_mode(pval); diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index 76144a337ff7..e0635d0894aa 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -161,6 +161,8 @@ struct regulator_ops { unsigned int old_selector, unsigned int new_selector); + int (*set_soft_start) (struct regulator_dev *); + /* report regulator status ... most other accessors report * control inputs, this reports results of combining inputs * from Linux (and other sources) with the actual load. diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h index 8ffb0619a03c..7f7d0a3fe1e1 100644 --- a/include/linux/regulator/machine.h +++ b/include/linux/regulator/machine.h @@ -142,6 +142,7 @@ struct regulation_constraints { unsigned boot_on:1; /* bootloader/firmware enabled regulator */ unsigned apply_uV:1; /* apply uV constraint if min == max */ unsigned ramp_disable:1; /* disable ramp delay */ + unsigned soft_start:1; /* ramp voltage slowly */ unsigned pull_down:1; /* pull down resistor when regulator off */ }; -- cgit v1.2.3 From 36e4f839de59b6216a16cdf5c1d3263f4dbd9421 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 11 Jun 2015 17:37:06 -0700 Subject: regulator: Add input current limit support Some regulators can limit their input current (typically annotated as ilim). Add an op (set_input_current_limit) and a DT property + constraint to support this. Signed-off-by: Stephen Boyd Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/regulator.txt | 1 + drivers/regulator/core.c | 9 +++++++++ drivers/regulator/of_regulator.c | 4 ++++ include/linux/regulator/driver.h | 3 +++ include/linux/regulator/machine.h | 2 ++ 5 files changed, 19 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index 4b1df61ccbd7..e29db73e55f4 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt @@ -7,6 +7,7 @@ Optional properties: - regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops - regulator-min-microamp: smallest current consumers may set - regulator-max-microamp: largest current consumers may set +- regulator-input-current-limit-microamp: maximum input current regulator allows - regulator-always-on: boolean, regulator should never be disabled - regulator-boot-on: bootloader/firmware enabled regulator - regulator-allow-bypass: allow the regulator to go into bypass mode diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 6dfb2d6c19ae..ba565416d1d0 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1008,6 +1008,15 @@ static int set_machine_constraints(struct regulator_dev *rdev, if (ret != 0) goto out; + if (rdev->constraints->ilim_uA && ops->set_input_current_limit) { + ret = ops->set_input_current_limit(rdev, + rdev->constraints->ilim_uA); + if (ret < 0) { + rdev_err(rdev, "failed to set input limit\n"); + goto out; + } + } + /* do we need to setup our suspend state */ if (rdev->constraints->initial_state) { ret = suspend_prepare(rdev, rdev->constraints->initial_state); diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c index 207da037cd2d..f025c1047d0a 100644 --- a/drivers/regulator/of_regulator.c +++ b/drivers/regulator/of_regulator.c @@ -58,6 +58,10 @@ static void of_get_regulation_constraints(struct device_node *np, if (!of_property_read_u32(np, "regulator-max-microamp", &pval)) constraints->max_uA = pval; + if (!of_property_read_u32(np, "regulator-input-current-limit-microamp", + &pval)) + constraints->ilim_uA = pval; + /* Current change possible? */ if (constraints->min_uA != constraints->max_uA) constraints->valid_ops_mask |= REGULATOR_CHANGE_CURRENT; diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index e0635d0894aa..125264f8be93 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -91,6 +91,7 @@ struct regulator_linear_range { * @set_current_limit: Configure a limit for a current-limited regulator. * The driver should select the current closest to max_uA. * @get_current_limit: Get the configured limit for a current-limited regulator. + * @set_input_current_limit: Configure an input limit. * * @set_mode: Set the configured operating mode for the regulator. * @get_mode: Get the configured operating mode for the regulator. @@ -145,6 +146,8 @@ struct regulator_ops { int min_uA, int max_uA); int (*get_current_limit) (struct regulator_dev *); + int (*set_input_current_limit) (struct regulator_dev *, int lim_uA); + /* enable/disable regulator */ int (*enable) (struct regulator_dev *); int (*disable) (struct regulator_dev *); diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h index 7f7d0a3fe1e1..85a3b457de51 100644 --- a/include/linux/regulator/machine.h +++ b/include/linux/regulator/machine.h @@ -75,6 +75,7 @@ struct regulator_state { * * @min_uA: Smallest current consumers may set. * @max_uA: Largest current consumers may set. + * @ilim_uA: Maximum input current. * @system_load: Load that isn't captured by any consumer requests. * * @valid_modes_mask: Mask of modes which may be configured by consumers. @@ -113,6 +114,7 @@ struct regulation_constraints { /* current output range (inclusive) - for current control */ int min_uA; int max_uA; + int ilim_uA; int system_load; -- cgit v1.2.3 From fe8e48ad3c620093b2c9064259558bdcba9a76fa Mon Sep 17 00:00:00 2001 From: Ranjit Waghmode Date: Wed, 10 Jun 2015 16:08:20 +0530 Subject: spi: zynq: Add DT bindings documentation for Zynq Ultrascale+ MPSoC GQSPI controller Add bindings documentation for GQSPI controller driver used by Zynq Ultrascale+ MPSoC Signed-off-by: Ranjit Waghmode Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-zynqmp-qspi.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt new file mode 100644 index 000000000000..c8f50e5cf70b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt @@ -0,0 +1,26 @@ +Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings +------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynqmp-qspi-1.0". +- reg : Physical base address and size of GQSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller. +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&misc_clk &misc_clk>; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>; + }; -- cgit v1.2.3 From b07d496177cd3bc4b70fb8a5e85ede24cb403a11 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Sat, 13 Jun 2015 00:23:21 +0900 Subject: Doc: networking: Fix URL for wiki.wireshark.org in udplite.txt This patch fix URL (http to https) for wiki.wireshark.org. Signed-off-by: Masanari Iida Signed-off-by: David S. Miller --- Documentation/networking/udplite.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/networking/udplite.txt b/Documentation/networking/udplite.txt index d727a3829100..53a726855e49 100644 --- a/Documentation/networking/udplite.txt +++ b/Documentation/networking/udplite.txt @@ -20,7 +20,7 @@ files/UDP-Lite-HOWTO.txt o The Wireshark UDP-Lite WiKi (with capture files): - http://wiki.wireshark.org/Lightweight_User_Datagram_Protocol + https://wiki.wireshark.org/Lightweight_User_Datagram_Protocol o The Protocol Spec, RFC 3828, http://www.ietf.org/rfc/rfc3828.txt -- cgit v1.2.3 From c5ab1f7faaba2d7f30f87bea2f0b5cf4b958fd2f Mon Sep 17 00:00:00 2001 From: Dmitry Kalinkin Date: Thu, 28 May 2015 15:06:58 +0300 Subject: Documentation: mention vme_master_mmap() in VME API Signed-off-by: Dmitry Kalinkin Cc: Igor Alekseev Signed-off-by: Greg Kroah-Hartman --- Documentation/vme_api.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/vme_api.txt b/Documentation/vme_api.txt index ffe6e22a2ccd..ca5b82797f6c 100644 --- a/Documentation/vme_api.txt +++ b/Documentation/vme_api.txt @@ -171,6 +171,12 @@ This functions by reading the offset, applying the mask. If the bits selected in the mask match with the values of the corresponding bits in the compare field, the value of swap is written the specified offset. +Parts of a VME window can be mapped into user space memory using the following +function: + + int vme_master_mmap(struct vme_resource *resource, + struct vm_area_struct *vma) + Slave windows ============= -- cgit v1.2.3 From 6cf600aba1b7fcb6ec67a1dcea3a3c2391eeb331 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 12 Jun 2015 18:04:17 +0900 Subject: serial: 8250_uniphier: add bindings document for UniPhier UART This is binding information for the UniPhier on-chip UART driver (drivers/tty/serial/8250/8250_uniphier.c). Signed-off-by: Masahiro Yamada Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/uniphier-uart.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/uniphier-uart.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/uniphier-uart.txt b/Documentation/devicetree/bindings/serial/uniphier-uart.txt new file mode 100644 index 000000000000..0b3892a7a528 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/uniphier-uart.txt @@ -0,0 +1,23 @@ +UniPhier UART controller + +Required properties: +- compatible: should be "socionext,uniphier-uart". +- reg: offset and length of the register set for the device. +- interrupts: a single interrupt specifier. +- clocks: phandle to the input clock. + +Optional properties: +- fifo-size: the RX/TX FIFO size. Defaults to 64 if not specified. + +Example: + aliases { + serial0 = &serial0; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; -- cgit v1.2.3 From 3e20c31a222e31aa681bdf6a62d7bc9b82af60b7 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 4 Jun 2015 10:57:00 +0300 Subject: Doc: tty.txt: remove mention of the BKL The BKL is long gone, no need to kill the dead. Signed-off-by: Baruch Siach Signed-off-by: Greg Kroah-Hartman --- Documentation/serial/tty.txt | 3 --- 1 file changed, 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/serial/tty.txt b/Documentation/serial/tty.txt index dbe6623fed1c..973c8ad3f959 100644 --- a/Documentation/serial/tty.txt +++ b/Documentation/serial/tty.txt @@ -4,9 +4,6 @@ Your guide to the ancient and twisted locking policies of the tty layer and the warped logic behind them. Beware all ye who read on. -FIXME: still need to work out the full set of BKL assumptions and document -them so they can eventually be killed off. - Line Discipline --------------- -- cgit v1.2.3 From 71206b9f8120eb513c621d4f31906577bb658df3 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 4 Jun 2015 10:56:59 +0300 Subject: Doc: serial-rs485.txt: update RS485 driver interface Since commit a5f276f10ff7 (serial_core: Handle TIOC[GS]RS485 ioctls., 2014-11-06) serial_core handles RS485 ioctls. Drivers only need to implement the rs485_config callback. Update serial-rs485.txt to reflect these changes. Signed-off-by: Baruch Siach Signed-off-by: Greg Kroah-Hartman --- Documentation/serial/serial-rs485.txt | 50 ++++------------------------------- 1 file changed, 5 insertions(+), 45 deletions(-) (limited to 'Documentation') diff --git a/Documentation/serial/serial-rs485.txt b/Documentation/serial/serial-rs485.txt index 39dac95422a3..2253b8b45a74 100644 --- a/Documentation/serial/serial-rs485.txt +++ b/Documentation/serial/serial-rs485.txt @@ -33,50 +33,10 @@ the values given by the device tree. Any driver for devices capable of working both as RS232 and RS485 should - provide at least the following ioctls: - - - TIOCSRS485 (typically associated with number 0x542F). This ioctl is used - to enable/disable RS485 mode from user-space - - - TIOCGRS485 (typically associated with number 0x542E). This ioctl is used - to get RS485 mode from kernel-space (i.e., driver) to user-space. - - In other words, the serial driver should contain a code similar to the next - one: - - static struct uart_ops atmel_pops = { - /* ... */ - .ioctl = handle_ioctl, - }; - - static int handle_ioctl(struct uart_port *port, - unsigned int cmd, - unsigned long arg) - { - struct serial_rs485 rs485conf; - - switch (cmd) { - case TIOCSRS485: - if (copy_from_user(&rs485conf, - (struct serial_rs485 *) arg, - sizeof(rs485conf))) - return -EFAULT; - - /* ... */ - break; - - case TIOCGRS485: - if (copy_to_user((struct serial_rs485 *) arg, - ..., - sizeof(rs485conf))) - return -EFAULT; - /* ... */ - break; - - /* ... */ - } - } - + implement the rs485_config callback in the uart_port structure. The + serial_core calls rs485_config to do the device specific part in response + to TIOCSRS485 and TIOCGRS485 ioctls (see below). The rs485_config callback + receives a pointer to struct serial_rs485. 4. USAGE FROM USER-LEVEL @@ -85,7 +45,7 @@ #include - /* Driver-specific ioctls: */ + /* RS485 ioctls: */ #define TIOCGRS485 0x542E #define TIOCSRS485 0x542F -- cgit v1.2.3 From f44c21ff6d2dc76957ddbf26fdf442ee5a9cf3c0 Mon Sep 17 00:00:00 2001 From: Alexandru M Stan Date: Tue, 9 Jun 2015 13:04:48 +0200 Subject: mfd: cros_ec: spi: Add a DT property to delay asserting the CS Some ECs need a little time for waking up before they can accept SPI data at a high speed. Add a "google,cros-ec-spi-pre-delay" property to the DT binding to configure this. If this property isn't set, then no delay will be added. However, if set it will cause a delay equal to the value passed to it to be inserted at the beginning of a transaction. Signed-off-by: Alexandru M Stan Reviewed-by: Doug Anderson Signed-off-by: Chris Zhong Signed-off-by: Javier Martinez Canillas Tested-by: Heiko Stuebner Acked-by: Lee Jones Acked-by: Olof Johansson Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/cros-ec.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt b/Documentation/devicetree/bindings/mfd/cros-ec.txt index 8009c3d87f33..1777916e9e28 100644 --- a/Documentation/devicetree/bindings/mfd/cros-ec.txt +++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt @@ -18,6 +18,10 @@ Required properties (SPI): - reg: SPI chip select Optional properties (SPI): +- google,cros-ec-spi-pre-delay: Some implementations of the EC need a little + time to wake up from sleep before they can receive SPI transfers at a high + clock rate. This property specifies the delay, in usecs, between the + assertion of the CS to the start of the first clock pulse. - google,cros-ec-spi-msg-delay: Some implementations of the EC require some additional processing time in order to accept new transactions. If the delay between transactions is not long enough the EC may not be able to respond -- cgit v1.2.3 From 812d6f6345d88632c11aeb602ef26f4616dabfa0 Mon Sep 17 00:00:00 2001 From: Haikun Wang Date: Mon, 15 Jun 2015 19:49:01 +0800 Subject: spi: spi-fsl-dspi: Update DT binding documentation DSPI driver has been updated and support more compatible strings. This patch update the DT binding documentation. Signed-off-by: Haikun Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index 70af78a9185e..fa77f874e321 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -1,7 +1,7 @@ ARM Freescale DSPI controller Required properties: -- compatible : "fsl,vf610-dspi" +- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt - clocks: from common clock binding: handle to dspi clock. -- cgit v1.2.3 From b4ad7baa01970d2c5096fbbcb0c593e199c6f18b Mon Sep 17 00:00:00 2001 From: Scott Feldman Date: Sun, 14 Jun 2015 11:33:11 -0700 Subject: bridge: del external_learned fdbs from device on flush or ageout We need to delete from offload the device externally learnded fdbs when any one of these events happen: 1) Bridge ages out fdb. (When bridge is doing ageing vs. device doing ageing. If device is doing ageing, it would send SWITCHDEV_FDB_DEL directly). 2) STP state change flushes fdbs on port. 3) User uses sysfs interface to flush fdbs from bridge or bridge port: echo 1 >/sys/class/net/BR_DEV/bridge/flush echo 1 >/sys/class/net/BR_PORT/brport/flush 4) Offload driver send event SWITCHDEV_FDB_DEL to delete fdb entry. For rocker, we can now get called to delete fdb entry in wait and nowait contexts, so set NOWAIT flag when deleting fdb entry. Signed-off-by: Scott Feldman Signed-off-by: David S. Miller --- Documentation/networking/switchdev.txt | 11 ++--------- drivers/net/ethernet/rocker/rocker.c | 2 +- net/bridge/br_fdb.c | 17 +++++++++++++++++ 3 files changed, 20 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/switchdev.txt b/Documentation/networking/switchdev.txt index da82cd75a4f6..c5d7ade10ff2 100644 --- a/Documentation/networking/switchdev.txt +++ b/Documentation/networking/switchdev.txt @@ -251,15 +251,8 @@ out stale FDB entries. To keep an FDB entry "alive", the driver should refresh the FDB entry by calling call_switchdev_notifiers(SWITCHDEV_FDB_ADD, ...). The notification will reset the FDB entry's last-used time to now. The driver should rate limit refresh notifications, for example, no more than once a -second. If the FDB entry expires, ndo_fdb_del is called to remove entry from -the device. XXX: this last part isn't currently correct: ndo_fdb_del isn't -called, so the stale entry remains in device...this need to get fixed. - -FDB Flush -^^^^^^^^^ - -XXX: Unimplemented. Need to support FDB flush by bridge driver for port and -remove both static and learned FDB entries. +second. If the FDB entry expires, fdb_delete is called to remove entry from +the device. STP State Change on Port ^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/drivers/net/ethernet/rocker/rocker.c b/drivers/net/ethernet/rocker/rocker.c index a06b93da6283..d4ec660bb3b7 100644 --- a/drivers/net/ethernet/rocker/rocker.c +++ b/drivers/net/ethernet/rocker/rocker.c @@ -4392,7 +4392,7 @@ static int rocker_port_fdb_del(struct rocker_port *rocker_port, const struct switchdev_obj_fdb *fdb) { __be16 vlan_id = rocker_port_vid_to_vlan(rocker_port, fdb->vid, NULL); - int flags = ROCKER_OP_FLAG_REMOVE; + int flags = ROCKER_OP_FLAG_NOWAIT | ROCKER_OP_FLAG_REMOVE; if (!rocker_port_is_bridged(rocker_port)) return -EINVAL; diff --git a/net/bridge/br_fdb.c b/net/bridge/br_fdb.c index 13949a71591d..be84b7e5a3da 100644 --- a/net/bridge/br_fdb.c +++ b/net/bridge/br_fdb.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "br_private.h" static struct kmem_cache *br_fdb_cache __read_mostly; @@ -130,11 +131,27 @@ static void fdb_del_hw_addr(struct net_bridge *br, const unsigned char *addr) } } +static void fdb_del_external_learn(struct net_bridge_fdb_entry *f) +{ + struct switchdev_obj obj = { + .id = SWITCHDEV_OBJ_PORT_FDB, + .u.fdb = { + .addr = f->addr.addr, + .vid = f->vlan_id, + }, + }; + + switchdev_port_obj_del(f->dst->dev, &obj); +} + static void fdb_delete(struct net_bridge *br, struct net_bridge_fdb_entry *f) { if (f->is_static) fdb_del_hw_addr(br, f->addr.addr); + if (f->added_by_external_learn) + fdb_del_external_learn(f); + hlist_del_rcu(&f->hlist); fdb_notify(br, f, RTM_DELNEIGH); call_rcu(&f->rcu, fdb_rcu_free); -- cgit v1.2.3 From 4c31d50d3ee67b4fdc1824ed51b6f707681d0136 Mon Sep 17 00:00:00 2001 From: Chaotian Jing Date: Mon, 15 Jun 2015 19:20:47 +0800 Subject: mmc: dt-bindings: add Mediatek MMC bindings Document the device-tree binding of Mediatek MMC host Signed-off-by: Chaotian Jing Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt new file mode 100644 index 000000000000..a1adfa495ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -0,0 +1,32 @@ +* MTK MMC controller + +The MTK MSDC can act as a MMC controller +to support MMC, SD, and SDIO types of memory cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the msdc driver. + +Required properties: +- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc" +- interrupts: Should contain MSDC interrupt number +- clocks: MSDC source clock, HCLK +- clock-names: "source", "hclk" +- pinctrl-names: should be "default", "state_uhs" +- pinctrl-0: should contain default/high speed pin ctrl +- pinctrl-1: should contain uhs mode pin ctrl +- vmmc-supply: power to the Core +- vqmmc-supply: power to the IO + +Examples: +mmc0: mmc@11230000 { + compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x108>; + interrupts = ; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; +}; -- cgit v1.2.3 From 43c4436e2f1890a7b28dc0f0d901866cda99a08c Mon Sep 17 00:00:00 2001 From: Hisashi Nakamura Date: Sat, 6 Jun 2015 01:34:48 +0300 Subject: pinctrl: sh-pfc: add R8A7794 PFC support Add PFC support for the R8A7794 SoC including pin groups for some on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF... Sergei: squashed together several patches, fixed the MLB_CLK typo, added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin group names, removed stray new line and fixed typos in the comments in the pinmux_config_regs[] initializer, removed the platform device ID, took into account limited number of signals in the GPIO1/5/6 controllers, added reasonable and removed unreasonable copyrights, modified the bindings document, renamed, added changelog. Changes in version 5: - resolved rejects, refreshed the patch; - added Laurent Pinchart's ACK. Changes in version 4: - reused the PORT_GP_26() macro to #define PORT_GP_28(). Changes in version 3: - removed the platform device ID; - added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the CPU_ALL_PORT() macro. Changes in version 2: - rebased the patch. Signed-off-by: Hisashi Nakamura Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/core.h | 1 + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 4008 ++++++++++++++++++++ 6 files changed, 4022 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7794.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 6bcf851b6779..51cee44fc140 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -18,6 +18,7 @@ Required Properties: - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. + - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 5d570fdf6065..8e024c9c9115 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -60,6 +60,11 @@ config PINCTRL_PFC_R8A7793 depends on ARCH_R8A7793 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7794 + def_bool y + depends on ARCH_R8A7794 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 11eefcb71ec9..ea2a60ef122a 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o +obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 96556362b28f..865d235612c5 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -487,6 +487,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7793_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7794 + { + .compatible = "renesas,pfc-r8a7794", + .data = &r8a7794_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index b151b771e876..4c3c37bf7161 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -72,6 +72,7 @@ extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; +extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c new file mode 100644 index 000000000000..0e2686a2093c --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -0,0 +1,4008 @@ +/* + * r8a7794 processor support - PFC hardware block. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2015 Renesas Solutions Corp. + * Copyright (C) 2015 Cogent Embedded, Inc., + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include +#include + +#include "core.h" +#include "sh_pfc.h" + +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + +#define PORT_GP_28(bank, fn, sfx) \ + PORT_GP_26(bank, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_26(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_28(5, fn, sfx), \ + PORT_GP_26(6, fn, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, + FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, + FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, + FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, + FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, + FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, + FN_IP2_17_16, + + /* GPSR1 */ + FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, + FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, + FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, + FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, + FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, + + /* GPSR2 */ + FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, + FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, + FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, + FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, + FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, + FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, + FN_IP6_5_4, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, + FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, + FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, + FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, + FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, + FN_IP8_22_20, + + /* GPSR4 */ + FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, + FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, + FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, + FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, + FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, + + /* GPSR5 */ + FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, + FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, + FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, + FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, + FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, + + /* GPSR6 */ + FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, + FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, + FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, + FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, + FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, + + /* IPSR0 */ + FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, + FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, + FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, + FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, + FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, + FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, + FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, + FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, + + /* IPSR1 */ + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1, + FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX, + FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, + FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, + FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13, + FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD, + FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0, + FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK, + FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, + FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, + + /* IPSR2 */ + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD, + FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10, + FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, + FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2, + FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, + FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16, + FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C, + FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, + FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, + FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, + FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1, + + /* IPSR3 */ + FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5, + FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3, + FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8, + FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, + FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0, + FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, + FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, + FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N, + FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK, + FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, + FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, + FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B, + FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N, + + /* IPSR4 */ + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0, + FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0, + FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1, + FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19, + FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5, + FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, + FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8, + FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9, + FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10, + FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4, + FN_LCDOUT12, FN_CC50_STATE12, + + /* IPSR5 */ + FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14, + FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0, + FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, + FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, + FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, + FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4, + FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6, + FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0, + FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, + FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, + + /* IPSR6 */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, + FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, + FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, + FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, + FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, + FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, + FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, + FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, + FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, + FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, + FN_ADIDATA, FN_AD_DI, + + /* IPSR7 */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, + FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, + FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, + FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, + FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, + FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, + FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, + FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, + FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, + + /* IPSR8 */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, + FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, + FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, + FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, + FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, + FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, + FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, + FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, + FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, + FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + + /* IPSR9 */ + FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B, + FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0, + FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC, + FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1, + FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B, + FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, + FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL, + FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, + FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, + FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, + FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, + FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, + FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, + FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, + + /* IPSR10 */ + FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0, + FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, + FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL, + FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, + FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, + FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1, + FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4, + FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, + FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, + FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, + FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD, + FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, + FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, + FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA, + FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9, + FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, + + /* IPSR11 */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, + FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, + FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, + FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, + FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, + FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, + FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, + FN_ADICLK_B, FN_AD_CLK_B, + + /* IPSR12 */ + FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, + FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B, + FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3, + FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, + FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4, + FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT, + FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B, + FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, + FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, + FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, + FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, + FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, + FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, + FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B, + + /* IPSR13 */ + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, + FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, + FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, + FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N, + FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, + FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9, + FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, + FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, + FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, + FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, + FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC, + FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C, + FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, + FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B, + FN_FMIN_E, FN_RDS_DATA_D, + + /* MOD_SEL */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, + FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, + FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, + FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, + FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, + FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, + FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, + FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, + FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, + FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, + FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, + + /* MOD_SEL2 */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, + FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, + FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, + FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, + FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, + FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, + FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, + FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, + FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, + FN_SEL_RDS_2, FN_SEL_RDS_3, + + /* MOD_SEL3 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, + FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, + FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, + FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, + FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + + SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, + SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, + + SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, + SD1_DATA2_MARK, SD1_DATA3_MARK, + + /* IPSR0 */ + SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, + MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, + SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, + SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, + MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, + CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, + CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, + SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, + SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, + SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, + + /* IPSR1 */ + D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK, + TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, + D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK, + HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, + D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, + D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, + D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK, + D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK, + IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK, + SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK, + A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK, + SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, + + /* IPSR2 */ + A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK, + SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, + A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK, + IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, + A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, + HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, + HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK, + HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK, + TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, + CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK, + SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK, + MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK, + SPCLK_MARK, MOUT1_MARK, + + /* IPSR3 */ + A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK, + MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK, + ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, + ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, + VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, + TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK, + PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK, + TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK, + SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK, + BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK, + SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK, + FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK, + SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK, + FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK, + PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK, + ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, + + /* IPSR4 */ + EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK, + DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, + CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, + I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK, + CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK, + DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK, + LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK, + CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK, + DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, + CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, + I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK, + CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK, + DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK, + + /* IPSR5 */ + DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK, + LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK, + CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, + I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK, + LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK, + CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK, + DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK, + LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK, + CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK, + DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK, + QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK, + QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, + CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, + CC50_STATE27_MARK, + + /* IPSR6 */ + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, + DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, + CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, + AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, + VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, + AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, + VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, + AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, + I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, + VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, + AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, + IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, + I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, + VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, + ADIDATA_MARK, AD_DI_MARK, + + /* IPSR7 */ + ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, + MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, + AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, + CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, + ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, + AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, + MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, + ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, + SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, + IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, + VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, + SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, + AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, + SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, + DREQ0_N_MARK, SCIFB1_RXD_MARK, + + /* IPSR8 */ + ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, + AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, + I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, + HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, + AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, + SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, + HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, + AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, + HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, + I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, + AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, + SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, + CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, + DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, + TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, + I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, + FMCLK_C_MARK, RDS_CLK_MARK, + + /* IPSR9 */ + MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, + RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK, + MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK, + TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, + RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, + TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK, + MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, + RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK, + I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, + I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK, + PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK, + VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, + DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK, + CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, + DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK, + SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, + CAN_TXCLK_MARK, CC50_STATE34_MARK, + + /* IPSR10 */ + SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, + CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK, + DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK, + SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, + USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK, + IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK, + CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK, + DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK, + CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, + DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK, + CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, + DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK, + RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, + DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK, + RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, + AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK, + SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK, + SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK, + + /* IPSR11 */ + SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, + CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, + DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, + SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, + SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, + SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, + DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, + DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, + AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, + MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, + PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, + ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, + PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, + + /* IPSR12 */ + SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, + AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK, + SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK, + SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, + CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, + IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK, + SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK, + SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, + DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, + IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK, + ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, + VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, + SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, + ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, + VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK, + + /* IPSR13 */ + SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, + SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK, + HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK, + ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK, + PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK, + ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, + VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK, + SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, + ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, + VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK, + AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, + TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, + AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, + TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK, + AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, + TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, + PINMUX_MARK_END, +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(WE0_N_MARK, FN_WE0_N), + PINMUX_DATA(WE1_N_MARK, FN_WE1_N), + PINMUX_DATA(DACK0_MARK, FN_DACK0), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), + PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), + PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), + PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), + PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), + PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), + PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), + PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), + PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), + PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), + PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), + PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), + PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), + PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_0, SD1_CD), + PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), + PINMUX_IPSR_DATA(IP0_9_8, IRQ7), + PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP0_10, MMC_CLK), + PINMUX_IPSR_DATA(IP0_10, SD2_CLK), + PINMUX_IPSR_DATA(IP0_11, MMC_CMD), + PINMUX_IPSR_DATA(IP0_11, SD2_CMD), + PINMUX_IPSR_DATA(IP0_12, MMC_D0), + PINMUX_IPSR_DATA(IP0_12, SD2_DATA0), + PINMUX_IPSR_DATA(IP0_13, MMC_D1), + PINMUX_IPSR_DATA(IP0_13, SD2_DATA1), + PINMUX_IPSR_DATA(IP0_14, MMC_D2), + PINMUX_IPSR_DATA(IP0_14, SD2_DATA2), + PINMUX_IPSR_DATA(IP0_15, MMC_D3), + PINMUX_IPSR_DATA(IP0_15, SD2_DATA3), + PINMUX_IPSR_DATA(IP0_16, MMC_D4), + PINMUX_IPSR_DATA(IP0_16, SD2_CD), + PINMUX_IPSR_DATA(IP0_17, MMC_D5), + PINMUX_IPSR_DATA(IP0_17, SD2_WP), + PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP0_23_22, D0), + PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_23_22, IRQ4), + PINMUX_IPSR_DATA(IP0_24, D1), + PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_25, D2), + PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_27_26, D3), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP0_29_28, D4), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP0_31_30, D5), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_1_0, D6), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), + PINMUX_IPSR_DATA(IP1_3_2, D7), + PINMUX_IPSR_DATA(IP1_3_2, IRQ3), + PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0), + PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), + PINMUX_IPSR_DATA(IP1_5_4, D8), + PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), + PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), + PINMUX_IPSR_DATA(IP1_7_6, D9), + PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), + PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), + PINMUX_IPSR_DATA(IP1_10_8, D10), + PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), + PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), + PINMUX_IPSR_DATA(IP1_10_8, IRQ6), + PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), + PINMUX_IPSR_DATA(IP1_12_11, D11), + PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), + PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), + PINMUX_IPSR_DATA(IP1_14_13, D12), + PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), + PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), + PINMUX_IPSR_DATA(IP1_17_15, D13), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP1_17_15, TANS1), + PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP1_19_18, D14), + PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), + PINMUX_IPSR_DATA(IP1_21_20, D15), + PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), + PINMUX_IPSR_DATA(IP1_23_22, A0), + PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), + PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), + PINMUX_IPSR_DATA(IP1_24, A1), + PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD), + PINMUX_IPSR_DATA(IP1_26, A3), + PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK), + PINMUX_IPSR_DATA(IP1_27, A4), + PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD), + PINMUX_IPSR_DATA(IP1_29_28, A5), + PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD), + PINMUX_IPSR_DATA(IP1_29_28, PWM4_B), + PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), + PINMUX_IPSR_DATA(IP1_31_30, A6), + PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), + PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_1_0, A7), + PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), + PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_DATA(IP2_3_2, A8), + PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_DATA(IP2_5_4, A9), + PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_DATA(IP2_7_6, A10), + PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), + PINMUX_IPSR_DATA(IP2_9_8, A11), + PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), + PINMUX_IPSR_DATA(IP2_11_10, A12), + PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_DATA(IP2_13_12, A13), + PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_DATA(IP2_15_14, A14), + PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0), + PINMUX_IPSR_DATA(IP2_17_16, A15), + PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0), + PINMUX_IPSR_DATA(IP2_20_18, A16), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0), + PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2), + PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), + PINMUX_IPSR_DATA(IP2_23_21, A17), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), + PINMUX_IPSR_DATA(IP2_26_24, A18), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), + PINMUX_IPSR_DATA(IP2_29_27, A19), + PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), + PINMUX_IPSR_DATA(IP2_29_27, PWM4), + PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), + PINMUX_IPSR_DATA(IP2_29_27, MOUT0), + PINMUX_IPSR_DATA(IP2_31_30, A20), + PINMUX_IPSR_DATA(IP2_31_30, SPCLK), + PINMUX_IPSR_DATA(IP2_29_27, MOUT1), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_1_0, A21), + PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0), + PINMUX_IPSR_DATA(IP3_1_0, MOUT2), + PINMUX_IPSR_DATA(IP3_3_2, A22), + PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1), + PINMUX_IPSR_DATA(IP3_3_2, MOUT5), + PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N), + PINMUX_IPSR_DATA(IP3_5_4, A23), + PINMUX_IPSR_DATA(IP3_5_4, IO2), + PINMUX_IPSR_DATA(IP3_5_4, MOUT6), + PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N), + PINMUX_IPSR_DATA(IP3_7_6, A24), + PINMUX_IPSR_DATA(IP3_7_6, IO3), + PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2), + PINMUX_IPSR_DATA(IP3_9_8, A25), + PINMUX_IPSR_DATA(IP3_9_8, SSL), + PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N), + PINMUX_IPSR_DATA(IP3_10, CS0_N), + PINMUX_IPSR_DATA(IP3_10, VI1_DATA8), + PINMUX_IPSR_DATA(IP3_11, CS1_N_A26), + PINMUX_IPSR_DATA(IP3_11, VI1_DATA9), + PINMUX_IPSR_DATA(IP3_12, EX_CS0_N), + PINMUX_IPSR_DATA(IP3_12, VI1_DATA10), + PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N), + PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B), + PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD), + PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), + PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), + PINMUX_IPSR_DATA(IP3_17_15, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0), + PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), + PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0), + PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), + PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0), + PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), + PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0), + PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), + PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_29_27, BS_N), + PINMUX_IPSR_DATA(IP3_29_27, DRACK0), + PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), + PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), + PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), + PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1), + PINMUX_IPSR_DATA(IP3_30, RD_N), + PINMUX_IPSR_DATA(IP3_30, ATACS11_N), + PINMUX_IPSR_DATA(IP3_31, RD_WR_N), + PINMUX_IPSR_DATA(IP3_31, ATAG1_N), + + /* IPSR4 */ + PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1), + PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), + PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), + PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), + PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), + PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), + PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), + PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), + PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), + PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), + PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2), + PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3), + PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19), + PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3), + PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4), + PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20), + PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4), + PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5), + PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21), + PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5), + PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6), + PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22), + PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6), + PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7), + PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23), + PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), + PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), + PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), + PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), + PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), + PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), + PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), + PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), + PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), + PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), + PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10), + PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3), + PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11), + PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11), + PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4), + PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12), + PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12), + + /* IPSR5 */ + PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5), + PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13), + PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13), + PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6), + PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14), + PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14), + PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7), + PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15), + PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), + PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), + PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), + PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), + PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), + PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), + PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), + PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), + PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18), + PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3), + PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3), + PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19), + PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4), + PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4), + PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20), + PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5), + PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5), + PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21), + PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6), + PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6), + PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22), + PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7), + PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7), + PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23), + PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN), + PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS), + PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24), + PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP5_27_26, QCLK), + PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25), + PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE), + PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26), + PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS), + PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), + PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), + PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), + PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), + PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), + PINMUX_IPSR_DATA(IP6_5_4, QPOLA), + PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), + PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), + PINMUX_IPSR_DATA(IP6_7_6, QPOLB), + PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), + PINMUX_IPSR_DATA(IP6_8, VI0_CLK), + PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), + PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), + PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), + PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), + PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), + PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), + PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), + PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), + PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), + PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), + PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), + PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), + PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), + PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + + /* IPSR7 */ + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_DATA(IP7_31, DREQ0_N), + PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), + + /* IPSR8 */ + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), + PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), + PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_19_17, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), + PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_28_26, IRQ5), + PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), + PINMUX_IPSR_DATA(IP9_5_3, IRQ0), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), + PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0), + PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), + PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), + PINMUX_IPSR_DATA(IP9_8_6, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), + PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0), + PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1), + PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1), + PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0), + PINMUX_IPSR_DATA(IP9_16_15, PWM6), + PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), + PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0), + PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), + PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), + PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), + PINMUX_IPSR_DATA(IP9_21_19, PWM2), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0), + PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0), + PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), + PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), + PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0), + PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), + PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), + PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), + PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP9_30_28, PWM3), + PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0), + PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), + PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), + PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), + + /* IPSR10 */ + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0), + PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), + PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), + PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0), + PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), + PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), + PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0), + PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), + PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), + PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), + PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), + PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0), + PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), + PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), + PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), + PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), + PINMUX_IPSR_DATA(IP10_14_12, IRQ1), + PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), + PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), + PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_DATA(IP10_17_15, IRQ2), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3), + PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), + PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_DATA(IP10_17_15, TANS2), + PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), + PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3), + PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), + PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), + PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3), + PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), + PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), + PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), + PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), + PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), + PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), + PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), + PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), + + /* IPSR11 */ + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_DATA(IP11_20_18, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), + PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), + PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0), + PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), + PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0), + PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), + PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), + PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), + PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), + PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), + PINMUX_IPSR_DATA(IP12_17_15, IRQ9), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0), + PINMUX_IPSR_DATA(IP12_17_15, DACK2), + PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), + PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), + PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0), + PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0), + PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), + + /* IPSR13 */ + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0), + PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0), + PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), + PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), + PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), + PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0), + PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), + PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), + PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), + PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), + PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), + PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), + PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), + PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), + PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4), + PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4), + PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4), + PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - ETH -------------------------------------------------------------------- */ +static const unsigned int eth_link_pins[] = { + /* LINK */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int eth_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int eth_magic_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int eth_magic_mux[] = { + ETH_MAGIC_MARK, +}; +static const unsigned int eth_mdio_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13), +}; +static const unsigned int eth_mdio_mux[] = { + ETH_MDC_MARK, ETH_MDIO_MARK, +}; +static const unsigned int eth_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20), + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19), +}; +static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, +}; +static const unsigned int eth_link_b_pins[] = { + /* LINK */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int eth_link_b_mux[] = { + ETH_LINK_B_MARK, +}; +static const unsigned int eth_magic_b_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int eth_magic_b_mux[] = { + ETH_MAGIC_B_MARK, +}; +static const unsigned int eth_mdio_b_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10), +}; +static const unsigned int eth_mdio_b_mux[] = { + ETH_MDC_B_MARK, ETH_MDIO_B_MARK, +}; +static const unsigned int eth_rmii_b_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16), +}; +static const unsigned int eth_rmii_b_mux[] = { + ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK, + ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK, +}; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), +}; +static const unsigned int hscif0_data_mux[] = { + HSCIF0_HRX_MARK, HSCIF0_HTX_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCIF0_HSCK_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK, +}; +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31), +}; +static const unsigned int hscif0_data_b_mux[] = { + HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK, +}; +static const unsigned int hscif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int hscif0_clk_b_mux[] = { + HSCIF0_HSCK_B_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int hscif1_data_mux[] = { + HSCIF1_HRX_MARK, HSCIF1_HTX_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 10), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCIF1_HSCK_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK, +}; +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int hscif1_data_b_mux[] = { + HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), +}; +static const unsigned int hscif2_data_mux[] = { + HSCIF2_HRX_MARK, HSCIF2_HTX_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCIF2_HSCK_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK, +}; +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), +}; +static const unsigned int i2c0_mux[] = { + I2C0_SCL_MARK, I2C0_SDA_MARK, +}; +static const unsigned int i2c0_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), +}; +static const unsigned int i2c0_b_mux[] = { + I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, +}; +static const unsigned int i2c0_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c0_c_mux[] = { + I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, +}; +static const unsigned int i2c0_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; +static const unsigned int i2c0_d_mux[] = { + I2C0_SCL_D_MARK, I2C0_SDA_D_MARK, +}; +static const unsigned int i2c0_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int i2c0_e_mux[] = { + I2C0_SCL_E_MARK, I2C0_SDA_E_MARK, +}; +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int i2c1_mux[] = { + I2C1_SCL_MARK, I2C1_SDA_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), +}; +static const unsigned int i2c1_b_mux[] = { + I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, +}; +static const unsigned int i2c1_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), +}; +static const unsigned int i2c1_c_mux[] = { + I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, +}; +static const unsigned int i2c1_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), +}; +static const unsigned int i2c1_d_mux[] = { + I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, +}; +static const unsigned int i2c1_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int i2c1_e_mux[] = { + I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, +}; +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int i2c2_mux[] = { + I2C2_SCL_MARK, I2C2_SDA_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int i2c2_b_mux[] = { + I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, +}; +static const unsigned int i2c2_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int i2c2_c_mux[] = { + I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, +}; +static const unsigned int i2c2_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int i2c2_d_mux[] = { + I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, +}; +static const unsigned int i2c2_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int i2c2_e_mux[] = { + I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, +}; +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int i2c3_mux[] = { + I2C3_SCL_MARK, I2C3_SDA_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), +}; +static const unsigned int i2c3_b_mux[] = { + I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, +}; +static const unsigned int i2c3_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), +}; +static const unsigned int i2c3_c_mux[] = { + I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, +}; +static const unsigned int i2c3_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int i2c3_d_mux[] = { + I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, +}; +static const unsigned int i2c3_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int i2c3_e_mux[] = { + I2C3_SCL_E_MARK, I2C3_SDA_E_MARK, +}; +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int i2c4_mux[] = { + I2C4_SCL_MARK, I2C4_SDA_MARK, +}; +static const unsigned int i2c4_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), +}; +static const unsigned int i2c4_b_mux[] = { + I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, +}; +static const unsigned int i2c4_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int i2c4_c_mux[] = { + I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, +}; +static const unsigned int i2c4_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int i2c4_d_mux[] = { + I2C4_SCL_D_MARK, I2C4_SDA_D_MARK, +}; +static const unsigned int i2c4_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), +}; +static const unsigned int i2c4_e_mux[] = { + I2C4_SCL_E_MARK, I2C4_SDA_E_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int intc_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(4, 1), +}; +static const unsigned int intc_irq5_mux[] = { + IRQ5_MARK, +}; +static const unsigned int intc_irq6_pins[] = { + /* IRQ6 */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int intc_irq6_mux[] = { + IRQ6_MARK, +}; +static const unsigned int intc_irq7_pins[] = { + /* IRQ7 */ + RCAR_GP_PIN(6, 15), +}; +static const unsigned int intc_irq7_mux[] = { + IRQ7_MARK, +}; +static const unsigned int intc_irq8_pins[] = { + /* IRQ8 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int intc_irq8_mux[] = { + IRQ8_MARK, +}; +static const unsigned int intc_irq9_pins[] = { + /* IRQ9 */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int intc_irq9_mux[] = { + IRQ9_MARK, +}; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(4, 7), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(4, 3), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 29), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 24), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 25), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 5), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 6), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int msiof1_rx_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int msiof1_tx_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 30), +}; +static const unsigned int msiof2_rx_mux[] = { + MSIOF2_RXD_MARK, +}; +static const unsigned int msiof2_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int msiof2_tx_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int msiof2_rx_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int msiof2_tx_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int scif0_data_mux[] = { + SCIF0_RXD_MARK, SCIF0_TXD_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int scif0_clk_mux[] = { + SCIF_CLK_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), +}; +static const unsigned int scif0_data_b_mux[] = { + SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, +}; +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 29), +}; +static const unsigned int scif0_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; +static const unsigned int scif0_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), +}; +static const unsigned int scif0_data_c_mux[] = { + SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK, +}; +static const unsigned int scif0_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int scif0_data_d_mux[] = { + SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int scif1_data_mux[] = { + SCIF1_RXD_MARK, SCIF1_TXD_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int scif1_clk_mux[] = { + SCIF1_SCK_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), +}; +static const unsigned int scif1_data_b_mux[] = { + SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCIF1_SCK_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), +}; +static const unsigned int scif1_data_c_mux[] = { + SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK, +}; +static const unsigned int scif1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif1_clk_c_mux[] = { + SCIF1_SCK_C_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scif2_data_mux[] = { + SCIF2_RXD_MARK, SCIF2_TXD_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int scif2_clk_mux[] = { + SCIF2_SCK_MARK, +}; +static const unsigned int scif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int scif2_data_b_mux[] = { + SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK, +}; +static const unsigned int scif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int scif2_clk_b_mux[] = { + SCIF2_SCK_B_MARK, +}; +static const unsigned int scif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int scif2_data_c_mux[] = { + SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK, +}; +static const unsigned int scif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 19), +}; +static const unsigned int scif2_clk_c_mux[] = { + SCIF2_SCK_C_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int scif3_data_mux[] = { + SCIF3_RXD_MARK, SCIF3_TXD_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int scif3_clk_mux[] = { + SCIF3_SCK_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), +}; +static const unsigned int scif3_data_b_mux[] = { + SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK, +}; +static const unsigned int scif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int scif3_clk_b_mux[] = { + SCIF3_SCK_B_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int scif4_data_mux[] = { + SCIF4_RXD_MARK, SCIF4_TXD_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; +static const unsigned int scif4_data_b_mux[] = { + SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK, +}; +static const unsigned int scif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), +}; +static const unsigned int scif4_data_c_mux[] = { + SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK, +}; +static const unsigned int scif4_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), +}; +static const unsigned int scif4_data_d_mux[] = { + SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK, +}; +static const unsigned int scif4_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), +}; +static const unsigned int scif4_data_e_mux[] = { + SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +}; +static const unsigned int scif5_data_mux[] = { + SCIF5_RXD_MARK, SCIF5_TXD_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), +}; +static const unsigned int scif5_data_b_mux[] = { + SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK, +}; +static const unsigned int scif5_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11), +}; +static const unsigned int scif5_data_c_mux[] = { + SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK, +}; +static const unsigned int scif5_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif5_data_d_mux[] = { + SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifa0_data_b_mux[] = { + SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK +}; +static const unsigned int scifa0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int scifa0_data_c_mux[] = { + SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK +}; +static const unsigned int scifa0_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scifa0_data_d_mux[] = { + SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scifa1_data_b_mux[] = { + SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, +}; +static const unsigned int scifa1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scifa1_clk_b_mux[] = { + SCIFA1_SCK_B_MARK, +}; +static const unsigned int scifa1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scifa1_data_c_mux[] = { + SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, +}; +static const unsigned int scifa1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scifa1_clk_c_mux[] = { + SCIFA1_SCK_C_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK_MARK, +}; +static const unsigned int scifa2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0), +}; +static const unsigned int scifa2_data_b_mux[] = { + SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, +}; +static const unsigned int scifa2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 30), +}; +static const unsigned int scifa2_clk_b_mux[] = { + SCIFA2_SCK_B_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 24), +}; +static const unsigned int scifa3_clk_mux[] = { + SCIFA3_SCK_MARK, +}; +static const unsigned int scifa3_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), +}; +static const unsigned int scifa3_data_b_mux[] = { + SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK, +}; +static const unsigned int scifa3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int scifa3_clk_b_mux[] = { + SCIFA3_SCK_B_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12), +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +static const unsigned int scifa4_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23), +}; +static const unsigned int scifa4_data_b_mux[] = { + SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK, +}; +static const unsigned int scifa4_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int scifa4_data_c_mux[] = { + SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK, +}; +static const unsigned int scifa4_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), +}; +static const unsigned int scifa4_data_d_mux[] = { + SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scifa5_data_mux[] = { + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, +}; +static const unsigned int scifa5_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), +}; +static const unsigned int scifa5_data_b_mux[] = { + SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK, +}; +static const unsigned int scifa5_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), +}; +static const unsigned int scifa5_data_c_mux[] = { + SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK, +}; +static const unsigned int scifa5_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), +}; +static const unsigned int scifa5_data_d_mux[] = { + SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20), +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17), +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(eth_link_b), + SH_PFC_PIN_GROUP(eth_magic_b), + SH_PFC_PIN_GROUP(eth_mdio_b), + SH_PFC_PIN_GROUP(eth_rmii_b), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_clk_b), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c0_d), + SH_PFC_PIN_GROUP(i2c0_e), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c3_e), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c4_d), + SH_PFC_PIN_GROUP(i2c4_e), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(intc_irq4), + SH_PFC_PIN_GROUP(intc_irq5), + SH_PFC_PIN_GROUP(intc_irq6), + SH_PFC_PIN_GROUP(intc_irq7), + SH_PFC_PIN_GROUP(intc_irq8), + SH_PFC_PIN_GROUP(intc_irq9), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rx_b), + SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_clk_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_data_d), + SH_PFC_PIN_GROUP(scif4_data_e), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_data_c), + SH_PFC_PIN_GROUP(scif5_data_d), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_data_c), + SH_PFC_PIN_GROUP(scifa0_data_d), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_clk_b), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_data_b), + SH_PFC_PIN_GROUP(scifa3_clk_b), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_data_b), + SH_PFC_PIN_GROUP(scifa4_data_c), + SH_PFC_PIN_GROUP(scifa4_data_d), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifa5_data_b), + SH_PFC_PIN_GROUP(scifa5_data_c), + SH_PFC_PIN_GROUP(scifa5_data_d), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), +}; + +static const char * const eth_groups[] = { + "eth_link", + "eth_magic", + "eth_mdio", + "eth_rmii", + "eth_link_b", + "eth_magic_b", + "eth_mdio_b", + "eth_rmii_b", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", + "hscif0_data_b", + "hscif0_clk_b", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", + "hscif1_data_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", + "i2c0_b", + "i2c0_c", + "i2c0_d", + "i2c0_e", +}; + +static const char * const i2c1_groups[] = { + "i2c1", + "i2c1_b", + "i2c1_c", + "i2c1_d", + "i2c1_e", +}; + +static const char * const i2c2_groups[] = { + "i2c2", + "i2c2_b", + "i2c2_c", + "i2c2_d", + "i2c2_e", +}; + +static const char * const i2c3_groups[] = { + "i2c3", + "i2c3_b", + "i2c3_c", + "i2c3_d", + "i2c3_e", +}; + +static const char * const i2c4_groups[] = { + "i2c4", + "i2c4_b", + "i2c4_c", + "i2c4_d", + "i2c4_e", +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", + "intc_irq4", + "intc_irq5", + "intc_irq6", + "intc_irq7", + "intc_irq8", + "intc_irq9", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_rx", + "msiof0_tx", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_rx", + "msiof1_tx", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_rx_b", + "msiof1_tx_b", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_rx", + "msiof2_tx", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_rx_b", + "msiof2_tx_b", +}; + +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_data_b", + "scif0_clk_b", + "scif0_data_c", + "scif0_data_d", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_data_b", + "scif1_clk_b", + "scif1_data_c", + "scif1_clk_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", + "scif2_data_b", + "scif2_clk_b", + "scif2_data_c", + "scif2_clk_c", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_data_b", + "scif3_clk_b", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_data_b", + "scif4_data_c", + "scif4_data_d", + "scif4_data_e", +}; + +static const char * const scif5_groups[] = { + "scif5_data", + "scif5_data_b", + "scif5_data_c", + "scif5_data_d", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_data_b", + "scifa0_data_c", + "scifa0_data_d", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_data_b", + "scifa1_clk_b", + "scifa1_data_c", + "scifa1_clk_c", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_data_b", + "scifa2_clk_b", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_clk", + "scifa3_data_b", + "scifa3_clk_b", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data", + "scifa4_data_b", + "scifa4_data_c", + "scifa4_data_d", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data", + "scifa5_data_b", + "scifa5_data_c", + "scifa5_data_d", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP2_17_16, + GP_0_30_FN, FN_IP2_15_14, + GP_0_29_FN, FN_IP2_13_12, + GP_0_28_FN, FN_IP2_11_10, + GP_0_27_FN, FN_IP2_9_8, + GP_0_26_FN, FN_IP2_7_6, + GP_0_25_FN, FN_IP2_5_4, + GP_0_24_FN, FN_IP2_3_2, + GP_0_23_FN, FN_IP2_1_0, + GP_0_22_FN, FN_IP1_31_30, + GP_0_21_FN, FN_IP1_29_28, + GP_0_20_FN, FN_IP1_27, + GP_0_19_FN, FN_IP1_26, + GP_0_18_FN, FN_A2, + GP_0_17_FN, FN_IP1_24, + GP_0_16_FN, FN_IP1_23_22, + GP_0_15_FN, FN_IP1_21_20, + GP_0_14_FN, FN_IP1_19_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_13, + GP_0_11_FN, FN_IP1_12_11, + GP_0_10_FN, FN_IP1_10_8, + GP_0_9_FN, FN_IP1_7_6, + GP_0_8_FN, FN_IP1_5_4, + GP_0_7_FN, FN_IP1_3_2, + GP_0_6_FN, FN_IP1_1_0, + GP_0_5_FN, FN_IP0_31_30, + GP_0_4_FN, FN_IP0_29_28, + GP_0_3_FN, FN_IP0_27_26, + GP_0_2_FN, FN_IP0_25, + GP_0_1_FN, FN_IP0_24, + GP_0_0_FN, FN_IP0_23_22, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_DACK0, + GP_1_24_FN, FN_IP7_31, + GP_1_23_FN, FN_IP4_1_0, + GP_1_22_FN, FN_WE1_N, + GP_1_21_FN, FN_WE0_N, + GP_1_20_FN, FN_IP3_31, + GP_1_19_FN, FN_IP3_30, + GP_1_18_FN, FN_IP3_29_27, + GP_1_17_FN, FN_IP3_26_24, + GP_1_16_FN, FN_IP3_23_21, + GP_1_15_FN, FN_IP3_20_18, + GP_1_14_FN, FN_IP3_17_15, + GP_1_13_FN, FN_IP3_14_13, + GP_1_12_FN, FN_IP3_12, + GP_1_11_FN, FN_IP3_11, + GP_1_10_FN, FN_IP3_10, + GP_1_9_FN, FN_IP3_9_8, + GP_1_8_FN, FN_IP3_7_6, + GP_1_7_FN, FN_IP3_5_4, + GP_1_6_FN, FN_IP3_3_2, + GP_1_5_FN, FN_IP3_1_0, + GP_1_4_FN, FN_IP2_31_30, + GP_1_3_FN, FN_IP2_29_27, + GP_1_2_FN, FN_IP2_26_24, + GP_1_1_FN, FN_IP2_23_21, + GP_1_0_FN, FN_IP2_20_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_4, + GP_2_29_FN, FN_IP6_3_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_31_30, + GP_2_26_FN, FN_IP5_29_28, + GP_2_25_FN, FN_IP5_27_26, + GP_2_24_FN, FN_IP5_25_24, + GP_2_23_FN, FN_IP5_23_22, + GP_2_22_FN, FN_IP5_21_20, + GP_2_21_FN, FN_IP5_19_18, + GP_2_20_FN, FN_IP5_17_16, + GP_2_19_FN, FN_IP5_15_14, + GP_2_18_FN, FN_IP5_13_12, + GP_2_17_FN, FN_IP5_11_9, + GP_2_16_FN, FN_IP5_8_6, + GP_2_15_FN, FN_IP5_5_4, + GP_2_14_FN, FN_IP5_3_2, + GP_2_13_FN, FN_IP5_1_0, + GP_2_12_FN, FN_IP4_31_30, + GP_2_11_FN, FN_IP4_29_28, + GP_2_10_FN, FN_IP4_27_26, + GP_2_9_FN, FN_IP4_25_23, + GP_2_8_FN, FN_IP4_22_20, + GP_2_7_FN, FN_IP4_19_18, + GP_2_6_FN, FN_IP4_17_16, + GP_2_5_FN, FN_IP4_15_14, + GP_2_4_FN, FN_IP4_13_12, + GP_2_3_FN, FN_IP4_11_10, + GP_2_2_FN, FN_IP4_9_8, + GP_2_1_FN, FN_IP4_7_5, + GP_2_0_FN, FN_IP4_4_2 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP8_22_20, + GP_3_30_FN, FN_IP8_19_17, + GP_3_29_FN, FN_IP8_16_15, + GP_3_28_FN, FN_IP8_14_12, + GP_3_27_FN, FN_IP8_11_9, + GP_3_26_FN, FN_IP8_8_6, + GP_3_25_FN, FN_IP8_5_3, + GP_3_24_FN, FN_IP8_2_0, + GP_3_23_FN, FN_IP7_29_27, + GP_3_22_FN, FN_IP7_26_24, + GP_3_21_FN, FN_IP7_23_21, + GP_3_20_FN, FN_IP7_20_18, + GP_3_19_FN, FN_IP7_17_15, + GP_3_18_FN, FN_IP7_14_12, + GP_3_17_FN, FN_IP7_11_9, + GP_3_16_FN, FN_IP7_8_6, + GP_3_15_FN, FN_IP7_5_3, + GP_3_14_FN, FN_IP7_2_0, + GP_3_13_FN, FN_IP6_31_29, + GP_3_12_FN, FN_IP6_28_26, + GP_3_11_FN, FN_IP6_25_23, + GP_3_10_FN, FN_IP6_22_20, + GP_3_9_FN, FN_IP6_19_17, + GP_3_8_FN, FN_IP6_16, + GP_3_7_FN, FN_IP6_15, + GP_3_6_FN, FN_IP6_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12, + GP_3_3_FN, FN_IP6_11, + GP_3_2_FN, FN_IP6_10, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP11_17_16, + GP_4_30_FN, FN_IP11_15_14, + GP_4_29_FN, FN_IP11_13_11, + GP_4_28_FN, FN_IP11_10_8, + GP_4_27_FN, FN_IP11_7_6, + GP_4_26_FN, FN_IP11_5_3, + GP_4_25_FN, FN_IP11_2_0, + GP_4_24_FN, FN_IP10_31_30, + GP_4_23_FN, FN_IP10_29_27, + GP_4_22_FN, FN_IP10_26_24, + GP_4_21_FN, FN_IP10_23_21, + GP_4_20_FN, FN_IP10_20_18, + GP_4_19_FN, FN_IP10_17_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_30_28, + GP_4_12_FN, FN_IP9_27_25, + GP_4_11_FN, FN_IP9_24_22, + GP_4_10_FN, FN_IP9_21_19, + GP_4_9_FN, FN_IP9_18_17, + GP_4_8_FN, FN_IP9_16_15, + GP_4_7_FN, FN_IP9_14_12, + GP_4_6_FN, FN_IP9_11_9, + GP_4_5_FN, FN_IP9_8_6, + GP_4_4_FN, FN_IP9_5_3, + GP_4_3_FN, FN_IP9_2_0, + GP_4_2_FN, FN_IP8_31_29, + GP_4_1_FN, FN_IP8_28_26, + GP_4_0_FN, FN_IP8_25_23 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_FN, FN_USB1_OVC, + GP_5_26_FN, FN_USB1_PWEN, + GP_5_25_FN, FN_USB0_OVC, + GP_5_24_FN, FN_USB0_PWEN, + GP_5_23_FN, FN_IP13_26_24, + GP_5_22_FN, FN_IP13_23_21, + GP_5_21_FN, FN_IP13_20_18, + GP_5_20_FN, FN_IP13_17_15, + GP_5_19_FN, FN_IP13_14_12, + GP_5_18_FN, FN_IP13_11_9, + GP_5_17_FN, FN_IP13_8_6, + GP_5_16_FN, FN_IP13_5_3, + GP_5_15_FN, FN_IP13_2_0, + GP_5_14_FN, FN_IP12_29_27, + GP_5_13_FN, FN_IP12_26_24, + GP_5_12_FN, FN_IP12_23_21, + GP_5_11_FN, FN_IP12_20_18, + GP_5_10_FN, FN_IP12_17_15, + GP_5_9_FN, FN_IP12_14_13, + GP_5_8_FN, FN_IP12_12_11, + GP_5_7_FN, FN_IP12_10_9, + GP_5_6_FN, FN_IP12_8_6, + GP_5_5_FN, FN_IP12_5_3, + GP_5_4_FN, FN_IP12_2_0, + GP_5_3_FN, FN_IP11_29_27, + GP_5_2_FN, FN_IP11_26_24, + GP_5_1_FN, FN_IP11_23_21, + GP_5_0_FN, FN_IP11_20_18 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_FN, FN_IP0_21_20, + GP_6_24_FN, FN_IP0_19_18, + GP_6_23_FN, FN_IP0_17, + GP_6_22_FN, FN_IP0_16, + GP_6_21_FN, FN_IP0_15, + GP_6_20_FN, FN_IP0_14, + GP_6_19_FN, FN_IP0_13, + GP_6_18_FN, FN_IP0_12, + GP_6_17_FN, FN_IP0_11, + GP_6_16_FN, FN_IP0_10, + GP_6_15_FN, FN_IP0_9_8, + GP_6_14_FN, FN_IP0_0, + GP_6_13_FN, FN_SD1_DATA3, + GP_6_12_FN, FN_SD1_DATA2, + GP_6_11_FN, FN_SD1_DATA1, + GP_6_10_FN, FN_SD1_DATA0, + GP_6_9_FN, FN_SD1_CMD, + GP_6_8_FN, FN_SD1_CLK, + GP_6_7_FN, FN_SD0_WP, + GP_6_6_FN, FN_SD0_CD, + GP_6_5_FN, FN_SD0_DATA3, + GP_6_4_FN, FN_SD0_DATA2, + GP_6_3_FN, FN_SD0_DATA1, + GP_6_2_FN, FN_SD0_DATA0, + GP_6_1_FN, FN_SD0_CMD, + GP_6_0_FN, FN_SD0_CLK } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 2, 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP0_31_30 [2] */ + FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, + /* IP0_29_28 [2] */ + FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, + /* IP0_27_26 [2] */ + FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, + /* IP0_25 [1] */ + FN_D2, FN_SCIFA3_TXD_B, + /* IP0_24 [1] */ + FN_D1, FN_SCIFA3_RXD_B, + /* IP0_23_22 [2] */ + FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, + /* IP0_21_20 [2] */ + FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, + /* IP0_19_18 [2] */ + FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, + /* IP0_17 [1] */ + FN_MMC_D5, FN_SD2_WP, + /* IP0_16 [1] */ + FN_MMC_D4, FN_SD2_CD, + /* IP0_15 [1] */ + FN_MMC_D3, FN_SD2_DATA3, + /* IP0_14 [1] */ + FN_MMC_D2, FN_SD2_DATA2, + /* IP0_13 [1] */ + FN_MMC_D1, FN_SD2_DATA1, + /* IP0_12 [1] */ + FN_MMC_D0, FN_SD2_DATA0, + /* IP0_11 [1] */ + FN_MMC_CMD, FN_SD2_CMD, + /* IP0_10 [1] */ + FN_MMC_CLK, FN_SD2_CLK, + /* IP0_9_8 [2] */ + FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, + /* IP0_7 [1] */ + 0, 0, + /* IP0_6 [1] */ + 0, 0, + /* IP0_5 [1] */ + 0, 0, + /* IP0_4 [1] */ + 0, 0, + /* IP0_3 [1] */ + 0, 0, + /* IP0_2 [1] */ + 0, 0, + /* IP0_1 [1] */ + 0, 0, + /* IP0_0 [1] */ + FN_SD1_CD, FN_CAN0_RX, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, + 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, + 2, 2) { + /* IP1_31_30 [2] */ + FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, + /* IP1_29_28 [2] */ + FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, + /* IP1_27 [1] */ + FN_A4, FN_SCIFB0_TXD, + /* IP1_26 [1] */ + FN_A3, FN_SCIFB0_SCK, + /* IP1_25 [1] */ + 0, 0, + /* IP1_24 [1] */ + FN_A1, FN_SCIFB1_TXD, + /* IP1_23_22 [2] */ + FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, + /* IP1_21_20 [2] */ + FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0, + /* IP1_19_18 [2] */ + FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0, + /* IP1_17_15 [3] */ + FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, + 0, 0, 0, + /* IP1_14_13 [2] */ + FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, + /* IP1_12_11 [2] */ + FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, + /* IP1_10_8 [3] */ + FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, + 0, 0, 0, + /* IP1_7_6 [2] */ + FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0, + /* IP1_5_4 [2] */ + FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0, + /* IP1_3_2 [2] */ + FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, + /* IP1_1_0 [2] */ + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + /* IP2_31_30 [2] */ + FN_A20, FN_SPCLK, FN_MOUT1, 0, + /* IP2_29_27 [3] */ + FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, + FN_MOUT0, 0, 0, 0, + /* IP2_26_24 [3] */ + FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, + FN_AVB_AVTP_MATCH_B, 0, 0, 0, + /* IP2_23_21 [3] */ + FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, + FN_AVB_AVTP_CAPTURE_B, 0, 0, 0, + /* IP2_20_18 [3] */ + FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, + FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0, + /* IP2_17_16 [2] */ + FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, + /* IP2_15_14 [2] */ + FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, + /* IP2_13_12 [2] */ + FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0, + /* IP2_11_10 [2] */ + FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, + /* IP2_9_8 [2] */ + FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0, + /* IP2_7_6 [2] */ + FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0, + /* IP2_5_4 [2] */ + FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, + /* IP2_3_2 [2] */ + FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, + /* IP2_1_0 [2] */ + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, + 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { + /* IP3_31 [1] */ + FN_RD_WR_N, FN_ATAG1_N, + /* IP3_30 [1] */ + FN_RD_N, FN_ATACS11_N, + /* IP3_29_27 [3] */ + FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, + FN_MTS_N_B, 0, 0, + /* IP3_26_24 [3] */ + FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, + FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, + /* IP3_23_21 [3] */ + FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, + FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B, + /* IP3_20_18 [3] */ + FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, + FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, + /* IP3_17_15 [3] */ + FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, + FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B, + /* IP3_14_13 [2] */ + FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, + /* IP3_12 [1] */ + FN_EX_CS0_N, FN_VI1_DATA10, + /* IP3_11 [1] */ + FN_CS1_N_A26, FN_VI1_DATA9, + /* IP3_10 [1] */ + FN_CS0_N, FN_VI1_DATA8, + /* IP3_9_8 [2] */ + FN_A25, FN_SSL, FN_ATARD1_N, 0, + /* IP3_7_6 [2] */ + FN_A24, FN_IO3, FN_EX_WAIT2, 0, + /* IP3_5_4 [2] */ + FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, + /* IP3_3_2 [2] */ + FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N, + /* IP3_1_0 [2] */ + FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, + 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { + /* IP4_31_30 [2] */ + FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0, + /* IP4_29_28 [2] */ + FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0, + /* IP4_27_26 [2] */ + FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0, + /* IP4_25_23 [3] */ + FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, + FN_CC50_STATE9, 0, 0, 0, + /* IP4_22_20 [3] */ + FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, + FN_CC50_STATE8, 0, 0, 0, + /* IP4_19_18 [2] */ + FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0, + /* IP4_17_16 [2] */ + FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0, + /* IP4_15_14 [2] */ + FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0, + /* IP4_13_12 [2] */ + FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0, + /* IP4_11_10 [2] */ + FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0, + /* IP4_9_8 [2] */ + FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0, + /* IP4_7_5 [3] */ + FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, + FN_CC50_STATE1, 0, 0, 0, + /* IP4_4_2 [3] */ + FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, + FN_CC50_STATE0, 0, 0, 0, + /* IP4_1_0 [2] */ + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { + /* IP5_31_30 [2] */ + FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0, + /* IP5_29_28 [2] */ + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0, + /* IP5_27_26 [2] */ + FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0, + /* IP5_25_24 [2] */ + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0, + /* IP5_23_22 [2] */ + FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0, + /* IP5_21_20 [2] */ + FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0, + /* IP5_19_18 [2] */ + FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0, + /* IP5_17_16 [2] */ + FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0, + /* IP5_15_14 [2] */ + FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0, + /* IP5_13_12 [2] */ + FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0, + /* IP5_11_9 [3] */ + FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, + FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0, + /* IP5_8_6 [3] */ + FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, + FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0, + /* IP5_5_4 [2] */ + FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0, + /* IP5_3_2 [2] */ + FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0, + /* IP5_1_0 [2] */ + FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2) { + /* IP6_31_29 [3] */ + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, + FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, + /* IP6_28_26 [3] */ + FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, + FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, + /* IP6_25_23 [3] */ + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, + FN_AVB_COL, 0, 0, 0, + /* IP6_22_20 [3] */ + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, + FN_AVB_RX_ER, 0, 0, 0, + /* IP6_19_17 [3] */ + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, + FN_AVB_RXD7, 0, 0, 0, + /* IP6_16 [1] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, + /* IP6_15 [1] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, + /* IP6_14 [1] */ + FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, + /* IP6_13 [1] */ + FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, + /* IP6_12 [1] */ + FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, + /* IP6_11 [1] */ + FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, + /* IP6_10 [1] */ + FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, + /* IP6_9 [1] */ + FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, + /* IP6_8 [1] */ + FN_VI0_CLK, FN_AVB_RX_CLK, + /* IP6_7_6 [2] */ + FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, + /* IP6_5_4 [2] */ + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, + /* IP6_3_2 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + /* IP6_1_0 [2] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP7_31 [1] */ + FN_DREQ0_N, FN_SCIFB1_RXD, + /* IP7_30 [1] */ + 0, 0, + /* IP7_29_27 [3] */ + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, + FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, + /* IP7_26_24 [3] */ + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, + FN_SSI_SCK6_B, 0, 0, 0, + /* IP7_23_21 [3] */ + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, + FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, + /* IP7_20_18 [3] */ + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, + FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, + /* IP7_17_15 [3] */ + FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, + FN_SSI_SCK5_B, 0, 0, 0, + /* IP7_14_12 [3] */ + FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, 0, 0, + /* IP7_11_9 [3] */ + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, + FN_AVB_TXD3, FN_ADICHS1, 0, 0, + /* IP7_8_6 [3] */ + FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, + FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, + /* IP7_5_3 [3] */ + FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, + FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, + /* IP7_2_0 [3] */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, + FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + /* IP8_31_29 [3] */ + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, + FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + /* IP8_28_26 [3] */ + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, + FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, + /* IP8_25_23 [3] */ + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, + FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, + /* IP8_22_20 [3] */ + FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, + FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, + /* IP8_19_17 [3] */ + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, + FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, + /* IP8_16_15 [2] */ + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + /* IP8_14_12 [3] */ + FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, + FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, + /* IP8_11_9 [3] */ + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, + /* IP8_8_6 [3] */ + FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, + FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, + /* IP8_5_3 [3] */ + FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, + FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, + /* IP8_2_0 [3] */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) { + /* IP9_31 [1] */ + 0, 0, + /* IP9_30_28 [3] */ + FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, + FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0, + /* IP9_27_25 [3] */ + FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, + FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0, + /* IP9_24_22 [3] */ + FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, + FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0, + /* IP9_21_19 [3] */ + FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, + FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0, + /* IP9_18_17 [2] */ + FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, + /* IP9_16_15 [2] */ + FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, + /* IP9_14_12 [3] */ + FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, + FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0, + /* IP9_11_9 [3] */ + FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, + FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0, + /* IP9_8_6 [3] */ + FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, + FN_RIF1_CLK, FN_BPFCLK_B, 0, 0, + /* IP9_5_3 [3] */ + FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, + FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0, + /* IP9_2_0 [3] */ + FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, + FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP10_31_30 [2] */ + FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, + /* IP10_29_27 [3] */ + FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, + FN_CAN_DEBUGOUT9, 0, 0, 0, + /* IP10_26_24 [3] */ + FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, + FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0, + /* IP10_23_21 [3] */ + FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, + FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, + /* IP10_20_18 [3] */ + FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, + FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, + /* IP10_17_15 [3] */ + FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, + FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, + /* IP10_14_12 [3] */ + FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, + FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0, + /* IP10_11_9 [3] */ + FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, + FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0, + /* IP10_8_6 [3] */ + FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, + FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0, + /* IP10_5_3 [3] */ + FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, + FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0, + /* IP10_2_0 [3] */ + FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, + FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + /* IP11_31_30 [2] */ + 0, 0, 0, 0, + /* IP11_29_27 [3] */ + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, + FN_AD_CLK_B, 0, 0, 0, + /* IP11_26_24 [3] */ + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, + FN_AD_DO_B, 0, 0, 0, + /* IP11_23_21 [3] */ + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, 0, 0, + /* IP11_20_18 [3] */ + FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, + FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, + /* IP11_17_16 [2] */ + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, + /* IP11_15_14 [2] */ + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, + /* IP11_13_11 [3] */ + FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, + /* IP11_10_8 [3] */ + FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, + /* IP11_7_6 [2] */ + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_CAN_DEBUGOUT13, + /* IP11_5_3 [3] */ + FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, + FN_CAN_DEBUGOUT12, 0, 0, 0, + /* IP11_2_0 [3] */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, + FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0, + /* IP12_26_24 [3] */ + FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, + FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0, + /* IP12_23_21 [3] */ + FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, + FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, + /* IP12_20_18 [3] */ + FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, + FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0, + /* IP12_17_15 [3] */ + FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, + FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, + /* IP12_14_13 [2] */ + FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK, + /* IP12_12_11 [2] */ + FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, + /* IP12_10_9 [2] */ + FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, + /* IP12_8_6 [3] */ + FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, + FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, + /* IP12_5_3 [3] */ + FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, + FN_CAN1_RX_C, FN_DACK1_B, 0, 0, + /* IP12_2_0 [3] */ + FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, + FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30 [1] */ + 0, 0, + /* IP13_29 [1] */ + 0, 0, + /* IP13_28 [1] */ + 0, 0, + /* IP13_27 [1] */ + 0, 0, + /* IP13_26_24 [3] */ + FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, + FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D, + /* IP13_23_21 [3] */ + FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, + FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, + /* IP13_20_18 [3] */ + FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, + FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, + /* IP13_17_15 [3] */ + FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, + FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0, + /* IP13_14_12 [3] */ + FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, + FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, + /* IP13_11_9 [3] */ + FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, + FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, + /* IP13_8_6 [3] */ + FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, + FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, + /* IP13_5_3 [2] */ + FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, + FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, + /* IP13_2_0 [3] */ + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, + FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, + 2, 1) { + /* SEL_ADG [2] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_CAN [2] */ + FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, + /* SEL_DARC [3] */ + FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, + FN_SEL_DARC_4, 0, 0, 0, + /* SEL_DR0 [1] */ + FN_SEL_DR0_0, FN_SEL_DR0_1, + /* SEL_DR1 [1] */ + FN_SEL_DR1_0, FN_SEL_DR1_1, + /* SEL_DR2 [1] */ + FN_SEL_DR2_0, FN_SEL_DR2_1, + /* SEL_DR3 [1] */ + FN_SEL_DR3_0, FN_SEL_DR3_1, + /* SEL_ETH [1] */ + FN_SEL_ETH_0, FN_SEL_ETH_1, + /* SLE_FSN [1] */ + FN_SEL_FSN_0, FN_SEL_FSN_1, + /* SEL_IC200 [3] */ + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, 0, 0, 0, + /* SEL_I2C01 [3] */ + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, 0, 0, 0, + /* SEL_I2C02 [3] */ + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C02_4, 0, 0, 0, + /* SEL_I2C03 [3] */ + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, 0, 0, 0, + /* SEL_I2C04 [3] */ + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, 0, 0, 0, + /* SEL_IIC00 [2] */ + FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, + /* SEL_AVB [1] */ + FN_SEL_AVB_0, FN_SEL_AVB_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, + 2, 2, 2, 1, 1, 2) { + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_MSI1 [1] */ + FN_SEL_MSI1_0, FN_SEL_MSI1_1, + /* SEL_MSI2 [1] */ + FN_SEL_MSI2_0, FN_SEL_MSI2_1, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIFA0 [2] */ + FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, + FN_SEL_SCIFA0_3, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIFA3 [1] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA4_3, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_SCIFA5_3, + /* SEL_SPDM [1] */ + FN_SEL_SPDM_0, FN_SEL_SPDM_1, + /* SEL_TMU [1] */ + FN_SEL_TMU_0, FN_SEL_TMU_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_RDS [2] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, + /* SEL_SCIF2 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, + /* SEL_SCIF3 [1] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* SEL_SCIF4 [3] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, 0, 0, 0, + /* SEL_SCIF5 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI2 [1] */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* SEL_SSI4 [1] */ + FN_SEL_SSI4_0, FN_SEL_SSI4_1, + /* SEL_SSI5 [1] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, + /* RESERVED [1] */ + 0, 0, } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7794_pinmux_info = { + .name = "r8a77940_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; -- cgit v1.2.3 From e92a4047419c805d08ad136fbc72368249d9f091 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 12 Jun 2015 15:47:10 -0700 Subject: regulator: Add QCOM SPMI regulator driver Add an SPMI regulator driver for Qualcomm's PM8841, PM8941, and PM8916 PMICs. This driver is based largely on code from codeaurora.org[1]. [1] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/qpnp-regulator.c?h=msm-3.10 Cc: David Collins Cc: Signed-off-by: Stephen Boyd Signed-off-by: Mark Brown --- .../bindings/regulator/qcom,spmi-regulator.txt | 121 ++ drivers/regulator/Kconfig | 11 + drivers/regulator/Makefile | 1 + drivers/regulator/qcom_spmi-regulator.c | 1437 ++++++++++++++++++++ 4 files changed, 1570 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt create mode 100644 drivers/regulator/qcom_spmi-regulator.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt new file mode 100644 index 000000000000..75b4604bad07 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt @@ -0,0 +1,121 @@ +Qualcomm SPMI Regulators + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,pm8841-regulators" + "qcom,pm8916-regulators" + "qcom,pm8941-regulators" + +- interrupts: + Usage: optional + Value type: + Definition: List of OCP interrupts. + +- interrupt-names: + Usage: required if 'interrupts' property present + Value type: + Definition: List of strings defining the names of the + interrupts in the 'interrupts' property 1-to-1. + Supported values are "ocp-", where + corresponds to a voltage switch + type regulator. + +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply: +- vdd_s6-supply: +- vdd_s7-supply: +- vdd_s8-supply: + Usage: optional (pm8841 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_l1_l3-supply: +- vdd_l2-supply: +- vdd_l4_l5_l6-supply: +- vdd_l7-supply: +- vdd_l8_l11_l14_l15_l16-supply: +- vdd_l9_l10_l12_l13_l17_l18-supply: + Usage: optional (pm8916 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_l1_l3-supply: +- vdd_l2_lvs_1_2_3-supply: +- vdd_l4_l11-supply: +- vdd_l5_l7-supply: +- vdd_l6_l12_l14_l15-supply: +- vdd_l8_l16_l18_19-supply: +- vdd_l9_l10_l17_l22-supply: +- vdd_l13_l20_l23_l24-supply: +- vdd_l21-supply: +- vin_5vs-supply: + Usage: optional (pm8941 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + + +The regulator node houses sub-nodes for each regulator within the device. Each +sub-node is identified using the node's name, with valid values listed for each +of the PMICs below. + +pm8841: + s1, s2, s3, s4, s5, s6, s7, s8 + +pm8916: + s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, + l14, l15, l16, l17, l18 + +pm8941: + s1, s2, s3, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, + l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3, + mvs1, mvs2 + +The content of each sub-node is defined by the standard binding for regulators - +see regulator.txt - with additional custom properties described below: + +- regulator-initial-mode: + Usage: optional + Value type: + Descrption: 1 = Set initial mode to high power mode (HPM), also referred + to as NPM. HPM consumes more ground current than LPM, but + it can source significantly higher load current. HPM is not + available on boost type regulators. For voltage switch type + regulators, HPM implies that over current protection and + soft start are active all the time. 0 = Set initial mode to + low power mode (LPM). + +Example: + + regulators { + compatible = "qcom,pm8941-regulators"; + vdd_l1_l3-supply = <&s1>; + + s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + }; + + ... + + l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + .... + }; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index a6f116aa5235..53b3e25a98a1 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -512,6 +512,17 @@ config REGULATOR_QCOM_RPM Qualcomm RPM as a module. The module will be named "qcom_rpm-regulator". +config REGULATOR_QCOM_SPMI + tristate "Qualcomm SPMI regulator driver" + depends on SPMI || COMPILE_TEST + help + If you say yes to this option, support will be included for the + regulators found in Qualcomm SPMI PMICs. + + Say M here if you want to include support for the regulators on the + Qualcomm SPMI PMICs as a module. The module will be named + "qcom_spmi-regulator". + config REGULATOR_RC5T583 tristate "RICOH RC5T583 Power regulators" depends on MFD_RC5T583 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 2c4da15e1545..7152c979c935 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o +obj-$(CONFIG_REGULATOR_QCOM_SPMI) += qcom_spmi-regulator.o obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o obj-$(CONFIG_REGULATOR_PWM) += pwm-regulator.o diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c new file mode 100644 index 000000000000..162b86501a91 --- /dev/null +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -0,0 +1,1437 @@ +/* + * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* These types correspond to unique register layouts. */ +enum spmi_regulator_logical_type { + SPMI_REGULATOR_LOGICAL_TYPE_SMPS, + SPMI_REGULATOR_LOGICAL_TYPE_LDO, + SPMI_REGULATOR_LOGICAL_TYPE_VS, + SPMI_REGULATOR_LOGICAL_TYPE_BOOST, + SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS, + SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP, + SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO, + SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, + SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, + SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, +}; + +enum spmi_regulator_type { + SPMI_REGULATOR_TYPE_BUCK = 0x03, + SPMI_REGULATOR_TYPE_LDO = 0x04, + SPMI_REGULATOR_TYPE_VS = 0x05, + SPMI_REGULATOR_TYPE_BOOST = 0x1b, + SPMI_REGULATOR_TYPE_FTS = 0x1c, + SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f, + SPMI_REGULATOR_TYPE_ULT_LDO = 0x21, + SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22, +}; + +enum spmi_regulator_subtype { + SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08, + SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09, + SPMI_REGULATOR_SUBTYPE_N50 = 0x01, + SPMI_REGULATOR_SUBTYPE_N150 = 0x02, + SPMI_REGULATOR_SUBTYPE_N300 = 0x03, + SPMI_REGULATOR_SUBTYPE_N600 = 0x04, + SPMI_REGULATOR_SUBTYPE_N1200 = 0x05, + SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06, + SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07, + SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14, + SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15, + SPMI_REGULATOR_SUBTYPE_P50 = 0x08, + SPMI_REGULATOR_SUBTYPE_P150 = 0x09, + SPMI_REGULATOR_SUBTYPE_P300 = 0x0a, + SPMI_REGULATOR_SUBTYPE_P600 = 0x0b, + SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c, + SPMI_REGULATOR_SUBTYPE_LN = 0x10, + SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28, + SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29, + SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a, + SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b, + SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c, + SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d, + SPMI_REGULATOR_SUBTYPE_LV100 = 0x01, + SPMI_REGULATOR_SUBTYPE_LV300 = 0x02, + SPMI_REGULATOR_SUBTYPE_MV300 = 0x08, + SPMI_REGULATOR_SUBTYPE_MV500 = 0x09, + SPMI_REGULATOR_SUBTYPE_HDMI = 0x10, + SPMI_REGULATOR_SUBTYPE_OTG = 0x11, + SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, + SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, + SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, + SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, +}; + +enum spmi_common_regulator_registers { + SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01, + SPMI_COMMON_REG_TYPE = 0x04, + SPMI_COMMON_REG_SUBTYPE = 0x05, + SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40, + SPMI_COMMON_REG_VOLTAGE_SET = 0x41, + SPMI_COMMON_REG_MODE = 0x45, + SPMI_COMMON_REG_ENABLE = 0x46, + SPMI_COMMON_REG_PULL_DOWN = 0x48, + SPMI_COMMON_REG_SOFT_START = 0x4c, + SPMI_COMMON_REG_STEP_CTRL = 0x61, +}; + +enum spmi_vs_registers { + SPMI_VS_REG_OCP = 0x4a, + SPMI_VS_REG_SOFT_START = 0x4c, +}; + +enum spmi_boost_registers { + SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a, +}; + +enum spmi_boost_byp_registers { + SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, +}; + +/* Used for indexing into ctrl_reg. These are offets from 0x40 */ +enum spmi_common_control_register_index { + SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, + SPMI_COMMON_IDX_VOLTAGE_SET = 1, + SPMI_COMMON_IDX_MODE = 5, + SPMI_COMMON_IDX_ENABLE = 6, +}; + +/* Common regulator control register layout */ +#define SPMI_COMMON_ENABLE_MASK 0x80 +#define SPMI_COMMON_ENABLE 0x80 +#define SPMI_COMMON_DISABLE 0x00 +#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08 +#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04 +#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02 +#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01 +#define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f + +/* Common regulator mode register layout */ +#define SPMI_COMMON_MODE_HPM_MASK 0x80 +#define SPMI_COMMON_MODE_AUTO_MASK 0x40 +#define SPMI_COMMON_MODE_BYPASS_MASK 0x20 +#define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10 +#define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08 +#define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04 +#define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02 +#define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 +#define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f + +/* Common regulator pull down control register layout */ +#define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 + +/* LDO regulator current limit control register layout */ +#define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80 + +/* LDO regulator soft start control register layout */ +#define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80 + +/* VS regulator over current protection control register layout */ +#define SPMI_VS_OCP_OVERRIDE 0x01 +#define SPMI_VS_OCP_NO_OVERRIDE 0x00 + +/* VS regulator soft start control register layout */ +#define SPMI_VS_SOFT_START_ENABLE_MASK 0x80 +#define SPMI_VS_SOFT_START_SEL_MASK 0x03 + +/* Boost regulator current limit control register layout */ +#define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80 +#define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07 + +#define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10 +#define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30 +#define SPMI_VS_OCP_FALL_DELAY_US 90 +#define SPMI_VS_OCP_FAULT_DELAY_US 20000 + +#define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18 +#define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3 +#define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 +#define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 + +/* Clock rate in kHz of the FTSMPS regulator reference clock. */ +#define SPMI_FTSMPS_CLOCK_RATE 19200 + +/* Minimum voltage stepper delay for each step. */ +#define SPMI_FTSMPS_STEP_DELAY 8 + +/* + * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to + * adjust the step rate in order to account for oscillator variance. + */ +#define SPMI_FTSMPS_STEP_MARGIN_NUM 4 +#define SPMI_FTSMPS_STEP_MARGIN_DEN 5 + +/* + * This voltage in uV is returned by get_voltage functions when there is no way + * to determine the current voltage level. It is needed because the regulator + * framework treats a 0 uV voltage as an error. + */ +#define VOLTAGE_UNKNOWN 1 + +/* VSET value to decide the range of ULT SMPS */ +#define ULT_SMPS_RANGE_SPLIT 0x60 + +/** + * struct spmi_voltage_range - regulator set point voltage mapping description + * @min_uV: Minimum programmable output voltage resulting from + * set point register value 0x00 + * @max_uV: Maximum programmable output voltage + * @step_uV: Output voltage increase resulting from the set point + * register value increasing by 1 + * @set_point_min_uV: Minimum allowed voltage + * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order + * to pick which range should be used in the case of + * overlapping set points. + * @n_voltages: Number of preferred voltage set points present in this + * range + * @range_sel: Voltage range register value corresponding to this range + * + * The following relationships must be true for the values used in this struct: + * (max_uV - min_uV) % step_uV == 0 + * (set_point_min_uV - min_uV) % step_uV == 0* + * (set_point_max_uV - min_uV) % step_uV == 0* + * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1 + * + * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to + * specify that the voltage range has meaning, but is not preferred. + */ +struct spmi_voltage_range { + int min_uV; + int max_uV; + int step_uV; + int set_point_min_uV; + int set_point_max_uV; + unsigned n_voltages; + u8 range_sel; +}; + +/* + * The ranges specified in the spmi_voltage_set_points struct must be listed + * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV. + */ +struct spmi_voltage_set_points { + struct spmi_voltage_range *range; + int count; + unsigned n_voltages; +}; + +struct spmi_regulator { + struct regulator_desc desc; + struct device *dev; + struct delayed_work ocp_work; + struct regmap *regmap; + struct spmi_voltage_set_points *set_points; + enum spmi_regulator_logical_type logical_type; + int ocp_irq; + int ocp_count; + int ocp_max_retries; + int ocp_retry_delay_ms; + int hpm_min_load; + int slew_rate; + ktime_t vs_enable_time; + u16 base; + struct list_head node; +}; + +struct spmi_regulator_mapping { + enum spmi_regulator_type type; + enum spmi_regulator_subtype subtype; + enum spmi_regulator_logical_type logical_type; + u32 revision_min; + u32 revision_max; + struct regulator_ops *ops; + struct spmi_voltage_set_points *set_points; + int hpm_min_load; +}; + +struct spmi_regulator_data { + const char *name; + u16 base; + const char *supply; + const char *ocp; + u16 force_type; +}; + +#define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \ + _logical_type, _ops_val, _set_points_val, _hpm_min_load) \ + { \ + .type = SPMI_REGULATOR_TYPE_##_type, \ + .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ + .revision_min = _dig_major_min, \ + .revision_max = _dig_major_max, \ + .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \ + .ops = &spmi_##_ops_val##_ops, \ + .set_points = &_set_points_val##_set_points, \ + .hpm_min_load = _hpm_min_load, \ + } + +#define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \ + { \ + .type = SPMI_REGULATOR_TYPE_VS, \ + .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ + .revision_min = _dig_major_min, \ + .revision_max = _dig_major_max, \ + .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \ + .ops = &spmi_vs_ops, \ + } + +#define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \ + _set_point_max_uV, _max_uV, _step_uV) \ + { \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .set_point_min_uV = _set_point_min_uV, \ + .set_point_max_uV = _set_point_max_uV, \ + .step_uV = _step_uV, \ + .range_sel = _range_sel, \ + } + +#define DEFINE_SPMI_SET_POINTS(name) \ +struct spmi_voltage_set_points name##_set_points = { \ + .range = name##_ranges, \ + .count = ARRAY_SIZE(name##_ranges), \ +} + +/* + * These tables contain the physically available PMIC regulator voltage setpoint + * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed + * to ensure that the setpoints available to software are monotonically + * increasing and unique. The set_voltage callback functions expect these + * properties to hold. + */ +static struct spmi_voltage_range pldo_ranges[] = { + SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), + SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000), + SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000), +}; + +static struct spmi_voltage_range nldo1_ranges[] = { + SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), +}; + +static struct spmi_voltage_range nldo2_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500), + SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250), + SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500), +}; + +static struct spmi_voltage_range nldo3_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), + SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500), + SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500), +}; + +static struct spmi_voltage_range ln_ldo_ranges[] = { + SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000), + SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000), +}; + +static struct spmi_voltage_range smps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), + SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), +}; + +static struct spmi_voltage_range ftsmps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), + SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), +}; + +static struct spmi_voltage_range ftsmps2p5_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000), + SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), +}; + +static struct spmi_voltage_range boost_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), +}; + +static struct spmi_voltage_range boost_byp_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000), +}; + +static struct spmi_voltage_range ult_lo_smps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), + SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000), +}; + +static struct spmi_voltage_range ult_ho_smps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000), +}; + +static struct spmi_voltage_range ult_nldo_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), +}; + +static struct spmi_voltage_range ult_pldo_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), +}; + +static DEFINE_SPMI_SET_POINTS(pldo); +static DEFINE_SPMI_SET_POINTS(nldo1); +static DEFINE_SPMI_SET_POINTS(nldo2); +static DEFINE_SPMI_SET_POINTS(nldo3); +static DEFINE_SPMI_SET_POINTS(ln_ldo); +static DEFINE_SPMI_SET_POINTS(smps); +static DEFINE_SPMI_SET_POINTS(ftsmps); +static DEFINE_SPMI_SET_POINTS(ftsmps2p5); +static DEFINE_SPMI_SET_POINTS(boost); +static DEFINE_SPMI_SET_POINTS(boost_byp); +static DEFINE_SPMI_SET_POINTS(ult_lo_smps); +static DEFINE_SPMI_SET_POINTS(ult_ho_smps); +static DEFINE_SPMI_SET_POINTS(ult_nldo); +static DEFINE_SPMI_SET_POINTS(ult_pldo); + +static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, + int len) +{ + return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); +} + +static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr, + u8 *buf, int len) +{ + return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); +} + +static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, + u8 mask) +{ + return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); +} + +static int spmi_regulator_common_is_enabled(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 reg; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_ENABLE, ®, 1); + + return (reg & SPMI_COMMON_ENABLE_MASK) == SPMI_COMMON_ENABLE; +} + +static int spmi_regulator_common_enable(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, + SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); +} + +static int spmi_regulator_vs_enable(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + + if (vreg->ocp_irq) { + vreg->ocp_count = 0; + vreg->vs_enable_time = ktime_get(); + } + + return spmi_regulator_common_enable(rdev); +} + +static int spmi_regulator_common_disable(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, + SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); +} + +static int spmi_regulator_select_voltage(struct spmi_regulator *vreg, + int min_uV, int max_uV, u8 *range_sel, u8 *voltage_sel, + unsigned *selector) +{ + const struct spmi_voltage_range *range; + int uV = min_uV; + int lim_min_uV, lim_max_uV, i, range_id, range_max_uV; + + /* Check if request voltage is outside of physically settable range. */ + lim_min_uV = vreg->set_points->range[0].set_point_min_uV; + lim_max_uV = + vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV; + + if (uV < lim_min_uV && max_uV >= lim_min_uV) + uV = lim_min_uV; + + if (uV < lim_min_uV || uV > lim_max_uV) { + dev_err(vreg->dev, + "request v=[%d, %d] is outside possible v=[%d, %d]\n", + min_uV, max_uV, lim_min_uV, lim_max_uV); + return -EINVAL; + } + + /* Find the range which uV is inside of. */ + for (i = vreg->set_points->count - 1; i > 0; i--) { + range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV; + if (uV > range_max_uV && range_max_uV > 0) + break; + } + + range_id = i; + range = &vreg->set_points->range[range_id]; + *range_sel = range->range_sel; + + /* + * Force uV to be an allowed set point by applying a ceiling function to + * the uV value. + */ + *voltage_sel = (uV - range->min_uV + range->step_uV - 1) + / range->step_uV; + uV = *voltage_sel * range->step_uV + range->min_uV; + + if (uV > max_uV) { + dev_err(vreg->dev, + "request v=[%d, %d] cannot be met by any set point; " + "next set point: %d\n", + min_uV, max_uV, uV); + return -EINVAL; + } + + *selector = 0; + for (i = 0; i < range_id; i++) + *selector += vreg->set_points->range[i].n_voltages; + *selector += (uV - range->set_point_min_uV) / range->step_uV; + + return 0; +} + +static const struct spmi_voltage_range * +spmi_regulator_find_range(struct spmi_regulator *vreg) +{ + u8 range_sel; + const struct spmi_voltage_range *range, *end; + + range = vreg->set_points->range; + end = range + vreg->set_points->count; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1); + + for (; range < end; range++) + if (range->range_sel == range_sel) + return range; + + return NULL; +} + +static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, + int min_uV, int max_uV, u8 *range_sel, u8 *voltage_sel, + unsigned *selector) +{ + const struct spmi_voltage_range *range; + int uV = min_uV; + int i; + + range = spmi_regulator_find_range(vreg); + if (!range) + goto different_range; + + if (uV < range->min_uV && max_uV >= range->min_uV) + uV = range->min_uV; + + if (uV < range->min_uV || uV > range->max_uV) { + /* Current range doesn't support the requested voltage. */ + goto different_range; + } + + /* + * Force uV to be an allowed set point by applying a ceiling function to + * the uV value. + */ + *voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); + uV = *voltage_sel * range->step_uV + range->min_uV; + + if (uV > max_uV) { + /* + * No set point in the current voltage range is within the + * requested min_uV to max_uV range. + */ + goto different_range; + } + + *selector = 0; + for (i = 0; i < vreg->set_points->count; i++) { + if (uV >= vreg->set_points->range[i].set_point_min_uV + && uV <= vreg->set_points->range[i].set_point_max_uV) + *selector += + (uV - vreg->set_points->range[i].set_point_min_uV) + / vreg->set_points->range[i].step_uV; + break; + + *selector += vreg->set_points->range[i].n_voltages; + } + + if (*selector >= vreg->set_points->n_voltages) + goto different_range; + + return 0; + +different_range: + return spmi_regulator_select_voltage(vreg, min_uV, max_uV, + range_sel, voltage_sel, selector); +} + +static int spmi_regulator_common_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, unsigned *selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + int ret; + u8 buf[2]; + u8 range_sel, voltage_sel; + + /* + * Favor staying in the current voltage range if possible. This avoids + * voltage spikes that occur when changing the voltage range. + */ + ret = spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV, + &range_sel, &voltage_sel, selector); + if (ret) + return ret; + + buf[0] = range_sel; + buf[1] = voltage_sel; + return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); +} + +static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, + unsigned int old_selector, unsigned int new_selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + const struct spmi_voltage_range *range; + int diff_uV; + + range = spmi_regulator_find_range(vreg); + if (!range) + return -EINVAL; + + diff_uV = abs(new_selector - old_selector) * range->step_uV; + + return DIV_ROUND_UP(diff_uV, vreg->slew_rate); +} + +static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + const struct spmi_voltage_range *range; + u8 voltage_sel; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); + + range = spmi_regulator_find_range(vreg); + if (!range) + return VOLTAGE_UNKNOWN; + + return range->step_uV * voltage_sel + range->min_uV; +} + +static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, unsigned *selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + int ret; + u8 range_sel, sel; + + ret = spmi_regulator_select_voltage(vreg, min_uV, max_uV, &range_sel, + &sel, selector); + if (ret) { + dev_err(vreg->dev, "could not set voltage, ret=%d\n", ret); + return ret; + } + + /* + * Certain types of regulators do not have a range select register so + * only voltage set register needs to be written. + */ + return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1); +} + +static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + const struct spmi_voltage_range *range = vreg->set_points->range; + u8 voltage_sel; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); + + return range->step_uV * voltage_sel + range->min_uV; +} + +static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, unsigned *selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + int ret; + u8 range_sel, voltage_sel; + + /* + * Favor staying in the current voltage range if possible. This avoids + * voltage spikes that occur when changing the voltage range. + */ + ret = spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV, + &range_sel, &voltage_sel, selector); + if (ret) + return ret; + + /* + * Calculate VSET based on range + * In case of range 0: voltage_sel is a 7 bit value, can be written + * witout any modification. + * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to + * [011]. + */ + if (range_sel == 1) + voltage_sel |= ULT_SMPS_RANGE_SPLIT; + + ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET, + voltage_sel, 0xff); + if (ret) + return ret; + + return 0; +} + +static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + const struct spmi_voltage_range *range; + u8 voltage_sel; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); + + range = spmi_regulator_find_range(vreg); + if (!range) + return VOLTAGE_UNKNOWN; + + if (range->range_sel == 1) + voltage_sel &= ~ULT_SMPS_RANGE_SPLIT; + + return range->step_uV * voltage_sel + range->min_uV; +} + +static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, + unsigned selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + int uV = 0; + int i; + + if (selector >= vreg->set_points->n_voltages) + return 0; + + for (i = 0; i < vreg->set_points->count; i++) { + if (selector < vreg->set_points->range[i].n_voltages) + uV = selector * vreg->set_points->range[i].step_uV + + vreg->set_points->range[i].set_point_min_uV; + break; + + selector -= vreg->set_points->range[i].n_voltages; + } + + return uV; +} + +static int +spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; + u8 val = 0; + + if (enable) + val = mask; + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); +} + +static int +spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 val; + int ret; + + ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); + *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; + + return ret; +} + +static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 reg; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); + + if (reg & SPMI_COMMON_MODE_HPM_MASK) + return REGULATOR_MODE_NORMAL; + + return REGULATOR_MODE_IDLE; +} + +static int +spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 mask = SPMI_COMMON_MODE_HPM_MASK; + u8 val = 0; + + if (mode == REGULATOR_MODE_NORMAL) + val = mask; + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); +} + +static int +spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + unsigned int mode; + + if (load_uA >= vreg->hpm_min_load) + mode = REGULATOR_MODE_NORMAL; + else + mode = REGULATOR_MODE_IDLE; + + return spmi_regulator_common_set_mode(rdev, mode); +} + +static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, + mask, mask); +} + +static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START, + mask, mask); +} + +static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + enum spmi_regulator_logical_type type = vreg->logical_type; + unsigned int current_reg; + u8 reg; + u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | + SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; + int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500; + + if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST) + current_reg = SPMI_BOOST_REG_CURRENT_LIMIT; + else + current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT; + + if (ilim_uA > max || ilim_uA <= 0) + return -EINVAL; + + reg = (ilim_uA - 1) / 500; + reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; + + return spmi_vreg_update_bits(vreg, current_reg, reg, mask); +} + +static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg) +{ + int ret; + + ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, + SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); + + vreg->vs_enable_time = ktime_get(); + + ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, + SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); + + return ret; +} + +static void spmi_regulator_vs_ocp_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct spmi_regulator *vreg + = container_of(dwork, struct spmi_regulator, ocp_work); + + spmi_regulator_vs_clear_ocp(vreg); +} + +static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) +{ + struct spmi_regulator *vreg = data; + ktime_t ocp_irq_time; + s64 ocp_trigger_delay_us; + + ocp_irq_time = ktime_get(); + ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time, + vreg->vs_enable_time); + + /* + * Reset the OCP count if there is a large delay between switch enable + * and when OCP triggers. This is indicative of a hotplug event as + * opposed to a fault. + */ + if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US) + vreg->ocp_count = 0; + + /* Wait for switch output to settle back to 0 V after OCP triggered. */ + udelay(SPMI_VS_OCP_FALL_DELAY_US); + + vreg->ocp_count++; + + if (vreg->ocp_count == 1) { + /* Immediately clear the over current condition. */ + spmi_regulator_vs_clear_ocp(vreg); + } else if (vreg->ocp_count <= vreg->ocp_max_retries) { + /* Schedule the over current clear task to run later. */ + schedule_delayed_work(&vreg->ocp_work, + msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1); + } else { + dev_err(vreg->dev, + "OCP triggered %d times; no further retries\n", + vreg->ocp_count); + } + + return IRQ_HANDLED; +} + +static struct regulator_ops spmi_smps_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_common_set_voltage, + .get_voltage = spmi_regulator_common_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_common_set_mode, + .get_mode = spmi_regulator_common_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_pull_down = spmi_regulator_common_set_pull_down, +}; + +static struct regulator_ops spmi_ldo_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_common_set_voltage, + .get_voltage = spmi_regulator_common_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_common_set_mode, + .get_mode = spmi_regulator_common_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_bypass = spmi_regulator_common_set_bypass, + .get_bypass = spmi_regulator_common_get_bypass, + .set_pull_down = spmi_regulator_common_set_pull_down, + .set_soft_start = spmi_regulator_common_set_soft_start, +}; + +static struct regulator_ops spmi_ln_ldo_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_common_set_voltage, + .get_voltage = spmi_regulator_common_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_bypass = spmi_regulator_common_set_bypass, + .get_bypass = spmi_regulator_common_get_bypass, +}; + +static struct regulator_ops spmi_vs_ops = { + .enable = spmi_regulator_vs_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_pull_down = spmi_regulator_common_set_pull_down, + .set_soft_start = spmi_regulator_common_set_soft_start, +}; + +static struct regulator_ops spmi_boost_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_single_range_set_voltage, + .get_voltage = spmi_regulator_single_range_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_input_current_limit = spmi_regulator_set_ilim, +}; + +static struct regulator_ops spmi_ftsmps_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_common_set_voltage, + .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, + .get_voltage = spmi_regulator_common_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_common_set_mode, + .get_mode = spmi_regulator_common_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_pull_down = spmi_regulator_common_set_pull_down, +}; + +static struct regulator_ops spmi_ult_lo_smps_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_ult_lo_smps_set_voltage, + .get_voltage = spmi_regulator_ult_lo_smps_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_common_set_mode, + .get_mode = spmi_regulator_common_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_pull_down = spmi_regulator_common_set_pull_down, +}; + +static struct regulator_ops spmi_ult_ho_smps_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_single_range_set_voltage, + .get_voltage = spmi_regulator_single_range_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_common_set_mode, + .get_mode = spmi_regulator_common_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_pull_down = spmi_regulator_common_set_pull_down, +}; + +static struct regulator_ops spmi_ult_ldo_ops = { + .enable = spmi_regulator_common_enable, + .disable = spmi_regulator_common_disable, + .is_enabled = spmi_regulator_common_is_enabled, + .set_voltage = spmi_regulator_single_range_set_voltage, + .get_voltage = spmi_regulator_single_range_get_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_common_set_mode, + .get_mode = spmi_regulator_common_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_bypass = spmi_regulator_common_set_bypass, + .get_bypass = spmi_regulator_common_get_bypass, + .set_pull_down = spmi_regulator_common_set_pull_down, + .set_soft_start = spmi_regulator_common_set_soft_start, +}; + +/* Maximum possible digital major revision value */ +#define INF 0xFF + +static const struct spmi_regulator_mapping supported_regulators[] = { + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), + SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), + SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), + SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000), + SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000), + SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000), + SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000), + SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000), + SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000), + SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000), + SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0), + SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000), + SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG_VS(LV100, 0, INF), + SPMI_VREG_VS(LV300, 0, INF), + SPMI_VREG_VS(MV300, 0, INF), + SPMI_VREG_VS(MV500, 0, INF), + SPMI_VREG_VS(HDMI, 0, INF), + SPMI_VREG_VS(OTG, 0, INF), + SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), + SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), + SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), + SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), + SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, + ult_lo_smps, 100000), + SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps, + ult_lo_smps, 100000), + SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps, + ult_lo_smps, 100000), + SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps, + ult_ho_smps, 100000), + SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), + SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), + SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), + SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), + SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), + SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), + SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), + SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), + SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), + SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), +}; + +static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) +{ + unsigned int n; + struct spmi_voltage_range *range = points->range; + + for (; range < points->range + points->count; range++) { + n = 0; + if (range->set_point_max_uV) { + n = range->set_point_max_uV - range->set_point_min_uV; + n /= range->step_uV + 1; + } + range->n_voltages = n; + points->n_voltages += n; + } +} + +static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) +{ + const struct spmi_regulator_mapping *mapping; + int ret, i; + u32 dig_major_rev; + u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1]; + u8 type, subtype; + + ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version, + ARRAY_SIZE(version)); + if (ret) { + dev_err(vreg->dev, "could not read version registers\n"); + return ret; + } + dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV + - SPMI_COMMON_REG_DIG_MAJOR_REV]; + if (!force_type) { + type = version[SPMI_COMMON_REG_TYPE - + SPMI_COMMON_REG_DIG_MAJOR_REV]; + subtype = version[SPMI_COMMON_REG_SUBTYPE - + SPMI_COMMON_REG_DIG_MAJOR_REV]; + } else { + type = force_type >> 8; + subtype = force_type; + } + + for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { + mapping = &supported_regulators[i]; + if (mapping->type == type && mapping->subtype == subtype + && mapping->revision_min <= dig_major_rev + && mapping->revision_max >= dig_major_rev) + goto found; + } + + dev_err(vreg->dev, + "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", + vreg->desc.name, type, subtype, dig_major_rev); + + return -ENODEV; + +found: + vreg->logical_type = mapping->logical_type; + vreg->set_points = mapping->set_points; + vreg->hpm_min_load = mapping->hpm_min_load; + vreg->desc.ops = mapping->ops; + + if (mapping->set_points) { + if (!mapping->set_points->n_voltages) + spmi_calculate_num_voltages(mapping->set_points); + vreg->desc.n_voltages = mapping->set_points->n_voltages; + } + + return 0; +} + +static int spmi_regulator_ftsmps_init_slew_rate(struct spmi_regulator *vreg) +{ + int ret; + u8 reg = 0; + int step, delay, slew_rate; + const struct spmi_voltage_range *range; + + ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); + if (ret) { + dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); + return ret; + } + + range = spmi_regulator_find_range(vreg); + if (!range) + return -EINVAL; + + step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; + step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT; + + delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; + delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT; + + /* slew_rate has units of uV/us */ + slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step); + slew_rate /= 1000 * (SPMI_FTSMPS_STEP_DELAY << delay); + slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM; + slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN; + + /* Ensure that the slew rate is greater than 0 */ + vreg->slew_rate = max(slew_rate, 1); + + return ret; +} + +static unsigned int spmi_regulator_of_map_mode(unsigned int mode) +{ + if (mode) + return REGULATOR_MODE_NORMAL; + + return REGULATOR_MODE_IDLE; +} + +static int spmi_regulator_of_parse(struct device_node *node, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + struct spmi_regulator *vreg = config->driver_data; + struct device *dev = config->dev; + int ret; + + vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES; + vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS; + + if (vreg->logical_type == SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS) { + ret = spmi_regulator_ftsmps_init_slew_rate(vreg); + if (ret) + return ret; + } + + if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS) + vreg->ocp_irq = 0; + + if (vreg->ocp_irq) { + ret = devm_request_irq(dev, vreg->ocp_irq, + spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp", + vreg); + if (ret < 0) { + dev_err(dev, "failed to request irq %d, ret=%d\n", + vreg->ocp_irq, ret); + return ret; + } + + INIT_DELAYED_WORK(&vreg->ocp_work, spmi_regulator_vs_ocp_work); + } + + return 0; +} + +static const struct spmi_regulator_data pm8941_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "l1", 0x4000, "vdd_l1_l3", }, + { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, + { "l3", 0x4200, "vdd_l1_l3", }, + { "l4", 0x4300, "vdd_l4_l11", }, + { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, + { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, + { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, + { "l8", 0x4700, "vdd_l8_l16_l18_19", }, + { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, + { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, + { "l11", 0x4a00, "vdd_l4_l11", }, + { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, + { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, + { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, + { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, + { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, + { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, + { "l18", 0x5100, "vdd_l8_l16_l18_19", }, + { "l19", 0x5200, "vdd_l8_l16_l18_19", }, + { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, + { "l21", 0x5400, "vdd_l21", }, + { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, + { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, + { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, + { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, + { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, + { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, + { "mvs1", 0x8300, "vin_5vs", }, + { "mvs2", 0x8400, "vin_5vs", }, + { } +}; + +static const struct spmi_regulator_data pm8841_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 }, + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 }, + { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 }, + { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 }, + { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 }, + { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 }, + { } +}; + +static const struct spmi_regulator_data pm8916_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0x1d00, "vdd_s4", }, + { "l1", 0x4000, "vdd_l1_l3", }, + { "l2", 0x4100, "vdd_l2", }, + { "l3", 0x4200, "vdd_l1_l3", }, + { "l4", 0x4300, "vdd_l4_l5_l6", }, + { "l5", 0x4400, "vdd_l4_l5_l6", }, + { "l6", 0x4500, "vdd_l4_l5_l6", }, + { "l7", 0x4600, "vdd_l7", }, + { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", }, + { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", }, + { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", }, + { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", }, + { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", }, + { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", }, + { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", }, + { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", }, + { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, + { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, + { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, + { } +}; + +static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, + { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, + { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); + +static int qcom_spmi_regulator_probe(struct platform_device *pdev) +{ + const struct spmi_regulator_data *reg; + const struct of_device_id *match; + struct regulator_config config = { }; + struct regulator_dev *rdev; + struct spmi_regulator *vreg; + struct regmap *regmap; + const char *name; + struct device *dev = &pdev->dev; + int ret; + struct list_head *vreg_list; + + vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); + if (!vreg_list) + return -ENOMEM; + INIT_LIST_HEAD(vreg_list); + platform_set_drvdata(pdev, vreg_list); + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + match = of_match_device(qcom_spmi_regulator_match, &pdev->dev); + if (!match) + return -ENODEV; + + for (reg = match->data; reg->name; reg++) { + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) + return -ENOMEM; + + vreg->dev = dev; + vreg->base = reg->base; + vreg->regmap = regmap; + + if (reg->ocp) { + vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); + if (vreg->ocp_irq < 0) { + ret = vreg->ocp_irq; + goto err; + } + } + + vreg->desc.id = -1; + vreg->desc.owner = THIS_MODULE; + vreg->desc.type = REGULATOR_VOLTAGE; + vreg->desc.name = name = reg->name; + vreg->desc.supply_name = reg->supply; + vreg->desc.of_match = reg->name; + vreg->desc.of_parse_cb = spmi_regulator_of_parse; + vreg->desc.of_map_mode = spmi_regulator_of_map_mode; + + ret = spmi_regulator_match(vreg, reg->force_type); + if (ret) + goto err; + + config.dev = dev; + config.driver_data = vreg; + rdev = devm_regulator_register(dev, &vreg->desc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register %s\n", name); + ret = PTR_ERR(rdev); + goto err; + } + + INIT_LIST_HEAD(&vreg->node); + list_add(&vreg->node, vreg_list); + } + + return 0; + +err: + list_for_each_entry(vreg, vreg_list, node) + if (vreg->ocp_irq) + cancel_delayed_work_sync(&vreg->ocp_work); + return ret; +} + +static int qcom_spmi_regulator_remove(struct platform_device *pdev) +{ + struct spmi_regulator *vreg; + struct list_head *vreg_list = platform_get_drvdata(pdev); + + list_for_each_entry(vreg, vreg_list, node) + if (vreg->ocp_irq) + cancel_delayed_work_sync(&vreg->ocp_work); + + return 0; +} + +static struct platform_driver qcom_spmi_regulator_driver = { + .driver = { + .name = "qcom-spmi-regulator", + .of_match_table = qcom_spmi_regulator_match, + }, + .probe = qcom_spmi_regulator_probe, + .remove = qcom_spmi_regulator_remove, +}; +module_platform_driver(qcom_spmi_regulator_driver); + +MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:qcom-spmi-regulator"); -- cgit v1.2.3 From ee0bcaff109f36d582df9851f204c9a5eb79c028 Mon Sep 17 00:00:00 2001 From: Koro Chen Date: Mon, 15 Jun 2015 22:38:02 +0800 Subject: ASoC: mediatek: Add AFE platform driver This is the DPCM based platform driver of AFE (Audio Front End) unit. Signed-off-by: Sascha Hauer Signed-off-by: Koro Chen Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/mtk-afe-pcm.txt | 45 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/mediatek/Kconfig | 9 + sound/soc/mediatek/Makefile | 2 + sound/soc/mediatek/mtk-afe-common.h | 109 ++ sound/soc/mediatek/mtk-afe-pcm.c | 1233 ++++++++++++++++++++ 7 files changed, 1400 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt create mode 100644 sound/soc/mediatek/Kconfig create mode 100644 sound/soc/mediatek/Makefile create mode 100644 sound/soc/mediatek/mtk-afe-common.h create mode 100644 sound/soc/mediatek/mtk-afe-pcm.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt new file mode 100644 index 000000000000..e302c7f43b95 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mtk-afe-pcm.txt @@ -0,0 +1,45 @@ +Mediatek AFE PCM controller + +Required properties: +- compatible = "mediatek,mt8173-afe-pcm"; +- reg: register location and size +- interrupts: Should contain AFE interrupt +- clock-names: should have these clock names: + "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + +Example: + + afe: mt8173-afe-pcm@11220000 { + compatible = "mediatek,mt8173-afe-pcm"; + reg = <0 0x11220000 0 0x1000>; + interrupts = ; + clocks = <&infracfg INFRA_AUDIO>, + <&topckgen TOP_AUDIO_SEL>, + <&topckgen TOP_AUD_INTBUS_SEL>, + <&topckgen TOP_APLL1_DIV0>, + <&topckgen TOP_APLL2_DIV0>, + <&topckgen TOP_I2S0_M_CK_SEL>, + <&topckgen TOP_I2S1_M_CK_SEL>, + <&topckgen TOP_I2S2_M_CK_SEL>, + <&topckgen TOP_I2S3_M_CK_SEL>, + <&topckgen TOP_I2S3_B_CK_SEL>; + clock-names = "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + }; diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 3ba52da18bc6..cc1b71875b26 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -45,6 +45,7 @@ source "sound/soc/nuc900/Kconfig" source "sound/soc/omap/Kconfig" source "sound/soc/kirkwood/Kconfig" source "sound/soc/intel/Kconfig" +source "sound/soc/mediatek/Kconfig" source "sound/soc/mxs/Kconfig" source "sound/soc/pxa/Kconfig" source "sound/soc/qcom/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 974ba708b482..e5526338aeda 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_SND_SOC) += dwc/ obj-$(CONFIG_SND_SOC) += fsl/ obj-$(CONFIG_SND_SOC) += jz4740/ obj-$(CONFIG_SND_SOC) += intel/ +obj-$(CONFIG_SND_SOC) += mediatek/ obj-$(CONFIG_SND_SOC) += mxs/ obj-$(CONFIG_SND_SOC) += nuc900/ obj-$(CONFIG_SND_SOC) += omap/ diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig new file mode 100644 index 000000000000..c622280cacd9 --- /dev/null +++ b/sound/soc/mediatek/Kconfig @@ -0,0 +1,9 @@ +config SND_SOC_MEDIATEK + tristate "ASoC support for Mediatek chip" + depends on ARCH_MEDIATEK + help + This adds ASoC platform driver support for Mediatek chip + that can be used with other codecs. + Select Y if you have such device. + Ex: MT8173 + diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile new file mode 100644 index 000000000000..5f27cc772f66 --- /dev/null +++ b/sound/soc/mediatek/Makefile @@ -0,0 +1,2 @@ +# MTK Platform Support +obj-$(CONFIG_SND_SOC_MEDIATEK) += mtk-afe-pcm.o diff --git a/sound/soc/mediatek/mtk-afe-common.h b/sound/soc/mediatek/mtk-afe-common.h new file mode 100644 index 000000000000..a88b17511fdf --- /dev/null +++ b/sound/soc/mediatek/mtk-afe-common.h @@ -0,0 +1,109 @@ +/* + * mtk_afe_common.h -- Mediatek audio driver common definitions + * + * Copyright (c) 2015 MediaTek Inc. + * Author: Koro Chen + * Sascha Hauer + * Hidalgo Huang + * Ir Lian + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MTK_AFE_COMMON_H_ +#define _MTK_AFE_COMMON_H_ + +#include +#include + +enum { + MTK_AFE_MEMIF_DL1, + MTK_AFE_MEMIF_DL2, + MTK_AFE_MEMIF_VUL, + MTK_AFE_MEMIF_DAI, + MTK_AFE_MEMIF_AWB, + MTK_AFE_MEMIF_MOD_DAI, + MTK_AFE_MEMIF_HDMI, + MTK_AFE_MEMIF_NUM, + MTK_AFE_IO_MOD_PCM1 = MTK_AFE_MEMIF_NUM, + MTK_AFE_IO_MOD_PCM2, + MTK_AFE_IO_PMIC, + MTK_AFE_IO_I2S, + MTK_AFE_IO_2ND_I2S, + MTK_AFE_IO_HW_GAIN1, + MTK_AFE_IO_HW_GAIN2, + MTK_AFE_IO_MRG_O, + MTK_AFE_IO_MRG_I, + MTK_AFE_IO_DAIBT, + MTK_AFE_IO_HDMI, +}; + +enum { + MTK_AFE_IRQ_1, + MTK_AFE_IRQ_2, + MTK_AFE_IRQ_3, + MTK_AFE_IRQ_4, + MTK_AFE_IRQ_5, + MTK_AFE_IRQ_6, + MTK_AFE_IRQ_7, + MTK_AFE_IRQ_8, + MTK_AFE_IRQ_NUM, +}; + +enum { + MTK_CLK_INFRASYS_AUD, + MTK_CLK_TOP_PDN_AUD, + MTK_CLK_TOP_PDN_AUD_BUS, + MTK_CLK_I2S0_M, + MTK_CLK_I2S1_M, + MTK_CLK_I2S2_M, + MTK_CLK_I2S3_M, + MTK_CLK_I2S3_B, + MTK_CLK_BCK0, + MTK_CLK_BCK1, + MTK_CLK_NUM +}; + +struct mtk_afe; +struct snd_pcm_substream; + +struct mtk_afe_memif_data { + int id; + const char *name; + int reg_ofs_base; + int reg_ofs_cur; + int fs_shift; + int mono_shift; + int enable_shift; + int irq_reg_cnt; + int irq_cnt_shift; + int irq_en_shift; + int irq_fs_shift; + int irq_clr_shift; +}; + +struct mtk_afe_memif { + unsigned int phys_buf_addr; + int buffer_size; + unsigned int hw_ptr; /* Previous IRQ's HW ptr */ + struct snd_pcm_substream *substream; + const struct mtk_afe_memif_data *data; + const struct mtk_afe_irq_data *irqdata; +}; + +struct mtk_afe { + /* address for ioremap audio hardware register */ + void __iomem *base_addr; + struct device *dev; + struct regmap *regmap; + struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM]; + struct clk *clocks[MTK_CLK_NUM]; +}; +#endif diff --git a/sound/soc/mediatek/mtk-afe-pcm.c b/sound/soc/mediatek/mtk-afe-pcm.c new file mode 100644 index 000000000000..cc228db5fb76 --- /dev/null +++ b/sound/soc/mediatek/mtk-afe-pcm.c @@ -0,0 +1,1233 @@ +/* + * Mediatek ALSA SoC AFE platform driver + * + * Copyright (c) 2015 MediaTek Inc. + * Author: Koro Chen + * Sascha Hauer + * Hidalgo Huang + * Ir Lian + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "mtk-afe-common.h" + +/***************************************************************************** + * R E G I S T E R D E F I N I T I O N + *****************************************************************************/ +#define AUDIO_TOP_CON0 0x0000 +#define AUDIO_TOP_CON1 0x0004 +#define AFE_DAC_CON0 0x0010 +#define AFE_DAC_CON1 0x0014 +#define AFE_I2S_CON1 0x0034 +#define AFE_I2S_CON2 0x0038 +#define AFE_CONN_24BIT 0x006c + +#define AFE_CONN1 0x0024 +#define AFE_CONN2 0x0028 +#define AFE_CONN7 0x0460 +#define AFE_CONN8 0x0464 +#define AFE_HDMI_CONN0 0x0390 + +/* Memory interface */ +#define AFE_DL1_BASE 0x0040 +#define AFE_DL1_CUR 0x0044 +#define AFE_DL2_BASE 0x0050 +#define AFE_DL2_CUR 0x0054 +#define AFE_AWB_BASE 0x0070 +#define AFE_AWB_CUR 0x007c +#define AFE_VUL_BASE 0x0080 +#define AFE_VUL_CUR 0x008c +#define AFE_DAI_BASE 0x0090 +#define AFE_DAI_CUR 0x009c +#define AFE_MOD_PCM_BASE 0x0330 +#define AFE_MOD_PCM_CUR 0x033c +#define AFE_HDMI_OUT_BASE 0x0374 +#define AFE_HDMI_OUT_CUR 0x0378 + +#define AFE_ADDA2_TOP_CON0 0x0600 + +#define AFE_HDMI_OUT_CON0 0x0370 + +#define AFE_IRQ_MCU_CON 0x03a0 +#define AFE_IRQ_STATUS 0x03a4 +#define AFE_IRQ_CLR 0x03a8 +#define AFE_IRQ_CNT1 0x03ac +#define AFE_IRQ_CNT2 0x03b0 +#define AFE_IRQ_MCU_EN 0x03b4 +#define AFE_IRQ_CNT5 0x03bc +#define AFE_IRQ_CNT7 0x03dc + +#define AFE_TDM_CON1 0x0548 +#define AFE_TDM_CON2 0x054c + +#define AFE_BASE_END_OFFSET 8 +#define AFE_IRQ_STATUS_BITS 0xff + +/* AUDIO_TOP_CON0 (0x0000) */ +#define AUD_TCON0_PDN_SPDF (0x1 << 21) +#define AUD_TCON0_PDN_HDMI (0x1 << 20) +#define AUD_TCON0_PDN_24M (0x1 << 9) +#define AUD_TCON0_PDN_22M (0x1 << 8) +#define AUD_TCON0_PDN_AFE (0x1 << 2) + +/* AFE_I2S_CON1 (0x0034) */ +#define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12) +#define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8) +#define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3) +#define AFE_I2S_CON1_EN (0x1 << 0) + +/* AFE_I2S_CON2 (0x0038) */ +#define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12) +#define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8) +#define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3) +#define AFE_I2S_CON2_EN (0x1 << 0) + +/* AFE_CONN_24BIT (0x006c) */ +#define AFE_CONN_24BIT_O04 (0x1 << 4) +#define AFE_CONN_24BIT_O03 (0x1 << 3) + +/* AFE_HDMI_CONN0 (0x0390) */ +#define AFE_HDMI_CONN0_O37_I37 (0x7 << 21) +#define AFE_HDMI_CONN0_O36_I36 (0x6 << 18) +#define AFE_HDMI_CONN0_O35_I33 (0x3 << 15) +#define AFE_HDMI_CONN0_O34_I32 (0x2 << 12) +#define AFE_HDMI_CONN0_O33_I35 (0x5 << 9) +#define AFE_HDMI_CONN0_O32_I34 (0x4 << 6) +#define AFE_HDMI_CONN0_O31_I31 (0x1 << 3) +#define AFE_HDMI_CONN0_O30_I30 (0x0 << 0) + +/* AFE_TDM_CON1 (0x0548) */ +#define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24) +#define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12) +#define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8) +#define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4) +#define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3) +#define AFE_TDM_CON1_BCK_INV (0x1 << 1) +#define AFE_TDM_CON1_EN (0x1 << 0) + +enum afe_tdm_ch_start { + AFE_TDM_CH_START_O30_O31 = 0, + AFE_TDM_CH_START_O32_O33, + AFE_TDM_CH_START_O34_O35, + AFE_TDM_CH_START_O36_O37, + AFE_TDM_CH_ZERO, +}; + +static const struct snd_pcm_hardware mtk_afe_hardware = { + .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID), + .buffer_bytes_max = 256 * 1024, + .period_bytes_min = 512, + .period_bytes_max = 128 * 1024, + .periods_min = 2, + .periods_max = 256, + .fifo_size = 0, +}; + +static snd_pcm_uframes_t mtk_afe_pcm_pointer + (struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; + + return bytes_to_frames(substream->runtime, memif->hw_ptr); +} + +static const struct snd_pcm_ops mtk_afe_pcm_ops = { + .ioctl = snd_pcm_lib_ioctl, + .pointer = mtk_afe_pcm_pointer, +}; + +static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd) +{ + size_t size; + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; + + size = mtk_afe_hardware.buffer_bytes_max; + + return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, + card->dev, size, size); +} + +static void mtk_afe_pcm_free(struct snd_pcm *pcm) +{ + snd_pcm_lib_preallocate_free_for_all(pcm); +} + +static const struct snd_soc_platform_driver mtk_afe_pcm_platform = { + .ops = &mtk_afe_pcm_ops, + .pcm_new = mtk_afe_pcm_new, + .pcm_free = mtk_afe_pcm_free, +}; + +struct mtk_afe_rate { + unsigned int rate; + unsigned int regvalue; +}; + +static const struct mtk_afe_rate mtk_afe_i2s_rates[] = { + { .rate = 8000, .regvalue = 0 }, + { .rate = 11025, .regvalue = 1 }, + { .rate = 12000, .regvalue = 2 }, + { .rate = 16000, .regvalue = 4 }, + { .rate = 22050, .regvalue = 5 }, + { .rate = 24000, .regvalue = 6 }, + { .rate = 32000, .regvalue = 8 }, + { .rate = 44100, .regvalue = 9 }, + { .rate = 48000, .regvalue = 10 }, + { .rate = 88000, .regvalue = 11 }, + { .rate = 96000, .regvalue = 12 }, + { .rate = 174000, .regvalue = 13 }, + { .rate = 192000, .regvalue = 14 }, +}; + +static int mtk_afe_i2s_fs(unsigned int sample_rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++) + if (mtk_afe_i2s_rates[i].rate == sample_rate) + return mtk_afe_i2s_rates[i].regvalue; + + return -EINVAL; +} + +static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate) +{ + unsigned int val; + int fs = mtk_afe_i2s_fs(rate); + + if (fs < 0) + return -EINVAL; + + /* from external ADC */ + regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1); + + /* set input */ + val = AFE_I2S_CON2_LOW_JITTER_CLK | + AFE_I2S_CON2_RATE(fs) | + AFE_I2S_CON2_FORMAT_I2S; + + regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val); + + /* set output */ + val = AFE_I2S_CON1_LOW_JITTER_CLK | + AFE_I2S_CON1_RATE(fs) | + AFE_I2S_CON1_FORMAT_I2S; + + regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val); + return 0; +} + +static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable) +{ + unsigned int val; + + regmap_read(afe->regmap, AFE_I2S_CON2, &val); + if (!!(val & AFE_I2S_CON2_EN) == enable) + return; /* must skip soft reset */ + + /* I2S soft reset begin */ + regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4); + + /* input */ + regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable); + + /* output */ + regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable); + + /* I2S soft reset end */ + udelay(1); + regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0); +} + +static int mtk_afe_dais_enable_clks(struct mtk_afe *afe, + struct clk *m_ck, struct clk *b_ck) +{ + int ret; + + if (m_ck) { + ret = clk_prepare_enable(m_ck); + if (ret) { + dev_err(afe->dev, "Failed to enable m_ck\n"); + return ret; + } + regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, + AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0); + } + + if (b_ck) { + ret = clk_prepare_enable(b_ck); + if (ret) { + dev_err(afe->dev, "Failed to enable b_ck\n"); + return ret; + } + } + return 0; +} + +static int mtk_afe_dais_set_clks(struct mtk_afe *afe, + struct clk *m_ck, unsigned int mck_rate, + struct clk *b_ck, unsigned int bck_rate) +{ + int ret; + + if (m_ck) { + ret = clk_set_rate(m_ck, mck_rate); + if (ret) { + dev_err(afe->dev, "Failed to set m_ck rate\n"); + return ret; + } + } + + if (b_ck) { + ret = clk_set_rate(b_ck, bck_rate); + if (ret) { + dev_err(afe->dev, "Failed to set b_ck rate\n"); + return ret; + } + } + return 0; +} + +static void mtk_afe_dais_disable_clks(struct mtk_afe *afe, + struct clk *m_ck, struct clk *b_ck) +{ + if (m_ck) { + regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, + AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, + AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M); + clk_disable_unprepare(m_ck); + } + if (b_ck) + clk_disable_unprepare(b_ck); +} + +static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + + if (dai->active) + return 0; + + mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL); + return 0; +} + +static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + + if (dai->active) + return; + + mtk_afe_set_i2s_enable(afe, false); + mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL); + + /* disable AFE */ + regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0); +} + +static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_pcm_runtime * const runtime = substream->runtime; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + int ret; + + mtk_afe_dais_set_clks(afe, + afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256, + NULL, 0); + /* config I2S */ + ret = mtk_afe_set_i2s(afe, substream->runtime->rate); + if (ret) + return ret; + + mtk_afe_set_i2s_enable(afe, true); + + return 0; +} + +static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + + if (dai->active) + return 0; + + mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M], + afe->clocks[MTK_CLK_I2S3_B]); + return 0; +} + +static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + + if (dai->active) + return; + + mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M], + afe->clocks[MTK_CLK_I2S3_B]); + + /* disable AFE */ + regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0); +} + +static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_pcm_runtime * const runtime = substream->runtime; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + unsigned int val; + + mtk_afe_dais_set_clks(afe, + afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128, + afe->clocks[MTK_CLK_I2S3_B], + runtime->rate * runtime->channels * 32); + + val = AFE_TDM_CON1_BCK_INV | + AFE_TDM_CON1_1_BCK_DELAY | + AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */ + AFE_TDM_CON1_WLEN_32BIT | + AFE_TDM_CON1_32_BCK_CYCLES | + AFE_TDM_CON1_LRCK_WIDTH(32); + regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val); + + /* set tdm2 config */ + switch (runtime->channels) { + case 1: + case 2: + val = AFE_TDM_CH_START_O30_O31; + val |= (AFE_TDM_CH_ZERO << 4); + val |= (AFE_TDM_CH_ZERO << 8); + val |= (AFE_TDM_CH_ZERO << 12); + break; + case 3: + case 4: + val = AFE_TDM_CH_START_O30_O31; + val |= (AFE_TDM_CH_START_O32_O33 << 4); + val |= (AFE_TDM_CH_ZERO << 8); + val |= (AFE_TDM_CH_ZERO << 12); + break; + case 5: + case 6: + val = AFE_TDM_CH_START_O30_O31; + val |= (AFE_TDM_CH_START_O32_O33 << 4); + val |= (AFE_TDM_CH_START_O34_O35 << 8); + val |= (AFE_TDM_CH_ZERO << 12); + break; + case 7: + case 8: + val = AFE_TDM_CH_START_O30_O31; + val |= (AFE_TDM_CH_START_O32_O33 << 4); + val |= (AFE_TDM_CH_START_O34_O35 << 8); + val |= (AFE_TDM_CH_START_O36_O37 << 12); + break; + default: + val = 0; + } + regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val); + + regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, + 0x000000f0, runtime->channels << 4); + return 0; +} + +static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + + dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, + AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0); + + /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */ + regmap_write(afe->regmap, AFE_HDMI_CONN0, + AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 | + AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 | + AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 | + AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37); + + /* enable Out control */ + regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1); + + /* enable tdm */ + regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1); + + return 0; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + /* disable tdm */ + regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0); + + /* disable Out control */ + regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0); + + regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, + AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, + AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF); + + return 0; + default: + return -EINVAL; + } +} + +static int mtk_afe_dais_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct snd_pcm_runtime *runtime = substream->runtime; + struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; + int ret; + + memif->substream = substream; + + snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware); + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); + return ret; +} + +static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; + + memif->substream = NULL; +} + +static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; + int ret; + + dev_dbg(afe->dev, + "%s period = %u, rate= %u, channels=%u\n", + __func__, params_period_size(params), params_rate(params), + params_channels(params)); + + ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); + if (ret < 0) + return ret; + + memif->phys_buf_addr = substream->runtime->dma_addr; + memif->buffer_size = substream->runtime->dma_bytes; + memif->hw_ptr = 0; + + /* start */ + regmap_write(afe->regmap, + memif->data->reg_ofs_base, memif->phys_buf_addr); + /* end */ + regmap_write(afe->regmap, + memif->data->reg_ofs_base + AFE_BASE_END_OFFSET, + memif->phys_buf_addr + memif->buffer_size - 1); + + /* set channel */ + if (memif->data->mono_shift >= 0) { + unsigned int mono = (params_channels(params) == 1) ? 1 : 0; + + regmap_update_bits(afe->regmap, AFE_DAC_CON1, + 1 << memif->data->mono_shift, + mono << memif->data->mono_shift); + } + + /* set rate */ + if (memif->data->fs_shift < 0) + return 0; + if (memif->data->id == MTK_AFE_MEMIF_DAI || + memif->data->id == MTK_AFE_MEMIF_MOD_DAI) { + unsigned int val; + + switch (params_rate(params)) { + case 8000: + val = 0; + break; + case 16000: + val = 1; + break; + case 32000: + val = 2; + break; + default: + return -EINVAL; + } + + if (memif->data->id == MTK_AFE_MEMIF_DAI) + regmap_update_bits(afe->regmap, AFE_DAC_CON0, + 0x3 << memif->data->fs_shift, + val << memif->data->fs_shift); + else + regmap_update_bits(afe->regmap, AFE_DAC_CON1, + 0x3 << memif->data->fs_shift, + val << memif->data->fs_shift); + + } else { + int fs = mtk_afe_i2s_fs(params_rate(params)); + + if (fs < 0) + return -EINVAL; + + regmap_update_bits(afe->regmap, AFE_DAC_CON1, + 0xf << memif->data->fs_shift, + fs << memif->data->fs_shift); + } + + return 0; +} + +static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + return snd_pcm_lib_free_pages(substream); +} + +static int mtk_afe_dais_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + + /* enable AFE */ + regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); + return 0; +} + +static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_pcm_runtime * const runtime = substream->runtime; + struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id]; + unsigned int counter = runtime->period_size; + + dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + if (memif->data->enable_shift >= 0) + regmap_update_bits(afe->regmap, AFE_DAC_CON0, + 1 << memif->data->enable_shift, + 1 << memif->data->enable_shift); + + /* set irq counter */ + regmap_update_bits(afe->regmap, + memif->data->irq_reg_cnt, + 0x3ffff << memif->data->irq_cnt_shift, + counter << memif->data->irq_cnt_shift); + + /* set irq fs */ + if (memif->data->irq_fs_shift >= 0) { + int fs = mtk_afe_i2s_fs(runtime->rate); + + if (fs < 0) + return -EINVAL; + + regmap_update_bits(afe->regmap, + AFE_IRQ_MCU_CON, + 0xf << memif->data->irq_fs_shift, + fs << memif->data->irq_fs_shift); + } + /* enable interrupt */ + regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON, + 1 << memif->data->irq_en_shift, + 1 << memif->data->irq_en_shift); + + return 0; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + if (memif->data->enable_shift >= 0) + regmap_update_bits(afe->regmap, AFE_DAC_CON0, + 1 << memif->data->enable_shift, 0); + /* disable interrupt */ + regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON, + 1 << memif->data->irq_en_shift, + 0 << memif->data->irq_en_shift); + /* and clear pending IRQ */ + regmap_write(afe->regmap, AFE_IRQ_CLR, + 1 << memif->data->irq_clr_shift); + memif->hw_ptr = 0; + return 0; + default: + return -EINVAL; + } +} + +/* FE DAIs */ +static const struct snd_soc_dai_ops mtk_afe_dai_ops = { + .startup = mtk_afe_dais_startup, + .shutdown = mtk_afe_dais_shutdown, + .hw_params = mtk_afe_dais_hw_params, + .hw_free = mtk_afe_dais_hw_free, + .prepare = mtk_afe_dais_prepare, + .trigger = mtk_afe_dais_trigger, +}; + +/* BE DAIs */ +static const struct snd_soc_dai_ops mtk_afe_i2s_ops = { + .startup = mtk_afe_i2s_startup, + .shutdown = mtk_afe_i2s_shutdown, + .prepare = mtk_afe_i2s_prepare, +}; + +static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = { + .startup = mtk_afe_hdmi_startup, + .shutdown = mtk_afe_hdmi_shutdown, + .prepare = mtk_afe_hdmi_prepare, + .trigger = mtk_afe_hdmi_trigger, + +}; + +static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = { + /* FE DAIs: memory intefaces to CPU */ + { + .name = "DL1", /* downlink 1 */ + .id = MTK_AFE_MEMIF_DL1, + .playback = { + .stream_name = "DL1", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &mtk_afe_dai_ops, + }, { + .name = "VUL", /* voice uplink */ + .id = MTK_AFE_MEMIF_VUL, + .capture = { + .stream_name = "VUL", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &mtk_afe_dai_ops, + }, { + /* BE DAIs */ + .name = "I2S", + .id = MTK_AFE_IO_I2S, + .playback = { + .stream_name = "I2S Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture = { + .stream_name = "I2S Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &mtk_afe_i2s_ops, + .symmetric_rates = 1, + }, +}; + +static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = { + /* FE DAIs */ + { + .name = "HDMI", + .id = MTK_AFE_MEMIF_HDMI, + .playback = { + .stream_name = "HDMI", + .channels_min = 2, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &mtk_afe_dai_ops, + }, { + /* BE DAIs */ + .name = "HDMIO", + .id = MTK_AFE_IO_HDMI, + .playback = { + .stream_name = "HDMIO Playback", + .channels_min = 2, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &mtk_afe_hdmi_ops, + }, +}; + +static const struct snd_kcontrol_new mtk_afe_o03_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_afe_o04_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_afe_o09_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_afe_o10_mix[] = { + SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0), +}; + +static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = { + /* Backend DAIs */ + SND_SOC_DAPM_AIF_IN("I2S Capture", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S Playback", NULL, 0, SND_SOC_NOPM, 0, 0), + + /* inter-connections */ + SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, + mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)), + SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0, + mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)), + SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0, + mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)), + SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0, + mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)), +}; + +static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = { + {"I05", NULL, "DL1"}, + {"I06", NULL, "DL1"}, + {"I2S Playback", NULL, "O03"}, + {"I2S Playback", NULL, "O04"}, + {"VUL", NULL, "O09"}, + {"VUL", NULL, "O10"}, + {"I17", NULL, "I2S Capture"}, + {"I18", NULL, "I2S Capture"}, + { "O03", "I05 Switch", "I05" }, + { "O04", "I06 Switch", "I06" }, + { "O09", "I17 Switch", "I17" }, + { "O10", "I18 Switch", "I18" }, +}; + +static const struct snd_soc_dapm_widget mtk_afe_hdmi_widgets[] = { + /* Backend DAIs */ + SND_SOC_DAPM_AIF_OUT("HDMIO Playback", NULL, 0, SND_SOC_NOPM, 0, 0), +}; + +static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = { + {"HDMIO Playback", NULL, "HDMI"}, +}; + +static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = { + .name = "mtk-afe-pcm-dai", + .dapm_widgets = mtk_afe_pcm_widgets, + .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets), + .dapm_routes = mtk_afe_pcm_routes, + .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes), +}; + +static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = { + .name = "mtk-afe-hdmi-dai", + .dapm_widgets = mtk_afe_hdmi_widgets, + .num_dapm_widgets = ARRAY_SIZE(mtk_afe_hdmi_widgets), + .dapm_routes = mtk_afe_hdmi_routes, + .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes), +}; + +static const char *aud_clks[MTK_CLK_NUM] = { + [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk", + [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio", + [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus", + [MTK_CLK_I2S0_M] = "i2s0_m", + [MTK_CLK_I2S1_M] = "i2s1_m", + [MTK_CLK_I2S2_M] = "i2s2_m", + [MTK_CLK_I2S3_M] = "i2s3_m", + [MTK_CLK_I2S3_B] = "i2s3_b", + [MTK_CLK_BCK0] = "bck0", + [MTK_CLK_BCK1] = "bck1", +}; + +static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = { + { + .name = "DL1", + .id = MTK_AFE_MEMIF_DL1, + .reg_ofs_base = AFE_DL1_BASE, + .reg_ofs_cur = AFE_DL1_CUR, + .fs_shift = 0, + .mono_shift = 21, + .enable_shift = 1, + .irq_reg_cnt = AFE_IRQ_CNT1, + .irq_cnt_shift = 0, + .irq_en_shift = 0, + .irq_fs_shift = 4, + .irq_clr_shift = 0, + }, { + .name = "DL2", + .id = MTK_AFE_MEMIF_DL2, + .reg_ofs_base = AFE_DL2_BASE, + .reg_ofs_cur = AFE_DL2_CUR, + .fs_shift = 4, + .mono_shift = 22, + .enable_shift = 2, + .irq_reg_cnt = AFE_IRQ_CNT1, + .irq_cnt_shift = 20, + .irq_en_shift = 2, + .irq_fs_shift = 16, + .irq_clr_shift = 2, + }, { + .name = "VUL", + .id = MTK_AFE_MEMIF_VUL, + .reg_ofs_base = AFE_VUL_BASE, + .reg_ofs_cur = AFE_VUL_CUR, + .fs_shift = 16, + .mono_shift = 27, + .enable_shift = 3, + .irq_reg_cnt = AFE_IRQ_CNT2, + .irq_cnt_shift = 0, + .irq_en_shift = 1, + .irq_fs_shift = 8, + .irq_clr_shift = 1, + }, { + .name = "DAI", + .id = MTK_AFE_MEMIF_DAI, + .reg_ofs_base = AFE_DAI_BASE, + .reg_ofs_cur = AFE_DAI_CUR, + .fs_shift = 24, + .mono_shift = -1, + .enable_shift = 4, + .irq_reg_cnt = AFE_IRQ_CNT2, + .irq_cnt_shift = 20, + .irq_en_shift = 3, + .irq_fs_shift = 20, + .irq_clr_shift = 3, + }, { + .name = "AWB", + .id = MTK_AFE_MEMIF_AWB, + .reg_ofs_base = AFE_AWB_BASE, + .reg_ofs_cur = AFE_AWB_CUR, + .fs_shift = 12, + .mono_shift = 24, + .enable_shift = 6, + .irq_reg_cnt = AFE_IRQ_CNT7, + .irq_cnt_shift = 0, + .irq_en_shift = 14, + .irq_fs_shift = 24, + .irq_clr_shift = 6, + }, { + .name = "MOD_DAI", + .id = MTK_AFE_MEMIF_MOD_DAI, + .reg_ofs_base = AFE_MOD_PCM_BASE, + .reg_ofs_cur = AFE_MOD_PCM_CUR, + .fs_shift = 30, + .mono_shift = 30, + .enable_shift = 7, + .irq_reg_cnt = AFE_IRQ_CNT2, + .irq_cnt_shift = 20, + .irq_en_shift = 3, + .irq_fs_shift = 20, + .irq_clr_shift = 3, + }, { + .name = "HDMI", + .id = MTK_AFE_MEMIF_HDMI, + .reg_ofs_base = AFE_HDMI_OUT_BASE, + .reg_ofs_cur = AFE_HDMI_OUT_CUR, + .fs_shift = -1, + .mono_shift = -1, + .enable_shift = -1, + .irq_reg_cnt = AFE_IRQ_CNT5, + .irq_cnt_shift = 0, + .irq_en_shift = 12, + .irq_fs_shift = -1, + .irq_clr_shift = 4, + }, +}; + +static const struct regmap_config mtk_afe_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = AFE_ADDA2_TOP_CON0, + .cache_type = REGCACHE_NONE, +}; + +static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id) +{ + struct mtk_afe *afe = dev_id; + unsigned int reg_value, hw_ptr; + int i, ret; + + ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value); + if (ret) { + dev_err(afe->dev, "%s irq status err\n", __func__); + reg_value = AFE_IRQ_STATUS_BITS; + goto err_irq; + } + + for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) { + struct mtk_afe_memif *memif = &afe->memif[i]; + + if (!(reg_value & (1 << memif->data->irq_clr_shift))) + continue; + + ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur, + &hw_ptr); + if (ret || hw_ptr == 0) { + dev_err(afe->dev, "%s hw_ptr err\n", __func__); + hw_ptr = memif->phys_buf_addr; + } + memif->hw_ptr = hw_ptr - memif->phys_buf_addr; + snd_pcm_period_elapsed(memif->substream); + } + +err_irq: + /* clear irq */ + regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS); + + return IRQ_HANDLED; +} + +static int mtk_afe_runtime_suspend(struct device *dev) +{ + struct mtk_afe *afe = dev_get_drvdata(dev); + + /* disable AFE clk */ + regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, + AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE); + + clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]); + clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]); + clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]); + clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]); + clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]); + return 0; +} + +static int mtk_afe_runtime_resume(struct device *dev) +{ + struct mtk_afe *afe = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]); + if (ret) + return ret; + + ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]); + if (ret) + goto err_infra; + + ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]); + if (ret) + goto err_top_aud_bus; + + ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]); + if (ret) + goto err_top_aud; + + ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]); + if (ret) + goto err_bck0; + + /* enable AFE clk */ + regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0); + + /* set O3/O4 16bits */ + regmap_update_bits(afe->regmap, AFE_CONN_24BIT, + AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0); + + /* unmask all IRQs */ + regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff); + return 0; + +err_bck0: + clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]); +err_top_aud: + clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]); +err_top_aud_bus: + clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]); +err_infra: + clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]); + return ret; +} + +static int mtk_afe_init_audio_clk(struct mtk_afe *afe) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { + afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); + if (IS_ERR(afe->clocks[i])) { + dev_err(afe->dev, "%s devm_clk_get %s fail\n", + __func__, aud_clks[i]); + return PTR_ERR(afe->clocks[i]); + } + } + clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */ + clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */ + return 0; +} + +static int mtk_afe_pcm_dev_probe(struct platform_device *pdev) +{ + int ret, i; + unsigned int irq_id; + struct mtk_afe *afe; + struct resource *res; + + afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); + if (!afe) + return -ENOMEM; + + afe->dev = &pdev->dev; + + irq_id = platform_get_irq(pdev, 0); + if (!irq_id) { + dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name); + return -ENXIO; + } + ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler, + 0, "Afe_ISR_Handle", (void *)afe); + if (ret) { + dev_err(afe->dev, "could not request_irq\n"); + return ret; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + afe->base_addr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(afe->base_addr)) + return PTR_ERR(afe->base_addr); + + afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, + &mtk_afe_regmap_config); + if (IS_ERR(afe->regmap)) + return PTR_ERR(afe->regmap); + + /* initial audio related clock */ + ret = mtk_afe_init_audio_clk(afe); + if (ret) { + dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n"); + return ret; + } + + for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) + afe->memif[i].data = &memif_data[i]; + + platform_set_drvdata(pdev, afe); + + pm_runtime_enable(&pdev->dev); + if (!pm_runtime_enabled(&pdev->dev)) { + ret = mtk_afe_runtime_resume(&pdev->dev); + if (ret) + goto err_pm_disable; + } + + ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform); + if (ret) + goto err_pm_disable; + + ret = snd_soc_register_component(&pdev->dev, + &mtk_afe_pcm_dai_component, + mtk_afe_pcm_dais, + ARRAY_SIZE(mtk_afe_pcm_dais)); + if (ret) + goto err_platform; + + ret = snd_soc_register_component(&pdev->dev, + &mtk_afe_hdmi_dai_component, + mtk_afe_hdmi_dais, + ARRAY_SIZE(mtk_afe_hdmi_dais)); + if (ret) + goto err_comp; + + dev_info(&pdev->dev, "MTK AFE driver initialized.\n"); + return 0; + +err_comp: + snd_soc_unregister_component(&pdev->dev); +err_platform: + snd_soc_unregister_platform(&pdev->dev); +err_pm_disable: + pm_runtime_disable(&pdev->dev); + return ret; +} + +static int mtk_afe_pcm_dev_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + snd_soc_unregister_component(&pdev->dev); + snd_soc_unregister_platform(&pdev->dev); + return 0; +} + +static const struct of_device_id mtk_afe_pcm_dt_match[] = { + { .compatible = "mediatek,mt8173-afe-pcm", }, + { } +}; +MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match); + +static const struct dev_pm_ops mtk_afe_pm_ops = { + SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume, + NULL) +}; + +static struct platform_driver mtk_afe_pcm_driver = { + .driver = { + .name = "mtk-afe-pcm", + .owner = THIS_MODULE, + .of_match_table = mtk_afe_pcm_dt_match, + .pm = &mtk_afe_pm_ops, + }, + .probe = mtk_afe_pcm_dev_probe, + .remove = mtk_afe_pcm_dev_remove, +}; + +module_platform_driver(mtk_afe_pcm_driver); + +MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver"); +MODULE_AUTHOR("Koro Chen "); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From a54f6f0c5b7fb4048ea3de9751720090ac92a570 Mon Sep 17 00:00:00 2001 From: Koro Chen Date: Mon, 15 Jun 2015 22:38:03 +0800 Subject: ASoC: mediatek: Add machine driver for MAX98090 codec This is the DPCM based machine driver with MAX98090 Signed-off-by: Koro Chen Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/mt8173-max98090.txt | 13 ++ sound/soc/mediatek/Kconfig | 10 + sound/soc/mediatek/Makefile | 2 + sound/soc/mediatek/mt8173-max98090.c | 213 +++++++++++++++++++++ 4 files changed, 238 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8173-max98090.txt create mode 100644 sound/soc/mediatek/mt8173-max98090.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/mt8173-max98090.txt b/Documentation/devicetree/bindings/sound/mt8173-max98090.txt new file mode 100644 index 000000000000..829bd26d17f8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8173-max98090.txt @@ -0,0 +1,13 @@ +MT8173 with MAX98090 CODEC + +Required properties: +- compatible : "mediatek,mt8173-max98090" +- mediatek,audio-codec: the phandle of the MAX98090 audio codec + +Example: + + sound { + compatible = "mediatek,mt8173-max98090"; + mediatek,audio-codec = <&max98090>; + }; + diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig index c622280cacd9..0bfd2a02a408 100644 --- a/sound/soc/mediatek/Kconfig +++ b/sound/soc/mediatek/Kconfig @@ -7,3 +7,13 @@ config SND_SOC_MEDIATEK Select Y if you have such device. Ex: MT8173 +config SND_SOC_MT8173_MAX98090 + tristate "ASoC Audio driver for MT8173 with MAX98090 codec" + depends on SND_SOC_MEDIATEK + select SND_SOC_MAX98090 + help + This adds ASoC driver for Mediatek MT8173 boards + with the MAX98090 audio codec. + Select Y if you have such device. + If unsure select "N". + diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile index 5f27cc772f66..08fa765b1f0b 100644 --- a/sound/soc/mediatek/Makefile +++ b/sound/soc/mediatek/Makefile @@ -1,2 +1,4 @@ # MTK Platform Support obj-$(CONFIG_SND_SOC_MEDIATEK) += mtk-afe-pcm.o +# Machine support +obj-$(CONFIG_SND_SOC_MT8173_MAX98090) += mt8173-max98090.o diff --git a/sound/soc/mediatek/mt8173-max98090.c b/sound/soc/mediatek/mt8173-max98090.c new file mode 100644 index 000000000000..4d44b5803e55 --- /dev/null +++ b/sound/soc/mediatek/mt8173-max98090.c @@ -0,0 +1,213 @@ +/* + * mt8173-max98090.c -- MT8173 MAX98090 ALSA SoC machine driver + * + * Copyright (c) 2015 MediaTek Inc. + * Author: Koro Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "../codecs/max98090.h" + +static struct snd_soc_jack mt8173_max98090_jack; + +static struct snd_soc_jack_pin mt8173_max98090_jack_pins[] = { + { + .pin = "Headphone", + .mask = SND_JACK_HEADPHONE, + }, + { + .pin = "Headset Mic", + .mask = SND_JACK_MICROPHONE, + }, +}; + +static const struct snd_soc_dapm_widget mt8173_max98090_widgets[] = { + SND_SOC_DAPM_SPK("Speaker", NULL), + SND_SOC_DAPM_MIC("Int Mic", NULL), + SND_SOC_DAPM_HP("Headphone", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), +}; + +static const struct snd_soc_dapm_route mt8173_max98090_routes[] = { + {"Speaker", NULL, "SPKL"}, + {"Speaker", NULL, "SPKR"}, + {"DMICL", NULL, "Int Mic"}, + {"Headphone", NULL, "HPL"}, + {"Headphone", NULL, "HPR"}, + {"Headset Mic", NULL, "MICBIAS"}, + {"IN34", NULL, "Headset Mic"}, +}; + +static const struct snd_kcontrol_new mt8173_max98090_controls[] = { + SOC_DAPM_PIN_SWITCH("Speaker"), + SOC_DAPM_PIN_SWITCH("Int Mic"), + SOC_DAPM_PIN_SWITCH("Headphone"), + SOC_DAPM_PIN_SWITCH("Headset Mic"), +}; + +static int mt8173_max98090_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + + return snd_soc_dai_set_sysclk(codec_dai, 0, params_rate(params) * 256, + SND_SOC_CLOCK_IN); +} + +static struct snd_soc_ops mt8173_max98090_ops = { + .hw_params = mt8173_max98090_hw_params, +}; + +static int mt8173_max98090_init(struct snd_soc_pcm_runtime *runtime) +{ + int ret; + struct snd_soc_card *card = runtime->card; + struct snd_soc_codec *codec = runtime->codec; + + /* enable jack detection */ + ret = snd_soc_card_jack_new(card, "Headphone", SND_JACK_HEADPHONE, + &mt8173_max98090_jack, NULL, 0); + if (ret) { + dev_err(card->dev, "Can't snd_soc_jack_new %d\n", ret); + return ret; + } + + ret = snd_soc_jack_add_pins(&mt8173_max98090_jack, + ARRAY_SIZE(mt8173_max98090_jack_pins), + mt8173_max98090_jack_pins); + if (ret) { + dev_err(card->dev, "Can't snd_soc_jack_add_pins %d\n", ret); + return ret; + } + + return max98090_mic_detect(codec, &mt8173_max98090_jack); +} + +/* Digital audio interface glue - connects codec <---> CPU */ +static struct snd_soc_dai_link mt8173_max98090_dais[] = { + /* Front End DAI links */ + { + .name = "MAX98090 Playback", + .stream_name = "MAX98090 Playback", + .cpu_dai_name = "DL1", + .platform_name = "11220000.mt8173-afe-pcm", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, + .dynamic = 1, + .dpcm_playback = 1, + }, + { + .name = "MAX98090 Capture", + .stream_name = "MAX98090 Capture", + .cpu_dai_name = "VUL", + .platform_name = "11220000.mt8173-afe-pcm", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, + .dynamic = 1, + .dpcm_capture = 1, + }, + /* Back End DAI links */ + { + .name = "Codec", + .cpu_dai_name = "I2S", + .platform_name = "11220000.mt8173-afe-pcm", + .no_pcm = 1, + .codec_dai_name = "HiFi", + .init = mt8173_max98090_init, + .ops = &mt8173_max98090_ops, + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, + .dpcm_playback = 1, + .dpcm_capture = 1, + }, +}; + +static struct snd_soc_card mt8173_max98090_card = { + .name = "mt8173-max98090", + .dai_link = mt8173_max98090_dais, + .num_links = ARRAY_SIZE(mt8173_max98090_dais), + .controls = mt8173_max98090_controls, + .num_controls = ARRAY_SIZE(mt8173_max98090_controls), + .dapm_widgets = mt8173_max98090_widgets, + .num_dapm_widgets = ARRAY_SIZE(mt8173_max98090_widgets), + .dapm_routes = mt8173_max98090_routes, + .num_dapm_routes = ARRAY_SIZE(mt8173_max98090_routes), +}; + +static int mt8173_max98090_dev_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card = &mt8173_max98090_card; + struct device_node *codec_node; + int ret, i; + + codec_node = of_parse_phandle(pdev->dev.of_node, + "mediatek,audio-codec", 0); + if (!codec_node) { + dev_err(&pdev->dev, + "Property 'audio-codec' missing or invalid\n"); + return -EINVAL; + } + for (i = 0; i < card->num_links; i++) { + if (mt8173_max98090_dais[i].codec_name) + continue; + mt8173_max98090_dais[i].codec_of_node = codec_node; + } + card->dev = &pdev->dev; + + ret = snd_soc_register_card(card); + if (ret) + dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n", + __func__, ret); + return ret; +} + +static int mt8173_max98090_dev_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + + snd_soc_unregister_card(card); + return 0; +} + +static const struct of_device_id mt8173_max98090_dt_match[] = { + { .compatible = "mediatek,mt8173-max98090", }, + { } +}; +MODULE_DEVICE_TABLE(of, mt8173_max98090_dt_match); + +static struct platform_driver mt8173_max98090_driver = { + .driver = { + .name = "mt8173-max98090", + .owner = THIS_MODULE, + .of_match_table = mt8173_max98090_dt_match, +#ifdef CONFIG_PM + .pm = &snd_soc_pm_ops, +#endif + }, + .probe = mt8173_max98090_dev_probe, + .remove = mt8173_max98090_dev_remove, +}; + +module_platform_driver(mt8173_max98090_driver); + +/* Module information */ +MODULE_DESCRIPTION("MT8173 MAX98090 ALSA SoC machine driver"); +MODULE_AUTHOR("Koro Chen "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:mt8173-max98090"); + -- cgit v1.2.3 From 662e8d917f685011a24492c106737ea5fdff8136 Mon Sep 17 00:00:00 2001 From: Koro Chen Date: Mon, 15 Jun 2015 22:38:04 +0800 Subject: ASoC: mediatek: Add machine driver for rt5650 rt5676 codec This is the DPCM based machine driver with rt5650 and rt5676 Signed-off-by: Nicolas Boichat Signed-off-by: Koro Chen Signed-off-by: Mark Brown --- .../bindings/sound/mt8173-rt5650-rt5676.txt | 13 + sound/soc/mediatek/Kconfig | 11 + sound/soc/mediatek/Makefile | 1 + sound/soc/mediatek/mt8173-rt5650-rt5676.c | 278 +++++++++++++++++++++ 4 files changed, 303 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt create mode 100644 sound/soc/mediatek/mt8173-rt5650-rt5676.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt new file mode 100644 index 000000000000..61e98c976bd4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt @@ -0,0 +1,13 @@ +MT8173 with RT5650 RT5676 CODECS + +Required properties: +- compatible : "mediatek,mt8173-rt5650-rt5676" +- mediatek,audio-codec: the phandles of rt5650 and rt5676 codecs + +Example: + + sound { + compatible = "mediatek,mt8173-rt5650-rt5676"; + mediatek,audio-codec = <&rt5650 &rt5676>; + }; + diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig index 0bfd2a02a408..15c04e2eae34 100644 --- a/sound/soc/mediatek/Kconfig +++ b/sound/soc/mediatek/Kconfig @@ -17,3 +17,14 @@ config SND_SOC_MT8173_MAX98090 Select Y if you have such device. If unsure select "N". +config SND_SOC_MT8173_RT5650_RT5676 + tristate "ASoC Audio driver for MT8173 with RT5650 RT5676 codecs" + depends on SND_SOC_MEDIATEK + select SND_SOC_RT5645 + select SND_SOC_RT5677 + help + This adds ASoC driver for Mediatek MT8173 boards + with the RT5650 and RT5676 codecs. + Select Y if you have such device. + If unsure select "N". + diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile index 08fa765b1f0b..75effbec438d 100644 --- a/sound/soc/mediatek/Makefile +++ b/sound/soc/mediatek/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_SND_SOC_MEDIATEK) += mtk-afe-pcm.o # Machine support obj-$(CONFIG_SND_SOC_MT8173_MAX98090) += mt8173-max98090.o +obj-$(CONFIG_SND_SOC_MT8173_RT5650_RT5676) += mt8173-rt5650-rt5676.o diff --git a/sound/soc/mediatek/mt8173-rt5650-rt5676.c b/sound/soc/mediatek/mt8173-rt5650-rt5676.c new file mode 100644 index 000000000000..094055323059 --- /dev/null +++ b/sound/soc/mediatek/mt8173-rt5650-rt5676.c @@ -0,0 +1,278 @@ +/* + * mt8173-rt5650-rt5676.c -- MT8173 machine driver with RT5650/5676 codecs + * + * Copyright (c) 2015 MediaTek Inc. + * Author: Koro Chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "../codecs/rt5645.h" +#include "../codecs/rt5677.h" + +#define MCLK_FOR_CODECS 12288000 + +static const struct snd_soc_dapm_widget mt8173_rt5650_rt5676_widgets[] = { + SND_SOC_DAPM_SPK("Speaker", NULL), + SND_SOC_DAPM_MIC("Int Mic", NULL), + SND_SOC_DAPM_HP("Headphone", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), +}; + +static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = { + {"Speaker", NULL, "SPOL"}, + {"Speaker", NULL, "SPOR"}, + {"Speaker", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */ + {"Sub DMIC L1", NULL, "Int Mic"}, /* DMIC from 5676 */ + {"Sub DMIC R1", NULL, "Int Mic"}, + {"Headphone", NULL, "HPOL"}, + {"Headphone", NULL, "HPOR"}, + {"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */ + {"Headset Mic", NULL, "micbias1"}, + {"Headset Mic", NULL, "micbias2"}, + {"IN1P", NULL, "Headset Mic"}, + {"IN1N", NULL, "Headset Mic"}, + {"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */ +}; + +static const struct snd_kcontrol_new mt8173_rt5650_rt5676_controls[] = { + SOC_DAPM_PIN_SWITCH("Speaker"), + SOC_DAPM_PIN_SWITCH("Int Mic"), + SOC_DAPM_PIN_SWITCH("Headphone"), + SOC_DAPM_PIN_SWITCH("Headset Mic"), +}; + +static int mt8173_rt5650_rt5676_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int i, ret; + + for (i = 0; i < rtd->num_codecs; i++) { + struct snd_soc_dai *codec_dai = rtd->codec_dais[i]; + + /* pll from mclk 12.288M */ + ret = snd_soc_dai_set_pll(codec_dai, 0, 0, MCLK_FOR_CODECS, + params_rate(params) * 512); + if (ret) + return ret; + + /* sysclk from pll */ + ret = snd_soc_dai_set_sysclk(codec_dai, 1, + params_rate(params) * 512, + SND_SOC_CLOCK_IN); + if (ret) + return ret; + } + return 0; +} + +static struct snd_soc_ops mt8173_rt5650_rt5676_ops = { + .hw_params = mt8173_rt5650_rt5676_hw_params, +}; + +static struct snd_soc_jack mt8173_rt5650_rt5676_jack; + +static int mt8173_rt5650_rt5676_init(struct snd_soc_pcm_runtime *runtime) +{ + struct snd_soc_card *card = runtime->card; + struct snd_soc_codec *codec = runtime->codec_dais[0]->codec; + struct snd_soc_codec *codec_sub = runtime->codec_dais[1]->codec; + int ret; + + rt5645_sel_asrc_clk_src(codec, + RT5645_DA_STEREO_FILTER | + RT5645_AD_STEREO_FILTER, + RT5645_CLK_SEL_I2S1_ASRC); + rt5677_sel_asrc_clk_src(codec_sub, + RT5677_DA_STEREO_FILTER | + RT5677_AD_STEREO1_FILTER, + RT5677_CLK_SEL_I2S1_ASRC); + rt5677_sel_asrc_clk_src(codec_sub, + RT5677_AD_STEREO2_FILTER | + RT5677_I2S2_SOURCE, + RT5677_CLK_SEL_I2S2_ASRC); + + /* enable jack detection */ + ret = snd_soc_card_jack_new(card, "Headset Jack", + SND_JACK_HEADPHONE | SND_JACK_MICROPHONE | + SND_JACK_BTN_0 | SND_JACK_BTN_1 | + SND_JACK_BTN_2 | SND_JACK_BTN_3, + &mt8173_rt5650_rt5676_jack, NULL, 0); + if (ret) { + dev_err(card->dev, "Can't new Headset Jack %d\n", ret); + return ret; + } + + return rt5645_set_jack_detect(codec, + &mt8173_rt5650_rt5676_jack, + &mt8173_rt5650_rt5676_jack, + &mt8173_rt5650_rt5676_jack); +} + +static struct snd_soc_dai_link_component mt8173_rt5650_rt5676_codecs[] = { + { + .dai_name = "rt5645-aif1", + }, + { + .dai_name = "rt5677-aif1", + }, +}; + +/* Digital audio interface glue - connects codec <---> CPU */ +static struct snd_soc_dai_link mt8173_rt5650_rt5676_dais[] = { + /* Front End DAI links */ + { + .name = "rt5650_rt5676 Playback", + .stream_name = "rt5650_rt5676 Playback", + .cpu_dai_name = "DL1", + .platform_name = "11220000.mt8173-afe-pcm", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, + .dynamic = 1, + .dpcm_playback = 1, + }, + { + .name = "rt5650_rt5676 Capture", + .stream_name = "rt5650_rt5676 Capture", + .cpu_dai_name = "VUL", + .platform_name = "11220000.mt8173-afe-pcm", + .codec_name = "snd-soc-dummy", + .codec_dai_name = "snd-soc-dummy-dai", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, + .dynamic = 1, + .dpcm_capture = 1, + }, + + /* Back End DAI links */ + { + .name = "Codec", + .cpu_dai_name = "I2S", + .platform_name = "11220000.mt8173-afe-pcm", + .no_pcm = 1, + .codecs = mt8173_rt5650_rt5676_codecs, + .num_codecs = 2, + .init = mt8173_rt5650_rt5676_init, + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, + .ops = &mt8173_rt5650_rt5676_ops, + .ignore_pmdown_time = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + }, + { /* rt5676 <-> rt5650 intercodec link: Sets rt5676 I2S2 as master */ + .name = "rt5650_rt5676 intercodec", + .stream_name = "rt5650_rt5676 intercodec", + .cpu_dai_name = "snd-soc-dummy-dai", + .platform_name = "snd-soc-dummy", + .no_pcm = 1, + .codec_dai_name = "rt5677-aif2", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM, + }, + +}; + +static struct snd_soc_codec_conf mt8173_rt5650_rt5676_codec_conf[] = { + { + .name_prefix = "Sub", + }, +}; + +static struct snd_soc_card mt8173_rt5650_rt5676_card = { + .name = "mtk-rt5650-rt5676", + .dai_link = mt8173_rt5650_rt5676_dais, + .num_links = ARRAY_SIZE(mt8173_rt5650_rt5676_dais), + .codec_conf = mt8173_rt5650_rt5676_codec_conf, + .num_configs = ARRAY_SIZE(mt8173_rt5650_rt5676_codec_conf), + .controls = mt8173_rt5650_rt5676_controls, + .num_controls = ARRAY_SIZE(mt8173_rt5650_rt5676_controls), + .dapm_widgets = mt8173_rt5650_rt5676_widgets, + .num_dapm_widgets = ARRAY_SIZE(mt8173_rt5650_rt5676_widgets), + .dapm_routes = mt8173_rt5650_rt5676_routes, + .num_dapm_routes = ARRAY_SIZE(mt8173_rt5650_rt5676_routes), +}; + +static int mt8173_rt5650_rt5676_dev_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card = &mt8173_rt5650_rt5676_card; + int ret; + + mt8173_rt5650_rt5676_codecs[0].of_node = + of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 0); + if (!mt8173_rt5650_rt5676_codecs[0].of_node) { + dev_err(&pdev->dev, + "Property 'audio-codec' missing or invalid\n"); + return -EINVAL; + } + mt8173_rt5650_rt5676_codecs[1].of_node = + of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 1); + if (!mt8173_rt5650_rt5676_codecs[1].of_node) { + dev_err(&pdev->dev, + "Property 'audio-codec' missing or invalid\n"); + return -EINVAL; + } + mt8173_rt5650_rt5676_codec_conf[0].of_node = + mt8173_rt5650_rt5676_codecs[1].of_node; + + mt8173_rt5650_rt5676_dais[3].codec_of_node = + mt8173_rt5650_rt5676_codecs[1].of_node; + + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + + ret = snd_soc_register_card(card); + if (ret) + dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n", + __func__, ret); + return ret; +} + +static int mt8173_rt5650_rt5676_dev_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + + snd_soc_unregister_card(card); + return 0; +} + +static const struct of_device_id mt8173_rt5650_rt5676_dt_match[] = { + { .compatible = "mediatek,mt8173-rt5650-rt5676", }, + { } +}; +MODULE_DEVICE_TABLE(of, mt8173_rt5650_rt5676_dt_match); + +static struct platform_driver mt8173_rt5650_rt5676_driver = { + .driver = { + .name = "mtk-rt5650-rt5676", + .owner = THIS_MODULE, + .of_match_table = mt8173_rt5650_rt5676_dt_match, +#ifdef CONFIG_PM + .pm = &snd_soc_pm_ops, +#endif + }, + .probe = mt8173_rt5650_rt5676_dev_probe, + .remove = mt8173_rt5650_rt5676_dev_remove, +}; + +module_platform_driver(mt8173_rt5650_rt5676_driver); + +/* Module information */ +MODULE_DESCRIPTION("MT8173 RT5650 and RT5676 SoC machine driver"); +MODULE_AUTHOR("Koro Chen "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:mtk-rt5650-rt5676"); + -- cgit v1.2.3 From 2c01a3d6b3cf0aaf39b55318fd986b1bd0b98168 Mon Sep 17 00:00:00 2001 From: Cyrille Pitchen Date: Tue, 16 Jun 2015 12:09:30 +0200 Subject: spi: atmel: update DT bindings documentation - add new property "atmel,fifo-size" - change "cs-gpios" to optional for SPI controller version >= 2. Please be aware that the VERSION register can not be used to guess the size of FIFOs. Indeed, for a given hardware version, the SPI controller can be integrated on Atmel SoCs with different FIFO sizes. Also the "atmel,fifo-size" property is optional as older SPI controllers don't embed FIFO at all. Besides, the FIFO size can not be read or guessed from other registers: When designing the FIFO feature, no dedicated registers were added to store this size. Unused spaces in the I/O register range are limited and better reserved for future usages. Instead, the FIFO size of each peripheral is documented in the programmer datasheet. Finally, on a given SoC, there can be several instances of the SPI controller with different FIFO sizes. This explain why we'd rather use a dedicated DT property than use the "compatible" property. For instance, sama5d2x SoCs come with some SPI controllers, the ones inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers use 16 data FIFOs. All these SPI controllers share the same IP version. Signed-off-by: Cyrille Pitchen Acked-by: Nicolas Ferre Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi_atmel.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt index 4f8184d069cb..fb588b3e6a9a 100644 --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt @@ -4,11 +4,16 @@ Required properties: - compatible : should be "atmel,at91rm9200-spi". - reg: Address and length of the register set for the device - interrupts: Should contain spi interrupt -- cs-gpios: chipselects +- cs-gpios: chipselects (optional for SPI controller version >= 2 with the + Chip Select Active After Transfer feature). - clock-names: tuple listing input clock names. Required elements: "spi_clk" - clocks: phandles to input clocks. +Optional properties: +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO + capable SPI controllers. + Example: spi1: spi@fffcc000 { @@ -20,6 +25,7 @@ spi1: spi@fffcc000 { clocks = <&spi1_clk>; clock-names = "spi_clk"; cs-gpios = <&pioB 3 0>; + atmel,fifo-size = <32>; status = "okay"; mmc-slot@0 { -- cgit v1.2.3 From 139069eff7388407f19794384c42a534d618ccd7 Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Wed, 5 Nov 2014 07:48:36 -0500 Subject: ima: add support for new "euid" policy condition The new "euid" policy condition measures files with the specified effective uid (euid). In addition, for CAP_SETUID files it measures files with the specified uid or suid. Changelog: - fixed checkpatch.pl warnings - fixed avc denied {setuid} messages - based on Roberto's feedback Signed-off-by: Mimi Zohar Signed-off-by: Dr. Greg Wettstein Cc: stable@vger.kernel.org --- Documentation/ABI/testing/ima_policy | 3 ++- security/integrity/ima/ima_policy.c | 27 +++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/ima_policy b/Documentation/ABI/testing/ima_policy index 8ae3f57090d4..4a571fa10f96 100644 --- a/Documentation/ABI/testing/ima_policy +++ b/Documentation/ABI/testing/ima_policy @@ -20,7 +20,7 @@ Description: action: measure | dont_measure | appraise | dont_appraise | audit condition:= base | lsm [option] base: [[func=] [mask=] [fsmagic=] [fsuuid=] [uid=] - [fowner]] + [euid=] [fowner=]] lsm: [[subj_user=] [subj_role=] [subj_type=] [obj_user=] [obj_role=] [obj_type=]] option: [[appraise_type=]] [permit_directio] @@ -31,6 +31,7 @@ Description: fsmagic:= hex value fsuuid:= file system UUID (e.g 8bcbe394-4f13-4144-be8e-5aa9ea2ce2f6) uid:= decimal value + euid:= decimal value fowner:=decimal value lsm: are LSM specific option: appraise_type:= [imasig] diff --git a/security/integrity/ima/ima_policy.c b/security/integrity/ima/ima_policy.c index f2421f7fa3c8..525301cf7d90 100644 --- a/security/integrity/ima/ima_policy.c +++ b/security/integrity/ima/ima_policy.c @@ -27,6 +27,7 @@ #define IMA_UID 0x0008 #define IMA_FOWNER 0x0010 #define IMA_FSUUID 0x0020 +#define IMA_EUID 0x0080 #define UNKNOWN 0 #define MEASURE 0x0001 /* same as IMA_MEASURE */ @@ -194,6 +195,16 @@ static bool ima_match_rules(struct ima_rule_entry *rule, return false; if ((rule->flags & IMA_UID) && !uid_eq(rule->uid, cred->uid)) return false; + if (rule->flags & IMA_EUID) { + if (has_capability_noaudit(current, CAP_SETUID)) { + if (!uid_eq(rule->uid, cred->euid) + && !uid_eq(rule->uid, cred->suid) + && !uid_eq(rule->uid, cred->uid)) + return false; + } else if (!uid_eq(rule->uid, cred->euid)) + return false; + } + if ((rule->flags & IMA_FOWNER) && !uid_eq(rule->fowner, inode->i_uid)) return false; for (i = 0; i < MAX_LSM_RULES; i++) { @@ -373,7 +384,8 @@ enum { Opt_audit, Opt_obj_user, Opt_obj_role, Opt_obj_type, Opt_subj_user, Opt_subj_role, Opt_subj_type, - Opt_func, Opt_mask, Opt_fsmagic, Opt_uid, Opt_fowner, + Opt_func, Opt_mask, Opt_fsmagic, + Opt_uid, Opt_euid, Opt_fowner, Opt_appraise_type, Opt_fsuuid, Opt_permit_directio }; @@ -394,6 +406,7 @@ static match_table_t policy_tokens = { {Opt_fsmagic, "fsmagic=%s"}, {Opt_fsuuid, "fsuuid=%s"}, {Opt_uid, "uid=%s"}, + {Opt_euid, "euid=%s"}, {Opt_fowner, "fowner=%s"}, {Opt_appraise_type, "appraise_type=%s"}, {Opt_permit_directio, "permit_directio"}, @@ -566,6 +579,9 @@ static int ima_parse_rule(char *rule, struct ima_rule_entry *entry) break; case Opt_uid: ima_log_string(ab, "uid", args[0].from); + case Opt_euid: + if (token == Opt_euid) + ima_log_string(ab, "euid", args[0].from); if (uid_valid(entry->uid)) { result = -EINVAL; @@ -574,11 +590,14 @@ static int ima_parse_rule(char *rule, struct ima_rule_entry *entry) result = kstrtoul(args[0].from, 10, &lnum); if (!result) { - entry->uid = make_kuid(current_user_ns(), (uid_t)lnum); - if (!uid_valid(entry->uid) || (((uid_t)lnum) != lnum)) + entry->uid = make_kuid(current_user_ns(), + (uid_t) lnum); + if (!uid_valid(entry->uid) || + (uid_t)lnum != lnum) result = -EINVAL; else - entry->flags |= IMA_UID; + entry->flags |= (token == Opt_uid) + ? IMA_UID : IMA_EUID; } break; case Opt_fowner: -- cgit v1.2.3 From 4351c294b8c1028077280f761e158d167b592974 Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Wed, 5 Nov 2014 07:53:55 -0500 Subject: ima: extend "mask" policy matching support The current "mask" policy option matches files opened as MAY_READ, MAY_WRITE, MAY_APPEND or MAY_EXEC. This patch extends the "mask" option to match files opened containing one of these modes. For example, "mask=^MAY_READ" would match files opened read-write. Signed-off-by: Mimi Zohar Signed-off-by: Dr. Greg Wettstein Cc: stable@vger.kernel.org --- Documentation/ABI/testing/ima_policy | 3 ++- security/integrity/ima/ima_policy.c | 20 +++++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/ima_policy b/Documentation/ABI/testing/ima_policy index 4a571fa10f96..0a378a88217a 100644 --- a/Documentation/ABI/testing/ima_policy +++ b/Documentation/ABI/testing/ima_policy @@ -27,7 +27,8 @@ Description: base: func:= [BPRM_CHECK][MMAP_CHECK][FILE_CHECK][MODULE_CHECK] [FIRMWARE_CHECK] - mask:= [MAY_READ] [MAY_WRITE] [MAY_APPEND] [MAY_EXEC] + mask:= [[^]MAY_READ] [[^]MAY_WRITE] [[^]MAY_APPEND] + [[^]MAY_EXEC] fsmagic:= hex value fsuuid:= file system UUID (e.g 8bcbe394-4f13-4144-be8e-5aa9ea2ce2f6) uid:= decimal value diff --git a/security/integrity/ima/ima_policy.c b/security/integrity/ima/ima_policy.c index 525301cf7d90..b3a2038ed424 100644 --- a/security/integrity/ima/ima_policy.c +++ b/security/integrity/ima/ima_policy.c @@ -27,6 +27,7 @@ #define IMA_UID 0x0008 #define IMA_FOWNER 0x0010 #define IMA_FSUUID 0x0020 +#define IMA_INMASK 0x0040 #define IMA_EUID 0x0080 #define UNKNOWN 0 @@ -187,6 +188,9 @@ static bool ima_match_rules(struct ima_rule_entry *rule, if ((rule->flags & IMA_MASK) && (rule->mask != mask && func != POST_SETATTR)) return false; + if ((rule->flags & IMA_INMASK) && + (!(rule->mask & mask) && func != POST_SETATTR)) + return false; if ((rule->flags & IMA_FSMAGIC) && rule->fsmagic != inode->i_sb->s_magic) return false; @@ -448,6 +452,7 @@ static void ima_log_string(struct audit_buffer *ab, char *key, char *value) static int ima_parse_rule(char *rule, struct ima_rule_entry *entry) { struct audit_buffer *ab; + char *from; char *p; int result = 0; @@ -538,18 +543,23 @@ static int ima_parse_rule(char *rule, struct ima_rule_entry *entry) if (entry->mask) result = -EINVAL; - if ((strcmp(args[0].from, "MAY_EXEC")) == 0) + from = args[0].from; + if (*from == '^') + from++; + + if ((strcmp(from, "MAY_EXEC")) == 0) entry->mask = MAY_EXEC; - else if (strcmp(args[0].from, "MAY_WRITE") == 0) + else if (strcmp(from, "MAY_WRITE") == 0) entry->mask = MAY_WRITE; - else if (strcmp(args[0].from, "MAY_READ") == 0) + else if (strcmp(from, "MAY_READ") == 0) entry->mask = MAY_READ; - else if (strcmp(args[0].from, "MAY_APPEND") == 0) + else if (strcmp(from, "MAY_APPEND") == 0) entry->mask = MAY_APPEND; else result = -EINVAL; if (!result) - entry->flags |= IMA_MASK; + entry->flags |= (*args[0].from == '^') + ? IMA_INMASK : IMA_MASK; break; case Opt_fsmagic: ima_log_string(ab, "fsmagic", args[0].from); -- cgit v1.2.3 From 24fd03c87695a76f0517df42a37e51b1597d2c8a Mon Sep 17 00:00:00 2001 From: Mimi Zohar Date: Thu, 11 Jun 2015 20:48:33 -0400 Subject: ima: update builtin policies This patch defines a builtin measurement policy "tcb", similar to the existing "ima_tcb", but with additional rules to also measure files based on the effective uid and to measure files opened with the "read" mode bit set (eg. read, read-write). Changing the builtin "ima_tcb" policy could potentially break existing users. Instead of defining a new separate boot command line option each time the builtin measurement policy is modified, this patch defines a single generic boot command line option "ima_policy=" to specify the builtin policy and deprecates the use of the builtin ima_tcb policy. [The "ima_policy=" boot command line option is based on Roberto Sassu's "ima: added new policy type exec" patch.] Signed-off-by: Mimi Zohar Signed-off-by: Dr. Greg Wettstein Cc: stable@vger.kernel.org --- Documentation/kernel-parameters.txt | 10 +++++- security/integrity/ima/ima_policy.c | 65 ++++++++++++++++++++++++++++++++----- 2 files changed, 65 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index abc496f95220..807b765087d4 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1398,7 +1398,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. The list of supported hash algorithms is defined in crypto/hash_info.h. - ima_tcb [IMA] + ima_policy= [IMA] + The builtin measurement policy to load during IMA + setup. Specyfing "tcb" as the value, measures all + programs exec'd, files mmap'd for exec, and all files + opened with the read mode bit set by either the + effective uid (euid=0) or uid=0. + Format: "tcb" + + ima_tcb [IMA] Deprecated. Use ima_policy= instead. Load a policy which meets the needs of the Trusted Computing Base. This means IMA will measure all programs exec'd, files mmap'd for exec, and all files diff --git a/security/integrity/ima/ima_policy.c b/security/integrity/ima/ima_policy.c index b3a2038ed424..3997e206f82d 100644 --- a/security/integrity/ima/ima_policy.c +++ b/security/integrity/ima/ima_policy.c @@ -44,6 +44,8 @@ enum lsm_rule_types { LSM_OBJ_USER, LSM_OBJ_ROLE, LSM_OBJ_TYPE, LSM_SUBJ_USER, LSM_SUBJ_ROLE, LSM_SUBJ_TYPE }; +enum policy_types { ORIGINAL_TCB = 1, DEFAULT_TCB }; + struct ima_rule_entry { struct list_head list; int action; @@ -72,7 +74,7 @@ struct ima_rule_entry { * normal users can easily run the machine out of memory simply building * and running executables. */ -static struct ima_rule_entry default_rules[] = { +static struct ima_rule_entry dont_measure_rules[] = { {.action = DONT_MEASURE, .fsmagic = PROC_SUPER_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_MEASURE, .fsmagic = SYSFS_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_MEASURE, .fsmagic = DEBUGFS_MAGIC, .flags = IMA_FSMAGIC}, @@ -83,13 +85,29 @@ static struct ima_rule_entry default_rules[] = { {.action = DONT_MEASURE, .fsmagic = SELINUX_MAGIC, .flags = IMA_FSMAGIC}, {.action = DONT_MEASURE, .fsmagic = CGROUP_SUPER_MAGIC, .flags = IMA_FSMAGIC}, - {.action = DONT_MEASURE, .fsmagic = NSFS_MAGIC, .flags = IMA_FSMAGIC}, + {.action = DONT_MEASURE, .fsmagic = NSFS_MAGIC, .flags = IMA_FSMAGIC} +}; + +static struct ima_rule_entry original_measurement_rules[] = { + {.action = MEASURE, .func = MMAP_CHECK, .mask = MAY_EXEC, + .flags = IMA_FUNC | IMA_MASK}, + {.action = MEASURE, .func = BPRM_CHECK, .mask = MAY_EXEC, + .flags = IMA_FUNC | IMA_MASK}, + {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, + .uid = GLOBAL_ROOT_UID, .flags = IMA_FUNC | IMA_MASK | IMA_UID}, + {.action = MEASURE, .func = MODULE_CHECK, .flags = IMA_FUNC}, + {.action = MEASURE, .func = FIRMWARE_CHECK, .flags = IMA_FUNC}, +}; + +static struct ima_rule_entry default_measurement_rules[] = { {.action = MEASURE, .func = MMAP_CHECK, .mask = MAY_EXEC, .flags = IMA_FUNC | IMA_MASK}, {.action = MEASURE, .func = BPRM_CHECK, .mask = MAY_EXEC, .flags = IMA_FUNC | IMA_MASK}, - {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, .uid = GLOBAL_ROOT_UID, - .flags = IMA_FUNC | IMA_MASK | IMA_UID}, + {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, + .uid = GLOBAL_ROOT_UID, .flags = IMA_FUNC | IMA_INMASK | IMA_EUID}, + {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, + .uid = GLOBAL_ROOT_UID, .flags = IMA_FUNC | IMA_INMASK | IMA_UID}, {.action = MEASURE, .func = MODULE_CHECK, .flags = IMA_FUNC}, {.action = MEASURE, .func = FIRMWARE_CHECK, .flags = IMA_FUNC}, }; @@ -121,14 +139,29 @@ static struct list_head *ima_rules; static DEFINE_MUTEX(ima_rules_mutex); -static bool ima_use_tcb __initdata; +static int ima_policy __initdata; static int __init default_measure_policy_setup(char *str) { - ima_use_tcb = 1; + if (ima_policy) + return 1; + + ima_policy = ORIGINAL_TCB; return 1; } __setup("ima_tcb", default_measure_policy_setup); +static int __init policy_setup(char *str) +{ + if (ima_policy) + return 1; + + if (strcmp(str, "tcb") == 0) + ima_policy = DEFAULT_TCB; + + return 1; +} +__setup("ima_policy=", policy_setup); + static bool ima_use_appraise_tcb __initdata; static int __init default_appraise_policy_setup(char *str) { @@ -352,13 +385,27 @@ void __init ima_init_policy(void) { int i, measure_entries, appraise_entries; - /* if !ima_use_tcb set entries = 0 so we load NO default rules */ - measure_entries = ima_use_tcb ? ARRAY_SIZE(default_rules) : 0; + /* if !ima_policy set entries = 0 so we load NO default rules */ + measure_entries = ima_policy ? ARRAY_SIZE(dont_measure_rules) : 0; appraise_entries = ima_use_appraise_tcb ? ARRAY_SIZE(default_appraise_rules) : 0; for (i = 0; i < measure_entries; i++) - list_add_tail(&default_rules[i].list, &ima_default_rules); + list_add_tail(&dont_measure_rules[i].list, &ima_default_rules); + + switch (ima_policy) { + case ORIGINAL_TCB: + for (i = 0; i < ARRAY_SIZE(original_measurement_rules); i++) + list_add_tail(&original_measurement_rules[i].list, + &ima_default_rules); + break; + case DEFAULT_TCB: + for (i = 0; i < ARRAY_SIZE(default_measurement_rules); i++) + list_add_tail(&default_measurement_rules[i].list, + &ima_default_rules); + default: + break; + } for (i = 0; i < appraise_entries; i++) { list_add_tail(&default_appraise_rules[i].list, -- cgit v1.2.3 From fec47d863587c272d6fbf4e50066209c953d5e60 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 22 May 2015 15:45:27 -0500 Subject: remoteproc: introduce rproc_get_by_phandle API Allow users of remoteproc the ability to get a handle to an rproc by passing a phandle supplied in the user's device tree node. This is useful in situations that require manual booting of the rproc. This patch uses the code removed by commit 40e575b1d0b3 ("remoteproc: remove the get_by_name/put API") for the ref counting but is modified to use a simple list and locking mechanism and has rproc_get_by_name replaced with an rproc_get_by_phandle API. Signed-off-by: Dave Gerlach Signed-off-by: Suman Anna [fix order of Signed-off-by tags] Signed-off-by: Ohad Ben-Cohen --- Documentation/remoteproc.txt | 6 +++++ drivers/remoteproc/remoteproc_core.c | 50 ++++++++++++++++++++++++++++++++++++ include/linux/remoteproc.h | 7 ++--- 3 files changed, 60 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/remoteproc.txt b/Documentation/remoteproc.txt index e6469fdcf89a..ef0219fa4bb4 100644 --- a/Documentation/remoteproc.txt +++ b/Documentation/remoteproc.txt @@ -51,6 +51,12 @@ cost. rproc_shutdown() returns, and users can still use it with a subsequent rproc_boot(), if needed. + struct rproc *rproc_get_by_phandle(phandle phandle) + - Find an rproc handle using a device tree phandle. Returns the rproc + handle on success, and NULL on failure. This function increments + the remote processor's refcount, so always use rproc_put() to + decrement it back once rproc isn't needed anymore. + 3. Typical usage #include diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c index e991512e04ed..e1a6d693b8bb 100644 --- a/drivers/remoteproc/remoteproc_core.c +++ b/drivers/remoteproc/remoteproc_core.c @@ -44,6 +44,9 @@ #include "remoteproc_internal.h" +static DEFINE_MUTEX(rproc_list_mutex); +static LIST_HEAD(rproc_list); + typedef int (*rproc_handle_resources_t)(struct rproc *rproc, struct resource_table *table, int len); typedef int (*rproc_handle_resource_t)(struct rproc *rproc, @@ -1144,6 +1147,43 @@ out: } EXPORT_SYMBOL(rproc_shutdown); +/** + * rproc_get_by_phandle() - find a remote processor by phandle + * @phandle: phandle to the rproc + * + * Finds an rproc handle using the remote processor's phandle, and then + * return a handle to the rproc. + * + * This function increments the remote processor's refcount, so always + * use rproc_put() to decrement it back once rproc isn't needed anymore. + * + * Returns the rproc handle on success, and NULL on failure. + */ +struct rproc *rproc_get_by_phandle(phandle phandle) +{ + struct rproc *rproc = NULL, *r; + struct device_node *np; + + np = of_find_node_by_phandle(phandle); + if (!np) + return NULL; + + mutex_lock(&rproc_list_mutex); + list_for_each_entry(r, &rproc_list, node) { + if (r->dev.parent && r->dev.parent->of_node == np) { + rproc = r; + get_device(&rproc->dev); + break; + } + } + mutex_unlock(&rproc_list_mutex); + + of_node_put(np); + + return rproc; +} +EXPORT_SYMBOL(rproc_get_by_phandle); + /** * rproc_add() - register a remote processor * @rproc: the remote processor handle to register @@ -1173,6 +1213,11 @@ int rproc_add(struct rproc *rproc) if (ret < 0) return ret; + /* expose to rproc_get_by_phandle users */ + mutex_lock(&rproc_list_mutex); + list_add(&rproc->node, &rproc_list); + mutex_unlock(&rproc_list_mutex); + dev_info(dev, "%s is available\n", rproc->name); dev_info(dev, "Note: remoteproc is still under development and considered experimental.\n"); @@ -1360,6 +1405,11 @@ int rproc_del(struct rproc *rproc) /* Free the copy of the resource table */ kfree(rproc->cached_table); + /* the rproc is downref'ed as soon as it's removed from the klist */ + mutex_lock(&rproc_list_mutex); + list_del(&rproc->node); + mutex_unlock(&rproc_list_mutex); + device_del(&rproc->dev); return 0; diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index 78b8a9b9d40a..56739e5df1e6 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -36,11 +36,11 @@ #define REMOTEPROC_H #include -#include #include #include #include #include +#include /** * struct resource_table - firmware resource table header @@ -375,7 +375,7 @@ enum rproc_crash_type { /** * struct rproc - represents a physical remote processor device - * @node: klist node of this rproc object + * @node: list node of this rproc object * @domain: iommu domain * @name: human readable name of the rproc * @firmware: name of firmware file to be loaded @@ -407,7 +407,7 @@ enum rproc_crash_type { * @has_iommu: flag to indicate if remote processor is behind an MMU */ struct rproc { - struct klist_node node; + struct list_head node; struct iommu_domain *domain; const char *name; const char *firmware; @@ -481,6 +481,7 @@ struct rproc_vdev { u32 rsc_offset; }; +struct rproc *rproc_get_by_phandle(phandle phandle); struct rproc *rproc_alloc(struct device *dev, const char *name, const struct rproc_ops *ops, const char *firmware, int len); -- cgit v1.2.3 From ccbbb9faac946ce61c241ce9f08b3486fabf031d Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 22 May 2015 15:45:29 -0500 Subject: Documentation: dt: add bindings for TI Wakeup M3 processor Add the device tree bindings document for the TI Wakeup M3 remote processor devices on AM33xx and AM43xx SoCs. These devices are used to offload low-level power management functionality, and are handled by the wkup_m3 remoteproc driver. Signed-off-by: Dave Gerlach Signed-off-by: Suman Anna Acked-by: Tony Lindgren Signed-off-by: Ohad Ben-Cohen --- .../bindings/remoteproc/wkup_m3_rproc.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt b/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt new file mode 100644 index 000000000000..3a70073797eb --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt @@ -0,0 +1,52 @@ +TI Wakeup M3 Remoteproc Driver +============================== + +The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor +(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks +that cannot be controlled from the MPU. This CM3 processor requires a firmware +binary to accomplish this. The wkup_m3 remoteproc driver handles the loading of +the firmware and booting of the CM3. + +Wkup M3 Device Node: +==================== +A wkup_m3 device node is used to represent the Wakeup M3 processor instance +within the SoC. It is added as a child node of the parent interconnect bus +(l4_wkup) through which it is accessible to the MPU. + +Required properties: +-------------------- +- compatible: Should be one of, + "ti,am3352-wkup-m3" for AM33xx SoCs + "ti,am4372-wkup-m3" for AM43xx SoCs +- reg: Should contain the address ranges for the two internal + memory regions, UMEM and DMEM. The parent node should + provide an appropriate ranges property for properly + translating these into bus addresses. +- reg-names: Contains the corresponding names for the two memory + regions. These should be named "umem" & "dmem". +- ti,hwmods: Name of the hwmod associated with the wkupm3 device. +- ti,pm-firmware: Name of firmware file to be used for loading and + booting the wkup_m3 remote processor. + +Example: +-------- +/* AM33xx */ +ocp { + l4_wkup: l4_wkup@44c00000 { + compatible = "am335-l4-wkup", "simple-bus"; + ranges = <0 0x44c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + + wkup_m3: wkup_m3@100000 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x100000 0x4000>, + <0x180000 0x2000>; + reg-names = "umem", "dmem"; + ti,hwmods = "wkup_m3"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + }; + + ... +}; -- cgit v1.2.3 From daecdc66968f122fe53038ded8cb7abe93e0aa8c Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Fri, 12 Jun 2015 23:51:01 +0200 Subject: pinctrl: rockchip: add support for the rk3368 The rk3368 is the first ARM64 soc from Rockchip, but seems to share most peripherals with the ARM32 soc, including the pinctrl functionality. The only notable difference is - as with every Rockchip soc - that the offsets in the General Register Files moved around and a split of the pmu section of the rk3288 into pmu and pmugrf (pmu general register files) sections. The pinctrl driver of course only needs the pmugrf registers for controlling the pin settings. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- .../bindings/pinctrl/rockchip,pinctrl.txt | 5 +- drivers/pinctrl/pinctrl-rockchip.c | 91 ++++++++++++++++++++++ 2 files changed, 94 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 388b213249fd..391ef4be8d50 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -21,14 +21,15 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl" + "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" Optional properties for iomux controller: - rockchip,pmu: phandle referencing a syscon providing the pmu registers as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. + Required for at least rk3188 and rk3288. On the rk3368 this should + point to the PMUGRF syscon. Deprecated properties for iomux controller: - reg: first element is the general register space of the iomux controller diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 429a6eec8c47..9affcd725776 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -63,6 +63,7 @@ enum rockchip_pinctrl_type { RK3066B, RK3188, RK3288, + RK3368, }; /** @@ -613,6 +614,68 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3368_PULL_GRF_OFFSET 0x100 +#define RK3368_PULL_PMU_OFFSET 0x10 + +static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3368_PULL_PMU_OFFSET; + + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3188_PULL_PINS_PER_REG; + *bit *= RK3188_PULL_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3368_PULL_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; + } +} + +#define RK3368_DRV_PMU_OFFSET 0x20 +#define RK3368_DRV_GRF_OFFSET 0x200 + +static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3368_DRV_PMU_OFFSET; + + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3288_DRV_PINS_PER_REG; + *bit *= RK3288_DRV_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3368_DRV_GRF_OFFSET; + + /* correct the offset, as we're starting with the 2nd bank */ + *reg -= 0x10; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; + } +} + static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 }; static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, @@ -703,6 +766,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case RK3188: case RK3288: + case RK3368: data >>= bit; data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; @@ -758,6 +822,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, break; case RK3188: case RK3288: + case RK3368: spin_lock_irqsave(&bank->slock, flags); /* enable the write to the equivalent lower bits */ @@ -935,6 +1000,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, return pull ? false : true; case RK3188: case RK3288: + case RK3368: return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); } @@ -2068,6 +2134,29 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3368_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU + ), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3368_pin_ctrl = { + .pin_banks = rk3368_pin_banks, + .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .label = "RK3368-GPIO", + .type = RK3368, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .drv_calc_reg = rk3368_calc_drv_reg_and_bit, +}; + + static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk2928-pinctrl", .data = (void *)&rk2928_pin_ctrl }, @@ -2079,6 +2168,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3188_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, + { .compatible = "rockchip,rk3368-pinctrl", + .data = (void *)&rk3368_pin_ctrl }, {}, }; MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); -- cgit v1.2.3 From 8366610283d08564f65a1af2ec8458df08418727 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Jun 2015 19:51:46 +0200 Subject: i2c: slave: fix the example how to instantiate from userspace I copied the wrong shell code into the documentation. Sorry to all who tried to get sense out of this current example :/ Slight rewording while we are here. Reported-by: Tim Bakker Signed-off-by: Wolfram Sang Signed-off-by: Wolfram Sang Cc: stable@kernel.org --- Documentation/i2c/slave-interface | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/i2c/slave-interface b/Documentation/i2c/slave-interface index 389bb5d61854..b228ca54bcf4 100644 --- a/Documentation/i2c/slave-interface +++ b/Documentation/i2c/slave-interface @@ -31,10 +31,10 @@ User manual =========== I2C slave backends behave like standard I2C clients. So, you can instantiate -them like described in the document 'instantiating-devices'. A quick example -for instantiating the slave-eeprom driver from userspace: +them as described in the document 'instantiating-devices'. A quick example for +instantiating the slave-eeprom driver from userspace at address 0x64 on bus 1: - # echo 0-0064 > /sys/bus/i2c/drivers/i2c-slave-eeprom/bind + # echo slave-24c02 0x64 > /sys/bus/i2c/devices/i2c-1/new_device Each backend should come with separate documentation to describe its specific behaviour and setup. -- cgit v1.2.3 From bccab6a01afc26f53d91762d78153513cad10b29 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Wed, 17 Jun 2015 11:43:38 -0400 Subject: dm cache: switch the "default" cache replacement policy from mq to smq The Stochastic multiqueue (SMQ) policy (vs MQ) offers the promise of less memory utilization, improved performance and increased adaptability in the face of changing workloads. SMQ also does not have any cumbersome tuning knobs. Users may switch from "mq" to "smq" simply by appropriately reloading a DM table that is using the cache target. Doing so will cause all of the mq policy's hints to be dropped. Also, performance of the cache may degrade slightly until smq recalculates the origin device's hotspots that should be cached. In the future the "mq" policy will just silently make use of "smq" and the mq code will be removed. Signed-off-by: Mike Snitzer Acked-by: Joe Thornber --- Documentation/device-mapper/cache-policies.txt | 67 ++++++++++++++++++++++++-- drivers/md/dm-cache-policy-mq.c | 34 ++----------- drivers/md/dm-cache-policy-smq.c | 17 +++++++ 3 files changed, 86 insertions(+), 32 deletions(-) (limited to 'Documentation') diff --git a/Documentation/device-mapper/cache-policies.txt b/Documentation/device-mapper/cache-policies.txt index 0d124a971801..d9246a32e673 100644 --- a/Documentation/device-mapper/cache-policies.txt +++ b/Documentation/device-mapper/cache-policies.txt @@ -25,10 +25,10 @@ trying to see when the io scheduler has let the ios run. Overview of supplied cache replacement policies =============================================== -multiqueue ----------- +multiqueue (mq) +--------------- -This policy is the default. +This policy has been deprecated in favor of the smq policy (see below). The multiqueue policy has three sets of 16 queues: one set for entries waiting for the cache and another two for those in the cache (a set for @@ -73,6 +73,67 @@ If you're trying to quickly warm a new cache device you may wish to reduce these to encourage promotion. Remember to switch them back to their defaults after the cache fills though. +Stochastic multiqueue (smq) +--------------------------- + +This policy is the default. + +The stochastic multi-queue (smq) policy addresses some of the problems +with the multiqueue (mq) policy. + +The smq policy (vs mq) offers the promise of less memory utilization, +improved performance and increased adaptability in the face of changing +workloads. SMQ also does not have any cumbersome tuning knobs. + +Users may switch from "mq" to "smq" simply by appropriately reloading a +DM table that is using the cache target. Doing so will cause all of the +mq policy's hints to be dropped. Also, performance of the cache may +degrade slightly until smq recalculates the origin device's hotspots +that should be cached. + +Memory usage: +The mq policy uses a lot of memory; 88 bytes per cache block on a 64 +bit machine. + +SMQ uses 28bit indexes to implement it's data structures rather than +pointers. It avoids storing an explicit hit count for each block. It +has a 'hotspot' queue rather than a pre cache which uses a quarter of +the entries (each hotspot block covers a larger area than a single +cache block). + +All these mean smq uses ~25bytes per cache block. Still a lot of +memory, but a substantial improvement nontheless. + +Level balancing: +MQ places entries in different levels of the multiqueue structures +based on their hit count (~ln(hit count)). This means the bottom +levels generally have the most entries, and the top ones have very +few. Having unbalanced levels like this reduces the efficacy of the +multiqueue. + +SMQ does not maintain a hit count, instead it swaps hit entries with +the least recently used entry from the level above. The over all +ordering being a side effect of this stochastic process. With this +scheme we can decide how many entries occupy each multiqueue level, +resulting in better promotion/demotion decisions. + +Adaptability: +The MQ policy maintains a hit count for each cache block. For a +different block to get promoted to the cache it's hit count has to +exceed the lowest currently in the cache. This means it can take a +long time for the cache to adapt between varying IO patterns. +Periodically degrading the hit counts could help with this, but I +haven't found a nice general solution. + +SMQ doesn't maintain hit counts, so a lot of this problem just goes +away. In addition it tracks performance of the hotspot queue, which +is used to decide which blocks to promote. If the hotspot queue is +performing badly then it starts moving entries more quickly between +levels. This lets it adapt to new IO patterns very quickly. + +Performance: +Testing SMQ shows substantially better performance than MQ. + cleaner ------- diff --git a/drivers/md/dm-cache-policy-mq.c b/drivers/md/dm-cache-policy-mq.c index 838665bb495a..32814371b8d3 100644 --- a/drivers/md/dm-cache-policy-mq.c +++ b/drivers/md/dm-cache-policy-mq.c @@ -1431,21 +1431,12 @@ bad_pre_cache_init: static struct dm_cache_policy_type mq_policy_type = { .name = "mq", - .version = {1, 3, 0}, + .version = {1, 4, 0}, .hint_size = 4, .owner = THIS_MODULE, .create = mq_create }; -static struct dm_cache_policy_type default_policy_type = { - .name = "default", - .version = {1, 3, 0}, - .hint_size = 4, - .owner = THIS_MODULE, - .create = mq_create, - .real = &mq_policy_type -}; - static int __init mq_init(void) { int r; @@ -1455,36 +1446,21 @@ static int __init mq_init(void) __alignof__(struct entry), 0, NULL); if (!mq_entry_cache) - goto bad; + return -ENOMEM; r = dm_cache_policy_register(&mq_policy_type); if (r) { DMERR("register failed %d", r); - goto bad_register_mq; - } - - r = dm_cache_policy_register(&default_policy_type); - if (!r) { - DMINFO("version %u.%u.%u loaded", - mq_policy_type.version[0], - mq_policy_type.version[1], - mq_policy_type.version[2]); - return 0; + kmem_cache_destroy(mq_entry_cache); + return -ENOMEM; } - DMERR("register failed (as default) %d", r); - - dm_cache_policy_unregister(&mq_policy_type); -bad_register_mq: - kmem_cache_destroy(mq_entry_cache); -bad: - return -ENOMEM; + return 0; } static void __exit mq_exit(void) { dm_cache_policy_unregister(&mq_policy_type); - dm_cache_policy_unregister(&default_policy_type); kmem_cache_destroy(mq_entry_cache); } diff --git a/drivers/md/dm-cache-policy-smq.c b/drivers/md/dm-cache-policy-smq.c index 66feb307e697..80f02d3330e2 100644 --- a/drivers/md/dm-cache-policy-smq.c +++ b/drivers/md/dm-cache-policy-smq.c @@ -1748,6 +1748,15 @@ static struct dm_cache_policy_type smq_policy_type = { .create = smq_create }; +static struct dm_cache_policy_type default_policy_type = { + .name = "default", + .version = {1, 0, 0}, + .hint_size = 4, + .owner = THIS_MODULE, + .create = smq_create, + .real = &smq_policy_type +}; + static int __init smq_init(void) { int r; @@ -1758,12 +1767,20 @@ static int __init smq_init(void) return -ENOMEM; } + r = dm_cache_policy_register(&default_policy_type); + if (r) { + DMERR("register failed (as default) %d", r); + dm_cache_policy_unregister(&smq_policy_type); + return -ENOMEM; + } + return 0; } static void __exit smq_exit(void) { dm_cache_policy_unregister(&smq_policy_type); + dm_cache_policy_unregister(&default_policy_type); } module_init(smq_init); -- cgit v1.2.3 From c96aec344de0de857ef3d7fba53992c7ba311e1e Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Tue, 9 Jun 2015 17:21:39 -0400 Subject: dm stats: support precise timestamps Make it possible to use precise timestamps with nanosecond granularity in dm statistics. Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer --- Documentation/device-mapper/statistics.txt | 28 +++++- drivers/md/dm-stats.c | 138 +++++++++++++++++++++-------- drivers/md/dm-stats.h | 4 +- 3 files changed, 127 insertions(+), 43 deletions(-) (limited to 'Documentation') diff --git a/Documentation/device-mapper/statistics.txt b/Documentation/device-mapper/statistics.txt index 2a1673adc200..ff6baeaa71f7 100644 --- a/Documentation/device-mapper/statistics.txt +++ b/Documentation/device-mapper/statistics.txt @@ -13,9 +13,13 @@ the range specified. The I/O statistics counters for each step-sized area of a region are in the same format as /sys/block/*/stat or /proc/diskstats (see: Documentation/iostats.txt). But two extra counters (12 and 13) are -provided: total time spent reading and writing in milliseconds. All -these counters may be accessed by sending the @stats_print message to -the appropriate DM device via dmsetup. +provided: total time spent reading and writing. All these counters may +be accessed by sending the @stats_print message to the appropriate DM +device via dmsetup. + +The reported times are in milliseconds and the granularity depends on +the kernel ticks. When the option precise_timestamps is used, the +reported times are in nanoseconds. Each region has a corresponding unique identifier, which we call a region_id, that is assigned when the region is created. The region_id @@ -33,7 +37,9 @@ memory is used by reading Messages ======== - @stats_create [ []] + @stats_create + [ ...] + [ []] Create a new region and return the region_id. @@ -48,6 +54,17 @@ Messages "/" - the range is subdivided into the specified number of areas. + + The number of optional arguments + + + The following optional arguments are supported + precise_timestamps - use precise timer with nanosecond resolution + instead of the "jiffies" variable. When this argument is + used, the resulting times are in nanoseconds instead of + milliseconds. Precise timestamps are a little bit slower + to obtain than jiffies-based timestamps. + An optional parameter. A name that uniquely identifies the userspace owner of the range. This groups ranges together @@ -55,6 +72,9 @@ Messages created and ignore those created by others. The kernel returns this string back in the output of @stats_list message, but it doesn't use it for anything else. + If we omit the number of optional arguments, program id must not + be a number, otherwise it would be interpreted as the number of + optional arguments. An optional parameter. A word that provides auxiliary data diff --git a/drivers/md/dm-stats.c b/drivers/md/dm-stats.c index d1fd31a6dd1a..4bfd84ab1d4a 100644 --- a/drivers/md/dm-stats.c +++ b/drivers/md/dm-stats.c @@ -33,13 +33,14 @@ struct dm_stat_percpu { struct dm_stat_shared { atomic_t in_flight[2]; - unsigned long stamp; + unsigned long long stamp; struct dm_stat_percpu tmp; }; struct dm_stat { struct list_head list_entry; int id; + unsigned stat_flags; size_t n_entries; sector_t start; sector_t end; @@ -53,6 +54,8 @@ struct dm_stat { struct dm_stat_shared stat_shared[0]; }; +#define STAT_PRECISE_TIMESTAMPS 1 + struct dm_stats_last_position { sector_t last_sector; unsigned last_rw; @@ -224,7 +227,8 @@ void dm_stats_cleanup(struct dm_stats *stats) } static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, - sector_t step, const char *program_id, const char *aux_data, + sector_t step, unsigned stat_flags, + const char *program_id, const char *aux_data, void (*suspend_callback)(struct mapped_device *), void (*resume_callback)(struct mapped_device *), struct mapped_device *md) @@ -265,6 +269,7 @@ static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, if (!s) return -ENOMEM; + s->stat_flags = stat_flags; s->n_entries = n_entries; s->start = start; s->end = end; @@ -414,18 +419,24 @@ static int dm_stats_list(struct dm_stats *stats, const char *program, return 1; } -static void dm_stat_round(struct dm_stat_shared *shared, struct dm_stat_percpu *p) +static void dm_stat_round(struct dm_stat *s, struct dm_stat_shared *shared, + struct dm_stat_percpu *p) { /* * This is racy, but so is part_round_stats_single. */ - unsigned long now = jiffies; - unsigned in_flight_read; - unsigned in_flight_write; - unsigned long difference = now - shared->stamp; + unsigned long long now, difference; + unsigned in_flight_read, in_flight_write; + + if (likely(!(s->stat_flags & STAT_PRECISE_TIMESTAMPS))) + now = jiffies; + else + now = ktime_to_ns(ktime_get()); + difference = now - shared->stamp; if (!difference) return; + in_flight_read = (unsigned)atomic_read(&shared->in_flight[READ]); in_flight_write = (unsigned)atomic_read(&shared->in_flight[WRITE]); if (in_flight_read) @@ -440,8 +451,9 @@ static void dm_stat_round(struct dm_stat_shared *shared, struct dm_stat_percpu * } static void dm_stat_for_entry(struct dm_stat *s, size_t entry, - unsigned long bi_rw, sector_t len, bool merged, - bool end, unsigned long duration) + unsigned long bi_rw, sector_t len, + struct dm_stats_aux *stats_aux, bool end, + unsigned long duration_jiffies) { unsigned long idx = bi_rw & REQ_WRITE; struct dm_stat_shared *shared = &s->stat_shared[entry]; @@ -471,15 +483,18 @@ static void dm_stat_for_entry(struct dm_stat *s, size_t entry, p = &s->stat_percpu[smp_processor_id()][entry]; if (!end) { - dm_stat_round(shared, p); + dm_stat_round(s, shared, p); atomic_inc(&shared->in_flight[idx]); } else { - dm_stat_round(shared, p); + dm_stat_round(s, shared, p); atomic_dec(&shared->in_flight[idx]); p->sectors[idx] += len; p->ios[idx] += 1; - p->merges[idx] += merged; - p->ticks[idx] += duration; + p->merges[idx] += stats_aux->merged; + if (!(s->stat_flags & STAT_PRECISE_TIMESTAMPS)) + p->ticks[idx] += duration_jiffies; + else + p->ticks[idx] += stats_aux->duration_ns; } #if BITS_PER_LONG == 32 @@ -491,7 +506,7 @@ static void dm_stat_for_entry(struct dm_stat *s, size_t entry, static void __dm_stat_bio(struct dm_stat *s, unsigned long bi_rw, sector_t bi_sector, sector_t end_sector, - bool end, unsigned long duration, + bool end, unsigned long duration_jiffies, struct dm_stats_aux *stats_aux) { sector_t rel_sector, offset, todo, fragment_len; @@ -520,7 +535,7 @@ static void __dm_stat_bio(struct dm_stat *s, unsigned long bi_rw, if (fragment_len > s->step - offset) fragment_len = s->step - offset; dm_stat_for_entry(s, entry, bi_rw, fragment_len, - stats_aux->merged, end, duration); + stats_aux, end, duration_jiffies); todo -= fragment_len; entry++; offset = 0; @@ -529,11 +544,13 @@ static void __dm_stat_bio(struct dm_stat *s, unsigned long bi_rw, void dm_stats_account_io(struct dm_stats *stats, unsigned long bi_rw, sector_t bi_sector, unsigned bi_sectors, bool end, - unsigned long duration, struct dm_stats_aux *stats_aux) + unsigned long duration_jiffies, + struct dm_stats_aux *stats_aux) { struct dm_stat *s; sector_t end_sector; struct dm_stats_last_position *last; + bool got_precise_time; if (unlikely(!bi_sectors)) return; @@ -557,8 +574,17 @@ void dm_stats_account_io(struct dm_stats *stats, unsigned long bi_rw, rcu_read_lock(); - list_for_each_entry_rcu(s, &stats->list, list_entry) - __dm_stat_bio(s, bi_rw, bi_sector, end_sector, end, duration, stats_aux); + got_precise_time = false; + list_for_each_entry_rcu(s, &stats->list, list_entry) { + if (s->stat_flags & STAT_PRECISE_TIMESTAMPS && !got_precise_time) { + if (!end) + stats_aux->duration_ns = ktime_to_ns(ktime_get()); + else + stats_aux->duration_ns = ktime_to_ns(ktime_get()) - stats_aux->duration_ns; + got_precise_time = true; + } + __dm_stat_bio(s, bi_rw, bi_sector, end_sector, end, duration_jiffies, stats_aux); + } rcu_read_unlock(); } @@ -571,7 +597,7 @@ static void __dm_stat_init_temporary_percpu_totals(struct dm_stat_shared *shared local_irq_disable(); p = &s->stat_percpu[smp_processor_id()][x]; - dm_stat_round(shared, p); + dm_stat_round(s, shared, p); local_irq_enable(); memset(&shared->tmp, 0, sizeof(shared->tmp)); @@ -643,11 +669,15 @@ static int dm_stats_clear(struct dm_stats *stats, int id) /* * This is like jiffies_to_msec, but works for 64-bit values. */ -static unsigned long long dm_jiffies_to_msec64(unsigned long long j) +static unsigned long long dm_jiffies_to_msec64(struct dm_stat *s, unsigned long long j) { - unsigned long long result = 0; + unsigned long long result; unsigned mult; + if (s->stat_flags & STAT_PRECISE_TIMESTAMPS) + return j; + + result = 0; if (j) result = jiffies_to_msecs(j & 0x3fffff); if (j >= 1 << 22) { @@ -709,16 +739,16 @@ static int dm_stats_print(struct dm_stats *stats, int id, shared->tmp.ios[READ], shared->tmp.merges[READ], shared->tmp.sectors[READ], - dm_jiffies_to_msec64(shared->tmp.ticks[READ]), + dm_jiffies_to_msec64(s, shared->tmp.ticks[READ]), shared->tmp.ios[WRITE], shared->tmp.merges[WRITE], shared->tmp.sectors[WRITE], - dm_jiffies_to_msec64(shared->tmp.ticks[WRITE]), + dm_jiffies_to_msec64(s, shared->tmp.ticks[WRITE]), dm_stat_in_flight(shared), - dm_jiffies_to_msec64(shared->tmp.io_ticks_total), - dm_jiffies_to_msec64(shared->tmp.time_in_queue), - dm_jiffies_to_msec64(shared->tmp.io_ticks[READ]), - dm_jiffies_to_msec64(shared->tmp.io_ticks[WRITE])); + dm_jiffies_to_msec64(s, shared->tmp.io_ticks_total), + dm_jiffies_to_msec64(s, shared->tmp.time_in_queue), + dm_jiffies_to_msec64(s, shared->tmp.io_ticks[READ]), + dm_jiffies_to_msec64(s, shared->tmp.io_ticks[WRITE])); if (unlikely(sz + 1 >= maxlen)) goto buffer_overflow; @@ -769,21 +799,31 @@ static int message_stats_create(struct mapped_device *md, unsigned long long start, end, len, step; unsigned divisor; const char *program_id, *aux_data; + unsigned stat_flags = 0; + + struct dm_arg_set as, as_backup; + const char *a; + unsigned feature_args; /* * Input format: - * [ []] + * [ ] [ []] */ - if (argc < 3 || argc > 5) + if (argc < 3) return -EINVAL; - if (!strcmp(argv[1], "-")) { + as.argc = argc; + as.argv = argv; + dm_consume_args(&as, 1); + + a = dm_shift_arg(&as); + if (!strcmp(a, "-")) { start = 0; len = dm_get_size(md); if (!len) len = 1; - } else if (sscanf(argv[1], "%llu+%llu%c", &start, &len, &dummy) != 2 || + } else if (sscanf(a, "%llu+%llu%c", &start, &len, &dummy) != 2 || start != (sector_t)start || len != (sector_t)len) return -EINVAL; @@ -791,7 +831,8 @@ static int message_stats_create(struct mapped_device *md, if (start >= end) return -EINVAL; - if (sscanf(argv[2], "/%u%c", &divisor, &dummy) == 1) { + a = dm_shift_arg(&as); + if (sscanf(a, "/%u%c", &divisor, &dummy) == 1) { if (!divisor) return -EINVAL; step = end - start; @@ -799,18 +840,39 @@ static int message_stats_create(struct mapped_device *md, step++; if (!step) step = 1; - } else if (sscanf(argv[2], "%llu%c", &step, &dummy) != 1 || + } else if (sscanf(a, "%llu%c", &step, &dummy) != 1 || step != (sector_t)step || !step) return -EINVAL; + as_backup = as; + a = dm_shift_arg(&as); + if (a && sscanf(a, "%u%c", &feature_args, &dummy) == 1) { + while (feature_args--) { + a = dm_shift_arg(&as); + if (!a) + return -EINVAL; + if (!strcasecmp(a, "precise_timestamps")) + stat_flags |= STAT_PRECISE_TIMESTAMPS; + else + return -EINVAL; + } + } else { + as = as_backup; + } + program_id = "-"; aux_data = "-"; - if (argc > 3) - program_id = argv[3]; + a = dm_shift_arg(&as); + if (a) + program_id = a; + + a = dm_shift_arg(&as); + if (a) + aux_data = a; - if (argc > 4) - aux_data = argv[4]; + if (as.argc) + return -EINVAL; /* * If a buffer overflow happens after we created the region, @@ -822,7 +884,7 @@ static int message_stats_create(struct mapped_device *md, if (dm_message_test_buffer_overflow(result, maxlen)) return 1; - id = dm_stats_create(dm_get_stats(md), start, end, step, program_id, aux_data, + id = dm_stats_create(dm_get_stats(md), start, end, step, stat_flags, program_id, aux_data, dm_internal_suspend_fast, dm_internal_resume_fast, md); if (id < 0) return id; diff --git a/drivers/md/dm-stats.h b/drivers/md/dm-stats.h index e7c4984bf235..f1c0956e3843 100644 --- a/drivers/md/dm-stats.h +++ b/drivers/md/dm-stats.h @@ -18,6 +18,7 @@ struct dm_stats { struct dm_stats_aux { bool merged; + unsigned long long duration_ns; }; void dm_stats_init(struct dm_stats *st); @@ -30,7 +31,8 @@ int dm_stats_message(struct mapped_device *md, unsigned argc, char **argv, void dm_stats_account_io(struct dm_stats *stats, unsigned long bi_rw, sector_t bi_sector, unsigned bi_sectors, bool end, - unsigned long duration, struct dm_stats_aux *aux); + unsigned long duration_jiffies, + struct dm_stats_aux *aux); static inline bool dm_stats_used(struct dm_stats *st) { -- cgit v1.2.3 From dfcfac3e4cd94abef779297fab6adfd2dbcf52fa Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Tue, 9 Jun 2015 17:22:05 -0400 Subject: dm stats: collect and report histogram of IO latencies Add an option to dm statistics to collect and report a histogram of IO latencies. Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer --- Documentation/device-mapper/statistics.txt | 19 ++- drivers/md/dm-stats.c | 205 +++++++++++++++++++++++++---- 2 files changed, 199 insertions(+), 25 deletions(-) (limited to 'Documentation') diff --git a/Documentation/device-mapper/statistics.txt b/Documentation/device-mapper/statistics.txt index ff6baeaa71f7..4919b2dfd1b3 100644 --- a/Documentation/device-mapper/statistics.txt +++ b/Documentation/device-mapper/statistics.txt @@ -13,9 +13,10 @@ the range specified. The I/O statistics counters for each step-sized area of a region are in the same format as /sys/block/*/stat or /proc/diskstats (see: Documentation/iostats.txt). But two extra counters (12 and 13) are -provided: total time spent reading and writing. All these counters may -be accessed by sending the @stats_print message to the appropriate DM -device via dmsetup. +provided: total time spent reading and writing. When the histogram +argument is used, the 14th parameter is reported that represents the +histogram of latencies. All these counters may be accessed by sending +the @stats_print message to the appropriate DM device via dmsetup. The reported times are in milliseconds and the granularity depends on the kernel ticks. When the option precise_timestamps is used, the @@ -64,6 +65,18 @@ Messages used, the resulting times are in nanoseconds instead of milliseconds. Precise timestamps are a little bit slower to obtain than jiffies-based timestamps. + histogram:n1,n2,n3,n4,... - collect histogram of latencies. The + numbers n1, n2, etc are times that represent the boundaries + of the histogram. If precise_timestamps is not used, the + times are in milliseconds, otherwise they are in + nanoseconds. For each range, the kernel will report the + number of requests that completed within this range. For + example, if we use "histogram:10,20,30", the kernel will + report four numbers a:b:c:d. a is the number of requests + that took 0-10 ms to complete, b is the number of requests + that took 10-20 ms to complete, c is the number of requests + that took 20-30 ms to complete and d is the number of + requests that took more than 30 ms to complete. An optional parameter. A name that uniquely identifies diff --git a/drivers/md/dm-stats.c b/drivers/md/dm-stats.c index 4bfd84ab1d4a..faf1071ef631 100644 --- a/drivers/md/dm-stats.c +++ b/drivers/md/dm-stats.c @@ -29,6 +29,7 @@ struct dm_stat_percpu { unsigned long long io_ticks[2]; unsigned long long io_ticks_total; unsigned long long time_in_queue; + unsigned long long *histogram; }; struct dm_stat_shared { @@ -45,11 +46,14 @@ struct dm_stat { sector_t start; sector_t end; sector_t step; + unsigned n_histogram_entries; + unsigned long long *histogram_boundaries; const char *program_id; const char *aux_data; struct rcu_head rcu_head; size_t shared_alloc_size; size_t percpu_alloc_size; + size_t histogram_alloc_size; struct dm_stat_percpu *stat_percpu[NR_CPUS]; struct dm_stat_shared stat_shared[0]; }; @@ -173,8 +177,11 @@ static void dm_stat_free(struct rcu_head *head) kfree(s->program_id); kfree(s->aux_data); - for_each_possible_cpu(cpu) + for_each_possible_cpu(cpu) { + dm_kvfree(s->stat_percpu[cpu][0].histogram, s->histogram_alloc_size); dm_kvfree(s->stat_percpu[cpu], s->percpu_alloc_size); + } + dm_kvfree(s->stat_shared[0].tmp.histogram, s->histogram_alloc_size); dm_kvfree(s, s->shared_alloc_size); } @@ -228,6 +235,8 @@ void dm_stats_cleanup(struct dm_stats *stats) static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, sector_t step, unsigned stat_flags, + unsigned n_histogram_entries, + unsigned long long *histogram_boundaries, const char *program_id, const char *aux_data, void (*suspend_callback)(struct mapped_device *), void (*resume_callback)(struct mapped_device *), @@ -239,6 +248,7 @@ static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, size_t ni; size_t shared_alloc_size; size_t percpu_alloc_size; + size_t histogram_alloc_size; struct dm_stat_percpu *p; int cpu; int ret_id; @@ -262,7 +272,12 @@ static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, if (percpu_alloc_size / sizeof(struct dm_stat_percpu) != n_entries) return -EOVERFLOW; - if (!check_shared_memory(shared_alloc_size + num_possible_cpus() * percpu_alloc_size)) + histogram_alloc_size = (n_histogram_entries + 1) * (size_t)n_entries * sizeof(unsigned long long); + if (histogram_alloc_size / (n_histogram_entries + 1) != (size_t)n_entries * sizeof(unsigned long long)) + return -EOVERFLOW; + + if (!check_shared_memory(shared_alloc_size + histogram_alloc_size + + num_possible_cpus() * (percpu_alloc_size + histogram_alloc_size))) return -ENOMEM; s = dm_kvzalloc(shared_alloc_size, NUMA_NO_NODE); @@ -276,6 +291,15 @@ static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, s->step = step; s->shared_alloc_size = shared_alloc_size; s->percpu_alloc_size = percpu_alloc_size; + s->histogram_alloc_size = histogram_alloc_size; + + s->n_histogram_entries = n_histogram_entries; + s->histogram_boundaries = kmemdup(histogram_boundaries, + s->n_histogram_entries * sizeof(unsigned long long), GFP_KERNEL); + if (!s->histogram_boundaries) { + r = -ENOMEM; + goto out; + } s->program_id = kstrdup(program_id, GFP_KERNEL); if (!s->program_id) { @@ -293,6 +317,19 @@ static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, atomic_set(&s->stat_shared[ni].in_flight[WRITE], 0); } + if (s->n_histogram_entries) { + unsigned long long *hi; + hi = dm_kvzalloc(s->histogram_alloc_size, NUMA_NO_NODE); + if (!hi) { + r = -ENOMEM; + goto out; + } + for (ni = 0; ni < n_entries; ni++) { + s->stat_shared[ni].tmp.histogram = hi; + hi += s->n_histogram_entries + 1; + } + } + for_each_possible_cpu(cpu) { p = dm_kvzalloc(percpu_alloc_size, cpu_to_node(cpu)); if (!p) { @@ -300,6 +337,18 @@ static int dm_stats_create(struct dm_stats *stats, sector_t start, sector_t end, goto out; } s->stat_percpu[cpu] = p; + if (s->n_histogram_entries) { + unsigned long long *hi; + hi = dm_kvzalloc(s->histogram_alloc_size, cpu_to_node(cpu)); + if (!hi) { + r = -ENOMEM; + goto out; + } + for (ni = 0; ni < n_entries; ni++) { + p[ni].histogram = hi; + hi += s->n_histogram_entries + 1; + } + } } /* @@ -377,9 +426,11 @@ static int dm_stats_delete(struct dm_stats *stats, int id) * vfree can't be called from RCU callback */ for_each_possible_cpu(cpu) - if (is_vmalloc_addr(s->stat_percpu)) + if (is_vmalloc_addr(s->stat_percpu) || + is_vmalloc_addr(s->stat_percpu[cpu][0].histogram)) goto do_sync_free; - if (is_vmalloc_addr(s)) { + if (is_vmalloc_addr(s) || + is_vmalloc_addr(s->stat_shared[0].tmp.histogram)) { do_sync_free: synchronize_rcu_expedited(); dm_stat_free(&s->rcu_head); @@ -486,15 +537,32 @@ static void dm_stat_for_entry(struct dm_stat *s, size_t entry, dm_stat_round(s, shared, p); atomic_inc(&shared->in_flight[idx]); } else { + unsigned long long duration; dm_stat_round(s, shared, p); atomic_dec(&shared->in_flight[idx]); p->sectors[idx] += len; p->ios[idx] += 1; p->merges[idx] += stats_aux->merged; - if (!(s->stat_flags & STAT_PRECISE_TIMESTAMPS)) + if (!(s->stat_flags & STAT_PRECISE_TIMESTAMPS)) { p->ticks[idx] += duration_jiffies; - else + duration = jiffies_to_msecs(duration_jiffies); + } else { p->ticks[idx] += stats_aux->duration_ns; + duration = stats_aux->duration_ns; + } + if (s->n_histogram_entries) { + unsigned lo = 0, hi = s->n_histogram_entries + 1; + while (lo + 1 < hi) { + unsigned mid = (lo + hi) / 2; + if (s->histogram_boundaries[mid - 1] > duration) { + hi = mid; + } else { + lo = mid; + } + + } + p->histogram[lo]++; + } } #if BITS_PER_LONG == 32 @@ -600,7 +668,22 @@ static void __dm_stat_init_temporary_percpu_totals(struct dm_stat_shared *shared dm_stat_round(s, shared, p); local_irq_enable(); - memset(&shared->tmp, 0, sizeof(shared->tmp)); + shared->tmp.sectors[READ] = 0; + shared->tmp.sectors[WRITE] = 0; + shared->tmp.ios[READ] = 0; + shared->tmp.ios[WRITE] = 0; + shared->tmp.merges[READ] = 0; + shared->tmp.merges[WRITE] = 0; + shared->tmp.ticks[READ] = 0; + shared->tmp.ticks[WRITE] = 0; + shared->tmp.io_ticks[READ] = 0; + shared->tmp.io_ticks[WRITE] = 0; + shared->tmp.io_ticks_total = 0; + shared->tmp.time_in_queue = 0; + + if (s->n_histogram_entries) + memset(shared->tmp.histogram, 0, (s->n_histogram_entries + 1) * sizeof(unsigned long long)); + for_each_possible_cpu(cpu) { p = &s->stat_percpu[cpu][x]; shared->tmp.sectors[READ] += ACCESS_ONCE(p->sectors[READ]); @@ -615,6 +698,11 @@ static void __dm_stat_init_temporary_percpu_totals(struct dm_stat_shared *shared shared->tmp.io_ticks[WRITE] += ACCESS_ONCE(p->io_ticks[WRITE]); shared->tmp.io_ticks_total += ACCESS_ONCE(p->io_ticks_total); shared->tmp.time_in_queue += ACCESS_ONCE(p->time_in_queue); + if (s->n_histogram_entries) { + unsigned i; + for (i = 0; i < s->n_histogram_entries + 1; i++) + shared->tmp.histogram[i] += ACCESS_ONCE(p->histogram[i]); + } } } @@ -644,6 +732,15 @@ static void __dm_stat_clear(struct dm_stat *s, size_t idx_start, size_t idx_end, p->io_ticks_total -= shared->tmp.io_ticks_total; p->time_in_queue -= shared->tmp.time_in_queue; local_irq_enable(); + if (s->n_histogram_entries) { + unsigned i; + for (i = 0; i < s->n_histogram_entries + 1; i++) { + local_irq_disable(); + p = &s->stat_percpu[smp_processor_id()][x]; + p->histogram[i] -= shared->tmp.histogram[i]; + local_irq_enable(); + } + } } } @@ -733,7 +830,7 @@ static int dm_stats_print(struct dm_stats *stats, int id, __dm_stat_init_temporary_percpu_totals(shared, s, x); - DMEMIT("%llu+%llu %llu %llu %llu %llu %llu %llu %llu %llu %d %llu %llu %llu %llu\n", + DMEMIT("%llu+%llu %llu %llu %llu %llu %llu %llu %llu %llu %d %llu %llu %llu %llu", (unsigned long long)start, (unsigned long long)step, shared->tmp.ios[READ], @@ -749,6 +846,13 @@ static int dm_stats_print(struct dm_stats *stats, int id, dm_jiffies_to_msec64(s, shared->tmp.time_in_queue), dm_jiffies_to_msec64(s, shared->tmp.io_ticks[READ]), dm_jiffies_to_msec64(s, shared->tmp.io_ticks[WRITE])); + if (s->n_histogram_entries) { + unsigned i; + for (i = 0; i < s->n_histogram_entries + 1; i++) { + DMEMIT("%s%llu", !i ? " " : ":", shared->tmp.histogram[i]); + } + } + DMEMIT("\n"); if (unlikely(sz + 1 >= maxlen)) goto buffer_overflow; @@ -790,10 +894,47 @@ static int dm_stats_set_aux(struct dm_stats *stats, int id, const char *aux_data return 0; } +static int parse_histogram(const char *h, unsigned *n_histogram_entries, + unsigned long long **histogram_boundaries) +{ + const char *q; + unsigned n; + unsigned long long last; + + *n_histogram_entries = 1; + for (q = h; *q; q++) + if (*q == ',') + (*n_histogram_entries)++; + + *histogram_boundaries = kmalloc(*n_histogram_entries * sizeof(unsigned long long), GFP_KERNEL); + if (!*histogram_boundaries) + return -ENOMEM; + + n = 0; + last = 0; + while (1) { + unsigned long long hi; + int s; + char ch; + s = sscanf(h, "%llu%c", &hi, &ch); + if (!s || (s == 2 && ch != ',')) + return -EINVAL; + if (hi <= last) + return -EINVAL; + last = hi; + (*histogram_boundaries)[n] = hi; + if (s == 1) + return 0; + h = strchr(h, ',') + 1; + n++; + } +} + static int message_stats_create(struct mapped_device *md, unsigned argc, char **argv, char *result, unsigned maxlen) { + int r; int id; char dummy; unsigned long long start, end, len, step; @@ -801,6 +942,9 @@ static int message_stats_create(struct mapped_device *md, const char *program_id, *aux_data; unsigned stat_flags = 0; + unsigned n_histogram_entries = 0; + unsigned long long *histogram_boundaries = NULL; + struct dm_arg_set as, as_backup; const char *a; unsigned feature_args; @@ -811,7 +955,7 @@ static int message_stats_create(struct mapped_device *md, */ if (argc < 3) - return -EINVAL; + goto ret_einval; as.argc = argc; as.argv = argv; @@ -825,11 +969,11 @@ static int message_stats_create(struct mapped_device *md, len = 1; } else if (sscanf(a, "%llu+%llu%c", &start, &len, &dummy) != 2 || start != (sector_t)start || len != (sector_t)len) - return -EINVAL; + goto ret_einval; end = start + len; if (start >= end) - return -EINVAL; + goto ret_einval; a = dm_shift_arg(&as); if (sscanf(a, "/%u%c", &divisor, &dummy) == 1) { @@ -842,7 +986,7 @@ static int message_stats_create(struct mapped_device *md, step = 1; } else if (sscanf(a, "%llu%c", &step, &dummy) != 1 || step != (sector_t)step || !step) - return -EINVAL; + goto ret_einval; as_backup = as; a = dm_shift_arg(&as); @@ -850,11 +994,16 @@ static int message_stats_create(struct mapped_device *md, while (feature_args--) { a = dm_shift_arg(&as); if (!a) - return -EINVAL; + goto ret_einval; if (!strcasecmp(a, "precise_timestamps")) stat_flags |= STAT_PRECISE_TIMESTAMPS; - else - return -EINVAL; + else if (!strncasecmp(a, "histogram:", 10)) { + if (n_histogram_entries) + goto ret_einval; + if ((r = parse_histogram(a + 10, &n_histogram_entries, &histogram_boundaries))) + goto ret; + } else + goto ret_einval; } } else { as = as_backup; @@ -872,7 +1021,7 @@ static int message_stats_create(struct mapped_device *md, aux_data = a; if (as.argc) - return -EINVAL; + goto ret_einval; /* * If a buffer overflow happens after we created the region, @@ -881,17 +1030,29 @@ static int message_stats_create(struct mapped_device *md, * leaked). So we must detect buffer overflow in advance. */ snprintf(result, maxlen, "%d", INT_MAX); - if (dm_message_test_buffer_overflow(result, maxlen)) - return 1; + if (dm_message_test_buffer_overflow(result, maxlen)) { + r = 1; + goto ret; + } - id = dm_stats_create(dm_get_stats(md), start, end, step, stat_flags, program_id, aux_data, + id = dm_stats_create(dm_get_stats(md), start, end, step, stat_flags, + n_histogram_entries, histogram_boundaries, program_id, aux_data, dm_internal_suspend_fast, dm_internal_resume_fast, md); - if (id < 0) - return id; + if (id < 0) { + r = id; + goto ret; + } snprintf(result, maxlen, "%d", id); - return 1; + r = 1; + goto ret; + +ret_einval: + r = -EINVAL; +ret: + kfree(histogram_boundaries); + return r; } static int message_stats_delete(struct mapped_device *md, -- cgit v1.2.3 From 5f88d9706fa48084eaab2dbbec27779809c5106b Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 26 May 2015 23:06:34 +0200 Subject: Documentation: dmaengine: document DMA_CTRL_ACK Add documentation about acking the transfers, and their reusability. Signed-off-by: Robert Jarzmik Acked-by: Maxime Ripard Signed-off-by: Vinod Koul --- Documentation/dmaengine/provider.txt | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/dmaengine/provider.txt b/Documentation/dmaengine/provider.txt index 05d2280190f1..ca67b0f04c6e 100644 --- a/Documentation/dmaengine/provider.txt +++ b/Documentation/dmaengine/provider.txt @@ -345,11 +345,12 @@ where to put them) that abstracts it away. * DMA_CTRL_ACK - - Undocumented feature - - No one really has an idea of what it's about, besides being - related to reusing the DMA transaction descriptors or having - additional transactions added to it in the async-tx API - - Useless in the case of the slave API + - If set, the transfer can be reused after being completed. + - There is a guarantee the transfer won't be freed until it is acked + by async_tx_ack(). + - As a consequence, if a device driver wants to skip the dma_map_sg() and + dma_unmap_sg() in between 2 transfers, because the DMA'd data wasn't used, + it can resubmit the transfer right after its completion. General Design Notes -------------------- -- cgit v1.2.3 From 3e1534cf4a2a8278e811e7c84a79da1a02347b8b Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Tue, 16 Jun 2015 18:48:32 -0400 Subject: writeback, blkio: add documentation for cgroup writeback support Update Documentation/cgroups/blkio-controller.txt to reflect the recently added cgroup writeback support. Signed-off-by: Tejun Heo Cc: Li Zefan Cc: Vivek Goyal Cc: cgroups@vger.kernel.org Cc: linux-fsdevel@vger.kernel.org Signed-off-by: Jens Axboe --- Documentation/cgroups/blkio-controller.txt | 83 ++++++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cgroups/blkio-controller.txt b/Documentation/cgroups/blkio-controller.txt index cd556b914786..68b6a6a470b0 100644 --- a/Documentation/cgroups/blkio-controller.txt +++ b/Documentation/cgroups/blkio-controller.txt @@ -387,8 +387,81 @@ groups and put applications in that group which are not driving enough IO to keep disk busy. In that case set group_idle=0, and CFQ will not idle on individual groups and throughput should improve. -What works -========== -- Currently only sync IO queues are support. All the buffered writes are - still system wide and not per group. Hence we will not see service - differentiation between buffered writes between groups. +Writeback +========= + +Page cache is dirtied through buffered writes and shared mmaps and +written asynchronously to the backing filesystem by the writeback +mechanism. Writeback sits between the memory and IO domains and +regulates the proportion of dirty memory by balancing dirtying and +write IOs. + +On traditional cgroup hierarchies, relationships between different +controllers cannot be established making it impossible for writeback +to operate accounting for cgroup resource restrictions and all +writeback IOs are attributed to the root cgroup. + +If both the blkio and memory controllers are used on the v2 hierarchy +and the filesystem supports cgroup writeback, writeback operations +correctly follow the resource restrictions imposed by both memory and +blkio controllers. + +Writeback examines both system-wide and per-cgroup dirty memory status +and enforces the more restrictive of the two. Also, writeback control +parameters which are absolute values - vm.dirty_bytes and +vm.dirty_background_bytes - are distributed across cgroups according +to their current writeback bandwidth. + +There's a peculiarity stemming from the discrepancy in ownership +granularity between memory controller and writeback. While memory +controller tracks ownership per page, writeback operates on inode +basis. cgroup writeback bridges the gap by tracking ownership by +inode but migrating ownership if too many foreign pages, pages which +don't match the current inode ownership, have been encountered while +writing back the inode. + +This is a conscious design choice as writeback operations are +inherently tied to inodes making strictly following page ownership +complicated and inefficient. The only use case which suffers from +this compromise is multiple cgroups concurrently dirtying disjoint +regions of the same inode, which is an unlikely use case and decided +to be unsupported. Note that as memory controller assigns page +ownership on the first use and doesn't update it until the page is +released, even if cgroup writeback strictly follows page ownership, +multiple cgroups dirtying overlapping areas wouldn't work as expected. +In general, write-sharing an inode across multiple cgroups is not well +supported. + +Filesystem support for cgroup writeback +--------------------------------------- + +A filesystem can make writeback IOs cgroup-aware by updating +address_space_operations->writepage[s]() to annotate bio's using the +following two functions. + +* wbc_init_bio(@wbc, @bio) + + Should be called for each bio carrying writeback data and associates + the bio with the inode's owner cgroup. Can be called anytime + between bio allocation and submission. + +* wbc_account_io(@wbc, @page, @bytes) + + Should be called for each data segment being written out. While + this function doesn't care exactly when it's called during the + writeback session, it's the easiest and most natural to call it as + data segments are added to a bio. + +With writeback bio's annotated, cgroup support can be enabled per +super_block by setting MS_CGROUPWB in ->s_flags. This allows for +selective disabling of cgroup writeback support which is helpful when +certain filesystem features, e.g. journaled data mode, are +incompatible. + +wbc_init_bio() binds the specified bio to its cgroup. Depending on +the configuration, the bio may be executed at a lower priority and if +the writeback session is holding shared resources, e.g. a journal +entry, may lead to priority inversion. There is no one easy solution +for the problem. Filesystems can try to work around specific problem +cases by skipping wbc_init_bio() or using bio_associate_blkcg() +directly. -- cgit v1.2.3 From 62a993df31f795d87bcb4c6cb005d36f32f6ad55 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 18 Jun 2015 15:07:35 +0200 Subject: irqchip: atmel-aic5: Add sama5d2 support Add sama5d2 support to irq-atmel-aic5. Signed-off-by: Nicolas Ferre Cc: Boris BREZILLON Cc: Alexandre Belloni Cc: Ludovic Desroches Cc: Jason Cooper Cc: Link: http://lkml.kernel.org/r/1434632855-27272-1-git-send-email-nicolas.ferre@atmel.com Signed-off-by: Thomas Gleixner --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- drivers/irqchip/irq-atmel-aic5.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index f292917fa00d..0e9f09a6a2fe 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -2,7 +2,7 @@ Required properties: - compatible: Should be "atmel,-aic" - can be "at91rm9200", "sama5d3" or "sama5d4" + can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - interrupt-controller: Identifies the node as an interrupt controller. - interrupt-parent: For single AIC system, it is an empty property. - #interrupt-cells: The number of cells to define the interrupts. It should be 3. diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index a2e8c3f876cb..459bf4429d36 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -339,6 +339,15 @@ static int __init aic5_of_init(struct device_node *node, return 0; } +#define NR_SAMA5D2_IRQS 77 + +static int __init sama5d2_aic5_of_init(struct device_node *node, + struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAMA5D2_IRQS); +} +IRQCHIP_DECLARE(sama5d2_aic5, "atmel,sama5d2-aic", sama5d2_aic5_of_init); + #define NR_SAMA5D3_IRQS 48 static int __init sama5d3_aic5_of_init(struct device_node *node, -- cgit v1.2.3 From 476276d69d84edd4f5de9711f55c810dfc69c26c Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Tue, 5 May 2015 11:13:18 -0700 Subject: clk: iproc: define Broadcom iProc clock binding Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Michael Turquette --- .../bindings/clock/brcm,iproc-clocks.txt | 132 +++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt new file mode 100644 index 000000000000..da8d9bb5751c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -0,0 +1,132 @@ +Broadcom iProc Family Clocks + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +The iProc clock controller manages clocks that are common to the iProc family. +An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL, +LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL +comprises of several leaf clocks + +Required properties for a PLL and its leaf clocks: + +- compatible: + Should have a value of the form "brcm,-". For example, GENPLL on +Cygnus has a compatible string of "brcm,cygnus-genpll" + +- #clock-cells: + Have a value of <1> since there are more than 1 leaf clock of a given PLL + +- reg: + Define the base and range of the I/O address space that contain the iProc +clock control registers required for the PLL + +- clocks: + The input parent clock phandle for the PLL. For most iProc PLLs, this is an +onboard crystal with a fixed rate + +- clock-output-names: + An ordered list of strings defining the names of the clocks + +Example: + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + genpll: genpll { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; + clocks = <&osc>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; + }; + +Required properties for ASIU clocks: + +ASIU clocks are a special case. These clocks are derived directly from the +reference clock of the onboard crystal + +- compatible: + Should have a value of the form "brcm,-asiu-clk". For example, ASIU +clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk" + +- #clock-cells: + Have a value of <1> since there are more than 1 ASIU clocks + +- reg: + Define the base and range of the I/O address space that contain the iProc +clock control registers required for ASIU clocks + +- clocks: + The input parent clock phandle for the ASIU clock, i.e., the onboard +crystal + +- clock-output-names: + An ordered list of strings defining the names of the ASIU clocks + +Example: + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + asiu_clks: asiu_clks { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x0301d048 0xc>, <0x180aa024 0x4>; + clocks = <&osc>; + clock-output-names = "keypad", "adc/touch", "pwm"; + }; + +Cygnus +------ +PLL and leaf clock compatible strings for Cygnus are: + "brcm,cygnus-armpll" + "brcm,cygnus-genpll" + "brcm,cygnus-lcpll0" + "brcm,cygnus-mipipll" + "brcm,cygnus-asiu-clk" + +The following table defines the set of PLL/clock index and ID for Cygnus. +These clock IDs are defined in: + "include/dt-bindings/clock/bcm-cygnus.h" + + Clock Source (Parent) Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK + adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK + pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK + + genpll crystal 0 BCM_CYGNUS_GENPLL + axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK + 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK + ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK + enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK + audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK + can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK + + lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 + pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK + ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK + sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK + usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK + smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK + ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED + + mipipll crystal 0 BCM_CYGNUS_MIPIPLL + ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED + ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD + ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D + ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED + ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED + ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED -- cgit v1.2.3 From d0b30c983f0e3793193a96697e59cfaaba594501 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Tue, 5 May 2015 11:13:23 -0700 Subject: clk: cygnus: remove Cygnus dummy clock binding Remove old Cygnus dummy clock binding document, as it's replaced by Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt Signed-off-by: Ray Jui Signed-off-by: Michael Turquette --- .../devicetree/bindings/clock/bcm-cygnus-clock.txt | 34 ---------------------- 1 file changed, 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt deleted file mode 100644 index 00d26edec8bc..000000000000 --- a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom Cygnus Clocks - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -Currently various "fixed" clocks are declared for peripheral drivers that use -the common clock framework to reference their core clocks. Proper support of -these clocks will be added later - -Device tree example: - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <25000000>; - }; - - apb_clk: apb_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - periph_clk: periph_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - }; - }; -- cgit v1.2.3 From 8a0792ef8e01f03cb43806c6a87738bde34df713 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 18 Jun 2015 16:54:28 -0400 Subject: cgroup: add delegation section to unified hierarchy documentation v2: Rearranged paragraphs as suggested by Johannes Weiner. Signed-off-by: Tejun Heo Acked-by: Johannes Weiner --- Documentation/cgroups/unified-hierarchy.txt | 102 +++++++++++++++++++++++----- 1 file changed, 84 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/cgroups/unified-hierarchy.txt b/Documentation/cgroups/unified-hierarchy.txt index eb102fb72213..86847a7647ab 100644 --- a/Documentation/cgroups/unified-hierarchy.txt +++ b/Documentation/cgroups/unified-hierarchy.txt @@ -17,15 +17,18 @@ CONTENTS 3. Structural Constraints 3-1. Top-down 3-2. No internal tasks -4. Other Changes - 4-1. [Un]populated Notification - 4-2. Other Core Changes - 4-3. Per-Controller Changes - 4-3-1. blkio - 4-3-2. cpuset - 4-3-3. memory -5. Planned Changes - 5-1. CAP for resource control +4. Delegation + 4-1. Model of delegation + 4-2. Common ancestor rule +5. Other Changes + 5-1. [Un]populated Notification + 5-2. Other Core Changes + 5-3. Per-Controller Changes + 5-3-1. blkio + 5-3-2. cpuset + 5-3-3. memory +6. Planned Changes + 6-1. CAP for resource control 1. Background @@ -245,9 +248,72 @@ cgroup must create children and transfer all its tasks to the children before enabling controllers in its "cgroup.subtree_control" file. -4. Other Changes +4. Delegation -4-1. [Un]populated Notification +4-1. Model of delegation + +A cgroup can be delegated to a less privileged user by granting write +access of the directory and its "cgroup.procs" file to the user. Note +that the resource control knobs in a given directory concern the +resources of the parent and thus must not be delegated along with the +directory. + +Once delegated, the user can build sub-hierarchy under the directory, +organize processes as it sees fit and further distribute the resources +it got from the parent. The limits and other settings of all resource +controllers are hierarchical and regardless of what happens in the +delegated sub-hierarchy, nothing can escape the resource restrictions +imposed by the parent. + +Currently, cgroup doesn't impose any restrictions on the number of +cgroups in or nesting depth of a delegated sub-hierarchy; however, +this may in the future be limited explicitly. + + +4-2. Common ancestor rule + +On the unified hierarchy, to write to a "cgroup.procs" file, in +addition to the usual write permission to the file and uid match, the +writer must also have write access to the "cgroup.procs" file of the +common ancestor of the source and destination cgroups. This prevents +delegatees from smuggling processes across disjoint sub-hierarchies. + +Let's say cgroups C0 and C1 have been delegated to user U0 who created +C00, C01 under C0 and C10 under C1 as follows. + + ~~~~~~~~~~~~~ - C0 - C00 + ~ cgroup ~ \ C01 + ~ hierarchy ~ + ~~~~~~~~~~~~~ - C1 - C10 + +C0 and C1 are separate entities in terms of resource distribution +regardless of their relative positions in the hierarchy. The +resources the processes under C0 are entitled to are controlled by +C0's ancestors and may be completely different from C1. It's clear +that the intention of delegating C0 to U0 is allowing U0 to organize +the processes under C0 and further control the distribution of C0's +resources. + +On traditional hierarchies, if a task has write access to "tasks" or +"cgroup.procs" file of a cgroup and its uid agrees with the target, it +can move the target to the cgroup. In the above example, U0 will not +only be able to move processes in each sub-hierarchy but also across +the two sub-hierarchies, effectively allowing it to violate the +organizational and resource restrictions implied by the hierarchical +structure above C0 and C1. + +On the unified hierarchy, let's say U0 wants to write the pid of a +process which has a matching uid and is currently in C10 into +"C00/cgroup.procs". U0 obviously has write access to the file and +migration permission on the process; however, the common ancestor of +the source cgroup C10 and the destination cgroup C00 is above the +points of delegation and U0 would not have write access to its +"cgroup.procs" and thus be denied with -EACCES. + + +5. Other Changes + +5-1. [Un]populated Notification cgroup users often need a way to determine when a cgroup's subhierarchy becomes empty so that it can be cleaned up. cgroup @@ -289,7 +355,7 @@ supported and the interface files "release_agent" and "notify_on_release" do not exist. -4-2. Other Core Changes +5-2. Other Core Changes - None of the mount options is allowed. @@ -306,14 +372,14 @@ supported and the interface files "release_agent" and - The "cgroup.clone_children" file is removed. -4-3. Per-Controller Changes +5-3. Per-Controller Changes -4-3-1. blkio +5-3-1. blkio - blk-throttle becomes properly hierarchical. -4-3-2. cpuset +5-3-2. cpuset - Tasks are kept in empty cpusets after hotplug and take on the masks of the nearest non-empty ancestor, instead of being moved to it. @@ -322,7 +388,7 @@ supported and the interface files "release_agent" and masks of the nearest non-empty ancestor. -4-3-3. memory +5-3-3. memory - use_hierarchy is on by default and the cgroup file for the flag is not created. @@ -407,9 +473,9 @@ supported and the interface files "release_agent" and memory.low, memory.high, and memory.max will use the string "max" to indicate and set the highest possible value. -5. Planned Changes +6. Planned Changes -5-1. CAP for resource control +6-1. CAP for resource control Unified hierarchy will require one of the capabilities(7), which is yet to be decided, for all resource control related knobs. Process -- cgit v1.2.3 From 02fdfd708fd252a778709beb6c65d5e7360341ac Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Fri, 29 May 2015 12:04:12 -0400 Subject: clk: keystone: add support for post divider register for main pll Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri Signed-off-by: Michael Turquette --- .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++---- drivers/clk/keystone/pll.c | 20 ++++++++++++++++++-- 2 files changed, 22 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt index 225990f79b7c..47570d207215 100644 --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt @@ -15,8 +15,8 @@ Required properties: - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" - clocks : parent clock phandle - reg - pll control0 and pll multipler registers -- reg-names : control and multiplier. The multiplier is applicable only for - main pll clock +- reg-names : control, multiplier and post-divider. The multiplier and + post-divider registers are applicable only for main pll clock - fixed-postdiv : fixed post divider value. If absent, use clkod register bits for postdiv @@ -25,8 +25,8 @@ Example: #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; fixed-postdiv = <2>; }; diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 0dd8a4b12747..4a375ead70e9 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -37,7 +37,8 @@ * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL * or PA PLL available on keystone2. These PLLs are controlled by * this register. Main PLL is controlled by a PLL controller. - * @pllm: PLL register map address + * @pllm: PLL register map address for multiplier bits + * @pllod: PLL register map address for post divider bits * @pll_ctl0: PLL controller map address * @pllm_lower_mask: multiplier lower mask * @pllm_upper_mask: multiplier upper mask @@ -53,6 +54,7 @@ struct clk_pll_data { u32 phy_pllm; u32 phy_pll_ctl0; void __iomem *pllm; + void __iomem *pllod; void __iomem *pll_ctl0; u32 pllm_lower_mask; u32 pllm_upper_mask; @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, /* read post divider from od bits*/ postdiv = ((val & pll_data->clkod_mask) >> pll_data->clkod_shift) + 1; - else + else if (pll_data->pllod) { + postdiv = readl(pll_data->pllod); + postdiv = ((postdiv & pll_data->clkod_mask) >> + pll_data->clkod_shift) + 1; + } else postdiv = pll_data->postdiv; rate /= (prediv + 1); @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) /* assume the PLL has output divider register bits */ pll_data->clkod_mask = CLKOD_MASK; pll_data->clkod_shift = CLKOD_SHIFT; + + /* + * Check if there is an post-divider register. If not + * assume od bits are part of control register. + */ + i = of_property_match_string(node, "reg-names", + "post-divider"); + pll_data->pllod = of_iomap(node, i); } i = of_property_match_string(node, "reg-names", "control"); pll_data->pll_ctl0 = of_iomap(node, i); if (!pll_data->pll_ctl0) { pr_err("%s: ioremap failed\n", __func__); + iounmap(pll_data->pllod); goto out; } @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) pll_data->pllm = of_iomap(node, i); if (!pll_data->pllm) { iounmap(pll_data->pll_ctl0); + iounmap(pll_data->pllod); goto out; } } -- cgit v1.2.3 From 668c45df36939fbf0a3578ad97f547c8db86a7a0 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 28 May 2015 22:31:44 +0200 Subject: doc: dt: add documentation for lpc1850-cgu clk driver Add DT binding documentation for lpc1850-cgu driver. Signed-off-by: Joachim Eastwood Signed-off-by: Michael Turquette --- .../devicetree/bindings/clock/lpc1850-cgu.txt | 131 +++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt new file mode 100644 index 000000000000..2cc32a9a945a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/lpc1850-cgu.txt @@ -0,0 +1,131 @@ +* NXP LPC1850 Clock Generation Unit (CGU) + +The CGU generates multiple independent clocks for the core and the +peripheral blocks of the LPC18xx. Each independent clock is called +a base clock and itself is one of the inputs to the two Clock +Control Units (CCUs) which control the branch clocks to the +individual peripherals. + +The CGU selects the inputs to the clock generators from multiple +clock sources, controls the clock generation, and routes the outputs +of the clock generators through the clock source bus to the output +stages. Each output stage provides an independent clock source and +corresponds to one of the base clocks for the LPC18xx. + + - Above text taken from NXP LPC1850 User Manual. + + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-cgu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the base clock numbers defined below. +- clocks: + Shall contain a list of phandles for the external input + sources to the CGU. The list shall be in the following + order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin. +- clock-indices: + Shall be an ordered list of numbers defining the base clock + number provided by the CGU. +- clock-output-names: + Shall be an ordered list of strings defining the names of + the clocks provided by the CGU. + +Which base clocks that are available on the CGU depends on the +specific LPC part. Base clocks are numbered from 0 to 27. + +Number: Name: Description: + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT + 1 BASE_USB0_CLK Base clock for USB0 + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, + SPI, and SGPIO + 3 BASE_USB1_CLK Base clock for USB1 + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core + and APB peripheral blocks #0 and #2 + 5 BASE_SPIFI_CLK Base clock for SPIFI + 6 BASE_SPI_CLK Base clock for SPI + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 +11 BASE_LCD_CLK Base clock for LCD +12 BASE_ADCHS_CLK Base clock for ADCHS +13 BASE_SDIO_CLK Base clock for SD/MMC +14 BASE_SSP0_CLK Base clock for SSP0 +15 BASE_SSP1_CLK Base clock for SSP1 +16 BASE_UART0_CLK Base clock for UART0 +17 BASE_UART1_CLK Base clock for UART1 +18 BASE_UART2_CLK Base clock for UART2 +19 BASE_UART3_CLK Base clock for UART3 +20 BASE_OUT_CLK Base clock for CLKOUT pin +24-21 - Reserved +25 BASE_AUDIO_CLK Base clock for audio system (I2S) +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output + +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. +BASE_ADCHS_CLK is only available on LPC4370. + + +Example board file: + +/ { + clocks { + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; + }; + }; + + soc { + cgu: clock-controller@40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + /* A CGU and CCU clock consumer */ + lcdc: lcdc@40008000 { + ... + clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; + clock-names = "clcdclk", "apb_pclk"; + ... + }; + }; +}; -- cgit v1.2.3 From ddfb157444e3cdb6da18ea759730b4b4af65d3d9 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 28 May 2015 22:31:46 +0200 Subject: doc: dt: add documentation for lpc1850-ccu clk driver Add DT binding documentation for lpc1850-ccu clk driver. Signed-off-by: Joachim Eastwood Signed-off-by: Michael Turquette --- .../devicetree/bindings/clock/lpc1850-ccu.txt | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-ccu.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt new file mode 100644 index 000000000000..fa97c12014ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt @@ -0,0 +1,77 @@ +* NXP LPC1850 Clock Control Unit (CCU) + +Each CGU base clock has several clock branches which can be turned on +or off independently by the Clock Control Units CCU1 or CCU2. The +branch clocks are distributed between CCU1 and CCU2. + + - Above text taken from NXP LPC1850 User Manual. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-ccu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the branch clock names defined in table below. +- clocks: + Shall contain a list of phandles for the base clocks routed + from the CGU to the specific CCU. See mapping of base clocks + and CCU in table below. +- clock-names: + Shall contain a list of names for the base clock routed + from the CGU to the specific CCU. Valid CCU clock names: + "base_usb0_clk", "base_periph_clk", "base_usb1_clk", + "base_cpu_clk", "base_spifi_clk", "base_spi_clk", + "base_apb1_clk", "base_apb3_clk", "base_adchs_clk", + "base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk", + "base_uart0_clk", "base_uart1_clk", "base_uart2_clk", + "base_uart3_clk", "base_audio_clk" + +Which branch clocks that are available on the CCU depends on the +specific LPC part. Check the user manual for your specific part. + +A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h. + +Example board file: + +soc { + ccu1: clock-controller@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + + /* A user of CCU brach clocks */ + uart1: serial@40082000 { + ... + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + ... + }; +}; -- cgit v1.2.3 From eb3486646187fe2010786e1d092a903343fbcc64 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 15 Jun 2015 13:48:00 +0200 Subject: ACPI / enumeration: Document the rules regarding the PRP0001 device ID Document how the ACPI device enumeration code uses the special PRP0001 device ID. Signed-off-by: Rafael J. Wysocki Acked-by: Mika Westerberg Reviewed-by: Hanjun Guo Reviewed-by: Darren Hart --- Documentation/acpi/enumeration.txt | 51 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'Documentation') diff --git a/Documentation/acpi/enumeration.txt b/Documentation/acpi/enumeration.txt index 15dfce708ebf..f44b0093d177 100644 --- a/Documentation/acpi/enumeration.txt +++ b/Documentation/acpi/enumeration.txt @@ -359,3 +359,54 @@ the id should be set like: The ACPI id "XYZ0001" is then used to lookup an ACPI device directly under the MFD device and if found, that ACPI companion device is bound to the resulting child platform device. + +Device Tree namespace link device ID +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The Device Tree protocol uses device indentification based on the "compatible" +property whose value is a string or an array of strings recognized as device +identifiers by drivers and the driver core. The set of all those strings may be +regarded as a device indentification namespace analogous to the ACPI/PNP device +ID namespace. Consequently, in principle it should not be necessary to allocate +a new (and arguably redundant) ACPI/PNP device ID for a devices with an existing +identification string in the Device Tree (DT) namespace, especially if that ID +is only needed to indicate that a given device is compatible with another one, +presumably having a matching driver in the kernel already. + +In ACPI, the device identification object called _CID (Compatible ID) is used to +list the IDs of devices the given one is compatible with, but those IDs must +belong to one of the namespaces prescribed by the ACPI specification (see +Section 6.1.2 of ACPI 6.0 for details) and the DT namespace is not one of them. +Moreover, the specification mandates that either a _HID or an _ADR identificaion +object be present for all ACPI objects representing devices (Section 6.1 of ACPI +6.0). For non-enumerable bus types that object must be _HID and its value must +be a device ID from one of the namespaces prescribed by the specification too. + +The special DT namespace link device ID, PRP0001, provides a means to use the +existing DT-compatible device identification in ACPI and to satisfy the above +requirements following from the ACPI specification at the same time. Namely, +if PRP0001 is returned by _HID, the ACPI subsystem will look for the +"compatible" property in the device object's _DSD and will use the value of that +property to identify the corresponding device in analogy with the original DT +device identification algorithm. If the "compatible" property is not present +or its value is not valid, the device will not be enumerated by the ACPI +subsystem. Otherwise, it will be enumerated automatically as a platform device +(except when an I2C or SPI link from the device to its parent is present, in +which case the ACPI core will leave the device enumeration to the parent's +driver) and the identification strings from the "compatible" property value will +be used to find a driver for the device along with the device IDs listed by _CID +(if present). + +Analogously, if PRP0001 is present in the list of device IDs returned by _CID, +the identification strings listed by the "compatible" property value (if present +and valid) will be used to look for a driver matching the device, but in that +case their relative priority with respect to the other device IDs listed by +_HID and _CID depends on the position of PRP0001 in the _CID return package. +Specifically, the device IDs returned by _HID and preceding PRP0001 in the _CID +return package will be checked first. Also in that case the bus type the device +will be enumerated to depends on the device ID returned by _HID. + +It is valid to define device objects with a _HID returning PRP0001 and without +the "compatible" property in the _DSD or a _CID as long as one of their +ancestors provides a _DSD with a valid "compatible" property. Such device +objects are then simply regarded as additional "blocks" providing hierarchical +configuration information to the driver of the composite ancestor device. -- cgit v1.2.3 From 1a147ed75cc94cb2eca3bfa5ca00e069574090fd Mon Sep 17 00:00:00 2001 From: Mathias Krause Date: Sat, 13 Jun 2015 14:27:00 +0200 Subject: ACPI: Constify ACPI device IDs in documentation ACPI device ID arrays normally don't need to be written to as they're only ever read. The common usage -- embedding pointers to acpi_device_id arrays in other data structures -- reference them as 'const', e.g. as in struct acpi_driver / acpi_scan_handler / device_driver. The matchers are taking const pointers, too. So it's only natural, to propose using const arrays. Change the documentation accordingly. Signed-off-by: Mathias Krause Signed-off-by: Rafael J. Wysocki --- Documentation/acpi/enumeration.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/acpi/enumeration.txt b/Documentation/acpi/enumeration.txt index f44b0093d177..b731b292e812 100644 --- a/Documentation/acpi/enumeration.txt +++ b/Documentation/acpi/enumeration.txt @@ -42,7 +42,7 @@ Adding ACPI support for an existing driver should be pretty straightforward. Here is the simplest example: #ifdef CONFIG_ACPI - static struct acpi_device_id mydrv_acpi_match[] = { + static const struct acpi_device_id mydrv_acpi_match[] = { /* ACPI IDs here */ { } }; @@ -166,7 +166,7 @@ the platform device drivers. Below is an example where we add ACPI support to at25 SPI eeprom driver (this is meant for the above ACPI snippet): #ifdef CONFIG_ACPI - static struct acpi_device_id at25_acpi_match[] = { + static const struct acpi_device_id at25_acpi_match[] = { { "AT25", 0 }, { }, }; @@ -230,7 +230,7 @@ Below is an example of how to add ACPI support to the existing mpu3050 input driver: #ifdef CONFIG_ACPI - static struct acpi_device_id mpu3050_acpi_match[] = { + static const struct acpi_device_id mpu3050_acpi_match[] = { { "MPU3050", 0 }, { }, }; -- cgit v1.2.3 From b4b56f9ecab40f3b4ef53e130c9f6663be491894 Mon Sep 17 00:00:00 2001 From: Sam bobroff Date: Fri, 12 Jun 2015 11:06:32 +1000 Subject: powerpc/tm: Abort syscalls in active transactions This patch changes the syscall handler to doom (tabort) active transactions when a syscall is made and return very early without performing the syscall and keeping side effects to a minimum (no CPU accounting or system call tracing is performed). Also included is a new HWCAP2 bit, PPC_FEATURE2_HTM_NOSC, to indicate this behaviour to userspace. Currently, the system call instruction automatically suspends an active transaction which causes side effects to persist when an active transaction fails. This does change the kernel's behaviour, but in a way that was documented as unsupported. It doesn't reduce functionality as syscalls will still be performed after tsuspend; it just requires that the transaction be explicitly suspended. It also provides a consistent interface and makes the behaviour of user code substantially the same across powerpc and platforms that do not support suspended transactions (e.g. x86 and s390). Performance measurements using http://ozlabs.org/~anton/junkcode/null_syscall.c indicate the cost of a normal (non-aborted) system call increases by about 0.25%. Signed-off-by: Sam Bobroff Signed-off-by: Michael Ellerman --- Documentation/powerpc/transactional_memory.txt | 32 +++++++++++----------- arch/powerpc/include/asm/cputable.h | 10 ++++--- arch/powerpc/include/uapi/asm/cputable.h | 1 + arch/powerpc/include/uapi/asm/tm.h | 2 +- arch/powerpc/kernel/cputable.c | 4 ++- arch/powerpc/kernel/entry_64.S | 35 +++++++++++++++++++++++++ tools/testing/selftests/powerpc/tm/Makefile | 4 +-- tools/testing/selftests/powerpc/tm/tm-syscall.c | 3 ++- 8 files changed, 66 insertions(+), 25 deletions(-) (limited to 'Documentation') diff --git a/Documentation/powerpc/transactional_memory.txt b/Documentation/powerpc/transactional_memory.txt index ded69794a5c0..ba0a2a4a54ba 100644 --- a/Documentation/powerpc/transactional_memory.txt +++ b/Documentation/powerpc/transactional_memory.txt @@ -74,22 +74,23 @@ Causes of transaction aborts Syscalls ======== -Performing syscalls from within transaction is not recommended, and can lead -to unpredictable results. +Syscalls made from within an active transaction will not be performed and the +transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL +| TM_CAUSE_PERSISTENT. -Syscalls do not by design abort transactions, but beware: The kernel code will -not be running in transactional state. The effect of syscalls will always -remain visible, but depending on the call they may abort your transaction as a -side-effect, read soon-to-be-aborted transactional data that should not remain -invisible, etc. If you constantly retry a transaction that constantly aborts -itself by calling a syscall, you'll have a livelock & make no progress. +Syscalls made from within a suspended transaction are performed as normal and +the transaction is not explicitly doomed by the kernel. However, what the +kernel does to perform the syscall may result in the transaction being doomed +by the hardware. The syscall is performed in suspended mode so any side +effects will be persistent, independent of transaction success or failure. No +guarantees are provided by the kernel about which syscalls will affect +transaction success. -Simple syscalls (e.g. sigprocmask()) "could" be OK. Even things like write() -from, say, printf() should be OK as long as the kernel does not access any -memory that was accessed transactionally. - -Consider any syscalls that happen to work as debug-only -- not recommended for -production use. Best to queue them up till after the transaction is over. +Care must be taken when relying on syscalls to abort during active transactions +if the calls are made via a library. Libraries may cache values (which may +give the appearance of success) or perform operations that cause transaction +failure before entering the kernel (which may produce different failure codes). +Examples are glibc's getpid() and lazy symbol resolution. Signals @@ -176,8 +177,7 @@ kernel aborted a transaction: TM_CAUSE_RESCHED Thread was rescheduled. TM_CAUSE_TLBI Software TLB invalid. TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap. - TM_CAUSE_SYSCALL Currently unused; future syscalls that must abort - transactions for consistency will use this. + TM_CAUSE_SYSCALL Syscall from active transaction. TM_CAUSE_SIGNAL Signal delivered. TM_CAUSE_MISC Currently unused. TM_CAUSE_ALIGNMENT Alignment fault. diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 6367b8347dad..4994648b9265 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -242,11 +242,13 @@ enum { /* We only set the TM feature if the kernel was compiled with TM supprt */ #ifdef CONFIG_PPC_TRANSACTIONAL_MEM -#define CPU_FTR_TM_COMP CPU_FTR_TM -#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM +#define CPU_FTR_TM_COMP CPU_FTR_TM +#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM +#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC #else -#define CPU_FTR_TM_COMP 0 -#define PPC_FEATURE2_HTM_COMP 0 +#define CPU_FTR_TM_COMP 0 +#define PPC_FEATURE2_HTM_COMP 0 +#define PPC_FEATURE2_HTM_NOSC_COMP 0 #endif /* We need to mark all pages as being coherent if we're SMP or we have a diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h index de2c0e4ee1aa..43686043e297 100644 --- a/arch/powerpc/include/uapi/asm/cputable.h +++ b/arch/powerpc/include/uapi/asm/cputable.h @@ -42,5 +42,6 @@ #define PPC_FEATURE2_ISEL 0x08000000 #define PPC_FEATURE2_TAR 0x04000000 #define PPC_FEATURE2_VEC_CRYPTO 0x02000000 +#define PPC_FEATURE2_HTM_NOSC 0x01000000 #endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */ diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h index 5d836b7c1176..5047659815a5 100644 --- a/arch/powerpc/include/uapi/asm/tm.h +++ b/arch/powerpc/include/uapi/asm/tm.h @@ -11,7 +11,7 @@ #define TM_CAUSE_RESCHED 0xde #define TM_CAUSE_TLBI 0xdc #define TM_CAUSE_FAC_UNAV 0xda -#define TM_CAUSE_SYSCALL 0xd8 /* future use */ +#define TM_CAUSE_SYSCALL 0xd8 #define TM_CAUSE_MISC 0xd6 /* future use */ #define TM_CAUSE_SIGNAL 0xd4 #define TM_CAUSE_ALIGNMENT 0xd2 diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 60262fdf35ba..7d80bfdfb15e 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -108,7 +108,9 @@ extern void __restore_cpu_e6500(void); PPC_FEATURE_TRUE_LE | \ PPC_FEATURE_PSERIES_PERFMON_COMPAT) #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \ - PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \ + PPC_FEATURE2_HTM_COMP | \ + PPC_FEATURE2_HTM_NOSC_COMP | \ + PPC_FEATURE2_DSCR | \ PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \ PPC_FEATURE2_VEC_CRYPTO) #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 278888e89acc..579e0f9a2d57 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -34,6 +34,7 @@ #include #include #include +#include /* * System calls. @@ -51,6 +52,12 @@ exception_marker: .globl system_call_common system_call_common: +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +BEGIN_FTR_SECTION + extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ + bne tabort_syscall +END_FTR_SECTION_IFSET(CPU_FTR_TM) +#endif andi. r10,r12,MSR_PR mr r10,r1 addi r1,r1,-INT_FRAME_SIZE @@ -311,6 +318,34 @@ syscall_exit_work: bl do_syscall_trace_leave b ret_from_except +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +tabort_syscall: + /* Firstly we need to enable TM in the kernel */ + mfmsr r10 + li r13, 1 + rldimi r10, r13, MSR_TM_LG, 63-MSR_TM_LG + mtmsrd r10, 0 + + /* tabort, this dooms the transaction, nothing else */ + li r13, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT) + TABORT(R13) + + /* + * Return directly to userspace. We have corrupted user register state, + * but userspace will never see that register state. Execution will + * resume after the tbegin of the aborted transaction with the + * checkpointed register state. + */ + li r13, MSR_RI + andc r10, r10, r13 + mtmsrd r10, 1 + mtspr SPRN_SRR0, r11 + mtspr SPRN_SRR1, r12 + + rfid + b . /* prevent speculative execution */ +#endif + /* Save non-volatile GPRs, if not already saved. */ _GLOBAL(save_nvgprs) ld r11,_TRAP(r1) diff --git a/tools/testing/selftests/powerpc/tm/Makefile b/tools/testing/selftests/powerpc/tm/Makefile index 6bff955e1d55..4bea62a319dc 100644 --- a/tools/testing/selftests/powerpc/tm/Makefile +++ b/tools/testing/selftests/powerpc/tm/Makefile @@ -1,11 +1,11 @@ -TEST_PROGS := tm-resched-dscr +TEST_PROGS := tm-resched-dscr tm-syscall all: $(TEST_PROGS) $(TEST_PROGS): ../harness.c tm-syscall: tm-syscall-asm.S -tm-syscall: CFLAGS += -mhtm +tm-syscall: CFLAGS += -mhtm -I../../../../../usr/include include ../../lib.mk diff --git a/tools/testing/selftests/powerpc/tm/tm-syscall.c b/tools/testing/selftests/powerpc/tm/tm-syscall.c index 3ed8d4b252fa..1276e23da63b 100644 --- a/tools/testing/selftests/powerpc/tm/tm-syscall.c +++ b/tools/testing/selftests/powerpc/tm/tm-syscall.c @@ -82,7 +82,8 @@ int tm_syscall(void) unsigned count = 0; struct timeval end, now; - SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM)); + SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) + & PPC_FEATURE2_HTM_NOSC)); setbuf(stdout, NULL); printf("Testing transactional syscalls for %d seconds...\n", TEST_DURATION); -- cgit v1.2.3 From 556cc1c5f528dcc87733920de17d61b6ebe8999d Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 27 Jan 2014 14:51:34 +0100 Subject: ARC: [axs101] Add support for AXS101 SDP (software development platform) The AXS10x platforms consist of a mainboard with peripherals, on which several daughter cards can be placed. The daughter cards typically contain a CPU and memory. Signed-off-by: Mischa Jonker Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta --- Documentation/devicetree/bindings/arc/axs101.txt | 7 + MAINTAINERS | 7 + arch/arc/Kconfig | 1 + arch/arc/Makefile | 1 + arch/arc/boot/dts/axc001.dtsi | 79 ++++++ arch/arc/boot/dts/axs101.dts | 21 ++ arch/arc/boot/dts/axs10x_mb.dtsi | 223 +++++++++++++++++ arch/arc/configs/axs101_defconfig | 111 +++++++++ arch/arc/plat-axs10x/Kconfig | 35 +++ arch/arc/plat-axs10x/Makefile | 9 + arch/arc/plat-axs10x/axs10x.c | 298 +++++++++++++++++++++++ 11 files changed, 792 insertions(+) create mode 100644 Documentation/devicetree/bindings/arc/axs101.txt create mode 100644 arch/arc/boot/dts/axc001.dtsi create mode 100644 arch/arc/boot/dts/axs101.dts create mode 100644 arch/arc/boot/dts/axs10x_mb.dtsi create mode 100644 arch/arc/configs/axs101_defconfig create mode 100644 arch/arc/plat-axs10x/Kconfig create mode 100644 arch/arc/plat-axs10x/Makefile create mode 100644 arch/arc/plat-axs10x/axs10x.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arc/axs101.txt b/Documentation/devicetree/bindings/arc/axs101.txt new file mode 100644 index 000000000000..568aa5f74de2 --- /dev/null +++ b/Documentation/devicetree/bindings/arc/axs101.txt @@ -0,0 +1,7 @@ +Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings +--------------------------------------------------------------------------- + +SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon + +Required root node properties: + - compatible = "snps,axs101"; diff --git a/MAINTAINERS b/MAINTAINERS index f8e0afb708b4..3a9afc9ec050 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9579,6 +9579,13 @@ F: arch/arc/ F: Documentation/devicetree/bindings/arc/ F: drivers/tty/serial/arc_uart.c +SYNOPSYS ARC SDP platform support +M: Alexey Brodkin +S: Supported +F: arch/arc/plat-axs10x +F: arch/arc/boot/dts/ax* +F: Documentation/devicetree/bindings/arc/axs10* + SYSV FILESYSTEM M: Christoph Hellwig S: Maintained diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index b52f7eba6765..1eeefd9763d1 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -83,6 +83,7 @@ menu "ARC Platform/SoC/Board" source "arch/arc/plat-sim/Kconfig" source "arch/arc/plat-tb10x/Kconfig" +source "arch/arc/plat-axs10x/Kconfig" #New platform adds here endmenu diff --git a/arch/arc/Makefile b/arch/arc/Makefile index 435b693637f6..86c71b2089d2 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -83,6 +83,7 @@ core-y += arch/arc/boot/dts/ core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/ core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ +core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/ drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/ diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi new file mode 100644 index 000000000000..6990ca45fc7b --- /dev/null +++ b/arch/arc/boot/dts/axc001.dtsi @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC001 770D/EM6/AS221 CPU card + * Note that this file only supports the 770D CPU + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <750000000>; /* 750 MHZ */ + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: arc700-intc@cpu { + compatible = "snps,arc700-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + /* + * this GPIO block ORs all interrupts on CPU card (creg,..) + * to uplink only 1 IRQ to ARC core intc + */ + dw-apb-gpio@0x2000 { + compatible = "snps,dw-apb-gpio"; + reg = < 0x2000 0x80 >; + #address-cells = <1>; + #size-cells = <0>; + + ictl_intc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&cpu_intc>; + interrupts = <15>; + }; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <33333000>; + interrupt-parent = <&ictl_intc>; + interrupts = <19 4>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + arcpmu0: pmu { + compatible = "snps,arc700-pct"; + }; + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts new file mode 100644 index 000000000000..6c3391da0e3b --- /dev/null +++ b/arch/arc/boot/dts/axs101.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * ARC AXS101 S/W development platform + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "axc001.dtsi" +/include/ "axs10x_mb.dtsi" + +/ { + compatible = "snps,axs101"; + + chosen { + bootargs = "console=tty0 console=ttyS3,115200n8 consoleblank=0"; + }; +}; diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi new file mode 100644 index 000000000000..255c7121ea80 --- /dev/null +++ b/arch/arc/boot/dts/axs10x_mb.dtsi @@ -0,0 +1,223 @@ +/* + * Support for peripherals on the AXS10x mainboard + * + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + axs10x_mb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0xe0000000 0x10000000>; + interrupt-parent = <&mb_intc>; + + clocks { + i2cclk: i2cclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + apbclk: apbclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + mmcclk: mmcclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + }; + + /* + * This INTC is actually connected to DW APB GPIO + * which acts as a wire between MB INTC and CPU INTC. + * GPIO INTC is configured in platform init code + * and here we mimic direct connection from MB INTC to + * CPU INTC, thus we set "interrupts = <7>" instead of + * "interrupts = <12>" + */ + mb_intc: dw-apb-ictl@0x12000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0x12000 0x200 >; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + interrupts = < 7 >; + }; + + ethernet@0x18000 { + #interrupt-cells = <1>; + compatible = "snps,dwmac"; + reg = < 0x18000 0x2000 >; + interrupts = < 4 >; + interrupt-names = "macirq"; + phy-mode = "rgmii"; + snps,pbl = < 32 >; + clocks = <&apbclk>; + clock-names = "stmmaceth"; + }; + + ehci@0x40000 { + compatible = "generic-ehci"; + reg = < 0x40000 0x100 >; + interrupts = < 8 >; + }; + + ohci@0x60000 { + compatible = "generic-ohci"; + reg = < 0x60000 0x100 >; + interrupts = < 8 >; + }; + + mmc@0x15000 { + compatible = "snps,dw-mshc"; + reg = < 0x15000 0x400 >; + num-slots = < 1 >; + fifo-depth = < 16 >; + card-detect-delay = < 200 >; + clocks = <&apbclk>, <&mmcclk>; + clock-names = "biu", "ciu"; + interrupts = < 7 >; + bus-width = < 4 >; + }; + + uart@0x20000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20000 0x100>; + clock-frequency = <33333333>; + interrupts = <17>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@0x21000 { + compatible = "snps,dw-apb-uart"; + reg = <0x21000 0x100>; + clock-frequency = <33333333>; + interrupts = <18>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + /* UART muxed with USB data port (ttyS3) */ + uart@0x22000 { + compatible = "snps,dw-apb-uart"; + reg = <0x22000 0x100>; + clock-frequency = <33333333>; + interrupts = <19>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + i2c@0x1d000 { + compatible = "snps,designware-i2c"; + reg = <0x1d000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <14>; + }; + + i2c@0x1e000 { + compatible = "snps,designware-i2c"; + reg = <0x1e000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <15>; + }; + + i2c@0x1f000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1f000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <16>; + + eeprom@0x54{ + compatible = "24c01"; + reg = <0x54>; + pagesize = <0x8>; + }; + + eeprom@0x57{ + compatible = "24c04"; + reg = <0x57>; + pagesize = <0x8>; + }; + }; + + gpio0:gpio@13000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0_banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + }; + + gpio0_bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <1>; + }; + + gpio0_bankc: gpio-controller@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <2>; + }; + }; + + gpio1:gpio@14000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio1_banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + }; + + gpio1_bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <10>; + reg = <1>; + }; + + gpio1_bankc: gpio-controller@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <2>; + }; + }; + }; +}; diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig new file mode 100644 index 000000000000..562dac6a7f78 --- /dev/null +++ b/arch/arc/configs/axs101_defconfig @@ -0,0 +1,111 @@ +CONFIG_CROSS_COMPILE="arc-linux-uclibc-" +CONFIG_DEFAULT_HOSTNAME="ARCLinux" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../arc_initramfs/" +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARC_PLAT_AXS10X=y +CONFIG_AXS101=y +CONFIG_ARC_CACHE_LINE_SHIFT=5 +CONFIG_ARC_BUILTIN_DTB_NAME="axs101" +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_STMMAC_ETH=y +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NATIONAL_PHY=y +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_INPUT_EVDEV=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=y +CONFIG_MOUSE_SYNAPTICS_USB=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_HWMON is not set +CONFIG_FB=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set diff --git a/arch/arc/plat-axs10x/Kconfig b/arch/arc/plat-axs10x/Kconfig new file mode 100644 index 000000000000..45641ca8aba8 --- /dev/null +++ b/arch/arc/plat-axs10x/Kconfig @@ -0,0 +1,35 @@ +# +# Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# + +config ARC_PLAT_AXS10X + bool "Synopsys ARC AXS10x Software Development Platforms" + select DW_APB_ICTL + select GPIO_DWAPB + select OF_GPIO + select GENERIC_IRQ_CHIP + select ARCH_REQUIRE_GPIOLIB + help + Support for the ARC AXS10x Software Development Platforms. + + The AXS10x Platforms consist of a mainboard with peripherals, + on which several daughter cards can be placed. The daughter cards + typically contain a CPU and memory. + +if ARC_PLAT_AXS10X + +config AXS101 + bool "AXS101 with AXC001 CPU Card (ARC 770D/EM6/AS221)" + help + This adds support for the 770D/EM6/AS221 CPU Card. Only the ARC + 770D is supported in Linux. + + The AXS101 Platform consists of an AXS10x mainboard with + this daughtercard. Please use the axs101.dts device tree + with this configuration. + +endif diff --git a/arch/arc/plat-axs10x/Makefile b/arch/arc/plat-axs10x/Makefile new file mode 100644 index 000000000000..d4748f27f86e --- /dev/null +++ b/arch/arc/plat-axs10x/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# + +obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x.o diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c new file mode 100644 index 000000000000..2e7686d1382f --- /dev/null +++ b/arch/arc/plat-axs10x/axs10x.c @@ -0,0 +1,298 @@ +/* + * AXS101 Software Development Platform + * + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#define AXS_MB_CGU 0xE0010000 +#define AXS_MB_CREG 0xE0011000 + +#define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214) +#define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220) +#define CREG_MB_VER (AXS_MB_CREG + 0x230) +#define CREG_MB_CONFIG (AXS_MB_CREG + 0x234) + +#define AXC001_CREG 0xF0001000 +#define AXC001_GPIO_INTC 0xF0003000 + +#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20) +#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60) +#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34) +#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74) + +#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114) +#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120) + +static void enable_gpio_intc_wire(void) +{ + /* + * Peripherals on CPU Card and Mother Board are wired to cpu intc via + * intermediate DW APB GPIO blocks (mainly for debouncing) + * + * --------------------- + * | snps,arc700-intc | + * --------------------- + * | #7 | #15 + * ------------------- ------------------- + * | snps,dw-apb-gpio | | snps,dw-apb-gpio | + * ------------------- ------------------- + * | | + * | [ Debug UART on cpu card ] + * | + * ------------------------ + * | snps,dw-apb-intc (MB)| + * ------------------------ + * | | | | + * [eth] [uart] [... other perip on Main Board] + * + * Current implementation of "irq-dw-apb-ictl" driver doesn't work well + * with stacked INTCs. In particular problem happens if its master INTC + * not yet instantiated. See discussion here - + * https://lkml.org/lkml/2015/3/4/755 + * + * So setup the first gpio block as a passive pass thru and hide it from + * DT hardware topology - connect MB intc directly to cpu intc + * The GPIO "wire" needs to be init nevertheless (here) + * + * One side adv is that peripheral interrupt handling avoids one nested + * intc ISR hop + */ +#define GPIO_INTEN (AXC001_GPIO_INTC + 0x30) +#define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34) +#define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38) +#define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c) +#define MB_TO_GPIO_IRQ 12 + + iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK); + iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL); + iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY); + iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN); +} + +static void axs10x_print_board_ver(unsigned int creg, const char *str) +{ + union ver { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:11, y:12, m:4, d:5; +#else + unsigned int d:5, m:4, y:12, pad:11; +#endif + }; + unsigned int val; + } board; + + board.val = ioread32((void __iomem *)creg); + pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m, + board.y); +} + +static void axs10x_early_init(void) +{ + int mb_rev; + char mb[32]; + + /* Determine motherboard version */ + if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28)) + mb_rev = 3; /* HT-3 (rev3.0) */ + else + mb_rev = 2; /* HT-2 (rev2.0) */ + + enable_gpio_intc_wire(); + + scnprintf(mb, 32, "MainBoard v%d", mb_rev); + axs10x_print_board_ver(CREG_MB_VER, mb); +} + +/* + * Set up System Memory Map for ARC cpu / peripherals controllers + * + * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each + * of which maps to a corresponding 256MB aperture in Target slave memory map. + * + * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0 + * (0x0000_0000) of DDR Port 0 (slave #1) + * + * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel: + * which has master/slaves on both ends. + * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14 + * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to + * MB AXI Tunnel Master, which also has a mem map setup + * + * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup + * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master + */ +struct aperture { + unsigned int slave_sel:4, slave_off:4, pad:24; +}; + +/* CPU Card target slaves */ +#define AXC001_SLV_NONE 0 +#define AXC001_SLV_DDR_PORT0 1 +#define AXC001_SLV_SRAM 2 +#define AXC001_SLV_AXI_TUNNEL 3 +#define AXC001_SLV_AXI2APB 6 +#define AXC001_SLV_DDR_PORT1 7 + +/* MB AXI Target slaves */ +#define AXS_MB_SLV_NONE 0 +#define AXS_MB_SLV_AXI_TUNNEL_CPU 1 +#define AXS_MB_SLV_AXI_TUNNEL_HAPS 2 +#define AXS_MB_SLV_SRAM 3 +#define AXS_MB_SLV_CONTROL 4 + +/* MB AXI masters */ +#define AXS_MB_MST_TUNNEL_CPU 0 +#define AXS_MB_MST_USB_OHCI 10 + +/* + * memmap for ARC core on CPU Card + */ +static const struct aperture axc001_memmap[16] = { + {AXC001_SLV_AXI_TUNNEL, 0x0}, + {AXC001_SLV_AXI_TUNNEL, 0x1}, + {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */ + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */ + {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */ + {AXC001_SLV_DDR_PORT1, 0x0}, + {AXC001_SLV_DDR_PORT1, 0x1}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_AXI_TUNNEL, 0xD}, + {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */ + {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */ +}; + +/* + * memmap for CPU Card AXI Tunnel Master (for access by MB controllers) + * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR + */ +static const struct aperture axc001_axi_tunnel_memmap[16] = { + {AXC001_SLV_AXI_TUNNEL, 0x0}, + {AXC001_SLV_AXI_TUNNEL, 0x1}, + {AXC001_SLV_SRAM, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_DDR_PORT0, 0x0}, + {AXC001_SLV_DDR_PORT0, 0x1}, + {AXC001_SLV_DDR_PORT1, 0x0}, + {AXC001_SLV_DDR_PORT1, 0x1}, + {AXC001_SLV_NONE, 0x0}, + {AXC001_SLV_AXI_TUNNEL, 0xD}, + {AXC001_SLV_AXI_TUNNEL, 0xE}, + {AXC001_SLV_AXI2APB, 0x0}, +}; + +/* + * memmap for MB AXI Masters + * Same mem map for all perip controllers as well as MB AXI Tunnel Master + */ +static const struct aperture axs_mb_memmap[16] = { + {AXS_MB_SLV_SRAM, 0x0}, + {AXS_MB_SLV_SRAM, 0x0}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */ + {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */ + {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA}, + {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB}, + {AXS_MB_SLV_NONE, 0x0}, + {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD}, + {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */ + {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF}, +}; + +static noinline void +axs101_set_memmap(void __iomem *base, const struct aperture map[16]) +{ + unsigned int slave_select, slave_offset; + int i; + + slave_select = slave_offset = 0; + for (i = 0; i < 8; i++) { + slave_select |= map[i].slave_sel << (i << 2); + slave_offset |= map[i].slave_off << (i << 2); + } + + iowrite32(slave_select, base + 0x0); /* SLV0 */ + iowrite32(slave_offset, base + 0x8); /* OFFSET0 */ + + slave_select = slave_offset = 0; + for (i = 0; i < 8; i++) { + slave_select |= map[i+8].slave_sel << (i << 2); + slave_offset |= map[i+8].slave_off << (i << 2); + } + + iowrite32(slave_select, base + 0x4); /* SLV1 */ + iowrite32(slave_offset, base + 0xC); /* OFFSET1 */ +} + +static void axs101_early_init(void) +{ + int i; + + /* ARC 770D memory view */ + axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap); + iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD); + + /* AXI tunnel memory map (incoming traffic from MB into CPU Card */ + axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN, + axc001_axi_tunnel_memmap); + iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD); + + /* MB peripherals memory map */ + for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++) + axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4), + axs_mb_memmap); + + iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */ + + /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */ + iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); + + /* Set up the MB interrupt system: mux interrupts to GPIO7) */ + iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); + + /* reset ethernet and ULPI interfaces */ + iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET); + + /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */ + iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX); + + axs10x_early_init(); +} + +static const char *axs101_compat[] __initconst = { + "snps,axs101", + NULL, +}; + +MACHINE_START(AXS101, "axs101") + .dt_compat = axs101_compat, + .init_early = axs101_early_init, +MACHINE_END -- cgit v1.2.3 From 8d0d56ba24d8d0b04bc9d9a7fbd1796d8966159f Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 2 Feb 2015 19:23:21 +0530 Subject: ARC: [axs101] support early 8250 uart Earlycon calculates UART clock as "BASE_BAUD * 16". In case of ARC "BASE_BAUD" is calculated dynamically in runtime, basically it is an alias to arc_early_base_baud(), which in turn just does "arc_base_baud/16". 8250 UART on AXS/SDP board uses 33.3MHz clock source which is set in "arc_base_baud" with this change. Additional compatibility string "snps,arc-sdp" is introduced as well because there're different flavours of AXS boards but they all share the same motherboard and so it's possible to re-use the same code for motherbord even if CPU daughterboard changes. Signed-off-by: Vineet Gupta --- Documentation/devicetree/bindings/arc/axs101.txt | 2 +- arch/arc/boot/dts/axs101.dts | 4 ++-- arch/arc/kernel/devtree.c | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arc/axs101.txt b/Documentation/devicetree/bindings/arc/axs101.txt index 568aa5f74de2..48290d5178b5 100644 --- a/Documentation/devicetree/bindings/arc/axs101.txt +++ b/Documentation/devicetree/bindings/arc/axs101.txt @@ -4,4 +4,4 @@ Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon Required root node properties: - - compatible = "snps,axs101"; + - compatible = "snps,axs101", "snps,arc-sdp"; diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts index 6c3391da0e3b..3f9b0582e734 100644 --- a/arch/arc/boot/dts/axs101.dts +++ b/arch/arc/boot/dts/axs101.dts @@ -13,9 +13,9 @@ /include/ "axs10x_mb.dtsi" / { - compatible = "snps,axs101"; + compatible = "snps,axs101", "snps,arc-sdp"; chosen { - bootargs = "console=tty0 console=ttyS3,115200n8 consoleblank=0"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; }; }; diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c index e32b54abff51..f801d46dc087 100644 --- a/arch/arc/kernel/devtree.c +++ b/arch/arc/kernel/devtree.c @@ -32,6 +32,8 @@ static void __init arc_set_early_base_baud(unsigned long dt_root) if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x")) arc_base_baud = core_clk/3; + else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp")) + arc_base_baud = 33333333; /* Fixed 33MHz clk */ else arc_base_baud = core_clk; } -- cgit v1.2.3 From c49bb94c8430a5697c59fba7a4d876990545d20b Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 17 Jun 2015 15:22:51 +0200 Subject: clk: at91: trivial: typo in peripheral clock description Signed-off-by: Nicolas Ferre Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/clock/at91-clock.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index 7a4d4926f44e..5ba6450693b9 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -248,7 +248,7 @@ Required properties for peripheral clocks: - #address-cells : shall be 1 (reg is used to encode clk id). - clocks : shall be the master clock phandle. e.g. clocks = <&mck>; -- name: device tree node describing a specific system clock. +- name: device tree node describing a specific peripheral clock. * #clock-cells : from common clock binding; shall be set to 0. * reg: peripheral id. See Atmel's datasheets to get a full list of peripheral ids. -- cgit v1.2.3 From 1c075486852920241ace0f8087498c3ef6522fb2 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 18 Jun 2015 15:46:17 +0200 Subject: crypto: mv_cesa - document the clocks property On Dove platforms, the crypto engine requires a clock. Document this clocks property in the mv_cesa bindings doc. Signed-off-by: Boris Brezillon Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/mv_cesa.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt index 47229b1a594b..eaa2873e7b25 100644 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt @@ -7,6 +7,8 @@ Required properties: length - reg-names : "regs" , "sram"; - interrupts : interrupt number +- clocks: reference to the crypto engines clocks. This property is only + required for Dove platforms Examples: -- cgit v1.2.3 From 51b44fc81178136bca88565dad07c067c8dc51da Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 18 Jun 2015 15:46:18 +0200 Subject: crypto: mv_cesa - use gen_pool to reserve the SRAM memory region The mv_cesa driver currently expects the SRAM memory region to be passed as a platform device resource. This approach implies two drawbacks: - the DT representation is wrong - the only one that can access the SRAM is the crypto engine The last point is particularly annoying in some cases: for example on armada 370, a small region of the crypto SRAM is used to implement the cpuidle, which means you would not be able to enable both cpuidle and the CESA driver. To address that problem, we explicitly define the SRAM device in the DT and then reference the sram node from the crypto engine node. Also note that the old way of retrieving the SRAM memory region is still supported, or in other words, backward compatibility is preserved. Signed-off-by: Boris Brezillon Signed-off-by: Herbert Xu --- .../devicetree/bindings/crypto/mv_cesa.txt | 24 ++++++--- drivers/crypto/Kconfig | 1 + drivers/crypto/mv_cesa.c | 58 ++++++++++++++++------ 3 files changed, 60 insertions(+), 23 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt index eaa2873e7b25..13b8fc5ddcf2 100644 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt @@ -2,21 +2,29 @@ Marvell Cryptographic Engines And Security Accelerator Required properties: - compatible : should be "marvell,orion-crypto" -- reg : base physical address of the engine and length of memory mapped - region, followed by base physical address of sram and its memory - length -- reg-names : "regs" , "sram"; -- interrupts : interrupt number +- reg: base physical address of the engine and length of memory mapped + region. Can also contain an entry for the SRAM attached to the CESA, + but this representation is deprecated and marvell,crypto-srams should + be used instead +- reg-names: "regs". Can contain an "sram" entry, but this representation + is deprecated and marvell,crypto-srams should be used instead +- interrupts: interrupt number - clocks: reference to the crypto engines clocks. This property is only required for Dove platforms +- marvell,crypto-srams: phandle to crypto SRAM definitions + +Optional properties: +- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not + specified the whole SRAM is used (2KB) Examples: crypto@30000 { compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0x4000000 0x800>; - reg-names = "regs" , "sram"; + reg = <0x30000 0x10000>; + reg-names = "regs"; interrupts = <22>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x600>; status = "okay"; }; diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 7a72797f6f58..31e7b7ce5990 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -165,6 +165,7 @@ config CRYPTO_DEV_MV_CESA select CRYPTO_AES select CRYPTO_BLKCIPHER select CRYPTO_HASH + select SRAM help This driver allows you to utilize the Cryptographic Engines and Security Accelerator (CESA) which can be found on the Marvell Orion diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c index eb645c2cf3eb..e31d82c1eebe 100644 --- a/drivers/crypto/mv_cesa.c +++ b/drivers/crypto/mv_cesa.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,8 @@ #define MAX_HW_HASH_SIZE 0xFFFF #define MV_CESA_EXPIRE 500 /* msec */ +#define MV_CESA_DEFAULT_SRAM_SIZE 2048 + /* * STM: * /---------------------------------------\ @@ -83,6 +86,8 @@ struct req_progress { struct crypto_priv { void __iomem *reg; void __iomem *sram; + struct gen_pool *sram_pool; + dma_addr_t sram_dma; int irq; struct clk *clk; struct task_struct *queue_th; @@ -1019,6 +1024,39 @@ static struct ahash_alg mv_hmac_sha1_alg = { } }; +static int mv_cesa_get_sram(struct platform_device *pdev, + struct crypto_priv *cp) +{ + struct resource *res; + u32 sram_size = MV_CESA_DEFAULT_SRAM_SIZE; + + of_property_read_u32(pdev->dev.of_node, "marvell,crypto-sram-size", + &sram_size); + + cp->sram_size = sram_size; + cp->sram_pool = of_get_named_gen_pool(&pdev->dev.of_node, + "marvell,crypto-srams", 0); + if (cp->sram_pool) { + cp->sram = gen_pool_dma_alloc(cp->sram_pool, sram_size, + &cp->sram_dma); + if (cp->sram) + return 0; + + return -ENOMEM; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "sram"); + if (!res || resource_size(res) < cp->sram_size) + return -EINVAL; + + cp->sram = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(cp->sram)) + return PTR_ERR(cp->sram); + + return 0; +} + static int mv_probe(struct platform_device *pdev) { struct crypto_priv *cp; @@ -1047,18 +1085,11 @@ static int mv_probe(struct platform_device *pdev) goto err; } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); - if (!res) { - ret = -ENXIO; + ret = mv_cesa_get_sram(pdev, cp); + if (ret) goto err; - } - cp->sram_size = resource_size(res); + cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE; - cp->sram = ioremap(res->start, cp->sram_size); - if (!cp->sram) { - ret = -ENOMEM; - goto err; - } if (pdev->dev.of_node) irq = irq_of_parse_and_map(pdev->dev.of_node, 0); @@ -1066,7 +1097,7 @@ static int mv_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0 || irq == NO_IRQ) { ret = irq; - goto err_unmap_sram; + goto err; } cp->irq = irq; @@ -1076,7 +1107,7 @@ static int mv_probe(struct platform_device *pdev) cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto"); if (IS_ERR(cp->queue_th)) { ret = PTR_ERR(cp->queue_th); - goto err_unmap_sram; + goto err; } ret = request_irq(irq, crypto_int, 0, dev_name(&pdev->dev), @@ -1134,8 +1165,6 @@ err_irq: } err_thread: kthread_stop(cp->queue_th); -err_unmap_sram: - iounmap(cp->sram); err: kfree(cp); cpg = NULL; @@ -1155,7 +1184,6 @@ static int mv_remove(struct platform_device *pdev) kthread_stop(cp->queue_th); free_irq(cp->irq, cp); memset(cp->sram, 0, cp->sram_size); - iounmap(cp->sram); if (!IS_ERR(cp->clk)) { clk_disable_unprepare(cp->clk); -- cgit v1.2.3 From 1fa2e9ae1d3782bd8f737487dc6306ba16b4d016 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 18 Jun 2015 15:46:19 +0200 Subject: crypto: mv_cesa - explicitly define kirkwood and dove compatible strings We are about to add a new driver to support new features like using the TDMA engine to offload the CPU. Orion, Dove and Kirkwood platforms are already using the mv_cesa driver, but Orion SoCs do not embed the TDMA engine, which means we will have to differentiate them if we want to get TDMA support on Dove and Kirkwood. In the other hand, the migration from the old driver to the new one is not something all people are willing to do without first auditing the new driver. Hence we have to support the new compatible in the mv_cesa driver so that new platforms with updated DTs can still attach their crypto engine device to this driver. Signed-off-by: Boris Brezillon Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/mv_cesa.txt | 5 ++++- drivers/crypto/mv_cesa.c | 4 +++- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt index 13b8fc5ddcf2..c0c35f00335b 100644 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt @@ -1,7 +1,10 @@ Marvell Cryptographic Engines And Security Accelerator Required properties: -- compatible : should be "marvell,orion-crypto" +- compatible: should be one of the following string + "marvell,orion-crypto" + "marvell,kirkwood-crypto" + "marvell,dove-crypto" - reg: base physical address of the engine and length of memory mapped region. Can also contain an entry for the SRAM attached to the CESA, but this representation is deprecated and marvell,crypto-srams should diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c index e31d82c1eebe..5bcd575fa96f 100644 --- a/drivers/crypto/mv_cesa.c +++ b/drivers/crypto/mv_cesa.c @@ -1034,7 +1034,7 @@ static int mv_cesa_get_sram(struct platform_device *pdev, &sram_size); cp->sram_size = sram_size; - cp->sram_pool = of_get_named_gen_pool(&pdev->dev.of_node, + cp->sram_pool = of_get_named_gen_pool(pdev->dev.of_node, "marvell,crypto-srams", 0); if (cp->sram_pool) { cp->sram = gen_pool_dma_alloc(cp->sram_pool, sram_size, @@ -1197,6 +1197,8 @@ static int mv_remove(struct platform_device *pdev) static const struct of_device_id mv_cesa_of_match_table[] = { { .compatible = "marvell,orion-crypto", }, + { .compatible = "marvell,kirkwood-crypto", }, + { .compatible = "marvell,dove-crypto", }, {} }; MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table); -- cgit v1.2.3 From 2df6bb5d8b22bc06a6ea83e8b2a6bcf3bb445304 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 18 Jun 2015 15:46:30 +0200 Subject: crypto: marvell/cesa - add DT bindings documentation Add DT bindings documentation for the new marvell-cesa driver. Signed-off-by: Boris Brezillon Signed-off-by: Herbert Xu --- .../devicetree/bindings/crypto/marvell-cesa.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/marvell-cesa.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/crypto/marvell-cesa.txt b/Documentation/devicetree/bindings/crypto/marvell-cesa.txt new file mode 100644 index 000000000000..c6c6a4a045bd --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/marvell-cesa.txt @@ -0,0 +1,45 @@ +Marvell Cryptographic Engines And Security Accelerator + +Required properties: +- compatible: should be one of the following string + "marvell,orion-crypto" + "marvell,kirkwood-crypto" + "marvell,dove-crypto" + "marvell,armada-370-crypto" + "marvell,armada-xp-crypto" + "marvell,armada-375-crypto" + "marvell,armada-38x-crypto" +- reg: base physical address of the engine and length of memory mapped + region. Can also contain an entry for the SRAM attached to the CESA, + but this representation is deprecated and marvell,crypto-srams should + be used instead +- reg-names: "regs". Can contain an "sram" entry, but this representation + is deprecated and marvell,crypto-srams should be used instead +- interrupts: interrupt number +- clocks: reference to the crypto engines clocks. This property is not + required for orion and kirkwood platforms +- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine + id. + This property is not required for the orion and kirkwoord + platforms. + "cesazX" clocks are not required on armada-370 platforms +- marvell,crypto-srams: phandle to crypto SRAM definitions + +Optional properties: +- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not + specified the whole SRAM is used (2KB) + + +Examples: + + crypto@90000 { + compatible = "marvell,armada-xp-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <48>, <49>; + clocks = <&gateclk 23>, <&gateclk 23>; + clock-names = "cesa0", "cesa1"; + marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; + marvell,crypto-sram-size = <0x600>; + status = "okay"; + }; -- cgit v1.2.3 From f289cc7bf9a2216785a9e22fd38e2543628b011c Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:11 +0100 Subject: devicetree/bindings: add Ingenic Semiconductor vendor prefix Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based SoCs. Simply use 'ingenic'. Signed-off-by: Paul Burton Acked-by: Rob Herring Cc: Lars-Peter Clausen Cc: Ian Campbell Cc: Kumar Gala Cc: Mark Rutland Cc: Pawel Moll Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Arnd Bergmann Cc: Hayato Suzuki Cc: Thierry Reding Cc: linux-kernel@vger.kernel.org Cc: Philipp Zabel Cc: Kuninori Morimoto Cc: Arnaud Ebalard Cc: Dmitry Torokhov Cc: Antony Pavlov Patchwork: https://patchwork.linux-mips.org/patch/10129/ Signed-off-by: Ralf Baechle --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..b335a99c7e05 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -100,6 +100,7 @@ ibm International Business Machines (IBM) idt Integrated Device Technologies, Inc. iom Iomega Corporation img Imagination Technologies Ltd. +ingenic Ingenic Semiconductor innolux Innolux Corporation intel Intel Corporation intercontrol Inter Control Group -- cgit v1.2.3 From 2d06fe53e76a096af06a964c7893a7b14248961c Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:12 +0100 Subject: devicetree/bindings: add Qi Hardware vendor prefix Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote (qi_lb60) among other open devices. Signed-off-by: Paul Burton Acked-by: Rob Herring Cc: Lars-Peter Clausen Cc: Ian Campbell Cc: Kumar Gala Cc: Mark Rutland Cc: Pawel Moll Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Arnd Bergmann Cc: Hayato Suzuki Cc: Thierry Reding Cc: linux-kernel@vger.kernel.org Cc: Philipp Zabel Cc: Kuninori Morimoto Cc: Arnaud Ebalard Cc: Dmitry Torokhov Cc: Antony Pavlov Patchwork: https://patchwork.linux-mips.org/patch/10142/ Signed-off-by: Ralf Baechle --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b335a99c7e05..c4ba705916c0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -155,6 +155,7 @@ powervr PowerVR (deprecated, use img) qca Qualcomm Atheros, Inc. qcom Qualcomm Technologies, Inc qemu QEMU, a generic and open source machine emulator and virtualizer +qi Qi Hardware qnap QNAP Systems, Inc. radxa Radxa raidsonic RaidSonic Technology GmbH -- cgit v1.2.3 From 5f408ebfd2f3fa791449c0d641254f795747c081 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:20 +0100 Subject: devicetree: document Ingenic SoC interrupt controller binding Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton Acked-by: Rob Herring Cc: Ian Campbell Cc: Jason Cooper Cc: Kumar Gala Cc: Lars-Peter Clausen Cc: Mark Rutland Cc: Pawel Moll Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10134/ Signed-off-by: Ralf Baechle --- .../bindings/interrupt-controller/ingenic,intc.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt new file mode 100644 index 000000000000..5f89fb635a1b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt @@ -0,0 +1,28 @@ +Ingenic SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,-intc". Valid strings are: + ingenic,jz4740-intc + ingenic,jz4770-intc + ingenic,jz4775-intc + ingenic,jz4780-intc +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + +intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +}; -- cgit v1.2.3 From fe4ef45b5b40c496aa0c85d059c713c79b804e06 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:34 +0100 Subject: DEVICETREE: Add Ingenic CGU binding documentation Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 & JZ4780 CGU blocks. Signed-off-by: Paul Burton Cc: Ian Campbell Cc: Kumar Gala Cc: Lars-Peter Clausen Cc: Mark Rutland Cc: Mike Turquette Cc: Pawel Moll Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10152/ Signed-off-by: Ralf Baechle --- .../devicetree/bindings/clock/ingenic,cgu.txt | 53 +++++++++++++ include/dt-bindings/clock/jz4740-cgu.h | 37 +++++++++ include/dt-bindings/clock/jz4780-cgu.h | 88 ++++++++++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ingenic,cgu.txt create mode 100644 include/dt-bindings/clock/jz4740-cgu.h create mode 100644 include/dt-bindings/clock/jz4780-cgu.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt new file mode 100644 index 000000000000..f8d4134ae409 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt @@ -0,0 +1,53 @@ +Ingenic SoC CGU binding + +The CGU in an Ingenic SoC provides all the clocks generated on-chip. It +typically includes a variety of PLLs, multiplexers, dividers & gates in order +to provide many different clock signals derived from only 2 external source +clocks. + +Required properties: +- compatible : Should be "ingenic,-cgu". + For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu". +- reg : The address & length of the CGU registers. +- clocks : List of phandle & clock specifiers for clocks external to the CGU. + Two such external clocks should be specified - first the external crystal + "ext" and second the RTC clock source "rtc". +- clock-names : List of name strings for the external clocks. +- #clock-cells: Should be 1. + Clock consumers specify this argument to identify a clock. The valid values + may be found in -cgu.h>. + +Example SoC include file: + +/ { + cgu: jz4740-cgu { + compatible = "ingenic,jz4740-cgu"; + reg = <0x10000000 0x100>; + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + clocks = <&cgu JZ4740_CLK_UART0>; + }; +}; + +Example board file: + +/ { + ext: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + rtc: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + &cgu { + clocks = <&ext> <&rtc>; + clock-names: "ext", "rtc"; + }; +}; diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h new file mode 100644 index 000000000000..43153d3e9bd2 --- /dev/null +++ b/include/dt-bindings/clock/jz4740-cgu.h @@ -0,0 +1,37 @@ +/* + * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4740 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ + +#define JZ4740_CLK_EXT 0 +#define JZ4740_CLK_RTC 1 +#define JZ4740_CLK_PLL 2 +#define JZ4740_CLK_PLL_HALF 3 +#define JZ4740_CLK_CCLK 4 +#define JZ4740_CLK_HCLK 5 +#define JZ4740_CLK_PCLK 6 +#define JZ4740_CLK_MCLK 7 +#define JZ4740_CLK_LCD 8 +#define JZ4740_CLK_LCD_PCLK 9 +#define JZ4740_CLK_I2S 10 +#define JZ4740_CLK_SPI 11 +#define JZ4740_CLK_MMC 12 +#define JZ4740_CLK_UHC 13 +#define JZ4740_CLK_UDC 14 +#define JZ4740_CLK_UART0 15 +#define JZ4740_CLK_UART1 16 +#define JZ4740_CLK_DMA 17 +#define JZ4740_CLK_IPU 18 +#define JZ4740_CLK_ADC 19 +#define JZ4740_CLK_I2C 20 +#define JZ4740_CLK_AIC 21 + +#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h new file mode 100644 index 000000000000..467165e3cfee --- /dev/null +++ b/include/dt-bindings/clock/jz4780-cgu.h @@ -0,0 +1,88 @@ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ -- cgit v1.2.3 From 98fd25e7eaa65e2365b8a883d6a572657f9a80e1 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:43 +0100 Subject: devicetree: document Ingenic SoC UART binding Add binding documentation for the UARTs found in Ingenic SoCs. Signed-off-by: Paul Burton Acked-by: Rob Herring Cc: Ian Campbell Cc: Kumar Gala Cc: Lars-Peter Clausen Cc: Mark Rutland Cc: Pawel Moll Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10161/ Signed-off-by: Ralf Baechle --- .../devicetree/bindings/serial/ingenic,uart.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt b/Documentation/devicetree/bindings/serial/ingenic,uart.txt new file mode 100644 index 000000000000..c2d3b3abe7d9 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt @@ -0,0 +1,22 @@ +* Ingenic SoC UART + +Required properties: +- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart" +- reg : offset and length of the register set for the device. +- interrupts : should contain uart interrupt. +- clocks : phandles to the module & baud clocks. +- clock-names: tuple listing input clock names. + Required elements: "baud", "module" + +Example: + +uart0: serial@10030000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10030000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <9>; + + clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; + clock-names = "baud", "module"; +}; -- cgit v1.2.3 From 90bc35c5da64d05378b15c26a664a0ecedc984ac Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Tue, 7 Apr 2015 15:04:16 -0700 Subject: phy: Add binding document for Pistachio USB2.0 PHY Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Kishon Vijay Abraham I Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley Cc: Damien Horsley Patchwork: https://patchwork.linux-mips.org/patch/9727/ Signed-off-by: Ralf Baechle --- .../devicetree/bindings/phy/pistachio-usb-phy.txt | 29 ++++++++++++++++++++++ include/dt-bindings/phy/phy-pistachio-usb.h | 16 ++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt create mode 100644 include/dt-bindings/phy/phy-pistachio-usb.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt new file mode 100644 index 000000000000..afbc7e24a3de --- /dev/null +++ b/Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt @@ -0,0 +1,29 @@ +IMG Pistachio USB PHY +===================== + +Required properties: +-------------------- + - compatible: Must be "img,pistachio-usb-phy". + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. + - clocks: Must contain an entry for each entry in clock-names. + See ../clock/clock-bindings.txt for details. + - clock-names: Must include "usb_phy". + - img,cr-top: Must constain a phandle to the CR_TOP syscon node. + - img,refclk: Indicates the reference clock source for the USB PHY. + See for a list of valid values. + +Optional properties: +-------------------- + - phy-supply: USB VBUS supply. Must supply 5.0V. + +Example: +-------- +usb_phy: usb-phy { + compatible = "img,pistachio-usb-phy"; + clocks = <&clk_core CLK_USB_PHY>; + clock-names = "usb_phy"; + phy-supply = <&usb_vbus>; + img,refclk = ; + img,cr-top = <&cr_top>; + #phy-cells = <0>; +}; diff --git a/include/dt-bindings/phy/phy-pistachio-usb.h b/include/dt-bindings/phy/phy-pistachio-usb.h new file mode 100644 index 000000000000..d1877aa0a3f5 --- /dev/null +++ b/include/dt-bindings/phy/phy-pistachio-usb.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_PHY_PISTACHIO +#define _DT_BINDINGS_PHY_PISTACHIO + +#define REFCLK_XO_CRYSTAL 0x0 +#define REFCLK_X0_EXT_CLK 0x1 +#define REFCLK_CLK_CORE 0x2 + +#endif /* _DT_BINDINGS_PHY_PISTACHIO */ -- cgit v1.2.3 From fe41b466f9f4c45b3368dee4a50d7c77ae7f37f9 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 01:52:24 +0200 Subject: DEVICETREE: Add bindings for the SoC of the ATH79 family Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- .../devicetree/bindings/mips/ath79-soc.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ath79-soc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mips/ath79-soc.txt b/Documentation/devicetree/bindings/mips/ath79-soc.txt new file mode 100644 index 000000000000..88a12a43e44e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ath79-soc.txt @@ -0,0 +1,21 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC + +Each device tree must specify a compatible value for the AR SoC +it uses in the compatible property of the root node. The compatible +value must be one of the following values: + +- qca,ar7130 +- qca,ar7141 +- qca,ar7161 +- qca,ar7240 +- qca,ar7241 +- qca,ar7242 +- qca,ar9130 +- qca,ar9132 +- qca,ar9330 +- qca,ar9331 +- qca,ar9341 +- qca,ar9342 +- qca,ar9344 +- qca,qca9556 +- qca,qca9558 -- cgit v1.2.3 From d25b4f65bf7608ba7f59d3f0251ea57e34b74238 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 01:52:26 +0200 Subject: DEVICETREE: Add bindings for the ATH79 DDR controllers The DDR controller of the ARxxx and AR9xxx families provides an interface to flush the FIFO between various devices and the DDR. This is mainly used by the IRQ controller to flush the FIFO before running the interrupt handler of such devices. Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- .../memory-controllers/ath79-ddr-controller.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt new file mode 100644 index 000000000000..efe35a065714 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt @@ -0,0 +1,35 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller + +The DDR controller of the ARxxx and AR9xxx families provides an interface +to flush the FIFO between various devices and the DDR. This is mainly used +by the IRQ controller to flush the FIFO before running the interrupt handler +of such devices. + +Required properties: + +- compatible: has to be "qca,-ddr-controller", + "qca,[ar7100|ar7240]-ddr-controller" as fallback. + On SoC with PCI support "qca,ar7100-ddr-controller" should be used as + fallback, otherwise "qca,ar7240-ddr-controller" should be used. +- reg: Base address and size of the controllers memory area +- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer + channel + +Example: + + ddr_ctrl: memory-controller@18000000 { + compatible = "qca,ar9132-ddr-controller", + "qca,ar7240-ddr-controller"; + reg = <0x18000000 0x100>; + + #qca,ddr-wb-channel-cells = <1>; + }; + + ... + + interrupt-controller { + ... + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; -- cgit v1.2.3 From 0fa4af8f53d0d2149b75d1e00a395c63922495fb Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 01:52:27 +0200 Subject: DEVICETREE: Add bindings for the ATH79 interrupt controllers Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- .../interrupt-controller/qca,ath79-cpu-intc.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt new file mode 100644 index 000000000000..aabce7810d29 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt @@ -0,0 +1,44 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller + +On most SoC the IRQ controller need to flush the DDR FIFO before running +the interrupt handler of some devices. This is configured using the +qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. + +Required Properties: + +- compatible: has to be "qca,-cpu-intc", "qca,ar7100-cpu-intc" + as fallback +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 1 for intc + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Optional Properties: + +- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write + buffer flush +- qca,ddr-wb-channels: List of phandles to the write buffer channels for + each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt + default to the entry's index. + +Example: + + interrupt-controller { + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; + + ... + + ddr_ctrl: memory-controller@18000000 { + ... + #qca,ddr-wb-channel-cells = <1>; + }; -- cgit v1.2.3 From bb35586fd07447515deaa774c0aa07cdfa4d4743 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 01:52:28 +0200 Subject: DEVICETREE: Add bindings for the ATH79 MISC interrupt controllers Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- .../interrupt-controller/qca,ath79-misc-intc.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt new file mode 100644 index 000000000000..391717a68f3b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt @@ -0,0 +1,30 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller + +The MISC interrupt controller is a secondary controller for lower priority +interrupt. + +Required Properties: +- compatible: has to be "qca,-cpu-intc", "qca,ar7100-misc-intc" + as fallback +- reg: Base address and size of the controllers memory area +- interrupt-parent: phandle of the parent interrupt controller. +- interrupts: Interrupt specifier for the controllers interrupt. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 1 + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Example: + + interrupt-controller@18060010 { + compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + }; -- cgit v1.2.3 From 44fad3323833624941b99dafd982978e1742dd53 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 01:52:30 +0200 Subject: DEVICETREE: Add bindings for the ATH79 PLL controllers Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- .../devicetree/bindings/clock/qca,ath79-pll.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt new file mode 100644 index 000000000000..e0fc2c11dd00 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt @@ -0,0 +1,33 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller + +The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. + +Required Properties: +- compatible: has to be "qca,-cpu-intc" and one of the following + fallbacks: + - "qca,ar7100-pll" + - "qca,ar7240-pll" + - "qca,ar9130-pll" + - "qca,ar9330-pll" + - "qca,ar9340-pll" + - "qca,qca9550-pll" +- reg: Base address and size of the controllers memory area +- clock-names: Name of the input clock, has to be "ref" +- clocks: phandle of the external reference clock +- #clock-cells: has to be one + +Optional properties: +- clock-output-names: should be "cpu", "ddr", "ahb" + +Example: + + memory-controller@18050000 { + compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; + reg = <0x18050000 0x20>; + + clock-names = "ref"; + clocks = <&extosc>; + + #clock-cells = <1>; + clock-output-names = "cpu", "ddr", "ahb"; + }; -- cgit v1.2.3 From d6743a496cfdd84375c7798cfc3dd0e1aeb4ca6d Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 02:18:23 +0200 Subject: DEVICETREE: Add bindings for the ATH79 GPIO controllers These bindings support the GPIO controllers found on the Qualcomm Atheros AR7xxx/AR9XXX SoC. Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- .../devicetree/bindings/gpio/gpio-ath79.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ath79.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpio/gpio-ath79.txt b/Documentation/devicetree/bindings/gpio/gpio-ath79.txt new file mode 100644 index 000000000000..c522851017ae --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-ath79.txt @@ -0,0 +1,38 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller + +Required properties: +- compatible: has to be "qca,-gpio" and one of the following + fallbacks: + - "qca,ar7100-gpio" + - "qca,ar9340-gpio" +- reg: Base address and size of the controllers memory area +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters. +- ngpios: Should be set to the number of GPIOs available on the SoC. + +Optional properties: +- interrupt-parent: phandle of the parent interrupt controller. +- interrupts: Interrupt specifier for the controllers interrupt. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 2 + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Example: + + gpio@18040000 { + compatible = "qca,ar9132-gpio", "qca,ar7100-gpio"; + reg = <0x18040000 0x30>; + interrupts = <2>; + + ngpios = <22>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; -- cgit v1.2.3 From 9db8e9bc047beecf4a33fad22964419f10332fcb Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Sun, 31 May 2015 02:18:25 +0200 Subject: OF: Add vendor prefix for TP-Link Technologies Co. Ltd Signed-off-by: Alban Bedel Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index c4ba705916c0..8270e9db8fcd 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -197,6 +197,7 @@ tlm Trusted Logic Mobility toradex Toradex AG toshiba Toshiba Corporation toumaz Toumaz +tplink TP-LINK Technologies Co., Ltd. truly Truly Semiconductors Limited usi Universal Scientific Industrial Co., Ltd. v3 V3 Semiconductor -- cgit v1.2.3 From 761c1770f2bf36a323ab97e2e1780db4f9b8a6fe Mon Sep 17 00:00:00 2001 From: "Maciej S. Szmigiero" Date: Sun, 21 Jun 2015 15:54:44 +0200 Subject: hwmon: add driver for Microchip TC74 Add hwmon driver for the Microchip TC74. The TC74 is a single-input 8-bit I2C temperature sensor, with +-2 degrees centigrade accuracy. Signed-off-by: Maciej Szmigiero Signed-off-by: Guenter Roeck --- Documentation/hwmon/tc74 | 20 ++++++ drivers/hwmon/Kconfig | 10 +++ drivers/hwmon/Makefile | 1 + drivers/hwmon/tc74.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 208 insertions(+) create mode 100644 Documentation/hwmon/tc74 create mode 100644 drivers/hwmon/tc74.c (limited to 'Documentation') diff --git a/Documentation/hwmon/tc74 b/Documentation/hwmon/tc74 new file mode 100644 index 000000000000..43027aad5f8e --- /dev/null +++ b/Documentation/hwmon/tc74 @@ -0,0 +1,20 @@ +Kernel driver tc74 +==================== + +Supported chips: + * Microchip TC74 + Prefix: 'tc74' + Datasheet: Publicly available at Microchip website. + +Description +----------- + +Driver supports the above part. + +The tc74 has an 8-bit sensor, with 1 degree centigrade resolution +and +- 2 degrees centigrade accuracy. + +Notes +----- + +Currently entering low power standby mode is not supported. diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 9c9d38b1e92e..54075a07d2a1 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1452,6 +1452,16 @@ config SENSORS_INA2XX This driver can also be built as a module. If so, the module will be called ina2xx. +config SENSORS_TC74 + tristate "Microchip TC74" + depends on I2C + help + If you say yes here you get support for Microchip TC74 single + input temperature sensor chips. + + This driver can also be built as a module. If so, the module + will be called tc74. + config SENSORS_THMC50 tristate "Texas Instruments THMC50 / Analog Devices ADM1022" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index b4a40f17e2aa..ab904027f074 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -140,6 +140,7 @@ obj-$(CONFIG_SENSORS_SMSC47B397)+= smsc47b397.o obj-$(CONFIG_SENSORS_SMSC47M1) += smsc47m1.o obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o obj-$(CONFIG_SENSORS_AMC6821) += amc6821.o +obj-$(CONFIG_SENSORS_TC74) += tc74.o obj-$(CONFIG_SENSORS_THMC50) += thmc50.o obj-$(CONFIG_SENSORS_TMP102) += tmp102.o obj-$(CONFIG_SENSORS_TMP103) += tmp103.o diff --git a/drivers/hwmon/tc74.c b/drivers/hwmon/tc74.c new file mode 100644 index 000000000000..d95165158800 --- /dev/null +++ b/drivers/hwmon/tc74.c @@ -0,0 +1,177 @@ +/* + * An hwmon driver for the Microchip TC74 + * + * Copyright 2015 Maciej Szmigiero + * + * Based on ad7414.c: + * Copyright 2006 Stefan Roese, DENX Software Engineering + * Copyright 2008 Sean MacLennan, PIKA Technologies + * Copyright 2008 Frank Edelhaeuser, Spansion Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TC74 registers */ +#define TC74_REG_TEMP 0x00 +#define TC74_REG_CONFIG 0x01 + +struct tc74_data { + struct i2c_client *client; + struct mutex lock; /* atomic read data updates */ + bool valid; /* validity of fields below */ + unsigned long next_update; /* In jiffies */ + s8 temp_input; /* Temp value in dC */ +}; + +static int tc74_update_device(struct device *dev) +{ + struct tc74_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + int ret; + + ret = mutex_lock_interruptible(&data->lock); + if (ret) + return ret; + + if (time_after(jiffies, data->next_update) || !data->valid) { + s32 value; + + value = i2c_smbus_read_byte_data(client, TC74_REG_CONFIG); + if (value < 0) { + dev_dbg(&client->dev, "TC74_REG_CONFIG read err %d\n", + (int)value); + + ret = value; + goto ret_unlock; + } + + if (!(value & BIT(6))) { + /* not ready yet */ + + ret = -EAGAIN; + goto ret_unlock; + } + + value = i2c_smbus_read_byte_data(client, TC74_REG_TEMP); + if (value < 0) { + dev_dbg(&client->dev, "TC74_REG_TEMP read err %d\n", + (int)value); + + ret = value; + goto ret_unlock; + } + + data->temp_input = value; + data->next_update = jiffies + HZ / 4; + data->valid = true; + } + +ret_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static ssize_t show_temp_input(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tc74_data *data = dev_get_drvdata(dev); + int ret; + + ret = tc74_update_device(dev); + if (ret) + return ret; + + return sprintf(buf, "%d\n", data->temp_input * 1000); +} +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp_input, NULL, 0); + +static struct attribute *tc74_attrs[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + NULL +}; + +ATTRIBUTE_GROUPS(tc74); + +static int tc74_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + struct device *dev = &client->dev; + struct tc74_data *data; + struct device *hwmon_dev; + s32 conf; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -EOPNOTSUPP; + + data = devm_kzalloc(dev, sizeof(struct tc74_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + mutex_init(&data->lock); + + /* Make sure the chip is powered up. */ + conf = i2c_smbus_read_byte_data(client, TC74_REG_CONFIG); + if (conf < 0) { + dev_err(dev, "unable to read config register\n"); + + return conf; + } + + if (conf & 0x3f) { + dev_err(dev, "invalid config register value\n"); + + return -ENODEV; + } + + if (conf & BIT(7)) { + s32 ret; + + conf &= ~BIT(7); + + ret = i2c_smbus_write_byte_data(client, TC74_REG_CONFIG, conf); + if (ret) + dev_warn(dev, "unable to disable STANDBY\n"); + } + + hwmon_dev = devm_hwmon_device_register_with_groups(dev, + client->name, + data, tc74_groups); + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static const struct i2c_device_id tc74_id[] = { + { "tc74", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, tc74_id); + +static struct i2c_driver tc74_driver = { + .driver = { + .name = "tc74", + }, + .probe = tc74_probe, + .id_table = tc74_id, +}; + +module_i2c_driver(tc74_driver); + +MODULE_AUTHOR("Maciej Szmigiero "); + +MODULE_DESCRIPTION("TC74 driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 820970a5aa3c98be26e1df64da4b93294d20d4e7 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 6 Mar 2015 14:08:20 +0530 Subject: ARCv2: [intc] HS38 core interrupt controller Cc: Jason Cooper Cc: Thomas Gleixner Signed-off-by: Vineet Gupta --- .../devicetree/bindings/arc/archs-intc.txt | 22 ++++ arch/arc/include/asm/arcregs.h | 1 + arch/arc/include/asm/irqflags-arcv2.h | 116 +++++++++++++++++ arch/arc/kernel/intc-arcv2.c | 143 +++++++++++++++++++++ 4 files changed, 282 insertions(+) create mode 100644 Documentation/devicetree/bindings/arc/archs-intc.txt create mode 100644 arch/arc/include/asm/irqflags-arcv2.h create mode 100644 arch/arc/kernel/intc-arcv2.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arc/archs-intc.txt b/Documentation/devicetree/bindings/arc/archs-intc.txt new file mode 100644 index 000000000000..69f326d6a5ad --- /dev/null +++ b/Documentation/devicetree/bindings/arc/archs-intc.txt @@ -0,0 +1,22 @@ +* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) + +Properties: + +- compatible: "snps,archs-intc" +- interrupt-controller: This is an interrupt controller. +- #interrupt-cells: Must be <1>. + + Single Cell "interrupts" property of a device specifies the IRQ number + between 16 to 256 + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +Example: + + intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <16 17 18 19 20 21 22 23 24 25>; + }; diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 336a9f694c2e..649646579986 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -31,6 +31,7 @@ #define ARC_REG_BPU_BCR 0xc0 #define ARC_REG_ISA_CFG_BCR 0xc1 #define ARC_REG_RTT_BCR 0xF2 +#define ARC_REG_IRQ_BCR 0xF3 #define ARC_REG_SMART_BCR 0xFF /* status32 Bits Positions */ diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h new file mode 100644 index 000000000000..c946c56f141c --- /dev/null +++ b/arch/arc/include/asm/irqflags-arcv2.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_IRQFLAGS_ARCV2_H +#define __ASM_IRQFLAGS_ARCV2_H + +#include + +/* status32 Bits */ +#define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */ +#define STATUS_IE_BIT 31 + +#define STATUS_AD_MASK (1< +#include +#include +#include +#include +#include "../../drivers/irqchip/irqchip.h" +#include + +/* + * Early Hardware specific Interrupt setup + * -Called very early (start_kernel -> setup_arch -> setup_processor) + * -Platform Independent (must for any ARC Core) + * -Needed for each CPU (hence not foldable into init_IRQ) + */ +void arc_init_IRQ(void) +{ + unsigned int tmp; + + struct aux_irq_ctrl { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int res3:18, save_idx_regs:1, res2:1, + save_u_to_u:1, save_lp_regs:1, save_blink:1, + res:4, save_nr_gpr_pairs:5; +#else + unsigned int save_nr_gpr_pairs:5, res:4, + save_blink:1, save_lp_regs:1, save_u_to_u:1, + res2:1, save_idx_regs:1, res3:18; +#endif + } ictrl; + + *(unsigned int *)&ictrl = 0; + + ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ + ictrl.save_blink = 1; + ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ + ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */ + ictrl.save_idx_regs = 1; /* JLI, LDI, EI */ + + WRITE_AUX(AUX_IRQ_CTRL, ictrl); + + /* setup status32, don't enable intr yet as kernel doesn't want */ + tmp = read_aux_reg(0xa); + tmp |= ISA_INIT_STATUS_BITS; + tmp &= ~STATUS_IE_MASK; + asm volatile("flag %0 \n"::"r"(tmp)); + + /* + * ARCv2 core intc provides multiple interrupt priorities (upto 16). + * Typical builds though have only two levels (0-high, 1-low) + * Linux by default uses lower prio 1 for most irqs, reserving 0 for + * NMI style interrupts in future (say perf) + * + * Read the intc BCR to confirm that Linux default priority is avail + * in h/w + * + * Note: + * IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level + * is 0 based. + */ + tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF; + if (ARCV2_IRQ_DEF_PRIO > tmp) + panic("Linux default irq prio incorrect\n"); +} + +static void arcv2_irq_mask(struct irq_data *data) +{ + write_aux_reg(AUX_IRQ_SELECT, data->irq); + write_aux_reg(AUX_IRQ_ENABLE, 0); +} + +static void arcv2_irq_unmask(struct irq_data *data) +{ + write_aux_reg(AUX_IRQ_SELECT, data->irq); + write_aux_reg(AUX_IRQ_ENABLE, 1); +} + +void arcv2_irq_enable(struct irq_data *data) +{ + /* set default priority */ + write_aux_reg(AUX_IRQ_SELECT, data->irq); + write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); + + /* + * hw auto enables (linux unmask) all by default + * So no need to do IRQ_ENABLE here + * XXX: However OSCI LAN need it + */ + write_aux_reg(AUX_IRQ_ENABLE, 1); +} + +static struct irq_chip arcv2_irq_chip = { + .name = "ARCv2 core Intc", + .irq_mask = arcv2_irq_mask, + .irq_unmask = arcv2_irq_unmask, + .irq_enable = arcv2_irq_enable +}; + +static int arcv2_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + if (irq == TIMER0_IRQ) + irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq); + else + irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops arcv2_irq_ops = { + .xlate = irq_domain_xlate_onecell, + .map = arcv2_irq_map, +}; + +static struct irq_domain *root_domain; + +static int __init +init_onchip_IRQ(struct device_node *intc, struct device_node *parent) +{ + if (parent) + panic("DeviceTree incore intc not a root irq controller\n"); + + root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, + &arcv2_irq_ops, NULL); + + if (!root_domain) + panic("root irq domain not avail\n"); + + /* with this we don't need to export root_domain */ + irq_set_default_host(root_domain); + + return 0; +} + +IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ); -- cgit v1.2.3 From eaf0ecc33f82b9c46528d1646575dd8caf586a3d Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 9 Mar 2015 14:03:10 +0530 Subject: ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution Cc: Jason Cooper Cc: Thomas Gleixner Signed-off-by: Vineet Gupta --- .../devicetree/bindings/arc/archs-idu-intc.txt | 46 ++++++ arch/arc/kernel/mcip.c | 183 ++++++++++++++++++++- 2 files changed, 228 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arc/archs-idu-intc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arc/archs-idu-intc.txt b/Documentation/devicetree/bindings/arc/archs-idu-intc.txt new file mode 100644 index 000000000000..0dcb7c7d3e40 --- /dev/null +++ b/Documentation/devicetree/bindings/arc/archs-idu-intc.txt @@ -0,0 +1,46 @@ +* ARC-HS Interrupt Distribution Unit + + This optional 2nd level interrupt controller can be used in SMP configurations for + dynamic IRQ routing, load balancing of common/external IRQs towards core intc. + +Properties: + +- compatible: "snps,archs-idu-intc" +- interrupt-controller: This is an interrupt controller. +- interrupt-parent: +- #interrupt-cells: Must be <2>. +- interrupts: <...> specifies the upstream core irqs + + First cell specifies the "common" IRQ from peripheral to IDU + Second cell specifies the irq distribution mode to cores + 0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +Example: + core_intc: core-interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + /* upstream core irqs: downstream these are "COMMON" irq 0,1.. */ + interrupts = <24 25 26 27 28 29 30 31>; + }; + + some_device: serial@c0fc1000 { + interrupt-parent = <&idu_intc>; + interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */ + }; diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c index ad7e90b97f6e..30284e8de6ff 100644 --- a/arch/arc/kernel/mcip.c +++ b/arch/arc/kernel/mcip.c @@ -14,10 +14,10 @@ #include static char smp_cpuinfo_buf[128]; +static int idu_detected; static DEFINE_RAW_SPINLOCK(mcip_lock); - /* * Any SMP specific init any CPU does when it comes up. * Here we setup the CPU to enable Inter-Processor-Interrupts @@ -150,6 +150,8 @@ void mcip_init_early_smp(void) IS_AVAIL1(mp.dbg, "DEBUG "), IS_AVAIL1(mp.grtc, "GRTC")); + idu_detected = mp.idu; + if (mp.dbg) { __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); @@ -158,3 +160,182 @@ void mcip_init_early_smp(void) if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc) panic("kernel trying to use non-existent GRTC\n"); } + +/*************************************************************************** + * ARCv2 Interrupt Distribution Unit (IDU) + * + * Connects external "COMMON" IRQs to core intc, providing: + * -dynamic routing (IRQ affinity) + * -load balancing (Round Robin interrupt distribution) + * -1:N distribution + * + * It physically resides in the MCIP hw block + */ + +#include +#include +#include +#include "../../drivers/irqchip/irqchip.h" + +/* + * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) + */ +static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) +{ + __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); +} + +static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, + unsigned int distr) +{ + union { + unsigned int word; + struct { + unsigned int distr:2, pad:2, lvl:1, pad2:27; + }; + } data; + + data.distr = distr; + data.lvl = lvl; + __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); +} + +static void idu_irq_mask(struct irq_data *data) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&mcip_lock, flags); + __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); + raw_spin_unlock_irqrestore(&mcip_lock, flags); +} + +static void idu_irq_unmask(struct irq_data *data) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&mcip_lock, flags); + __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); + raw_spin_unlock_irqrestore(&mcip_lock, flags); +} + +static int +idu_irq_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool f) +{ + return IRQ_SET_MASK_OK; +} + +static struct irq_chip idu_irq_chip = { + .name = "MCIP IDU Intc", + .irq_mask = idu_irq_mask, + .irq_unmask = idu_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = idu_irq_set_affinity, +#endif + +}; + +static int idu_first_irq; + +static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc) +{ + struct irq_domain *domain = irq_desc_get_handler_data(desc); + unsigned int idu_irq; + + idu_irq = core_irq - idu_first_irq; + generic_handle_irq(irq_find_mapping(domain, idu_irq)); +} + +static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); + irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); + + return 0; +} + +static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, + const u32 *intspec, unsigned int intsize, + irq_hw_number_t *out_hwirq, unsigned int *out_type) +{ + irq_hw_number_t hwirq = *out_hwirq = intspec[0]; + int distri = intspec[1]; + unsigned long flags; + + *out_type = IRQ_TYPE_NONE; + + /* XXX: validate distribution scheme again online cpu mask */ + if (distri == 0) { + /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ + raw_spin_lock_irqsave(&mcip_lock, flags); + idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); + idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); + raw_spin_unlock_irqrestore(&mcip_lock, flags); + } else { + /* + * DEST based distribution for Level Triggered intr can only + * have 1 CPU, so generalize it to always contain 1 cpu + */ + int cpu = ffs(distri); + + if (cpu != fls(distri)) + pr_warn("IDU irq %lx distri mode set to cpu %x\n", + hwirq, cpu); + + raw_spin_lock_irqsave(&mcip_lock, flags); + idu_set_dest(hwirq, cpu); + idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); + raw_spin_unlock_irqrestore(&mcip_lock, flags); + } + + return 0; +} + +static const struct irq_domain_ops idu_irq_ops = { + .xlate = idu_irq_xlate, + .map = idu_irq_map, +}; + +/* + * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) + * [24, 23+C]: If C > 0 then "C" common IRQs + * [24+C, N]: Not statically assigned, private-per-core + */ + + +static int __init +idu_of_init(struct device_node *intc, struct device_node *parent) +{ + struct irq_domain *domain; + /* Read IDU BCR to confirm nr_irqs */ + int nr_irqs = of_irq_count(intc); + int i, irq; + + if (!idu_detected) + panic("IDU not detected, but DeviceTree using it"); + + pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); + + domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); + + /* Parent interrupts (core-intc) are already mapped */ + + for (i = 0; i < nr_irqs; i++) { + /* + * Return parent uplink IRQs (towards core intc) 24,25,..... + * this step has been done before already + * however we need it to get the parent virq and set IDU handler + * as first level isr + */ + irq = irq_of_parse_and_map(intc, i); + if (!i) + idu_first_irq = irq; + + irq_set_handler_data(irq, domain); + irq_set_chained_handler(irq, idu_cascade_isr); + } + + __mcip_cmd(CMD_IDU_ENABLE, 0); + + return 0; +} +IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); -- cgit v1.2.3 From 891ee7aa19b0b0d54609e29636dbe0b0b348c458 Mon Sep 17 00:00:00 2001 From: Jacek Anaszewski Date: Tue, 28 Apr 2015 09:18:42 +0200 Subject: mfd: documentation: dt: Add documentation for the mfd Maxim max77693 This patch adds device tree binding documentation for the flash cell of the Maxim max77693 multifunctional device. Signed-off-by: Jacek Anaszewski Signed-off-by: Andrzej Hajda Acked-by: Kyungmin Park Acked-by: Sakari Ailus Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/max77693.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/max77693.txt b/Documentation/devicetree/bindings/mfd/max77693.txt index 38e64405e98d..d3425846aa5b 100644 --- a/Documentation/devicetree/bindings/mfd/max77693.txt +++ b/Documentation/devicetree/bindings/mfd/max77693.txt @@ -76,7 +76,60 @@ Optional properties: Valid values: 4300000, 4700000, 4800000, 4900000 Default: 4300000 +- led : the LED submodule device node + +There are two LED outputs available - FLED1 and FLED2. Each of them can +control a separate LED or they can be connected together to double +the maximum current for a single connected LED. One LED is represented +by one child node. + +Required properties: +- compatible : Must be "maxim,max77693-led". + +Optional properties: +- maxim,boost-mode : + In boost mode the device can produce up to 1.2A of total current + on both outputs. The maximum current on each output is reduced + to 625mA then. If not enabled explicitly, boost setting defaults to + LEDS_BOOST_FIXED in case both current sources are used. + Possible values: + LEDS_BOOST_OFF (0) - no boost, + LEDS_BOOST_ADAPTIVE (1) - adaptive mode, + LEDS_BOOST_FIXED (2) - fixed mode. +- maxim,boost-mvout : Output voltage of the boost module in millivolts. + Valid values: 3300 - 5500, step by 25 (rounded down) + Default: 3300 +- maxim,mvsys-min : Low input voltage level in millivolts. Flash is not fired + if chip estimates that system voltage could drop below this level due + to flash power consumption. + Valid values: 2400 - 3400, step by 33 (rounded down) + Default: 2400 + +Required properties for the LED child node: +- led-sources : see Documentation/devicetree/bindings/leds/common.txt; + device current output identifiers: 0 - FLED1, 1 - FLED2 +- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + Valid values for a LED connected to one FLED output: + 15625 - 250000, step by 15625 (rounded down) + Valid values for a LED connected to both FLED outputs: + 15625 - 500000, step by 15625 (rounded down) +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + Valid values for a single LED connected to one FLED output + (boost mode must be turned off): + 15625 - 1000000, step by 15625 (rounded down) + Valid values for a single LED connected to both FLED outputs: + 15625 - 1250000, step by 15625 (rounded down) + Valid values for two LEDs case: + 15625 - 625000, step by 15625 (rounded down) +- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt + Valid values: 62500 - 1000000, step by 62500 (rounded down) + +Optional properties for the LED child node: +- label : see Documentation/devicetree/bindings/leds/common.txt + Example: +#include + max77693@66 { compatible = "maxim,max77693"; reg = <0x66>; @@ -117,5 +170,19 @@ Example: maxim,thermal-regulation-celsius = <75>; maxim,battery-overcurrent-microamp = <3000000>; maxim,charge-input-threshold-microvolt = <4300000>; + + led { + compatible = "maxim,max77693-led"; + maxim,boost-mode = ; + maxim,boost-mvout = <5000>; + maxim,mvsys-min = <2400>; + + camera_flash: flash-led { + label = "max77693-flash"; + led-sources = <0>, <1>; + led-max-microamp = <500000>; + flash-max-microamp = <1250000>; + flash-max-timeout-us = <1000000>; + }; }; }; -- cgit v1.2.3 From 53960e2bff0107231d21f9ee7b31502b1daed344 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 20 Apr 2015 16:17:37 -0300 Subject: mfd: documentation: dt: max77686: Fix typo Fix typo in 'Multifunction'. Signed-off-by: Fabio Estevam Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/max77686.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt index e39f0bc1f55e..163bd81a4607 100644 --- a/Documentation/devicetree/bindings/mfd/max77686.txt +++ b/Documentation/devicetree/bindings/mfd/max77686.txt @@ -1,6 +1,6 @@ Maxim MAX77686 multi-function device -MAX77686 is a Mulitifunction device with PMIC, RTC and Charger on chip. It is +MAX77686 is a Multifunction device with PMIC, RTC and Charger on chip. It is interfaced to host controller using i2c interface. PMIC and Charger submodules are addressed using same i2c slave address whereas RTC submodule uses different i2c slave address,presently for which we are statically creating i2c -- cgit v1.2.3 From b64610dfbdf6a21e92073d50fef33704dbfe6028 Mon Sep 17 00:00:00 2001 From: Richard Fitzgerald Date: Fri, 1 May 2015 16:15:19 +0100 Subject: Documentation: Add WM8998/WM1814 device tree bindings Signed-off-by: Richard Fitzgerald Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/arizona.txt | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 7665aa95979f..64fa3b2de6cd 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -10,6 +10,9 @@ Required properties: "wlf,wm5110" "wlf,wm8280" "wlf,wm8997" + "wlf,wm8998" + "wlf,wm1814" + - reg : I2C slave address when connected using I2C, chip select number when using SPI. @@ -31,10 +34,10 @@ Required properties: as covered in Documentation/devicetree/bindings/regulator/regulator.txt - DBVDD2-supply, DBVDD3-supply : Additional databus power supplies (wm5102, - wm5110, wm8280) + wm5110, wm8280, wm8998, wm1814) - SPKVDDL-supply, SPKVDDR-supply : Speaker driver power supplies (wm5102, - wm5110, wm8280) + wm5110, wm8280, wm8998, wm1814) - SPKVDD-supply : Speaker driver power supply (wm8997) @@ -53,8 +56,10 @@ Optional properties: of input signals. Valid values are 0 (Differential), 1 (Single-ended) and 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. If present, values must be specified less than or equal to the number of - input singals. If values less than the number of input signals, elements - that has not been specifed are set to 0 by default. + input signals. If values less than the number of input signals, elements + that have not been specified are set to 0 by default. Entries are: + (wm5102, wm5110, wm8280, wm8997) + (wm8998, wm1814) - wlf,dmic-ref : DMIC reference voltage source for each input, can be selected from either MICVDD or one of the MICBIAS's, defines -- cgit v1.2.3 From 557e86e5c9613b46f19b7aac834aa6aa7cd2cc28 Mon Sep 17 00:00:00 2001 From: Steve Twiss Date: Tue, 19 May 2015 11:32:45 +0100 Subject: mfd: dt: Add bindings for DA9063 OnKey Add device tree bindings for the DA9063 OnKey driver. Signed-off-by: Steve Twiss Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/da9063.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/da9063.txt b/Documentation/devicetree/bindings/mfd/da9063.txt index 42c6fa6f1c9a..05b21bcb8543 100644 --- a/Documentation/devicetree/bindings/mfd/da9063.txt +++ b/Documentation/devicetree/bindings/mfd/da9063.txt @@ -5,6 +5,7 @@ DA9093 consists of a large and varied group of sub-devices (I2C Only): Device Supply Names Description ------ ------------ ----------- da9063-regulator : : LDOs & BUCKs +da9063-onkey : : On Key da9063-rtc : : Real-Time Clock da9063-watchdog : : Watchdog @@ -51,6 +52,18 @@ Sub-nodes: the DA9063. There are currently no entries in this binding, however compatible = "dlg,da9063-rtc" should be added if a node is created. +- onkey : This node defines the OnKey settings for controlling the key + functionality of the device. The node should contain the compatible property + with the value "dlg,da9063-onkey". + + Optional onkey properties: + + - dlg,disable-key-power : Disable power-down using a long key-press. If this + entry exists the OnKey driver will remove support for the KEY_POWER key + press. If this entry does not exist then by default the key-press + triggered power down is enabled and the OnKey will support both KEY_POWER + and KEY_SLEEP. + - watchdog : This node defines settings for the Watchdog timer associated with the DA9063. There are currently no entries in this binding, however compatible = "dlg,da9063-watchdog" should be added if a node is created. @@ -73,6 +86,11 @@ Example: compatible = "dlg,da9063-watchdog"; }; + onkey { + compatible = "dlg,da9063-onkey"; + dlg,disable-key-power; + }; + regulators { DA9063_BCORE1: bcore1 { regulator-name = "BCORE1"; -- cgit v1.2.3 From b901b518077ba87bc84c84de02fce186cf9e5856 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Thu, 4 Jun 2015 21:50:31 +0530 Subject: PM / OPP: Add new bindings to address shortcomings of existing bindings Current OPP (Operating performance point) device tree bindings have been insufficient due to the inflexible nature of the original bindings. Over time, we have realized that Operating Performance Point definitions and usage is varied depending on the SoC and a "single size (just frequency, voltage) fits all" model which the original bindings attempted and failed. The proposed next generation of the bindings addresses by providing a expandable binding for OPPs and introduces the following common shortcomings seen with the original bindings: - Getting clock/voltage/current rails sharing information between CPUs. Shared by all cores vs independent clock per core vs shared clock per cluster. - Support for specifying current levels along with voltages. - Support for multiple regulators. - Support for turbo modes. - Other per OPP settings: transition latencies, disabled status, etc.? - Expandability of OPPs in future. This patch introduces new bindings "operating-points-v2" to get these problems solved. Refer to the bindings for more details. We now have multiple versions of OPP binding and only one of them should be used per device. Signed-off-by: Viresh Kumar Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Acked-by: Nishanth Menon Signed-off-by: Rafael J. Wysocki --- Documentation/devicetree/bindings/power/opp.txt | 381 +++++++++++++++++++++++- 1 file changed, 377 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 74499e5033fc..259bf00edf7d 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -1,8 +1,19 @@ -* Generic OPP Interface +Generic OPP (Operating Performance Points) Bindings +---------------------------------------------------- -SoCs have a standard set of tuples consisting of frequency and -voltage pairs that the device will support per voltage domain. These -are called Operating Performance Points or OPPs. +Devices work at voltage-current-frequency combinations and some implementations +have the liberty of choosing these. These combinations are called Operating +Performance Points aka OPPs. This document defines bindings for these OPPs +applicable across wide range of devices. For illustration purpose, this document +uses CPU as a device. + +This document contain multiple versions of OPP binding and only one of them +should be used per device. + +Binding 1: operating-points +============================ + +This binding only supports voltage-frequency pairs. Properties: - operating-points: An array of 2-tuples items, and each item consists @@ -23,3 +34,365 @@ cpu@0 { 198000 850000 >; }; + + +Binding 2: operating-points-v2 +============================ + +* Property: operating-points-v2 + +Devices supporting OPPs must set their "operating-points-v2" property with +phandle to a OPP table in their DT node. The OPP core will use this phandle to +find the operating points for the device. + +If required, this can be extended for SoC vendor specfic bindings. Such bindings +should be documented as Documentation/devicetree/bindings/power/-opp.txt +and should have a compatible description like: "operating-points-v2-". + +* OPP Table Node + +This describes the OPPs belonging to a device. This node can have following +properties: + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2". + +- OPP nodes: One or more OPP nodes describing voltage-current-frequency + combinations. Their name isn't significant but their phandle can be used to + reference an OPP. + +Optional properties: +- opp-shared: Indicates that device nodes using this OPP Table Node's phandle + switch their DVFS state together, i.e. they share clock/voltage/current lines. + Missing property means devices have independent clock/voltage/current lines, + but they share OPP tables. + + +* OPP Node + +This defines voltage-current-frequency combinations along with other related +properties. + +Required properties: +- opp-hz: Frequency in Hz + +Optional properties: +- opp-microvolt: voltage in micro Volts. + + A single regulator's voltage is specified with an array of size one or three. + Single entry is for target voltage and three entries are for + voltages. + + Entries for multiple regulators must be present in the same order as + regulators are specified in device's DT node. + +- opp-microamp: The maximum current drawn by the device in microamperes + considering system specific parameters (such as transients, process, aging, + maximum operating temperature range etc.) as necessary. This may be used to + set the most efficient regulator operating mode. + + Should only be set if opp-microvolt is set for the OPP. + + Entries for multiple regulators must be present in the same order as + regulators are specified in device's DT node. If this property isn't required + for few regulators, then this should be marked as zero for them. If it isn't + required for any regulator, then this property need not be present. + +- clock-latency-ns: Specifies the maximum possible transition latency (in + nanoseconds) for switching to this OPP from any other OPP. + +- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is + available on some platforms, where the device can run over its operating + frequency for a short duration of time limited by the device's power, current + and thermal limits. + +- status: Marks the node enabled/disabled. + +Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + }; + opp01 { + opp-hz = <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + }; + opp02 { + opp-hz = <1200000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; +}; + +Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states +independently. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu_opp_table>; + }; + + cpu@1 { + compatible = "qcom,krait"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply1>; + operating-points-v2 = <&cpu_opp_table>; + }; + + cpu@2 { + compatible = "qcom,krait"; + reg = <2>; + next-level-cache = <&L2>; + clocks = <&clk_controller 2>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply2>; + operating-points-v2 = <&cpu_opp_table>; + }; + + cpu@3 { + compatible = "qcom,krait"; + reg = <3>; + next-level-cache = <&L2>; + clocks = <&clk_controller 3>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply3>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + /* + * Missing opp-shared property means CPUs switch DVFS states + * independently. + */ + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + }; + opp01 { + opp-hz = <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + }; + opp02 { + opp-hz = <1200000000>; + opp-microvolt = <1025000>; + opp-microamp = <90000; + lock-latency-ns = <290000>; + turbo-mode; + }; + }; +}; + +Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch +DVFS state together. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu@100 { + compatible = "arm,cortex-a15"; + reg = <100>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply1>; + operating-points-v2 = <&cluster1_opp>; + }; + + cpu@101 { + compatible = "arm,cortex-a15"; + reg = <101>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply1>; + operating-points-v2 = <&cluster1_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + }; + opp01 { + opp-hz = <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + }; + opp02 { + opp-hz = <1200000000>; + opp-microvolt = <1025000>; + opp-microamp = <90000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp10 { + opp-hz = <1300000000>; + opp-microvolt = <1045000 1050000 1055000>; + opp-microamp = <95000>; + clock-latency-ns = <400000>; + }; + opp11 { + opp-hz = <1400000000>; + opp-microvolt = <1075000>; + opp-microamp = <100000>; + clock-latency-ns = <400000>; + }; + opp12 { + opp-hz = <1500000000>; + opp-microvolt = <1010000 1100000 1110000>; + opp-microamp = <95000>; + clock-latency-ns = <400000>; + turbo-mode; + }; + }; +}; + +Example 4: Handling multiple regulators + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + cpu-supply = <&cpu_supply0>, <&cpu_supply1>, <&cpu_supply2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000>, /* Supply 0 */ + <960000>, /* Supply 1 */ + <960000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <70000>, /* Supply 1 */ + <70000>; /* Supply 2 */ + clock-latency-ns = <300000>; + }; + + /* OR */ + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>, /* Supply 0 */ + <960000 965000 975000>, /* Supply 1 */ + <960000 965000 975000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <70000>, /* Supply 1 */ + <70000>; /* Supply 2 */ + clock-latency-ns = <300000>; + }; + + /* OR */ + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>, /* Supply 0 */ + <960000 965000 975000>, /* Supply 1 */ + <960000 965000 975000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <0>, /* Supply 1 doesn't need this */ + <70000>; /* Supply 2 */ + clock-latency-ns = <300000>; + }; + }; +}; -- cgit v1.2.3 From a9a80e7e3177000344c3993411aada4d1e019f7c Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Mon, 22 Jun 2015 14:21:38 +0200 Subject: PM / OPP: Allow multiple OPP tables to be passed via DT On some platforms (Like Qualcomm's SoCs), it is not decided until runtime on what OPPs to use. The OPP tables can be fixed at compile time, but which table to use is found out only after reading some efuses (sort of an prom) and knowing characteristics of the SoC. To support such platform we need to pass multiple OPP tables per device and hardware should be able to choose one and only one table out of those. Update operating-points-v2 bindings to support that. Reviewed-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki --- Documentation/devicetree/bindings/power/opp.txt | 60 +++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 259bf00edf7d..3d5d32ca0f97 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -45,10 +45,21 @@ Devices supporting OPPs must set their "operating-points-v2" property with phandle to a OPP table in their DT node. The OPP core will use this phandle to find the operating points for the device. +Devices may want to choose OPP tables at runtime and so can provide a list of +phandles here. But only *one* of them should be chosen at runtime. This must be +accompanied by a corresponding "operating-points-names" property, to uniquely +identify the OPP tables. + If required, this can be extended for SoC vendor specfic bindings. Such bindings should be documented as Documentation/devicetree/bindings/power/-opp.txt and should have a compatible description like: "operating-points-v2-". +Optional properties: +- operating-points-names: Names of OPP tables (required if multiple OPP + tables are present), to uniquely identify them. The same list must be present + for all the CPUs which are sharing clock/voltage rails and hence the OPP + tables. + * OPP Table Node This describes the OPPs belonging to a device. This node can have following @@ -68,6 +79,8 @@ Optional properties: Missing property means devices have independent clock/voltage/current lines, but they share OPP tables. +- status: Marks the OPP table enabled/disabled. + * OPP Node @@ -396,3 +409,50 @@ Example 4: Handling multiple regulators }; }; }; + +Example 5: Multiple OPP tables + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + cpu-supply = <&cpu_supply> + operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; + operating-points-names = "slow", "fast"; + }; + }; + + cpu0_opp_table_slow: opp_table_slow { + compatible = "operating-points-v2"; + status = "okay"; + opp-shared; + + opp00 { + opp-hz = <600000000>; + ... + }; + + opp01 { + opp-hz = <800000000>; + ... + }; + }; + + cpu0_opp_table_fast: opp_table_fast { + compatible = "operating-points-v2"; + status = "okay"; + opp-shared; + + opp10 { + opp-hz = <1000000000>; + ... + }; + + opp11 { + opp-hz = <1100000000>; + ... + }; + }; +}; -- cgit v1.2.3 From 9f20d6815c6c537980b8a8fcb1a172c0b95bd99f Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Mon, 22 Jun 2015 14:23:27 +0200 Subject: PM / OPP: Add binding for 'opp-suspend' On few platforms, for power efficiency, we want the device to be configured for a specific OPP while we put the device in suspend state. Add an optional property in operating-points-v2 bindings for that. Suggested-by: Nishanth Menon Signed-off-by: Viresh Kumar Acked-by: Nishanth Menon Acked-by: Rob Herring Signed-off-by: Rafael J. Wysocki --- Documentation/devicetree/bindings/power/opp.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 3d5d32ca0f97..0d5e7c978121 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -120,6 +120,9 @@ Optional properties: frequency for a short duration of time limited by the device's power, current and thermal limits. +- opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in + the table should have this. + - status: Marks the node enabled/disabled. Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. @@ -159,6 +162,7 @@ Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. opp-microvolt = <970000 975000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; + opp-suspend; }; opp01 { opp-hz = <1100000000>; @@ -237,6 +241,7 @@ independently. opp-microvolt = <970000 975000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; + opp-suspend; }; opp01 { opp-hz = <1100000000>; @@ -312,6 +317,7 @@ DVFS state together. opp-microvolt = <970000 975000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; + opp-suspend; }; opp01 { opp-hz = <1100000000>; @@ -337,6 +343,7 @@ DVFS state together. opp-microvolt = <1045000 1050000 1055000>; opp-microamp = <95000>; clock-latency-ns = <400000>; + opp-suspend; }; opp11 { opp-hz = <1400000000>; -- cgit v1.2.3 From 6f48fdf3bb86a173655502f178f6972291c2c0c5 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 9 Apr 2015 15:47:30 +0100 Subject: watchdog: bindings: Provide ST bindings for ST's LPC Watchdog device On current ST platforms the LPC controls a number of functions including Watchdog and Real Time Clock. This patch provides the bindings used to configure LPC in Watchdog mode. Signed-off-by: Lee Jones Signed-off-by: Wim Van Sebroeck --- .../devicetree/bindings/watchdog/st_lpc_wdt.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt b/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt new file mode 100644 index 000000000000..388c88a01222 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt @@ -0,0 +1,38 @@ +STMicroelectronics Low Power Controller (LPC) - Watchdog +======================================================== + +LPC currently supports Watchdog OR Real Time Clock functionality. + +[See: ../rtc/rtc-st-lpc.txt for RTC options] + +Required properties + +- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc" + "st,stih415-lpc" "st,stid127-lpc" +- reg : LPC registers base address + size +- interrupts : LPC interrupt line number and associated flags +- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) +- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or + ST_LPC_MODE_WDT [1]. One (and only one) mode must be + selected. + +Required properties [watchdog mode] + +- st,syscfg : Phandle to syscfg node used to enable watchdog and configure + CPU reset type. +- timeout-sec : Watchdog timeout in seconds + +Optional properties [watchdog mode] + +- st,warm-reset : If present reset type will be 'warm' - if not it will be cold + +Example: + lpc@fde05000 { + compatible = "st,stih407-lpc"; + reg = <0xfde05000 0x1000>; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + st,syscfg = <&syscfg_core>; + timeout-sec = <120>; + st,lpc-mode = ; + st,warm-reset; + }; -- cgit v1.2.3 From b0abc8ff75e25901fe4afcd62d5e4315df4a8138 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 31 Mar 2015 09:14:58 +0300 Subject: watchdog: digicolor: document device tree binding Add a device tree binding documentation to the watchdog hardware block on the Conexant CX92755 SoC. The CX92755 is from the Digicolor SoCs series. Other SoCs in that series may share the same hardware block. Signed-off-by: Baruch Siach Reviewed-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../devicetree/bindings/watchdog/digicolor-wdt.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt b/Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt new file mode 100644 index 000000000000..a882967e17d4 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/digicolor-wdt.txt @@ -0,0 +1,25 @@ +Conexant Digicolor SoCs Watchdog timer + +The watchdog functionality in Conexant Digicolor SoCs relies on the so called +"Agent Communication" block. This block includes the eight programmable system +timer counters. The first timer (called "Timer A") is the only one that can be +used as watchdog. + +Required properties: + +- compatible : Should be "cnxt,cx92755-wdt" +- reg : Specifies base physical address and size of the registers +- clocks : phandle; specifies the clock that drives the timer + +Optional properties: + +- timeout-sec : Contains the watchdog timeout in seconds + +Example: + + watchdog@f0000fc0 { + compatible = "cnxt,cx92755-wdt"; + reg = <0xf0000fc0 0x8>; + clocks = <&main_clk>; + timeout-sec = <15>; + }; -- cgit v1.2.3 From 83efa1cbcff406f0305d4b227d356d6bdce8cb13 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 27 Apr 2015 11:22:58 +0200 Subject: watchdog: omap: clearify device tree documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ti,hwmods doesn't belong into the compatible section but is a property on it's own. Also reformat the section of required properties to match the usual style of dt binding documents. Signed-off-by: Uwe Kleine-König Reviewed-by: Felipe Balbi Acked-by: Felipe Balbi Reviewed-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/omap-wdt.txt | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt index c227970671ea..597e19d18dca 100644 --- a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt @@ -1,10 +1,8 @@ TI Watchdog Timer (WDT) Controller for OMAP Required properties: -compatible: -- "ti,omap3-wdt" for OMAP3 -- "ti,omap4-wdt" for OMAP4 -- ti,hwmods: Name of the hwmod associated to the WDT +- compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4 +- ti,hwmods : Name of the hwmod associated to the WDT Examples: -- cgit v1.2.3 From a4f741e3e157c3a5c8aea5f2ea62b692fbf17338 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 27 Apr 2015 11:22:59 +0200 Subject: watchdog: omap: use watchdog_init_timeout instead of open coding it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of (partly) open coding watchdog_init_timeout to determine the inital timeout use the core function that exists for exactly this purpose. As a side effect the "timeout-sec" device-tree property is recognized now (though currently unused in the omap device trees). Signed-off-by: Uwe Kleine-König Reviewed-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/omap-wdt.txt | 3 +++ drivers/watchdog/omap_wdt.c | 5 +---- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt index 597e19d18dca..1fa20e453a2d 100644 --- a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt @@ -4,6 +4,9 @@ Required properties: - compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4 - ti,hwmods : Name of the hwmod associated to the WDT +Optional properties: +- timeout-sec : default watchdog timeout in seconds + Examples: wdt2: wdt@4a314000 { diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 1e6be9e40577..88ca2ea88695 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -234,10 +234,7 @@ static int omap_wdt_probe(struct platform_device *pdev) omap_wdt->min_timeout = TIMER_MARGIN_MIN; omap_wdt->max_timeout = TIMER_MARGIN_MAX; - if (timer_margin >= TIMER_MARGIN_MIN && - timer_margin <= TIMER_MARGIN_MAX) - omap_wdt->timeout = timer_margin; - else + if (watchdog_init_timeout(omap_wdt, timer_margin, &pdev->dev) < 0) omap_wdt->timeout = TIMER_MARGIN_DEFAULT; watchdog_set_drvdata(omap_wdt, wdev); -- cgit v1.2.3 From a47911e99fe8d2080426951711a7e776d331ba77 Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Wed, 17 Jun 2015 11:13:27 +0200 Subject: watchdog: docs: omap_wdt also understands nowayout The omap_wdt kernel driver also understands the nowayout module parameter. This updates the watchdog-parameters.txt to reflect this fact. Signed-off-by: Lars Poeschel Reviewed-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/watchdog/watchdog-parameters.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/watchdog/watchdog-parameters.txt b/Documentation/watchdog/watchdog-parameters.txt index 692791cc674c..74252c431e05 100644 --- a/Documentation/watchdog/watchdog-parameters.txt +++ b/Documentation/watchdog/watchdog-parameters.txt @@ -208,6 +208,8 @@ nowayout: Watchdog cannot be stopped once started ------------------------------------------------- omap_wdt: timer_margin: initial watchdog timeout (in seconds) +nowayout: Watchdog cannot be stopped once started + (default=kernel config parameter) ------------------------------------------------- orion_wdt: heartbeat: Initial watchdog heartbeat in seconds -- cgit v1.2.3 From ed45d403696150864ee3090e69e0564d4397eebc Mon Sep 17 00:00:00 2001 From: Anish Bhatt Date: Mon, 8 Jun 2015 17:37:31 -0700 Subject: kbuild : Fix documentation of INSTALL_HDR_PATH The header install makefile creates an 'include' directory inside INSTALL_HDR_PATH and appending include to the path results in headers being installed to include/include. Don't recommend appending include to the path as makefile already does this. Signed-off-by: Anish Bhatt Signed-off-by: Jonathan Corbet --- Documentation/kbuild/headers_install.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/kbuild/headers_install.txt b/Documentation/kbuild/headers_install.txt index 951eb9f1e040..f0153adb95e2 100644 --- a/Documentation/kbuild/headers_install.txt +++ b/Documentation/kbuild/headers_install.txt @@ -24,7 +24,7 @@ The "make headers_install" command can be run in the top level directory of the kernel source code (or using a standard out-of-tree build). It takes two optional arguments: - make headers_install ARCH=i386 INSTALL_HDR_PATH=/usr/include + make headers_install ARCH=i386 INSTALL_HDR_PATH=/usr ARCH indicates which architecture to produce headers for, and defaults to the current architecture. The linux/asm directory of the exported kernel headers @@ -33,8 +33,11 @@ the command: ls -d include/asm-* | sed 's/.*-//' -INSTALL_HDR_PATH indicates where to install the headers. It defaults to -"./usr/include". +INSTALL_HDR_PATH indicates where to install the headers. It defaults to +"./usr". + +An 'include' directory is automatically created inside INSTALL_HDR_PATH and +headers are installed in 'INSTALL_HDR_PATH/include'. The command "make headers_install_all" exports headers for all architectures simultaneously. (This is mostly of interest to distribution maintainers, -- cgit v1.2.3 From ce9ae951d45a8595d43b614063ec9b49fa236d5c Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Wed, 10 Jun 2015 12:53:47 +0900 Subject: Doc:pps: Fix typo in pps.txt This patch fix a spelling typo in Documentation/pps/pps.txt Signed-off-by: Masanari Iida Acked-by: Rodolfo Giometti [jc: did s/into/in the/ on the same line while we were there] Signed-off-by: Jonathan Corbet --- Documentation/pps/pps.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/pps/pps.txt b/Documentation/pps/pps.txt index c03b1be5eb15..c508cceeee7d 100644 --- a/Documentation/pps/pps.txt +++ b/Documentation/pps/pps.txt @@ -166,7 +166,7 @@ Testing the PPS support In order to test the PPS support even without specific hardware you can use the ktimer driver (see the client subsection in the PPS configuration menu) -and the userland tools provided into Documentaion/pps/ directory. +and the userland tools provided in the Documentation/pps/ directory. Once you have enabled the compilation of ktimer just modprobe it (if not statically compiled): -- cgit v1.2.3 From c43088e3b8caec2362dec4e9e899493fa6440e22 Mon Sep 17 00:00:00 2001 From: Alexander Kuleshov Date: Wed, 10 Jun 2015 23:21:15 +0600 Subject: Documentation/kernel-parameters: add missing pciserial to the earlyprintk The PCI based UART can be specified for earlyprintk with the 'pciserial' parameter from the ea9e9d802. This patch adds missing information about this parameter. Signed-off-by: Alexander Kuleshov Signed-off-by: Jonathan Corbet --- Documentation/kernel-parameters.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index e9159eb986ec..a74d62f4c821 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1009,6 +1009,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. earlyprintk=serial[,0x...[,baudrate]] earlyprintk=ttySn[,baudrate] earlyprintk=dbgp[debugController#] + earlyprintk=pciserial,bus:device.function[,baudrate] earlyprintk is useful when the kernel crashes before the normal console is initialized. It is not enabled by -- cgit v1.2.3 From ae13c65bc74a69f06b39d0124af60710ba6d0d49 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Thu, 18 Jun 2015 00:12:02 +0900 Subject: Doc: Change wikipedia's URL from http to https Recently wikipedia announced to secure access to the servers. Now all http access re-route to https. Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/RCU/RTFP.txt | 2 +- Documentation/arm/vlocks.txt | 2 +- Documentation/debugging-via-ohci1394.txt | 2 +- Documentation/input/rotary-encoder.txt | 2 +- Documentation/kmemleak.txt | 2 +- Documentation/networking/fore200e.txt | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/RCU/RTFP.txt b/Documentation/RCU/RTFP.txt index f29bcbc463e7..370ca006db7a 100644 --- a/Documentation/RCU/RTFP.txt +++ b/Documentation/RCU/RTFP.txt @@ -1496,7 +1496,7 @@ Canis Rufus and Zoicon5 and Anome and Hal Eisen" ,month="July" ,day="8" ,year="2006" -,note="\url{http://en.wikipedia.org/wiki/Read-copy-update}" +,note="\url{https://en.wikipedia.org/wiki/Read-copy-update}" ,annotation={ Wikipedia RCU page as of July 8 2006. [Viewed August 21, 2006] diff --git a/Documentation/arm/vlocks.txt b/Documentation/arm/vlocks.txt index 415960a9bab0..45731672c564 100644 --- a/Documentation/arm/vlocks.txt +++ b/Documentation/arm/vlocks.txt @@ -206,6 +206,6 @@ References [1] Lamport, L. "A New Solution of Dijkstra's Concurrent Programming Problem", Communications of the ACM 17, 8 (August 1974), 453-455. - http://en.wikipedia.org/wiki/Lamport%27s_bakery_algorithm + https://en.wikipedia.org/wiki/Lamport%27s_bakery_algorithm [2] linux/arch/arm/common/vlock.S, www.kernel.org. diff --git a/Documentation/debugging-via-ohci1394.txt b/Documentation/debugging-via-ohci1394.txt index 5c9a567b3fac..03703afc4d30 100644 --- a/Documentation/debugging-via-ohci1394.txt +++ b/Documentation/debugging-via-ohci1394.txt @@ -181,4 +181,4 @@ Notes Documentation and specifications: http://halobates.de/firewire/ FireWire is a trademark of Apple Inc. - for more information please refer to: -http://en.wikipedia.org/wiki/FireWire +https://en.wikipedia.org/wiki/FireWire diff --git a/Documentation/input/rotary-encoder.txt b/Documentation/input/rotary-encoder.txt index 92e68bce13a4..5737e3590adb 100644 --- a/Documentation/input/rotary-encoder.txt +++ b/Documentation/input/rotary-encoder.txt @@ -33,7 +33,7 @@ The phase diagram of these two outputs look like this: one step (half-period mode) For more information, please see - http://en.wikipedia.org/wiki/Rotary_encoder + https://en.wikipedia.org/wiki/Rotary_encoder 1. Events / state machine diff --git a/Documentation/kmemleak.txt b/Documentation/kmemleak.txt index 45e777f4e41d..18e24abb3ecf 100644 --- a/Documentation/kmemleak.txt +++ b/Documentation/kmemleak.txt @@ -6,7 +6,7 @@ Introduction Kmemleak provides a way of detecting possible kernel memory leaks in a way similar to a tracing garbage collector -(http://en.wikipedia.org/wiki/Garbage_collection_%28computer_science%29#Tracing_garbage_collectors), +(https://en.wikipedia.org/wiki/Garbage_collection_%28computer_science%29#Tracing_garbage_collectors), with the difference that the orphan objects are not freed but only reported via /sys/kernel/debug/kmemleak. A similar method is used by the Valgrind tool (memcheck --leak-check) to detect the memory leaks in diff --git a/Documentation/networking/fore200e.txt b/Documentation/networking/fore200e.txt index d52af53efdc5..1f98f62b4370 100644 --- a/Documentation/networking/fore200e.txt +++ b/Documentation/networking/fore200e.txt @@ -37,7 +37,7 @@ version. Alternative binary firmware images can be found somewhere on the ForeThought CD-ROM supplied with your adapter by FORE Systems. You can also get the latest firmware images from FORE Systems at -http://en.wikipedia.org/wiki/FORE_Systems. Register TACTics Online and go to +https://en.wikipedia.org/wiki/FORE_Systems. Register TACTics Online and go to the 'software updates' pages. The firmware binaries are part of the various ForeThought software distributions. -- cgit v1.2.3 From 57d1c23f9829a0f3a0bebf41f49ea9b0f2819c26 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Thu, 18 Jun 2015 23:44:25 +0900 Subject: Doc: Docbook: Change wikipedia's URL from http to https in scsi.tmpl Recently wikipedia announced to secure access to the servers. Now all http access re-route to https. Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/DocBook/scsi.tmpl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/DocBook/scsi.tmpl b/Documentation/DocBook/scsi.tmpl index 324b53494f08..4b9b9b286cea 100644 --- a/Documentation/DocBook/scsi.tmpl +++ b/Documentation/DocBook/scsi.tmpl @@ -81,7 +81,7 @@ SAS, Fibre Channel, FireWire, and ATAPI devices. SCSI packets are also commonly exchanged over Infiniband, I20, TCP/IP - (iSCSI), even + (iSCSI), even Parallel ports. -- cgit v1.2.3 From e368c7291f20c624cfc202a8ad836d6de54c0c24 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Sat, 20 Jun 2015 11:17:20 +0900 Subject: Doc:ABI/testing: Fix typo in sysfs-bus-fcoe This patch fix some spelling typo in sysfs-bus-fcoe Signed-off-by: Masanari Iida Signed-off-by: Jonathan Corbet --- Documentation/ABI/testing/sysfs-bus-fcoe | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-fcoe b/Documentation/ABI/testing/sysfs-bus-fcoe index 21640eaad371..657df13b100d 100644 --- a/Documentation/ABI/testing/sysfs-bus-fcoe +++ b/Documentation/ABI/testing/sysfs-bus-fcoe @@ -32,7 +32,7 @@ Description: 'FCoE Controller' instances on the fcoe bus. Attributes: - fcf_dev_loss_tmo: Device loss timeout peroid (see below). Changing + fcf_dev_loss_tmo: Device loss timeout period (see below). Changing this value will change the dev_loss_tmo for all FCFs discovered by this controller. @@ -61,7 +61,7 @@ Attributes: lesb/err_block: Link Error Status Block (LESB) block error count. lesb/fcs_error: Link Error Status Block (LESB) Fibre Channel - Serivces error count. + Services error count. Notes: ctlr_X (global increment starting at 0) @@ -85,7 +85,7 @@ Attributes: fabric. selected: 1 indicates that the switch has been selected for use; - 0 indicates that the swich will not be used. + 0 indicates that the switch will not be used. fc_map: The Fibre Channel MAP @@ -93,7 +93,7 @@ Attributes: mac: The FCF's MAC address - fka_peroid: The FIP Keep-Alive peroid + fka_period: The FIP Keep-Alive period fabric_state: The internal kernel state "Unknown" - Initialization value @@ -101,9 +101,9 @@ Attributes: "Connected" - Host is connected to the FCF "Deleted" - FCF is being removed from the system - dev_loss_tmo: The device loss timeout peroid for this FCF. + dev_loss_tmo: The device loss timeout period for this FCF. -Notes: A device loss infrastructre similar to the FC Transport's +Notes: A device loss infrastructure similar to the FC Transport's is present in fcoe_sysfs. It is nice to have so that a link flapping adapter doesn't continually advance the count used to identify the discovered FCF. FCFs will exist in a -- cgit v1.2.3 From 8bdc89390ed645c7d7c1e23470d24fbd523e7168 Mon Sep 17 00:00:00 2001 From: Jacek Anaszewski Date: Mon, 8 Jun 2015 02:02:21 -0700 Subject: DT: aat1290: Document handling external strobe sources This patch adds documentation for a pinctrl-names property. The property, when present, is used for switching the source of the strobe signal for the device. Signed-off-by: Jacek Anaszewski Acked-by: Kyungmin Park Cc: Bryan Wu Cc: Richard Purdie Cc: devicetree@vger.kernel.org Acked-by: Sakari Ailus Signed-off-by: Bryan Wu --- .../devicetree/bindings/leds/leds-aat1290.txt | 36 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/leds/leds-aat1290.txt b/Documentation/devicetree/bindings/leds/leds-aat1290.txt index ef88b9c53e37..c05ed91a4e42 100644 --- a/Documentation/devicetree/bindings/leds/leds-aat1290.txt +++ b/Documentation/devicetree/bindings/leds/leds-aat1290.txt @@ -2,7 +2,9 @@ The device is controlled through two pins: FL_EN and EN_SET. The pins when, asserted high, enable flash strobe and movie mode (max 1/2 of flash current) -respectively. +respectively. In order to add a capability of selecting the strobe signal source +(e.g. CPU or camera sensor) there is an additional switch required, independent +of the flash chip. The switch is controlled with pin control. Required properties: @@ -10,6 +12,13 @@ Required properties: - flen-gpios : Must be device tree identifier of the flash device FL_EN pin. - enset-gpios : Must be device tree identifier of the flash device EN_SET pin. +Optional properties: +- pinctrl-names : Must contain entries: "default", "host", "isp". Entries + "default" and "host" must refer to the same pin configuration + node, which sets the host as a strobe signal provider. Entry + "isp" must refer to the pin configuration node, which sets the + ISP as a strobe signal provider. + A discrete LED element connected to the device must be represented by a child node - see Documentation/devicetree/bindings/leds/common.txt. @@ -25,13 +34,22 @@ Required properties of the LED child node: Optional properties of the LED child node: - label : see Documentation/devicetree/bindings/leds/common.txt -Example (by Ct = 220nF, Rset = 160kohm): +Example (by Ct = 220nF, Rset = 160kohm and exynos4412-trats2 board with +a switch that allows for routing strobe signal either from the host or from +the camera sensor): + +#include "exynos4412.dtsi" aat1290 { compatible = "skyworks,aat1290"; flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "host", "isp"; + pinctrl-0 = <&camera_flash_host>; + pinctrl-1 = <&camera_flash_host>; + pinctrl-2 = <&camera_flash_isp>; + camera_flash: flash-led { label = "aat1290-flash"; led-max-microamp = <520833>; @@ -39,3 +57,17 @@ aat1290 { flash-timeout-us = <1940000>; }; }; + +&pinctrl_0 { + camera_flash_host: camera-flash-host { + samsung,pins = "gpj1-0"; + samsung,pin-function = <1>; + samsung,pin-val = <0>; + }; + + camera_flash_isp: camera-flash-isp { + samsung,pins = "gpj1-0"; + samsung,pin-function = <1>; + samsung,pin-val = <1>; + }; +}; -- cgit v1.2.3 From 6a407a81a9abcf6664698b22e70d070605063f7c Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sat, 20 Jun 2015 21:10:28 -0400 Subject: Documentation/vDSO: don't build tests when cross compiling The following was seen in linux-next build coverage, which is somewhat unique since it uses powerpc host to cross compile x86: Documentation/vDSO/vdso_standalone_test_x86.c:49:2: error: impossible register constraint in 'asm' make[4]: *** [Documentation/vDSO/vdso_standalone_test_x86.o] Error 1 It probably makes sense to just skip building these tests when we are cross compiling. Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: Andy Lutomirski Signed-off-by: Paul Gortmaker Signed-off-by: Jonathan Corbet --- Documentation/vDSO/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/vDSO/Makefile b/Documentation/vDSO/Makefile index ee075c3d2124..b12e98770e1f 100644 --- a/Documentation/vDSO/Makefile +++ b/Documentation/vDSO/Makefile @@ -1,3 +1,4 @@ +ifndef CROSS_COMPILE # vdso_test won't build for glibc < 2.16, so disable it # hostprogs-y := vdso_test hostprogs-$(CONFIG_X86) := vdso_standalone_test_x86 @@ -13,3 +14,4 @@ HOSTLOADLIBES_vdso_standalone_test_x86 := -nostdlib ifeq ($(CONFIG_X86_32),y) HOSTLOADLIBES_vdso_standalone_test_x86 += -lgcc_s endif +endif -- cgit v1.2.3 From f59514b6a8c5ca6dd282881a25e367e20ef4cb68 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sat, 20 Jun 2015 21:22:20 -0400 Subject: Documentation/prctl: don't build tsc tests when cross compiling The following was seen in linux-next build coverage, which is somewhat unique since it uses powerpc host to cross compile x86: Documentation/prctl/disable-tsc-on-off-stress-test.c:36:1: error: impossible register constraint in 'asm' Documentation/prctl/disable-tsc-ctxt-sw-stress-test.c:34:1: error: impossible register constraint in 'asm' Documentation/prctl/disable-tsc-test.c:36:1: error: impossible register constraint in 'asm' It probably makes sense to just skip building these tests when we are cross compiling. Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: Erik Bosman Signed-off-by: Paul Gortmaker Signed-off-by: Jonathan Corbet --- Documentation/prctl/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/prctl/Makefile b/Documentation/prctl/Makefile index 2948b7b124b9..44de3080c7f2 100644 --- a/Documentation/prctl/Makefile +++ b/Documentation/prctl/Makefile @@ -1,3 +1,4 @@ +ifndef CROSS_COMPILE # List of programs to build hostprogs-$(CONFIG_X86) := disable-tsc-ctxt-sw-stress-test disable-tsc-on-off-stress-test disable-tsc-test # Tell kbuild to always build the programs @@ -6,3 +7,4 @@ always := $(hostprogs-y) HOSTCFLAGS_disable-tsc-ctxt-sw-stress-test.o += -I$(objtree)/usr/include HOSTCFLAGS_disable-tsc-on-off-stress-test.o += -I$(objtree)/usr/include HOSTCFLAGS_disable-tsc-test.o += -I$(objtree)/usr/include +endif -- cgit v1.2.3 From 65f6f092a6987489a5a4d7d63a2a825077755aff Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 21 Jun 2015 00:32:05 -0400 Subject: Documentation/mic/mpssd: don't build x86 userspace when cross compiling The following was seen in linux-next build coverage, which is somewhat unique since it uses powerpc host to cross compile x86: Documentation/mic/mpssd/mpssd.c:93:10: error: braced-group within expression allowed only inside a function Documentation/mic/mpssd/mpssd.c:96:10: error: braced-group within expression allowed only inside a function Documentation/mic/mpssd/mpssd.c:113:10: error: braced-group within expression allowed only inside a function Documentation/mic/mpssd/mpssd.c:116:10: error: braced-group within expression allowed only inside a function Documentation/mic/mpssd/mpssd.c:119:3: error: initializer element is not constant Documentation/mic/mpssd/mpssd.c:119:3: error: (near initialization for 'virtnet_dev_page.host_features') Documentation/mic/mpssd/mpssd.c:146:10: error: braced-group within expression allowed only inside a function Documentation/mic/mpssd/mpssd.c:149:3: error: initializer element is not constant Documentation/mic/mpssd/mpssd.c:149:3: error: (near initialization for 'virtblk_dev_page.host_features') Documentation/mic/mpssd/mpssd.c:151:3: error: initializer element is not constant Documentation/mic/mpssd/mpssd.c:151:3: error: (near initialization for 'virtblk_dev_page.blk_config.seg_max') Documentation/mic/mpssd/mpssd.c:152:3: error: initializer element is not constant Documentation/mic/mpssd/mpssd.c:152:3: error: (near initialization for 'virtblk_dev_page.blk_config.capacity') make[5]: *** [Documentation/mic/mpssd/mpssd.o] Error 1 Since it is building /usr/sbin/mpssd and /usr/sbin/micctrl for x86_64 and the original authors indicated[1] that: MIC card is expected to work with x86_64 host, not with ppc64. We have never compiled on ppc host.. so it probably makes sense to just skip building these userspace programs when we are cross compiling. [1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-December/123296.html Cc: Jonathan Corbet Cc: Ashutosh Dixit Cc: Sudeep Dutt Cc: Caz Yokoyama Cc: linux-doc@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Jonathan Corbet --- Documentation/mic/mpssd/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/mic/mpssd/Makefile b/Documentation/mic/mpssd/Makefile index f47fe6ba7300..06871b0c08a6 100644 --- a/Documentation/mic/mpssd/Makefile +++ b/Documentation/mic/mpssd/Makefile @@ -1,3 +1,4 @@ +ifndef CROSS_COMPILE # List of programs to build hostprogs-$(CONFIG_X86_64) := mpssd @@ -17,3 +18,4 @@ HOSTLOADLIBES_mpssd := -lpthread install: install mpssd /usr/sbin/mpssd install micctrl /usr/sbin/micctrl +endif -- cgit v1.2.3 From 41655239eaed741ac8da066bc43c2483c78e61ec Mon Sep 17 00:00:00 2001 From: Daniel Thompson Date: Wed, 10 Jun 2015 21:09:36 +0100 Subject: dt-bindings: Document the STM32F4 clock bindings This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson Acked-by: Maxime Coquelin Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 000000000000..fee3205cdff9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (CRYP) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + }; -- cgit v1.2.3 From e1d0be616186906ddc2a23bdf643c02551feebf0 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Wed, 28 Jan 2015 02:53:55 +0900 Subject: sh-sci: Add h8300 SCI Signed-off-by: Yoshinori Sato Acked-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 + drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 ++++++ 3 files changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index ae73bb0e9ad9..7534d46e9ad8 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -29,6 +29,7 @@ Required properties: - "renesas,scifa" for generic SCIFA compatible UART. - "renesas,scifb" for generic SCIFB compatible UART. - "renesas,hscif" for generic HSCIF compatible UART. + - "renesas,sci" for generic SCI compatible UART. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first followed by the diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index f8120c1bde14..dea1eff6a92c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -728,7 +728,7 @@ config SERIAL_IP22_ZILOG_CONSOLE config SERIAL_SH_SCI tristate "SuperH SCI(F) serial port support" - depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST + depends on SUPERH || ARCH_SHMOBILE || H8300 || COMPILE_TEST select SERIAL_CORE config SERIAL_SH_SCI_NR_UARTS diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index e7d6566fafaf..1468ec5047cc 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2535,6 +2535,12 @@ static const struct of_device_id of_sci_match[] = { .type = PORT_HSCIF, .regtype = SCIx_HSCIF_REGTYPE, }, + }, { + .compatible = "renesas,sci", + .data = &(const struct sci_port_info) { + .type = PORT_SCI, + .regtype = SCIx_SCI_REGTYPE, + }, }, { /* Terminator */ }, -- cgit v1.2.3 From d8b0bdb444ed0e2bd5f9d3ea7412cb90bdec58cf Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Mon, 11 May 2015 02:31:32 +0900 Subject: h8300: kernel startup Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/h8300/cpu.txt | 13 ++ .../memory-controllers/renesas,h8300-bsc.txt | 12 + arch/h8300/kernel/setup.c | 255 +++++++++++++++++++++ 3 files changed, 280 insertions(+) create mode 100644 Documentation/devicetree/bindings/h8300/cpu.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt create mode 100644 arch/h8300/kernel/setup.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/h8300/cpu.txt b/Documentation/devicetree/bindings/h8300/cpu.txt new file mode 100644 index 000000000000..70cd58608f4b --- /dev/null +++ b/Documentation/devicetree/bindings/h8300/cpu.txt @@ -0,0 +1,13 @@ +* H8/300 CPU bindings + +Required properties: + +- compatible: Compatible property value should be "renesas,h8300". +- clock-frequency: Contains the clock frequency for CPU, in Hz. + +Example: + + cpu@0 { + compatible = "renesas,h8300"; + clock-frequency = <20000000>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt b/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt new file mode 100644 index 000000000000..cdf406c902e2 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.txt @@ -0,0 +1,12 @@ +* H8/300 bus controller + +Required properties: + - compatible: Must be "renesas,h8300-bsc". + - reg: Base address and length of BSC registers. + +Example. + bsc: memory-controller@fee01e { + compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; + reg = <0xfee01e 8>; + }; + diff --git a/arch/h8300/kernel/setup.c b/arch/h8300/kernel/setup.c new file mode 100644 index 000000000000..0fd1fe65c0b8 --- /dev/null +++ b/arch/h8300/kernel/setup.c @@ -0,0 +1,255 @@ +/* + * linux/arch/h8300/kernel/setup.c + * + * Copyright (C) 2001-2014 Yoshinori Sato + */ + +/* + * This file handles the architecture-dependent parts of system setup + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#if defined(CONFIG_CPU_H8300H) +#define CPU "H8/300H" +#elif defined(CONFIG_CPU_H8S) +#define CPU "H8S" +#else +#define CPU "Unknown" +#endif + +unsigned long memory_start; +unsigned long memory_end; +EXPORT_SYMBOL(memory_end); +static unsigned long freq; +extern char __dtb_start[]; + +#ifdef CONFIG_VT +struct screen_info screen_info; +#endif + +char __initdata command_line[COMMAND_LINE_SIZE]; + +void sim_console_register(void); + +void __init h8300_fdt_init(void *fdt, char *bootargs) +{ + if (!fdt) + fdt = __dtb_start; + else + strcpy(command_line, bootargs); + + early_init_dt_scan(fdt); + memblock_allow_resize(); +} + +static void __init bootmem_init(void) +{ + int bootmap_size; + unsigned long ram_start_pfn; + unsigned long free_ram_start_pfn; + unsigned long ram_end_pfn; + struct memblock_region *region; + + memory_end = memory_start = 0; + + /* Find main memory where is the kernel */ + for_each_memblock(memory, region) { + memory_start = region->base; + memory_end = region->base + region->size; + } + + if (!memory_end) + panic("No memory!"); + + ram_start_pfn = PFN_UP(memory_start); + /* free_ram_start_pfn is first page after kernel */ + free_ram_start_pfn = PFN_UP(__pa(_end)); + ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM()); + + max_pfn = ram_end_pfn; + + /* + * give all the memory to the bootmap allocator, tell it to put the + * boot mem_map at the start of memory + */ + bootmap_size = init_bootmem_node(NODE_DATA(0), + free_ram_start_pfn, + 0, + ram_end_pfn); + /* + * free the usable memory, we have to make sure we do not free + * the bootmem bitmap so we then reserve it after freeing it :-) + */ + free_bootmem(PFN_PHYS(free_ram_start_pfn), + (ram_end_pfn - free_ram_start_pfn) << PAGE_SHIFT); + reserve_bootmem(PFN_PHYS(free_ram_start_pfn), bootmap_size, + BOOTMEM_DEFAULT); + + for_each_memblock(reserved, region) { + reserve_bootmem(region->base, region->size, BOOTMEM_DEFAULT); + } +} + +void __init setup_arch(char **cmdline_p) +{ + unflatten_and_copy_device_tree(); + + init_mm.start_code = (unsigned long) _stext; + init_mm.end_code = (unsigned long) _etext; + init_mm.end_data = (unsigned long) _edata; + init_mm.brk = (unsigned long) 0; + + pr_notice("\r\n\nuClinux " CPU "\n"); + pr_notice("Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne\n"); + + if (*command_line) + strcpy(boot_command_line, command_line); + *cmdline_p = boot_command_line; + + parse_early_param(); + + bootmem_init(); +#if defined(CONFIG_H8300H_SIM) || defined(CONFIG_H8S_SIM) + sim_console_register(); +#endif + + early_platform_driver_probe("earlyprintk", 1, 0); + /* + * get kmalloc into gear + */ + paging_init(); +} + +/* + * Get CPU information for use by the procfs. + */ + +static int show_cpuinfo(struct seq_file *m, void *v) +{ + char *cpu; + + cpu = CPU; + + seq_printf(m, "CPU:\t\t%s\n" + "Clock:\t\t%lu.%1luMHz\n" + "BogoMips:\t%lu.%02lu\n" + "Calibration:\t%lu loops\n", + cpu, + freq/1000, freq%1000, + (loops_per_jiffy*HZ)/500000, + ((loops_per_jiffy*HZ)/5000)%100, + (loops_per_jiffy*HZ)); + + return 0; +} + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < num_possible_cpus() ? + ((void *) 0x12345678) : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return c_start(m, pos); +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +const struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; + +static int __init device_probe(void) +{ + of_platform_populate(NULL, NULL, NULL, NULL); + + return 0; +} + +device_initcall(device_probe); + +#if defined(CONFIG_CPU_H8300H) +#define get_wait(base, addr) ({ \ + int baddr; \ + baddr = ((addr) / 0x200000 * 2); \ + w *= (ctrl_inw((unsigned long)(base) + 2) & (3 << baddr)) + 1; \ + }) +#endif +#if defined(CONFIG_CPU_H8S) +#define get_wait(base, addr) ({ \ + int baddr; \ + baddr = ((addr) / 0x200000 * 16); \ + w *= (ctrl_inl((unsigned long)(base) + 2) & (7 << baddr)) + 1; \ + }) +#endif + +static __init int access_timing(void) +{ + struct device_node *bsc; + void __iomem *base; + unsigned long addr = (unsigned long)&__delay; + int bit = 1 << (addr / 0x200000); + int w; + + bsc = of_find_compatible_node(NULL, NULL, "renesas,h8300-bsc"); + base = of_iomap(bsc, 0); + w = (ctrl_inb((unsigned long)base + 0) & bit)?2:1; + if (ctrl_inb((unsigned long)base + 1) & bit) + w *= get_wait(base, addr); + else + w *= 2; + return w * 3 / 2; +} + +void __init calibrate_delay(void) +{ + struct device_node *cpu; + int freq; + + cpu = of_find_compatible_node(NULL, NULL, "renesas,h8300"); + of_property_read_s32(cpu, "clock-frequency", &freq); + loops_per_jiffy = freq / HZ / (access_timing() * 2); + pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n", + loops_per_jiffy / (500000 / HZ), + (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy); +} + + +void __init time_init(void) +{ + of_clk_init(NULL); +} -- cgit v1.2.3 From 7b5bb891a6e44bd18bd8661ede2e09ccae258ef5 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Fri, 8 May 2015 23:31:57 +0900 Subject: h8300: clock driver Signed-off-by: Yoshinori Sato --- .../bindings/clock/renesas,h8300-div-clock.txt | 24 ++++ .../bindings/clock/renesas,h8s2678-pll-clock.txt | 23 ++++ drivers/clk/Makefile | 1 + drivers/clk/h8300/Makefile | 2 + drivers/clk/h8300/clk-div.c | 53 ++++++++ drivers/clk/h8300/clk-h8s2678.c | 147 +++++++++++++++++++++ 6 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt create mode 100644 drivers/clk/h8300/Makefile create mode 100644 drivers/clk/h8300/clk-div.c create mode 100644 drivers/clk/h8300/clk-h8s2678.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt new file mode 100644 index 000000000000..36c2b528245c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt @@ -0,0 +1,24 @@ +* Renesas H8/300 divider clock + +Required Properties: + + - compatible: Must be "renesas,sh73a0-h8300-div-clock" + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - reg: Base address and length of the divide rate selector + + - renesas,width: bit width of selector + +Example +------- + + cclk: cclk { + compatible = "renesas,h8300-div-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee01b 2>; + renesas,width = <2>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt new file mode 100644 index 000000000000..500cdadbceb7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt @@ -0,0 +1,23 @@ +Renesas H8S2678 PLL clock + +This device is Clock multiplyer + +Required Properties: + + - compatible: Must be "renesas,h8s2678-pll-clock" + + - clocks: Reference to the parent clocks + + - #clock-cells: Must be 0 + + - reg: Two rate selector (Multiply / Divide) register address + +Example +------- + + pllclk: pllclk { + compatible = "renesas,h8s2678-pll-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee03b 2>, <0xfee045 2>; + }; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 3d00c25382c5..9df871d53c6e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -73,3 +73,4 @@ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_X86) += x86/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ +obj-$(CONFIG_H8300) += h8300/ diff --git a/drivers/clk/h8300/Makefile b/drivers/clk/h8300/Makefile new file mode 100644 index 000000000000..b86427c31fca --- /dev/null +++ b/drivers/clk/h8300/Makefile @@ -0,0 +1,2 @@ +obj-y += clk-div.o +obj-$(CONFIG_H8S2678) += clk-h8s2678.o diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c new file mode 100644 index 000000000000..56f9eba91b83 --- /dev/null +++ b/drivers/clk/h8300/clk-div.c @@ -0,0 +1,53 @@ +/* + * H8/300 divide clock driver + * + * Copyright 2015 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(clklock); + +static void __init h8300_div_clk_setup(struct device_node *node) +{ + unsigned int num_parents; + struct clk *clk; + const char *clk_name = node->name; + const char *parent_name; + void __iomem *divcr = NULL; + int width; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 1) { + pr_err("%s: no parent found", clk_name); + return; + } + + divcr = of_iomap(node, 0); + if (divcr == NULL) { + pr_err("%s: failed to map divide register", clk_name); + goto error; + } + + parent_name = of_clk_get_parent_name(node, 0); + of_property_read_u32(node, "renesas,width", &width); + clk = clk_register_divider(NULL, clk_name, parent_name, + CLK_SET_RATE_GATE, divcr, 0, width, + CLK_DIVIDER_POWER_OF_TWO, &clklock); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + } + pr_err("%s: failed to register %s div clock (%ld)\n", + __func__, clk_name, PTR_ERR(clk)); +error: + if (divcr) + iounmap(divcr); +} + +CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup); diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c new file mode 100644 index 000000000000..4de7ee534bfc --- /dev/null +++ b/drivers/clk/h8300/clk-h8s2678.c @@ -0,0 +1,147 @@ +/* + * H8S2678 clock driver + * + * Copyright 2015 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(clklock); + +#define MAX_FREQ 33333333 +#define MIN_FREQ 8000000 + +struct pll_clock { + struct clk_hw hw; + void __iomem *sckcr; + void __iomem *pllcr; +}; + +#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw) + +static unsigned long pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clock *pll_clock = to_pll_clock(hw); + int mul = 1 << (ctrl_inb((unsigned long)pll_clock->pllcr) & 3); + + return parent_rate * mul; +} + +static long pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + int i, m = -1; + long offset[3]; + + if (rate > MAX_FREQ) + rate = MAX_FREQ; + if (rate < MIN_FREQ) + rate = MIN_FREQ; + + for (i = 0; i < 3; i++) + offset[i] = abs(rate - (*prate * (1 << i))); + for (i = 0; i < 3; i++) + if (m < 0) + m = i; + else + m = (offset[i] < offset[m])?i:m; + + return *prate * (1 << m); +} + +static int pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int pll; + unsigned char val; + unsigned long flags; + struct pll_clock *pll_clock = to_pll_clock(hw); + + pll = ((rate / parent_rate) / 2) & 0x03; + spin_lock_irqsave(&clklock, flags); + val = ctrl_inb((unsigned long)pll_clock->sckcr); + val |= 0x08; + ctrl_outb(val, (unsigned long)pll_clock->sckcr); + val = ctrl_inb((unsigned long)pll_clock->pllcr); + val &= ~0x03; + val |= pll; + ctrl_outb(val, (unsigned long)pll_clock->pllcr); + spin_unlock_irqrestore(&clklock, flags); + return 0; +} + +static const struct clk_ops pll_ops = { + .recalc_rate = pll_recalc_rate, + .round_rate = pll_round_rate, + .set_rate = pll_set_rate, +}; + +static void __init h8s2678_pll_clk_setup(struct device_node *node) +{ + unsigned int num_parents; + struct clk *clk; + const char *clk_name = node->name; + const char *parent_name; + struct pll_clock *pll_clock; + struct clk_init_data init; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 1) { + pr_err("%s: no parent found", clk_name); + return; + } + + + pll_clock = kzalloc(sizeof(struct pll_clock), GFP_KERNEL); + if (!pll_clock) { + pr_err("%s: failed to alloc memory", clk_name); + return; + } + + pll_clock->sckcr = of_iomap(node, 0); + if (pll_clock->sckcr == NULL) { + pr_err("%s: failed to map divide register", clk_name); + goto error; + } + + pll_clock->pllcr = of_iomap(node, 1); + if (pll_clock->pllcr == NULL) { + pr_err("%s: failed to map multiply register", clk_name); + goto error; + } + + parent_name = of_clk_get_parent_name(node, 0); + init.name = clk_name; + init.ops = &pll_ops; + init.flags = CLK_IS_BASIC; + init.parent_names = &parent_name; + init.num_parents = 1; + pll_clock->hw.init = &init; + + clk = clk_register(NULL, &pll_clock->hw); + if (IS_ERR(clk)) + kfree(pll_clock); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + } + pr_err("%s: failed to register %s div clock (%ld)\n", + __func__, clk_name, PTR_ERR(clk)); +error: + if (pll_clock) { + if (pll_clock->sckcr) + iounmap(pll_clock->sckcr); + if (pll_clock->pllcr) + iounmap(pll_clock->pllcr); + kfree(pll_clock); + } +} + +CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock", + h8s2678_pll_clk_setup); -- cgit v1.2.3 From 618b902d8c098f2fff188119da7b3184c4bc5483 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Wed, 28 Jan 2015 02:52:42 +0900 Subject: h8300: clocksource h8300_timer8: 8bit clockevent device h8300_timer16 / h8300_tpu: 16bit clocksource Signed-off-by: Yoshinori Sato --- .../bindings/timer/renesas,16bit-timer.txt | 25 ++ .../bindings/timer/renesas,8bit-timer.txt | 25 ++ .../devicetree/bindings/timer/renesas,tpu.txt | 21 ++ drivers/clocksource/Kconfig | 7 + drivers/clocksource/Makefile | 3 + drivers/clocksource/h8300_timer16.c | 254 +++++++++++++++++ drivers/clocksource/h8300_timer8.c | 313 +++++++++++++++++++++ drivers/clocksource/h8300_tpu.c | 207 ++++++++++++++ 8 files changed, 855 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/renesas,tpu.txt create mode 100644 drivers/clocksource/h8300_timer16.c create mode 100644 drivers/clocksource/h8300_timer8.c create mode 100644 drivers/clocksource/h8300_tpu.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt b/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt new file mode 100644 index 000000000000..e8792447a199 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,16bit-timer.txt @@ -0,0 +1,25 @@ +* Renesas H8/300 16bit timer + +The 16bit timer is a 16bit timer/counter with configurable clock inputs and +programmable compare match. + +Required Properties: + + - compatible: must contain "renesas,16bit-timer" + - reg: base address and length of the registers block for the timer module. + - interrupts: interrupt-specifier for the timer, IMIA + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "peripheral_clk" for the functional clock. + - renesas,channel: timer channel number. + +Example: + + timer16: timer@ffff68 { + compatible = "reneas,16bit-timer"; + reg = <0xffff68 8>, <0xffff60 8>; + interrupts = <24>; + renesas,channel = <0>; + clocks = <&pclk>; + clock-names = "peripheral_clk"; + }; + diff --git a/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt b/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt new file mode 100644 index 000000000000..9dca3759a0f0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,8bit-timer.txt @@ -0,0 +1,25 @@ +* Renesas H8/300 8bit timer + +The 8bit timer is a 8bit timer/counter with configurable clock inputs and +programmable compare match. + +This implement only supported cascade mode. + +Required Properties: + + - compatible: must contain "renesas,8bit-timer" + - reg: base address and length of the registers block for the timer module. + - interrupts: interrupt-specifier for the timer, CMIA and TOVI + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "fck" for the functional clock. + +Example: + + timer8_0: timer@ffff80 { + compatible = "renesas,8bit-timer"; + reg = <0xffff80 10>; + interrupts = <36>; + clocks = <&fclk>; + clock-names = "fck"; + }; + diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.txt b/Documentation/devicetree/bindings/timer/renesas,tpu.txt new file mode 100644 index 000000000000..f8b25897fb31 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/renesas,tpu.txt @@ -0,0 +1,21 @@ +* Renesas H8/300 Timer Pluse Unit + +The TPU is a 16bit timer/counter with configurable clock inputs and +programmable compare match. +This implementation support only cascade mode. + +Required Properties: + + - compatible: must contain "renesas,tpu" + - reg: base address and length of the registers block in 2 channel. + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "peripheral_clk" for the functional clock. + + +Example: + tpu: tpu@ffffe0 { + compatible = "renesas,tpu"; + reg = <0xffffe0 16>, <0xfffff0 12>; + clocks = <&pclk>; + clock-names = "peripheral_clk"; + }; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 51d7865fdddb..acce7cfb3cee 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -258,4 +258,11 @@ config CLKSRC_PXA help This enables OST0 support available on PXA and SA-11x0 platforms. + +config H8300_TMR16 + bool + +config H8300_TPU + bool + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5b85f6adb258..8288c4eea802 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -52,3 +52,6 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o +obj-$(CONFIG_H8300) += h8300_timer8.o +obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o +obj-$(CONFIG_H8300_TPU) += h8300_tpu.o diff --git a/drivers/clocksource/h8300_timer16.c b/drivers/clocksource/h8300_timer16.c new file mode 100644 index 000000000000..82941c1e9e33 --- /dev/null +++ b/drivers/clocksource/h8300_timer16.c @@ -0,0 +1,254 @@ +/* + * H8/300 16bit Timer driver + * + * Copyright 2015 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TSTR 0 +#define TSNC 1 +#define TMDR 2 +#define TOLR 3 +#define TISRA 4 +#define TISRB 5 +#define TISRC 6 + +#define TCR 0 +#define TIOR 1 +#define TCNT 2 +#define GRA 4 +#define GRB 6 + +#define FLAG_REPROGRAM (1 << 0) +#define FLAG_SKIPEVENT (1 << 1) +#define FLAG_IRQCONTEXT (1 << 2) +#define FLAG_STARTED (1 << 3) + +#define ONESHOT 0 +#define PERIODIC 1 + +#define RELATIVE 0 +#define ABSOLUTE 1 + +struct timer16_priv { + struct platform_device *pdev; + struct clocksource cs; + struct irqaction irqaction; + unsigned long total_cycles; + unsigned long mapbase; + unsigned long mapcommon; + unsigned long flags; + unsigned short gra; + unsigned short cs_enabled; + unsigned char enb; + unsigned char imfa; + unsigned char imiea; + unsigned char ovf; + raw_spinlock_t lock; + struct clk *clk; +}; + +static unsigned long timer16_get_counter(struct timer16_priv *p) +{ + unsigned long v1, v2, v3; + int o1, o2; + + o1 = ctrl_inb(p->mapcommon + TISRC) & p->ovf; + + /* Make sure the timer value is stable. Stolen from acpi_pm.c */ + do { + o2 = o1; + v1 = ctrl_inw(p->mapbase + TCNT); + v2 = ctrl_inw(p->mapbase + TCNT); + v3 = ctrl_inw(p->mapbase + TCNT); + o1 = ctrl_inb(p->mapcommon + TISRC) & p->ovf; + } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) + || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); + + v2 |= 0x10000; + return v2; +} + + +static irqreturn_t timer16_interrupt(int irq, void *dev_id) +{ + struct timer16_priv *p = (struct timer16_priv *)dev_id; + + ctrl_outb(ctrl_inb(p->mapcommon + TISRA) & ~p->imfa, + p->mapcommon + TISRA); + p->total_cycles += 0x10000; + + return IRQ_HANDLED; +} + +static inline struct timer16_priv *cs_to_priv(struct clocksource *cs) +{ + return container_of(cs, struct timer16_priv, cs); +} + +static cycle_t timer16_clocksource_read(struct clocksource *cs) +{ + struct timer16_priv *p = cs_to_priv(cs); + unsigned long flags, raw; + unsigned long value; + + raw_spin_lock_irqsave(&p->lock, flags); + value = p->total_cycles; + raw = timer16_get_counter(p); + raw_spin_unlock_irqrestore(&p->lock, flags); + + return value + raw; +} + +static int timer16_enable(struct clocksource *cs) +{ + struct timer16_priv *p = cs_to_priv(cs); + + WARN_ON(p->cs_enabled); + + p->total_cycles = 0; + ctrl_outw(0x0000, p->mapbase + TCNT); + ctrl_outb(0x83, p->mapbase + TCR); + ctrl_outb(ctrl_inb(p->mapcommon + TSTR) | p->enb, + p->mapcommon + TSTR); + + p->cs_enabled = true; + return 0; +} + +static void timer16_disable(struct clocksource *cs) +{ + struct timer16_priv *p = cs_to_priv(cs); + + WARN_ON(!p->cs_enabled); + + ctrl_outb(ctrl_inb(p->mapcommon + TSTR) & ~p->enb, + p->mapcommon + TSTR); + + p->cs_enabled = false; +} + +#define REG_CH 0 +#define REG_COMM 1 + +static int timer16_setup(struct timer16_priv *p, struct platform_device *pdev) +{ + struct resource *res[2]; + int ret, irq; + unsigned int ch; + + memset(p, 0, sizeof(*p)); + p->pdev = pdev; + + res[REG_CH] = platform_get_resource(p->pdev, + IORESOURCE_MEM, REG_CH); + res[REG_COMM] = platform_get_resource(p->pdev, + IORESOURCE_MEM, REG_COMM); + if (!res[REG_CH] || !res[REG_COMM]) { + dev_err(&p->pdev->dev, "failed to get I/O memory\n"); + return -ENXIO; + } + irq = platform_get_irq(p->pdev, 0); + if (irq < 0) { + dev_err(&p->pdev->dev, "failed to get irq\n"); + return irq; + } + + p->clk = clk_get(&p->pdev->dev, "fck"); + if (IS_ERR(p->clk)) { + dev_err(&p->pdev->dev, "can't get clk\n"); + return PTR_ERR(p->clk); + } + of_property_read_u32(p->pdev->dev.of_node, "renesas,channel", &ch); + + p->pdev = pdev; + p->mapbase = res[REG_CH]->start; + p->mapcommon = res[REG_COMM]->start; + p->enb = 1 << ch; + p->imfa = 1 << ch; + p->imiea = 1 << (4 + ch); + p->cs.name = pdev->name; + p->cs.rating = 200; + p->cs.read = timer16_clocksource_read; + p->cs.enable = timer16_enable; + p->cs.disable = timer16_disable; + p->cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); + p->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + ret = request_irq(irq, timer16_interrupt, + IRQF_TIMER, pdev->name, p); + if (ret < 0) { + dev_err(&p->pdev->dev, "failed to request irq %d\n", irq); + return ret; + } + + clocksource_register_hz(&p->cs, clk_get_rate(p->clk) / 8); + + return 0; +} + +static int timer16_probe(struct platform_device *pdev) +{ + struct timer16_priv *p = platform_get_drvdata(pdev); + + if (p) { + dev_info(&pdev->dev, "kept as earlytimer\n"); + return 0; + } + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + return timer16_setup(p, pdev); +} + +static int timer16_remove(struct platform_device *pdev) +{ + return -EBUSY; +} + +static const struct of_device_id timer16_of_table[] = { + { .compatible = "renesas,16bit-timer" }, + { } +}; +static struct platform_driver timer16_driver = { + .probe = timer16_probe, + .remove = timer16_remove, + .driver = { + .name = "h8300h-16timer", + .of_match_table = of_match_ptr(timer16_of_table), + } +}; + +static int __init timer16_init(void) +{ + return platform_driver_register(&timer16_driver); +} + +static void __exit timer16_exit(void) +{ + platform_driver_unregister(&timer16_driver); +} + +subsys_initcall(timer16_init); +module_exit(timer16_exit); +MODULE_AUTHOR("Yoshinori Sato"); +MODULE_DESCRIPTION("H8/300H 16bit Timer Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clocksource/h8300_timer8.c b/drivers/clocksource/h8300_timer8.c new file mode 100644 index 000000000000..1c6f8b935a7b --- /dev/null +++ b/drivers/clocksource/h8300_timer8.c @@ -0,0 +1,313 @@ +/* + * linux/arch/h8300/kernel/cpu/timer/timer8.c + * + * Yoshinori Sato + * + * 8bit Timer driver + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define _8TCR 0 +#define _8TCSR 2 +#define TCORA 4 +#define TCORB 6 +#define _8TCNT 8 + +#define FLAG_REPROGRAM (1 << 0) +#define FLAG_SKIPEVENT (1 << 1) +#define FLAG_IRQCONTEXT (1 << 2) +#define FLAG_STARTED (1 << 3) + +#define ONESHOT 0 +#define PERIODIC 1 + +#define RELATIVE 0 +#define ABSOLUTE 1 + +struct timer8_priv { + struct platform_device *pdev; + struct clock_event_device ced; + struct irqaction irqaction; + unsigned long mapbase; + raw_spinlock_t lock; + unsigned long flags; + unsigned int rate; + unsigned int tcora; + struct clk *pclk; +}; + +static unsigned long timer8_get_counter(struct timer8_priv *p) +{ + unsigned long v1, v2, v3; + int o1, o2; + + o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20; + + /* Make sure the timer value is stable. Stolen from acpi_pm.c */ + do { + o2 = o1; + v1 = ctrl_inw(p->mapbase + _8TCNT); + v2 = ctrl_inw(p->mapbase + _8TCNT); + v3 = ctrl_inw(p->mapbase + _8TCNT); + o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20; + } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) + || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); + + v2 |= o1 << 10; + return v2; +} + +static irqreturn_t timer8_interrupt(int irq, void *dev_id) +{ + struct timer8_priv *p = dev_id; + + ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40, + p->mapbase + _8TCSR); + p->flags |= FLAG_IRQCONTEXT; + ctrl_outw(p->tcora, p->mapbase + TCORA); + if (!(p->flags & FLAG_SKIPEVENT)) { + if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) + ctrl_outw(0x0000, p->mapbase + _8TCR); + p->ced.event_handler(&p->ced); + } + p->flags &= ~(FLAG_SKIPEVENT | FLAG_IRQCONTEXT); + + return IRQ_HANDLED; +} + +static void timer8_set_next(struct timer8_priv *p, unsigned long delta) +{ + unsigned long flags; + unsigned long now; + + raw_spin_lock_irqsave(&p->lock, flags); + if (delta >= 0x10000) + dev_warn(&p->pdev->dev, "delta out of range\n"); + now = timer8_get_counter(p); + p->tcora = delta; + ctrl_outb(ctrl_inb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR); + if (delta > now) + ctrl_outw(delta, p->mapbase + TCORA); + else + ctrl_outw(now + 1, p->mapbase + TCORA); + + raw_spin_unlock_irqrestore(&p->lock, flags); +} + +static int timer8_enable(struct timer8_priv *p) +{ + p->rate = clk_get_rate(p->pclk) / 64; + ctrl_outw(0xffff, p->mapbase + TCORA); + ctrl_outw(0x0000, p->mapbase + _8TCNT); + ctrl_outw(0x0c02, p->mapbase + _8TCR); + + return 0; +} + +static int timer8_start(struct timer8_priv *p) +{ + int ret = 0; + unsigned long flags; + + raw_spin_lock_irqsave(&p->lock, flags); + + if (!(p->flags & FLAG_STARTED)) + ret = timer8_enable(p); + + if (ret) + goto out; + p->flags |= FLAG_STARTED; + + out: + raw_spin_unlock_irqrestore(&p->lock, flags); + + return ret; +} + +static void timer8_stop(struct timer8_priv *p) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&p->lock, flags); + + ctrl_outw(0x0000, p->mapbase + _8TCR); + + raw_spin_unlock_irqrestore(&p->lock, flags); +} + +static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced) +{ + return container_of(ced, struct timer8_priv, ced); +} + +static void timer8_clock_event_start(struct timer8_priv *p, int periodic) +{ + struct clock_event_device *ced = &p->ced; + + timer8_start(p); + + ced->shift = 32; + ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); + ced->max_delta_ns = clockevent_delta2ns(0xffff, ced); + ced->min_delta_ns = clockevent_delta2ns(0x0001, ced); + + timer8_set_next(p, periodic?(p->rate + HZ/2) / HZ:0x10000); +} + +static void timer8_clock_event_mode(enum clock_event_mode mode, + struct clock_event_device *ced) +{ + struct timer8_priv *p = ced_to_priv(ced); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + dev_info(&p->pdev->dev, "used for periodic clock events\n"); + timer8_stop(p); + timer8_clock_event_start(p, PERIODIC); + break; + case CLOCK_EVT_MODE_ONESHOT: + dev_info(&p->pdev->dev, "used for oneshot clock events\n"); + timer8_stop(p); + timer8_clock_event_start(p, ONESHOT); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + timer8_stop(p); + break; + default: + break; + } +} + +static int timer8_clock_event_next(unsigned long delta, + struct clock_event_device *ced) +{ + struct timer8_priv *p = ced_to_priv(ced); + + BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); + timer8_set_next(p, delta - 1); + + return 0; +} + +static int timer8_setup(struct timer8_priv *p, + struct platform_device *pdev) +{ + struct resource *res; + int irq; + int ret; + + memset(p, 0, sizeof(*p)); + p->pdev = pdev; + + res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&p->pdev->dev, "failed to get I/O memory\n"); + return -ENXIO; + } + + irq = platform_get_irq(p->pdev, 0); + if (irq < 0) { + dev_err(&p->pdev->dev, "failed to get irq\n"); + return -ENXIO; + } + + p->mapbase = res->start; + + p->irqaction.name = dev_name(&p->pdev->dev); + p->irqaction.handler = timer8_interrupt; + p->irqaction.dev_id = p; + p->irqaction.flags = IRQF_TIMER; + + p->pclk = clk_get(&p->pdev->dev, "fck"); + if (IS_ERR(p->pclk)) { + dev_err(&p->pdev->dev, "can't get clk\n"); + return PTR_ERR(p->pclk); + } + + p->ced.name = pdev->name; + p->ced.features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT; + p->ced.rating = 200; + p->ced.cpumask = cpumask_of(0); + p->ced.set_next_event = timer8_clock_event_next; + p->ced.set_mode = timer8_clock_event_mode; + + ret = setup_irq(irq, &p->irqaction); + if (ret < 0) { + dev_err(&p->pdev->dev, + "failed to request irq %d\n", irq); + return ret; + } + clockevents_register_device(&p->ced); + platform_set_drvdata(pdev, p); + + return 0; +} + +static int timer8_probe(struct platform_device *pdev) +{ + struct timer8_priv *p = platform_get_drvdata(pdev); + + if (p) { + dev_info(&pdev->dev, "kept as earlytimer\n"); + return 0; + } + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + return timer8_setup(p, pdev); +} + +static int timer8_remove(struct platform_device *pdev) +{ + return -EBUSY; +} + +static const struct of_device_id timer8_of_table[] __maybe_unused = { + { .compatible = "renesas,8bit-timer" }, + { } +}; + +MODULE_DEVICE_TABLE(of, sh_cmt_of_table); +static struct platform_driver timer8_driver = { + .probe = timer8_probe, + .remove = timer8_remove, + .driver = { + .name = "h8300-8timer", + .of_match_table = of_match_ptr(timer8_of_table), + } +}; + +static int __init timer8_init(void) +{ + return platform_driver_register(&timer8_driver); +} + +static void __exit timer8_exit(void) +{ + platform_driver_unregister(&timer8_driver); +} + +subsys_initcall(timer8_init); +module_exit(timer8_exit); +MODULE_AUTHOR("Yoshinori Sato"); +MODULE_DESCRIPTION("H8/300 8bit Timer Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clocksource/h8300_tpu.c b/drivers/clocksource/h8300_tpu.c new file mode 100644 index 000000000000..64195fdd78bf --- /dev/null +++ b/drivers/clocksource/h8300_tpu.c @@ -0,0 +1,207 @@ +/* + * H8/300 TPU Driver + * + * Copyright 2015 Yoshinori Sato + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TCR 0 +#define TMDR 1 +#define TIOR 2 +#define TER 4 +#define TSR 5 +#define TCNT 6 +#define TGRA 8 +#define TGRB 10 +#define TGRC 12 +#define TGRD 14 + +struct tpu_priv { + struct platform_device *pdev; + struct clocksource cs; + struct clk *clk; + unsigned long mapbase1; + unsigned long mapbase2; + raw_spinlock_t lock; + unsigned int cs_enabled; +}; + +static inline unsigned long read_tcnt32(struct tpu_priv *p) +{ + unsigned long tcnt; + + tcnt = ctrl_inw(p->mapbase1 + TCNT) << 16; + tcnt |= ctrl_inw(p->mapbase2 + TCNT); + return tcnt; +} + +static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val) +{ + unsigned long v1, v2, v3; + int o1, o2; + + o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10; + + /* Make sure the timer value is stable. Stolen from acpi_pm.c */ + do { + o2 = o1; + v1 = read_tcnt32(p); + v2 = read_tcnt32(p); + v3 = read_tcnt32(p); + o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10; + } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) + || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); + + *val = v2; + return o1; +} + +static inline struct tpu_priv *cs_to_priv(struct clocksource *cs) +{ + return container_of(cs, struct tpu_priv, cs); +} + +static cycle_t tpu_clocksource_read(struct clocksource *cs) +{ + struct tpu_priv *p = cs_to_priv(cs); + unsigned long flags; + unsigned long long value; + + raw_spin_lock_irqsave(&p->lock, flags); + if (tpu_get_counter(p, &value)) + value += 0x100000000; + raw_spin_unlock_irqrestore(&p->lock, flags); + + return value; +} + +static int tpu_clocksource_enable(struct clocksource *cs) +{ + struct tpu_priv *p = cs_to_priv(cs); + + WARN_ON(p->cs_enabled); + + ctrl_outw(0, p->mapbase1 + TCNT); + ctrl_outw(0, p->mapbase2 + TCNT); + ctrl_outb(0x0f, p->mapbase1 + TCR); + ctrl_outb(0x03, p->mapbase2 + TCR); + + p->cs_enabled = true; + return 0; +} + +static void tpu_clocksource_disable(struct clocksource *cs) +{ + struct tpu_priv *p = cs_to_priv(cs); + + WARN_ON(!p->cs_enabled); + + ctrl_outb(0, p->mapbase1 + TCR); + ctrl_outb(0, p->mapbase2 + TCR); + p->cs_enabled = false; +} + +#define CH_L 0 +#define CH_H 1 + +static int __init tpu_setup(struct tpu_priv *p, struct platform_device *pdev) +{ + struct resource *res[2]; + + memset(p, 0, sizeof(*p)); + p->pdev = pdev; + + res[CH_L] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_L); + res[CH_H] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_H); + if (!res[CH_L] || !res[CH_H]) { + dev_err(&p->pdev->dev, "failed to get I/O memory\n"); + return -ENXIO; + } + + p->clk = clk_get(&p->pdev->dev, "fck"); + if (IS_ERR(p->clk)) { + dev_err(&p->pdev->dev, "can't get clk\n"); + return PTR_ERR(p->clk); + } + + p->mapbase1 = res[CH_L]->start; + p->mapbase2 = res[CH_H]->start; + + p->cs.name = pdev->name; + p->cs.rating = 200; + p->cs.read = tpu_clocksource_read; + p->cs.enable = tpu_clocksource_enable; + p->cs.disable = tpu_clocksource_disable; + p->cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); + p->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + clocksource_register_hz(&p->cs, clk_get_rate(p->clk) / 64); + platform_set_drvdata(pdev, p); + + return 0; +} + +static int tpu_probe(struct platform_device *pdev) +{ + struct tpu_priv *p = platform_get_drvdata(pdev); + + if (p) { + dev_info(&pdev->dev, "kept as earlytimer\n"); + return 0; + } + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + return tpu_setup(p, pdev); +} + +static int tpu_remove(struct platform_device *pdev) +{ + return -EBUSY; +} + +static const struct of_device_id tpu_of_table[] = { + { .compatible = "renesas,tpu" }, + { } +}; + +static struct platform_driver tpu_driver = { + .probe = tpu_probe, + .remove = tpu_remove, + .driver = { + .name = "h8s-tpu", + .of_match_table = of_match_ptr(tpu_of_table), + } +}; + +static int __init tpu_init(void) +{ + return platform_driver_register(&tpu_driver); +} + +static void __exit tpu_exit(void) +{ + platform_driver_unregister(&tpu_driver); +} + +subsys_initcall(tpu_init); +module_exit(tpu_exit); +MODULE_AUTHOR("Yoshinori Sato"); +MODULE_DESCRIPTION("H8S Timer Pulse Unit Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 8a7644821ae00b76e0c039f9128ee584dda146a8 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Sun, 10 May 2015 02:30:47 +0900 Subject: h8300: IRQ chip driver Signed-off-by: Yoshinori Sato --- .../interrupt-controller/renesas,h8300h-intc.txt | 22 +++++ .../interrupt-controller/renesas,h8s-intc.txt | 22 +++++ drivers/irqchip/Kconfig | 8 ++ drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-renesas-h8300h.c | 95 +++++++++++++++++++ drivers/irqchip/irq-renesas-h8s.c | 101 +++++++++++++++++++++ 6 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt create mode 100644 drivers/irqchip/irq-renesas-h8300h.c create mode 100644 drivers/irqchip/irq-renesas-h8s.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt new file mode 100644 index 000000000000..56e8d82aff34 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt @@ -0,0 +1,22 @@ +* H8/300H Interrupt controller + +Required properties: + +- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback. +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory +- regs: Base address of interrupt controller registers. + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties + +Example: + + h8intc: interrupt-controller@fee012 { + compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfee012 7>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt new file mode 100644 index 000000000000..faded2b1559b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt @@ -0,0 +1,22 @@ +* H8S Interrupt controller + +Required properties: + +- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback. +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory +- regs: Base address of interrupt controller registers. + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties + +Example: + + h8intc: interrupt-controller@fffe00 { + compatible = "renesas,h8s-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfffe00 24>; + }; diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 6de62a96e79c..998681587d1e 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -158,3 +158,11 @@ config KEYSTONE_IRQ config MIPS_GIC bool select MIPS_CM + +config RENESAS_H8300H_INTC + bool + select IRQ_DOMAIN + +config RENESAS_H8S_INTC + bool + select IRQ_DOMAIN \ No newline at end of file diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index dda4927e47a6..f8efb7087760 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -47,3 +47,5 @@ obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o +obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o +obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o diff --git a/drivers/irqchip/irq-renesas-h8300h.c b/drivers/irqchip/irq-renesas-h8300h.c new file mode 100644 index 000000000000..1870e6bd3dd9 --- /dev/null +++ b/drivers/irqchip/irq-renesas-h8300h.c @@ -0,0 +1,95 @@ +/* + * H8/300H interrupt controller driver + * + * Copyright 2015 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include + +#include "irqchip.h" + +static const char ipr_bit[] = { + 7, 6, 5, 5, + 4, 4, 4, 4, 3, 3, 3, 3, + 2, 2, 2, 2, 1, 1, 1, 1, + 0, 0, 0, 0, 15, 15, 15, 15, + 14, 14, 14, 14, 13, 13, 13, 13, + -1, -1, -1, -1, 11, 11, 11, 11, + 10, 10, 10, 10, 9, 9, 9, 9, +}; + +static void *intc_baseaddr; + +#define IPR ((unsigned long)intc_baseaddr + 6) + +static void h8300h_disable_irq(struct irq_data *data) +{ + int bit; + int irq = data->irq - 12; + + bit = ipr_bit[irq]; + if (bit >= 0) { + if (bit < 8) + ctrl_bclr(bit & 7, IPR); + else + ctrl_bclr(bit & 7, (IPR+1)); + } +} + +static void h8300h_enable_irq(struct irq_data *data) +{ + int bit; + int irq = data->irq - 12; + + bit = ipr_bit[irq]; + if (bit >= 0) { + if (bit < 8) + ctrl_bset(bit & 7, IPR); + else + ctrl_bset(bit & 7, (IPR+1)); + } +} + +struct irq_chip h8300h_irq_chip = { + .name = "H8/300H-INTC", + .irq_enable = h8300h_enable_irq, + .irq_disable = h8300h_disable_irq, +}; + +static int irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &h8300h_irq_chip, handle_simple_irq); + + return 0; +} + +static struct irq_domain_ops irq_ops = { + .map = irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init h8300h_intc_of_init(struct device_node *intc, + struct device_node *parent) +{ + struct irq_domain *domain; + + intc_baseaddr = of_iomap(intc, 0); + BUG_ON(!intc_baseaddr); + + /* All interrupt priority low */ + ctrl_outb(0x00, IPR + 0); + ctrl_outb(0x00, IPR + 1); + + domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL); + BUG_ON(!domain); + irq_set_default_host(domain); + return 0; +} + +IRQCHIP_DECLARE(h8300h_intc, "renesas,h8300h-intc", h8300h_intc_of_init); diff --git a/drivers/irqchip/irq-renesas-h8s.c b/drivers/irqchip/irq-renesas-h8s.c new file mode 100644 index 000000000000..64425f4de7d9 --- /dev/null +++ b/drivers/irqchip/irq-renesas-h8s.c @@ -0,0 +1,101 @@ +/* + * H8S interrupt contoller driver + * + * Copyright 2015 Yoshinori Sato + */ + +#include +#include +#include +#include +#include "irqchip.h" + +static void *intc_baseaddr; +#define IPRA ((unsigned long)intc_baseaddr) + +static const unsigned char ipr_table[] = { + 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */ + 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */ + 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */ + 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */ + 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */ + 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */ + 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */ + 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */ + 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */ + 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */ + 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */ + 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */ + 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */ + 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */ +}; + +static void h8s_disable_irq(struct irq_data *data) +{ + int pos; + unsigned int addr; + unsigned short pri; + int irq = data->irq; + + addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3); + pos = (ipr_table[irq - 16] & 0x0f) * 4; + pri = ~(0x000f << pos); + pri &= ctrl_inw(addr); + ctrl_outw(pri, addr); +} + +static void h8s_enable_irq(struct irq_data *data) +{ + int pos; + unsigned int addr; + unsigned short pri; + int irq = data->irq; + + addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3); + pos = (ipr_table[irq - 16] & 0x0f) * 4; + pri = ~(0x000f << pos); + pri &= ctrl_inw(addr); + pri |= 1 << pos; + ctrl_outw(pri, addr); +} + +struct irq_chip h8s_irq_chip = { + .name = "H8S-INTC", + .irq_enable = h8s_enable_irq, + .irq_disable = h8s_disable_irq, +}; + +static __init int irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq); + + return 0; +} + +static struct irq_domain_ops irq_ops = { + .map = irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init h8s_intc_of_init(struct device_node *intc, + struct device_node *parent) +{ + struct irq_domain *domain; + int n; + + intc_baseaddr = of_iomap(intc, 0); + BUG_ON(!intc_baseaddr); + + /* All interrupt priority is 0 (disable) */ + /* IPRA to IPRK */ + for (n = 0; n <= 'k' - 'a'; n++) + ctrl_outw(0x0000, IPRA + (n * 2)); + + domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL); + BUG_ON(!domain); + irq_set_default_host(domain); + return 0; +} + +IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init); -- cgit v1.2.3 From f76a28c24c8cda765aa0da2abe4eb3899054e61f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 18 Jun 2015 16:27:20 +0200 Subject: net/macb: bindings doc: fix compatibility string In the driver and the DT bindings we use the "atmel" prefix. Fix it in the binding documentation. Signed-off-by: Nicolas Ferre Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 8ec5fdf444e9..0ae6974383d7 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -7,8 +7,8 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem". - Use "cdns,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. - Use "cdns,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs. + Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. + Use "atmel,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt -- cgit v1.2.3 From f58393f4a2f78002f9003b501d0d5fb2d00c49a8 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 18 Jun 2015 16:27:21 +0200 Subject: net/macb: bindings doc/trivial: fix sama5d4 comment On sama5d4, we only have a GEM IP that is configured to do 10/100 Mbits. So the use of "Gigabit" can be confusing. Signed-off-by: Nicolas Ferre Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 0ae6974383d7..97349e3f3ff2 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -8,7 +8,7 @@ Required properties: Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem". Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. - Use "atmel,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs. + Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt -- cgit v1.2.3 From bb7506c92971a4042d734db183d1a07bcf9a979f Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 18 Jun 2015 16:27:22 +0200 Subject: net/macb: bindings doc: add sama5d2 compatibility sting Add sama5d2 to the biding documentation for this use of the GEM IP. Signed-off-by: Nicolas Ferre Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 97349e3f3ff2..b5d79761ac97 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -7,6 +7,7 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem". + Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs. Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. -- cgit v1.2.3 From 36f95a0b34cb980dcfff9c1082ca5d8f0dc5e78b Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Tue, 23 Jun 2015 17:08:21 +0800 Subject: doc:md: fix typo in md.txt. Signed-off-by: Wei Fang Signed-off-by: Jonathan Corbet --- Documentation/md.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/md.txt b/Documentation/md.txt index f925666e4342..1a2ada46aaed 100644 --- a/Documentation/md.txt +++ b/Documentation/md.txt @@ -549,7 +549,7 @@ also have sync_speed_max This are similar to /proc/sys/dev/raid/speed_limit_{min,max} however they only apply to the particular array. - If no value has been written to these, of if the word 'system' + If no value has been written to these, or if the word 'system' is written, then the system-wide value is used. If a value, in kibibytes-per-second is written, then it is used. When the files are read, they show the currently active value -- cgit v1.2.3 From df558854cfb3123267b5b15e7b7f4bb900bb7782 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sun, 21 Jun 2015 21:52:54 +0200 Subject: net: stmmac: dwmac-rk: add rk3368-specific data Add constants and callback functions for the dwmac on rk3368 socs. As can be seen, the base structure is the same, only registers and the bits in them moved slightly. Signed-off-by: Heiko Stuebner Signed-off-by: David S. Miller --- .../devicetree/bindings/net/rockchip-dwmac.txt | 2 +- drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 126 +++++++++++++++++++++ 2 files changed, 127 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt index 21fd199e89b5..93eac7ce1446 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt @@ -3,7 +3,7 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC) The device node has following properties. Required properties: - - compatible: Can be "rockchip,rk3288-gmac". + - compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac" - reg: addresses and length of the register sets for the device. - interrupts: Should contain the GMAC interrupts. - interrupt-names: Should contain the interrupt names "macirq". diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index 65afca69d42f..00a1e1e09d4f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -184,6 +184,118 @@ struct rk_gmac_ops rk3288_ops = { .set_rmii_speed = rk3288_set_rmii_speed, }; +#define RK3368_GRF_SOC_CON15 0x043c +#define RK3368_GRF_SOC_CON16 0x0440 + +/* RK3368_GRF_SOC_CON15 */ +#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ + GRF_CLR_BIT(11)) +#define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ + GRF_BIT(11)) +#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) +#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) +#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) +#define RK3368_GMAC_SPEED_100M GRF_BIT(7) +#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) +#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) +#define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) +#define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) +#define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) +#define RK3368_GMAC_RMII_MODE GRF_BIT(6) +#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) + +/* RK3368_GRF_SOC_CON16 */ +#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) +#define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) +#define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) +#define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) +#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) +#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) + +static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) +{ + struct device *dev = &bsp_priv->pdev->dev; + + if (IS_ERR(bsp_priv->grf)) { + dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); + return; + } + + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_PHY_INTF_SEL_RGMII | + RK3368_GMAC_RMII_MODE_CLR); + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, + RK3368_GMAC_RXCLK_DLY_ENABLE | + RK3368_GMAC_TXCLK_DLY_ENABLE | + RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | + RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); +} + +static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + struct device *dev = &bsp_priv->pdev->dev; + + if (IS_ERR(bsp_priv->grf)) { + dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); + return; + } + + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); +} + +static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) +{ + struct device *dev = &bsp_priv->pdev->dev; + + if (IS_ERR(bsp_priv->grf)) { + dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); + return; + } + + if (speed == 10) + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_CLK_2_5M); + else if (speed == 100) + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_CLK_25M); + else if (speed == 1000) + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_CLK_125M); + else + dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); +} + +static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) +{ + struct device *dev = &bsp_priv->pdev->dev; + + if (IS_ERR(bsp_priv->grf)) { + dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); + return; + } + + if (speed == 10) { + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_RMII_CLK_2_5M | + RK3368_GMAC_SPEED_10M); + } else if (speed == 100) { + regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, + RK3368_GMAC_RMII_CLK_25M | + RK3368_GMAC_SPEED_100M); + } else { + dev_err(dev, "unknown speed value for RMII! speed=%d", speed); + } +} + +struct rk_gmac_ops rk3368_ops = { + .set_to_rgmii = rk3368_set_to_rgmii, + .set_to_rmii = rk3368_set_to_rmii, + .set_rgmii_speed = rk3368_set_rgmii_speed, + .set_rmii_speed = rk3368_set_rmii_speed, +}; + static int gmac_clk_init(struct rk_priv_data *bsp_priv) { struct device *dev = &bsp_priv->pdev->dev; @@ -422,6 +534,11 @@ static void *rk3288_gmac_setup(struct platform_device *pdev) return rk_gmac_setup(pdev, &rk3288_ops); } +static void *rk3368_gmac_setup(struct platform_device *pdev) +{ + return rk_gmac_setup(pdev, &rk3368_ops); +} + static int rk_gmac_init(struct platform_device *pdev, void *priv) { struct rk_priv_data *bsp_priv = priv; @@ -467,8 +584,17 @@ static const struct stmmac_of_data rk3288_gmac_data = { .exit = rk_gmac_exit, }; +static const struct stmmac_of_data rk3368_gmac_data = { + .has_gmac = 1, + .fix_mac_speed = rk_fix_speed, + .setup = rk3368_gmac_setup, + .init = rk_gmac_init, + .exit = rk_gmac_exit, +}; + static const struct of_device_id rk_gmac_dwmac_match[] = { { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_gmac_data}, + { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_gmac_data}, { } }; MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); -- cgit v1.2.3 From 0dd0770936363ecd4d49192782bceccb882d3a24 Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Tue, 23 Jun 2015 11:43:53 +0300 Subject: NET: Add ezchip ethernet driver Simple LAN device for debug or management purposes. Device supports interrupts for RX and TX(completion). Device does not have DMA ability. Signed-off-by: Noam Camus Signed-off-by: Tal Zilcer Acked-by: Alexey Brodkin Signed-off-by: David S. Miller --- .../devicetree/bindings/net/ezchip_enet.txt | 15 + drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/ezchip/Kconfig | 26 + drivers/net/ethernet/ezchip/Makefile | 1 + drivers/net/ethernet/ezchip/nps_enet.c | 658 +++++++++++++++++++++ drivers/net/ethernet/ezchip/nps_enet.h | 336 +++++++++++ 7 files changed, 1038 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ezchip_enet.txt create mode 100644 drivers/net/ethernet/ezchip/Kconfig create mode 100644 drivers/net/ethernet/ezchip/Makefile create mode 100644 drivers/net/ethernet/ezchip/nps_enet.c create mode 100644 drivers/net/ethernet/ezchip/nps_enet.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/ezchip_enet.txt b/Documentation/devicetree/bindings/net/ezchip_enet.txt new file mode 100644 index 000000000000..4e29b2b82873 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ezchip_enet.txt @@ -0,0 +1,15 @@ +* EZchip NPS Management Ethernet port driver + +Required properties: +- compatible: Should be "ezchip,nps-mgt-enet" +- reg: Address and length of the register set for the device +- interrupts: Should contain the ENET interrupt + +Examples: + + ethernet@f0003000 { + compatible = "ezchip,nps-mgt-enet"; + reg = <0xf0003000 0x44>; + interrupts = <7>; + mac-address = [ 00 11 22 33 44 55 ]; + }; diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 9a8308553520..f3bb1784066b 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -67,6 +67,7 @@ config DNET source "drivers/net/ethernet/dec/Kconfig" source "drivers/net/ethernet/dlink/Kconfig" source "drivers/net/ethernet/emulex/Kconfig" +source "drivers/net/ethernet/ezchip/Kconfig" source "drivers/net/ethernet/neterion/Kconfig" source "drivers/net/ethernet/faraday/Kconfig" source "drivers/net/ethernet/freescale/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 4395d99115a0..c51014b0464f 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_NET_VENDOR_DEC) += dec/ obj-$(CONFIG_NET_VENDOR_DLINK) += dlink/ obj-$(CONFIG_NET_VENDOR_EMULEX) += emulex/ +obj-$(CONFIG_NET_VENDOR_EZCHIP) += ezchip/ obj-$(CONFIG_NET_VENDOR_EXAR) += neterion/ obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/ obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/ diff --git a/drivers/net/ethernet/ezchip/Kconfig b/drivers/net/ethernet/ezchip/Kconfig new file mode 100644 index 000000000000..48ecbc8aaaea --- /dev/null +++ b/drivers/net/ethernet/ezchip/Kconfig @@ -0,0 +1,26 @@ +# +# EZchip network device configuration +# + +config NET_VENDOR_EZCHIP + bool "EZchip devices" + default y + ---help--- + If you have a network (Ethernet) device belonging to this class, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about EZchip devices. If you say Y, you will be asked for + your specific device in the following questions. + +if NET_VENDOR_EZCHIP + +config EZCHIP_NPS_MANAGEMENT_ENET + tristate "EZchip NPS management enet support" + depends on OF_IRQ && OF_NET + ---help--- + Simple LAN device for debug or management purposes. + Device supports interrupts for RX and TX(completion). + Device does not have DMA ability. + +endif diff --git a/drivers/net/ethernet/ezchip/Makefile b/drivers/net/ethernet/ezchip/Makefile new file mode 100644 index 000000000000..e490176a8137 --- /dev/null +++ b/drivers/net/ethernet/ezchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_EZCHIP_NPS_MANAGEMENT_ENET) += nps_enet.o diff --git a/drivers/net/ethernet/ezchip/nps_enet.c b/drivers/net/ethernet/ezchip/nps_enet.c new file mode 100644 index 000000000000..24a85b292007 --- /dev/null +++ b/drivers/net/ethernet/ezchip/nps_enet.c @@ -0,0 +1,658 @@ +/* + * Copyright(c) 2015 EZchip Technologies. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + */ + +#include +#include +#include +#include +#include +#include +#include "nps_enet.h" + +#define DRV_NAME "nps_mgt_enet" + +static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32)); + + /* Empty Rx FIFO buffer by reading all words */ + for (i = 0; i < len; i++) + nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); +} + +static void nps_enet_read_rx_fifo(struct net_device *ndev, + unsigned char *dst, u32 length) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + s32 i, last = length & (sizeof(u32) - 1); + u32 *reg = (u32 *)dst, len = length / sizeof(u32); + bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32)); + + /* In case dst is not aligned we need an intermediate buffer */ + if (dst_is_aligned) + for (i = 0; i < len; i++, reg++) + *reg = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); + else { /* !dst_is_aligned */ + for (i = 0; i < len; i++, reg++) { + u32 buf = + nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); + + /* to accommodate word-unaligned address of "reg" + * we have to do memcpy_toio() instead of simple "=". + */ + memcpy_toio((void __iomem *)reg, &buf, sizeof(buf)); + } + } + + /* copy last bytes (if any) */ + if (last) { + u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF); + + memcpy_toio((void __iomem *)reg, &buf, last); + } +} + +static u32 nps_enet_rx_handler(struct net_device *ndev) +{ + u32 frame_len, err = 0; + u32 work_done = 0; + struct nps_enet_priv *priv = netdev_priv(ndev); + struct sk_buff *skb; + struct nps_enet_rx_ctl rx_ctrl; + + rx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL); + frame_len = rx_ctrl.nr; + + /* Check if we got RX */ + if (!rx_ctrl.cr) + return work_done; + + /* If we got here there is a work for us */ + work_done++; + + /* Check Rx error */ + if (rx_ctrl.er) { + ndev->stats.rx_errors++; + err = 1; + } + + /* Check Rx CRC error */ + if (rx_ctrl.crc) { + ndev->stats.rx_crc_errors++; + ndev->stats.rx_dropped++; + err = 1; + } + + /* Check Frame length Min 64b */ + if (unlikely(frame_len < ETH_ZLEN)) { + ndev->stats.rx_length_errors++; + ndev->stats.rx_dropped++; + err = 1; + } + + if (err) + goto rx_irq_clean; + + /* Skb allocation */ + skb = netdev_alloc_skb_ip_align(ndev, frame_len); + if (unlikely(!skb)) { + ndev->stats.rx_errors++; + ndev->stats.rx_dropped++; + goto rx_irq_clean; + } + + /* Copy frame from Rx fifo into the skb */ + nps_enet_read_rx_fifo(ndev, skb->data, frame_len); + + skb_put(skb, frame_len); + skb->protocol = eth_type_trans(skb, ndev); + skb->ip_summed = CHECKSUM_UNNECESSARY; + + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += frame_len; + netif_receive_skb(skb); + + goto rx_irq_frame_done; + +rx_irq_clean: + /* Clean Rx fifo */ + nps_enet_clean_rx_fifo(ndev, frame_len); + +rx_irq_frame_done: + /* Ack Rx ctrl register */ + nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0); + + return work_done; +} + +static void nps_enet_tx_handler(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_tx_ctl tx_ctrl; + + tx_ctrl.value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL); + + /* Check if we got TX */ + if (!priv->tx_packet_sent || tx_ctrl.ct) + return; + + /* Check Tx transmit error */ + if (unlikely(tx_ctrl.et)) { + ndev->stats.tx_errors++; + } else { + ndev->stats.tx_packets++; + ndev->stats.tx_bytes += tx_ctrl.nt; + } + + if (priv->tx_skb) { + dev_kfree_skb(priv->tx_skb); + priv->tx_skb = NULL; + } + + priv->tx_packet_sent = false; + + if (netif_queue_stopped(ndev)) + netif_wake_queue(ndev); +} + +/** + * nps_enet_poll - NAPI poll handler. + * @napi: Pointer to napi_struct structure. + * @budget: How many frames to process on one call. + * + * returns: Number of processed frames + */ +static int nps_enet_poll(struct napi_struct *napi, int budget) +{ + struct net_device *ndev = napi->dev; + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_buf_int_enable buf_int_enable; + u32 work_done; + + buf_int_enable.rx_rdy = NPS_ENET_ENABLE; + buf_int_enable.tx_done = NPS_ENET_ENABLE; + nps_enet_tx_handler(ndev); + work_done = nps_enet_rx_handler(ndev); + if (work_done < budget) { + napi_complete(napi); + nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, + buf_int_enable.value); + } + + return work_done; +} + +/** + * nps_enet_irq_handler - Global interrupt handler for ENET. + * @irq: irq number. + * @dev_instance: device instance. + * + * returns: IRQ_HANDLED for all cases. + * + * EZchip ENET has 2 interrupt causes, and depending on bits raised in + * CTRL registers we may tell what is a reason for interrupt to fire up. + * We got one for RX and the other for TX (completion). + */ +static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance) +{ + struct net_device *ndev = dev_instance; + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_buf_int_cause buf_int_cause; + + buf_int_cause.value = + nps_enet_reg_get(priv, NPS_ENET_REG_BUF_INT_CAUSE); + + if (buf_int_cause.tx_done || buf_int_cause.rx_rdy) + if (likely(napi_schedule_prep(&priv->napi))) { + nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); + __napi_schedule(&priv->napi); + } + + return IRQ_HANDLED; +} + +static void nps_enet_set_hw_mac_address(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_ge_mac_cfg_1 ge_mac_cfg_1; + struct nps_enet_ge_mac_cfg_2 *ge_mac_cfg_2 = &priv->ge_mac_cfg_2; + + /* set MAC address in HW */ + ge_mac_cfg_1.octet_0 = ndev->dev_addr[0]; + ge_mac_cfg_1.octet_1 = ndev->dev_addr[1]; + ge_mac_cfg_1.octet_2 = ndev->dev_addr[2]; + ge_mac_cfg_1.octet_3 = ndev->dev_addr[3]; + ge_mac_cfg_2->octet_4 = ndev->dev_addr[4]; + ge_mac_cfg_2->octet_5 = ndev->dev_addr[5]; + + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1, + ge_mac_cfg_1.value); + + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, + ge_mac_cfg_2->value); +} + +/** + * nps_enet_hw_reset - Reset the network device. + * @ndev: Pointer to the network device. + * + * This function reset the PCS and TX fifo. + * The programming model is to set the relevant reset bits + * wait for some time for this to propagate and then unset + * the reset bits. This way we ensure that reset procedure + * is done successfully by device. + */ +static void nps_enet_hw_reset(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_ge_rst ge_rst; + struct nps_enet_phase_fifo_ctl phase_fifo_ctl; + + ge_rst.value = 0; + phase_fifo_ctl.value = 0; + /* Pcs reset sequence*/ + ge_rst.gmac_0 = NPS_ENET_ENABLE; + nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst.value); + usleep_range(10, 20); + ge_rst.value = 0; + nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst.value); + + /* Tx fifo reset sequence */ + phase_fifo_ctl.rst = NPS_ENET_ENABLE; + phase_fifo_ctl.init = NPS_ENET_ENABLE; + nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, + phase_fifo_ctl.value); + usleep_range(10, 20); + phase_fifo_ctl.value = 0; + nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL, + phase_fifo_ctl.value); +} + +static void nps_enet_hw_enable_control(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_ge_mac_cfg_0 ge_mac_cfg_0; + struct nps_enet_buf_int_enable buf_int_enable; + struct nps_enet_ge_mac_cfg_2 *ge_mac_cfg_2 = &priv->ge_mac_cfg_2; + struct nps_enet_ge_mac_cfg_3 *ge_mac_cfg_3 = &priv->ge_mac_cfg_3; + s32 max_frame_length; + + ge_mac_cfg_0.value = 0; + buf_int_enable.value = 0; + /* Enable Rx and Tx statistics */ + ge_mac_cfg_2->stat_en = NPS_ENET_GE_MAC_CFG_2_STAT_EN; + + /* Discard packets with different MAC address */ + ge_mac_cfg_2->disc_da = NPS_ENET_ENABLE; + + /* Discard multicast packets */ + ge_mac_cfg_2->disc_mc = NPS_ENET_ENABLE; + + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, + ge_mac_cfg_2->value); + + /* Discard Packets bigger than max frame length */ + max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN; + if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) { + ge_mac_cfg_3->max_len = max_frame_length; + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3, + ge_mac_cfg_3->value); + } + + /* Enable interrupts */ + buf_int_enable.rx_rdy = NPS_ENET_ENABLE; + buf_int_enable.tx_done = NPS_ENET_ENABLE; + nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, + buf_int_enable.value); + + /* Write device MAC address to HW */ + nps_enet_set_hw_mac_address(ndev); + + /* Rx and Tx HW features */ + ge_mac_cfg_0.tx_pad_en = NPS_ENET_ENABLE; + ge_mac_cfg_0.tx_crc_en = NPS_ENET_ENABLE; + ge_mac_cfg_0.rx_crc_strip = NPS_ENET_ENABLE; + + /* IFG configuration */ + ge_mac_cfg_0.rx_ifg = NPS_ENET_GE_MAC_CFG_0_RX_IFG; + ge_mac_cfg_0.tx_ifg = NPS_ENET_GE_MAC_CFG_0_TX_IFG; + + /* preamble configuration */ + ge_mac_cfg_0.rx_pr_check_en = NPS_ENET_ENABLE; + ge_mac_cfg_0.tx_pr_len = NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN; + + /* enable flow control frames */ + ge_mac_cfg_0.tx_fc_en = NPS_ENET_ENABLE; + ge_mac_cfg_0.rx_fc_en = NPS_ENET_ENABLE; + ge_mac_cfg_0.tx_fc_retr = NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR; + + /* Enable Rx and Tx */ + ge_mac_cfg_0.rx_en = NPS_ENET_ENABLE; + ge_mac_cfg_0.tx_en = NPS_ENET_ENABLE; + + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, + ge_mac_cfg_0.value); +} + +static void nps_enet_hw_disable_control(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + + /* Disable interrupts */ + nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0); + + /* Disable Rx and Tx */ + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0); +} + +static void nps_enet_send_frame(struct net_device *ndev, + struct sk_buff *skb) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_tx_ctl tx_ctrl; + short length = skb->len; + u32 i, len = DIV_ROUND_UP(length, sizeof(u32)); + u32 *src = (u32 *)virt_to_phys(skb->data); + bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32)); + + tx_ctrl.value = 0; + /* In case src is not aligned we need an intermediate buffer */ + if (src_is_aligned) + for (i = 0; i < len; i++, src++) + nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF, *src); + else { /* !src_is_aligned */ + for (i = 0; i < len; i++, src++) { + u32 buf; + + /* to accommodate word-unaligned address of "src" + * we have to do memcpy_fromio() instead of simple "=" + */ + memcpy_fromio(&buf, (void __iomem *)src, sizeof(buf)); + nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF, buf); + } + } + /* Write the length of the Frame */ + tx_ctrl.nt = length; + + /* Indicate SW is done */ + priv->tx_packet_sent = true; + tx_ctrl.ct = NPS_ENET_ENABLE; + + /* Send Frame */ + nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl.value); +} + +/** + * nps_enet_set_mac_address - Set the MAC address for this device. + * @ndev: Pointer to net_device structure. + * @p: 6 byte Address to be written as MAC address. + * + * This function copies the HW address from the sockaddr structure to the + * net_device structure and updates the address in HW. + * + * returns: -EBUSY if the net device is busy or 0 if the address is set + * successfully. + */ +static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p) +{ + struct sockaddr *addr = p; + s32 res; + + if (netif_running(ndev)) + return -EBUSY; + + res = eth_mac_addr(ndev, p); + if (!res) { + ether_addr_copy(ndev->dev_addr, addr->sa_data); + nps_enet_set_hw_mac_address(ndev); + } + + return res; +} + +/** + * nps_enet_set_rx_mode - Change the receive filtering mode. + * @ndev: Pointer to the network device. + * + * This function enables/disables promiscuous mode + */ +static void nps_enet_set_rx_mode(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2; + + ge_mac_cfg_2.value = priv->ge_mac_cfg_2.value; + + if (ndev->flags & IFF_PROMISC) { + ge_mac_cfg_2.disc_da = NPS_ENET_DISABLE; + ge_mac_cfg_2.disc_mc = NPS_ENET_DISABLE; + } else { + ge_mac_cfg_2.disc_da = NPS_ENET_ENABLE; + ge_mac_cfg_2.disc_mc = NPS_ENET_ENABLE; + } + + nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2.value); +} + +/** + * nps_enet_open - Open the network device. + * @ndev: Pointer to the network device. + * + * returns: 0, on success or non-zero error value on failure. + * + * This function sets the MAC address, requests and enables an IRQ + * for the ENET device and starts the Tx queue. + */ +static s32 nps_enet_open(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + s32 err; + + /* Reset private variables */ + priv->tx_packet_sent = false; + priv->ge_mac_cfg_2.value = 0; + priv->ge_mac_cfg_3.value = 0; + + /* ge_mac_cfg_3 default values */ + priv->ge_mac_cfg_3.rx_ifg_th = NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH; + priv->ge_mac_cfg_3.max_len = NPS_ENET_GE_MAC_CFG_3_MAX_LEN; + + /* Disable HW device */ + nps_enet_hw_disable_control(ndev); + + /* irq Rx allocation */ + err = request_irq(priv->irq, nps_enet_irq_handler, + 0, "enet-rx-tx", ndev); + if (err) + return err; + + napi_enable(&priv->napi); + + /* Enable HW device */ + nps_enet_hw_reset(ndev); + nps_enet_hw_enable_control(ndev); + + netif_start_queue(ndev); + + return 0; +} + +/** + * nps_enet_stop - Close the network device. + * @ndev: Pointer to the network device. + * + * This function stops the Tx queue, disables interrupts for the ENET device. + */ +static s32 nps_enet_stop(struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + + napi_disable(&priv->napi); + netif_stop_queue(ndev); + nps_enet_hw_disable_control(ndev); + free_irq(priv->irq, ndev); + + return 0; +} + +/** + * nps_enet_start_xmit - Starts the data transmission. + * @skb: sk_buff pointer that contains data to be Transmitted. + * @ndev: Pointer to net_device structure. + * + * returns: NETDEV_TX_OK, on success + * NETDEV_TX_BUSY, if any of the descriptors are not free. + * + * This function is invoked from upper layers to initiate transmission. + */ +static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct nps_enet_priv *priv = netdev_priv(ndev); + + /* This driver handles one frame at a time */ + netif_stop_queue(ndev); + + nps_enet_send_frame(ndev, skb); + + priv->tx_skb = skb; + + return NETDEV_TX_OK; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +static void nps_enet_poll_controller(struct net_device *ndev) +{ + disable_irq(ndev->irq); + nps_enet_irq_handler(ndev->irq, ndev); + enable_irq(ndev->irq); +} +#endif + +static const struct net_device_ops nps_netdev_ops = { + .ndo_open = nps_enet_open, + .ndo_stop = nps_enet_stop, + .ndo_start_xmit = nps_enet_start_xmit, + .ndo_set_mac_address = nps_enet_set_mac_address, + .ndo_set_rx_mode = nps_enet_set_rx_mode, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = nps_enet_poll_controller, +#endif +}; + +static s32 nps_enet_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct net_device *ndev; + struct nps_enet_priv *priv; + s32 err = 0; + const char *mac_addr; + struct resource *res_regs; + + if (!dev->of_node) + return -ENODEV; + + ndev = alloc_etherdev(sizeof(struct nps_enet_priv)); + if (!ndev) + return -ENOMEM; + + platform_set_drvdata(pdev, ndev); + SET_NETDEV_DEV(ndev, dev); + priv = netdev_priv(ndev); + + /* The EZ NET specific entries in the device structure. */ + ndev->netdev_ops = &nps_netdev_ops; + ndev->watchdog_timeo = (400 * HZ / 1000); + /* FIXME :: no multicast support yet */ + ndev->flags &= ~IFF_MULTICAST; + + res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs_base = devm_ioremap_resource(dev, res_regs); + if (IS_ERR(priv->regs_base)) { + err = PTR_ERR(priv->regs_base); + goto out_netdev; + } + dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base); + + /* set kernel MAC address to dev */ + mac_addr = of_get_mac_address(dev->of_node); + if (mac_addr) + ether_addr_copy(ndev->dev_addr, mac_addr); + else + eth_hw_addr_random(ndev); + + /* Get IRQ number */ + priv->irq = platform_get_irq(pdev, 0); + if (!priv->irq) { + dev_err(dev, "failed to retrieve value from device tree\n"); + err = -ENODEV; + goto out_netdev; + } + + netif_napi_add(ndev, &priv->napi, nps_enet_poll, + NPS_ENET_NAPI_POLL_WEIGHT); + + /* Register the driver. Should be the last thing in probe */ + err = register_netdev(ndev); + if (err) { + dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n", + ndev->name, (s32)err); + goto out_netif_api; + } + + dev_info(dev, "(rx/tx=%d)\n", priv->irq); + return 0; + +out_netif_api: + netif_napi_del(&priv->napi); +out_netdev: + if (err) + free_netdev(ndev); + + return err; +} + +static s32 nps_enet_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct nps_enet_priv *priv = netdev_priv(ndev); + + unregister_netdev(ndev); + free_netdev(ndev); + netif_napi_del(&priv->napi); + + return 0; +} + +static const struct of_device_id nps_enet_dt_ids[] = { + { .compatible = "ezchip,nps-mgt-enet" }, + { /* Sentinel */ } +}; + +static struct platform_driver nps_enet_driver = { + .probe = nps_enet_probe, + .remove = nps_enet_remove, + .driver = { + .name = DRV_NAME, + .of_match_table = nps_enet_dt_ids, + }, +}; + +module_platform_driver(nps_enet_driver); + +MODULE_AUTHOR("EZchip Semiconductor"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/ethernet/ezchip/nps_enet.h b/drivers/net/ethernet/ezchip/nps_enet.h new file mode 100644 index 000000000000..fc45c9daa1c2 --- /dev/null +++ b/drivers/net/ethernet/ezchip/nps_enet.h @@ -0,0 +1,336 @@ +/* + * Copyright(c) 2015 EZchip Technologies. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + */ + +#ifndef _NPS_ENET_H +#define _NPS_ENET_H + +/* default values */ +#define NPS_ENET_NAPI_POLL_WEIGHT 0x2 +#define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF +#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7 +#define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5 +#define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC +#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7 +#define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3 +#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14 +#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC +#define NPS_ENET_ENABLE 1 +#define NPS_ENET_DISABLE 0 + +/* register definitions */ +#define NPS_ENET_REG_TX_CTL 0x800 +#define NPS_ENET_REG_TX_BUF 0x808 +#define NPS_ENET_REG_RX_CTL 0x810 +#define NPS_ENET_REG_RX_BUF 0x818 +#define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0 +#define NPS_ENET_REG_BUF_INT_CAUSE 0x8C4 +#define NPS_ENET_REG_GE_MAC_CFG_0 0x1000 +#define NPS_ENET_REG_GE_MAC_CFG_1 0x1004 +#define NPS_ENET_REG_GE_MAC_CFG_2 0x1008 +#define NPS_ENET_REG_GE_MAC_CFG_3 0x100C +#define NPS_ENET_REG_GE_RST 0x1400 +#define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404 + +/* Tx control register */ +struct nps_enet_tx_ctl { + union { + /* ct: SW sets to indicate frame ready in Tx buffer for + * transmission. HW resets to when transmission done + * et: Transmit error + * nt: Length in bytes of Tx frame loaded to Tx buffer + */ + struct { + u32 + __reserved_1:16, + ct:1, + et:1, + __reserved_2:3, + nt:11; + }; + + u32 value; + }; +}; + +/* Rx control register */ +struct nps_enet_rx_ctl { + union { + /* cr: HW sets to indicate frame ready in Rx buffer. + * SW resets to indicate host read received frame + * and new frames can be written to Rx buffer + * er: Rx error indication + * crc: Rx CRC error indication + * nr: Length in bytes of Rx frame loaded by MAC to Rx buffer + */ + struct { + u32 + __reserved_1:16, + cr:1, + er:1, + crc:1, + __reserved_2:2, + nr:11; + }; + + u32 value; + }; +}; + +/* Interrupt enable for data buffer events register */ +struct nps_enet_buf_int_enable { + union { + /* tx_done: Interrupt generation in the case when new frame + * is ready in Rx buffer + * rx_rdy: Interrupt generation in the case when current frame + * was read from TX buffer + */ + struct { + u32 + __reserved:30, + tx_done:1, + rx_rdy:1; + }; + + u32 value; + }; +}; + +/* Interrupt cause for data buffer events register */ +struct nps_enet_buf_int_cause { + union { + /* tx_done: Interrupt in the case when current frame was + * read from TX buffer. + * rx_rdy: Interrupt in the case when new frame is ready + * in RX buffer. + */ + struct { + u32 + __reserved:30, + tx_done:1, + rx_rdy:1; + }; + + u32 value; + }; +}; + +/* Gbps Eth MAC Configuration 0 register */ +struct nps_enet_ge_mac_cfg_0 { + union { + /* tx_pr_len: Transmit preamble length in bytes + * tx_ifg_nib: Tx idle pattern + * nib_mode: Nibble (4-bit) Mode + * rx_pr_check_en: Receive preamble Check Enable + * tx_ifg: Transmit inter-Frame Gap + * rx_ifg: Receive inter-Frame Gap + * tx_fc_retr: Transmit Flow Control Retransmit Mode + * rx_length_check_en: Receive Length Check Enable + * rx_crc_ignore: Results of the CRC check are ignored + * rx_crc_strip: MAC strips the CRC from received frames + * rx_fc_en: Receive Flow Control Enable + * tx_crc_en: Transmit CRC Enabled + * tx_pad_en: Transmit Padding Enable + * tx_cf_en: Transmit Flow Control Enable + * tx_en: Transmit Enable + * rx_en: Receive Enable + */ + struct { + u32 + tx_pr_len:4, + tx_ifg_nib:4, + nib_mode:1, + rx_pr_check_en:1, + tx_ifg:6, + rx_ifg:4, + tx_fc_retr:3, + rx_length_check_en:1, + rx_crc_ignore:1, + rx_crc_strip:1, + rx_fc_en:1, + tx_crc_en:1, + tx_pad_en:1, + tx_fc_en:1, + tx_en:1, + rx_en:1; + }; + + u32 value; + }; +}; + +/* Gbps Eth MAC Configuration 1 register */ +struct nps_enet_ge_mac_cfg_1 { + union { + /* octet_3: MAC address octet 3 + * octet_2: MAC address octet 2 + * octet_1: MAC address octet 1 + * octet_0: MAC address octet 0 + */ + struct { + u32 + octet_3:8, + octet_2:8, + octet_1:8, + octet_0:8; + }; + + u32 value; + }; +}; + +/* Gbps Eth MAC Configuration 2 register */ +struct nps_enet_ge_mac_cfg_2 { + union { + /* transmit_flush_en: MAC flush enable + * stat_en: RMON statistics interface enable + * disc_da: Discard frames with DA different + * from MAC address + * disc_bc: Discard broadcast frames + * disc_mc: Discard multicast frames + * octet_5: MAC address octet 5 + * octet_4: MAC address octet 4 + */ + struct { + u32 + transmit_flush_en:1, + __reserved_1:5, + stat_en:2, + __reserved_2:1, + disc_da:1, + disc_bc:1, + disc_mc:1, + __reserved_3:4, + octet_5:8, + octet_4:8; + }; + + u32 value; + }; +}; + +/* Gbps Eth MAC Configuration 3 register */ +struct nps_enet_ge_mac_cfg_3 { + union { + /* ext_oob_cbfc_sel: Selects one of the 4 profiles for + * extended OOB in-flow-control indication + * max_len: Maximum receive frame length in bytes + * tx_cbfc_en: Enable transmission of class-based + * flow control packets + * rx_ifg_th: Threshold for IFG status reporting via OOB + * cf_timeout: Configurable time to decrement FC counters + * cf_drop: Drop control frames + * redirect_cbfc_sel: Selects one of CBFC redirect profiles + * rx_cbfc_redir_en: Enable Rx class-based flow + * control redirect + * rx_cbfc_en: Enable Rx class-based flow control + * tm_hd_mode: TM header mode + */ + struct { + u32 + ext_oob_cbfc_sel:2, + max_len:14, + tx_cbfc_en:1, + rx_ifg_th:5, + cf_timeout:4, + cf_drop:1, + redirect_cbfc_sel:2, + rx_cbfc_redir_en:1, + rx_cbfc_en:1, + tm_hd_mode:1; + }; + + u32 value; + }; +}; + +/* GE MAC, PCS reset control register */ +struct nps_enet_ge_rst { + union { + /* gmac_0: GE MAC reset + * spcs_0: SGMII PCS reset + */ + struct { + u32 + __reserved_1:23, + gmac_0:1, + __reserved_2:7, + spcs_0:1; + }; + + u32 value; + }; +}; + +/* Tx phase sync FIFO control register */ +struct nps_enet_phase_fifo_ctl { + union { + /* init: initialize serdes TX phase sync FIFO pointers + * rst: reset serdes TX phase sync FIFO + */ + struct { + u32 + __reserved:30, + init:1, + rst:1; + }; + + u32 value; + }; +}; + +/** + * struct nps_enet_priv - Storage of ENET's private information. + * @regs_base: Base address of ENET memory-mapped control registers. + * @irq: For RX/TX IRQ number. + * @tx_packet_sent: SW indication if frame is being sent. + * @tx_skb: socket buffer of sent frame. + * @napi: Structure for NAPI. + */ +struct nps_enet_priv { + void __iomem *regs_base; + s32 irq; + bool tx_packet_sent; + struct sk_buff *tx_skb; + struct napi_struct napi; + struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2; + struct nps_enet_ge_mac_cfg_3 ge_mac_cfg_3; +}; + +/** + * nps_reg_set - Sets ENET register with provided value. + * @priv: Pointer to EZchip ENET private data structure. + * @reg: Register offset from base address. + * @value: Value to set in register. + */ +static inline void nps_enet_reg_set(struct nps_enet_priv *priv, + s32 reg, s32 value) +{ + iowrite32be(value, priv->regs_base + reg); +} + +/** + * nps_reg_get - Gets value of specified ENET register. + * @priv: Pointer to EZchip ENET private data structure. + * @reg: Register offset from base address. + * + * returns: Value of requested register. + */ +static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg) +{ + return ioread32be(priv->regs_base + reg); +} + +#endif /* _NPS_ENET_H */ -- cgit v1.2.3 From 72d942e23cdab62fba0337403db218dcc9973494 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 12 Jun 2015 17:44:07 +0200 Subject: of: Add vendor prefix for Zodiac Inflight Innovations Signed-off-by: Andrew Lunn Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 80339192c93e..c400c95abc67 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -211,3 +211,4 @@ xillybus Xillybus Ltd. xlnx Xilinx zyxel ZyXEL Communications Corp. zarlink Zarlink Semiconductor +zii Zodiac Inflight Innovations -- cgit v1.2.3 From 0b34c1a489f6f018c4fbfbd12657acaa0b4f4ca9 Mon Sep 17 00:00:00 2001 From: Thomas Langer Date: Thu, 18 Jun 2015 18:19:02 +0000 Subject: Documentation: DT: Fix a typo in the filename "lantiq,-pinumx.txt" To fix it, use the chance to rename according the compatible string, which is "lantiq,pinctrl-falcon" and "lantiq,pinctrl-xway" Signed-off-by: Thomas Langer Cc: John Crispin Signed-off-by: Rob Herring --- .../bindings/pinctrl/lantiq,falcon-pinumx.txt | 83 ------------------ .../bindings/pinctrl/lantiq,pinctrl-falcon.txt | 83 ++++++++++++++++++ .../bindings/pinctrl/lantiq,pinctrl-xway.txt | 97 ++++++++++++++++++++++ .../bindings/pinctrl/lantiq,xway-pinumx.txt | 97 ---------------------- 4 files changed, 180 insertions(+), 180 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt deleted file mode 100644 index ac4da9fe07bd..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Lantiq FALCON pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-falcon" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, - jtag, slic, pcm, asc1 - - functions: - rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down -- lantiq,drive-current: Boolean, enables drive-current -- lantiq,slew-rate: Boolean, enables slew-rate - -Example: - pinmux0 { - compatible = "lantiq,pinctrl-falcon"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - asc0 { - lantiq,groups = "asc0"; - lantiq,function = "asc"; - }; - ntr { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - }; - i2c { - lantiq,groups = "i2c"; - lantiq,function = "i2c"; - }; - hrst { - lantiq,groups = "hrst"; - lantiq,function = "rst"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt new file mode 100644 index 000000000000..ac4da9fe07bd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt @@ -0,0 +1,83 @@ +Lantiq FALCON pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-falcon" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, + jtag, slic, pcm, asc1 + + functions: + rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down +- lantiq,drive-current: Boolean, enables drive-current +- lantiq,slew-rate: Boolean, enables slew-rate + +Example: + pinmux0 { + compatible = "lantiq,pinctrl-falcon"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + asc0 { + lantiq,groups = "asc0"; + lantiq,function = "asc"; + }; + ntr { + lantiq,groups = "ntr8k"; + lantiq,function = "ntr"; + }; + i2c { + lantiq,groups = "i2c"; + lantiq,function = "i2c"; + }; + hrst { + lantiq,groups = "hrst"; + lantiq,function = "rst"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt new file mode 100644 index 000000000000..e89b4677567d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt @@ -0,0 +1,97 @@ +Lantiq XWAY pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, + ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, + spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, + gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, + req3 + + additional mux groups (XR9 only): + mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio + + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down, 2: up. +- lantiq,open-drain: Boolean, enables open-drain on the defined pin. + +Valid values for XWAY pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for XR9 pin names: + Pinconf pins can be referenced via the names io0-io55. + +Example: + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt deleted file mode 100644 index e89b4677567d..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt +++ /dev/null @@ -1,97 +0,0 @@ -Lantiq XWAY pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, - ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, - spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, - gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, - req3 - - additional mux groups (XR9 only): - mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio - - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- lantiq,open-drain: Boolean, enables open-drain on the defined pin. - -Valid values for XWAY pin names: - Pinconf pins can be referenced via the names io0-io31. - -Valid values for XR9 pin names: - Pinconf pins can be referenced via the names io0-io55. - -Example: - gpio: pinmux@E100B10 { - compatible = "lantiq,pinctrl-xway"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - -- cgit v1.2.3 From 54b4a8f57848bb08dcbdfba94b9b1ddef1c23358 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 4 Jun 2015 09:28:48 -0500 Subject: arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support Add support for the Arria10 SDRAM EDAC. Update the bindings document for the new match string. Signed-off-by: Thor Thayer Cc: Arnd Bergmann Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov --- .../devicetree/bindings/arm/altera/socfpga-sdram-edac.txt | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt index d0ce01da5c59..f5ad0ff69fae 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt @@ -2,7 +2,7 @@ Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] The EDAC accesses a range of registers in the SDRAM controller. Required properties: -- compatible : should contain "altr,sdram-edac"; +- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" - altr,sdr-syscon : phandle of the sdr module - interrupts : Should contain the SDRAM ECC IRQ in the appropriate format for the IRQ controller. diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 8a05c47fd57f..4be75960a603 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -253,6 +253,17 @@ status = "disabled"; }; + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffcfb100 0x80>; + }; + + sdramedac { + compatible = "altr,sdram-edac-a10"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 2 4>, <0 0 4>; + }; + L2: l2-cache@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; -- cgit v1.2.3 From 3aae9edd5a63e226baf3375bb8f7e8d05f5d9098 Mon Sep 17 00:00:00 2001 From: Rami Rosen Date: Fri, 19 Jun 2015 09:18:34 +0300 Subject: EDAC: Fix typos in Documentation/edac.txt Fix various typos in Documentation/edac.txt. Signed-off-by: Rami Rosen Link: http://lkml.kernel.org/r/1434694714-2924-1-git-send-email-ramirose@gmail.com Signed-off-by: Borislav Petkov --- Documentation/edac.txt | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/edac.txt b/Documentation/edac.txt index 73fff13e848f..4df786e73e87 100644 --- a/Documentation/edac.txt +++ b/Documentation/edac.txt @@ -25,7 +25,7 @@ first time, it was renamed to 'EDAC'. The bluesmoke project at sourceforge.net is now utilized as a 'staging area' for EDAC development, before it is sent upstream to kernel.org -At the bluesmoke/EDAC project site is a series of quilt patches against +At the bluesmoke/EDAC project site, there is a series of quilt patches against recent kernels, stored in a SVN repository. For easier downloading, there is also a tarball snapshot available. @@ -235,7 +235,7 @@ In 'mcX' directories are EDAC control and attribute files for this 'X' instance of the memory controllers. For a description of the sysfs API, please see: - Documentation/ABI/testing/sysfs/devices-edac + Documentation/ABI/testing/sysfs-devices-edac ============================================================================ @@ -276,7 +276,7 @@ Total memory managed by this csrow attribute file: 'size_mb' - This attribute file displays, in count of megabytes, of memory + This attribute file displays, in count of megabytes, the memory that this csrow contains. @@ -516,7 +516,7 @@ Panic on PCI PARITY Error: 'panic_on_pci_parity' - This control files enables or disables panicking when a parity + This control file enables or disables panicking when a parity error has been detected. @@ -617,7 +617,7 @@ The 'test_device_edac' device adds 4 attributes and 1 control: reset all the above counters. -Use of the 'test_device_edac' driver should any others to create their own +Use of the 'test_device_edac' driver should enable any others to create their own unique drivers for their hardware systems. The 'test_device_edac' sample driver is located at the @@ -633,7 +633,7 @@ of the driver. Due to the way Nehalem exports Memory Controller data, some adjustments were done at i7core_edac driver. This chapter will cover those differences -1) On Nehalem, there are one Memory Controller per Quick Patch Interconnect +1) On Nehalem, there is one Memory Controller per Quick Patch Interconnect (QPI). At the driver, the term "socket" means one QPI. This is associated with a physical CPU socket. @@ -642,7 +642,7 @@ were done at i7core_edac driver. This chapter will cover those differences Each channel can have up to 3 DIMMs. The minimum known unity is DIMMs. There are no information about csrows. - As EDAC API maps the minimum unity is csrows, the driver sequencially + As EDAC API maps the minimum unity is csrows, the driver sequentially maps channel/dimm into different csrows. For example, supposing the following layout: @@ -664,7 +664,7 @@ exports one Each QPI is exported as a different memory controller. -2) Nehalem MC has the hability to generate errors. The driver implements this +2) Nehalem MC has the ability to generate errors. The driver implements this functionality via some error injection nodes: For injecting a memory error, there are some sysfs nodes, under @@ -771,5 +771,5 @@ exports one The standard error counters are generated when an mcelog error is received by the driver. Since, with udimm, this is counted by software, it is - possible that some errors could be lost. With rdimm's, they displays the + possible that some errors could be lost. With rdimm's, they display the contents of the registers -- cgit v1.2.3 From 043b43180efee8dcc41dde5ca710827b26d17510 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Fri, 19 Jun 2015 11:47:17 +0200 Subject: EDAC: Update Documentation/edac.txt Do some initial cleanup, more probably will come. - Move credits section to the end - Update maintainers - Drop sourceforge reference - project is long upstream now - Reformat sections - Reformat paragraphs - Clarify text - Bring it up-to-date - Drop useless "future hardware scanning" section Signed-off-by: Borislav Petkov --- Documentation/edac.txt | 273 +++++++++++++++++++++++-------------------------- 1 file changed, 130 insertions(+), 143 deletions(-) (limited to 'Documentation') diff --git a/Documentation/edac.txt b/Documentation/edac.txt index 4df786e73e87..0cf27a3544a5 100644 --- a/Documentation/edac.txt +++ b/Documentation/edac.txt @@ -1,53 +1,34 @@ - - EDAC - Error Detection And Correction - -Written by Doug Thompson -7 Dec 2005 -17 Jul 2007 Updated - -(c) Mauro Carvalho Chehab -05 Aug 2009 Nehalem interface - -EDAC is maintained and written by: - - Doug Thompson, Dave Jiang, Dave Peterson et al, - original author: Thayne Harbaugh, - -Contact: - website: bluesmoke.sourceforge.net - mailing list: bluesmoke-devel@lists.sourceforge.net +===================================== "bluesmoke" was the name for this device driver when it was "out-of-tree" and maintained at sourceforge.net. When it was pushed into 2.6.16 for the first time, it was renamed to 'EDAC'. -The bluesmoke project at sourceforge.net is now utilized as a 'staging area' -for EDAC development, before it is sent upstream to kernel.org - -At the bluesmoke/EDAC project site, there is a series of quilt patches against -recent kernels, stored in a SVN repository. For easier downloading, there -is also a tarball snapshot available. +PURPOSE +------- -============================================================================ -EDAC PURPOSE - -The 'edac' kernel module goal is to detect and report errors that occur -within the computer system running under linux. +The 'edac' kernel module's goal is to detect and report hardware errors +that occur within the computer system running under linux. MEMORY +------ -In the initial release, memory Correctable Errors (CE) and Uncorrectable -Errors (UE) are the primary errors being harvested. These types of errors -are harvested by the 'edac_mc' class of device. +Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are the +primary errors being harvested. These types of errors are harvested by +the 'edac_mc' device. Detecting CE events, then harvesting those events and reporting them, -CAN be a predictor of future UE events. With CE events, the system can -continue to operate, but with less safety. Preventive maintenance and -proactive part replacement of memory DIMMs exhibiting CEs can reduce -the likelihood of the dreaded UE events and system 'panics'. +*can* but must not necessarily be a predictor of future UE events. With +CE events only, the system can and will continue to operate as no data +has been damaged yet. + +However, preventive maintenance and proactive part replacement of memory +DIMMs exhibiting CEs can reduce the likelihood of the dreaded UE events +and system panics. -NON-MEMORY +OTHER HARDWARE ELEMENTS +----------------------- A new feature for EDAC, the edac_device class of device, was added in the 2.6.23 version of the kernel. @@ -56,70 +37,57 @@ This new device type allows for non-memory type of ECC hardware detectors to have their states harvested and presented to userspace via the sysfs interface. -Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA -engines, fabric switches, main data path switches, interconnections, -and various other hardware data paths. If the hardware reports it, then -a edac_device device probably can be constructed to harvest and present -that to userspace. +Some architectures have ECC detectors for L1, L2 and L3 caches, +along with DMA engines, fabric switches, main data path switches, +interconnections, and various other hardware data paths. If the hardware +reports it, then a edac_device device probably can be constructed to +harvest and present that to userspace. PCI BUS SCANNING +---------------- -In addition, PCI Bus Parity and SERR Errors are scanned for on PCI devices -in order to determine if errors are occurring on data transfers. +In addition, PCI devices are scanned for PCI Bus Parity and SERR Errors +in order to determine if errors are occurring during data transfers. The presence of PCI Parity errors must be examined with a grain of salt. -There are several add-in adapters that do NOT follow the PCI specification +There are several add-in adapters that do *not* follow the PCI specification with regards to Parity generation and reporting. The specification says the vendor should tie the parity status bits to 0 if they do not intend to generate parity. Some vendors do not do this, and thus the parity bit can "float" giving false positives. -In the kernel there is a PCI device attribute located in sysfs that is -checked by the EDAC PCI scanning code. If that attribute is set, -PCI parity/error scanning is skipped for that device. The attribute -is: +There is a PCI device attribute located in sysfs that is checked by +the EDAC PCI scanning code. If that attribute is set, PCI parity/error +scanning is skipped for that device. The attribute is: broken_parity_status -as is located in /sys/devices/pci/0000:XX:YY.Z directories for +and is located in /sys/devices/pci/0000:XX:YY.Z directories for PCI devices. -FUTURE HARDWARE SCANNING -EDAC will have future error detectors that will be integrated with -EDAC or added to it, in the following list: - - MCE Machine Check Exception - MCA Machine Check Architecture - NMI NMI notification of ECC errors - MSRs Machine Specific Register error cases - and other mechanisms. - -These errors are usually bus errors, ECC errors, thermal throttling -and the like. - - -============================================================================ -EDAC VERSIONING +VERSIONING +---------- EDAC is composed of a "core" module (edac_core.ko) and several Memory -Controller (MC) driver modules. On a given system, the CORE -is loaded and one MC driver will be loaded. Both the CORE and -the MC driver (or edac_device driver) have individual versions that reflect -current release level of their respective modules. +Controller (MC) driver modules. On a given system, the CORE is loaded +and one MC driver will be loaded. Both the CORE and the MC driver (or +edac_device driver) have individual versions that reflect current +release level of their respective modules. -Thus, to "report" on what version a system is running, one must report both -the CORE's and the MC driver's versions. +Thus, to "report" on what version a system is running, one must report +both the CORE's and the MC driver's versions. LOADING +------- -If 'edac' was statically linked with the kernel then no loading is -necessary. If 'edac' was built as modules then simply modprobe the -'edac' pieces that you need. You should be able to modprobe -hardware-specific modules and have the dependencies load the necessary core -modules. +If 'edac' was statically linked with the kernel then no loading +is necessary. If 'edac' was built as modules then simply modprobe +the 'edac' pieces that you need. You should be able to modprobe +hardware-specific modules and have the dependencies load the necessary +core modules. Example: @@ -129,35 +97,33 @@ loads both the amd76x_edac.ko memory controller module and the edac_mc.ko core module. -============================================================================ -EDAC sysfs INTERFACE - -EDAC presents a 'sysfs' interface for control, reporting and attribute -reporting purposes. +SYSFS INTERFACE +--------------- -EDAC lives in the /sys/devices/system/edac directory. +EDAC presents a 'sysfs' interface for control and reporting purposes. It +lives in the /sys/devices/system/edac directory. -Within this directory there currently reside 2 'edac' components: +Within this directory there currently reside 2 components: mc memory controller(s) system pci PCI control and status system -============================================================================ + Memory Controller (mc) Model +---------------------------- -First a background on the memory controller's model abstracted in EDAC. -Each 'mc' device controls a set of DIMM memory modules. These modules are -laid out in a Chip-Select Row (csrowX) and Channel table (chX). There can -be multiple csrows and multiple channels. +Each 'mc' device controls a set of DIMM memory modules. These modules +are laid out in a Chip-Select Row (csrowX) and Channel table (chX). +There can be multiple csrows and multiple channels. -Memory controllers allow for several csrows, with 8 csrows being a typical value. -Yet, the actual number of csrows depends on the electrical "loading" -of a given motherboard, memory controller and DIMM characteristics. +Memory controllers allow for several csrows, with 8 csrows being a +typical value. Yet, the actual number of csrows depends on the layout of +a given motherboard, memory controller and DIMM characteristics. -Dual channels allows for 128 bit data transfers to the CPU from memory. -Some newer chipsets allow for more than 2 channels, like Fully Buffered DIMMs -(FB-DIMMs). The following example will assume 2 channels: +Dual channels allows for 128 bit data transfers to/from the CPU from/to +memory. Some newer chipsets allow for more than 2 channels, like Fully +Buffered DIMMs (FB-DIMMs). The following example will assume 2 channels: Channel 0 Channel 1 @@ -179,12 +145,12 @@ for memory DIMMs: DIMM_A1 DIMM_B1 -Labels for these slots are usually silk screened on the motherboard. Slots -labeled 'A' are channel 0 in this example. Slots labeled 'B' -are channel 1. Notice that there are two csrows possible on a -physical DIMM. These csrows are allocated their csrow assignment -based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM -is placed in each Channel, the csrows cross both DIMMs. +Labels for these slots are usually silk-screened on the motherboard. +Slots labeled 'A' are channel 0 in this example. Slots labeled 'B' are +channel 1. Notice that there are two csrows possible on a physical DIMM. +These csrows are allocated their csrow assignment based on the slot into +which the memory DIMM is placed. Thus, when 1 DIMM is placed in each +Channel, the csrows cross both DIMMs. Memory DIMMs come single or dual "ranked". A rank is a populated csrow. Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above @@ -193,8 +159,8 @@ when 2 dual ranked DIMMs are similarly placed, then both csrow0 and csrow1 will be populated. The pattern repeats itself for csrow2 and csrow3. -The representation of the above is reflected in the directory tree -in EDAC's sysfs interface. Starting in directory +The representation of the above is reflected in the directory +tree in EDAC's sysfs interface. Starting in directory /sys/devices/system/edac/mc each memory controller will be represented by its own 'mcX' directory, where 'X' is the index of the MC. @@ -217,19 +183,19 @@ Under each 'mcX' directory each 'csrowX' is again represented by a |->csrow3 .... -Notice that there is no csrow1, which indicates that csrow0 is -composed of a single ranked DIMMs. This should also apply in both -Channels, in order to have dual-channel mode be operational. Since -both csrow2 and csrow3 are populated, this indicates a dual ranked -set of DIMMs for channels 0 and 1. +Notice that there is no csrow1, which indicates that csrow0 is composed +of a single ranked DIMMs. This should also apply in both Channels, in +order to have dual-channel mode be operational. Since both csrow2 and +csrow3 are populated, this indicates a dual ranked set of DIMMs for +channels 0 and 1. -Within each of the 'mcX' and 'csrowX' directories are several -EDAC control and attribute files. +Within each of the 'mcX' and 'csrowX' directories are several EDAC +control and attribute files. -============================================================================ -'mcX' DIRECTORIES +'mcX' directories +----------------- In 'mcX' directories are EDAC control and attribute files for this 'X' instance of the memory controllers. @@ -238,13 +204,14 @@ For a description of the sysfs API, please see: Documentation/ABI/testing/sysfs-devices-edac -============================================================================ -'csrowX' DIRECTORIES -When CONFIG_EDAC_LEGACY_SYSFS is enabled, the sysfs will contain the -csrowX directories. As this API doesn't work properly for Rambus, FB-DIMMs -and modern Intel Memory Controllers, this is being deprecated in favor -of dimmX directories. +'csrowX' directories +-------------------- + +When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain the csrowX +directories. As this API doesn't work properly for Rambus, FB-DIMMs and +modern Intel Memory Controllers, this is being deprecated in favor of +dimmX directories. In the 'csrowX' directories are EDAC control and attribute files for this 'X' instance of csrow: @@ -265,11 +232,11 @@ Total Correctable Errors count attribute file: 'ce_count' This attribute file displays the total count of correctable - errors that have occurred on this csrow. This - count is very important to examine. CEs provide early - indications that a DIMM is beginning to fail. This count - field should be monitored for non-zero values and report - such information to the system administrator. + errors that have occurred on this csrow. This count is very + important to examine. CEs provide early indications that a + DIMM is beginning to fail. This count field should be + monitored for non-zero values and report such information + to the system administrator. Total memory managed by this csrow attribute file: @@ -377,11 +344,13 @@ Channel 1 DIMM Label control file: motherboard specific and determination of this information must occur in userland at this time. -============================================================================ + + SYSTEM LOGGING +-------------- -If logging for UEs and CEs are enabled then system logs will have -error notices indicating errors that have been detected: +If logging for UEs and CEs is enabled, then system logs will contain +information indicating that errors have been detected: EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac @@ -404,24 +373,23 @@ The structure of the message is: and then an optional, driver-specific message that may have additional information. -Both UEs and CEs with no info will lack all but memory controller, -error type, a notice of "no info" and then an optional, -driver-specific error message. +Both UEs and CEs with no info will lack all but memory controller, error +type, a notice of "no info" and then an optional, driver-specific error +message. -============================================================================ PCI Bus Parity Detection +------------------------ - -On Header Type 00 devices the primary status is looked at -for any parity error regardless of whether Parity is enabled on the -device. (The spec indicates parity is generated in some cases). -On Header Type 01 bridges, the secondary status register is also -looked at to see if parity occurred on the bus on the other side of -the bridge. +On Header Type 00 devices, the primary status is looked at for any +parity error regardless of whether parity is enabled on the device or +not. (The spec indicates parity is generated in some cases). On Header +Type 01 bridges, the secondary status register is also looked at to see +if parity occurred on the bus on the other side of the bridge. SYSFS CONFIGURATION +------------------- Under /sys/devices/system/edac/pci are control and attribute files as follows: @@ -450,8 +418,9 @@ Parity Count: have been detected. -============================================================================ + MODULE PARAMETERS +----------------- Panic on UE control file: @@ -530,10 +499,8 @@ Panic on PCI PARITY Error: -======================================================================= - - -EDAC_DEVICE type of device +EDAC device type +---------------- In the header file, edac_core.h, there is a series of edac_device structures and APIs for the EDAC_DEVICE. @@ -573,6 +540,7 @@ The test_device_edac device adds at least one of its own custom control: The symlink points to the 'struct dev' that is registered for this edac_device. INSTANCES +--------- One or more instance directories are present. For the 'test_device_edac' case: @@ -586,6 +554,7 @@ counter in deeper subdirectories. ue_count total of UE events of subdirectories BLOCKS +------ At the lowest directory level is the 'block' directory. There can be 0, 1 or more blocks specified in each instance. @@ -623,8 +592,9 @@ unique drivers for their hardware systems. The 'test_device_edac' sample driver is located at the bluesmoke.sourceforge.net project site for EDAC. -======================================================================= + NEHALEM USAGE OF EDAC APIs +-------------------------- This chapter documents some EXPERIMENTAL mappings for EDAC API to handle Nehalem EDAC driver. They will likely be changed on future versions @@ -773,3 +743,20 @@ exports one by the driver. Since, with udimm, this is counted by software, it is possible that some errors could be lost. With rdimm's, they display the contents of the registers + +CREDITS: +======== + +Written by Doug Thompson +7 Dec 2005 +17 Jul 2007 Updated + +(c) Mauro Carvalho Chehab +05 Aug 2009 Nehalem interface + +EDAC authors/maintainers: + + Doug Thompson, Dave Jiang, Dave Peterson et al, + Mauro Carvalho Chehab + Borislav Petkov + original author: Thayne Harbaugh -- cgit v1.2.3 From 4be1f6bbd1e968ab02653c28eababd9480dfff77 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 13 Jun 2015 12:34:04 +0200 Subject: rtc: hym8563: make the irq optional Sometimes the irq line is not connected to any soc-pin. This does not hinder basic timekeeping functionality of the rtc, so probe should not fail in this case. Signed-off-by: Heiko Stuebner Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/haoyu,hym8563.txt | 2 +- drivers/rtc/rtc-hym8563.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt b/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt index 5c199ee044cb..a8934fe2ab4c 100644 --- a/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt +++ b/Documentation/devicetree/bindings/rtc/haoyu,hym8563.txt @@ -6,11 +6,11 @@ as well as a clock output of up to 32kHz. Required properties: - compatible: should be: "haoyu,hym8563" - reg: i2c address -- interrupts: rtc alarm/event interrupt - #clock-cells: the value should be 0 Optional properties: - clock-output-names: From common clock binding +- interrupts: rtc alarm/event interrupt Example: diff --git a/drivers/rtc/rtc-hym8563.c b/drivers/rtc/rtc-hym8563.c index 0f710e98538f..e9da7959d3fe 100644 --- a/drivers/rtc/rtc-hym8563.c +++ b/drivers/rtc/rtc-hym8563.c @@ -548,14 +548,16 @@ static int hym8563_probe(struct i2c_client *client, return ret; } - ret = devm_request_threaded_irq(&client->dev, client->irq, - NULL, hym8563_irq, - IRQF_TRIGGER_LOW | IRQF_ONESHOT, - client->name, hym8563); - if (ret < 0) { - dev_err(&client->dev, "irq %d request failed, %d\n", - client->irq, ret); - return ret; + if (client->irq > 0) { + ret = devm_request_threaded_irq(&client->dev, client->irq, + NULL, hym8563_irq, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + client->name, hym8563); + if (ret < 0) { + dev_err(&client->dev, "irq %d request failed, %d\n", + client->irq, ret); + return ret; + } } /* check state of calendar information */ -- cgit v1.2.3 From 5fa2daaa8d8223d06fcdba171a7a668dc8e8b179 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 9 Mar 2015 14:33:40 +0530 Subject: ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores Cc: Grant Likely Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Vineet Gupta --- Documentation/devicetree/bindings/arc/axs103.txt | 8 + arch/arc/boot/dts/axc003.dtsi | 102 ++++++++++++ arch/arc/boot/dts/axc003_idu.dtsi | 126 +++++++++++++++ arch/arc/boot/dts/axs103.dts | 24 +++ arch/arc/boot/dts/axs103_idu.dts | 24 +++ arch/arc/configs/axs103_defconfig | 117 ++++++++++++++ arch/arc/configs/axs103_smp_defconfig | 118 ++++++++++++++ arch/arc/kernel/devtree.c | 2 +- arch/arc/plat-axs10x/Kconfig | 13 +- arch/arc/plat-axs10x/axs10x.c | 198 +++++++++++++++++++++-- 10 files changed, 720 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/arc/axs103.txt create mode 100644 arch/arc/boot/dts/axc003.dtsi create mode 100644 arch/arc/boot/dts/axc003_idu.dtsi create mode 100644 arch/arc/boot/dts/axs103.dts create mode 100644 arch/arc/boot/dts/axs103_idu.dts create mode 100644 arch/arc/configs/axs103_defconfig create mode 100644 arch/arc/configs/axs103_smp_defconfig (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arc/axs103.txt b/Documentation/devicetree/bindings/arc/axs103.txt new file mode 100644 index 000000000000..6eea862e72b9 --- /dev/null +++ b/Documentation/devicetree/bindings/arc/axs103.txt @@ -0,0 +1,8 @@ +Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings +--------------------------------------------------------------------------- + +SDP Main Board with an AXC003 FPGA Card which can contain various flavours of +HS38x cores. + +Required root node properties: + - compatible = "snps,axs103", "snps,arc-sdp"; diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi new file mode 100644 index 000000000000..15c8d6226c9d --- /dev/null +++ b/arch/arc/boot/dts/axc003.dtsi @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC003 CPU card: HS38x UP configuration + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <75000000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: archs-intc@cpu { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + /* + * this GPIO block ORs all interrupts on CPU card (creg,..) + * to uplink only 1 IRQ to ARC core intc + */ + dw-apb-gpio@0x2000 { + compatible = "snps,dw-apb-gpio"; + reg = < 0x2000 0x80 >; + #address-cells = <1>; + #size-cells = <0>; + + ictl_intc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&cpu_intc>; + interrupts = <25>; + }; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <33333000>; + interrupt-parent = <&ictl_intc>; + interrupts = <2 4>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupt-parent = <&cpu_intc>; + interrupts = <20>; + }; + }; + + /* + * This INTC is actually connected to DW APB GPIO + * which acts as a wire between MB INTC and CPU INTC. + * GPIO INTC is configured in platform init code + * and here we mimic direct connection from MB INTC to + * CPU INTC, thus we set "interrupts = <7>" instead of + * "interrupts = <12>" + * + * This intc actually resides on MB, but we move it here to + * avoid duplicating the MB dtsi file given that IRQ from + * this intc to cpu intc are different for axs101 and axs103 + */ + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + interrupts = < 24 >; + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi new file mode 100644 index 000000000000..199d42820eca --- /dev/null +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <75000000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: archs-intc@cpu { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + /* + * upstream irqs to core intc - downstream these are + * "COMMON" irq 0,1.. + */ + interrupts = <24 25>; + }; + + /* + * this GPIO block ORs all interrupts on CPU card (creg,..) + * to uplink only 1 IRQ to ARC core intc + */ + dw-apb-gpio@0x2000 { + compatible = "snps,dw-apb-gpio"; + reg = < 0x2000 0x80 >; + #address-cells = <1>; + #size-cells = <0>; + + ictl_intc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&idu_intc>; + + /* + * cmn irq 1 -> cpu irq 25 + * Distribute to cpu0 only + */ + interrupts = <1 1>; + }; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <33333000>; + interrupt-parent = <&ictl_intc>; + interrupts = <2 4>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupt-parent = <&cpu_intc>; + interrupts = <20>; + }; + }; + + /* + * This INTC is actually connected to DW APB GPIO + * which acts as a wire between MB INTC and CPU INTC. + * GPIO INTC is configured in platform init code + * and here we mimic direct connection from MB INTC to + * CPU INTC, thus we set "interrupts = <0 1>" instead of + * "interrupts = <12>" + * + * This intc actually resides on MB, but we move it here to + * avoid duplicating the MB dtsi file given that IRQ from + * this intc to cpu intc are different for axs101 and axs103 + */ + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&idu_intc>; + interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24 + distribute to cpu0 only */ + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/arch/arc/boot/dts/axs103.dts b/arch/arc/boot/dts/axs103.dts new file mode 100644 index 000000000000..e6d0e31ea299 --- /dev/null +++ b/arch/arc/boot/dts/axs103.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device Tree for AXS103 SDP with AXS10X Main Board and + * AXC003 FPGA Card (with UP bitfile) + */ +/dts-v1/; + +/include/ "axc003.dtsi" +/include/ "axs10x_mb.dtsi" + +/ { + compatible = "snps,axs103", "snps,arc-sdp"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + }; +}; diff --git a/arch/arc/boot/dts/axs103_idu.dts b/arch/arc/boot/dts/axs103_idu.dts new file mode 100644 index 000000000000..f999fef5a60a --- /dev/null +++ b/arch/arc/boot/dts/axs103_idu.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device Tree for AXS103 SDP with AXS10X Main Board and + * AXC003 FPGA Card (with SMP bitfile) + */ +/dts-v1/; + +/include/ "axc003_idu.dtsi" +/include/ "axs10x_mb.dtsi" + +/ { + compatible = "snps,axs103", "snps,arc-sdp"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + }; +}; diff --git a/arch/arc/configs/axs103_defconfig b/arch/arc/configs/axs103_defconfig new file mode 100644 index 000000000000..83a6d8d5cc58 --- /dev/null +++ b/arch/arc/configs/axs103_defconfig @@ -0,0 +1,117 @@ +CONFIG_CROSS_COMPILE="arc-linux-uclibc-" +CONFIG_DEFAULT_HOSTNAME="ARCLinux" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/" +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARC_PLAT_AXS10X=y +CONFIG_AXS103=y +CONFIG_ISA_ARCV2=y +CONFIG_ARC_BUILTIN_DTB_NAME="axs103" +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AXS=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_STMMAC_ETH=y +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NATIONAL_PHY=y +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_INPUT_EVDEV=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=y +CONFIG_MOUSE_SYNAPTICS_USB=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_HWMON is not set +CONFIG_FB=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig new file mode 100644 index 000000000000..f1e1c84e0dda --- /dev/null +++ b/arch/arc/configs/axs103_smp_defconfig @@ -0,0 +1,118 @@ +CONFIG_CROSS_COMPILE="arc-linux-uclibc-" +CONFIG_DEFAULT_HOSTNAME="ARCLinux" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/" +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARC_PLAT_AXS10X=y +CONFIG_AXS103=y +CONFIG_ISA_ARCV2=y +CONFIG_SMP=y +CONFIG_ARC_BUILTIN_DTB_NAME="axs103_idu" +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AXS=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_STMMAC_ETH=y +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NATIONAL_PHY=y +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_INPUT_EVDEV=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=y +CONFIG_MOUSE_SYNAPTICS_USB=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_HWMON is not set +CONFIG_FB=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c index f801d46dc087..7e844fd8213f 100644 --- a/arch/arc/kernel/devtree.c +++ b/arch/arc/kernel/devtree.c @@ -33,7 +33,7 @@ static void __init arc_set_early_base_baud(unsigned long dt_root) if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x")) arc_base_baud = core_clk/3; else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp")) - arc_base_baud = 33333333; /* Fixed 33MHz clk */ + arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */ else arc_base_baud = core_clk; } diff --git a/arch/arc/plat-axs10x/Kconfig b/arch/arc/plat-axs10x/Kconfig index 45641ca8aba8..d475f9d4847c 100644 --- a/arch/arc/plat-axs10x/Kconfig +++ b/arch/arc/plat-axs10x/Kconfig @@ -6,7 +6,7 @@ # published by the Free Software Foundation. # -config ARC_PLAT_AXS10X +menuconfig ARC_PLAT_AXS10X bool "Synopsys ARC AXS10x Software Development Platforms" select DW_APB_ICTL select GPIO_DWAPB @@ -23,6 +23,7 @@ config ARC_PLAT_AXS10X if ARC_PLAT_AXS10X config AXS101 + depends on ISA_ARCOMPACT bool "AXS101 with AXC001 CPU Card (ARC 770D/EM6/AS221)" help This adds support for the 770D/EM6/AS221 CPU Card. Only the ARC @@ -32,4 +33,14 @@ config AXS101 this daughtercard. Please use the axs101.dts device tree with this configuration. +config AXS103 + bool "AXS103 with AXC003 CPU Card (ARC HS38x)" + depends on ISA_ARCV2 + help + This adds support for the HS38x CPU Card. + + The AXS103 Platform consists of an AXS10x mainboard with + this daughtercard. Please use the axs103.dts device tree + with this configuration. + endif diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index a1cecdaf9dca..ad0a7ef84660 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -1,5 +1,5 @@ /* - * AXS101 Software Development Platform + * AXS101/AXS103 Software Development Platform * * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) * @@ -15,8 +15,10 @@ */ #include -#include +#include #include +#include +#include #define AXS_MB_CGU 0xE0010000 #define AXS_MB_CREG 0xE0011000 @@ -29,14 +31,6 @@ #define AXC001_CREG 0xF0001000 #define AXC001_GPIO_INTC 0xF0003000 -#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20) -#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60) -#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34) -#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74) - -#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114) -#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120) - static void __init axs10x_enable_gpio_intc_wire(void) { /* @@ -83,6 +77,22 @@ static void __init axs10x_enable_gpio_intc_wire(void) iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN); } +static inline void __init +write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg) +{ + unsigned int loops = 128 * 1024, ctr; + + iowrite32(value, reg); + + ctr = loops; + while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */ + cpu_relax(); + + ctr = loops; + while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */ + cpu_relax(); +} + static void __init axs10x_print_board_ver(unsigned int creg, const char *str) { union ver { @@ -118,6 +128,16 @@ static void __init axs10x_early_init(void) axs10x_print_board_ver(CREG_MB_VER, mb); } +#ifdef CONFIG_AXS101 + +#define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20) +#define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60) +#define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34) +#define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74) + +#define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114) +#define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120) + /* * Set up System Memory Map for ARC cpu / peripherals controllers * @@ -287,6 +307,145 @@ static void __init axs101_early_init(void) axs10x_early_init(); } +#endif /* CONFIG_AXS101 */ + +#ifdef CONFIG_AXS103 + +#define AXC003_CGU 0xF0000000 +#define AXC003_CREG 0xF0001000 +#define AXC003_MST_AXI_TUNNEL 0 +#define AXC003_MST_HS38 1 + +#define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440) +#define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480) +#define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494) + + +union pll_reg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6; +#else + unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17; +#endif + }; + unsigned int val; +}; + +static unsigned int __init axs103_get_freq(void) +{ + union pll_reg idiv, fbdiv, odiv; + unsigned int f = 33333333; + + idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0); + fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4); + odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8); + + if (idiv.bypass != 1) + f = f / (idiv.low + idiv.high); + + if (fbdiv.bypass != 1) + f = f * (fbdiv.low + fbdiv.high); + + if (odiv.bypass != 1) + f = f / (odiv.low + odiv.high); + + f = (f + 500000) / 1000000; /* Rounding */ + return f; +} + +static inline unsigned int __init encode_div(unsigned int id, int upd) +{ + union pll_reg div; + + div.val = 0; + + div.noupd = !upd; + div.bypass = id == 1 ? 1 : 0; + div.edge = (id%2 == 0) ? 0 : 1; /* 0 = rising */ + div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1; + div.high = id >> 1; + + return div.val; +} + +noinline static void __init +axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) +{ + write_cgu_reg(encode_div(id, 0), + (void __iomem *)AXC003_CGU + 0x80 + 0, + (void __iomem *)AXC003_CGU + 0x110); + + write_cgu_reg(encode_div(fd, 0), + (void __iomem *)AXC003_CGU + 0x80 + 4, + (void __iomem *)AXC003_CGU + 0x110); + + write_cgu_reg(encode_div(od, 1), + (void __iomem *)AXC003_CGU + 0x80 + 8, + (void __iomem *)AXC003_CGU + 0x110); +} + +static void __init axs103_early_init(void) +{ + switch (arc_get_core_freq()/1000000) { + case 33: + axs103_set_freq(1, 1, 1); + break; + case 50: + axs103_set_freq(1, 30, 20); + break; + case 75: + axs103_set_freq(2, 45, 10); + break; + case 90: + axs103_set_freq(2, 54, 10); + break; + case 100: + axs103_set_freq(1, 30, 10); + break; + case 125: + axs103_set_freq(2, 45, 6); + break; + default: + /* + * In this case, core_frequency derived from + * DT "clock-frequency" might not match with board value. + * Hence update it to match the board value. + */ + arc_set_core_freq(axs103_get_freq() * 1000000); + break; + } + + pr_info("Freq is %dMHz\n", axs103_get_freq()); + + /* Memory maps already config in pre-bootloader */ + + /* set GPIO mux to UART */ + iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); + + iowrite32((0x00100000U | 0x000C0000U | 0x00003322U), + (void __iomem *) CREG_CPU_TUN_IO_CTRL); + + /* Set up the AXS_MB interrupt system.*/ + iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX + + (AXC003_MST_HS38 << 2))); + + /* connect ICTL - Main Board with GPIO line */ + iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); + + axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card"); + + axs10x_early_init(); + +#ifdef CONFIG_ARC_MCIP + /* No Hardware init, but filling the smp ops callbacks */ + mcip_init_early_smp(); +#endif +} +#endif + +#ifdef CONFIG_AXS101 + static const char *axs101_compat[] __initconst = { "snps,axs101", NULL, @@ -296,3 +455,22 @@ MACHINE_START(AXS101, "axs101") .dt_compat = axs101_compat, .init_early = axs101_early_init, MACHINE_END + +#endif /* CONFIG_AXS101 */ + +#ifdef CONFIG_AXS103 + +static const char *axs103_compat[] __initconst = { + "snps,axs103", + NULL, +}; + +MACHINE_START(AXS103, "axs103") + .dt_compat = axs103_compat, + .init_early = axs103_early_init, +#ifdef CONFIG_ARC_MCIP + .init_smp = mcip_init_smp, +#endif +MACHINE_END + +#endif /* CONFIG_AXS103 */ -- cgit v1.2.3 From fe4ba3c34352b7e8068b7f18eb233444aed17011 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Wed, 24 Jun 2015 16:55:45 -0700 Subject: watchdog: add watchdog_cpumask sysctl to assist nohz Change the default behavior of watchdog so it only runs on the housekeeping cores when nohz_full is enabled at build and boot time. Allow modifying the set of cores the watchdog is currently running on with a new kernel.watchdog_cpumask sysctl. In the current system, the watchdog subsystem runs a periodic timer that schedules the watchdog kthread to run. However, nohz_full cores are designed to allow userspace application code running on those cores to have 100% access to the CPU. So the watchdog system prevents the nohz_full application code from being able to run the way it wants to, thus the motivation to suppress the watchdog on nohz_full cores, which this patchset provides by default. However, if we disable the watchdog globally, then the housekeeping cores can't benefit from the watchdog functionality. So we allow disabling it only on some cores. See Documentation/lockup-watchdogs.txt for more information. [jhubbard@nvidia.com: fix a watchdog crash in some configurations] Signed-off-by: Chris Metcalf Acked-by: Don Zickus Cc: Ingo Molnar Cc: Ulrich Obergfell Cc: Thomas Gleixner Cc: Peter Zijlstra Cc: Frederic Weisbecker Signed-off-by: John Hubbard Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/lockup-watchdogs.txt | 18 ++++++++++ Documentation/sysctl/kernel.txt | 21 ++++++++++++ include/linux/nmi.h | 3 ++ kernel/smpboot.c | 1 + kernel/sysctl.c | 7 ++++ kernel/watchdog.c | 67 +++++++++++++++++++++++++++++++++++--- 6 files changed, 112 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/lockup-watchdogs.txt b/Documentation/lockup-watchdogs.txt index ab0baa692c13..22dd6af2e4bd 100644 --- a/Documentation/lockup-watchdogs.txt +++ b/Documentation/lockup-watchdogs.txt @@ -61,3 +61,21 @@ As explained above, a kernel knob is provided that allows administrators to configure the period of the hrtimer and the perf event. The right value for a particular environment is a trade-off between fast response to lockups and detection overhead. + +By default, the watchdog runs on all online cores. However, on a +kernel configured with NO_HZ_FULL, by default the watchdog runs only +on the housekeeping cores, not the cores specified in the "nohz_full" +boot argument. If we allowed the watchdog to run by default on +the "nohz_full" cores, we would have to run timer ticks to activate +the scheduler, which would prevent the "nohz_full" functionality +from protecting the user code on those cores from the kernel. +Of course, disabling it by default on the nohz_full cores means that +when those cores do enter the kernel, by default we will not be +able to detect if they lock up. However, allowing the watchdog +to continue to run on the housekeeping (non-tickless) cores means +that we will continue to detect lockups properly on those cores. + +In either case, the set of cores excluded from running the watchdog +may be adjusted via the kernel.watchdog_cpumask sysctl. For +nohz_full cores, this may be useful for debugging a case where the +kernel seems to be hanging on the nohz_full cores. diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt index c831001c45f1..e5d528e0c46e 100644 --- a/Documentation/sysctl/kernel.txt +++ b/Documentation/sysctl/kernel.txt @@ -923,6 +923,27 @@ and nmi_watchdog. ============================================================== +watchdog_cpumask: + +This value can be used to control on which cpus the watchdog may run. +The default cpumask is all possible cores, but if NO_HZ_FULL is +enabled in the kernel config, and cores are specified with the +nohz_full= boot argument, those cores are excluded by default. +Offline cores can be included in this mask, and if the core is later +brought online, the watchdog will be started based on the mask value. + +Typically this value would only be touched in the nohz_full case +to re-enable cores that by default were not running the watchdog, +if a kernel lockup was suspected on those cores. + +The argument value is the standard cpulist format for cpumasks, +so for example to enable the watchdog on cores 0, 2, 3, and 4 you +might say: + + echo 0,2-4 > /proc/sys/kernel/watchdog_cpumask + +============================================================== + watchdog_thresh: This value can be used to control the frequency of hrtimer and NMI diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 3d46fb4708e0..f94da0e65dea 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -67,6 +67,7 @@ extern int nmi_watchdog_enabled; extern int soft_watchdog_enabled; extern int watchdog_user_enabled; extern int watchdog_thresh; +extern unsigned long *watchdog_cpumask_bits; extern int sysctl_softlockup_all_cpu_backtrace; struct ctl_table; extern int proc_watchdog(struct ctl_table *, int , @@ -77,6 +78,8 @@ extern int proc_soft_watchdog(struct ctl_table *, int , void __user *, size_t *, loff_t *); extern int proc_watchdog_thresh(struct ctl_table *, int , void __user *, size_t *, loff_t *); +extern int proc_watchdog_cpumask(struct ctl_table *, int, + void __user *, size_t *, loff_t *); #endif #ifdef CONFIG_HAVE_ACPI_APEI_NMI diff --git a/kernel/smpboot.c b/kernel/smpboot.c index 5e46c2a75d59..7c434c39f02a 100644 --- a/kernel/smpboot.c +++ b/kernel/smpboot.c @@ -338,6 +338,7 @@ EXPORT_SYMBOL_GPL(smpboot_unregister_percpu_thread); * * The cpumask field in the smp_hotplug_thread must not be updated directly * by the client, but only by calling this function. + * This function can only be called on a registered smp_hotplug_thread. */ int smpboot_update_cpumask_percpu_thread(struct smp_hotplug_thread *plug_thread, const struct cpumask *new) diff --git a/kernel/sysctl.c b/kernel/sysctl.c index b13e9d2de302..812fcc3fd390 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -871,6 +871,13 @@ static struct ctl_table kern_table[] = { .extra1 = &zero, .extra2 = &one, }, + { + .procname = "watchdog_cpumask", + .data = &watchdog_cpumask_bits, + .maxlen = NR_CPUS, + .mode = 0644, + .proc_handler = proc_watchdog_cpumask, + }, { .procname = "softlockup_panic", .data = &softlockup_panic, diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 581a68a04c64..a6ffa43f2993 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -58,6 +59,12 @@ int __read_mostly sysctl_softlockup_all_cpu_backtrace; #else #define sysctl_softlockup_all_cpu_backtrace 0 #endif +static struct cpumask watchdog_cpumask __read_mostly; +unsigned long *watchdog_cpumask_bits = cpumask_bits(&watchdog_cpumask); + +/* Helper for online, unparked cpus. */ +#define for_each_watchdog_cpu(cpu) \ + for_each_cpu_and((cpu), cpu_online_mask, &watchdog_cpumask) static int __read_mostly watchdog_running; static u64 __read_mostly sample_period; @@ -207,7 +214,7 @@ void touch_all_softlockup_watchdogs(void) * do we care if a 0 races with a timestamp? * all it means is the softlock check starts one cycle later */ - for_each_online_cpu(cpu) + for_each_watchdog_cpu(cpu) per_cpu(watchdog_touch_ts, cpu) = 0; } @@ -616,7 +623,7 @@ void watchdog_nmi_enable_all(void) goto unlock; get_online_cpus(); - for_each_online_cpu(cpu) + for_each_watchdog_cpu(cpu) watchdog_nmi_enable(cpu); put_online_cpus(); @@ -634,7 +641,7 @@ void watchdog_nmi_disable_all(void) goto unlock; get_online_cpus(); - for_each_online_cpu(cpu) + for_each_watchdog_cpu(cpu) watchdog_nmi_disable(cpu); put_online_cpus(); @@ -696,7 +703,7 @@ static void update_watchdog_all_cpus(void) int cpu; get_online_cpus(); - for_each_online_cpu(cpu) + for_each_watchdog_cpu(cpu) update_watchdog(cpu); put_online_cpus(); } @@ -709,8 +716,12 @@ static int watchdog_enable_all_cpus(void) err = smpboot_register_percpu_thread(&watchdog_threads); if (err) pr_err("Failed to create watchdog threads, disabled\n"); - else + else { + if (smpboot_update_cpumask_percpu_thread( + &watchdog_threads, &watchdog_cpumask)) + pr_err("Failed to set cpumask for watchdog threads\n"); watchdog_running = 1; + } } else { /* * Enable/disable the lockup detectors or @@ -879,12 +890,58 @@ out: mutex_unlock(&watchdog_proc_mutex); return err; } + +/* + * The cpumask is the mask of possible cpus that the watchdog can run + * on, not the mask of cpus it is actually running on. This allows the + * user to specify a mask that will include cpus that have not yet + * been brought online, if desired. + */ +int proc_watchdog_cpumask(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) +{ + int err; + + mutex_lock(&watchdog_proc_mutex); + err = proc_do_large_bitmap(table, write, buffer, lenp, ppos); + if (!err && write) { + /* Remove impossible cpus to keep sysctl output cleaner. */ + cpumask_and(&watchdog_cpumask, &watchdog_cpumask, + cpu_possible_mask); + + if (watchdog_running) { + /* + * Failure would be due to being unable to allocate + * a temporary cpumask, so we are likely not in a + * position to do much else to make things better. + */ + if (smpboot_update_cpumask_percpu_thread( + &watchdog_threads, &watchdog_cpumask) != 0) + pr_err("cpumask update failed\n"); + } + } + mutex_unlock(&watchdog_proc_mutex); + return err; +} + #endif /* CONFIG_SYSCTL */ void __init lockup_detector_init(void) { set_sample_period(); +#ifdef CONFIG_NO_HZ_FULL + if (tick_nohz_full_enabled()) { + if (!cpumask_empty(tick_nohz_full_mask)) + pr_info("Disabling watchdog on nohz_full cores by default\n"); + cpumask_andnot(&watchdog_cpumask, cpu_possible_mask, + tick_nohz_full_mask); + } else + cpumask_copy(&watchdog_cpumask, cpu_possible_mask); +#else + cpumask_copy(&watchdog_cpumask, cpu_possible_mask); +#endif + if (watchdog_enabled) watchdog_enable_all_cpus(); } -- cgit v1.2.3 From 9b012a29a300ea780d919205906d00d15cc6286e Mon Sep 17 00:00:00 2001 From: Michal Hocko Date: Wed, 24 Jun 2015 16:57:50 -0700 Subject: Documentation/vm/unevictable-lru.txt: clarify MAP_LOCKED behavior There is a very subtle difference between mmap()+mlock() vs mmap(MAP_LOCKED) semantic. The former one fails if the population of the area fails while the later one doesn't. This basically means that mmap(MAPLOCKED) areas might see major fault after mmap syscall returns which is not the case for mlock. mmap man page has already been altered but Documentation/vm/unevictable-lru.txt deserves a clarification as well. Signed-off-by: Michal Hocko Reported-by: David Rientjes Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/vm/unevictable-lru.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/vm/unevictable-lru.txt b/Documentation/vm/unevictable-lru.txt index 3be0bfc4738d..32ee3a67dba2 100644 --- a/Documentation/vm/unevictable-lru.txt +++ b/Documentation/vm/unevictable-lru.txt @@ -467,7 +467,13 @@ mmap(MAP_LOCKED) SYSTEM CALL HANDLING In addition the mlock()/mlockall() system calls, an application can request that a region of memory be mlocked supplying the MAP_LOCKED flag to the mmap() -call. Furthermore, any mmap() call or brk() call that expands the heap by a +call. There is one important and subtle difference here, though. mmap() + mlock() +will fail if the range cannot be faulted in (e.g. because mm_populate fails) +and returns with ENOMEM while mmap(MAP_LOCKED) will not fail. The mmaped +area will still have properties of the locked area - aka. pages will not get +swapped out - but major page faults to fault memory in might still happen. + +Furthermore, any mmap() call or brk() call that expands the heap by a task that has previously called mlockall() with the MCL_FUTURE flag will result in the newly mapped memory being mlocked. Before the unevictable/mlock changes, the kernel simply called make_pages_present() to allocate pages and -- cgit v1.2.3 From d7f96f97c4031fa4ffdb7801f9aae23e96170a6f Mon Sep 17 00:00:00 2001 From: Ivan Khoronzhuk Date: Thu, 25 Jun 2015 09:06:56 +0200 Subject: firmware: dmi_scan: add SBMIOS entry and DMI tables Some utils, like dmidecode and smbios, need to access SMBIOS entry table area in order to get information like SMBIOS version, size, etc. Currently it's done via /dev/mem. But for situation when /dev/mem usage is disabled, the utils have to use dmi sysfs instead, which doesn't represent SMBIOS entry and adds code/delay redundancy when direct access for table is needed. So this patch creates dmi/tables and adds SMBIOS entry point to allow utils in question to work correctly without /dev/mem. Also patch adds raw dmi table to simplify dmi table processing in user space, as proposed by Jean Delvare. Tested-by: Roy Franz Signed-off-by: Ivan Khoronzhuk Signed-off-by: Jean Delvare --- .../ABI/testing/sysfs-firmware-dmi-tables | 22 ++++++ MAINTAINERS | 1 + drivers/firmware/dmi-sysfs.c | 17 +++-- drivers/firmware/dmi_scan.c | 78 ++++++++++++++++++++++ include/linux/dmi.h | 2 + 5 files changed, 111 insertions(+), 9 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-firmware-dmi-tables (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-firmware-dmi-tables b/Documentation/ABI/testing/sysfs-firmware-dmi-tables new file mode 100644 index 000000000000..ff3cac8ed0bd --- /dev/null +++ b/Documentation/ABI/testing/sysfs-firmware-dmi-tables @@ -0,0 +1,22 @@ +What: /sys/firmware/dmi/tables/ +Date: April 2015 +Contact: Ivan Khoronzhuk +Description: + The firmware provides DMI structures as a packed list of + data referenced by a SMBIOS table entry point. The SMBIOS + entry point contains general information, like SMBIOS + version, DMI table size, etc. The structure, content and + size of SMBIOS entry point is dependent on SMBIOS version. + The format of SMBIOS entry point and DMI structures + can be read in SMBIOS specification. + + The dmi/tables provides raw SMBIOS entry point and DMI tables + through sysfs as an alternative to utilities reading them + from /dev/mem. The raw SMBIOS entry point and DMI table are + presented as binary attributes and are accessible via: + + /sys/firmware/dmi/tables/smbios_entry_point + /sys/firmware/dmi/tables/DMI + + The complete DMI information can be obtained using these two + tables. diff --git a/MAINTAINERS b/MAINTAINERS index 0502f9a7087f..ca473689d0f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3289,6 +3289,7 @@ DMI/SMBIOS SUPPORT M: Jean Delvare S: Maintained T: quilt http://jdelvare.nerim.net/devel/linux/jdelvare-dmi/ +F: Documentation/ABI/testing/sysfs-firmware-dmi-tables F: drivers/firmware/dmi-id.c F: drivers/firmware/dmi_scan.c F: include/linux/dmi.h diff --git a/drivers/firmware/dmi-sysfs.c b/drivers/firmware/dmi-sysfs.c index e0f1cb3d3598..ef76e5eecf0b 100644 --- a/drivers/firmware/dmi-sysfs.c +++ b/drivers/firmware/dmi-sysfs.c @@ -566,7 +566,6 @@ static struct kobj_type dmi_sysfs_entry_ktype = { .default_attrs = dmi_sysfs_entry_attrs, }; -static struct kobject *dmi_kobj; static struct kset *dmi_kset; /* Global count of all instances seen. Only for setup */ @@ -648,17 +647,20 @@ static void cleanup_entry_list(void) static int __init dmi_sysfs_init(void) { - int error = -ENOMEM; + int error; int val; - /* Set up our directory */ - dmi_kobj = kobject_create_and_add("dmi", firmware_kobj); - if (!dmi_kobj) + if (!dmi_kobj) { + pr_err("dmi-sysfs: dmi entry is absent.\n"); + error = -ENODATA; goto err; + } dmi_kset = kset_create_and_add("entries", NULL, dmi_kobj); - if (!dmi_kset) + if (!dmi_kset) { + error = -ENOMEM; goto err; + } val = 0; error = dmi_walk(dmi_sysfs_register_handle, &val); @@ -675,7 +677,6 @@ static int __init dmi_sysfs_init(void) err: cleanup_entry_list(); kset_unregister(dmi_kset); - kobject_put(dmi_kobj); return error; } @@ -685,8 +686,6 @@ static void __exit dmi_sysfs_exit(void) pr_debug("dmi-sysfs: unloading.\n"); cleanup_entry_list(); kset_unregister(dmi_kset); - kobject_del(dmi_kobj); - kobject_put(dmi_kobj); } module_init(dmi_sysfs_init); diff --git a/drivers/firmware/dmi_scan.c b/drivers/firmware/dmi_scan.c index 7fdf2868a276..5e0b770fdae5 100644 --- a/drivers/firmware/dmi_scan.c +++ b/drivers/firmware/dmi_scan.c @@ -10,6 +10,9 @@ #include #include +struct kobject *dmi_kobj; +EXPORT_SYMBOL_GPL(dmi_kobj); + /* * DMI stands for "Desktop Management Interface". It is part * of and an antecedent to, SMBIOS, which stands for System @@ -20,6 +23,9 @@ static const char dmi_empty_string[] = " "; static u32 dmi_ver __initdata; static u32 dmi_len; static u16 dmi_num; +static u8 smbios_entry_point[32]; +static int smbios_entry_point_size; + /* * Catch too early calls to dmi_check_system(): */ @@ -488,6 +494,8 @@ static int __init dmi_present(const u8 *buf) if (memcmp(buf, "_SM_", 4) == 0 && buf[5] < 32 && dmi_checksum(buf, buf[5])) { smbios_ver = get_unaligned_be16(buf + 6); + smbios_entry_point_size = buf[5]; + memcpy(smbios_entry_point, buf, smbios_entry_point_size); /* Some BIOS report weird SMBIOS version, fix that up */ switch (smbios_ver) { @@ -522,6 +530,9 @@ static int __init dmi_present(const u8 *buf) pr_info("SMBIOS %d.%d present.\n", dmi_ver >> 8, dmi_ver & 0xFF); } else { + smbios_entry_point_size = 15; + memcpy(smbios_entry_point, buf, + smbios_entry_point_size); pr_info("Legacy DMI %d.%d present.\n", dmi_ver >> 8, dmi_ver & 0xFF); } @@ -548,6 +559,8 @@ static int __init dmi_smbios3_present(const u8 *buf) dmi_num = 0; /* No longer specified */ dmi_len = get_unaligned_le32(buf + 12); dmi_base = get_unaligned_le64(buf + 16); + smbios_entry_point_size = buf[6]; + memcpy(smbios_entry_point, buf, smbios_entry_point_size); if (dmi_walk_early(dmi_decode) == 0) { pr_info("SMBIOS %d.%d.%d present.\n", @@ -639,6 +652,71 @@ void __init dmi_scan_machine(void) dmi_initialized = 1; } +static ssize_t raw_table_read(struct file *file, struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t pos, size_t count) +{ + memcpy(buf, attr->private + pos, count); + return count; +} + +static BIN_ATTR(smbios_entry_point, S_IRUSR, raw_table_read, NULL, 0); +static BIN_ATTR(DMI, S_IRUSR, raw_table_read, NULL, 0); + +static int __init dmi_init(void) +{ + struct kobject *tables_kobj; + u8 *dmi_table; + int ret = -ENOMEM; + + if (!dmi_available) { + ret = -ENODATA; + goto err; + } + + /* + * Set up dmi directory at /sys/firmware/dmi. This entry should stay + * even after farther error, as it can be used by other modules like + * dmi-sysfs. + */ + dmi_kobj = kobject_create_and_add("dmi", firmware_kobj); + if (!dmi_kobj) + goto err; + + tables_kobj = kobject_create_and_add("tables", dmi_kobj); + if (!tables_kobj) + goto err; + + dmi_table = dmi_remap(dmi_base, dmi_len); + if (!dmi_table) + goto err_tables; + + bin_attr_smbios_entry_point.size = smbios_entry_point_size; + bin_attr_smbios_entry_point.private = smbios_entry_point; + ret = sysfs_create_bin_file(tables_kobj, &bin_attr_smbios_entry_point); + if (ret) + goto err_unmap; + + bin_attr_DMI.size = dmi_len; + bin_attr_DMI.private = dmi_table; + ret = sysfs_create_bin_file(tables_kobj, &bin_attr_DMI); + if (!ret) + return 0; + + sysfs_remove_bin_file(tables_kobj, + &bin_attr_smbios_entry_point); + err_unmap: + dmi_unmap(dmi_table); + err_tables: + kobject_del(tables_kobj); + kobject_put(tables_kobj); + err: + pr_err("dmi: Firmware registration failed.\n"); + + return ret; +} +subsys_initcall(dmi_init); + /** * dmi_set_dump_stack_arch_desc - set arch description for dump_stack() * diff --git a/include/linux/dmi.h b/include/linux/dmi.h index f820f0a336c9..2f9f98827c0a 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -2,6 +2,7 @@ #define __DMI_H__ #include +#include #include /* enum dmi_field is in mod_devicetable.h */ @@ -93,6 +94,7 @@ struct dmi_dev_onboard { int devfn; }; +extern struct kobject *dmi_kobj; extern int dmi_check_system(const struct dmi_system_id *list); const struct dmi_system_id *dmi_first_match(const struct dmi_system_id *list); extern const char * dmi_get_system_info(int field); -- cgit v1.2.3 From 863ef5ba29529165279562820cd7e6ea0a4f5793 Mon Sep 17 00:00:00 2001 From: Ivan Khoronzhuk Date: Thu, 25 Jun 2015 09:06:57 +0200 Subject: Documentation: ABI: sysfs-firmware-dmi: add -entries suffix to file name The dmi-sysfs module adds DMI table structures entries under /sys/firmware/dmi/entries only, so rename documentation file to sysfs-firmware-dmi-entries as more appropriate. Without renaming it's confusing to differ this from sysfs-firmware-dmi-tables that adds raw DMI table and actually adds "dmi" kobject. Signed-off-by: Ivan Khoronzhuk Signed-off-by: Jean Delvare --- Documentation/ABI/testing/sysfs-firmware-dmi | 110 --------------------- .../ABI/testing/sysfs-firmware-dmi-entries | 110 +++++++++++++++++++++ 2 files changed, 110 insertions(+), 110 deletions(-) delete mode 100644 Documentation/ABI/testing/sysfs-firmware-dmi create mode 100644 Documentation/ABI/testing/sysfs-firmware-dmi-entries (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-firmware-dmi b/Documentation/ABI/testing/sysfs-firmware-dmi deleted file mode 100644 index c78f9ab01e56..000000000000 --- a/Documentation/ABI/testing/sysfs-firmware-dmi +++ /dev/null @@ -1,110 +0,0 @@ -What: /sys/firmware/dmi/ -Date: February 2011 -Contact: Mike Waychison -Description: - Many machines' firmware (x86 and ia64) export DMI / - SMBIOS tables to the operating system. Getting at this - information is often valuable to userland, especially in - cases where there are OEM extensions used. - - The kernel itself does not rely on the majority of the - information in these tables being correct. It equally - cannot ensure that the data as exported to userland is - without error either. - - DMI is structured as a large table of entries, where - each entry has a common header indicating the type and - length of the entry, as well as a firmware-provided - 'handle' that is supposed to be unique amongst all - entries. - - Some entries are required by the specification, but many - others are optional. In general though, users should - never expect to find a specific entry type on their - system unless they know for certain what their firmware - is doing. Machine to machine experiences will vary. - - Multiple entries of the same type are allowed. In order - to handle these duplicate entry types, each entry is - assigned by the operating system an 'instance', which is - derived from an entry type's ordinal position. That is - to say, if there are 'N' multiple entries with the same type - 'T' in the DMI tables (adjacent or spread apart, it - doesn't matter), they will be represented in sysfs as - entries "T-0" through "T-(N-1)": - - Example entry directories: - - /sys/firmware/dmi/entries/17-0 - /sys/firmware/dmi/entries/17-1 - /sys/firmware/dmi/entries/17-2 - /sys/firmware/dmi/entries/17-3 - ... - - Instance numbers are used in lieu of the firmware - assigned entry handles as the kernel itself makes no - guarantees that handles as exported are unique, and - there are likely firmware images that get this wrong in - the wild. - - Each DMI entry in sysfs has the common header values - exported as attributes: - - handle : The 16bit 'handle' that is assigned to this - entry by the firmware. This handle may be - referred to by other entries. - length : The length of the entry, as presented in the - entry itself. Note that this is _not the - total count of bytes associated with the - entry_. This value represents the length of - the "formatted" portion of the entry. This - "formatted" region is sometimes followed by - the "unformatted" region composed of nul - terminated strings, with termination signalled - by a two nul characters in series. - raw : The raw bytes of the entry. This includes the - "formatted" portion of the entry, the - "unformatted" strings portion of the entry, - and the two terminating nul characters. - type : The type of the entry. This value is the same - as found in the directory name. It indicates - how the rest of the entry should be interpreted. - instance: The instance ordinal of the entry for the - given type. This value is the same as found - in the parent directory name. - position: The ordinal position (zero-based) of the entry - within the entirety of the DMI entry table. - - === Entry Specialization === - - Some entry types may have other information available in - sysfs. Not all types are specialized. - - --- Type 15 - System Event Log --- - - This entry allows the firmware to export a log of - events the system has taken. This information is - typically backed by nvram, but the implementation - details are abstracted by this table. This entry's data - is exported in the directory: - - /sys/firmware/dmi/entries/15-0/system_event_log - - and has the following attributes (documented in the - SMBIOS / DMI specification under "System Event Log (Type 15)": - - area_length - header_start_offset - data_start_offset - access_method - status - change_token - access_method_address - header_format - per_log_type_descriptor_length - type_descriptors_supported_count - - As well, the kernel exports the binary attribute: - - raw_event_log : The raw binary bits of the event log - as described by the DMI entry. diff --git a/Documentation/ABI/testing/sysfs-firmware-dmi-entries b/Documentation/ABI/testing/sysfs-firmware-dmi-entries new file mode 100644 index 000000000000..210ad44b95a5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-firmware-dmi-entries @@ -0,0 +1,110 @@ +What: /sys/firmware/dmi/entries/ +Date: February 2011 +Contact: Mike Waychison +Description: + Many machines' firmware (x86 and ia64) export DMI / + SMBIOS tables to the operating system. Getting at this + information is often valuable to userland, especially in + cases where there are OEM extensions used. + + The kernel itself does not rely on the majority of the + information in these tables being correct. It equally + cannot ensure that the data as exported to userland is + without error either. + + DMI is structured as a large table of entries, where + each entry has a common header indicating the type and + length of the entry, as well as a firmware-provided + 'handle' that is supposed to be unique amongst all + entries. + + Some entries are required by the specification, but many + others are optional. In general though, users should + never expect to find a specific entry type on their + system unless they know for certain what their firmware + is doing. Machine to machine experiences will vary. + + Multiple entries of the same type are allowed. In order + to handle these duplicate entry types, each entry is + assigned by the operating system an 'instance', which is + derived from an entry type's ordinal position. That is + to say, if there are 'N' multiple entries with the same type + 'T' in the DMI tables (adjacent or spread apart, it + doesn't matter), they will be represented in sysfs as + entries "T-0" through "T-(N-1)": + + Example entry directories: + + /sys/firmware/dmi/entries/17-0 + /sys/firmware/dmi/entries/17-1 + /sys/firmware/dmi/entries/17-2 + /sys/firmware/dmi/entries/17-3 + ... + + Instance numbers are used in lieu of the firmware + assigned entry handles as the kernel itself makes no + guarantees that handles as exported are unique, and + there are likely firmware images that get this wrong in + the wild. + + Each DMI entry in sysfs has the common header values + exported as attributes: + + handle : The 16bit 'handle' that is assigned to this + entry by the firmware. This handle may be + referred to by other entries. + length : The length of the entry, as presented in the + entry itself. Note that this is _not the + total count of bytes associated with the + entry_. This value represents the length of + the "formatted" portion of the entry. This + "formatted" region is sometimes followed by + the "unformatted" region composed of nul + terminated strings, with termination signalled + by a two nul characters in series. + raw : The raw bytes of the entry. This includes the + "formatted" portion of the entry, the + "unformatted" strings portion of the entry, + and the two terminating nul characters. + type : The type of the entry. This value is the same + as found in the directory name. It indicates + how the rest of the entry should be interpreted. + instance: The instance ordinal of the entry for the + given type. This value is the same as found + in the parent directory name. + position: The ordinal position (zero-based) of the entry + within the entirety of the DMI entry table. + + === Entry Specialization === + + Some entry types may have other information available in + sysfs. Not all types are specialized. + + --- Type 15 - System Event Log --- + + This entry allows the firmware to export a log of + events the system has taken. This information is + typically backed by nvram, but the implementation + details are abstracted by this table. This entry's data + is exported in the directory: + + /sys/firmware/dmi/entries/15-0/system_event_log + + and has the following attributes (documented in the + SMBIOS / DMI specification under "System Event Log (Type 15)": + + area_length + header_start_offset + data_start_offset + access_method + status + change_token + access_method_address + header_format + per_log_type_descriptor_length + type_descriptors_supported_count + + As well, the kernel exports the binary attribute: + + raw_event_log : The raw binary bits of the event log + as described by the DMI entry. -- cgit v1.2.3 From 3d8ed88ba7f612305785fc1f3cefa043f817bb3e Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Thu, 25 Jun 2015 15:00:00 -0700 Subject: zram: add `compact` sysfs entry to documentation We currently don't support zram on-demand device creation. The only way to have N zram devices is to specify num_devices module parameter (default value 1). That means that if, for some reason, at some point, user wants to have N + 1 devies he/she must umount all the existing devices, unload the module, load the module passing num_devices equals to N + 1. This patchset introduces zram-control sysfs class, which has two sysfs attrs: - hot_add -- add a new zram device - hot_remove -- remove a specific (device_id) zram device Usage example: # add a new specific zram device cat /sys/class/zram-control/hot_add 1 # remove a specific zram device echo 4 > /sys/class/zram-control/hot_remove This patch (of 10): Briefly describe missing `compact` sysfs entry. Signed-off-by: Sergey Senozhatsky Acked-by: Minchan Kim Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/blockdev/zram.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/blockdev/zram.txt b/Documentation/blockdev/zram.txt index 48a183e29988..bef499868269 100644 --- a/Documentation/blockdev/zram.txt +++ b/Documentation/blockdev/zram.txt @@ -126,7 +126,7 @@ mem_used_max RW the maximum amount memory zram have consumed to mem_limit RW the maximum amount of memory ZRAM can use to store the compressed data num_migrated RO the number of objects migrated migrated by compaction - +compact WO trigger memory compaction WARNING ======= -- cgit v1.2.3 From c3cdb40e66344553898daa3ccd068c03173a3f42 Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Thu, 25 Jun 2015 15:00:11 -0700 Subject: zram: remove max_num_devices limitation Limiting the number of zram devices to 32 (default max_num_devices value) is confusing, let's drop it. A user with 2TB or 4TB of RAM, for example, can request as many devices as he can handle. Signed-off-by: Sergey Senozhatsky Acked-by: Minchan Kim Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/blockdev/zram.txt | 4 +++- drivers/block/zram/zram_drv.c | 8 +------- drivers/block/zram/zram_drv.h | 6 ------ 3 files changed, 4 insertions(+), 14 deletions(-) (limited to 'Documentation') diff --git a/Documentation/blockdev/zram.txt b/Documentation/blockdev/zram.txt index bef499868269..65e94301e57b 100644 --- a/Documentation/blockdev/zram.txt +++ b/Documentation/blockdev/zram.txt @@ -19,7 +19,9 @@ Following shows a typical sequence of steps for using zram. 1) Load Module: modprobe zram num_devices=4 This creates 4 devices: /dev/zram{0,1,2,3} - (num_devices parameter is optional. Default: 1) + +num_devices parameter is optional and tells zram how many devices should be +pre-created. Default: 1. 2) Set max number of compression streams Compression backend may use up to max_comp_streams compression streams, diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 82bc2ff9bd81..70aac2e564e9 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -1287,12 +1287,6 @@ static int __init zram_init(void) { int ret, dev_id; - if (num_devices > max_num_devices) { - pr_warn("Invalid value for num_devices: %u\n", - num_devices); - return -EINVAL; - } - zram_major = register_blkdev(0, "zram"); if (zram_major <= 0) { pr_warn("Unable to get major number\n"); @@ -1322,7 +1316,7 @@ module_init(zram_init); module_exit(zram_exit); module_param(num_devices, uint, 0); -MODULE_PARM_DESC(num_devices, "Number of zram devices"); +MODULE_PARM_DESC(num_devices, "Number of pre-created zram devices"); MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR("Nitin Gupta "); diff --git a/drivers/block/zram/zram_drv.h b/drivers/block/zram/zram_drv.h index 570c598f4ce9..042994e807cf 100644 --- a/drivers/block/zram/zram_drv.h +++ b/drivers/block/zram/zram_drv.h @@ -20,12 +20,6 @@ #include "zcomp.h" -/* - * Some arbitrary value. This is just to catch - * invalid value for num_devices module parameter. - */ -static const unsigned max_num_devices = 32; - /*-- Configurable parameters */ /* -- cgit v1.2.3 From 6566d1a32bf725a4fa9119f16270505451ad01ac Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Thu, 25 Jun 2015 15:00:24 -0700 Subject: zram: add dynamic device add/remove functionality We currently don't support on-demand device creation. The one and only way to have N zram devices is to specify num_devices module parameter (default value: 1). IOW if, for some reason, at some point, user wants to have N + 1 devies he/she must umount all the existing devices, unload the module, load the module passing num_devices equals to N + 1. And do this again, if needed. This patch introduces zram control sysfs class, which has two sysfs attrs: - hot_add -- add a new zram device - hot_remove -- remove a specific (device_id) zram device hot_add sysfs attr is read-only and has only automatic device id assignment mode (as requested by Minchan Kim). read operation performed on this attr creates a new zram device and returns back its device_id or error status. Usage example: # add a new specific zram device cat /sys/class/zram-control/hot_add 2 # remove a specific zram device echo 4 > /sys/class/zram-control/hot_remove Returning zram_add() error code back to user (-ENOMEM in this case) cat /sys/class/zram-control/hot_add cat: /sys/class/zram-control/hot_add: Cannot allocate memory NOTE, there might be users who already depend on the fact that at least zram0 device gets always created by zram_init(). Preserve this behavior. [minchan@kernel.org: use zram->claim to avoid lockdep splat] Signed-off-by: Sergey Senozhatsky Cc: Minchan Kim Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/ABI/testing/sysfs-class-zram | 24 +++++++ Documentation/blockdev/zram.txt | 23 ++++++- drivers/block/zram/zram_drv.c | 100 ++++++++++++++++++++++++++++- 3 files changed, 141 insertions(+), 6 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-class-zram (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-class-zram b/Documentation/ABI/testing/sysfs-class-zram new file mode 100644 index 000000000000..48ddacbe0e69 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-zram @@ -0,0 +1,24 @@ +What: /sys/class/zram-control/ +Date: August 2015 +KernelVersion: 4.2 +Contact: Sergey Senozhatsky +Description: + The zram-control/ class sub-directory belongs to zram + device class + +What: /sys/class/zram-control/hot_add +Date: August 2015 +KernelVersion: 4.2 +Contact: Sergey Senozhatsky +Description: + RO attribute. Read operation will cause zram to add a new + device and return its device id back to user (so one can + use /dev/zram), or error code. + +What: /sys/class/zram-control/hot_remove +Date: August 2015 +KernelVersion: 4.2 +Contact: Sergey Senozhatsky +Description: + WO attribute. Remove a specific /dev/zramX device, where X + is a device_id provided by user. diff --git a/Documentation/blockdev/zram.txt b/Documentation/blockdev/zram.txt index 65e94301e57b..c4de576093af 100644 --- a/Documentation/blockdev/zram.txt +++ b/Documentation/blockdev/zram.txt @@ -99,7 +99,24 @@ size of the disk when not in use so a huge zram is wasteful. mkfs.ext4 /dev/zram1 mount /dev/zram1 /tmp -7) Stats: +7) Add/remove zram devices + +zram provides a control interface, which enables dynamic (on-demand) device +addition and removal. + +In order to add a new /dev/zramX device, perform read operation on hot_add +attribute. This will return either new device's device id (meaning that you +can use /dev/zram) or error code. + +Example: + cat /sys/class/zram-control/hot_add + 1 + +To remove the existing /dev/zramX device (where X is a device id) +execute + echo X > /sys/class/zram-control/hot_remove + +8) Stats: Per-device statistics are exported as various nodes under /sys/block/zram/ A brief description of exported device attritbutes. For more details please @@ -174,11 +191,11 @@ line of text and contains the following stats separated by whitespace: zero_pages num_migrated -8) Deactivate: +9) Deactivate: swapoff /dev/zram0 umount /dev/zram1 -9) Reset: +10) Reset: Write any positive value to 'reset' sysfs node echo 1 > /sys/block/zram0/reset echo 1 > /sys/block/zram1/reset diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 6a3b36d5bad6..830f0eb501fa 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -29,10 +29,14 @@ #include #include #include +#include #include "zram_drv.h" static DEFINE_IDR(zram_index_idr); +/* idr index must be protected */ +static DEFINE_MUTEX(zram_index_mutex); + static int zram_major; static const char *default_compressor = "lzo"; @@ -1273,24 +1277,104 @@ out_free_dev: return ret; } -static void zram_remove(struct zram *zram) +static int zram_remove(struct zram *zram) { - pr_info("Removed device: %s\n", zram->disk->disk_name); + struct block_device *bdev; + + bdev = bdget_disk(zram->disk, 0); + if (!bdev) + return -ENOMEM; + + mutex_lock(&bdev->bd_mutex); + if (bdev->bd_openers || zram->claim) { + mutex_unlock(&bdev->bd_mutex); + bdput(bdev); + return -EBUSY; + } + + zram->claim = true; + mutex_unlock(&bdev->bd_mutex); + /* * Remove sysfs first, so no one will perform a disksize - * store while we destroy the devices + * store while we destroy the devices. This also helps during + * hot_remove -- zram_reset_device() is the last holder of + * ->init_lock, no later/concurrent disksize_store() or any + * other sysfs handlers are possible. */ sysfs_remove_group(&disk_to_dev(zram->disk)->kobj, &zram_disk_attr_group); + /* Make sure all the pending I/O are finished */ + fsync_bdev(bdev); zram_reset_device(zram); + bdput(bdev); + + pr_info("Removed device: %s\n", zram->disk->disk_name); + idr_remove(&zram_index_idr, zram->disk->first_minor); blk_cleanup_queue(zram->disk->queue); del_gendisk(zram->disk); put_disk(zram->disk); kfree(zram); + return 0; +} + +/* zram-control sysfs attributes */ +static ssize_t hot_add_show(struct class *class, + struct class_attribute *attr, + char *buf) +{ + int ret; + + mutex_lock(&zram_index_mutex); + ret = zram_add(); + mutex_unlock(&zram_index_mutex); + + if (ret < 0) + return ret; + return scnprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +static ssize_t hot_remove_store(struct class *class, + struct class_attribute *attr, + const char *buf, + size_t count) +{ + struct zram *zram; + int ret, dev_id; + + /* dev_id is gendisk->first_minor, which is `int' */ + ret = kstrtoint(buf, 10, &dev_id); + if (ret) + return ret; + if (dev_id < 0) + return -EINVAL; + + mutex_lock(&zram_index_mutex); + + zram = idr_find(&zram_index_idr, dev_id); + if (zram) + ret = zram_remove(zram); + else + ret = -ENODEV; + + mutex_unlock(&zram_index_mutex); + return ret ? ret : count; } +static struct class_attribute zram_control_class_attrs[] = { + __ATTR_RO(hot_add), + __ATTR_WO(hot_remove), + __ATTR_NULL, +}; + +static struct class zram_control_class = { + .name = "zram-control", + .owner = THIS_MODULE, + .class_attrs = zram_control_class_attrs, +}; + static int zram_remove_cb(int id, void *ptr, void *data) { zram_remove(ptr); @@ -1299,6 +1383,7 @@ static int zram_remove_cb(int id, void *ptr, void *data) static void destroy_devices(void) { + class_unregister(&zram_control_class); idr_for_each(&zram_index_idr, &zram_remove_cb, NULL); idr_destroy(&zram_index_idr); unregister_blkdev(zram_major, "zram"); @@ -1308,14 +1393,23 @@ static int __init zram_init(void) { int ret; + ret = class_register(&zram_control_class); + if (ret) { + pr_warn("Unable to register zram-control class\n"); + return ret; + } + zram_major = register_blkdev(0, "zram"); if (zram_major <= 0) { pr_warn("Unable to get major number\n"); + class_unregister(&zram_control_class); return -EBUSY; } while (num_devices != 0) { + mutex_lock(&zram_index_mutex); ret = zram_add(); + mutex_unlock(&zram_index_mutex); if (ret < 0) goto out_error; num_devices--; -- cgit v1.2.3 From c00ed16a9eb98a7fc076e227bdd95c1451ca1e6e Mon Sep 17 00:00:00 2001 From: Dan Streetman Date: Thu, 25 Jun 2015 15:00:35 -0700 Subject: zswap: runtime enable/disable Change the "enabled" parameter to be configurable at runtime. Remove the enabled check from init(), and move it to the frontswap store() function; when enabled, pages will be stored, and when disabled, pages won't be stored. This is almost identical to Seth's patch from 2 years ago: http://lkml.iu.edu/hypermail/linux/kernel/1307.2/04289.html [akpm@linux-foundation.org: tweak documentation] Signed-off-by: Dan Streetman Suggested-by: Seth Jennings Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/vm/zswap.txt | 18 ++++++++++++++++-- mm/zswap.c | 12 +++++------- 2 files changed, 21 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/vm/zswap.txt b/Documentation/vm/zswap.txt index 00c3d31e7971..8458c0861e4e 100644 --- a/Documentation/vm/zswap.txt +++ b/Documentation/vm/zswap.txt @@ -26,8 +26,22 @@ Zswap evicts pages from compressed cache on an LRU basis to the backing swap device when the compressed pool reaches its size limit. This requirement had been identified in prior community discussions. -To enabled zswap, the "enabled" attribute must be set to 1 at boot time. e.g. -zswap.enabled=1 +Zswap is disabled by default but can be enabled at boot time by setting +the "enabled" attribute to 1 at boot time. ie: zswap.enabled=1. Zswap +can also be enabled and disabled at runtime using the sysfs interface. +An example command to enable zswap at runtime, assuming sysfs is mounted +at /sys, is: + +echo 1 > /sys/modules/zswap/parameters/enabled + +When zswap is disabled at runtime it will stop storing pages that are +being swapped out. However, it will _not_ immediately write out or fault +back into memory all of the pages stored in the compressed pool. The +pages stored in zswap will remain in the compressed pool until they are +either invalidated or faulted back into memory. In order to force all +pages out of the compressed pool, a swapoff on the swap device(s) will +fault back into memory all swapped out pages, including those in the +compressed pool. Design: diff --git a/mm/zswap.c b/mm/zswap.c index 4249e82ff934..2d5727baed59 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -75,9 +75,10 @@ static u64 zswap_duplicate_entry; /********************************* * tunables **********************************/ -/* Enable/disable zswap (disabled by default, fixed at boot for now) */ -static bool zswap_enabled __read_mostly; -module_param_named(enabled, zswap_enabled, bool, 0444); + +/* Enable/disable zswap (disabled by default) */ +static bool zswap_enabled; +module_param_named(enabled, zswap_enabled, bool, 0644); /* Compressor to be used by zswap (fixed at boot for now) */ #define ZSWAP_COMPRESSOR_DEFAULT "lzo" @@ -648,7 +649,7 @@ static int zswap_frontswap_store(unsigned type, pgoff_t offset, u8 *src, *dst; struct zswap_header *zhdr; - if (!tree) { + if (!zswap_enabled || !tree) { ret = -ENODEV; goto reject; } @@ -901,9 +902,6 @@ static int __init init_zswap(void) { gfp_t gfp = __GFP_NORETRY | __GFP_NOWARN; - if (!zswap_enabled) - return 0; - pr_info("loading zswap\n"); zswap_pool = zpool_create_pool(zswap_zpool_type, "zswap", gfp, -- cgit v1.2.3 From e34cadde3be793f179107228243242ccabdbb57c Mon Sep 17 00:00:00 2001 From: Pratyush Anand Date: Thu, 25 Jun 2015 15:01:08 -0700 Subject: Pratyush Anand has moved pratyush.anand@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with pratyush.anand@gmail.com. Signed-off-by: Pratyush Anand Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- .mailmap | 1 + Documentation/ABI/testing/configfs-spear-pcie-gadget | 2 +- Documentation/ABI/testing/sysfs-bus-usb-lvstest | 12 ++++++------ Documentation/misc-devices/spear-pcie-gadget.txt | 2 +- drivers/misc/spear13xx_pcie_gadget.c | 2 +- drivers/pci/host/pcie-spear13xx.c | 4 ++-- drivers/phy/phy-spear1310-miphy.c | 4 ++-- drivers/phy/phy-spear1340-miphy.c | 4 ++-- drivers/usb/misc/lvstest.c | 2 +- 9 files changed, 17 insertions(+), 16 deletions(-) (limited to 'Documentation') diff --git a/.mailmap b/.mailmap index 6287004040e7..145eaa9f7d71 100644 --- a/.mailmap +++ b/.mailmap @@ -95,6 +95,7 @@ Patrick Mochel Peter A Jonsson Peter Oruba Peter Oruba +Pratyush Anand Praveen BP Rajesh Shah Ralf Baechle diff --git a/Documentation/ABI/testing/configfs-spear-pcie-gadget b/Documentation/ABI/testing/configfs-spear-pcie-gadget index 875988146a63..840c324ef34d 100644 --- a/Documentation/ABI/testing/configfs-spear-pcie-gadget +++ b/Documentation/ABI/testing/configfs-spear-pcie-gadget @@ -1,7 +1,7 @@ What: /config/pcie-gadget Date: Feb 2011 KernelVersion: 2.6.37 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Interface is used to configure selected dual mode PCIe controller diff --git a/Documentation/ABI/testing/sysfs-bus-usb-lvstest b/Documentation/ABI/testing/sysfs-bus-usb-lvstest index aae68fc2d842..5151290cf8e7 100644 --- a/Documentation/ABI/testing/sysfs-bus-usb-lvstest +++ b/Documentation/ABI/testing/sysfs-bus-usb-lvstest @@ -4,14 +4,14 @@ driver is bound with root hub device. What: /sys/bus/usb/devices/.../get_dev_desc Date: March 2014 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Write to this node to issue "Get Device Descriptor" for Link Layer Validation device. It is needed for TD.7.06. What: /sys/bus/usb/devices/.../u1_timeout Date: March 2014 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Set "U1 timeout" for the downstream port where Link Layer Validation device is connected. Timeout value must be between 0 @@ -19,7 +19,7 @@ Description: What: /sys/bus/usb/devices/.../u2_timeout Date: March 2014 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Set "U2 timeout" for the downstream port where Link Layer Validation device is connected. Timeout value must be between 0 @@ -27,21 +27,21 @@ Description: What: /sys/bus/usb/devices/.../hot_reset Date: March 2014 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Write to this node to issue "Reset" for Link Layer Validation device. It is needed for TD.7.29, TD.7.31, TD.7.34 and TD.7.35. What: /sys/bus/usb/devices/.../u3_entry Date: March 2014 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Write to this node to issue "U3 entry" for Link Layer Validation device. It is needed for TD.7.35 and TD.7.36. What: /sys/bus/usb/devices/.../u3_exit Date: March 2014 -Contact: Pratyush Anand +Contact: Pratyush Anand Description: Write to this node to issue "U3 exit" for Link Layer Validation device. It is needed for TD.7.36. diff --git a/Documentation/misc-devices/spear-pcie-gadget.txt b/Documentation/misc-devices/spear-pcie-gadget.txt index 02c13ef5e908..89b88dee4143 100644 --- a/Documentation/misc-devices/spear-pcie-gadget.txt +++ b/Documentation/misc-devices/spear-pcie-gadget.txt @@ -2,7 +2,7 @@ Spear PCIe Gadget Driver: Author ============= -Pratyush Anand (pratyush.anand@st.com) +Pratyush Anand (pratyush.anand@gmail.com) Location ============ diff --git a/drivers/misc/spear13xx_pcie_gadget.c b/drivers/misc/spear13xx_pcie_gadget.c index fe3ad0ca9a3e..b8374cdaf9c9 100644 --- a/drivers/misc/spear13xx_pcie_gadget.c +++ b/drivers/misc/spear13xx_pcie_gadget.c @@ -2,7 +2,7 @@ * drivers/misc/spear13xx_pcie_gadget.c * * Copyright (C) 2010 ST Microelectronics - * Pratyush Anand + * Pratyush Anand * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index dfec4281bd50..3ba275a4f4d3 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -4,7 +4,7 @@ * SPEAr13xx PCIe Glue Layer Source Code * * Copyright (C) 2010-2014 ST Microelectronics - * Pratyush Anand + * Pratyush Anand * Mohit Kumar * * This file is licensed under the terms of the GNU General Public @@ -386,5 +386,5 @@ static int __init spear13xx_pcie_init(void) module_init(spear13xx_pcie_init); MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver"); -MODULE_AUTHOR("Pratyush Anand "); +MODULE_AUTHOR("Pratyush Anand "); MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-spear1310-miphy.c b/drivers/phy/phy-spear1310-miphy.c index 65ae640cfbd1..85d3e11e6769 100644 --- a/drivers/phy/phy-spear1310-miphy.c +++ b/drivers/phy/phy-spear1310-miphy.c @@ -2,7 +2,7 @@ * ST SPEAr1310-miphy driver * * Copyright (C) 2014 ST Microelectronics - * Pratyush Anand + * Pratyush Anand * Mohit Kumar * * This program is free software; you can redistribute it and/or modify @@ -257,5 +257,5 @@ static struct platform_driver spear1310_miphy_driver = { module_platform_driver(spear1310_miphy_driver); MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver"); -MODULE_AUTHOR("Pratyush Anand "); +MODULE_AUTHOR("Pratyush Anand "); MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-spear1340-miphy.c b/drivers/phy/phy-spear1340-miphy.c index 1a00c2817f34..2f98ebaa6ba9 100644 --- a/drivers/phy/phy-spear1340-miphy.c +++ b/drivers/phy/phy-spear1340-miphy.c @@ -2,7 +2,7 @@ * ST spear1340-miphy driver * * Copyright (C) 2014 ST Microelectronics - * Pratyush Anand + * Pratyush Anand * Mohit Kumar * * This program is free software; you can redistribute it and/or modify @@ -290,5 +290,5 @@ static struct platform_driver spear1340_miphy_driver = { module_platform_driver(spear1340_miphy_driver); MODULE_DESCRIPTION("ST SPEAR1340-MIPHY driver"); -MODULE_AUTHOR("Pratyush Anand "); +MODULE_AUTHOR("Pratyush Anand "); MODULE_LICENSE("GPL v2"); diff --git a/drivers/usb/misc/lvstest.c b/drivers/usb/misc/lvstest.c index 62cb8cd08403..86b4e4b2ab9a 100644 --- a/drivers/usb/misc/lvstest.c +++ b/drivers/usb/misc/lvstest.c @@ -4,7 +4,7 @@ * Test pattern generation for Link Layer Validation System Tests * * Copyright (C) 2014 ST Microelectronics - * Pratyush Anand + * Pratyush Anand * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any -- cgit v1.2.3 From 6fe29354befe4c46eb308b662155d4d8017358e1 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 25 Jun 2015 15:01:30 -0700 Subject: printk: implement support for extended console drivers printk log_buf keeps various metadata for each message including its sequence number and timestamp. The metadata is currently available only through /dev/kmsg and stripped out before passed onto console drivers. We want this metadata to be available to console drivers too so that console consumers can get full information including the metadata and dictionary, which among other things can be used to detect whether messages got lost in transit. This patch implements support for extended console drivers. Consoles can indicate that they want extended messages by setting the new CON_EXTENDED flag and they'll be fed messages formatted the same way as /dev/kmsg. ",,,;\n" If extended consoles exist, in-kernel fragment assembly is disabled. This ensures that all messages emitted to consoles have full metadata including sequence number. The contflag carries enough information to reassemble the fragments from the reader side trivially. Note that this only affects /dev/kmsg. Regular console and /proc/kmsg outputs are not affected by this change. * Extended message formatting for console drivers is enabled iff there are registered extended consoles. * Comment describing /dev/kmsg message format updated to add missing contflag field and help distinguishing variable from verbatim terms. Signed-off-by: Tejun Heo Cc: David Miller Cc: Kay Sievers Reviewed-by: Petr Mladek Cc: Tetsuo Handa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/ABI/testing/dev-kmsg | 9 ++++++ include/linux/console.h | 1 + kernel/printk/printk.c | 66 +++++++++++++++++++++++++++++++++----- 3 files changed, 68 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/dev-kmsg b/Documentation/ABI/testing/dev-kmsg index bb820be48179..fff817efa508 100644 --- a/Documentation/ABI/testing/dev-kmsg +++ b/Documentation/ABI/testing/dev-kmsg @@ -98,4 +98,13 @@ Description: The /dev/kmsg character device node provides userspace access logic is used internally when messages are printed to the console, /proc/kmsg or the syslog() syscall. + By default, kernel tries to avoid fragments by concatenating + when it can and fragments are rare; however, when extended + console support is enabled, the in-kernel concatenation is + disabled and /dev/kmsg output will contain more fragments. If + the log consumer performs concatenation, the end result + should be the same. In the future, the in-kernel concatenation + may be removed entirely and /dev/kmsg users are recommended to + implement fragment handling. + Users: dmesg(1), userspace kernel log consumers diff --git a/include/linux/console.h b/include/linux/console.h index 9f50fb413c11..bd194343c346 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -115,6 +115,7 @@ static inline int con_debug_leave(void) #define CON_BOOT (8) #define CON_ANYTIME (16) /* Safe to call when cpu is offline */ #define CON_BRL (32) /* Used for a braille device */ +#define CON_EXTENDED (64) /* Use the extended output format a la /dev/kmsg */ struct console { char name[16]; diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index 51ce4f1838b3..ae980dc3ac1e 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -84,6 +84,18 @@ static struct lockdep_map console_lock_dep_map = { }; #endif +/* + * Number of registered extended console drivers. + * + * If extended consoles are present, in-kernel cont reassembly is disabled + * and each fragment is stored as a separate log entry with proper + * continuation flag so that every emitted message has full metadata. This + * doesn't change the result for regular consoles or /proc/kmsg. For + * /dev/kmsg, as long as the reader concatenates messages according to + * consecutive continuation flags, the end result should be the same too. + */ +static int nr_ext_console_drivers; + /* * Helper macros to handle lockdep when locking/unlocking console_sem. We use * macros instead of functions so that _RET_IP_ contains useful information. @@ -195,7 +207,7 @@ static int console_may_schedule; * need to be changed in the future, when the requirements change. * * /dev/kmsg exports the structured data in the following line format: - * "level,sequnum,timestamp;\n" + * ",,,;\n" * * The optional key/value pairs are attached as continuation lines starting * with a space character and terminated by a newline. All possible @@ -1417,7 +1429,9 @@ SYSCALL_DEFINE3(syslog, int, type, char __user *, buf, int, len) * log_buf[start] to log_buf[end - 1]. * The console_lock must be held. */ -static void call_console_drivers(int level, const char *text, size_t len) +static void call_console_drivers(int level, + const char *ext_text, size_t ext_len, + const char *text, size_t len) { struct console *con; @@ -1438,7 +1452,10 @@ static void call_console_drivers(int level, const char *text, size_t len) if (!cpu_online(smp_processor_id()) && !(con->flags & CON_ANYTIME)) continue; - con->write(con, text, len); + if (con->flags & CON_EXTENDED) + con->write(con, ext_text, ext_len); + else + con->write(con, text, len); } } @@ -1581,8 +1598,12 @@ static bool cont_add(int facility, int level, const char *text, size_t len) if (cont.len && cont.flushed) return false; - if (cont.len + len > sizeof(cont.buf)) { - /* the line gets too long, split it up in separate records */ + /* + * If ext consoles are present, flush and skip in-kernel + * continuation. See nr_ext_console_drivers definition. Also, if + * the line gets too long, split it up in separate records. + */ + if (nr_ext_console_drivers || cont.len + len > sizeof(cont.buf)) { cont_flush(LOG_CONT); return false; } @@ -1917,9 +1938,19 @@ static struct cont { u8 level; bool flushed:1; } cont; +static char *log_text(const struct printk_log *msg) { return NULL; } +static char *log_dict(const struct printk_log *msg) { return NULL; } static struct printk_log *log_from_idx(u32 idx) { return NULL; } static u32 log_next(u32 idx) { return 0; } -static void call_console_drivers(int level, const char *text, size_t len) {} +static ssize_t msg_print_ext_header(char *buf, size_t size, + struct printk_log *msg, u64 seq, + enum log_flags prev_flags) { return 0; } +static ssize_t msg_print_ext_body(char *buf, size_t size, + char *dict, size_t dict_len, + char *text, size_t text_len) { return 0; } +static void call_console_drivers(int level, + const char *ext_text, size_t ext_len, + const char *text, size_t len) {} static size_t msg_print_text(const struct printk_log *msg, enum log_flags prev, bool syslog, char *buf, size_t size) { return 0; } static size_t cont_print_text(char *text, size_t size) { return 0; } @@ -2172,7 +2203,7 @@ static void console_cont_flush(char *text, size_t size) len = cont_print_text(text, size); raw_spin_unlock(&logbuf_lock); stop_critical_timings(); - call_console_drivers(cont.level, text, len); + call_console_drivers(cont.level, NULL, 0, text, len); start_critical_timings(); local_irq_restore(flags); return; @@ -2196,6 +2227,7 @@ out: */ void console_unlock(void) { + static char ext_text[CONSOLE_EXT_LOG_MAX]; static char text[LOG_LINE_MAX + PREFIX_MAX]; static u64 seen_seq; unsigned long flags; @@ -2214,6 +2246,7 @@ void console_unlock(void) again: for (;;) { struct printk_log *msg; + size_t ext_len = 0; size_t len; int level; @@ -2259,13 +2292,22 @@ skip: level = msg->level; len += msg_print_text(msg, console_prev, false, text + len, sizeof(text) - len); + if (nr_ext_console_drivers) { + ext_len = msg_print_ext_header(ext_text, + sizeof(ext_text), + msg, console_seq, console_prev); + ext_len += msg_print_ext_body(ext_text + ext_len, + sizeof(ext_text) - ext_len, + log_dict(msg), msg->dict_len, + log_text(msg), msg->text_len); + } console_idx = log_next(console_idx); console_seq++; console_prev = msg->flags; raw_spin_unlock(&logbuf_lock); stop_critical_timings(); /* don't trace print latency */ - call_console_drivers(level, text, len); + call_console_drivers(level, ext_text, ext_len, text, len); start_critical_timings(); local_irq_restore(flags); } @@ -2521,6 +2563,11 @@ void register_console(struct console *newcon) newcon->next = console_drivers->next; console_drivers->next = newcon; } + + if (newcon->flags & CON_EXTENDED) + if (!nr_ext_console_drivers++) + pr_info("printk: continuation disabled due to ext consoles, expect more fragments in /dev/kmsg\n"); + if (newcon->flags & CON_PRINTBUFFER) { /* * console_unlock(); will print out the buffered messages @@ -2593,6 +2640,9 @@ int unregister_console(struct console *console) } } + if (!res && (console->flags & CON_EXTENDED)) + nr_ext_console_drivers--; + /* * If this isn't the last console and it has CON_CONSDEV set, we * need to set it on the next preferred console. -- cgit v1.2.3 From e2f15f9a79201ddd596727b84a85c419ee57ad5c Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 25 Jun 2015 15:01:41 -0700 Subject: netconsole: implement extended console support printk logbuf keeps various metadata and optional key=value dictionary for structured messages, both of which are stripped when messages are handed to regular console drivers. It can be useful to have this metadata and dictionary available to netconsole consumers. This obviously makes logging via netconsole more complete and the sequence number in particular is useful in environments where messages may be lost or reordered in transit - e.g. when netconsole is used to collect messages in a large cluster where packets may have to travel congested hops to reach the aggregator. The lost and reordered messages can easily be identified and handled accordingly using the sequence numbers. printk recently added extended console support which can be selected by setting CON_EXTENDED flag. From console driver side, not much changes. The only difference is that the text passed to the write callback is formatted the same way as /dev/kmsg. This patch implements extended console support for netconsole which can be enabled by either prepending "+" to a netconsole boot param entry or echoing 1 to "extended" file in configfs. When enabled, netconsole transmits extended log messages with headers identical to /dev/kmsg output. There's one complication due to message fragments. netconsole limits the maximum message size to 1k and messages longer than that are split into multiple fragments. As all extended console messages should carry matching headers and be uniquely identifiable, each extended message fragment carries full copy of the metadata and an extra header field to identify the specific fragment. The optional header is of the form "ncfrag=OFF/LEN" where OFF is the byte offset into the message body and LEN is the total length. To avoid unnecessarily making printk format extended messages, Extended netconsole is registered with printk when the first extended netconsole is configured. Signed-off-by: Tejun Heo Cc: David Miller Cc: Kay Sievers Cc: Petr Mladek Cc: Tetsuo Handa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/networking/netconsole.txt | 35 +++++++- drivers/net/netconsole.c | 141 +++++++++++++++++++++++++++++++- 2 files changed, 173 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/networking/netconsole.txt b/Documentation/networking/netconsole.txt index a5d574a9ae09..30409a36e95d 100644 --- a/Documentation/networking/netconsole.txt +++ b/Documentation/networking/netconsole.txt @@ -2,6 +2,7 @@ started by Ingo Molnar , 2001.09.17 2.6 port and netpoll api by Matt Mackall , Sep 9 2003 IPv6 support by Cong Wang , Jan 1 2013 +Extended console support by Tejun Heo , May 1 2015 Please send bug reports to Matt Mackall Satyam Sharma , and Cong Wang @@ -24,9 +25,10 @@ Sender and receiver configuration: It takes a string configuration parameter "netconsole" in the following format: - netconsole=[src-port]@[src-ip]/[],[tgt-port]@/[tgt-macaddr] + netconsole=[+][src-port]@[src-ip]/[],[tgt-port]@/[tgt-macaddr] where + + if present, enable extended console support src-port source for UDP packets (defaults to 6665) src-ip source IP to use (interface address) dev network interface (eth0) @@ -107,6 +109,7 @@ To remove a target: The interface exposes these parameters of a netconsole target to userspace: enabled Is this target currently enabled? (read-write) + extended Extended mode enabled (read-write) dev_name Local network interface name (read-write) local_port Source UDP port to use (read-write) remote_port Remote agent's UDP port (read-write) @@ -132,6 +135,36 @@ You can also update the local interface dynamically. This is especially useful if you want to use interfaces that have newly come up (and may not have existed when netconsole was loaded / initialized). +Extended console: +================= + +If '+' is prefixed to the configuration line or "extended" config file +is set to 1, extended console support is enabled. An example boot +param follows. + + linux netconsole=+4444@10.0.0.1/eth1,9353@10.0.0.2/12:34:56:78:9a:bc + +Log messages are transmitted with extended metadata header in the +following format which is the same as /dev/kmsg. + + ,,,; + +Non printable characters in are escaped using "\xff" +notation. If the message contains optional dictionary, verbatim +newline is used as the delimeter. + +If a message doesn't fit in certain number of bytes (currently 1000), +the message is split into multiple fragments by netconsole. These +fragments are transmitted with "ncfrag" header field added. + + ncfrag=/ + +For example, assuming a lot smaller chunk size, a message "the first +chunk, the 2nd chunk." may be split as follows. + + 6,416,1758426,-,ncfrag=0/31;the first chunk, + 6,416,1758426,-,ncfrag=16/31; the 2nd chunk. + Miscellaneous notes: ==================== diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 9b0c81e7c752..97f3acd44798 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -79,6 +79,12 @@ static LIST_HEAD(target_list); /* This needs to be a spinlock because write_msg() cannot sleep */ static DEFINE_SPINLOCK(target_list_lock); +/* + * Console driver for extended netconsoles. Registered on the first use to + * avoid unnecessarily enabling ext message formatting. + */ +static struct console netconsole_ext; + /** * struct netconsole_target - Represents a configured netconsole target. * @list: Links this target into the target_list. @@ -105,6 +111,7 @@ struct netconsole_target { struct config_item item; #endif bool enabled; + bool extended; struct netpoll np; }; @@ -187,6 +194,11 @@ static struct netconsole_target *alloc_param_target(char *target_config) nt->np.remote_port = 6666; eth_broadcast_addr(nt->np.remote_mac); + if (*target_config == '+') { + nt->extended = true; + target_config++; + } + /* Parse parameters and setup netpoll */ err = netpoll_parse_options(&nt->np, target_config); if (err) @@ -257,6 +269,11 @@ static ssize_t show_enabled(struct netconsole_target *nt, char *buf) return snprintf(buf, PAGE_SIZE, "%d\n", nt->enabled); } +static ssize_t show_extended(struct netconsole_target *nt, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", nt->extended); +} + static ssize_t show_dev_name(struct netconsole_target *nt, char *buf) { return snprintf(buf, PAGE_SIZE, "%s\n", nt->np.dev_name); @@ -328,6 +345,11 @@ static ssize_t store_enabled(struct netconsole_target *nt, } if (enabled) { /* true */ + if (nt->extended && !(netconsole_ext.flags & CON_ENABLED)) { + netconsole_ext.flags |= CON_ENABLED; + register_console(&netconsole_ext); + } + /* * Skip netpoll_parse_options() -- all the attributes are * already configured via configfs. Just print them out. @@ -355,6 +377,30 @@ static ssize_t store_enabled(struct netconsole_target *nt, return strnlen(buf, count); } +static ssize_t store_extended(struct netconsole_target *nt, + const char *buf, + size_t count) +{ + int extended; + int err; + + if (nt->enabled) { + pr_err("target (%s) is enabled, disable to update parameters\n", + config_item_name(&nt->item)); + return -EINVAL; + } + + err = kstrtoint(buf, 10, &extended); + if (err < 0) + return err; + if (extended < 0 || extended > 1) + return -EINVAL; + + nt->extended = extended; + + return strnlen(buf, count); +} + static ssize_t store_dev_name(struct netconsole_target *nt, const char *buf, size_t count) @@ -507,6 +553,7 @@ static struct netconsole_target_attr netconsole_target_##_name = \ __CONFIGFS_ATTR(_name, S_IRUGO | S_IWUSR, show_##_name, store_##_name) NETCONSOLE_TARGET_ATTR_RW(enabled); +NETCONSOLE_TARGET_ATTR_RW(extended); NETCONSOLE_TARGET_ATTR_RW(dev_name); NETCONSOLE_TARGET_ATTR_RW(local_port); NETCONSOLE_TARGET_ATTR_RW(remote_port); @@ -517,6 +564,7 @@ NETCONSOLE_TARGET_ATTR_RW(remote_mac); static struct configfs_attribute *netconsole_target_attrs[] = { &netconsole_target_enabled.attr, + &netconsole_target_extended.attr, &netconsole_target_dev_name.attr, &netconsole_target_local_port.attr, &netconsole_target_remote_port.attr, @@ -727,6 +775,82 @@ static struct notifier_block netconsole_netdev_notifier = { .notifier_call = netconsole_netdev_event, }; +/** + * send_ext_msg_udp - send extended log message to target + * @nt: target to send message to + * @msg: extended log message to send + * @msg_len: length of message + * + * Transfer extended log @msg to @nt. If @msg is longer than + * MAX_PRINT_CHUNK, it'll be split and transmitted in multiple chunks with + * ncfrag header field added to identify them. + */ +static void send_ext_msg_udp(struct netconsole_target *nt, const char *msg, + int msg_len) +{ + static char buf[MAX_PRINT_CHUNK]; /* protected by target_list_lock */ + const char *header, *body; + int offset = 0; + int header_len, body_len; + + if (msg_len <= MAX_PRINT_CHUNK) { + netpoll_send_udp(&nt->np, msg, msg_len); + return; + } + + /* need to insert extra header fields, detect header and body */ + header = msg; + body = memchr(msg, ';', msg_len); + if (WARN_ON_ONCE(!body)) + return; + + header_len = body - header; + body_len = msg_len - header_len - 1; + body++; + + /* + * Transfer multiple chunks with the following extra header. + * "ncfrag=/" + */ + memcpy(buf, header, header_len); + + while (offset < body_len) { + int this_header = header_len; + int this_chunk; + + this_header += scnprintf(buf + this_header, + sizeof(buf) - this_header, + ",ncfrag=%d/%d;", offset, body_len); + + this_chunk = min(body_len - offset, + MAX_PRINT_CHUNK - this_header); + if (WARN_ON_ONCE(this_chunk <= 0)) + return; + + memcpy(buf + this_header, body + offset, this_chunk); + + netpoll_send_udp(&nt->np, buf, this_header + this_chunk); + + offset += this_chunk; + } +} + +static void write_ext_msg(struct console *con, const char *msg, + unsigned int len) +{ + struct netconsole_target *nt; + unsigned long flags; + + if ((oops_only && !oops_in_progress) || list_empty(&target_list)) + return; + + spin_lock_irqsave(&target_list_lock, flags); + list_for_each_entry(nt, &target_list, list) + if (nt->extended && nt->enabled && netif_running(nt->np.dev)) + send_ext_msg_udp(nt, msg, len); + spin_unlock_irqrestore(&target_list_lock, flags); +} + static void write_msg(struct console *con, const char *msg, unsigned int len) { int frag, left; @@ -742,7 +866,7 @@ static void write_msg(struct console *con, const char *msg, unsigned int len) spin_lock_irqsave(&target_list_lock, flags); list_for_each_entry(nt, &target_list, list) { - if (nt->enabled && netif_running(nt->np.dev)) { + if (!nt->extended && nt->enabled && netif_running(nt->np.dev)) { /* * We nest this inside the for-each-target loop above * so that we're able to get as much logging out to @@ -761,6 +885,12 @@ static void write_msg(struct console *con, const char *msg, unsigned int len) spin_unlock_irqrestore(&target_list_lock, flags); } +static struct console netconsole_ext = { + .name = "netcon_ext", + .flags = CON_EXTENDED, /* starts disabled, registered on first use */ + .write = write_ext_msg, +}; + static struct console netconsole = { .name = "netcon", .flags = CON_ENABLED, @@ -783,7 +913,11 @@ static int __init init_netconsole(void) goto fail; } /* Dump existing printks when we register */ - netconsole.flags |= CON_PRINTBUFFER; + if (nt->extended) + netconsole_ext.flags |= CON_PRINTBUFFER | + CON_ENABLED; + else + netconsole.flags |= CON_PRINTBUFFER; spin_lock_irqsave(&target_list_lock, flags); list_add(&nt->list, &target_list); @@ -799,6 +933,8 @@ static int __init init_netconsole(void) if (err) goto undonotifier; + if (netconsole_ext.flags & CON_ENABLED) + register_console(&netconsole_ext); register_console(&netconsole); pr_info("network logging started\n"); @@ -827,6 +963,7 @@ static void __exit cleanup_netconsole(void) { struct netconsole_target *nt, *tmp; + unregister_console(&netconsole_ext); unregister_console(&netconsole); dynamic_netconsole_exit(); unregister_netdevice_notifier(&netconsole_netdev_notifier); -- cgit v1.2.3 From 5202efe544c279be152f44f2821010ff7b2d7e5b Mon Sep 17 00:00:00 2001 From: Nicolas Iooss Date: Thu, 25 Jun 2015 15:03:51 -0700 Subject: coredump: use from_kuid/kgid when formatting corename When adding __printf attribute to cn_printf, gcc reports some issues: fs/coredump.c:213:5: warning: format '%d' expects argument of type 'int', but argument 3 has type 'kuid_t' [-Wformat=] err = cn_printf(cn, "%d", cred->uid); ^ fs/coredump.c:217:5: warning: format '%d' expects argument of type 'int', but argument 3 has type 'kgid_t' [-Wformat=] err = cn_printf(cn, "%d", cred->gid); ^ These warnings come from the fact that the value of uid/gid needs to be extracted from the kuid_t/kgid_t structure before being used as an integer. More precisely, cred->uid and cred->gid need to be converted to either user-namespace uid/gid or to init_user_ns uid/gid. Use init_user_ns in order not to break existing ABI, and document this in Documentation/sysctl/kernel.txt. While at it, format uid and gid values with %u instead of %d because uid_t/__kernel_uid32_t and gid_t/__kernel_gid32_t are unsigned int. Signed-off-by: Nicolas Iooss Acked-by: "Eric W. Biederman" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/sysctl/kernel.txt | 4 ++-- fs/coredump.c | 8 ++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt index e5d528e0c46e..6fccb69c03e7 100644 --- a/Documentation/sysctl/kernel.txt +++ b/Documentation/sysctl/kernel.txt @@ -197,8 +197,8 @@ core_pattern is used to specify a core dumpfile pattern name. %P global pid (init PID namespace) %i tid %I global tid (init PID namespace) - %u uid - %g gid + %u uid (in initial user namespace) + %g gid (in initial user namespace) %d dump mode, matches PR_SET_DUMPABLE and /proc/sys/fs/suid_dumpable %s signal number diff --git a/fs/coredump.c b/fs/coredump.c index bbbe139ab280..833a57bc856c 100644 --- a/fs/coredump.c +++ b/fs/coredump.c @@ -209,11 +209,15 @@ static int format_corename(struct core_name *cn, struct coredump_params *cprm) break; /* uid */ case 'u': - err = cn_printf(cn, "%d", cred->uid); + err = cn_printf(cn, "%u", + from_kuid(&init_user_ns, + cred->uid)); break; /* gid */ case 'g': - err = cn_printf(cn, "%d", cred->gid); + err = cn_printf(cn, "%u", + from_kgid(&init_user_ns, + cred->gid)); break; case 'd': err = cn_printf(cn, "%d", -- cgit v1.2.3 From 5212e11fde4d40fa627668b4f2222d20db488f71 Mon Sep 17 00:00:00 2001 From: Vishal Verma Date: Thu, 25 Jun 2015 04:20:32 -0400 Subject: nd_btt: atomic sector updates BTT stands for Block Translation Table, and is a way to provide power fail sector atomicity semantics for block devices that have the ability to perform byte granularity IO. It relies on the capability of libnvdimm namespace devices to do byte aligned IO. The BTT works as a stacked blocked device, and reserves a chunk of space from the backing device for its accounting metadata. It is a bio-based driver because all IO is done synchronously, and there is no queuing or asynchronous completions at either the device or the driver level. The BTT uses 'lanes' to index into various 'on-disk' data structures, and lanes also act as a synchronization mechanism in case there are more CPUs than available lanes. We did a comparison between two lane lock strategies - first where we kept an atomic counter around that tracked which was the last lane that was used, and 'our' lane was determined by atomically incrementing that. That way, for the nr_cpus > nr_lanes case, theoretically, no CPU would be blocked waiting for a lane. The other strategy was to use the cpu number we're scheduled on to and hash it to a lane number. Theoretically, this could block an IO that could've otherwise run using a different, free lane. But some fio workloads showed that the direct cpu -> lane hash performed faster than tracking 'last lane' - my reasoning is the cache thrash caused by moving the atomic variable made that approach slower than simply waiting out the in-progress IO. This supports the conclusion that the driver can be a very simple bio-based one that does synchronous IOs instead of queuing. Cc: Andy Lutomirski Cc: Boaz Harrosh Cc: H. Peter Anvin Cc: Jens Axboe Cc: Ingo Molnar Cc: Christoph Hellwig Cc: Neil Brown Cc: Jeff Moyer Cc: Dave Chinner Cc: Greg KH [jmoyer: fix nmi watchdog timeout in btt_map_init] [jmoyer: move btt initialization to module load path] [jmoyer: fix memory leak in the btt initialization path] [jmoyer: Don't overwrite corrupted arenas] Signed-off-by: Vishal Verma Signed-off-by: Dan Williams --- Documentation/nvdimm/btt.txt | 273 ++++++++ drivers/acpi/nfit.c | 1 + drivers/nvdimm/Kconfig | 28 +- drivers/nvdimm/Makefile | 3 + drivers/nvdimm/btt.c | 1371 +++++++++++++++++++++++++++++++++++++++ drivers/nvdimm/btt.h | 141 ++++ drivers/nvdimm/btt_devs.c | 3 +- drivers/nvdimm/namespace_devs.c | 24 + drivers/nvdimm/nd.h | 22 +- drivers/nvdimm/pmem.c | 14 +- drivers/nvdimm/region.c | 12 + drivers/nvdimm/region_devs.c | 82 ++- include/linux/libnvdimm.h | 1 + 13 files changed, 1950 insertions(+), 25 deletions(-) create mode 100644 Documentation/nvdimm/btt.txt create mode 100644 drivers/nvdimm/btt.c (limited to 'Documentation') diff --git a/Documentation/nvdimm/btt.txt b/Documentation/nvdimm/btt.txt new file mode 100644 index 000000000000..95134d5ec4a0 --- /dev/null +++ b/Documentation/nvdimm/btt.txt @@ -0,0 +1,273 @@ +BTT - Block Translation Table +============================= + + +1. Introduction +--------------- + +Persistent memory based storage is able to perform IO at byte (or more +accurately, cache line) granularity. However, we often want to expose such +storage as traditional block devices. The block drivers for persistent memory +will do exactly this. However, they do not provide any atomicity guarantees. +Traditional SSDs typically provide protection against torn sectors in hardware, +using stored energy in capacitors to complete in-flight block writes, or perhaps +in firmware. We don't have this luxury with persistent memory - if a write is in +progress, and we experience a power failure, the block will contain a mix of old +and new data. Applications may not be prepared to handle such a scenario. + +The Block Translation Table (BTT) provides atomic sector update semantics for +persistent memory devices, so that applications that rely on sector writes not +being torn can continue to do so. The BTT manifests itself as a stacked block +device, and reserves a portion of the underlying storage for its metadata. At +the heart of it, is an indirection table that re-maps all the blocks on the +volume. It can be thought of as an extremely simple file system that only +provides atomic sector updates. + + +2. Static Layout +---------------- + +The underlying storage on which a BTT can be laid out is not limited in any way. +The BTT, however, splits the available space into chunks of up to 512 GiB, +called "Arenas". + +Each arena follows the same layout for its metadata, and all references in an +arena are internal to it (with the exception of one field that points to the +next arena). The following depicts the "On-disk" metadata layout: + + + Backing Store +-------> Arena ++---------------+ | +------------------+ +| | | | Arena info block | +| Arena 0 +---+ | 4K | +| 512G | +------------------+ +| | | | ++---------------+ | | +| | | | +| Arena 1 | | Data Blocks | +| 512G | | | +| | | | ++---------------+ | | +| . | | | +| . | | | +| . | | | +| | | | +| | | | ++---------------+ +------------------+ + | | + | BTT Map | + | | + | | + +------------------+ + | | + | BTT Flog | + | | + +------------------+ + | Info block copy | + | 4K | + +------------------+ + + +3. Theory of Operation +---------------------- + + +a. The BTT Map +-------------- + +The map is a simple lookup/indirection table that maps an LBA to an internal +block. Each map entry is 32 bits. The two most significant bits are special +flags, and the remaining form the internal block number. + +Bit Description +31 : TRIM flag - marks if the block was trimmed or discarded +30 : ERROR flag - marks an error block. Cleared on write. +29 - 0 : Mappings to internal 'postmap' blocks + + +Some of the terminology that will be subsequently used: + +External LBA : LBA as made visible to upper layers. +ABA : Arena Block Address - Block offset/number within an arena +Premap ABA : The block offset into an arena, which was decided upon by range + checking the External LBA +Postmap ABA : The block number in the "Data Blocks" area obtained after + indirection from the map +nfree : The number of free blocks that are maintained at any given time. + This is the number of concurrent writes that can happen to the + arena. + + +For example, after adding a BTT, we surface a disk of 1024G. We get a read for +the external LBA at 768G. This falls into the second arena, and of the 512G +worth of blocks that this arena contributes, this block is at 256G. Thus, the +premap ABA is 256G. We now refer to the map, and find out the mapping for block +'X' (256G) points to block 'Y', say '64'. Thus the postmap ABA is 64. + + +b. The BTT Flog +--------------- + +The BTT provides sector atomicity by making every write an "allocating write", +i.e. Every write goes to a "free" block. A running list of free blocks is +maintained in the form of the BTT flog. 'Flog' is a combination of the words +"free list" and "log". The flog contains 'nfree' entries, and an entry contains: + +lba : The premap ABA that is being written to +old_map : The old postmap ABA - after 'this' write completes, this will be a + free block. +new_map : The new postmap ABA. The map will up updated to reflect this + lba->postmap_aba mapping, but we log it here in case we have to + recover. +seq : Sequence number to mark which of the 2 sections of this flog entry is + valid/newest. It cycles between 01->10->11->01 (binary) under normal + operation, with 00 indicating an uninitialized state. +lba' : alternate lba entry +old_map': alternate old postmap entry +new_map': alternate new postmap entry +seq' : alternate sequence number. + +Each of the above fields is 32-bit, making one entry 16 bytes. Flog updates are +done such that for any entry being written, it: +a. overwrites the 'old' section in the entry based on sequence numbers +b. writes the new entry such that the sequence number is written last. + + +c. The concept of lanes +----------------------- + +While 'nfree' describes the number of concurrent IOs an arena can process +concurrently, 'nlanes' is the number of IOs the BTT device as a whole can +process. + nlanes = min(nfree, num_cpus) +A lane number is obtained at the start of any IO, and is used for indexing into +all the on-disk and in-memory data structures for the duration of the IO. It is +protected by a spinlock. + + +d. In-memory data structure: Read Tracking Table (RTT) +------------------------------------------------------ + +Consider a case where we have two threads, one doing reads and the other, +writes. We can hit a condition where the writer thread grabs a free block to do +a new IO, but the (slow) reader thread is still reading from it. In other words, +the reader consulted a map entry, and started reading the corresponding block. A +writer started writing to the same external LBA, and finished the write updating +the map for that external LBA to point to its new postmap ABA. At this point the +internal, postmap block that the reader is (still) reading has been inserted +into the list of free blocks. If another write comes in for the same LBA, it can +grab this free block, and start writing to it, causing the reader to read +incorrect data. To prevent this, we introduce the RTT. + +The RTT is a simple, per arena table with 'nfree' entries. Every reader inserts +into rtt[lane_number], the postmap ABA it is reading, and clears it after the +read is complete. Every writer thread, after grabbing a free block, checks the +RTT for its presence. If the postmap free block is in the RTT, it waits till the +reader clears the RTT entry, and only then starts writing to it. + + +e. In-memory data structure: map locks +-------------------------------------- + +Consider a case where two writer threads are writing to the same LBA. There can +be a race in the following sequence of steps: + +free[lane] = map[premap_aba] +map[premap_aba] = postmap_aba + +Both threads can update their respective free[lane] with the same old, freed +postmap_aba. This has made the layout inconsistent by losing a free entry, and +at the same time, duplicating another free entry for two lanes. + +To solve this, we could have a single map lock (per arena) that has to be taken +before performing the above sequence, but we feel that could be too contentious. +Instead we use an array of (nfree) map_locks that is indexed by +(premap_aba modulo nfree). + + +f. Reconstruction from the Flog +------------------------------- + +On startup, we analyze the BTT flog to create our list of free blocks. We walk +through all the entries, and for each lane, of the set of two possible +'sections', we always look at the most recent one only (based on the sequence +number). The reconstruction rules/steps are simple: +- Read map[log_entry.lba]. +- If log_entry.new matches the map entry, then log_entry.old is free. +- If log_entry.new does not match the map entry, then log_entry.new is free. + (This case can only be caused by power-fails/unsafe shutdowns) + + +g. Summarizing - Read and Write flows +------------------------------------- + +Read: + +1. Convert external LBA to arena number + pre-map ABA +2. Get a lane (and take lane_lock) +3. Read map to get the entry for this pre-map ABA +4. Enter post-map ABA into RTT[lane] +5. If TRIM flag set in map, return zeroes, and end IO (go to step 8) +6. If ERROR flag set in map, end IO with EIO (go to step 8) +7. Read data from this block +8. Remove post-map ABA entry from RTT[lane] +9. Release lane (and lane_lock) + +Write: + +1. Convert external LBA to Arena number + pre-map ABA +2. Get a lane (and take lane_lock) +3. Use lane to index into in-memory free list and obtain a new block, next flog + index, next sequence number +4. Scan the RTT to check if free block is present, and spin/wait if it is. +5. Write data to this free block +6. Read map to get the existing post-map ABA entry for this pre-map ABA +7. Write flog entry: [premap_aba / old postmap_aba / new postmap_aba / seq_num] +8. Write new post-map ABA into map. +9. Write old post-map entry into the free list +10. Calculate next sequence number and write into the free list entry +11. Release lane (and lane_lock) + + +4. Error Handling +================= + +An arena would be in an error state if any of the metadata is corrupted +irrecoverably, either due to a bug or a media error. The following conditions +indicate an error: +- Info block checksum does not match (and recovering from the copy also fails) +- All internal available blocks are not uniquely and entirely addressed by the + sum of mapped blocks and free blocks (from the BTT flog). +- Rebuilding free list from the flog reveals missing/duplicate/impossible + entries +- A map entry is out of bounds + +If any of these error conditions are encountered, the arena is put into a read +only state using a flag in the info block. + + +5. In-kernel usage +================== + +Any block driver that supports byte granularity IO to the storage may register +with the BTT. It will have to provide the rw_bytes interface in its +block_device_operations struct: + + int (*rw_bytes)(struct gendisk *, void *, size_t, off_t, int rw); + +It may register with the BTT after it adds its own gendisk, using btt_init: + + struct btt *btt_init(struct gendisk *disk, unsigned long long rawsize, + u32 lbasize, u8 uuid[], int maxlane); + +note that maxlane is the maximum amount of concurrency the driver wishes to +allow the BTT to use. + +The BTT 'disk' appears as a stacked block device that grabs the underlying block +device in the O_EXCL mode. + +When the driver wishes to remove the backing disk, it should similarly call +btt_fini using the same struct btt* handle that was provided to it by btt_init. + + void btt_fini(struct btt *btt); + diff --git a/drivers/acpi/nfit.c b/drivers/acpi/nfit.c index 35af6f7f0abd..fc38b49eff7d 100644 --- a/drivers/acpi/nfit.c +++ b/drivers/acpi/nfit.c @@ -902,6 +902,7 @@ static int acpi_nfit_init_mapping(struct acpi_nfit_desc *acpi_desc, } else { nd_mapping->size = nfit_mem->bdw->capacity; nd_mapping->start = nfit_mem->bdw->start_address; + ndr_desc->num_lanes = nfit_mem->bdw->windows; blk_valid = 1; } diff --git a/drivers/nvdimm/Kconfig b/drivers/nvdimm/Kconfig index 5680e8e7a7aa..204ee0796411 100644 --- a/drivers/nvdimm/Kconfig +++ b/drivers/nvdimm/Kconfig @@ -8,11 +8,11 @@ menuconfig LIBNVDIMM NFIT, or otherwise can discover NVDIMM resources, a libnvdimm bus is registered to advertise PMEM (persistent memory) namespaces (/dev/pmemX) and BLK (sliding mmio window(s)) - namespaces (/dev/ndX). A PMEM namespace refers to a memory - resource that may span multiple DIMMs and support DAX (see - CONFIG_DAX). A BLK namespace refers to an NVDIMM control - region which exposes an mmio register set for windowed - access mode to non-volatile memory. + namespaces (/dev/ndblkX.Y). A PMEM namespace refers to a + memory resource that may span multiple DIMMs and support DAX + (see CONFIG_DAX). A BLK namespace refers to an NVDIMM control + region which exposes an mmio register set for windowed access + mode to non-volatile memory. if LIBNVDIMM @@ -20,6 +20,7 @@ config BLK_DEV_PMEM tristate "PMEM: Persistent memory block device support" default LIBNVDIMM depends on HAS_IOMEM + select ND_BTT if BTT help Memory ranges for PMEM are described by either an NFIT (NVDIMM Firmware Interface Table, see CONFIG_NFIT_ACPI), a @@ -33,7 +34,22 @@ config BLK_DEV_PMEM Say Y if you want to use an NVDIMM +config ND_BTT + tristate + config BTT - def_bool y + bool "BTT: Block Translation Table (atomic sector updates)" + default y if LIBNVDIMM + help + The Block Translation Table (BTT) provides atomic sector + update semantics for persistent memory devices, so that + applications that rely on sector writes not being torn (a + guarantee that typical disks provide) can continue to do so. + The BTT manifests itself as an alternate personality for an + NVDIMM namespace, i.e. a namespace can be in raw mode (pmemX, + ndblkX.Y, etc...), or 'sectored' mode, (pmemXs, ndblkX.Ys, + etc...). + + Select Y if unsure endif diff --git a/drivers/nvdimm/Makefile b/drivers/nvdimm/Makefile index 6085b4bd7312..d2aab6c58492 100644 --- a/drivers/nvdimm/Makefile +++ b/drivers/nvdimm/Makefile @@ -1,8 +1,11 @@ obj-$(CONFIG_LIBNVDIMM) += libnvdimm.o obj-$(CONFIG_BLK_DEV_PMEM) += nd_pmem.o +obj-$(CONFIG_ND_BTT) += nd_btt.o nd_pmem-y := pmem.o +nd_btt-y := btt.o + libnvdimm-y := core.o libnvdimm-y += bus.o libnvdimm-y += dimm_devs.o diff --git a/drivers/nvdimm/btt.c b/drivers/nvdimm/btt.c new file mode 100644 index 000000000000..7ae38aac2c25 --- /dev/null +++ b/drivers/nvdimm/btt.c @@ -0,0 +1,1371 @@ +/* + * Block Translation Table + * Copyright (c) 2014-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "btt.h" +#include "nd.h" + +enum log_ent_request { + LOG_NEW_ENT = 0, + LOG_OLD_ENT +}; + +static int btt_major; + +static int arena_read_bytes(struct arena_info *arena, resource_size_t offset, + void *buf, size_t n) +{ + struct nd_btt *nd_btt = arena->nd_btt; + struct nd_namespace_common *ndns = nd_btt->ndns; + + /* arena offsets are 4K from the base of the device */ + offset += SZ_4K; + return nvdimm_read_bytes(ndns, offset, buf, n); +} + +static int arena_write_bytes(struct arena_info *arena, resource_size_t offset, + void *buf, size_t n) +{ + struct nd_btt *nd_btt = arena->nd_btt; + struct nd_namespace_common *ndns = nd_btt->ndns; + + /* arena offsets are 4K from the base of the device */ + offset += SZ_4K; + return nvdimm_write_bytes(ndns, offset, buf, n); +} + +static int btt_info_write(struct arena_info *arena, struct btt_sb *super) +{ + int ret; + + ret = arena_write_bytes(arena, arena->info2off, super, + sizeof(struct btt_sb)); + if (ret) + return ret; + + return arena_write_bytes(arena, arena->infooff, super, + sizeof(struct btt_sb)); +} + +static int btt_info_read(struct arena_info *arena, struct btt_sb *super) +{ + WARN_ON(!super); + return arena_read_bytes(arena, arena->infooff, super, + sizeof(struct btt_sb)); +} + +/* + * 'raw' version of btt_map write + * Assumptions: + * mapping is in little-endian + * mapping contains 'E' and 'Z' flags as desired + */ +static int __btt_map_write(struct arena_info *arena, u32 lba, __le32 mapping) +{ + u64 ns_off = arena->mapoff + (lba * MAP_ENT_SIZE); + + WARN_ON(lba >= arena->external_nlba); + return arena_write_bytes(arena, ns_off, &mapping, MAP_ENT_SIZE); +} + +static int btt_map_write(struct arena_info *arena, u32 lba, u32 mapping, + u32 z_flag, u32 e_flag) +{ + u32 ze; + __le32 mapping_le; + + /* + * This 'mapping' is supposed to be just the LBA mapping, without + * any flags set, so strip the flag bits. + */ + mapping &= MAP_LBA_MASK; + + ze = (z_flag << 1) + e_flag; + switch (ze) { + case 0: + /* + * We want to set neither of the Z or E flags, and + * in the actual layout, this means setting the bit + * positions of both to '1' to indicate a 'normal' + * map entry + */ + mapping |= MAP_ENT_NORMAL; + break; + case 1: + mapping |= (1 << MAP_ERR_SHIFT); + break; + case 2: + mapping |= (1 << MAP_TRIM_SHIFT); + break; + default: + /* + * The case where Z and E are both sent in as '1' could be + * construed as a valid 'normal' case, but we decide not to, + * to avoid confusion + */ + WARN_ONCE(1, "Invalid use of Z and E flags\n"); + return -EIO; + } + + mapping_le = cpu_to_le32(mapping); + return __btt_map_write(arena, lba, mapping_le); +} + +static int btt_map_read(struct arena_info *arena, u32 lba, u32 *mapping, + int *trim, int *error) +{ + int ret; + __le32 in; + u32 raw_mapping, postmap, ze, z_flag, e_flag; + u64 ns_off = arena->mapoff + (lba * MAP_ENT_SIZE); + + WARN_ON(lba >= arena->external_nlba); + + ret = arena_read_bytes(arena, ns_off, &in, MAP_ENT_SIZE); + if (ret) + return ret; + + raw_mapping = le32_to_cpu(in); + + z_flag = (raw_mapping & MAP_TRIM_MASK) >> MAP_TRIM_SHIFT; + e_flag = (raw_mapping & MAP_ERR_MASK) >> MAP_ERR_SHIFT; + ze = (z_flag << 1) + e_flag; + postmap = raw_mapping & MAP_LBA_MASK; + + /* Reuse the {z,e}_flag variables for *trim and *error */ + z_flag = 0; + e_flag = 0; + + switch (ze) { + case 0: + /* Initial state. Return postmap = premap */ + *mapping = lba; + break; + case 1: + *mapping = postmap; + e_flag = 1; + break; + case 2: + *mapping = postmap; + z_flag = 1; + break; + case 3: + *mapping = postmap; + break; + default: + return -EIO; + } + + if (trim) + *trim = z_flag; + if (error) + *error = e_flag; + + return ret; +} + +static int btt_log_read_pair(struct arena_info *arena, u32 lane, + struct log_entry *ent) +{ + WARN_ON(!ent); + return arena_read_bytes(arena, + arena->logoff + (2 * lane * LOG_ENT_SIZE), ent, + 2 * LOG_ENT_SIZE); +} + +static struct dentry *debugfs_root; + +static void arena_debugfs_init(struct arena_info *a, struct dentry *parent, + int idx) +{ + char dirname[32]; + struct dentry *d; + + /* If for some reason, parent bttN was not created, exit */ + if (!parent) + return; + + snprintf(dirname, 32, "arena%d", idx); + d = debugfs_create_dir(dirname, parent); + if (IS_ERR_OR_NULL(d)) + return; + a->debugfs_dir = d; + + debugfs_create_x64("size", S_IRUGO, d, &a->size); + debugfs_create_x64("external_lba_start", S_IRUGO, d, + &a->external_lba_start); + debugfs_create_x32("internal_nlba", S_IRUGO, d, &a->internal_nlba); + debugfs_create_u32("internal_lbasize", S_IRUGO, d, + &a->internal_lbasize); + debugfs_create_x32("external_nlba", S_IRUGO, d, &a->external_nlba); + debugfs_create_u32("external_lbasize", S_IRUGO, d, + &a->external_lbasize); + debugfs_create_u32("nfree", S_IRUGO, d, &a->nfree); + debugfs_create_u16("version_major", S_IRUGO, d, &a->version_major); + debugfs_create_u16("version_minor", S_IRUGO, d, &a->version_minor); + debugfs_create_x64("nextoff", S_IRUGO, d, &a->nextoff); + debugfs_create_x64("infooff", S_IRUGO, d, &a->infooff); + debugfs_create_x64("dataoff", S_IRUGO, d, &a->dataoff); + debugfs_create_x64("mapoff", S_IRUGO, d, &a->mapoff); + debugfs_create_x64("logoff", S_IRUGO, d, &a->logoff); + debugfs_create_x64("info2off", S_IRUGO, d, &a->info2off); + debugfs_create_x32("flags", S_IRUGO, d, &a->flags); +} + +static void btt_debugfs_init(struct btt *btt) +{ + int i = 0; + struct arena_info *arena; + + btt->debugfs_dir = debugfs_create_dir(dev_name(&btt->nd_btt->dev), + debugfs_root); + if (IS_ERR_OR_NULL(btt->debugfs_dir)) + return; + + list_for_each_entry(arena, &btt->arena_list, list) { + arena_debugfs_init(arena, btt->debugfs_dir, i); + i++; + } +} + +/* + * This function accepts two log entries, and uses the + * sequence number to find the 'older' entry. + * It also updates the sequence number in this old entry to + * make it the 'new' one if the mark_flag is set. + * Finally, it returns which of the entries was the older one. + * + * TODO The logic feels a bit kludge-y. make it better.. + */ +static int btt_log_get_old(struct log_entry *ent) +{ + int old; + + /* + * the first ever time this is seen, the entry goes into [0] + * the next time, the following logic works out to put this + * (next) entry into [1] + */ + if (ent[0].seq == 0) { + ent[0].seq = cpu_to_le32(1); + return 0; + } + + if (ent[0].seq == ent[1].seq) + return -EINVAL; + if (le32_to_cpu(ent[0].seq) + le32_to_cpu(ent[1].seq) > 5) + return -EINVAL; + + if (le32_to_cpu(ent[0].seq) < le32_to_cpu(ent[1].seq)) { + if (le32_to_cpu(ent[1].seq) - le32_to_cpu(ent[0].seq) == 1) + old = 0; + else + old = 1; + } else { + if (le32_to_cpu(ent[0].seq) - le32_to_cpu(ent[1].seq) == 1) + old = 1; + else + old = 0; + } + + return old; +} + +static struct device *to_dev(struct arena_info *arena) +{ + return &arena->nd_btt->dev; +} + +/* + * This function copies the desired (old/new) log entry into ent if + * it is not NULL. It returns the sub-slot number (0 or 1) + * where the desired log entry was found. Negative return values + * indicate errors. + */ +static int btt_log_read(struct arena_info *arena, u32 lane, + struct log_entry *ent, int old_flag) +{ + int ret; + int old_ent, ret_ent; + struct log_entry log[2]; + + ret = btt_log_read_pair(arena, lane, log); + if (ret) + return -EIO; + + old_ent = btt_log_get_old(log); + if (old_ent < 0 || old_ent > 1) { + dev_info(to_dev(arena), + "log corruption (%d): lane %d seq [%d, %d]\n", + old_ent, lane, log[0].seq, log[1].seq); + /* TODO set error state? */ + return -EIO; + } + + ret_ent = (old_flag ? old_ent : (1 - old_ent)); + + if (ent != NULL) + memcpy(ent, &log[ret_ent], LOG_ENT_SIZE); + + return ret_ent; +} + +/* + * This function commits a log entry to media + * It does _not_ prepare the freelist entry for the next write + * btt_flog_write is the wrapper for updating the freelist elements + */ +static int __btt_log_write(struct arena_info *arena, u32 lane, + u32 sub, struct log_entry *ent) +{ + int ret; + /* + * Ignore the padding in log_entry for calculating log_half. + * The entry is 'committed' when we write the sequence number, + * and we want to ensure that that is the last thing written. + * We don't bother writing the padding as that would be extra + * media wear and write amplification + */ + unsigned int log_half = (LOG_ENT_SIZE - 2 * sizeof(u64)) / 2; + u64 ns_off = arena->logoff + (((2 * lane) + sub) * LOG_ENT_SIZE); + void *src = ent; + + /* split the 16B write into atomic, durable halves */ + ret = arena_write_bytes(arena, ns_off, src, log_half); + if (ret) + return ret; + + ns_off += log_half; + src += log_half; + return arena_write_bytes(arena, ns_off, src, log_half); +} + +static int btt_flog_write(struct arena_info *arena, u32 lane, u32 sub, + struct log_entry *ent) +{ + int ret; + + ret = __btt_log_write(arena, lane, sub, ent); + if (ret) + return ret; + + /* prepare the next free entry */ + arena->freelist[lane].sub = 1 - arena->freelist[lane].sub; + if (++(arena->freelist[lane].seq) == 4) + arena->freelist[lane].seq = 1; + arena->freelist[lane].block = le32_to_cpu(ent->old_map); + + return ret; +} + +/* + * This function initializes the BTT map to the initial state, which is + * all-zeroes, and indicates an identity mapping + */ +static int btt_map_init(struct arena_info *arena) +{ + int ret = -EINVAL; + void *zerobuf; + size_t offset = 0; + size_t chunk_size = SZ_2M; + size_t mapsize = arena->logoff - arena->mapoff; + + zerobuf = kzalloc(chunk_size, GFP_KERNEL); + if (!zerobuf) + return -ENOMEM; + + while (mapsize) { + size_t size = min(mapsize, chunk_size); + + ret = arena_write_bytes(arena, arena->mapoff + offset, zerobuf, + size); + if (ret) + goto free; + + offset += size; + mapsize -= size; + cond_resched(); + } + + free: + kfree(zerobuf); + return ret; +} + +/* + * This function initializes the BTT log with 'fake' entries pointing + * to the initial reserved set of blocks as being free + */ +static int btt_log_init(struct arena_info *arena) +{ + int ret; + u32 i; + struct log_entry log, zerolog; + + memset(&zerolog, 0, sizeof(zerolog)); + + for (i = 0; i < arena->nfree; i++) { + log.lba = cpu_to_le32(i); + log.old_map = cpu_to_le32(arena->external_nlba + i); + log.new_map = cpu_to_le32(arena->external_nlba + i); + log.seq = cpu_to_le32(LOG_SEQ_INIT); + ret = __btt_log_write(arena, i, 0, &log); + if (ret) + return ret; + ret = __btt_log_write(arena, i, 1, &zerolog); + if (ret) + return ret; + } + + return 0; +} + +static int btt_freelist_init(struct arena_info *arena) +{ + int old, new, ret; + u32 i, map_entry; + struct log_entry log_new, log_old; + + arena->freelist = kcalloc(arena->nfree, sizeof(struct free_entry), + GFP_KERNEL); + if (!arena->freelist) + return -ENOMEM; + + for (i = 0; i < arena->nfree; i++) { + old = btt_log_read(arena, i, &log_old, LOG_OLD_ENT); + if (old < 0) + return old; + + new = btt_log_read(arena, i, &log_new, LOG_NEW_ENT); + if (new < 0) + return new; + + /* sub points to the next one to be overwritten */ + arena->freelist[i].sub = 1 - new; + arena->freelist[i].seq = nd_inc_seq(le32_to_cpu(log_new.seq)); + arena->freelist[i].block = le32_to_cpu(log_new.old_map); + + /* This implies a newly created or untouched flog entry */ + if (log_new.old_map == log_new.new_map) + continue; + + /* Check if map recovery is needed */ + ret = btt_map_read(arena, le32_to_cpu(log_new.lba), &map_entry, + NULL, NULL); + if (ret) + return ret; + if ((le32_to_cpu(log_new.new_map) != map_entry) && + (le32_to_cpu(log_new.old_map) == map_entry)) { + /* + * Last transaction wrote the flog, but wasn't able + * to complete the map write. So fix up the map. + */ + ret = btt_map_write(arena, le32_to_cpu(log_new.lba), + le32_to_cpu(log_new.new_map), 0, 0); + if (ret) + return ret; + } + + } + + return 0; +} + +static int btt_rtt_init(struct arena_info *arena) +{ + arena->rtt = kcalloc(arena->nfree, sizeof(u32), GFP_KERNEL); + if (arena->rtt == NULL) + return -ENOMEM; + + return 0; +} + +static int btt_maplocks_init(struct arena_info *arena) +{ + u32 i; + + arena->map_locks = kcalloc(arena->nfree, sizeof(struct aligned_lock), + GFP_KERNEL); + if (!arena->map_locks) + return -ENOMEM; + + for (i = 0; i < arena->nfree; i++) + spin_lock_init(&arena->map_locks[i].lock); + + return 0; +} + +static struct arena_info *alloc_arena(struct btt *btt, size_t size, + size_t start, size_t arena_off) +{ + struct arena_info *arena; + u64 logsize, mapsize, datasize; + u64 available = size; + + arena = kzalloc(sizeof(struct arena_info), GFP_KERNEL); + if (!arena) + return NULL; + arena->nd_btt = btt->nd_btt; + + if (!size) + return arena; + + arena->size = size; + arena->external_lba_start = start; + arena->external_lbasize = btt->lbasize; + arena->internal_lbasize = roundup(arena->external_lbasize, + INT_LBASIZE_ALIGNMENT); + arena->nfree = BTT_DEFAULT_NFREE; + arena->version_major = 1; + arena->version_minor = 1; + + if (available % BTT_PG_SIZE) + available -= (available % BTT_PG_SIZE); + + /* Two pages are reserved for the super block and its copy */ + available -= 2 * BTT_PG_SIZE; + + /* The log takes a fixed amount of space based on nfree */ + logsize = roundup(2 * arena->nfree * sizeof(struct log_entry), + BTT_PG_SIZE); + available -= logsize; + + /* Calculate optimal split between map and data area */ + arena->internal_nlba = div_u64(available - BTT_PG_SIZE, + arena->internal_lbasize + MAP_ENT_SIZE); + arena->external_nlba = arena->internal_nlba - arena->nfree; + + mapsize = roundup((arena->external_nlba * MAP_ENT_SIZE), BTT_PG_SIZE); + datasize = available - mapsize; + + /* 'Absolute' values, relative to start of storage space */ + arena->infooff = arena_off; + arena->dataoff = arena->infooff + BTT_PG_SIZE; + arena->mapoff = arena->dataoff + datasize; + arena->logoff = arena->mapoff + mapsize; + arena->info2off = arena->logoff + logsize; + return arena; +} + +static void free_arenas(struct btt *btt) +{ + struct arena_info *arena, *next; + + list_for_each_entry_safe(arena, next, &btt->arena_list, list) { + list_del(&arena->list); + kfree(arena->rtt); + kfree(arena->map_locks); + kfree(arena->freelist); + debugfs_remove_recursive(arena->debugfs_dir); + kfree(arena); + } +} + +/* + * This function checks if the metadata layout is valid and error free + */ +static int arena_is_valid(struct arena_info *arena, struct btt_sb *super, + u8 *uuid, u32 lbasize) +{ + u64 checksum; + + if (memcmp(super->uuid, uuid, 16)) + return 0; + + checksum = le64_to_cpu(super->checksum); + super->checksum = 0; + if (checksum != nd_btt_sb_checksum(super)) + return 0; + super->checksum = cpu_to_le64(checksum); + + if (lbasize != le32_to_cpu(super->external_lbasize)) + return 0; + + /* TODO: figure out action for this */ + if ((le32_to_cpu(super->flags) & IB_FLAG_ERROR_MASK) != 0) + dev_info(to_dev(arena), "Found arena with an error flag\n"); + + return 1; +} + +/* + * This function reads an existing valid btt superblock and + * populates the corresponding arena_info struct + */ +static void parse_arena_meta(struct arena_info *arena, struct btt_sb *super, + u64 arena_off) +{ + arena->internal_nlba = le32_to_cpu(super->internal_nlba); + arena->internal_lbasize = le32_to_cpu(super->internal_lbasize); + arena->external_nlba = le32_to_cpu(super->external_nlba); + arena->external_lbasize = le32_to_cpu(super->external_lbasize); + arena->nfree = le32_to_cpu(super->nfree); + arena->version_major = le16_to_cpu(super->version_major); + arena->version_minor = le16_to_cpu(super->version_minor); + + arena->nextoff = (super->nextoff == 0) ? 0 : (arena_off + + le64_to_cpu(super->nextoff)); + arena->infooff = arena_off; + arena->dataoff = arena_off + le64_to_cpu(super->dataoff); + arena->mapoff = arena_off + le64_to_cpu(super->mapoff); + arena->logoff = arena_off + le64_to_cpu(super->logoff); + arena->info2off = arena_off + le64_to_cpu(super->info2off); + + arena->size = (super->nextoff > 0) ? (le64_to_cpu(super->nextoff)) : + (arena->info2off - arena->infooff + BTT_PG_SIZE); + + arena->flags = le32_to_cpu(super->flags); +} + +static int discover_arenas(struct btt *btt) +{ + int ret = 0; + struct arena_info *arena; + struct btt_sb *super; + size_t remaining = btt->rawsize; + u64 cur_nlba = 0; + size_t cur_off = 0; + int num_arenas = 0; + + super = kzalloc(sizeof(*super), GFP_KERNEL); + if (!super) + return -ENOMEM; + + while (remaining) { + /* Alloc memory for arena */ + arena = alloc_arena(btt, 0, 0, 0); + if (!arena) { + ret = -ENOMEM; + goto out_super; + } + + arena->infooff = cur_off; + ret = btt_info_read(arena, super); + if (ret) + goto out; + + if (!arena_is_valid(arena, super, btt->nd_btt->uuid, + btt->lbasize)) { + if (remaining == btt->rawsize) { + btt->init_state = INIT_NOTFOUND; + dev_info(to_dev(arena), "No existing arenas\n"); + goto out; + } else { + dev_info(to_dev(arena), + "Found corrupted metadata!\n"); + ret = -ENODEV; + goto out; + } + } + + arena->external_lba_start = cur_nlba; + parse_arena_meta(arena, super, cur_off); + + ret = btt_freelist_init(arena); + if (ret) + goto out; + + ret = btt_rtt_init(arena); + if (ret) + goto out; + + ret = btt_maplocks_init(arena); + if (ret) + goto out; + + list_add_tail(&arena->list, &btt->arena_list); + + remaining -= arena->size; + cur_off += arena->size; + cur_nlba += arena->external_nlba; + num_arenas++; + + if (arena->nextoff == 0) + break; + } + btt->num_arenas = num_arenas; + btt->nlba = cur_nlba; + btt->init_state = INIT_READY; + + kfree(super); + return ret; + + out: + kfree(arena); + free_arenas(btt); + out_super: + kfree(super); + return ret; +} + +static int create_arenas(struct btt *btt) +{ + size_t remaining = btt->rawsize; + size_t cur_off = 0; + + while (remaining) { + struct arena_info *arena; + size_t arena_size = min_t(u64, ARENA_MAX_SIZE, remaining); + + remaining -= arena_size; + if (arena_size < ARENA_MIN_SIZE) + break; + + arena = alloc_arena(btt, arena_size, btt->nlba, cur_off); + if (!arena) { + free_arenas(btt); + return -ENOMEM; + } + btt->nlba += arena->external_nlba; + if (remaining >= ARENA_MIN_SIZE) + arena->nextoff = arena->size; + else + arena->nextoff = 0; + cur_off += arena_size; + list_add_tail(&arena->list, &btt->arena_list); + } + + return 0; +} + +/* + * This function completes arena initialization by writing + * all the metadata. + * It is only called for an uninitialized arena when a write + * to that arena occurs for the first time. + */ +static int btt_arena_write_layout(struct arena_info *arena, u8 *uuid) +{ + int ret; + struct btt_sb *super; + + ret = btt_map_init(arena); + if (ret) + return ret; + + ret = btt_log_init(arena); + if (ret) + return ret; + + super = kzalloc(sizeof(struct btt_sb), GFP_NOIO); + if (!super) + return -ENOMEM; + + strncpy(super->signature, BTT_SIG, BTT_SIG_LEN); + memcpy(super->uuid, uuid, 16); + super->flags = cpu_to_le32(arena->flags); + super->version_major = cpu_to_le16(arena->version_major); + super->version_minor = cpu_to_le16(arena->version_minor); + super->external_lbasize = cpu_to_le32(arena->external_lbasize); + super->external_nlba = cpu_to_le32(arena->external_nlba); + super->internal_lbasize = cpu_to_le32(arena->internal_lbasize); + super->internal_nlba = cpu_to_le32(arena->internal_nlba); + super->nfree = cpu_to_le32(arena->nfree); + super->infosize = cpu_to_le32(sizeof(struct btt_sb)); + super->nextoff = cpu_to_le64(arena->nextoff); + /* + * Subtract arena->infooff (arena start) so numbers are relative + * to 'this' arena + */ + super->dataoff = cpu_to_le64(arena->dataoff - arena->infooff); + super->mapoff = cpu_to_le64(arena->mapoff - arena->infooff); + super->logoff = cpu_to_le64(arena->logoff - arena->infooff); + super->info2off = cpu_to_le64(arena->info2off - arena->infooff); + + super->flags = 0; + super->checksum = cpu_to_le64(nd_btt_sb_checksum(super)); + + ret = btt_info_write(arena, super); + + kfree(super); + return ret; +} + +/* + * This function completes the initialization for the BTT namespace + * such that it is ready to accept IOs + */ +static int btt_meta_init(struct btt *btt) +{ + int ret = 0; + struct arena_info *arena; + + mutex_lock(&btt->init_lock); + list_for_each_entry(arena, &btt->arena_list, list) { + ret = btt_arena_write_layout(arena, btt->nd_btt->uuid); + if (ret) + goto unlock; + + ret = btt_freelist_init(arena); + if (ret) + goto unlock; + + ret = btt_rtt_init(arena); + if (ret) + goto unlock; + + ret = btt_maplocks_init(arena); + if (ret) + goto unlock; + } + + btt->init_state = INIT_READY; + + unlock: + mutex_unlock(&btt->init_lock); + return ret; +} + +/* + * This function calculates the arena in which the given LBA lies + * by doing a linear walk. This is acceptable since we expect only + * a few arenas. If we have backing devices that get much larger, + * we can construct a balanced binary tree of arenas at init time + * so that this range search becomes faster. + */ +static int lba_to_arena(struct btt *btt, sector_t sector, __u32 *premap, + struct arena_info **arena) +{ + struct arena_info *arena_list; + __u64 lba = div_u64(sector << SECTOR_SHIFT, btt->sector_size); + + list_for_each_entry(arena_list, &btt->arena_list, list) { + if (lba < arena_list->external_nlba) { + *arena = arena_list; + *premap = lba; + return 0; + } + lba -= arena_list->external_nlba; + } + + return -EIO; +} + +/* + * The following (lock_map, unlock_map) are mostly just to improve + * readability, since they index into an array of locks + */ +static void lock_map(struct arena_info *arena, u32 premap) + __acquires(&arena->map_locks[idx].lock) +{ + u32 idx = (premap * MAP_ENT_SIZE / L1_CACHE_BYTES) % arena->nfree; + + spin_lock(&arena->map_locks[idx].lock); +} + +static void unlock_map(struct arena_info *arena, u32 premap) + __releases(&arena->map_locks[idx].lock) +{ + u32 idx = (premap * MAP_ENT_SIZE / L1_CACHE_BYTES) % arena->nfree; + + spin_unlock(&arena->map_locks[idx].lock); +} + +static u64 to_namespace_offset(struct arena_info *arena, u64 lba) +{ + return arena->dataoff + ((u64)lba * arena->internal_lbasize); +} + +static int btt_data_read(struct arena_info *arena, struct page *page, + unsigned int off, u32 lba, u32 len) +{ + int ret; + u64 nsoff = to_namespace_offset(arena, lba); + void *mem = kmap_atomic(page); + + ret = arena_read_bytes(arena, nsoff, mem + off, len); + kunmap_atomic(mem); + + return ret; +} + +static int btt_data_write(struct arena_info *arena, u32 lba, + struct page *page, unsigned int off, u32 len) +{ + int ret; + u64 nsoff = to_namespace_offset(arena, lba); + void *mem = kmap_atomic(page); + + ret = arena_write_bytes(arena, nsoff, mem + off, len); + kunmap_atomic(mem); + + return ret; +} + +static void zero_fill_data(struct page *page, unsigned int off, u32 len) +{ + void *mem = kmap_atomic(page); + + memset(mem + off, 0, len); + kunmap_atomic(mem); +} + +static int btt_read_pg(struct btt *btt, struct page *page, unsigned int off, + sector_t sector, unsigned int len) +{ + int ret = 0; + int t_flag, e_flag; + struct arena_info *arena = NULL; + u32 lane = 0, premap, postmap; + + while (len) { + u32 cur_len; + + lane = nd_region_acquire_lane(btt->nd_region); + + ret = lba_to_arena(btt, sector, &premap, &arena); + if (ret) + goto out_lane; + + cur_len = min(btt->sector_size, len); + + ret = btt_map_read(arena, premap, &postmap, &t_flag, &e_flag); + if (ret) + goto out_lane; + + /* + * We loop to make sure that the post map LBA didn't change + * from under us between writing the RTT and doing the actual + * read. + */ + while (1) { + u32 new_map; + + if (t_flag) { + zero_fill_data(page, off, cur_len); + goto out_lane; + } + + if (e_flag) { + ret = -EIO; + goto out_lane; + } + + arena->rtt[lane] = RTT_VALID | postmap; + /* + * Barrier to make sure this write is not reordered + * to do the verification map_read before the RTT store + */ + barrier(); + + ret = btt_map_read(arena, premap, &new_map, &t_flag, + &e_flag); + if (ret) + goto out_rtt; + + if (postmap == new_map) + break; + + postmap = new_map; + } + + ret = btt_data_read(arena, page, off, postmap, cur_len); + if (ret) + goto out_rtt; + + arena->rtt[lane] = RTT_INVALID; + nd_region_release_lane(btt->nd_region, lane); + + len -= cur_len; + off += cur_len; + sector += btt->sector_size >> SECTOR_SHIFT; + } + + return 0; + + out_rtt: + arena->rtt[lane] = RTT_INVALID; + out_lane: + nd_region_release_lane(btt->nd_region, lane); + return ret; +} + +static int btt_write_pg(struct btt *btt, sector_t sector, struct page *page, + unsigned int off, unsigned int len) +{ + int ret = 0; + struct arena_info *arena = NULL; + u32 premap = 0, old_postmap, new_postmap, lane = 0, i; + struct log_entry log; + int sub; + + while (len) { + u32 cur_len; + + lane = nd_region_acquire_lane(btt->nd_region); + + ret = lba_to_arena(btt, sector, &premap, &arena); + if (ret) + goto out_lane; + cur_len = min(btt->sector_size, len); + + if ((arena->flags & IB_FLAG_ERROR_MASK) != 0) { + ret = -EIO; + goto out_lane; + } + + new_postmap = arena->freelist[lane].block; + + /* Wait if the new block is being read from */ + for (i = 0; i < arena->nfree; i++) + while (arena->rtt[i] == (RTT_VALID | new_postmap)) + cpu_relax(); + + + if (new_postmap >= arena->internal_nlba) { + ret = -EIO; + goto out_lane; + } else + ret = btt_data_write(arena, new_postmap, page, + off, cur_len); + if (ret) + goto out_lane; + + lock_map(arena, premap); + ret = btt_map_read(arena, premap, &old_postmap, NULL, NULL); + if (ret) + goto out_map; + if (old_postmap >= arena->internal_nlba) { + ret = -EIO; + goto out_map; + } + + log.lba = cpu_to_le32(premap); + log.old_map = cpu_to_le32(old_postmap); + log.new_map = cpu_to_le32(new_postmap); + log.seq = cpu_to_le32(arena->freelist[lane].seq); + sub = arena->freelist[lane].sub; + ret = btt_flog_write(arena, lane, sub, &log); + if (ret) + goto out_map; + + ret = btt_map_write(arena, premap, new_postmap, 0, 0); + if (ret) + goto out_map; + + unlock_map(arena, premap); + nd_region_release_lane(btt->nd_region, lane); + + len -= cur_len; + off += cur_len; + sector += btt->sector_size >> SECTOR_SHIFT; + } + + return 0; + + out_map: + unlock_map(arena, premap); + out_lane: + nd_region_release_lane(btt->nd_region, lane); + return ret; +} + +static int btt_do_bvec(struct btt *btt, struct page *page, + unsigned int len, unsigned int off, int rw, + sector_t sector) +{ + int ret; + + if (rw == READ) { + ret = btt_read_pg(btt, page, off, sector, len); + flush_dcache_page(page); + } else { + flush_dcache_page(page); + ret = btt_write_pg(btt, sector, page, off, len); + } + + return ret; +} + +static void btt_make_request(struct request_queue *q, struct bio *bio) +{ + struct btt *btt = q->queuedata; + struct bvec_iter iter; + struct bio_vec bvec; + int err = 0, rw; + + rw = bio_data_dir(bio); + bio_for_each_segment(bvec, bio, iter) { + unsigned int len = bvec.bv_len; + + BUG_ON(len > PAGE_SIZE); + /* Make sure len is in multiples of sector size. */ + /* XXX is this right? */ + BUG_ON(len < btt->sector_size); + BUG_ON(len % btt->sector_size); + + err = btt_do_bvec(btt, bvec.bv_page, len, bvec.bv_offset, + rw, iter.bi_sector); + if (err) { + dev_info(&btt->nd_btt->dev, + "io error in %s sector %lld, len %d,\n", + (rw == READ) ? "READ" : "WRITE", + (unsigned long long) iter.bi_sector, len); + goto out; + } + } + +out: + bio_endio(bio, err); +} + +static int btt_rw_page(struct block_device *bdev, sector_t sector, + struct page *page, int rw) +{ + struct btt *btt = bdev->bd_disk->private_data; + + btt_do_bvec(btt, page, PAGE_CACHE_SIZE, 0, rw, sector); + page_endio(page, rw & WRITE, 0); + return 0; +} + + +static int btt_getgeo(struct block_device *bd, struct hd_geometry *geo) +{ + /* some standard values */ + geo->heads = 1 << 6; + geo->sectors = 1 << 5; + geo->cylinders = get_capacity(bd->bd_disk) >> 11; + return 0; +} + +static const struct block_device_operations btt_fops = { + .owner = THIS_MODULE, + .rw_page = btt_rw_page, + .getgeo = btt_getgeo, +}; + +static int btt_blk_init(struct btt *btt) +{ + struct nd_btt *nd_btt = btt->nd_btt; + struct nd_namespace_common *ndns = nd_btt->ndns; + + /* create a new disk and request queue for btt */ + btt->btt_queue = blk_alloc_queue(GFP_KERNEL); + if (!btt->btt_queue) + return -ENOMEM; + + btt->btt_disk = alloc_disk(0); + if (!btt->btt_disk) { + blk_cleanup_queue(btt->btt_queue); + return -ENOMEM; + } + + nvdimm_namespace_disk_name(ndns, btt->btt_disk->disk_name); + btt->btt_disk->driverfs_dev = &btt->nd_btt->dev; + btt->btt_disk->major = btt_major; + btt->btt_disk->first_minor = 0; + btt->btt_disk->fops = &btt_fops; + btt->btt_disk->private_data = btt; + btt->btt_disk->queue = btt->btt_queue; + btt->btt_disk->flags = GENHD_FL_EXT_DEVT; + + blk_queue_make_request(btt->btt_queue, btt_make_request); + blk_queue_logical_block_size(btt->btt_queue, btt->sector_size); + blk_queue_max_hw_sectors(btt->btt_queue, UINT_MAX); + blk_queue_bounce_limit(btt->btt_queue, BLK_BOUNCE_ANY); + queue_flag_set_unlocked(QUEUE_FLAG_NONROT, btt->btt_queue); + btt->btt_queue->queuedata = btt; + + set_capacity(btt->btt_disk, + btt->nlba * btt->sector_size >> SECTOR_SHIFT); + add_disk(btt->btt_disk); + + return 0; +} + +static void btt_blk_cleanup(struct btt *btt) +{ + del_gendisk(btt->btt_disk); + put_disk(btt->btt_disk); + blk_cleanup_queue(btt->btt_queue); +} + +/** + * btt_init - initialize a block translation table for the given device + * @nd_btt: device with BTT geometry and backing device info + * @rawsize: raw size in bytes of the backing device + * @lbasize: lba size of the backing device + * @uuid: A uuid for the backing device - this is stored on media + * @maxlane: maximum number of parallel requests the device can handle + * + * Initialize a Block Translation Table on a backing device to provide + * single sector power fail atomicity. + * + * Context: + * Might sleep. + * + * Returns: + * Pointer to a new struct btt on success, NULL on failure. + */ +static struct btt *btt_init(struct nd_btt *nd_btt, unsigned long long rawsize, + u32 lbasize, u8 *uuid, struct nd_region *nd_region) +{ + int ret; + struct btt *btt; + struct device *dev = &nd_btt->dev; + + btt = kzalloc(sizeof(struct btt), GFP_KERNEL); + if (!btt) + return NULL; + + btt->nd_btt = nd_btt; + btt->rawsize = rawsize; + btt->lbasize = lbasize; + btt->sector_size = ((lbasize >= 4096) ? 4096 : 512); + INIT_LIST_HEAD(&btt->arena_list); + mutex_init(&btt->init_lock); + btt->nd_region = nd_region; + + ret = discover_arenas(btt); + if (ret) { + dev_err(dev, "init: error in arena_discover: %d\n", ret); + goto out_free; + } + + if (btt->init_state != INIT_READY) { + btt->num_arenas = (rawsize / ARENA_MAX_SIZE) + + ((rawsize % ARENA_MAX_SIZE) ? 1 : 0); + dev_dbg(dev, "init: %d arenas for %llu rawsize\n", + btt->num_arenas, rawsize); + + ret = create_arenas(btt); + if (ret) { + dev_info(dev, "init: create_arenas: %d\n", ret); + goto out_free; + } + + ret = btt_meta_init(btt); + if (ret) { + dev_err(dev, "init: error in meta_init: %d\n", ret); + return NULL; + } + } + + ret = btt_blk_init(btt); + if (ret) { + dev_err(dev, "init: error in blk_init: %d\n", ret); + goto out_free; + } + + btt_debugfs_init(btt); + + return btt; + + out_free: + kfree(btt); + return NULL; +} + +/** + * btt_fini - de-initialize a BTT + * @btt: the BTT handle that was generated by btt_init + * + * De-initialize a Block Translation Table on device removal + * + * Context: + * Might sleep. + */ +static void btt_fini(struct btt *btt) +{ + if (btt) { + btt_blk_cleanup(btt); + free_arenas(btt); + debugfs_remove_recursive(btt->debugfs_dir); + kfree(btt); + } +} + +int nvdimm_namespace_attach_btt(struct nd_namespace_common *ndns) +{ + struct nd_btt *nd_btt = to_nd_btt(ndns->claim); + struct nd_region *nd_region; + struct btt *btt; + size_t rawsize; + + if (!nd_btt->uuid || !nd_btt->ndns || !nd_btt->lbasize) + return -ENODEV; + + rawsize = nvdimm_namespace_capacity(ndns) - SZ_4K; + if (rawsize < ARENA_MIN_SIZE) { + return -ENXIO; + } + nd_region = to_nd_region(nd_btt->dev.parent); + btt = btt_init(nd_btt, rawsize, nd_btt->lbasize, nd_btt->uuid, + nd_region); + if (!btt) + return -ENOMEM; + nd_btt->btt = btt; + + return 0; +} +EXPORT_SYMBOL(nvdimm_namespace_attach_btt); + +int nvdimm_namespace_detach_btt(struct nd_namespace_common *ndns) +{ + struct nd_btt *nd_btt = to_nd_btt(ndns->claim); + struct btt *btt = nd_btt->btt; + + btt_fini(btt); + nd_btt->btt = NULL; + + return 0; +} +EXPORT_SYMBOL(nvdimm_namespace_detach_btt); + +static int __init nd_btt_init(void) +{ + int rc; + + BUILD_BUG_ON(sizeof(struct btt_sb) != SZ_4K); + + btt_major = register_blkdev(0, "btt"); + if (btt_major < 0) + return btt_major; + + debugfs_root = debugfs_create_dir("btt", NULL); + if (IS_ERR_OR_NULL(debugfs_root)) { + rc = -ENXIO; + goto err_debugfs; + } + + return 0; + + err_debugfs: + unregister_blkdev(btt_major, "btt"); + + return rc; +} + +static void __exit nd_btt_exit(void) +{ + debugfs_remove_recursive(debugfs_root); + unregister_blkdev(btt_major, "btt"); +} + +MODULE_ALIAS_ND_DEVICE(ND_DEVICE_BTT); +MODULE_AUTHOR("Vishal Verma "); +MODULE_LICENSE("GPL v2"); +module_init(nd_btt_init); +module_exit(nd_btt_exit); diff --git a/drivers/nvdimm/btt.h b/drivers/nvdimm/btt.h index e8f6d8e0ddd3..8c95a7792c3e 100644 --- a/drivers/nvdimm/btt.h +++ b/drivers/nvdimm/btt.h @@ -19,6 +19,39 @@ #define BTT_SIG_LEN 16 #define BTT_SIG "BTT_ARENA_INFO\0" +#define MAP_ENT_SIZE 4 +#define MAP_TRIM_SHIFT 31 +#define MAP_TRIM_MASK (1 << MAP_TRIM_SHIFT) +#define MAP_ERR_SHIFT 30 +#define MAP_ERR_MASK (1 << MAP_ERR_SHIFT) +#define MAP_LBA_MASK (~((1 << MAP_TRIM_SHIFT) | (1 << MAP_ERR_SHIFT))) +#define MAP_ENT_NORMAL 0xC0000000 +#define LOG_ENT_SIZE sizeof(struct log_entry) +#define ARENA_MIN_SIZE (1UL << 24) /* 16 MB */ +#define ARENA_MAX_SIZE (1ULL << 39) /* 512 GB */ +#define RTT_VALID (1UL << 31) +#define RTT_INVALID 0 +#define INT_LBASIZE_ALIGNMENT 256 +#define BTT_PG_SIZE 4096 +#define BTT_DEFAULT_NFREE ND_MAX_LANES +#define LOG_SEQ_INIT 1 + +#define IB_FLAG_ERROR 0x00000001 +#define IB_FLAG_ERROR_MASK 0x00000001 + +enum btt_init_state { + INIT_UNCHECKED = 0, + INIT_NOTFOUND, + INIT_READY +}; + +struct log_entry { + __le32 lba; + __le32 old_map; + __le32 new_map; + __le32 seq; + __le64 padding[2]; +}; struct btt_sb { u8 signature[BTT_SIG_LEN]; @@ -42,4 +75,112 @@ struct btt_sb { __le64 checksum; }; +struct free_entry { + u32 block; + u8 sub; + u8 seq; +}; + +struct aligned_lock { + union { + spinlock_t lock; + u8 cacheline_padding[L1_CACHE_BYTES]; + }; +}; + +/** + * struct arena_info - handle for an arena + * @size: Size in bytes this arena occupies on the raw device. + * This includes arena metadata. + * @external_lba_start: The first external LBA in this arena. + * @internal_nlba: Number of internal blocks available in the arena + * including nfree reserved blocks + * @internal_lbasize: Internal and external lba sizes may be different as + * we can round up 'odd' external lbasizes such as 520B + * to be aligned. + * @external_nlba: Number of blocks contributed by the arena to the number + * reported to upper layers. (internal_nlba - nfree) + * @external_lbasize: LBA size as exposed to upper layers. + * @nfree: A reserve number of 'free' blocks that is used to + * handle incoming writes. + * @version_major: Metadata layout version major. + * @version_minor: Metadata layout version minor. + * @nextoff: Offset in bytes to the start of the next arena. + * @infooff: Offset in bytes to the info block of this arena. + * @dataoff: Offset in bytes to the data area of this arena. + * @mapoff: Offset in bytes to the map area of this arena. + * @logoff: Offset in bytes to the log area of this arena. + * @info2off: Offset in bytes to the backup info block of this arena. + * @freelist: Pointer to in-memory list of free blocks + * @rtt: Pointer to in-memory "Read Tracking Table" + * @map_locks: Spinlocks protecting concurrent map writes + * @nd_btt: Pointer to parent nd_btt structure. + * @list: List head for list of arenas + * @debugfs_dir: Debugfs dentry + * @flags: Arena flags - may signify error states. + * + * arena_info is a per-arena handle. Once an arena is narrowed down for an + * IO, this struct is passed around for the duration of the IO. + */ +struct arena_info { + u64 size; /* Total bytes for this arena */ + u64 external_lba_start; + u32 internal_nlba; + u32 internal_lbasize; + u32 external_nlba; + u32 external_lbasize; + u32 nfree; + u16 version_major; + u16 version_minor; + /* Byte offsets to the different on-media structures */ + u64 nextoff; + u64 infooff; + u64 dataoff; + u64 mapoff; + u64 logoff; + u64 info2off; + /* Pointers to other in-memory structures for this arena */ + struct free_entry *freelist; + u32 *rtt; + struct aligned_lock *map_locks; + struct nd_btt *nd_btt; + struct list_head list; + struct dentry *debugfs_dir; + /* Arena flags */ + u32 flags; +}; + +/** + * struct btt - handle for a BTT instance + * @btt_disk: Pointer to the gendisk for BTT device + * @btt_queue: Pointer to the request queue for the BTT device + * @arena_list: Head of the list of arenas + * @debugfs_dir: Debugfs dentry + * @nd_btt: Parent nd_btt struct + * @nlba: Number of logical blocks exposed to the upper layers + * after removing the amount of space needed by metadata + * @rawsize: Total size in bytes of the available backing device + * @lbasize: LBA size as requested and presented to upper layers. + * This is sector_size + size of any metadata. + * @sector_size: The Linux sector size - 512 or 4096 + * @lanes: Per-lane spinlocks + * @init_lock: Mutex used for the BTT initialization + * @init_state: Flag describing the initialization state for the BTT + * @num_arenas: Number of arenas in the BTT instance + */ +struct btt { + struct gendisk *btt_disk; + struct request_queue *btt_queue; + struct list_head arena_list; + struct dentry *debugfs_dir; + struct nd_btt *nd_btt; + u64 nlba; + unsigned long long rawsize; + u32 lbasize; + u32 sector_size; + struct nd_region *nd_region; + struct mutex init_lock; + int init_state; + int num_arenas; +}; #endif diff --git a/drivers/nvdimm/btt_devs.c b/drivers/nvdimm/btt_devs.c index effb70a88347..470fbdccd0ac 100644 --- a/drivers/nvdimm/btt_devs.c +++ b/drivers/nvdimm/btt_devs.c @@ -348,7 +348,8 @@ struct device *nd_btt_create(struct nd_region *nd_region) */ u64 nd_btt_sb_checksum(struct btt_sb *btt_sb) { - u64 sum, sum_save; + u64 sum; + __le64 sum_save; sum_save = btt_sb->checksum; btt_sb->checksum = 0; diff --git a/drivers/nvdimm/namespace_devs.c b/drivers/nvdimm/namespace_devs.c index 2c50a0719f8d..4aa647c8d644 100644 --- a/drivers/nvdimm/namespace_devs.c +++ b/drivers/nvdimm/namespace_devs.c @@ -76,6 +76,30 @@ static bool is_namespace_io(struct device *dev) return dev ? dev->type == &namespace_io_device_type : false; } +const char *nvdimm_namespace_disk_name(struct nd_namespace_common *ndns, + char *name) +{ + struct nd_region *nd_region = to_nd_region(ndns->dev.parent); + const char *suffix = ""; + + if (ndns->claim && is_nd_btt(ndns->claim)) + suffix = "s"; + + if (is_namespace_pmem(&ndns->dev) || is_namespace_io(&ndns->dev)) + sprintf(name, "pmem%d%s", nd_region->id, suffix); + else if (is_namespace_blk(&ndns->dev)) { + struct nd_namespace_blk *nsblk; + + nsblk = to_nd_namespace_blk(&ndns->dev); + sprintf(name, "ndblk%d.%d%s", nd_region->id, nsblk->id, suffix); + } else { + return NULL; + } + + return name; +} +EXPORT_SYMBOL(nvdimm_namespace_disk_name); + static ssize_t nstype_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/drivers/nvdimm/nd.h b/drivers/nvdimm/nd.h index d13eccbb67e9..1b937c235913 100644 --- a/drivers/nvdimm/nd.h +++ b/drivers/nvdimm/nd.h @@ -20,6 +20,12 @@ #include "label.h" enum { + /* + * Limits the maximum number of block apertures a dimm can + * support and is an input to the geometry/on-disk-format of a + * BTT instance + */ + ND_MAX_LANES = 256, SECTOR_SHIFT = 9, }; @@ -75,6 +81,11 @@ static inline struct nd_namespace_index *to_next_namespace_index( for (res = (ndd)->dpa.child, next = res ? res->sibling : NULL; \ res; res = next, next = next ? next->sibling : NULL) +struct nd_percpu_lane { + int count; + spinlock_t lock; +}; + struct nd_region { struct device dev; struct ida ns_ida; @@ -84,9 +95,10 @@ struct nd_region { u16 ndr_mappings; u64 ndr_size; u64 ndr_start; - int id; + int id, num_lanes; void *provider_data; struct nd_interleave_set *nd_set; + struct nd_percpu_lane __percpu *lane; struct nd_mapping mapping[0]; }; @@ -100,9 +112,11 @@ static inline unsigned nd_inc_seq(unsigned seq) return next[seq & 3]; } +struct btt; struct nd_btt { struct device dev; struct nd_namespace_common *ndns; + struct btt *btt; unsigned long lbasize; u8 *uuid; int id; @@ -157,6 +171,8 @@ static inline struct device *nd_btt_create(struct nd_region *nd_region) #endif struct nd_region *to_nd_region(struct device *dev); +unsigned int nd_region_acquire_lane(struct nd_region *nd_region); +void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane); int nd_region_to_nstype(struct nd_region *nd_region); int nd_region_register_namespaces(struct nd_region *nd_region, int *err); u64 nd_region_interleave_set_cookie(struct nd_region *nd_region); @@ -172,4 +188,8 @@ struct resource *nvdimm_allocate_dpa(struct nvdimm_drvdata *ndd, resource_size_t n); resource_size_t nvdimm_namespace_capacity(struct nd_namespace_common *ndns); struct nd_namespace_common *nvdimm_namespace_common_probe(struct device *dev); +int nvdimm_namespace_attach_btt(struct nd_namespace_common *ndns); +int nvdimm_namespace_detach_btt(struct nd_namespace_common *ndns); +const char *nvdimm_namespace_disk_name(struct nd_namespace_common *ndns, + char *name); #endif /* __ND_H__ */ diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c index d0c6b4bdba69..7346054bccbb 100644 --- a/drivers/nvdimm/pmem.c +++ b/drivers/nvdimm/pmem.c @@ -160,7 +160,6 @@ static void pmem_detach_disk(struct pmem_device *pmem) static int pmem_attach_disk(struct nd_namespace_common *ndns, struct pmem_device *pmem) { - struct nd_region *nd_region = to_nd_region(ndns->dev.parent); struct gendisk *disk; pmem->pmem_queue = blk_alloc_queue(GFP_KERNEL); @@ -183,7 +182,7 @@ static int pmem_attach_disk(struct nd_namespace_common *ndns, disk->private_data = pmem; disk->queue = pmem->pmem_queue; disk->flags = GENHD_FL_EXT_DEVT; - sprintf(disk->disk_name, "pmem%d", nd_region->id); + nvdimm_namespace_disk_name(ndns, disk->disk_name); disk->driverfs_dev = &ndns->dev; set_capacity(disk, pmem->size >> 9); pmem->pmem_disk = disk; @@ -211,17 +210,6 @@ static int pmem_rw_bytes(struct nd_namespace_common *ndns, return 0; } -static int nvdimm_namespace_attach_btt(struct nd_namespace_common *ndns) -{ - /* TODO */ - return -ENXIO; -} - -static void nvdimm_namespace_detach_btt(struct nd_namespace_common *ndns) -{ - /* TODO */ -} - static void pmem_free(struct pmem_device *pmem) { iounmap(pmem->virt_addr); diff --git a/drivers/nvdimm/region.c b/drivers/nvdimm/region.c index 2a5f3f53d79d..eb8aebcd4800 100644 --- a/drivers/nvdimm/region.c +++ b/drivers/nvdimm/region.c @@ -10,6 +10,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. */ +#include #include #include #include @@ -18,10 +19,21 @@ static int nd_region_probe(struct device *dev) { int err; + static unsigned long once; struct nd_region_namespaces *num_ns; struct nd_region *nd_region = to_nd_region(dev); int rc = nd_region_register_namespaces(nd_region, &err); + if (nd_region->num_lanes > num_online_cpus() + && nd_region->num_lanes < num_possible_cpus() + && !test_and_set_bit(0, &once)) { + dev_info(dev, "online cpus (%d) < concurrent i/o lanes (%d) < possible cpus (%d)\n", + num_online_cpus(), nd_region->num_lanes, + num_possible_cpus()); + dev_info(dev, "setting nr_cpus=%d may yield better libnvdimm device performance\n", + nd_region->num_lanes); + } + num_ns = devm_kzalloc(dev, sizeof(*num_ns), GFP_KERNEL); if (!num_ns) return -ENOMEM; diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index 4fd92389fa7e..fe8ec21fe3d7 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -32,6 +32,7 @@ static void nd_region_release(struct device *dev) put_device(&nvdimm->dev); } + free_percpu(nd_region->lane); ida_simple_remove(®ion_ida, nd_region->id); kfree(nd_region); } @@ -531,13 +532,66 @@ void *nd_region_provider_data(struct nd_region *nd_region) } EXPORT_SYMBOL_GPL(nd_region_provider_data); +/** + * nd_region_acquire_lane - allocate and lock a lane + * @nd_region: region id and number of lanes possible + * + * A lane correlates to a BLK-data-window and/or a log slot in the BTT. + * We optimize for the common case where there are 256 lanes, one + * per-cpu. For larger systems we need to lock to share lanes. For now + * this implementation assumes the cost of maintaining an allocator for + * free lanes is on the order of the lock hold time, so it implements a + * static lane = cpu % num_lanes mapping. + * + * In the case of a BTT instance on top of a BLK namespace a lane may be + * acquired recursively. We lock on the first instance. + * + * In the case of a BTT instance on top of PMEM, we only acquire a lane + * for the BTT metadata updates. + */ +unsigned int nd_region_acquire_lane(struct nd_region *nd_region) +{ + unsigned int cpu, lane; + + cpu = get_cpu(); + if (nd_region->num_lanes < nr_cpu_ids) { + struct nd_percpu_lane *ndl_lock, *ndl_count; + + lane = cpu % nd_region->num_lanes; + ndl_count = per_cpu_ptr(nd_region->lane, cpu); + ndl_lock = per_cpu_ptr(nd_region->lane, lane); + if (ndl_count->count++ == 0) + spin_lock(&ndl_lock->lock); + } else + lane = cpu; + + return lane; +} +EXPORT_SYMBOL(nd_region_acquire_lane); + +void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) +{ + if (nd_region->num_lanes < nr_cpu_ids) { + unsigned int cpu = get_cpu(); + struct nd_percpu_lane *ndl_lock, *ndl_count; + + ndl_count = per_cpu_ptr(nd_region->lane, cpu); + ndl_lock = per_cpu_ptr(nd_region->lane, lane); + if (--ndl_count->count == 0) + spin_unlock(&ndl_lock->lock); + put_cpu(); + } + put_cpu(); +} +EXPORT_SYMBOL(nd_region_release_lane); + static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, struct nd_region_desc *ndr_desc, struct device_type *dev_type, const char *caller) { struct nd_region *nd_region; struct device *dev; - u16 i; + unsigned int i; for (i = 0; i < ndr_desc->num_mappings; i++) { struct nd_mapping *nd_mapping = &ndr_desc->nd_mapping[i]; @@ -557,9 +611,19 @@ static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, if (!nd_region) return NULL; nd_region->id = ida_simple_get(®ion_ida, 0, 0, GFP_KERNEL); - if (nd_region->id < 0) { - kfree(nd_region); - return NULL; + if (nd_region->id < 0) + goto err_id; + + nd_region->lane = alloc_percpu(struct nd_percpu_lane); + if (!nd_region->lane) + goto err_percpu; + + for (i = 0; i < nr_cpu_ids; i++) { + struct nd_percpu_lane *ndl; + + ndl = per_cpu_ptr(nd_region->lane, i); + spin_lock_init(&ndl->lock); + ndl->count = 0; } memcpy(nd_region->mapping, ndr_desc->nd_mapping, @@ -573,6 +637,7 @@ static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, nd_region->ndr_mappings = ndr_desc->num_mappings; nd_region->provider_data = ndr_desc->provider_data; nd_region->nd_set = ndr_desc->nd_set; + nd_region->num_lanes = ndr_desc->num_lanes; ida_init(&nd_region->ns_ida); ida_init(&nd_region->btt_ida); dev = &nd_region->dev; @@ -585,11 +650,18 @@ static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, nd_device_register(dev); return nd_region; + + err_percpu: + ida_simple_remove(®ion_ida, nd_region->id); + err_id: + kfree(nd_region); + return NULL; } struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, struct nd_region_desc *ndr_desc) { + ndr_desc->num_lanes = ND_MAX_LANES; return nd_region_create(nvdimm_bus, ndr_desc, &nd_pmem_device_type, __func__); } @@ -600,6 +672,7 @@ struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, { if (ndr_desc->num_mappings > 1) return NULL; + ndr_desc->num_lanes = min(ndr_desc->num_lanes, ND_MAX_LANES); return nd_region_create(nvdimm_bus, ndr_desc, &nd_blk_device_type, __func__); } @@ -608,6 +681,7 @@ EXPORT_SYMBOL_GPL(nvdimm_blk_region_create); struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, struct nd_region_desc *ndr_desc) { + ndr_desc->num_lanes = ND_MAX_LANES; return nd_region_create(nvdimm_bus, ndr_desc, &nd_volatile_device_type, __func__); } diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h index a59dca17b3aa..531d99dfac68 100644 --- a/include/linux/libnvdimm.h +++ b/include/linux/libnvdimm.h @@ -85,6 +85,7 @@ struct nd_region_desc { const struct attribute_group **attr_groups; struct nd_interleave_set *nd_set; void *provider_data; + int num_lanes; }; struct nvdimm_bus; -- cgit v1.2.3 From bc30196f715ed3a94d050ef8bc465e567a6050be Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Thu, 25 Jun 2015 04:48:19 -0400 Subject: libnvdimm: Non-Volatile Devices Maintainer information and documentation for drivers/nvdimm Cc: Andy Lutomirski Cc: Boaz Harrosh Cc: H. Peter Anvin Cc: Jens Axboe Cc: Ingo Molnar Cc: Christoph Hellwig Cc: Neil Brown Cc: Greg KH Signed-off-by: Dan Williams --- Documentation/nvdimm/btt.txt | 24 +- Documentation/nvdimm/nvdimm.txt | 808 ++++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 39 +- 3 files changed, 858 insertions(+), 13 deletions(-) create mode 100644 Documentation/nvdimm/nvdimm.txt (limited to 'Documentation') diff --git a/Documentation/nvdimm/btt.txt b/Documentation/nvdimm/btt.txt index 95134d5ec4a0..b91443f577dc 100644 --- a/Documentation/nvdimm/btt.txt +++ b/Documentation/nvdimm/btt.txt @@ -80,9 +80,17 @@ block. Each map entry is 32 bits. The two most significant bits are special flags, and the remaining form the internal block number. Bit Description -31 : TRIM flag - marks if the block was trimmed or discarded -30 : ERROR flag - marks an error block. Cleared on write. -29 - 0 : Mappings to internal 'postmap' blocks +31 - 30 : Error and Zero flags - Used in the following way: + Bit Description + 31 30 + ----------------------------------------------------------------------- + 00 Initial state. Reads return zeroes; Premap = Postmap + 01 Zero state: Reads return zeroes + 10 Error state: Reads fail; Writes clear 'E' bit + 11 Normal Block – has valid postmap + + +29 - 0 : Mappings to internal 'postmap' blocks Some of the terminology that will be subsequently used: @@ -127,10 +135,11 @@ old_map': alternate old postmap entry new_map': alternate new postmap entry seq' : alternate sequence number. -Each of the above fields is 32-bit, making one entry 16 bytes. Flog updates are +Each of the above fields is 32-bit, making one entry 32 bytes. Entries are also +padded to 64 bytes to avoid cache line sharing or aliasing. Flog updates are done such that for any entry being written, it: a. overwrites the 'old' section in the entry based on sequence numbers -b. writes the new entry such that the sequence number is written last. +b. writes the 'new' section such that the sequence number is written last. c. The concept of lanes @@ -141,8 +150,9 @@ concurrently, 'nlanes' is the number of IOs the BTT device as a whole can process. nlanes = min(nfree, num_cpus) A lane number is obtained at the start of any IO, and is used for indexing into -all the on-disk and in-memory data structures for the duration of the IO. It is -protected by a spinlock. +all the on-disk and in-memory data structures for the duration of the IO. If +there are more CPUs than the max number of available lanes, than lanes are +protected by spinlocks. d. In-memory data structure: Read Tracking Table (RTT) diff --git a/Documentation/nvdimm/nvdimm.txt b/Documentation/nvdimm/nvdimm.txt new file mode 100644 index 000000000000..197a0b6b0582 --- /dev/null +++ b/Documentation/nvdimm/nvdimm.txt @@ -0,0 +1,808 @@ + LIBNVDIMM: Non-Volatile Devices + libnvdimm - kernel / libndctl - userspace helper library + linux-nvdimm@lists.01.org + v13 + + + Glossary + Overview + Supporting Documents + Git Trees + LIBNVDIMM PMEM and BLK + Why BLK? + PMEM vs BLK + BLK-REGIONs, PMEM-REGIONs, Atomic Sectors, and DAX + Example NVDIMM Platform + LIBNVDIMM Kernel Device Model and LIBNDCTL Userspace API + LIBNDCTL: Context + libndctl: instantiate a new library context example + LIBNVDIMM/LIBNDCTL: Bus + libnvdimm: control class device in /sys/class + libnvdimm: bus + libndctl: bus enumeration example + LIBNVDIMM/LIBNDCTL: DIMM (NMEM) + libnvdimm: DIMM (NMEM) + libndctl: DIMM enumeration example + LIBNVDIMM/LIBNDCTL: Region + libnvdimm: region + libndctl: region enumeration example + Why Not Encode the Region Type into the Region Name? + How Do I Determine the Major Type of a Region? + LIBNVDIMM/LIBNDCTL: Namespace + libnvdimm: namespace + libndctl: namespace enumeration example + libndctl: namespace creation example + Why the Term "namespace"? + LIBNVDIMM/LIBNDCTL: Block Translation Table "btt" + libnvdimm: btt layout + libndctl: btt creation example + Summary LIBNDCTL Diagram + + +Glossary +-------- + +PMEM: A system-physical-address range where writes are persistent. A +block device composed of PMEM is capable of DAX. A PMEM address range +may span an interleave of several DIMMs. + +BLK: A set of one or more programmable memory mapped apertures provided +by a DIMM to access its media. This indirection precludes the +performance benefit of interleaving, but enables DIMM-bounded failure +modes. + +DPA: DIMM Physical Address, is a DIMM-relative offset. With one DIMM in +the system there would be a 1:1 system-physical-address:DPA association. +Once more DIMMs are added a memory controller interleave must be +decoded to determine the DPA associated with a given +system-physical-address. BLK capacity always has a 1:1 relationship +with a single-DIMM's DPA range. + +DAX: File system extensions to bypass the page cache and block layer to +mmap persistent memory, from a PMEM block device, directly into a +process address space. + +BTT: Block Translation Table: Persistent memory is byte addressable. +Existing software may have an expectation that the power-fail-atomicity +of writes is at least one sector, 512 bytes. The BTT is an indirection +table with atomic update semantics to front a PMEM/BLK block device +driver and present arbitrary atomic sector sizes. + +LABEL: Metadata stored on a DIMM device that partitions and identifies +(persistently names) storage between PMEM and BLK. It also partitions +BLK storage to host BTTs with different parameters per BLK-partition. +Note that traditional partition tables, GPT/MBR, are layered on top of a +BLK or PMEM device. + + +Overview +-------- + +The LIBNVDIMM subsystem provides support for three types of NVDIMMs, namely, +PMEM, BLK, and NVDIMM devices that can simultaneously support both PMEM +and BLK mode access. These three modes of operation are described by +the "NVDIMM Firmware Interface Table" (NFIT) in ACPI 6. While the LIBNVDIMM +implementation is generic and supports pre-NFIT platforms, it was guided +by the superset of capabilities need to support this ACPI 6 definition +for NVDIMM resources. The bulk of the kernel implementation is in place +to handle the case where DPA accessible via PMEM is aliased with DPA +accessible via BLK. When that occurs a LABEL is needed to reserve DPA +for exclusive access via one mode a time. + +Supporting Documents +ACPI 6: http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf +NVDIMM Namespace: http://pmem.io/documents/NVDIMM_Namespace_Spec.pdf +DSM Interface Example: http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf +Driver Writer's Guide: http://pmem.io/documents/NVDIMM_Driver_Writers_Guide.pdf + +Git Trees +LIBNVDIMM: https://git.kernel.org/cgit/linux/kernel/git/djbw/nvdimm.git +LIBNDCTL: https://github.com/pmem/ndctl.git +PMEM: https://github.com/01org/prd + + +LIBNVDIMM PMEM and BLK +------------------ + +Prior to the arrival of the NFIT, non-volatile memory was described to a +system in various ad-hoc ways. Usually only the bare minimum was +provided, namely, a single system-physical-address range where writes +are expected to be durable after a system power loss. Now, the NFIT +specification standardizes not only the description of PMEM, but also +BLK and platform message-passing entry points for control and +configuration. + +For each NVDIMM access method (PMEM, BLK), LIBNVDIMM provides a block +device driver: + + 1. PMEM (nd_pmem.ko): Drives a system-physical-address range. This + range is contiguous in system memory and may be interleaved (hardware + memory controller striped) across multiple DIMMs. When interleaved the + platform may optionally provide details of which DIMMs are participating + in the interleave. + + Note that while LIBNVDIMM describes system-physical-address ranges that may + alias with BLK access as ND_NAMESPACE_PMEM ranges and those without + alias as ND_NAMESPACE_IO ranges, to the nd_pmem driver there is no + distinction. The different device-types are an implementation detail + that userspace can exploit to implement policies like "only interface + with address ranges from certain DIMMs". It is worth noting that when + aliasing is present and a DIMM lacks a label, then no block device can + be created by default as userspace needs to do at least one allocation + of DPA to the PMEM range. In contrast ND_NAMESPACE_IO ranges, once + registered, can be immediately attached to nd_pmem. + + 2. BLK (nd_blk.ko): This driver performs I/O using a set of platform + defined apertures. A set of apertures will all access just one DIMM. + Multiple windows allow multiple concurrent accesses, much like + tagged-command-queuing, and would likely be used by different threads or + different CPUs. + + The NFIT specification defines a standard format for a BLK-aperture, but + the spec also allows for vendor specific layouts, and non-NFIT BLK + implementations may other designs for BLK I/O. For this reason "nd_blk" + calls back into platform-specific code to perform the I/O. One such + implementation is defined in the "Driver Writer's Guide" and "DSM + Interface Example". + + +Why BLK? +-------- + +While PMEM provides direct byte-addressable CPU-load/store access to +NVDIMM storage, it does not provide the best system RAS (recovery, +availability, and serviceability) model. An access to a corrupted +system-physical-address address causes a cpu exception while an access +to a corrupted address through an BLK-aperture causes that block window +to raise an error status in a register. The latter is more aligned with +the standard error model that host-bus-adapter attached disks present. +Also, if an administrator ever wants to replace a memory it is easier to +service a system at DIMM module boundaries. Compare this to PMEM where +data could be interleaved in an opaque hardware specific manner across +several DIMMs. + +PMEM vs BLK +BLK-apertures solve this RAS problem, but their presence is also the +major contributing factor to the complexity of the ND subsystem. They +complicate the implementation because PMEM and BLK alias in DPA space. +Any given DIMM's DPA-range may contribute to one or more +system-physical-address sets of interleaved DIMMs, *and* may also be +accessed in its entirety through its BLK-aperture. Accessing a DPA +through a system-physical-address while simultaneously accessing the +same DPA through a BLK-aperture has undefined results. For this reason, +DIMMs with this dual interface configuration include a DSM function to +store/retrieve a LABEL. The LABEL effectively partitions the DPA-space +into exclusive system-physical-address and BLK-aperture accessible +regions. For simplicity a DIMM is allowed a PMEM "region" per each +interleave set in which it is a member. The remaining DPA space can be +carved into an arbitrary number of BLK devices with discontiguous +extents. + +BLK-REGIONs, PMEM-REGIONs, Atomic Sectors, and DAX +-------------------------------------------------- + +One of the few +reasons to allow multiple BLK namespaces per REGION is so that each +BLK-namespace can be configured with a BTT with unique atomic sector +sizes. While a PMEM device can host a BTT the LABEL specification does +not provide for a sector size to be specified for a PMEM namespace. +This is due to the expectation that the primary usage model for PMEM is +via DAX, and the BTT is incompatible with DAX. However, for the cases +where an application or filesystem still needs atomic sector update +guarantees it can register a BTT on a PMEM device or partition. See +LIBNVDIMM/NDCTL: Block Translation Table "btt" + + +Example NVDIMM Platform +----------------------- + +For the remainder of this document the following diagram will be +referenced for any example sysfs layouts. + + + (a) (b) DIMM BLK-REGION + +-------------------+--------+--------+--------+ ++------+ | pm0.0 | blk2.0 | pm1.0 | blk2.1 | 0 region2 +| imc0 +--+- - - region0- - - +--------+ +--------+ ++--+---+ | pm0.0 | blk3.0 | pm1.0 | blk3.1 | 1 region3 + | +-------------------+--------v v--------+ ++--+---+ | | +| cpu0 | region1 ++--+---+ | | + | +----------------------------^ ^--------+ ++--+---+ | blk4.0 | pm1.0 | blk4.0 | 2 region4 +| imc1 +--+----------------------------| +--------+ ++------+ | blk5.0 | pm1.0 | blk5.0 | 3 region5 + +----------------------------+--------+--------+ + +In this platform we have four DIMMs and two memory controllers in one +socket. Each unique interface (BLK or PMEM) to DPA space is identified +by a region device with a dynamically assigned id (REGION0 - REGION5). + + 1. The first portion of DIMM0 and DIMM1 are interleaved as REGION0. A + single PMEM namespace is created in the REGION0-SPA-range that spans + DIMM0 and DIMM1 with a user-specified name of "pm0.0". Some of that + interleaved system-physical-address range is reclaimed as BLK-aperture + accessed space starting at DPA-offset (a) into each DIMM. In that + reclaimed space we create two BLK-aperture "namespaces" from REGION2 and + REGION3 where "blk2.0" and "blk3.0" are just human readable names that + could be set to any user-desired name in the LABEL. + + 2. In the last portion of DIMM0 and DIMM1 we have an interleaved + system-physical-address range, REGION1, that spans those two DIMMs as + well as DIMM2 and DIMM3. Some of REGION1 allocated to a PMEM namespace + named "pm1.0" the rest is reclaimed in 4 BLK-aperture namespaces (for + each DIMM in the interleave set), "blk2.1", "blk3.1", "blk4.0", and + "blk5.0". + + 3. The portion of DIMM2 and DIMM3 that do not participate in the REGION1 + interleaved system-physical-address range (i.e. the DPA address below + offset (b) are also included in the "blk4.0" and "blk5.0" namespaces. + Note, that this example shows that BLK-aperture namespaces don't need to + be contiguous in DPA-space. + + This bus is provided by the kernel under the device + /sys/devices/platform/nfit_test.0 when CONFIG_NFIT_TEST is enabled and + the nfit_test.ko module is loaded. This not only test LIBNVDIMM but the + acpi_nfit.ko driver as well. + + +LIBNVDIMM Kernel Device Model and LIBNDCTL Userspace API +---------------------------------------------------- + +What follows is a description of the LIBNVDIMM sysfs layout and a +corresponding object hierarchy diagram as viewed through the LIBNDCTL +api. The example sysfs paths and diagrams are relative to the Example +NVDIMM Platform which is also the LIBNVDIMM bus used in the LIBNDCTL unit +test. + +LIBNDCTL: Context +Every api call in the LIBNDCTL library requires a context that holds the +logging parameters and other library instance state. The library is +based on the libabc template: +https://git.kernel.org/cgit/linux/kernel/git/kay/libabc.git/ + +LIBNDCTL: instantiate a new library context example + + struct ndctl_ctx *ctx; + + if (ndctl_new(&ctx) == 0) + return ctx; + else + return NULL; + +LIBNVDIMM/LIBNDCTL: Bus +------------------- + +A bus has a 1:1 relationship with an NFIT. The current expectation for +ACPI based systems is that there is only ever one platform-global NFIT. +That said, it is trivial to register multiple NFITs, the specification +does not preclude it. The infrastructure supports multiple busses and +we we use this capability to test multiple NFIT configurations in the +unit test. + +LIBNVDIMM: control class device in /sys/class + +This character device accepts DSM messages to be passed to DIMM +identified by its NFIT handle. + + /sys/class/nd/ndctl0 + |-- dev + |-- device -> ../../../ndbus0 + |-- subsystem -> ../../../../../../../class/nd + + + +LIBNVDIMM: bus + + struct nvdimm_bus *nvdimm_bus_register(struct device *parent, + struct nvdimm_bus_descriptor *nfit_desc); + + /sys/devices/platform/nfit_test.0/ndbus0 + |-- commands + |-- nd + |-- nfit + |-- nmem0 + |-- nmem1 + |-- nmem2 + |-- nmem3 + |-- power + |-- provider + |-- region0 + |-- region1 + |-- region2 + |-- region3 + |-- region4 + |-- region5 + |-- uevent + `-- wait_probe + +LIBNDCTL: bus enumeration example +Find the bus handle that describes the bus from Example NVDIMM Platform + + static struct ndctl_bus *get_bus_by_provider(struct ndctl_ctx *ctx, + const char *provider) + { + struct ndctl_bus *bus; + + ndctl_bus_foreach(ctx, bus) + if (strcmp(provider, ndctl_bus_get_provider(bus)) == 0) + return bus; + + return NULL; + } + + bus = get_bus_by_provider(ctx, "nfit_test.0"); + + +LIBNVDIMM/LIBNDCTL: DIMM (NMEM) +--------------------------- + +The DIMM device provides a character device for sending commands to +hardware, and it is a container for LABELs. If the DIMM is defined by +NFIT then an optional 'nfit' attribute sub-directory is available to add +NFIT-specifics. + +Note that the kernel device name for "DIMMs" is "nmemX". The NFIT +describes these devices via "Memory Device to System Physical Address +Range Mapping Structure", and there is no requirement that they actually +be physical DIMMs, so we use a more generic name. + +LIBNVDIMM: DIMM (NMEM) + + struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus, void *provider_data, + const struct attribute_group **groups, unsigned long flags, + unsigned long *dsm_mask); + + /sys/devices/platform/nfit_test.0/ndbus0 + |-- nmem0 + | |-- available_slots + | |-- commands + | |-- dev + | |-- devtype + | |-- driver -> ../../../../../bus/nd/drivers/nvdimm + | |-- modalias + | |-- nfit + | | |-- device + | | |-- format + | | |-- handle + | | |-- phys_id + | | |-- rev_id + | | |-- serial + | | `-- vendor + | |-- state + | |-- subsystem -> ../../../../../bus/nd + | `-- uevent + |-- nmem1 + [..] + + +LIBNDCTL: DIMM enumeration example + +Note, in this example we are assuming NFIT-defined DIMMs which are +identified by an "nfit_handle" a 32-bit value where: +Bit 3:0 DIMM number within the memory channel +Bit 7:4 memory channel number +Bit 11:8 memory controller ID +Bit 15:12 socket ID (within scope of a Node controller if node controller is present) +Bit 27:16 Node Controller ID +Bit 31:28 Reserved + + static struct ndctl_dimm *get_dimm_by_handle(struct ndctl_bus *bus, + unsigned int handle) + { + struct ndctl_dimm *dimm; + + ndctl_dimm_foreach(bus, dimm) + if (ndctl_dimm_get_handle(dimm) == handle) + return dimm; + + return NULL; + } + + #define DIMM_HANDLE(n, s, i, c, d) \ + (((n & 0xfff) << 16) | ((s & 0xf) << 12) | ((i & 0xf) << 8) \ + | ((c & 0xf) << 4) | (d & 0xf)) + + dimm = get_dimm_by_handle(bus, DIMM_HANDLE(0, 0, 0, 0, 0)); + +LIBNVDIMM/LIBNDCTL: Region +---------------------- + +A generic REGION device is registered for each PMEM range orBLK-aperture +set. Per the example there are 6 regions: 2 PMEM and 4 BLK-aperture +sets on the "nfit_test.0" bus. The primary role of regions are to be a +container of "mappings". A mapping is a tuple of . + +LIBNVDIMM provides a built-in driver for these REGION devices. This driver +is responsible for reconciling the aliased DPA mappings across all +regions, parsing the LABEL, if present, and then emitting NAMESPACE +devices with the resolved/exclusive DPA-boundaries for the nd_pmem or +nd_blk device driver to consume. + +In addition to the generic attributes of "mapping"s, "interleave_ways" +and "size" the REGION device also exports some convenience attributes. +"nstype" indicates the integer type of namespace-device this region +emits, "devtype" duplicates the DEVTYPE variable stored by udev at the +'add' event, "modalias" duplicates the MODALIAS variable stored by udev +at the 'add' event, and finally, the optional "spa_index" is provided in +the case where the region is defined by a SPA. + +LIBNVDIMM: region + + struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, + struct nd_region_desc *ndr_desc); + struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, + struct nd_region_desc *ndr_desc); + + /sys/devices/platform/nfit_test.0/ndbus0 + |-- region0 + | |-- available_size + | |-- btt0 + | |-- btt_seed + | |-- devtype + | |-- driver -> ../../../../../bus/nd/drivers/nd_region + | |-- init_namespaces + | |-- mapping0 + | |-- mapping1 + | |-- mappings + | |-- modalias + | |-- namespace0.0 + | |-- namespace_seed + | |-- numa_node + | |-- nfit + | | `-- spa_index + | |-- nstype + | |-- set_cookie + | |-- size + | |-- subsystem -> ../../../../../bus/nd + | `-- uevent + |-- region1 + [..] + +LIBNDCTL: region enumeration example + +Sample region retrieval routines based on NFIT-unique data like +"spa_index" (interleave set id) for PMEM and "nfit_handle" (dimm id) for +BLK. + + static struct ndctl_region *get_pmem_region_by_spa_index(struct ndctl_bus *bus, + unsigned int spa_index) + { + struct ndctl_region *region; + + ndctl_region_foreach(bus, region) { + if (ndctl_region_get_type(region) != ND_DEVICE_REGION_PMEM) + continue; + if (ndctl_region_get_spa_index(region) == spa_index) + return region; + } + return NULL; + } + + static struct ndctl_region *get_blk_region_by_dimm_handle(struct ndctl_bus *bus, + unsigned int handle) + { + struct ndctl_region *region; + + ndctl_region_foreach(bus, region) { + struct ndctl_mapping *map; + + if (ndctl_region_get_type(region) != ND_DEVICE_REGION_BLOCK) + continue; + ndctl_mapping_foreach(region, map) { + struct ndctl_dimm *dimm = ndctl_mapping_get_dimm(map); + + if (ndctl_dimm_get_handle(dimm) == handle) + return region; + } + } + return NULL; + } + + +Why Not Encode the Region Type into the Region Name? +---------------------------------------------------- + +At first glance it seems since NFIT defines just PMEM and BLK interface +types that we should simply name REGION devices with something derived +from those type names. However, the ND subsystem explicitly keeps the +REGION name generic and expects userspace to always consider the +region-attributes for 4 reasons: + + 1. There are already more than two REGION and "namespace" types. For + PMEM there are two subtypes. As mentioned previously we have PMEM where + the constituent DIMM devices are known and anonymous PMEM. For BLK + regions the NFIT specification already anticipates vendor specific + implementations. The exact distinction of what a region contains is in + the region-attributes not the region-name or the region-devtype. + + 2. A region with zero child-namespaces is a possible configuration. For + example, the NFIT allows for a DCR to be published without a + corresponding BLK-aperture. This equates to a DIMM that can only accept + control/configuration messages, but no i/o through a descendant block + device. Again, this "type" is advertised in the attributes ('mappings' + == 0) and the name does not tell you much. + + 3. What if a third major interface type arises in the future? Outside + of vendor specific implementations, it's not difficult to envision a + third class of interface type beyond BLK and PMEM. With a generic name + for the REGION level of the device-hierarchy old userspace + implementations can still make sense of new kernel advertised + region-types. Userspace can always rely on the generic region + attributes like "mappings", "size", etc and the expected child devices + named "namespace". This generic format of the device-model hierarchy + allows the LIBNVDIMM and LIBNDCTL implementations to be more uniform and + future-proof. + + 4. There are more robust mechanisms for determining the major type of a + region than a device name. See the next section, How Do I Determine the + Major Type of a Region? + +How Do I Determine the Major Type of a Region? +---------------------------------------------- + +Outside of the blanket recommendation of "use libndctl", or simply +looking at the kernel header (/usr/include/linux/ndctl.h) to decode the +"nstype" integer attribute, here are some other options. + + 1. module alias lookup: + + The whole point of region/namespace device type differentiation is to + decide which block-device driver will attach to a given LIBNVDIMM namespace. + One can simply use the modalias to lookup the resulting module. It's + important to note that this method is robust in the presence of a + vendor-specific driver down the road. If a vendor-specific + implementation wants to supplant the standard nd_blk driver it can with + minimal impact to the rest of LIBNVDIMM. + + In fact, a vendor may also want to have a vendor-specific region-driver + (outside of nd_region). For example, if a vendor defined its own LABEL + format it would need its own region driver to parse that LABEL and emit + the resulting namespaces. The output from module resolution is more + accurate than a region-name or region-devtype. + + 2. udev: + + The kernel "devtype" is registered in the udev database + # udevadm info --path=/devices/platform/nfit_test.0/ndbus0/region0 + P: /devices/platform/nfit_test.0/ndbus0/region0 + E: DEVPATH=/devices/platform/nfit_test.0/ndbus0/region0 + E: DEVTYPE=nd_pmem + E: MODALIAS=nd:t2 + E: SUBSYSTEM=nd + + # udevadm info --path=/devices/platform/nfit_test.0/ndbus0/region4 + P: /devices/platform/nfit_test.0/ndbus0/region4 + E: DEVPATH=/devices/platform/nfit_test.0/ndbus0/region4 + E: DEVTYPE=nd_blk + E: MODALIAS=nd:t3 + E: SUBSYSTEM=nd + + ...and is available as a region attribute, but keep in mind that the + "devtype" does not indicate sub-type variations and scripts should + really be understanding the other attributes. + + 3. type specific attributes: + + As it currently stands a BLK-aperture region will never have a + "nfit/spa_index" attribute, but neither will a non-NFIT PMEM region. A + BLK region with a "mappings" value of 0 is, as mentioned above, a DIMM + that does not allow I/O. A PMEM region with a "mappings" value of zero + is a simple system-physical-address range. + + +LIBNVDIMM/LIBNDCTL: Namespace +------------------------- + +A REGION, after resolving DPA aliasing and LABEL specified boundaries, +surfaces one or more "namespace" devices. The arrival of a "namespace" +device currently triggers either the nd_blk or nd_pmem driver to load +and register a disk/block device. + +LIBNVDIMM: namespace +Here is a sample layout from the three major types of NAMESPACE where +namespace0.0 represents DIMM-info-backed PMEM (note that it has a 'uuid' +attribute), namespace2.0 represents a BLK namespace (note it has a +'sector_size' attribute) that, and namespace6.0 represents an anonymous +PMEM namespace (note that has no 'uuid' attribute due to not support a +LABEL). + + /sys/devices/platform/nfit_test.0/ndbus0/region0/namespace0.0 + |-- alt_name + |-- devtype + |-- dpa_extents + |-- force_raw + |-- modalias + |-- numa_node + |-- resource + |-- size + |-- subsystem -> ../../../../../../bus/nd + |-- type + |-- uevent + `-- uuid + /sys/devices/platform/nfit_test.0/ndbus0/region2/namespace2.0 + |-- alt_name + |-- devtype + |-- dpa_extents + |-- force_raw + |-- modalias + |-- numa_node + |-- sector_size + |-- size + |-- subsystem -> ../../../../../../bus/nd + |-- type + |-- uevent + `-- uuid + /sys/devices/platform/nfit_test.1/ndbus1/region6/namespace6.0 + |-- block + | `-- pmem0 + |-- devtype + |-- driver -> ../../../../../../bus/nd/drivers/pmem + |-- force_raw + |-- modalias + |-- numa_node + |-- resource + |-- size + |-- subsystem -> ../../../../../../bus/nd + |-- type + `-- uevent + +LIBNDCTL: namespace enumeration example +Namespaces are indexed relative to their parent region, example below. +These indexes are mostly static from boot to boot, but subsystem makes +no guarantees in this regard. For a static namespace identifier use its +'uuid' attribute. + +static struct ndctl_namespace *get_namespace_by_id(struct ndctl_region *region, + unsigned int id) +{ + struct ndctl_namespace *ndns; + + ndctl_namespace_foreach(region, ndns) + if (ndctl_namespace_get_id(ndns) == id) + return ndns; + + return NULL; +} + +LIBNDCTL: namespace creation example +Idle namespaces are automatically created by the kernel if a given +region has enough available capacity to create a new namespace. +Namespace instantiation involves finding an idle namespace and +configuring it. For the most part the setting of namespace attributes +can occur in any order, the only constraint is that 'uuid' must be set +before 'size'. This enables the kernel to track DPA allocations +internally with a static identifier. + +static int configure_namespace(struct ndctl_region *region, + struct ndctl_namespace *ndns, + struct namespace_parameters *parameters) +{ + char devname[50]; + + snprintf(devname, sizeof(devname), "namespace%d.%d", + ndctl_region_get_id(region), paramaters->id); + + ndctl_namespace_set_alt_name(ndns, devname); + /* 'uuid' must be set prior to setting size! */ + ndctl_namespace_set_uuid(ndns, paramaters->uuid); + ndctl_namespace_set_size(ndns, paramaters->size); + /* unlike pmem namespaces, blk namespaces have a sector size */ + if (parameters->lbasize) + ndctl_namespace_set_sector_size(ndns, parameters->lbasize); + ndctl_namespace_enable(ndns); +} + + +Why the Term "namespace"? + + 1. Why not "volume" for instance? "volume" ran the risk of confusing ND + as a volume manager like device-mapper. + + 2. The term originated to describe the sub-devices that can be created + within a NVME controller (see the nvme specification: + http://www.nvmexpress.org/specifications/), and NFIT namespaces are + meant to parallel the capabilities and configurability of + NVME-namespaces. + + +LIBNVDIMM/LIBNDCTL: Block Translation Table "btt" +--------------------------------------------- + +A BTT (design document: http://pmem.io/2014/09/23/btt.html) is a stacked +block device driver that fronts either the whole block device or a +partition of a block device emitted by either a PMEM or BLK NAMESPACE. + +LIBNVDIMM: btt layout +Every region will start out with at least one BTT device which is the +seed device. To activate it set the "namespace", "uuid", and +"sector_size" attributes and then bind the device to the nd_pmem or +nd_blk driver depending on the region type. + + /sys/devices/platform/nfit_test.1/ndbus0/region0/btt0/ + |-- namespace + |-- delete + |-- devtype + |-- modalias + |-- numa_node + |-- sector_size + |-- subsystem -> ../../../../../bus/nd + |-- uevent + `-- uuid + +LIBNDCTL: btt creation example +Similar to namespaces an idle BTT device is automatically created per +region. Each time this "seed" btt device is configured and enabled a new +seed is created. Creating a BTT configuration involves two steps of +finding and idle BTT and assigning it to consume a PMEM or BLK namespace. + + static struct ndctl_btt *get_idle_btt(struct ndctl_region *region) + { + struct ndctl_btt *btt; + + ndctl_btt_foreach(region, btt) + if (!ndctl_btt_is_enabled(btt) + && !ndctl_btt_is_configured(btt)) + return btt; + + return NULL; + } + + static int configure_btt(struct ndctl_region *region, + struct btt_parameters *parameters) + { + btt = get_idle_btt(region); + + ndctl_btt_set_uuid(btt, parameters->uuid); + ndctl_btt_set_sector_size(btt, parameters->sector_size); + ndctl_btt_set_namespace(btt, parameters->ndns); + /* turn off raw mode device */ + ndctl_namespace_disable(parameters->ndns); + /* turn on btt access */ + ndctl_btt_enable(btt); + } + +Once instantiated a new inactive btt seed device will appear underneath +the region. + +Once a "namespace" is removed from a BTT that instance of the BTT device +will be deleted or otherwise reset to default values. This deletion is +only at the device model level. In order to destroy a BTT the "info +block" needs to be destroyed. Note, that to destroy a BTT the media +needs to be written in raw mode. By default, the kernel will autodetect +the presence of a BTT and disable raw mode. This autodetect behavior +can be suppressed by enabling raw mode for the namespace via the +ndctl_namespace_set_raw_mode() api. + + +Summary LIBNDCTL Diagram +------------------------ + +For the given example above, here is the view of the objects as seen by the LIBNDCTL api: + +---+ + |CTX| +---------+ +--------------+ +---------------+ + +-+-+ +-> REGION0 +---> NAMESPACE0.0 +--> PMEM8 "pm0.0" | + | | +---------+ +--------------+ +---------------+ ++-------+ | | +---------+ +--------------+ +---------------+ +| DIMM0 <-+ | +-> REGION1 +---> NAMESPACE1.0 +--> PMEM6 "pm1.0" | ++-------+ | | | +---------+ +--------------+ +---------------+ +| DIMM1 <-+ +-v--+ | +---------+ +--------------+ +---------------+ ++-------+ +-+BUS0+---> REGION2 +-+-> NAMESPACE2.0 +--> ND6 "blk2.0" | +| DIMM2 <-+ +----+ | +---------+ | +--------------+ +----------------------+ ++-------+ | | +-> NAMESPACE2.1 +--> ND5 "blk2.1" | BTT2 | +| DIMM3 <-+ | +--------------+ +----------------------+ ++-------+ | +---------+ +--------------+ +---------------+ + +-> REGION3 +-+-> NAMESPACE3.0 +--> ND4 "blk3.0" | + | +---------+ | +--------------+ +----------------------+ + | +-> NAMESPACE3.1 +--> ND3 "blk3.1" | BTT1 | + | +--------------+ +----------------------+ + | +---------+ +--------------+ +---------------+ + +-> REGION4 +---> NAMESPACE4.0 +--> ND2 "blk4.0" | + | +---------+ +--------------+ +---------------+ + | +---------+ +--------------+ +----------------------+ + +-> REGION5 +---> NAMESPACE5.0 +--> ND1 "blk5.0" | BTT0 | + +---------+ +--------------+ +---------------+------+ + + diff --git a/MAINTAINERS b/MAINTAINERS index 590304b96b03..c2f55aed811d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5912,6 +5912,39 @@ M: Sasha Levin S: Maintained F: tools/lib/lockdep/ +LIBNVDIMM: NON-VOLATILE MEMORY DEVICE SUBSYSTEM +M: Dan Williams +L: linux-nvdimm@lists.01.org +Q: https://patchwork.kernel.org/project/linux-nvdimm/list/ +S: Supported +F: drivers/nvdimm/* +F: include/linux/nd.h +F: include/linux/libnvdimm.h +F: include/uapi/linux/ndctl.h + +LIBNVDIMM BLK: MMIO-APERTURE DRIVER +M: Ross Zwisler +L: linux-nvdimm@lists.01.org +Q: https://patchwork.kernel.org/project/linux-nvdimm/list/ +S: Supported +F: drivers/nvdimm/blk.c +F: drivers/nvdimm/region_devs.c +F: drivers/acpi/nfit* + +LIBNVDIMM BTT: BLOCK TRANSLATION TABLE +M: Vishal Verma +L: linux-nvdimm@lists.01.org +Q: https://patchwork.kernel.org/project/linux-nvdimm/list/ +S: Supported +F: drivers/nvdimm/btt* + +LIBNVDIMM PMEM: PERSISTENT MEMORY DRIVER +M: Ross Zwisler +L: linux-nvdimm@lists.01.org +Q: https://patchwork.kernel.org/project/linux-nvdimm/list/ +S: Supported +F: drivers/nvdimm/pmem.c + LINUX FOR IBM pSERIES (RS/6000) M: Paul Mackerras W: http://www.ibm.com/linux/ltc/projects/ppc @@ -8136,12 +8169,6 @@ S: Maintained F: Documentation/blockdev/ramdisk.txt F: drivers/block/brd.c -PERSISTENT MEMORY DRIVER -M: Ross Zwisler -L: linux-nvdimm@lists.01.org -S: Supported -F: drivers/block/pmem.c - RANDOM NUMBER DRIVER M: "Theodore Ts'o" S: Maintained -- cgit v1.2.3 From ef90174f821041313d42d99c1c8b35a3af64a910 Mon Sep 17 00:00:00 2001 From: Jean-Baptiste Theou Date: Tue, 9 Jun 2015 09:55:02 -0700 Subject: watchdog: watchdog_core: Add watchdog registration deferral mechanism Currently, watchdog subsystem require the misc subsystem to register a watchdog. This may not be the case in case of an early registration of a watchdog, which can be required when the watchdog cannot be disabled. This patch introduces a deferral mechanism to remove this requirement. Signed-off-by: Jean-Baptiste Theou Reviewed-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/watchdog/watchdog-kernel-api.txt | 7 ++ drivers/watchdog/watchdog_core.c | 118 +++++++++++++++++++++---- include/linux/watchdog.h | 3 + 3 files changed, 110 insertions(+), 18 deletions(-) (limited to 'Documentation') diff --git a/Documentation/watchdog/watchdog-kernel-api.txt b/Documentation/watchdog/watchdog-kernel-api.txt index a0438f3957ca..d8b0d3367706 100644 --- a/Documentation/watchdog/watchdog-kernel-api.txt +++ b/Documentation/watchdog/watchdog-kernel-api.txt @@ -36,6 +36,10 @@ The watchdog_unregister_device routine deregisters a registered watchdog timer device. The parameter of this routine is the pointer to the registered watchdog_device structure. +The watchdog subsystem includes an registration deferral mechanism, +which allows you to register an watchdog as early as you wish during +the boot process. + The watchdog device structure looks like this: struct watchdog_device { @@ -52,6 +56,7 @@ struct watchdog_device { void *driver_data; struct mutex lock; unsigned long status; + struct list_head deferred; }; It contains following fields: @@ -80,6 +85,8 @@ It contains following fields: information about the status of the device (Like: is the watchdog timer running/active, is the nowayout bit set, is the device opened via the /dev/watchdog interface or not, ...). +* deferred: entry in wtd_deferred_reg_list which is used to + register early initialized watchdogs. The list of watchdog operations is defined as: diff --git a/drivers/watchdog/watchdog_core.c b/drivers/watchdog/watchdog_core.c index cec9b559647d..1a8059455413 100644 --- a/drivers/watchdog/watchdog_core.c +++ b/drivers/watchdog/watchdog_core.c @@ -43,6 +43,45 @@ static DEFINE_IDA(watchdog_ida); static struct class *watchdog_class; +/* + * Deferred Registration infrastructure. + * + * Sometimes watchdog drivers needs to be loaded as soon as possible, + * for example when it's impossible to disable it. To do so, + * raising the initcall level of the watchdog driver is a solution. + * But in such case, the miscdev is maybe not ready (subsys_initcall), and + * watchdog_core need miscdev to register the watchdog as a char device. + * + * The deferred registration infrastructure offer a way for the watchdog + * subsystem to register a watchdog properly, even before miscdev is ready. + */ + +static DEFINE_MUTEX(wtd_deferred_reg_mutex); +static LIST_HEAD(wtd_deferred_reg_list); +static bool wtd_deferred_reg_done; + +static int watchdog_deferred_registration_add(struct watchdog_device *wdd) +{ + list_add_tail(&wdd->deferred, + &wtd_deferred_reg_list); + return 0; +} + +static void watchdog_deferred_registration_del(struct watchdog_device *wdd) +{ + struct list_head *p, *n; + struct watchdog_device *wdd_tmp; + + list_for_each_safe(p, n, &wtd_deferred_reg_list) { + wdd_tmp = list_entry(p, struct watchdog_device, + deferred); + if (wdd_tmp == wdd) { + list_del(&wdd_tmp->deferred); + break; + } + } +} + static void watchdog_check_min_max_timeout(struct watchdog_device *wdd) { /* @@ -98,17 +137,7 @@ int watchdog_init_timeout(struct watchdog_device *wdd, } EXPORT_SYMBOL_GPL(watchdog_init_timeout); -/** - * watchdog_register_device() - register a watchdog device - * @wdd: watchdog device - * - * Register a watchdog device with the kernel so that the - * watchdog timer can be accessed from userspace. - * - * A zero is returned on success and a negative errno code for - * failure. - */ -int watchdog_register_device(struct watchdog_device *wdd) +static int __watchdog_register_device(struct watchdog_device *wdd) { int ret, id, devno; @@ -164,16 +193,33 @@ int watchdog_register_device(struct watchdog_device *wdd) return 0; } -EXPORT_SYMBOL_GPL(watchdog_register_device); /** - * watchdog_unregister_device() - unregister a watchdog device - * @wdd: watchdog device to unregister + * watchdog_register_device() - register a watchdog device + * @wdd: watchdog device * - * Unregister a watchdog device that was previously successfully - * registered with watchdog_register_device(). + * Register a watchdog device with the kernel so that the + * watchdog timer can be accessed from userspace. + * + * A zero is returned on success and a negative errno code for + * failure. */ -void watchdog_unregister_device(struct watchdog_device *wdd) + +int watchdog_register_device(struct watchdog_device *wdd) +{ + int ret; + + mutex_lock(&wtd_deferred_reg_mutex); + if (wtd_deferred_reg_done) + ret = __watchdog_register_device(wdd); + else + ret = watchdog_deferred_registration_add(wdd); + mutex_unlock(&wtd_deferred_reg_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(watchdog_register_device); + +static void __watchdog_unregister_device(struct watchdog_device *wdd) { int ret; int devno; @@ -189,8 +235,43 @@ void watchdog_unregister_device(struct watchdog_device *wdd) ida_simple_remove(&watchdog_ida, wdd->id); wdd->dev = NULL; } + +/** + * watchdog_unregister_device() - unregister a watchdog device + * @wdd: watchdog device to unregister + * + * Unregister a watchdog device that was previously successfully + * registered with watchdog_register_device(). + */ + +void watchdog_unregister_device(struct watchdog_device *wdd) +{ + mutex_lock(&wtd_deferred_reg_mutex); + if (wtd_deferred_reg_done) + __watchdog_unregister_device(wdd); + else + watchdog_deferred_registration_del(wdd); + mutex_unlock(&wtd_deferred_reg_mutex); +} + EXPORT_SYMBOL_GPL(watchdog_unregister_device); +static int __init watchdog_deferred_registration(void) +{ + mutex_lock(&wtd_deferred_reg_mutex); + wtd_deferred_reg_done = true; + while (!list_empty(&wtd_deferred_reg_list)) { + struct watchdog_device *wdd; + + wdd = list_first_entry(&wtd_deferred_reg_list, + struct watchdog_device, deferred); + list_del(&wdd->deferred); + __watchdog_register_device(wdd); + } + mutex_unlock(&wtd_deferred_reg_mutex); + return 0; +} + static int __init watchdog_init(void) { int err; @@ -207,6 +288,7 @@ static int __init watchdog_init(void) return err; } + watchdog_deferred_registration(); return 0; } @@ -217,7 +299,7 @@ static void __exit watchdog_exit(void) ida_destroy(&watchdog_ida); } -subsys_initcall(watchdog_init); +subsys_initcall_sync(watchdog_init); module_exit(watchdog_exit); MODULE_AUTHOR("Alan Cox "); diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h index a746bf5216f8..f47feada5b42 100644 --- a/include/linux/watchdog.h +++ b/include/linux/watchdog.h @@ -65,6 +65,8 @@ struct watchdog_ops { * @driver-data:Pointer to the drivers private data. * @lock: Lock for watchdog core internal use only. * @status: Field that contains the devices internal status bits. + * @deferred: entry in wtd_deferred_reg_list which is used to + * register early initialized watchdogs. * * The watchdog_device structure contains all information about a * watchdog timer device. @@ -95,6 +97,7 @@ struct watchdog_device { #define WDOG_ALLOW_RELEASE 2 /* Did we receive the magic char ? */ #define WDOG_NO_WAY_OUT 3 /* Is 'nowayout' feature set ? */ #define WDOG_UNREGISTERED 4 /* Has the device been unregistered */ + struct list_head deferred; }; #define WATCHDOG_NOWAYOUT IS_BUILTIN(CONFIG_WATCHDOG_NOWAYOUT) -- cgit v1.2.3 From f522a975a8101895a85354b9c143f41b8248e71a Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 30 Jun 2015 16:20:20 +0200 Subject: net: mvneta: introduce compatible string "marvell, armada-xp-neta" The mvneta driver supports the Ethernet IP found in the Armada 370, XP, 380 and 385 SoCs. Since at least one more hardware feature is available for the Armada XP SoCs then a way to identify them is needed. This patch introduces a new compatible string "marvell,armada-xp-neta". Signed-off-by: Simon Guinot Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network unit") Cc: # v3.8+ Acked-by: Gregory CLEMENT Acked-by: Thomas Petazzoni Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 2 +- drivers/net/ethernet/marvell/mvneta.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt index 750d577e8083..f5a8ca29aff0 100644 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt @@ -1,7 +1,7 @@ * Marvell Armada 370 / Armada XP Ethernet Controller (NETA) Required properties: -- compatible: should be "marvell,armada-370-neta". +- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta". - reg: address and length of the register set for the device. - interrupts: interrupt for the device - phy: See ethernet.txt file in the same directory. diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 5bdf78231a4e..218749c6b806 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -3185,6 +3185,7 @@ static int mvneta_remove(struct platform_device *pdev) static const struct of_device_id mvneta_match[] = { { .compatible = "marvell,armada-370-neta" }, + { .compatible = "marvell,armada-xp-neta" }, { } }; MODULE_DEVICE_TABLE(of, mvneta_match); -- cgit v1.2.3 From 8a81252b774b53e628a8a0fe18e2b8fc236d92cc Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 30 Jun 2015 15:54:08 +0200 Subject: fs/file.c: don't acquire files->file_lock in fd_install() Mateusz Guzik reported : Currently obtaining a new file descriptor results in locking fdtable twice - once in order to reserve a slot and second time to fill it. Holding the spinlock in __fd_install() is needed in case a resize is done, or to prevent a resize. Mateusz provided an RFC patch and a micro benchmark : http://people.redhat.com/~mguzik/pipebench.c A resize is an unlikely operation in a process lifetime, as table size is at least doubled at every resize. We can use RCU instead of the spinlock. __fd_install() must wait if a resize is in progress. The resize must block new __fd_install() callers from starting, and wait that ongoing install are finished (synchronize_sched()) resize should be attempted by a single thread to not waste resources. rcu_sched variant is used, as __fd_install() and expand_fdtable() run from process context. It gives us a ~30% speedup using pipebench on a dual Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz Signed-off-by: Eric Dumazet Reported-by: Mateusz Guzik Acked-by: Mateusz Guzik Tested-by: Mateusz Guzik Signed-off-by: Al Viro --- Documentation/filesystems/porting | 4 +++ fs/file.c | 67 ++++++++++++++++++++++++++++----------- include/linux/fdtable.h | 3 ++ 3 files changed, 55 insertions(+), 19 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/porting b/Documentation/filesystems/porting index 3eae250254d5..ec5456113072 100644 --- a/Documentation/filesystems/porting +++ b/Documentation/filesystems/porting @@ -500,3 +500,7 @@ in your dentry operations instead. dentry, it does not get nameidata at all and it gets called only when cookie is non-NULL. Note that link body isn't available anymore, so if you need it, store it as cookie. +-- +[mandatory] + __fd_install() & fd_install() can now sleep. Callers should not + hold a spinlock or other resources that do not allow a schedule. diff --git a/fs/file.c b/fs/file.c index 93c5f89c248b..3d2eb4c542a4 100644 --- a/fs/file.c +++ b/fs/file.c @@ -147,6 +147,13 @@ static int expand_fdtable(struct files_struct *files, int nr) spin_unlock(&files->file_lock); new_fdt = alloc_fdtable(nr); + + /* make sure all __fd_install() have seen resize_in_progress + * or have finished their rcu_read_lock_sched() section. + */ + if (atomic_read(&files->count) > 1) + synchronize_sched(); + spin_lock(&files->file_lock); if (!new_fdt) return -ENOMEM; @@ -158,21 +165,14 @@ static int expand_fdtable(struct files_struct *files, int nr) __free_fdtable(new_fdt); return -EMFILE; } - /* - * Check again since another task may have expanded the fd table while - * we dropped the lock - */ cur_fdt = files_fdtable(files); - if (nr >= cur_fdt->max_fds) { - /* Continue as planned */ - copy_fdtable(new_fdt, cur_fdt); - rcu_assign_pointer(files->fdt, new_fdt); - if (cur_fdt != &files->fdtab) - call_rcu(&cur_fdt->rcu, free_fdtable_rcu); - } else { - /* Somebody else expanded, so undo our attempt */ - __free_fdtable(new_fdt); - } + BUG_ON(nr < cur_fdt->max_fds); + copy_fdtable(new_fdt, cur_fdt); + rcu_assign_pointer(files->fdt, new_fdt); + if (cur_fdt != &files->fdtab) + call_rcu(&cur_fdt->rcu, free_fdtable_rcu); + /* coupled with smp_rmb() in __fd_install() */ + smp_wmb(); return 1; } @@ -185,21 +185,38 @@ static int expand_fdtable(struct files_struct *files, int nr) * The files->file_lock should be held on entry, and will be held on exit. */ static int expand_files(struct files_struct *files, int nr) + __releases(files->file_lock) + __acquires(files->file_lock) { struct fdtable *fdt; + int expanded = 0; +repeat: fdt = files_fdtable(files); /* Do we need to expand? */ if (nr < fdt->max_fds) - return 0; + return expanded; /* Can we expand? */ if (nr >= sysctl_nr_open) return -EMFILE; + if (unlikely(files->resize_in_progress)) { + spin_unlock(&files->file_lock); + expanded = 1; + wait_event(files->resize_wait, !files->resize_in_progress); + spin_lock(&files->file_lock); + goto repeat; + } + /* All good, so we try */ - return expand_fdtable(files, nr); + files->resize_in_progress = true; + expanded = expand_fdtable(files, nr); + files->resize_in_progress = false; + + wake_up_all(&files->resize_wait); + return expanded; } static inline void __set_close_on_exec(int fd, struct fdtable *fdt) @@ -256,6 +273,8 @@ struct files_struct *dup_fd(struct files_struct *oldf, int *errorp) atomic_set(&newf->count, 1); spin_lock_init(&newf->file_lock); + newf->resize_in_progress = false; + init_waitqueue_head(&newf->resize_wait); newf->next_fd = 0; new_fdt = &newf->fdtab; new_fdt->max_fds = NR_OPEN_DEFAULT; @@ -553,11 +572,21 @@ void __fd_install(struct files_struct *files, unsigned int fd, struct file *file) { struct fdtable *fdt; - spin_lock(&files->file_lock); - fdt = files_fdtable(files); + + might_sleep(); + rcu_read_lock_sched(); + + while (unlikely(files->resize_in_progress)) { + rcu_read_unlock_sched(); + wait_event(files->resize_wait, !files->resize_in_progress); + rcu_read_lock_sched(); + } + /* coupled with smp_wmb() in expand_fdtable() */ + smp_rmb(); + fdt = rcu_dereference_sched(files->fdt); BUG_ON(fdt->fd[fd] != NULL); rcu_assign_pointer(fdt->fd[fd], file); - spin_unlock(&files->file_lock); + rcu_read_unlock_sched(); } void fd_install(unsigned int fd, struct file *file) diff --git a/include/linux/fdtable.h b/include/linux/fdtable.h index 230f87bdf5ad..fbb88740634a 100644 --- a/include/linux/fdtable.h +++ b/include/linux/fdtable.h @@ -47,6 +47,9 @@ struct files_struct { * read mostly part */ atomic_t count; + bool resize_in_progress; + wait_queue_head_t resize_wait; + struct fdtable __rcu *fdt; struct fdtable fdtab; /* -- cgit v1.2.3 From 00c570f4ba43ae73b41fa0a2269c3b0ac20386ef Mon Sep 17 00:00:00 2001 From: Miklos Szeredi Date: Wed, 1 Jul 2015 16:26:08 +0200 Subject: fuse: device fd clone Allow an open fuse device to be "cloned". Userspace can create a clone by: newfd = open("/dev/fuse", O_RDWR) ioctl(newfd, FUSE_DEV_IOC_CLONE, &oldfd); At this point newfd will refer to the same fuse connection as oldfd. Signed-off-by: Miklos Szeredi Reviewed-by: Ashish Samant --- Documentation/ioctl/ioctl-number.txt | 1 + fs/fuse/dev.c | 40 ++++++++++++++++++++++++++++++++++++ include/uapi/linux/fuse.h | 3 +++ 3 files changed, 44 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 51f4221657bf..611c52267d24 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -321,6 +321,7 @@ Code Seq#(hex) Include File Comments 0xDB 00-0F drivers/char/mwave/mwavepub.h 0xDD 00-3F ZFCP device driver see drivers/s390/scsi/ +0xE5 00-3F linux/fuse.h 0xEC 00-01 drivers/platform/chrome/cros_ec_dev.h ChromeOS EC driver 0xF3 00-3F drivers/usb/misc/sisusbvga/sisusb.h sisfb (in development) diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index dcfc87172a47..d405c1fa4618 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -2197,6 +2197,44 @@ static int fuse_dev_fasync(int fd, struct file *file, int on) return fasync_helper(fd, file, on, &fc->iq.fasync); } +static int fuse_device_clone(struct fuse_conn *fc, struct file *new) +{ + if (new->private_data) + return -EINVAL; + + new->private_data = fuse_conn_get(fc); + + return 0; +} + +static long fuse_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + int err = -ENOTTY; + + if (cmd == FUSE_DEV_IOC_CLONE) { + int oldfd; + + err = -EFAULT; + if (!get_user(oldfd, (__u32 __user *) arg)) { + struct file *old = fget(oldfd); + + err = -EINVAL; + if (old) { + struct fuse_conn *fc = fuse_get_conn(old); + + if (fc) { + mutex_lock(&fuse_mutex); + err = fuse_device_clone(fc, file); + mutex_unlock(&fuse_mutex); + } + fput(old); + } + } + } + return err; +} + const struct file_operations fuse_dev_operations = { .owner = THIS_MODULE, .open = fuse_dev_open, @@ -2208,6 +2246,8 @@ const struct file_operations fuse_dev_operations = { .poll = fuse_dev_poll, .release = fuse_dev_release, .fasync = fuse_dev_fasync, + .unlocked_ioctl = fuse_dev_ioctl, + .compat_ioctl = fuse_dev_ioctl, }; EXPORT_SYMBOL_GPL(fuse_dev_operations); diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index 25084a052a1e..c9aca042e61d 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -755,4 +755,7 @@ struct fuse_notify_retrieve_in { uint64_t dummy4; }; +/* Device ioctls: */ +#define FUSE_DEV_IOC_CLONE _IOR(229, 0, uint32_t) + #endif /* _LINUX_FUSE_H */ -- cgit v1.2.3 From b2102eb36e7909c779e46f66595fda75aa219f4c Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Thu, 25 Jun 2015 12:21:51 +0200 Subject: watchdog: omap_wdt: early_enable module parameter Add a early_enable module parameter to the omap_wdt that starts the watchdog on module insertion. The default value is 0 which does not start the watchdog - which also does not change the behavior if the parameter is not given. Signed-off-by: Lars Poeschel Reviewed-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/watchdog/watchdog-parameters.txt | 1 + drivers/watchdog/omap_wdt.c | 8 ++++++++ 2 files changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/watchdog/watchdog-parameters.txt b/Documentation/watchdog/watchdog-parameters.txt index 74252c431e05..9f9ec9f76039 100644 --- a/Documentation/watchdog/watchdog-parameters.txt +++ b/Documentation/watchdog/watchdog-parameters.txt @@ -208,6 +208,7 @@ nowayout: Watchdog cannot be stopped once started ------------------------------------------------- omap_wdt: timer_margin: initial watchdog timeout (in seconds) +early_enable: Watchdog is started on module insertion (default=0 nowayout: Watchdog cannot be stopped once started (default=kernel config parameter) ------------------------------------------------- diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index ebea6e66fba9..de911c7e477c 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -55,6 +55,11 @@ MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); #define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog) +static bool early_enable; +module_param(early_enable, bool, 0); +MODULE_PARM_DESC(early_enable, + "Watchdog is started on module insertion (default=0)"); + struct omap_wdt_dev { struct watchdog_device wdog; void __iomem *base; /* physical */ @@ -279,6 +284,9 @@ static int omap_wdt_probe(struct platform_device *pdev) pm_runtime_put_sync(wdev->dev); + if (early_enable) + omap_wdt_start(&wdev->wdog); + return 0; } -- cgit v1.2.3 From 50f0a44991516b5b9744ecb2c080c2ec6ad21b25 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 17 Jun 2015 10:59:04 +0200 Subject: ARM: at91/dt: trivial: fix USB udc compatible string To please checkpatch and the tiresome reader, add the "atmel," prefix to the USB udc compatible string. Signed-off-by: Nicolas Ferre Cc: #4.0+ Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/usb/atmel-usb.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 1be8d7a26c15..5883b73ea1b5 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -79,9 +79,9 @@ Atmel High-Speed USB device controller Required properties: - compatible: Should be one of the following - "at91sam9rl-udc" - "at91sam9g45-udc" - "sama5d3-udc" + "atmel,at91sam9rl-udc" + "atmel,at91sam9g45-udc" + "atmel,sama5d3-udc" - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt - clocks: Should reference the peripheral and host clocks -- cgit v1.2.3 From 864d5bb957138d1ed9641a5eff7849a56ddadc16 Mon Sep 17 00:00:00 2001 From: James C Boyd Date: Wed, 1 Jul 2015 15:13:26 -0500 Subject: x86/asm/entry/64: Update path names The paths mentioned in this file weren't updated through some file rename commits. Fix them to refer to the correct path. Signed-off-by: James C Boyd Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: corbet@lwn.net Cc: trivial@kernel.org Link: http://lkml.kernel.org/r/1435781606-3037-1-git-send-email-jcboyd.dev@gmail.com Signed-off-by: Ingo Molnar --- Documentation/x86/entry_64.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/x86/entry_64.txt b/Documentation/x86/entry_64.txt index 33884d156125..c1df8eba9dfd 100644 --- a/Documentation/x86/entry_64.txt +++ b/Documentation/x86/entry_64.txt @@ -1,14 +1,14 @@ This file documents some of the kernel entries in -arch/x86/kernel/entry_64.S. A lot of this explanation is adapted from +arch/x86/entry/entry_64.S. A lot of this explanation is adapted from an email from Ingo Molnar: http://lkml.kernel.org/r/<20110529191055.GC9835%40elte.hu> The x86 architecture has quite a few different ways to jump into kernel code. Most of these entry points are registered in -arch/x86/kernel/traps.c and implemented in arch/x86/kernel/entry_64.S -for 64-bit, arch/x86/kernel/entry_32.S for 32-bit and finally -arch/x86/ia32/ia32entry.S which implements the 32-bit compatibility +arch/x86/kernel/traps.c and implemented in arch/x86/entry/entry_64.S +for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally +arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility syscall entry points and thus provides for 32-bit processes the ability to execute syscalls when running on 64-bit kernels. -- cgit v1.2.3 From 18d78b64fddc11eb336f01e46ad3303a3f55d039 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Fri, 3 Jul 2015 01:06:00 +0200 Subject: ACPI / init: Make it possible to override _REV The platform firmware on some systems expects Linux to return "5" as the supported ACPI revision which makes it expose system configuration information in a special way. For example, based on what ACPI exports as the supported revision, Dell XPS 13 (2015) configures its audio device to either work in HDA mode or in I2S mode, where the former is supposed to be used on Linux until the latter is fully supported (in the kernel as well as in user space). Since ACPI 6 mandates that _REV should return "2" if ACPI 2 or later is supported by the OS, a subsequent change will make that happen, so make it possible to override that on systems where "5" is expected to be returned for Linux to work correctly one them (such as the Dell machine mentioned above). Original-by: Dominik Brodowski Signed-off-by: Rafael J. Wysocki --- Documentation/kernel-parameters.txt | 6 ++++++ drivers/acpi/Kconfig | 20 ++++++++++++++++++++ drivers/acpi/blacklist.c | 26 ++++++++++++++++++++++++++ drivers/acpi/internal.h | 1 + drivers/acpi/osl.c | 18 ++++++++++++++++++ 5 files changed, 71 insertions(+) (limited to 'Documentation') diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 61ab1628a057..180102480fc0 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -274,6 +274,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. acpi_os_name= [HW,ACPI] Tell ACPI BIOS the name of the OS Format: To spoof as Windows 98: ="Microsoft Windows" + acpi_rev_override [ACPI] Override the _REV object to return 5 (instead + of 2 which is mandated by ACPI 6) as the supported ACPI + specification revision (when using this switch, it may + be necessary to carry out a cold reboot _twice_ in a + row to make it take effect on the platform firmware). + acpi_osi= [HW,ACPI] Modify list of supported OS interface strings acpi_osi="string1" # add string1 acpi_osi="!string2" # remove string2 diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index ab2cbb51c6aa..2b652f1d4edb 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -77,6 +77,26 @@ config ACPI_PROCFS_POWER Say N to delete power /proc/acpi/ directories that have moved to /sys/ +config ACPI_REV_OVERRIDE_POSSIBLE + bool "Allow supported ACPI revision to be overriden" + depends on X86 + default y + help + The platform firmware on some systems expects Linux to return "5" as + the supported ACPI revision which makes it expose system configuration + information in a special way. + + For example, based on what ACPI exports as the supported revision, + Dell XPS 13 (2015) configures its audio device to either work in HDA + mode or in I2S mode, where the former is supposed to be used on Linux + until the latter is fully supported (in the kernel as well as in user + space). + + This option enables a DMI-based quirk for the above Dell machine (so + that HDA audio is exposed by the platform firmware to the kernel) and + makes it possible to force the kernel to return "5" as the supported + ACPI revision via the "acpi_rev_override" command line switch. + config ACPI_EC_DEBUGFS tristate "EC read/write access through /sys/kernel/debug/ec" default n diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/blacklist.c index 1d1791935c31..278dc4be992a 100644 --- a/drivers/acpi/blacklist.c +++ b/drivers/acpi/blacklist.c @@ -162,6 +162,15 @@ static int __init dmi_disable_osi_win8(const struct dmi_system_id *d) acpi_osi_setup("!Windows 2012"); return 0; } +#ifdef CONFIG_ACPI_REV_OVERRIDE_POSSIBLE +static int __init dmi_enable_rev_override(const struct dmi_system_id *d) +{ + printk(KERN_NOTICE PREFIX "DMI detected: %s (force ACPI _REV to 5)\n", + d->ident); + acpi_rev_override_setup(NULL); + return 0; +} +#endif static struct dmi_system_id acpi_osi_dmi_table[] __initdata = { { @@ -325,6 +334,23 @@ static struct dmi_system_id acpi_osi_dmi_table[] __initdata = { DMI_MATCH(DMI_PRODUCT_NAME, "1015PX"), }, }, + +#ifdef CONFIG_ACPI_REV_OVERRIDE_POSSIBLE + /* + * DELL XPS 13 (2015) switches sound between HDA and I2S + * depending on the ACPI _REV callback. If userspace supports + * I2S sufficiently (or if you do not care about sound), you + * can safely disable this quirk. + */ + { + .callback = dmi_enable_rev_override, + .ident = "DELL XPS 13 (2015)", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343"), + }, + }, +#endif {} }; diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h index ba4a61e964be..42f304288829 100644 --- a/drivers/acpi/internal.h +++ b/drivers/acpi/internal.h @@ -58,6 +58,7 @@ void acpi_cmos_rtc_init(void); #else static inline void acpi_cmos_rtc_init(void) {} #endif +int acpi_rev_override_setup(char *str); extern bool acpi_force_hot_remove; diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 39748bb3a543..37e592798cd5 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -537,6 +537,19 @@ acpi_os_get_physical_address(void *virt, acpi_physical_address * phys) } #endif +#ifdef CONFIG_ACPI_REV_OVERRIDE_POSSIBLE +static bool acpi_rev_override; + +int __init acpi_rev_override_setup(char *str) +{ + acpi_rev_override = true; + return 1; +} +__setup("acpi_rev_override", acpi_rev_override_setup); +#else +#define acpi_rev_override false +#endif + #define ACPI_MAX_OVERRIDE_LEN 100 static char acpi_os_name[ACPI_MAX_OVERRIDE_LEN]; @@ -555,6 +568,11 @@ acpi_os_predefined_override(const struct acpi_predefined_names *init_val, *new_val = acpi_os_name; } + if (!memcmp(init_val->name, "_REV", 4) && acpi_rev_override) { + printk(KERN_INFO PREFIX "Overriding _REV return value to 5\n"); + *new_val = (char *)5; + } + return AE_OK; } -- cgit v1.2.3 From f617f7310cfdca5245a10629979d85682323f1a4 Mon Sep 17 00:00:00 2001 From: Roger Lucas Date: Tue, 12 May 2015 22:01:37 +0100 Subject: hwmon: (w83792d) Additional PWM outputs support Add pwm[4-7] and the associated pwm[4-7]_mode attributes. Signed-off-by: Roger Lucas Signed-off-by: Jean Delvare --- Documentation/hwmon/w83792d | 18 +++++++++++++----- drivers/hwmon/w83792d.c | 27 ++++++++++++++++++++++----- 2 files changed, 35 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/hwmon/w83792d b/Documentation/hwmon/w83792d index 53f7b6866fec..f2ffc402ea45 100644 --- a/Documentation/hwmon/w83792d +++ b/Documentation/hwmon/w83792d @@ -8,6 +8,7 @@ Supported chips: Datasheet: http://www.winbond.com.tw Author: Shane Huang (Winbond) +Updated: Roger Lucas Module Parameters @@ -38,9 +39,16 @@ parameter; this will put it into a more well-behaved state first. The driver implements three temperature sensors, seven fan rotation speed sensors, nine voltage sensors, and two automatic fan regulation strategies called: Smart Fan I (Thermal Cruise mode) and Smart Fan II. -Automatic fan control mode is possible only for fan1-fan3. Fan4-fan7 can run -synchronized with selected fan (fan1-fan3). This functionality and manual PWM -control for fan4-fan7 is not yet implemented. + +The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7 +can be configured to PWM output or Analogue DC output via their associated +pwmX_mode. Outputs pwm4 through pwm7 may or may not be present depending on +how the W83792AD/D was configured by the BIOS. + +Automatic fan control mode is possible only for fan1-fan3. + +For all pwmX outputs, a value of 0 means minimum fan speed and a value of +255 means maximum fan speed. Temperatures are measured in degrees Celsius and measurement resolution is 1 degC for temp1 and 0.5 degC for temp2 and temp3. An alarm is triggered when @@ -157,14 +165,14 @@ for each fan. /sys files ---------- -pwm[1-3] - this file stores PWM duty cycle or DC value (fan speed) in range: +pwm[1-7] - this file stores PWM duty cycle or DC value (fan speed) in range: 0 (stop) to 255 (full) pwm[1-3]_enable - this file controls mode of fan/temperature control: * 0 Disabled * 1 Manual mode * 2 Smart Fan II * 3 Thermal Cruise -pwm[1-3]_mode - Select PWM of DC mode +pwm[1-7]_mode - Select PWM or DC mode * 0 DC * 1 PWM thermal_cruise[1-3] - Selects the desired temperature for cruise (degC) diff --git a/drivers/hwmon/w83792d.c b/drivers/hwmon/w83792d.c index 4068db4d9580..0a8bce726b4b 100644 --- a/drivers/hwmon/w83792d.c +++ b/drivers/hwmon/w83792d.c @@ -289,10 +289,7 @@ struct w83792d_data { u8 temp1[3]; /* current, over, thyst */ u8 temp_add[2][6]; /* Register value */ u8 fan_div[7]; /* Register encoding, shifted right */ - u8 pwm[7]; /* - * We only consider the first 3 set of pwm, - * although 792 chip has 7 set of pwm. - */ + u8 pwm[7]; /* The 7 PWM outputs */ u8 pwmenable[3]; u32 alarms; /* realtime status register encoding,combined */ u8 chassis; /* Chassis status */ @@ -1075,6 +1072,10 @@ static DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, static SENSOR_DEVICE_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0); static SENSOR_DEVICE_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1); static SENSOR_DEVICE_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2); +static SENSOR_DEVICE_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3); +static SENSOR_DEVICE_ATTR(pwm5, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 4); +static SENSOR_DEVICE_ATTR(pwm6, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 5); +static SENSOR_DEVICE_ATTR(pwm7, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 6); static SENSOR_DEVICE_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwmenable, store_pwmenable, 1); static SENSOR_DEVICE_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, @@ -1087,6 +1088,14 @@ static SENSOR_DEVICE_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode, store_pwm_mode, 1); static SENSOR_DEVICE_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode, store_pwm_mode, 2); +static SENSOR_DEVICE_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, + show_pwm_mode, store_pwm_mode, 3); +static SENSOR_DEVICE_ATTR(pwm5_mode, S_IWUSR | S_IRUGO, + show_pwm_mode, store_pwm_mode, 4); +static SENSOR_DEVICE_ATTR(pwm6_mode, S_IWUSR | S_IRUGO, + show_pwm_mode, store_pwm_mode, 5); +static SENSOR_DEVICE_ATTR(pwm7_mode, S_IWUSR | S_IRUGO, + show_pwm_mode, store_pwm_mode, 6); static SENSOR_DEVICE_ATTR(tolerance1, S_IWUSR | S_IRUGO, show_tolerance, store_tolerance, 1); static SENSOR_DEVICE_ATTR(tolerance2, S_IWUSR | S_IRUGO, @@ -1177,30 +1186,38 @@ static SENSOR_DEVICE_ATTR(fan6_div, S_IWUSR | S_IRUGO, static SENSOR_DEVICE_ATTR(fan7_div, S_IWUSR | S_IRUGO, show_fan_div, store_fan_div, 7); -static struct attribute *w83792d_attributes_fan[4][5] = { +static struct attribute *w83792d_attributes_fan[4][7] = { { &sensor_dev_attr_fan4_input.dev_attr.attr, &sensor_dev_attr_fan4_min.dev_attr.attr, &sensor_dev_attr_fan4_div.dev_attr.attr, &sensor_dev_attr_fan4_alarm.dev_attr.attr, + &sensor_dev_attr_pwm4.dev_attr.attr, + &sensor_dev_attr_pwm4_mode.dev_attr.attr, NULL }, { &sensor_dev_attr_fan5_input.dev_attr.attr, &sensor_dev_attr_fan5_min.dev_attr.attr, &sensor_dev_attr_fan5_div.dev_attr.attr, &sensor_dev_attr_fan5_alarm.dev_attr.attr, + &sensor_dev_attr_pwm5.dev_attr.attr, + &sensor_dev_attr_pwm5_mode.dev_attr.attr, NULL }, { &sensor_dev_attr_fan6_input.dev_attr.attr, &sensor_dev_attr_fan6_min.dev_attr.attr, &sensor_dev_attr_fan6_div.dev_attr.attr, &sensor_dev_attr_fan6_alarm.dev_attr.attr, + &sensor_dev_attr_pwm6.dev_attr.attr, + &sensor_dev_attr_pwm6_mode.dev_attr.attr, NULL }, { &sensor_dev_attr_fan7_input.dev_attr.attr, &sensor_dev_attr_fan7_min.dev_attr.attr, &sensor_dev_attr_fan7_div.dev_attr.attr, &sensor_dev_attr_fan7_alarm.dev_attr.attr, + &sensor_dev_attr_pwm7.dev_attr.attr, + &sensor_dev_attr_pwm7_mode.dev_attr.attr, NULL } }; -- cgit v1.2.3 From 97607f9882a0e0d3553382a4c7996d3a37d08268 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 3 Jul 2015 14:39:05 +0200 Subject: hwmon: Document which I2C addresses can be probed Add an item to the checklist when submitting a new hwmon driver: only some I2C addresses can be probed, others should not for safety reasons. Signed-off-by: Jean Delvare Reviewed-by: Guenter Roeck --- Documentation/hwmon/submitting-patches | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/hwmon/submitting-patches b/Documentation/hwmon/submitting-patches index 3d1bac399a22..d201828d202f 100644 --- a/Documentation/hwmon/submitting-patches +++ b/Documentation/hwmon/submitting-patches @@ -81,6 +81,13 @@ increase the chances of your change being accepted. * Provide a detect function if and only if a chip can be detected reliably. +* Only the following I2C addresses shall be probed: 0x18-0x1f, 0x28-0x2f, + 0x48-0x4f, 0x58, 0x5c, 0x73 and 0x77. Probing other addresses is strongly + discouraged as it is known to cause trouble with other (non-hwmon) I2C + chips. If your chip lives at an address which can't be probed then the + device will have to be instantiated explicitly (which is always better + anyway.) + * Avoid writing to chip registers in the detect function. If you have to write, only do it after you have already gathered enough data to be certain that the detection is going to be successful. -- cgit v1.2.3 From a1bd3baeb2f18b2b3d0f98ce5fdaa725149b950b Mon Sep 17 00:00:00 2001 From: Allen Hubbe Date: Thu, 9 Apr 2015 10:33:20 -0400 Subject: NTB: Add NTB hardware abstraction layer Abstract the NTB device behind a programming interface, so that it can support different hardware and client drivers. Signed-off-by: Allen Hubbe Signed-off-by: Jon Mason --- Documentation/ntb.txt | 32 ++ MAINTAINERS | 4 +- drivers/ntb/Makefile | 1 + drivers/ntb/ntb.c | 251 +++++++++++++ include/linux/ntb.h | 984 ++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 1271 insertions(+), 1 deletion(-) create mode 100644 Documentation/ntb.txt create mode 100644 drivers/ntb/ntb.c create mode 100644 include/linux/ntb.h (limited to 'Documentation') diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt new file mode 100644 index 000000000000..9d46dc9712a8 --- /dev/null +++ b/Documentation/ntb.txt @@ -0,0 +1,32 @@ +# NTB Drivers + +NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects +the separate memory systems of two computers to the same PCI-Express fabric. +Existing NTB hardware supports a common feature set, including scratchpad +registers, doorbell registers, and memory translation windows. Scratchpad +registers are read-and-writable registers that are accessible from either side +of the device, so that peers can exchange a small amount of information at a +fixed address. Doorbell registers provide a way for peers to send interrupt +events. Memory windows allow translated read and write access to the peer +memory. + +## NTB Core Driver (ntb) + +The NTB core driver defines an api wrapping the common feature set, and allows +clients interested in NTB features to discover NTB the devices supported by +hardware drivers. The term "client" is used here to mean an upper layer +component making use of the NTB api. The term "driver," or "hardware driver," +is used here to mean a driver for a specific vendor and model of NTB hardware. + +## NTB Client Drivers + +NTB client drivers should register with the NTB core driver. After +registering, the client probe and remove functions will be called appropriately +as ntb hardware, or hardware drivers, are inserted and removed. The +registration uses the Linux Device framework, so it should feel familiar to +anyone who has written a pci driver. + +## NTB Hardware Drivers + +NTB hardware drivers should register devices with the NTB core driver. After +registering, clients probe and remove functions will be called. diff --git a/MAINTAINERS b/MAINTAINERS index 663bc8ed1860..e2fc9eec2e16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6995,15 +6995,17 @@ F: drivers/power/bq27x00_battery.c F: drivers/power/isp1704_charger.c F: drivers/power/rx51_battery.c -NTB DRIVER +NTB DRIVER CORE M: Jon Mason M: Dave Jiang +M: Allen Hubbe S: Supported W: https://github.com/jonmason/ntb/wiki T: git git://github.com/jonmason/ntb.git F: drivers/ntb/ F: drivers/net/ntb_netdev.c F: include/linux/ntb.h +F: include/linux/ntb_transport.h NTFS FILESYSTEM M: Anton Altaparmakov diff --git a/drivers/ntb/Makefile b/drivers/ntb/Makefile index 545b10a131af..712e953a8fda 100644 --- a/drivers/ntb/Makefile +++ b/drivers/ntb/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_NTB) += ntb.o obj-$(CONFIG_NTB) += ntb_hw_intel.o ntb_hw_intel-objs := hw/intel/ntb_hw_intel.o ntb_transport.o diff --git a/drivers/ntb/ntb.c b/drivers/ntb/ntb.c new file mode 100644 index 000000000000..23435f2a5486 --- /dev/null +++ b/drivers/ntb/ntb.c @@ -0,0 +1,251 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * BSD LICENSE + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copy + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * PCIe NTB Linux driver + * + * Contact Information: + * Allen Hubbe + */ + +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "ntb" +#define DRIVER_DESCRIPTION "PCIe NTB Driver Framework" + +#define DRIVER_LICENSE "Dual BSD/GPL" +#define DRIVER_VERSION "1.0" +#define DRIVER_RELDATE "24 March 2015" +#define DRIVER_AUTHOR "Allen Hubbe " + +MODULE_LICENSE(DRIVER_LICENSE); +MODULE_VERSION(DRIVER_VERSION); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESCRIPTION); + +static struct bus_type ntb_bus; +static void ntb_dev_release(struct device *dev); + +int __ntb_register_client(struct ntb_client *client, struct module *mod, + const char *mod_name) +{ + if (!client) + return -EINVAL; + if (!ntb_client_ops_is_valid(&client->ops)) + return -EINVAL; + + memset(&client->drv, 0, sizeof(client->drv)); + client->drv.bus = &ntb_bus; + client->drv.name = mod_name; + client->drv.owner = mod; + + return driver_register(&client->drv); +} +EXPORT_SYMBOL(__ntb_register_client); + +void ntb_unregister_client(struct ntb_client *client) +{ + driver_unregister(&client->drv); +} +EXPORT_SYMBOL(ntb_unregister_client); + +int ntb_register_device(struct ntb_dev *ntb) +{ + if (!ntb) + return -EINVAL; + if (!ntb->pdev) + return -EINVAL; + if (!ntb->ops) + return -EINVAL; + if (!ntb_dev_ops_is_valid(ntb->ops)) + return -EINVAL; + + init_completion(&ntb->released); + + memset(&ntb->dev, 0, sizeof(ntb->dev)); + ntb->dev.bus = &ntb_bus; + ntb->dev.parent = &ntb->pdev->dev; + ntb->dev.release = ntb_dev_release; + dev_set_name(&ntb->dev, pci_name(ntb->pdev)); + + ntb->ctx = NULL; + ntb->ctx_ops = NULL; + spin_lock_init(&ntb->ctx_lock); + + return device_register(&ntb->dev); +} +EXPORT_SYMBOL(ntb_register_device); + +void ntb_unregister_device(struct ntb_dev *ntb) +{ + device_unregister(&ntb->dev); + wait_for_completion(&ntb->released); +} +EXPORT_SYMBOL(ntb_unregister_device); + +int ntb_set_ctx(struct ntb_dev *ntb, void *ctx, + const struct ntb_ctx_ops *ctx_ops) +{ + unsigned long irqflags; + + if (!ntb_ctx_ops_is_valid(ctx_ops)) + return -EINVAL; + if (ntb->ctx_ops) + return -EINVAL; + + spin_lock_irqsave(&ntb->ctx_lock, irqflags); + { + ntb->ctx = ctx; + ntb->ctx_ops = ctx_ops; + } + spin_unlock_irqrestore(&ntb->ctx_lock, irqflags); + + return 0; +} +EXPORT_SYMBOL(ntb_set_ctx); + +void ntb_clear_ctx(struct ntb_dev *ntb) +{ + unsigned long irqflags; + + spin_lock_irqsave(&ntb->ctx_lock, irqflags); + { + ntb->ctx_ops = NULL; + ntb->ctx = NULL; + } + spin_unlock_irqrestore(&ntb->ctx_lock, irqflags); +} +EXPORT_SYMBOL(ntb_clear_ctx); + +void ntb_link_event(struct ntb_dev *ntb) +{ + unsigned long irqflags; + + spin_lock_irqsave(&ntb->ctx_lock, irqflags); + { + if (ntb->ctx_ops && ntb->ctx_ops->link_event) + ntb->ctx_ops->link_event(ntb->ctx); + } + spin_unlock_irqrestore(&ntb->ctx_lock, irqflags); +} +EXPORT_SYMBOL(ntb_link_event); + +void ntb_db_event(struct ntb_dev *ntb, int vector) +{ + unsigned long irqflags; + + spin_lock_irqsave(&ntb->ctx_lock, irqflags); + { + if (ntb->ctx_ops && ntb->ctx_ops->db_event) + ntb->ctx_ops->db_event(ntb->ctx, vector); + } + spin_unlock_irqrestore(&ntb->ctx_lock, irqflags); +} +EXPORT_SYMBOL(ntb_db_event); + +static int ntb_probe(struct device *dev) +{ + struct ntb_dev *ntb; + struct ntb_client *client; + int rc; + + get_device(dev); + ntb = dev_ntb(dev); + client = drv_ntb_client(dev->driver); + + rc = client->ops.probe(client, ntb); + if (rc) + put_device(dev); + + return rc; +} + +static int ntb_remove(struct device *dev) +{ + struct ntb_dev *ntb; + struct ntb_client *client; + + if (dev->driver) { + ntb = dev_ntb(dev); + client = drv_ntb_client(dev->driver); + + client->ops.remove(client, ntb); + put_device(dev); + } + + return 0; +} + +static void ntb_dev_release(struct device *dev) +{ + struct ntb_dev *ntb = dev_ntb(dev); + + complete(&ntb->released); +} + +static struct bus_type ntb_bus = { + .name = "ntb", + .probe = ntb_probe, + .remove = ntb_remove, +}; + +static int __init ntb_driver_init(void) +{ + return bus_register(&ntb_bus); +} +module_init(ntb_driver_init); + +static void __exit ntb_driver_exit(void) +{ + bus_unregister(&ntb_bus); +} +module_exit(ntb_driver_exit); + diff --git a/include/linux/ntb.h b/include/linux/ntb.h new file mode 100644 index 000000000000..b02f72bb8e32 --- /dev/null +++ b/include/linux/ntb.h @@ -0,0 +1,984 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * BSD LICENSE + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copy + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * PCIe NTB Linux driver + * + * Contact Information: + * Allen Hubbe + */ + +#ifndef _NTB_H_ +#define _NTB_H_ + +#include +#include + +struct ntb_client; +struct ntb_dev; +struct pci_dev; + +/** + * enum ntb_topo - NTB connection topology + * @NTB_TOPO_NONE: Topology is unknown or invalid. + * @NTB_TOPO_PRI: On primary side of local ntb. + * @NTB_TOPO_SEC: On secondary side of remote ntb. + * @NTB_TOPO_B2B_USD: On primary side of local ntb upstream of remote ntb. + * @NTB_TOPO_B2B_DSD: On primary side of local ntb downstream of remote ntb. + */ +enum ntb_topo { + NTB_TOPO_NONE = -1, + NTB_TOPO_PRI, + NTB_TOPO_SEC, + NTB_TOPO_B2B_USD, + NTB_TOPO_B2B_DSD, +}; + +static inline int ntb_topo_is_b2b(enum ntb_topo topo) +{ + switch ((int)topo) { + case NTB_TOPO_B2B_USD: + case NTB_TOPO_B2B_DSD: + return 1; + } + return 0; +} + +static inline char *ntb_topo_string(enum ntb_topo topo) +{ + switch (topo) { + case NTB_TOPO_NONE: return "NTB_TOPO_NONE"; + case NTB_TOPO_PRI: return "NTB_TOPO_PRI"; + case NTB_TOPO_SEC: return "NTB_TOPO_SEC"; + case NTB_TOPO_B2B_USD: return "NTB_TOPO_B2B_USD"; + case NTB_TOPO_B2B_DSD: return "NTB_TOPO_B2B_DSD"; + } + return "NTB_TOPO_INVALID"; +} + +/** + * enum ntb_speed - NTB link training speed + * @NTB_SPEED_AUTO: Request the max supported speed. + * @NTB_SPEED_NONE: Link is not trained to any speed. + * @NTB_SPEED_GEN1: Link is trained to gen1 speed. + * @NTB_SPEED_GEN2: Link is trained to gen2 speed. + * @NTB_SPEED_GEN3: Link is trained to gen3 speed. + */ +enum ntb_speed { + NTB_SPEED_AUTO = -1, + NTB_SPEED_NONE = 0, + NTB_SPEED_GEN1 = 1, + NTB_SPEED_GEN2 = 2, + NTB_SPEED_GEN3 = 3, +}; + +/** + * enum ntb_width - NTB link training width + * @NTB_WIDTH_AUTO: Request the max supported width. + * @NTB_WIDTH_NONE: Link is not trained to any width. + * @NTB_WIDTH_1: Link is trained to 1 lane width. + * @NTB_WIDTH_2: Link is trained to 2 lane width. + * @NTB_WIDTH_4: Link is trained to 4 lane width. + * @NTB_WIDTH_8: Link is trained to 8 lane width. + * @NTB_WIDTH_12: Link is trained to 12 lane width. + * @NTB_WIDTH_16: Link is trained to 16 lane width. + * @NTB_WIDTH_32: Link is trained to 32 lane width. + */ +enum ntb_width { + NTB_WIDTH_AUTO = -1, + NTB_WIDTH_NONE = 0, + NTB_WIDTH_1 = 1, + NTB_WIDTH_2 = 2, + NTB_WIDTH_4 = 4, + NTB_WIDTH_8 = 8, + NTB_WIDTH_12 = 12, + NTB_WIDTH_16 = 16, + NTB_WIDTH_32 = 32, +}; + +/** + * struct ntb_client_ops - ntb client operations + * @probe: Notify client of a new device. + * @remove: Notify client to remove a device. + */ +struct ntb_client_ops { + int (*probe)(struct ntb_client *client, struct ntb_dev *ntb); + void (*remove)(struct ntb_client *client, struct ntb_dev *ntb); +}; + +static inline int ntb_client_ops_is_valid(const struct ntb_client_ops *ops) +{ + /* commented callbacks are not required: */ + return + ops->probe && + ops->remove && + 1; +} + +/** + * struct ntb_ctx_ops - ntb driver context operations + * @link_event: See ntb_link_event(). + * @db_event: See ntb_db_event(). + */ +struct ntb_ctx_ops { + void (*link_event)(void *ctx); + void (*db_event)(void *ctx, int db_vector); +}; + +static inline int ntb_ctx_ops_is_valid(const struct ntb_ctx_ops *ops) +{ + /* commented callbacks are not required: */ + return + /* ops->link_event && */ + /* ops->db_event && */ + 1; +} + +/** + * struct ntb_ctx_ops - ntb device operations + * @mw_count: See ntb_mw_count(). + * @mw_get_range: See ntb_mw_get_range(). + * @mw_set_trans: See ntb_mw_set_trans(). + * @mw_clear_trans: See ntb_mw_clear_trans(). + * @link_is_up: See ntb_link_is_up(). + * @link_enable: See ntb_link_enable(). + * @link_disable: See ntb_link_disable(). + * @db_is_unsafe: See ntb_db_is_unsafe(). + * @db_valid_mask: See ntb_db_valid_mask(). + * @db_vector_count: See ntb_db_vector_count(). + * @db_vector_mask: See ntb_db_vector_mask(). + * @db_read: See ntb_db_read(). + * @db_set: See ntb_db_set(). + * @db_clear: See ntb_db_clear(). + * @db_read_mask: See ntb_db_read_mask(). + * @db_set_mask: See ntb_db_set_mask(). + * @db_clear_mask: See ntb_db_clear_mask(). + * @peer_db_addr: See ntb_peer_db_addr(). + * @peer_db_read: See ntb_peer_db_read(). + * @peer_db_set: See ntb_peer_db_set(). + * @peer_db_clear: See ntb_peer_db_clear(). + * @peer_db_read_mask: See ntb_peer_db_read_mask(). + * @peer_db_set_mask: See ntb_peer_db_set_mask(). + * @peer_db_clear_mask: See ntb_peer_db_clear_mask(). + * @spad_is_unsafe: See ntb_spad_is_unsafe(). + * @spad_count: See ntb_spad_count(). + * @spad_read: See ntb_spad_read(). + * @spad_write: See ntb_spad_write(). + * @peer_spad_addr: See ntb_peer_spad_addr(). + * @peer_spad_read: See ntb_peer_spad_read(). + * @peer_spad_write: See ntb_peer_spad_write(). + */ +struct ntb_dev_ops { + int (*mw_count)(struct ntb_dev *ntb); + int (*mw_get_range)(struct ntb_dev *ntb, int idx, + phys_addr_t *base, resource_size_t *size, + resource_size_t *align, resource_size_t *align_size); + int (*mw_set_trans)(struct ntb_dev *ntb, int idx, + dma_addr_t addr, resource_size_t size); + int (*mw_clear_trans)(struct ntb_dev *ntb, int idx); + + int (*link_is_up)(struct ntb_dev *ntb, + enum ntb_speed *speed, enum ntb_width *width); + int (*link_enable)(struct ntb_dev *ntb, + enum ntb_speed max_speed, enum ntb_width max_width); + int (*link_disable)(struct ntb_dev *ntb); + + int (*db_is_unsafe)(struct ntb_dev *ntb); + u64 (*db_valid_mask)(struct ntb_dev *ntb); + int (*db_vector_count)(struct ntb_dev *ntb); + u64 (*db_vector_mask)(struct ntb_dev *ntb, int db_vector); + + u64 (*db_read)(struct ntb_dev *ntb); + int (*db_set)(struct ntb_dev *ntb, u64 db_bits); + int (*db_clear)(struct ntb_dev *ntb, u64 db_bits); + + u64 (*db_read_mask)(struct ntb_dev *ntb); + int (*db_set_mask)(struct ntb_dev *ntb, u64 db_bits); + int (*db_clear_mask)(struct ntb_dev *ntb, u64 db_bits); + + int (*peer_db_addr)(struct ntb_dev *ntb, + phys_addr_t *db_addr, resource_size_t *db_size); + u64 (*peer_db_read)(struct ntb_dev *ntb); + int (*peer_db_set)(struct ntb_dev *ntb, u64 db_bits); + int (*peer_db_clear)(struct ntb_dev *ntb, u64 db_bits); + + u64 (*peer_db_read_mask)(struct ntb_dev *ntb); + int (*peer_db_set_mask)(struct ntb_dev *ntb, u64 db_bits); + int (*peer_db_clear_mask)(struct ntb_dev *ntb, u64 db_bits); + + int (*spad_is_unsafe)(struct ntb_dev *ntb); + int (*spad_count)(struct ntb_dev *ntb); + + u32 (*spad_read)(struct ntb_dev *ntb, int idx); + int (*spad_write)(struct ntb_dev *ntb, int idx, u32 val); + + int (*peer_spad_addr)(struct ntb_dev *ntb, int idx, + phys_addr_t *spad_addr); + u32 (*peer_spad_read)(struct ntb_dev *ntb, int idx); + int (*peer_spad_write)(struct ntb_dev *ntb, int idx, u32 val); +}; + +static inline int ntb_dev_ops_is_valid(const struct ntb_dev_ops *ops) +{ + /* commented callbacks are not required: */ + return + ops->mw_count && + ops->mw_get_range && + ops->mw_set_trans && + /* ops->mw_clear_trans && */ + ops->link_is_up && + ops->link_enable && + ops->link_disable && + /* ops->db_is_unsafe && */ + ops->db_valid_mask && + + /* both set, or both unset */ + (!ops->db_vector_count == !ops->db_vector_mask) && + + ops->db_read && + /* ops->db_set && */ + ops->db_clear && + /* ops->db_read_mask && */ + ops->db_set_mask && + ops->db_clear_mask && + ops->peer_db_addr && + /* ops->peer_db_read && */ + ops->peer_db_set && + /* ops->peer_db_clear && */ + /* ops->peer_db_read_mask && */ + /* ops->peer_db_set_mask && */ + /* ops->peer_db_clear_mask && */ + /* ops->spad_is_unsafe && */ + ops->spad_count && + ops->spad_read && + ops->spad_write && + ops->peer_spad_addr && + /* ops->peer_spad_read && */ + ops->peer_spad_write && + 1; +} + +/** + * struct ntb_client - client interested in ntb devices + * @drv: Linux driver object. + * @ops: See &ntb_client_ops. + */ +struct ntb_client { + struct device_driver drv; + const struct ntb_client_ops ops; +}; + +#define drv_ntb_client(__drv) container_of((__drv), struct ntb_client, drv) + +/** + * struct ntb_device - ntb device + * @dev: Linux device object. + * @pdev: Pci device entry of the ntb. + * @topo: Detected topology of the ntb. + * @ops: See &ntb_dev_ops. + * @ctx: See &ntb_ctx_ops. + * @ctx_ops: See &ntb_ctx_ops. + */ +struct ntb_dev { + struct device dev; + struct pci_dev *pdev; + enum ntb_topo topo; + const struct ntb_dev_ops *ops; + void *ctx; + const struct ntb_ctx_ops *ctx_ops; + + /* private: */ + + /* synchronize setting, clearing, and calling ctx_ops */ + spinlock_t ctx_lock; + /* block unregister until device is fully released */ + struct completion released; +}; + +#define dev_ntb(__dev) container_of((__dev), struct ntb_dev, dev) + +/** + * ntb_register_client() - register a client for interest in ntb devices + * @client: Client context. + * + * The client will be added to the list of clients interested in ntb devices. + * The client will be notified of any ntb devices that are not already + * associated with a client, or if ntb devices are registered later. + * + * Return: Zero if the client is registered, otherwise an error number. + */ +#define ntb_register_client(client) \ + __ntb_register_client((client), THIS_MODULE, KBUILD_MODNAME) + +int __ntb_register_client(struct ntb_client *client, struct module *mod, + const char *mod_name); + +/** + * ntb_unregister_client() - unregister a client for interest in ntb devices + * @client: Client context. + * + * The client will be removed from the list of clients interested in ntb + * devices. If any ntb devices are associated with the client, the client will + * be notified to remove those devices. + */ +void ntb_unregister_client(struct ntb_client *client); + +#define module_ntb_client(__ntb_client) \ + module_driver(__ntb_client, ntb_register_client, \ + ntb_unregister_client) + +/** + * ntb_register_device() - register a ntb device + * @ntb: NTB device context. + * + * The device will be added to the list of ntb devices. If any clients are + * interested in ntb devices, each client will be notified of the ntb device, + * until at most one client accepts the device. + * + * Return: Zero if the device is registered, otherwise an error number. + */ +int ntb_register_device(struct ntb_dev *ntb); + +/** + * ntb_register_device() - unregister a ntb device + * @ntb: NTB device context. + * + * The device will be removed from the list of ntb devices. If the ntb device + * is associated with a client, the client will be notified to remove the + * device. + */ +void ntb_unregister_device(struct ntb_dev *ntb); + +/** + * ntb_set_ctx() - associate a driver context with an ntb device + * @ntb: NTB device context. + * @ctx: Driver context. + * @ctx_ops: Driver context operations. + * + * Associate a driver context and operations with a ntb device. The context is + * provided by the client driver, and the driver may associate a different + * context with each ntb device. + * + * Return: Zero if the context is associated, otherwise an error number. + */ +int ntb_set_ctx(struct ntb_dev *ntb, void *ctx, + const struct ntb_ctx_ops *ctx_ops); + +/** + * ntb_clear_ctx() - disassociate any driver context from an ntb device + * @ntb: NTB device context. + * + * Clear any association that may exist between a driver context and the ntb + * device. + */ +void ntb_clear_ctx(struct ntb_dev *ntb); + +/** + * ntb_link_event() - notify driver context of a change in link status + * @ntb: NTB device context. + * + * Notify the driver context that the link status may have changed. The driver + * should call ntb_link_is_up() to get the current status. + */ +void ntb_link_event(struct ntb_dev *ntb); + +/** + * ntb_db_event() - notify driver context of a doorbell event + * @ntb: NTB device context. + * @vector: Interrupt vector number. + * + * Notify the driver context of a doorbell event. If hardware supports + * multiple interrupt vectors for doorbells, the vector number indicates which + * vector received the interrupt. The vector number is relative to the first + * vector used for doorbells, starting at zero, and must be less than + ** ntb_db_vector_count(). The driver may call ntb_db_read() to check which + * doorbell bits need service, and ntb_db_vector_mask() to determine which of + * those bits are associated with the vector number. + */ +void ntb_db_event(struct ntb_dev *ntb, int vector); + +/** + * ntb_mw_count() - get the number of memory windows + * @ntb: NTB device context. + * + * Hardware and topology may support a different number of memory windows. + * + * Return: the number of memory windows. + */ +static inline int ntb_mw_count(struct ntb_dev *ntb) +{ + return ntb->ops->mw_count(ntb); +} + +/** + * ntb_mw_get_range() - get the range of a memory window + * @ntb: NTB device context. + * @idx: Memory window number. + * @base: OUT - the base address for mapping the memory window + * @size: OUT - the size for mapping the memory window + * @align: OUT - the base alignment for translating the memory window + * @align_size: OUT - the size alignment for translating the memory window + * + * Get the range of a memory window. NULL may be given for any output + * parameter if the value is not needed. The base and size may be used for + * mapping the memory window, to access the peer memory. The alignment and + * size may be used for translating the memory window, for the peer to access + * memory on the local system. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_mw_get_range(struct ntb_dev *ntb, int idx, + phys_addr_t *base, resource_size_t *size, + resource_size_t *align, resource_size_t *align_size) +{ + return ntb->ops->mw_get_range(ntb, idx, base, size, + align, align_size); +} + +/** + * ntb_mw_set_trans() - set the translation of a memory window + * @ntb: NTB device context. + * @idx: Memory window number. + * @addr: The dma address local memory to expose to the peer. + * @size: The size of the local memory to expose to the peer. + * + * Set the translation of a memory window. The peer may access local memory + * through the window starting at the address, up to the size. The address + * must be aligned to the alignment specified by ntb_mw_get_range(). The size + * must be aligned to the size alignment specified by ntb_mw_get_range(). + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_mw_set_trans(struct ntb_dev *ntb, int idx, + dma_addr_t addr, resource_size_t size) +{ + return ntb->ops->mw_set_trans(ntb, idx, addr, size); +} + +/** + * ntb_mw_clear_trans() - clear the translation of a memory window + * @ntb: NTB device context. + * @idx: Memory window number. + * + * Clear the translation of a memory window. The peer may no longer access + * local memory through the window. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_mw_clear_trans(struct ntb_dev *ntb, int idx) +{ + if (!ntb->ops->mw_clear_trans) + return ntb->ops->mw_set_trans(ntb, idx, 0, 0); + + return ntb->ops->mw_clear_trans(ntb, idx); +} + +/** + * ntb_link_is_up() - get the current ntb link state + * @ntb: NTB device context. + * @speed: OUT - The link speed expressed as PCIe generation number. + * @width: OUT - The link width expressed as the number of PCIe lanes. + * + * Set the translation of a memory window. The peer may access local memory + * through the window starting at the address, up to the size. The address + * must be aligned to the alignment specified by ntb_mw_get_range(). The size + * must be aligned to the size alignment specified by ntb_mw_get_range(). + * + * Return: One if the link is up, zero if the link is down, otherwise a + * negative value indicating the error number. + */ +static inline int ntb_link_is_up(struct ntb_dev *ntb, + enum ntb_speed *speed, enum ntb_width *width) +{ + return ntb->ops->link_is_up(ntb, speed, width); +} + +/** + * ntb_link_enable() - enable the link on the secondary side of the ntb + * @ntb: NTB device context. + * @max_speed: The maximum link speed expressed as PCIe generation number. + * @max_width: The maximum link width expressed as the number of PCIe lanes. + * + * Enable the link on the secondary side of the ntb. This can only be done + * from the primary side of the ntb in primary or b2b topology. The ntb device + * should train the link to its maximum speed and width, or the requested speed + * and width, whichever is smaller, if supported. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_link_enable(struct ntb_dev *ntb, + enum ntb_speed max_speed, + enum ntb_width max_width) +{ + return ntb->ops->link_enable(ntb, max_speed, max_width); +} + +/** + * ntb_link_disable() - disable the link on the secondary side of the ntb + * @ntb: NTB device context. + * + * Disable the link on the secondary side of the ntb. This can only be + * done from the primary side of the ntb in primary or b2b topology. The ntb + * device should disable the link. Returning from this call must indicate that + * a barrier has passed, though with no more writes may pass in either + * direction across the link, except if this call returns an error number. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_link_disable(struct ntb_dev *ntb) +{ + return ntb->ops->link_disable(ntb); +} + +/** + * ntb_db_is_unsafe() - check if it is safe to use hardware doorbell + * @ntb: NTB device context. + * + * It is possible for some ntb hardware to be affected by errata. Hardware + * drivers can advise clients to avoid using doorbells. Clients may ignore + * this advice, though caution is recommended. + * + * Return: Zero if it is safe to use doorbells, or One if it is not safe. + */ +static inline int ntb_db_is_unsafe(struct ntb_dev *ntb) +{ + if (!ntb->ops->db_is_unsafe) + return 0; + + return ntb->ops->db_is_unsafe(ntb); +} + +/** + * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb + * @ntb: NTB device context. + * + * Hardware may support different number or arrangement of doorbell bits. + * + * Return: A mask of doorbell bits supported by the ntb. + */ +static inline u64 ntb_db_valid_mask(struct ntb_dev *ntb) +{ + return ntb->ops->db_valid_mask(ntb); +} + +/** + * ntb_db_vector_count() - get the number of doorbell interrupt vectors + * @ntb: NTB device context. + * + * Hardware may support different number of interrupt vectors. + * + * Return: The number of doorbell interrupt vectors. + */ +static inline int ntb_db_vector_count(struct ntb_dev *ntb) +{ + if (!ntb->ops->db_vector_count) + return 1; + + return ntb->ops->db_vector_count(ntb); +} + +/** + * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector + * @ntb: NTB device context. + * @vector: Doorbell vector number. + * + * Each interrupt vector may have a different number or arrangement of bits. + * + * Return: A mask of doorbell bits serviced by a vector. + */ +static inline u64 ntb_db_vector_mask(struct ntb_dev *ntb, int vector) +{ + if (!ntb->ops->db_vector_mask) + return ntb_db_valid_mask(ntb); + + return ntb->ops->db_vector_mask(ntb, vector); +} + +/** + * ntb_db_read() - read the local doorbell register + * @ntb: NTB device context. + * + * Read the local doorbell register, and return the bits that are set. + * + * Return: The bits currently set in the local doorbell register. + */ +static inline u64 ntb_db_read(struct ntb_dev *ntb) +{ + return ntb->ops->db_read(ntb); +} + +/** + * ntb_db_set() - set bits in the local doorbell register + * @ntb: NTB device context. + * @db_bits: Doorbell bits to set. + * + * Set bits in the local doorbell register, which may generate a local doorbell + * interrupt. Bits that were already set must remain set. + * + * This is unusual, and hardware may not support it. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_db_set(struct ntb_dev *ntb, u64 db_bits) +{ + if (!ntb->ops->db_set) + return -EINVAL; + + return ntb->ops->db_set(ntb, db_bits); +} + +/** + * ntb_db_clear() - clear bits in the local doorbell register + * @ntb: NTB device context. + * @db_bits: Doorbell bits to clear. + * + * Clear bits in the local doorbell register, arming the bits for the next + * doorbell. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) +{ + return ntb->ops->db_clear(ntb, db_bits); +} + +/** + * ntb_db_read_mask() - read the local doorbell mask + * @ntb: NTB device context. + * + * Read the local doorbell mask register, and return the bits that are set. + * + * This is unusual, though hardware is likely to support it. + * + * Return: The bits currently set in the local doorbell mask register. + */ +static inline u64 ntb_db_read_mask(struct ntb_dev *ntb) +{ + if (!ntb->ops->db_read_mask) + return 0; + + return ntb->ops->db_read_mask(ntb); +} + +/** + * ntb_db_set_mask() - set bits in the local doorbell mask + * @ntb: NTB device context. + * @db_bits: Doorbell mask bits to set. + * + * Set bits in the local doorbell mask register, preventing doorbell interrupts + * from being generated for those doorbell bits. Bits that were already set + * must remain set. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) +{ + return ntb->ops->db_set_mask(ntb, db_bits); +} + +/** + * ntb_db_clear_mask() - clear bits in the local doorbell mask + * @ntb: NTB device context. + * @db_bits: Doorbell bits to clear. + * + * Clear bits in the local doorbell mask register, allowing doorbell interrupts + * from being generated for those doorbell bits. If a doorbell bit is already + * set at the time the mask is cleared, and the corresponding mask bit is + * changed from set to clear, then the ntb driver must ensure that + * ntb_db_event() is called. If the hardware does not generate the interrupt + * on clearing the mask bit, then the driver must call ntb_db_event() anyway. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) +{ + return ntb->ops->db_clear_mask(ntb, db_bits); +} + +/** + * ntb_peer_db_addr() - address and size of the peer doorbell register + * @ntb: NTB device context. + * @db_addr: OUT - The address of the peer doorbell register. + * @db_size: OUT - The number of bytes to write the peer doorbell register. + * + * Return the address of the peer doorbell register. This may be used, for + * example, by drivers that offload memory copy operations to a dma engine. + * The drivers may wish to ring the peer doorbell at the completion of memory + * copy operations. For efficiency, and to simplify ordering of operations + * between the dma memory copies and the ringing doorbell, the driver may + * append one additional dma memory copy with the doorbell register as the + * destination, after the memory copy operations. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_db_addr(struct ntb_dev *ntb, + phys_addr_t *db_addr, + resource_size_t *db_size) +{ + return ntb->ops->peer_db_addr(ntb, db_addr, db_size); +} + +/** + * ntb_peer_db_read() - read the peer doorbell register + * @ntb: NTB device context. + * + * Read the peer doorbell register, and return the bits that are set. + * + * This is unusual, and hardware may not support it. + * + * Return: The bits currently set in the peer doorbell register. + */ +static inline u64 ntb_peer_db_read(struct ntb_dev *ntb) +{ + if (!ntb->ops->peer_db_read) + return 0; + + return ntb->ops->peer_db_read(ntb); +} + +/** + * ntb_peer_db_set() - set bits in the peer doorbell register + * @ntb: NTB device context. + * @db_bits: Doorbell bits to set. + * + * Set bits in the peer doorbell register, which may generate a peer doorbell + * interrupt. Bits that were already set must remain set. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) +{ + return ntb->ops->peer_db_set(ntb, db_bits); +} + +/** + * ntb_peer_db_clear() - clear bits in the local doorbell register + * @ntb: NTB device context. + * @db_bits: Doorbell bits to clear. + * + * Clear bits in the peer doorbell register, arming the bits for the next + * doorbell. + * + * This is unusual, and hardware may not support it. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_db_clear(struct ntb_dev *ntb, u64 db_bits) +{ + if (!ntb->ops->db_clear) + return -EINVAL; + + return ntb->ops->peer_db_clear(ntb, db_bits); +} + +/** + * ntb_peer_db_read_mask() - read the peer doorbell mask + * @ntb: NTB device context. + * + * Read the peer doorbell mask register, and return the bits that are set. + * + * This is unusual, and hardware may not support it. + * + * Return: The bits currently set in the peer doorbell mask register. + */ +static inline u64 ntb_peer_db_read_mask(struct ntb_dev *ntb) +{ + if (!ntb->ops->db_read_mask) + return 0; + + return ntb->ops->peer_db_read_mask(ntb); +} + +/** + * ntb_peer_db_set_mask() - set bits in the peer doorbell mask + * @ntb: NTB device context. + * @db_bits: Doorbell mask bits to set. + * + * Set bits in the peer doorbell mask register, preventing doorbell interrupts + * from being generated for those doorbell bits. Bits that were already set + * must remain set. + * + * This is unusual, and hardware may not support it. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_db_set_mask(struct ntb_dev *ntb, u64 db_bits) +{ + if (!ntb->ops->db_set_mask) + return -EINVAL; + + return ntb->ops->peer_db_set_mask(ntb, db_bits); +} + +/** + * ntb_peer_db_clear_mask() - clear bits in the peer doorbell mask + * @ntb: NTB device context. + * @db_bits: Doorbell bits to clear. + * + * Clear bits in the peer doorbell mask register, allowing doorbell interrupts + * from being generated for those doorbell bits. If the hardware does not + * generate the interrupt on clearing the mask bit, then the driver should not + * implement this function! + * + * This is unusual, and hardware may not support it. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) +{ + if (!ntb->ops->db_clear_mask) + return -EINVAL; + + return ntb->ops->peer_db_clear_mask(ntb, db_bits); +} + +/** + * ntb_spad_is_unsafe() - check if it is safe to use the hardware scratchpads + * @ntb: NTB device context. + * + * It is possible for some ntb hardware to be affected by errata. Hardware + * drivers can advise clients to avoid using scratchpads. Clients may ignore + * this advice, though caution is recommended. + * + * Return: Zero if it is safe to use scratchpads, or One if it is not safe. + */ +static inline int ntb_spad_is_unsafe(struct ntb_dev *ntb) +{ + if (!ntb->ops->spad_is_unsafe) + return 0; + + return ntb->ops->spad_is_unsafe(ntb); +} + +/** + * ntb_mw_count() - get the number of scratchpads + * @ntb: NTB device context. + * + * Hardware and topology may support a different number of scratchpads. + * + * Return: the number of scratchpads. + */ +static inline int ntb_spad_count(struct ntb_dev *ntb) +{ + return ntb->ops->spad_count(ntb); +} + +/** + * ntb_spad_read() - read the local scratchpad register + * @ntb: NTB device context. + * @idx: Scratchpad index. + * + * Read the local scratchpad register, and return the value. + * + * Return: The value of the local scratchpad register. + */ +static inline u32 ntb_spad_read(struct ntb_dev *ntb, int idx) +{ + return ntb->ops->spad_read(ntb, idx); +} + +/** + * ntb_spad_write() - write the local scratchpad register + * @ntb: NTB device context. + * @idx: Scratchpad index. + * @val: Scratchpad value. + * + * Write the value to the local scratchpad register. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val) +{ + return ntb->ops->spad_write(ntb, idx, val); +} + +/** + * ntb_peer_spad_addr() - address of the peer scratchpad register + * @ntb: NTB device context. + * @idx: Scratchpad index. + * @spad_addr: OUT - The address of the peer scratchpad register. + * + * Return the address of the peer doorbell register. This may be used, for + * example, by drivers that offload memory copy operations to a dma engine. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_spad_addr(struct ntb_dev *ntb, int idx, + phys_addr_t *spad_addr) +{ + return ntb->ops->peer_spad_addr(ntb, idx, spad_addr); +} + +/** + * ntb_peer_spad_read() - read the peer scratchpad register + * @ntb: NTB device context. + * @idx: Scratchpad index. + * + * Read the peer scratchpad register, and return the value. + * + * Return: The value of the local scratchpad register. + */ +static inline u32 ntb_peer_spad_read(struct ntb_dev *ntb, int idx) +{ + return ntb->ops->peer_spad_read(ntb, idx); +} + +/** + * ntb_peer_spad_write() - write the peer scratchpad register + * @ntb: NTB device context. + * @idx: Scratchpad index. + * @val: Scratchpad value. + * + * Write the value to the peer scratchpad register. + * + * Return: Zero on success, otherwise an error number. + */ +static inline int ntb_peer_spad_write(struct ntb_dev *ntb, int idx, u32 val) +{ + return ntb->ops->peer_spad_write(ntb, idx, val); +} + +#endif -- cgit v1.2.3 From e26a5843f7f5014ae4460030ca4de029a3ac35d3 Mon Sep 17 00:00:00 2001 From: Allen Hubbe Date: Thu, 9 Apr 2015 10:33:20 -0400 Subject: NTB: Split ntb_hw_intel and ntb_transport drivers Change ntb_hw_intel to use the new NTB hardware abstraction layer. Split ntb_transport into its own driver. Change it to use the new NTB hardware abstraction layer. Signed-off-by: Allen Hubbe Signed-off-by: Jon Mason --- Documentation/ntb.txt | 26 + MAINTAINERS | 8 + drivers/net/ntb_netdev.c | 54 +- drivers/ntb/Kconfig | 37 +- drivers/ntb/Makefile | 6 +- drivers/ntb/hw/Kconfig | 1 + drivers/ntb/hw/Makefile | 1 + drivers/ntb/hw/intel/Kconfig | 7 + drivers/ntb/hw/intel/Makefile | 1 + drivers/ntb/hw/intel/ntb_hw_intel.c | 3075 +++++++++++++++++++---------------- drivers/ntb/hw/intel/ntb_hw_intel.h | 607 ++++--- drivers/ntb/ntb_transport.c | 936 ++++++----- include/linux/ntb_transport.h | 25 +- 13 files changed, 2589 insertions(+), 2195 deletions(-) create mode 100644 drivers/ntb/hw/Kconfig create mode 100644 drivers/ntb/hw/Makefile create mode 100644 drivers/ntb/hw/intel/Kconfig create mode 100644 drivers/ntb/hw/intel/Makefile (limited to 'Documentation') diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt index 9d46dc9712a8..725ba1e6c127 100644 --- a/Documentation/ntb.txt +++ b/Documentation/ntb.txt @@ -26,7 +26,33 @@ as ntb hardware, or hardware drivers, are inserted and removed. The registration uses the Linux Device framework, so it should feel familiar to anyone who has written a pci driver. +### NTB Transport Client (ntb\_transport) and NTB Netdev (ntb\_netdev) + +The primary client for NTB is the Transport client, used in tandem with NTB +Netdev. These drivers function together to create a logical link to the peer, +across the ntb, to exchange packets of network data. The Transport client +establishes a logical link to the peer, and creates queue pairs to exchange +messages and data. The NTB Netdev then creates an ethernet device using a +Transport queue pair. Network data is copied between socket buffers and the +Transport queue pair buffer. The Transport client may be used for other things +besides Netdev, however no other applications have yet been written. + ## NTB Hardware Drivers NTB hardware drivers should register devices with the NTB core driver. After registering, clients probe and remove functions will be called. + +### NTB Intel Hardware Driver (ntb\_hw\_intel) + +The Intel hardware driver supports NTB on Xeon and Atom CPUs. + +Module Parameters: + +* b2b\_mw\_idx - If the peer ntb is to be accessed via a memory window, then use + this memory window to access the peer ntb. A value of zero or positive + starts from the first mw idx, and a negative value starts from the last + mw idx. Both sides MUST set the same value here! The default value is + `-1`. +* b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if + the memory window is large enough, still allow the client to use the + second half of the memory window for address translation to the peer. diff --git a/MAINTAINERS b/MAINTAINERS index e2fc9eec2e16..a682805d6d56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7007,6 +7007,14 @@ F: drivers/net/ntb_netdev.c F: include/linux/ntb.h F: include/linux/ntb_transport.h +NTB INTEL DRIVER +M: Jon Mason +M: Dave Jiang +S: Supported +W: https://github.com/jonmason/ntb/wiki +T: git git://github.com/jonmason/ntb.git +F: drivers/ntb/hw/intel/ + NTFS FILESYSTEM M: Anton Altaparmakov L: linux-ntfs-dev@lists.sourceforge.net diff --git a/drivers/net/ntb_netdev.c b/drivers/net/ntb_netdev.c index 6d3bfa62f5ec..3cc316cb7e6b 100644 --- a/drivers/net/ntb_netdev.c +++ b/drivers/net/ntb_netdev.c @@ -5,6 +5,7 @@ * GPL LICENSE SUMMARY * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as @@ -13,6 +14,7 @@ * BSD LICENSE * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -40,7 +42,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Intel PCIe NTB Network Linux driver + * PCIe NTB Network Linux driver * * Contact Information: * Jon Mason @@ -49,6 +51,7 @@ #include #include #include +#include #include #define NTB_NETDEV_VER "0.7" @@ -70,26 +73,19 @@ struct ntb_netdev { static LIST_HEAD(dev_list); -static void ntb_netdev_event_handler(void *data, int status) +static void ntb_netdev_event_handler(void *data, int link_is_up) { struct net_device *ndev = data; struct ntb_netdev *dev = netdev_priv(ndev); - netdev_dbg(ndev, "Event %x, Link %x\n", status, + netdev_dbg(ndev, "Event %x, Link %x\n", link_is_up, ntb_transport_link_query(dev->qp)); - switch (status) { - case NTB_LINK_DOWN: + if (link_is_up) { + if (ntb_transport_link_query(dev->qp)) + netif_carrier_on(ndev); + } else { netif_carrier_off(ndev); - break; - case NTB_LINK_UP: - if (!ntb_transport_link_query(dev->qp)) - return; - - netif_carrier_on(ndev); - break; - default: - netdev_warn(ndev, "Unsupported event type %d\n", status); } } @@ -160,8 +156,6 @@ static netdev_tx_t ntb_netdev_start_xmit(struct sk_buff *skb, struct ntb_netdev *dev = netdev_priv(ndev); int rc; - netdev_dbg(ndev, "%s: skb len %d\n", __func__, skb->len); - rc = ntb_transport_tx_enqueue(dev->qp, skb, skb->data, skb->len); if (rc) goto err; @@ -322,20 +316,26 @@ static const struct ntb_queue_handlers ntb_netdev_handlers = { .event_handler = ntb_netdev_event_handler, }; -static int ntb_netdev_probe(struct pci_dev *pdev) +static int ntb_netdev_probe(struct device *client_dev) { + struct ntb_dev *ntb; struct net_device *ndev; + struct pci_dev *pdev; struct ntb_netdev *dev; int rc; - ndev = alloc_etherdev(sizeof(struct ntb_netdev)); + ntb = dev_ntb(client_dev->parent); + pdev = ntb->pdev; + if (!pdev) + return -ENODEV; + + ndev = alloc_etherdev(sizeof(*dev)); if (!ndev) return -ENOMEM; dev = netdev_priv(ndev); dev->ndev = ndev; dev->pdev = pdev; - BUG_ON(!dev->pdev); ndev->features = NETIF_F_HIGHDMA; ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; @@ -349,7 +349,8 @@ static int ntb_netdev_probe(struct pci_dev *pdev) ndev->netdev_ops = &ntb_netdev_ops; ndev->ethtool_ops = &ntb_ethtool_ops; - dev->qp = ntb_transport_create_queue(ndev, pdev, &ntb_netdev_handlers); + dev->qp = ntb_transport_create_queue(ndev, client_dev, + &ntb_netdev_handlers); if (!dev->qp) { rc = -EIO; goto err; @@ -372,12 +373,17 @@ err: return rc; } -static void ntb_netdev_remove(struct pci_dev *pdev) +static void ntb_netdev_remove(struct device *client_dev) { + struct ntb_dev *ntb; struct net_device *ndev; + struct pci_dev *pdev; struct ntb_netdev *dev; bool found = false; + ntb = dev_ntb(client_dev->parent); + pdev = ntb->pdev; + list_for_each_entry(dev, &dev_list, list) { if (dev->pdev == pdev) { found = true; @@ -396,7 +402,7 @@ static void ntb_netdev_remove(struct pci_dev *pdev) free_netdev(ndev); } -static struct ntb_client ntb_netdev_client = { +static struct ntb_transport_client ntb_netdev_client = { .driver.name = KBUILD_MODNAME, .driver.owner = THIS_MODULE, .probe = ntb_netdev_probe, @@ -407,7 +413,7 @@ static int __init ntb_netdev_init_module(void) { int rc; - rc = ntb_register_client_dev(KBUILD_MODNAME); + rc = ntb_transport_register_client_dev(KBUILD_MODNAME); if (rc) return rc; return ntb_transport_register_client(&ntb_netdev_client); @@ -417,6 +423,6 @@ module_init(ntb_netdev_init_module); static void __exit ntb_netdev_exit_module(void) { ntb_transport_unregister_client(&ntb_netdev_client); - ntb_unregister_client_dev(KBUILD_MODNAME); + ntb_transport_unregister_client_dev(KBUILD_MODNAME); } module_exit(ntb_netdev_exit_module); diff --git a/drivers/ntb/Kconfig b/drivers/ntb/Kconfig index f69df793dbe2..53b042429673 100644 --- a/drivers/ntb/Kconfig +++ b/drivers/ntb/Kconfig @@ -1,13 +1,26 @@ -config NTB - tristate "Intel Non-Transparent Bridge support" - depends on PCI - depends on X86 - help - The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus - connecting 2 systems. When configured, writes to the device's PCI - mapped memory will be mirrored to a buffer on the remote system. The - ntb Linux driver uses this point-to-point communication as a method to - transfer data from one system to the other. - - If unsure, say N. +menuconfig NTB + tristate "Non-Transparent Bridge support" + depends on PCI + help + The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus + connecting 2 systems. When configured, writes to the device's PCI + mapped memory will be mirrored to a buffer on the remote system. The + ntb Linux driver uses this point-to-point communication as a method to + transfer data from one system to the other. + If unsure, say N. + +if NTB + +source "drivers/ntb/hw/Kconfig" + +config NTB_TRANSPORT + tristate "NTB Transport Client" + help + This is a transport driver that enables connected systems to exchange + messages over the ntb hardware. The transport exposes a queue pair api + to client drivers. + + If unsure, say N. + +endif # NTB diff --git a/drivers/ntb/Makefile b/drivers/ntb/Makefile index 712e953a8fda..b9fa663ecfec 100644 --- a/drivers/ntb/Makefile +++ b/drivers/ntb/Makefile @@ -1,4 +1,2 @@ -obj-$(CONFIG_NTB) += ntb.o -obj-$(CONFIG_NTB) += ntb_hw_intel.o - -ntb_hw_intel-objs := hw/intel/ntb_hw_intel.o ntb_transport.o +obj-$(CONFIG_NTB) += ntb.o hw/ +obj-$(CONFIG_NTB_TRANSPORT) += ntb_transport.o diff --git a/drivers/ntb/hw/Kconfig b/drivers/ntb/hw/Kconfig new file mode 100644 index 000000000000..4d5535c4cddf --- /dev/null +++ b/drivers/ntb/hw/Kconfig @@ -0,0 +1 @@ +source "drivers/ntb/hw/intel/Kconfig" diff --git a/drivers/ntb/hw/Makefile b/drivers/ntb/hw/Makefile new file mode 100644 index 000000000000..175d7c92a569 --- /dev/null +++ b/drivers/ntb/hw/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_NTB_INTEL) += intel/ diff --git a/drivers/ntb/hw/intel/Kconfig b/drivers/ntb/hw/intel/Kconfig new file mode 100644 index 000000000000..91f995e33ac6 --- /dev/null +++ b/drivers/ntb/hw/intel/Kconfig @@ -0,0 +1,7 @@ +config NTB_INTEL + tristate "Intel Non-Transparent Bridge support" + depends on X86_64 + help + This driver supports Intel NTB on capable Xeon and Atom hardware. + + If unsure, say N. diff --git a/drivers/ntb/hw/intel/Makefile b/drivers/ntb/hw/intel/Makefile new file mode 100644 index 000000000000..1b434568d2ad --- /dev/null +++ b/drivers/ntb/hw/intel/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_NTB_INTEL) += ntb_hw_intel.o diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index 044534a995f1..686091756ba4 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c @@ -5,6 +5,7 @@ * GPL LICENSE SUMMARY * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as @@ -13,6 +14,7 @@ * BSD LICENSE * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +47,7 @@ * Contact Information: * Jon Mason */ + #include #include #include @@ -53,99 +56,97 @@ #include #include #include +#include + #include "ntb_hw_intel.h" -#define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver" -#define NTB_VER "1.0" +#define NTB_NAME "ntb_hw_intel" +#define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver" +#define NTB_VER "2.0" -MODULE_DESCRIPTION(NTB_NAME); +MODULE_DESCRIPTION(NTB_DESC); MODULE_VERSION(NTB_VER); MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR("Intel Corporation"); -enum { - NTB_CONN_TRANSPARENT = 0, - NTB_CONN_B2B, - NTB_CONN_RP, -}; - -enum { - NTB_DEV_USD = 0, - NTB_DEV_DSD, -}; - -enum { - SNB_HW = 0, - BWD_HW, -}; - +#define bar0_off(base, bar) ((base) + ((bar) << 2)) +#define bar2_off(base, bar) bar0_off(base, (bar) - 2) + +static int b2b_mw_idx = -1; +module_param(b2b_mw_idx, int, 0644); +MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A " + "value of zero or positive starts from first mw idx, and a " + "negative value starts from last mw idx. Both sides MUST " + "set the same value here!"); + +static unsigned int b2b_mw_share; +module_param(b2b_mw_share, uint, 0644); +MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " + "ntb so that the peer ntb only occupies the first half of " + "the mw, so the second half can still be used as a mw. Both " + "sides MUST set the same value here!"); + +static const struct intel_ntb_reg bwd_reg; +static const struct intel_ntb_alt_reg bwd_pri_reg; +static const struct intel_ntb_alt_reg bwd_sec_reg; +static const struct intel_ntb_alt_reg bwd_b2b_reg; +static const struct intel_ntb_xlat_reg bwd_pri_xlat; +static const struct intel_ntb_xlat_reg bwd_sec_xlat; +static const struct intel_ntb_reg snb_reg; +static const struct intel_ntb_alt_reg snb_pri_reg; +static const struct intel_ntb_alt_reg snb_sec_reg; +static const struct intel_ntb_alt_reg snb_b2b_reg; +static const struct intel_ntb_xlat_reg snb_pri_xlat; +static const struct intel_ntb_xlat_reg snb_sec_xlat; +static const struct intel_b2b_addr snb_b2b_usd_addr; +static const struct intel_b2b_addr snb_b2b_dsd_addr; + +static const struct ntb_dev_ops intel_ntb_ops; + +static const struct file_operations intel_ntb_debugfs_info; static struct dentry *debugfs_dir; -#define BWD_LINK_RECOVERY_TIME 500 - -/* Translate memory window 0,1,2 to BAR 2,4,5 */ -#define MW_TO_BAR(mw) (mw == 0 ? 2 : (mw == 1 ? 4 : 5)) - -static const struct pci_device_id ntb_pci_tbl[] = { - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)}, - {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)}, - {0} -}; -MODULE_DEVICE_TABLE(pci, ntb_pci_tbl); - -static int is_ntb_xeon(struct ntb_device *ndev) +#ifndef ioread64 +#ifdef readq +#define ioread64 readq +#else +#define ioread64 _ioread64 +static inline u64 _ioread64(void __iomem *mmio) { - switch (ndev->pdev->device) { - case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: - case PCI_DEVICE_ID_INTEL_NTB_SS_SNB: - case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: - case PCI_DEVICE_ID_INTEL_NTB_SS_HSX: - case PCI_DEVICE_ID_INTEL_NTB_PS_JSF: - case PCI_DEVICE_ID_INTEL_NTB_PS_SNB: - case PCI_DEVICE_ID_INTEL_NTB_PS_IVT: - case PCI_DEVICE_ID_INTEL_NTB_PS_HSX: - case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF: - case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB: - case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: - case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: - return 1; - default: - return 0; - } + u64 low, high; - return 0; + low = ioread32(mmio); + high = ioread32(mmio + sizeof(u32)); + return low | (high << 32); +} +#endif +#endif + +#ifndef iowrite64 +#ifdef writeq +#define iowrite64 writeq +#else +#define iowrite64 _iowrite64 +static inline void _iowrite64(u64 val, void __iomem *mmio) +{ + iowrite32(val, mmio); + iowrite32(val >> 32, mmio + sizeof(u32)); } +#endif +#endif -static int is_ntb_atom(struct ntb_device *ndev) +static inline int pdev_is_bwd(struct pci_dev *pdev) { - switch (ndev->pdev->device) { + switch (pdev->device) { case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD: return 1; - default: - return 0; } - return 0; } -static void ntb_set_errata_flags(struct ntb_device *ndev) +static inline int pdev_is_snb(struct pci_dev *pdev) { - switch (ndev->pdev->device) { - /* - * this workaround applies to all platform up to IvyBridge - * Haswell has splitbar support and use a different workaround - */ + switch (pdev->device) { case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: case PCI_DEVICE_ID_INTEL_NTB_SS_SNB: case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: @@ -158,1737 +159,1957 @@ static void ntb_set_errata_flags(struct ntb_device *ndev) case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB: case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: - ndev->wa_flags |= WA_SNB_ERR; - break; + return 1; } + return 0; } -/** - * ntb_register_event_callback() - register event callback - * @ndev: pointer to ntb_device instance - * @func: callback function to register - * - * This function registers a callback for any HW driver events such as link - * up/down, power management notices and etc. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int ntb_register_event_callback(struct ntb_device *ndev, - void (*func)(void *handle, - enum ntb_hw_event event)) +static inline void ndev_reset_unsafe_flags(struct intel_ntb_dev *ndev) { - if (ndev->event_cb) - return -EINVAL; - - ndev->event_cb = func; - - return 0; + ndev->unsafe_flags = 0; + ndev->unsafe_flags_ignore = 0; + + /* Only B2B has a workaround to avoid SDOORBELL */ + if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) + if (!ntb_topo_is_b2b(ndev->ntb.topo)) + ndev->unsafe_flags |= NTB_UNSAFE_DB; + + /* No low level workaround to avoid SB01BASE */ + if (ndev->hwerr_flags & NTB_HWERR_SB01BASE_LOCKUP) { + ndev->unsafe_flags |= NTB_UNSAFE_DB; + ndev->unsafe_flags |= NTB_UNSAFE_SPAD; + } } -/** - * ntb_unregister_event_callback() - unregisters the event callback - * @ndev: pointer to ntb_device instance - * - * This function unregisters the existing callback from transport - */ -void ntb_unregister_event_callback(struct ntb_device *ndev) +static inline int ndev_is_unsafe(struct intel_ntb_dev *ndev, + unsigned long flag) { - ndev->event_cb = NULL; + return !!(flag & ndev->unsafe_flags & ~ndev->unsafe_flags_ignore); } -static void ntb_irq_work(unsigned long data) +static inline int ndev_ignore_unsafe(struct intel_ntb_dev *ndev, + unsigned long flag) { - struct ntb_db_cb *db_cb = (struct ntb_db_cb *)data; - int rc; + flag &= ndev->unsafe_flags; + ndev->unsafe_flags_ignore |= flag; - rc = db_cb->callback(db_cb->data, db_cb->db_num); - if (rc) - tasklet_schedule(&db_cb->irq_work); - else { - struct ntb_device *ndev = db_cb->ndev; - unsigned long mask; - - mask = readw(ndev->reg_ofs.ldb_mask); - clear_bit(db_cb->db_num * ndev->bits_per_vector, &mask); - writew(mask, ndev->reg_ofs.ldb_mask); - } + return !!flag; } -/** - * ntb_register_db_callback() - register a callback for doorbell interrupt - * @ndev: pointer to ntb_device instance - * @idx: doorbell index to register callback, zero based - * @data: pointer to be returned to caller with every callback - * @func: callback function to register - * - * This function registers a callback function for the doorbell interrupt - * on the primary side. The function will unmask the doorbell as well to - * allow interrupt. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx, - void *data, int (*func)(void *data, int db_num)) +static int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx) { - unsigned long mask; - - if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) { - dev_warn(&ndev->pdev->dev, "Invalid Index.\n"); + if (idx < 0 || idx > ndev->mw_count) return -EINVAL; - } + return ndev->reg->mw_bar[idx]; +} - ndev->db_cb[idx].callback = func; - ndev->db_cb[idx].data = data; - ndev->db_cb[idx].ndev = ndev; +static inline int ndev_db_addr(struct intel_ntb_dev *ndev, + phys_addr_t *db_addr, resource_size_t *db_size, + phys_addr_t reg_addr, unsigned long reg) +{ + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_DB)); - tasklet_init(&ndev->db_cb[idx].irq_work, ntb_irq_work, - (unsigned long) &ndev->db_cb[idx]); + if (db_addr) { + *db_addr = reg_addr + reg; + dev_dbg(ndev_dev(ndev), "Peer db addr %llx\n", *db_addr); + } - /* unmask interrupt */ - mask = readw(ndev->reg_ofs.ldb_mask); - clear_bit(idx * ndev->bits_per_vector, &mask); - writew(mask, ndev->reg_ofs.ldb_mask); + if (db_size) { + *db_size = ndev->reg->db_size; + dev_dbg(ndev_dev(ndev), "Peer db size %llx\n", *db_size); + } return 0; } -/** - * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt - * @ndev: pointer to ntb_device instance - * @idx: doorbell index to register callback, zero based - * - * This function unregisters a callback function for the doorbell interrupt - * on the primary side. The function will also mask the said doorbell. - */ -void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx) +static inline u64 ndev_db_read(struct intel_ntb_dev *ndev, + void __iomem *mmio) { - unsigned long mask; + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_DB)); - if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback) - return; + return ndev->reg->db_ioread(mmio); +} + +static inline int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits, + void __iomem *mmio) +{ + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_DB)); - mask = readw(ndev->reg_ofs.ldb_mask); - set_bit(idx * ndev->bits_per_vector, &mask); - writew(mask, ndev->reg_ofs.ldb_mask); + if (db_bits & ~ndev->db_valid_mask) + return -EINVAL; - tasklet_disable(&ndev->db_cb[idx].irq_work); + ndev->reg->db_iowrite(db_bits, mmio); - ndev->db_cb[idx].callback = NULL; + return 0; } -/** - * ntb_find_transport() - find the transport pointer - * @transport: pointer to pci device - * - * Given the pci device pointer, return the transport pointer passed in when - * the transport attached when it was inited. - * - * RETURNS: pointer to transport. - */ -void *ntb_find_transport(struct pci_dev *pdev) +static inline int ndev_db_set_mask(struct intel_ntb_dev *ndev, u64 db_bits, + void __iomem *mmio) { - struct ntb_device *ndev = pci_get_drvdata(pdev); - return ndev->ntb_transport; -} + unsigned long irqflags; -/** - * ntb_register_transport() - Register NTB transport with NTB HW driver - * @transport: transport identifier - * - * This function allows a transport to reserve the hardware driver for - * NTB usage. - * - * RETURNS: pointer to ntb_device, NULL on error. - */ -struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport) -{ - struct ntb_device *ndev = pci_get_drvdata(pdev); + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_DB)); + + if (db_bits & ~ndev->db_valid_mask) + return -EINVAL; - if (ndev->ntb_transport) - return NULL; + spin_lock_irqsave(&ndev->db_mask_lock, irqflags); + { + ndev->db_mask |= db_bits; + ndev->reg->db_iowrite(ndev->db_mask, mmio); + } + spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags); - ndev->ntb_transport = transport; - return ndev; + return 0; } -/** - * ntb_unregister_transport() - Unregister the transport with the NTB HW driver - * @ndev - ntb_device of the transport to be freed - * - * This function unregisters the transport from the HW driver and performs any - * necessary cleanups. - */ -void ntb_unregister_transport(struct ntb_device *ndev) +static inline int ndev_db_clear_mask(struct intel_ntb_dev *ndev, u64 db_bits, + void __iomem *mmio) { - int i; + unsigned long irqflags; - if (!ndev->ntb_transport) - return; + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_DB)); + + if (db_bits & ~ndev->db_valid_mask) + return -EINVAL; - for (i = 0; i < ndev->max_cbs; i++) - ntb_unregister_db_callback(ndev, i); + spin_lock_irqsave(&ndev->db_mask_lock, irqflags); + { + ndev->db_mask &= ~db_bits; + ndev->reg->db_iowrite(ndev->db_mask, mmio); + } + spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags); - ntb_unregister_event_callback(ndev); - ndev->ntb_transport = NULL; + return 0; } -/** - * ntb_write_local_spad() - write to the secondary scratchpad register - * @ndev: pointer to ntb_device instance - * @idx: index to the scratchpad register, 0 based - * @val: the data value to put into the register - * - * This function allows writing of a 32bit value to the indexed scratchpad - * register. This writes over the data mirrored to the local scratchpad register - * by the remote system. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val) +static inline int ndev_vec_mask(struct intel_ntb_dev *ndev, int db_vector) { - if (idx >= ndev->limits.max_spads) - return -EINVAL; + u64 shift, mask; - dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n", - val, idx); - writel(val, ndev->reg_ofs.spad_read + idx * 4); + shift = ndev->db_vec_shift; + mask = BIT_ULL(shift) - 1; - return 0; + return mask << (shift * db_vector); } -/** - * ntb_read_local_spad() - read from the primary scratchpad register - * @ndev: pointer to ntb_device instance - * @idx: index to scratchpad register, 0 based - * @val: pointer to 32bit integer for storing the register value - * - * This function allows reading of the 32bit scratchpad register on - * the primary (internal) side. This allows the local system to read data - * written and mirrored to the scratchpad register by the remote system. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val) +static inline int ndev_spad_addr(struct intel_ntb_dev *ndev, int idx, + phys_addr_t *spad_addr, phys_addr_t reg_addr, + unsigned long reg) { - if (idx >= ndev->limits.max_spads) + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD)); + + if (idx < 0 || idx >= ndev->spad_count) return -EINVAL; - *val = readl(ndev->reg_ofs.spad_write + idx * 4); - dev_dbg(&ndev->pdev->dev, - "Reading %x from local scratch pad index %d\n", *val, idx); + if (spad_addr) { + *spad_addr = reg_addr + reg + (idx << 2); + dev_dbg(ndev_dev(ndev), "Peer spad addr %llx\n", *spad_addr); + } return 0; } -/** - * ntb_write_remote_spad() - write to the secondary scratchpad register - * @ndev: pointer to ntb_device instance - * @idx: index to the scratchpad register, 0 based - * @val: the data value to put into the register - * - * This function allows writing of a 32bit value to the indexed scratchpad - * register. The register resides on the secondary (external) side. This allows - * the local system to write data to be mirrored to the remote systems - * scratchpad register. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val) +static inline u32 ndev_spad_read(struct intel_ntb_dev *ndev, int idx, + void __iomem *mmio) { - if (idx >= ndev->limits.max_spads) - return -EINVAL; + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD)); - dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n", - val, idx); - writel(val, ndev->reg_ofs.spad_write + idx * 4); + if (idx < 0 || idx >= ndev->spad_count) + return 0; - return 0; + return ioread32(mmio + (idx << 2)); } -/** - * ntb_read_remote_spad() - read from the primary scratchpad register - * @ndev: pointer to ntb_device instance - * @idx: index to scratchpad register, 0 based - * @val: pointer to 32bit integer for storing the register value - * - * This function allows reading of the 32bit scratchpad register on - * the primary (internal) side. This alloows the local system to read the data - * it wrote to be mirrored on the remote system. - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val) +static inline int ndev_spad_write(struct intel_ntb_dev *ndev, int idx, u32 val, + void __iomem *mmio) { - if (idx >= ndev->limits.max_spads) + WARN_ON_ONCE(ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD)); + + if (idx < 0 || idx >= ndev->spad_count) return -EINVAL; - *val = readl(ndev->reg_ofs.spad_read + idx * 4); - dev_dbg(&ndev->pdev->dev, - "Reading %x from remote scratch pad index %d\n", *val, idx); + iowrite32(val, mmio + (idx << 2)); return 0; } -/** - * ntb_get_mw_base() - get addr for the NTB memory window - * @ndev: pointer to ntb_device instance - * @mw: memory window number - * - * This function provides the base address of the memory window specified. - * - * RETURNS: address, or NULL on error. - */ -resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw) +static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec) { - if (mw >= ntb_max_mw(ndev)) - return 0; + u64 vec_mask; + + vec_mask = ndev_vec_mask(ndev, vec); + + dev_dbg(ndev_dev(ndev), "vec %d vec_mask %llx\n", vec, vec_mask); - return pci_resource_start(ndev->pdev, MW_TO_BAR(mw)); + ndev->last_ts = jiffies; + + if (vec_mask & ndev->db_link_mask) { + if (ndev->reg->poll_link(ndev)) + ntb_link_event(&ndev->ntb); + } + + if (vec_mask & ndev->db_valid_mask) + ntb_db_event(&ndev->ntb, vec); + + return IRQ_HANDLED; } -/** - * ntb_get_mw_vbase() - get virtual addr for the NTB memory window - * @ndev: pointer to ntb_device instance - * @mw: memory window number - * - * This function provides the base virtual address of the memory window - * specified. - * - * RETURNS: pointer to virtual address, or NULL on error. - */ -void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw) +static irqreturn_t ndev_vec_isr(int irq, void *dev) { - if (mw >= ntb_max_mw(ndev)) - return NULL; + struct intel_ntb_vec *nvec = dev; - return ndev->mw[mw].vbase; + return ndev_interrupt(nvec->ndev, nvec->num); } -/** - * ntb_get_mw_size() - return size of NTB memory window - * @ndev: pointer to ntb_device instance - * @mw: memory window number - * - * This function provides the physical size of the memory window specified - * - * RETURNS: the size of the memory window or zero on error - */ -u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw) +static irqreturn_t ndev_irq_isr(int irq, void *dev) { - if (mw >= ntb_max_mw(ndev)) - return 0; + struct intel_ntb_dev *ndev = dev; - return ndev->mw[mw].bar_sz; + return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq); } -/** - * ntb_set_mw_addr - set the memory window address - * @ndev: pointer to ntb_device instance - * @mw: memory window number - * @addr: base address for data - * - * This function sets the base physical address of the memory window. This - * memory address is where data from the remote system will be transfered into - * or out of depending on how the transport is configured. - */ -void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr) +static int ndev_init_isr(struct intel_ntb_dev *ndev, + int msix_min, int msix_max, + int msix_shift, int total_shift) { - if (mw >= ntb_max_mw(ndev)) - return; + struct pci_dev *pdev; + int rc, i, msix_count; - dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr, - MW_TO_BAR(mw)); + pdev = ndev_pdev(ndev); - ndev->mw[mw].phys_addr = addr; + /* Mask all doorbell interrupts */ + ndev->db_mask = ndev->db_valid_mask; + ndev->reg->db_iowrite(ndev->db_mask, + ndev->self_mmio + + ndev->self_reg->db_mask); - switch (MW_TO_BAR(mw)) { - case NTB_BAR_23: - writeq(addr, ndev->reg_ofs.bar2_xlat); - break; - case NTB_BAR_4: - if (ndev->split_bar) - writel(addr, ndev->reg_ofs.bar4_xlat); - else - writeq(addr, ndev->reg_ofs.bar4_xlat); - break; - case NTB_BAR_5: - writel(addr, ndev->reg_ofs.bar5_xlat); - break; + /* Try to set up msix irq */ + + ndev->vec = kcalloc(msix_max, sizeof(*ndev->vec), GFP_KERNEL); + if (!ndev->vec) + goto err_msix_vec_alloc; + + ndev->msix = kcalloc(msix_max, sizeof(*ndev->msix), GFP_KERNEL); + if (!ndev->msix) + goto err_msix_alloc; + + for (i = 0; i < msix_max; ++i) + ndev->msix[i].entry = i; + + msix_count = pci_enable_msix_range(pdev, ndev->msix, + msix_min, msix_max); + if (msix_count < 0) + goto err_msix_enable; + + for (i = 0; i < msix_count; ++i) { + ndev->vec[i].ndev = ndev; + ndev->vec[i].num = i; + rc = request_irq(ndev->msix[i].vector, ndev_vec_isr, 0, + "ndev_vec_isr", &ndev->vec[i]); + if (rc) + goto err_msix_request; } -} -/** - * ntb_ring_doorbell() - Set the doorbell on the secondary/external side - * @ndev: pointer to ntb_device instance - * @db: doorbell to ring - * - * This function allows triggering of a doorbell on the secondary/external - * side that will initiate an interrupt on the remote host - * - * RETURNS: An appropriate -ERRNO error value on error, or zero for success. - */ -void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db) -{ - dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db); + dev_dbg(ndev_dev(ndev), "Using msix interrupts\n"); + ndev->db_vec_count = msix_count; + ndev->db_vec_shift = msix_shift; + return 0; - if (ndev->hw_type == BWD_HW) - writeq((u64) 1 << db, ndev->reg_ofs.rdb); - else - writew(((1 << ndev->bits_per_vector) - 1) << - (db * ndev->bits_per_vector), ndev->reg_ofs.rdb); -} +err_msix_request: + while (i-- > 0) + free_irq(ndev->msix[i].vector, ndev); + pci_disable_msix(pdev); +err_msix_enable: + kfree(ndev->msix); +err_msix_alloc: + kfree(ndev->vec); +err_msix_vec_alloc: + ndev->msix = NULL; + ndev->vec = NULL; -static void bwd_recover_link(struct ntb_device *ndev) -{ - u32 status; + /* Try to set up msi irq */ - /* Driver resets the NTB ModPhy lanes - magic! */ - writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6); - writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4); - writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4); - writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6); + rc = pci_enable_msi(pdev); + if (rc) + goto err_msi_enable; - /* Driver waits 100ms to allow the NTB ModPhy to settle */ - msleep(100); + rc = request_irq(pdev->irq, ndev_irq_isr, 0, + "ndev_irq_isr", ndev); + if (rc) + goto err_msi_request; - /* Clear AER Errors, write to clear */ - status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET); - dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status); - status &= PCI_ERR_COR_REP_ROLL; - writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET); + dev_dbg(ndev_dev(ndev), "Using msi interrupts\n"); + ndev->db_vec_count = 1; + ndev->db_vec_shift = total_shift; + return 0; - /* Clear unexpected electrical idle event in LTSSM, write to clear */ - status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET); - dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status); - status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI; - writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET); +err_msi_request: + pci_disable_msi(pdev); +err_msi_enable: - /* Clear DeSkew Buffer error, write to clear */ - status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET); - dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status); - status |= BWD_DESKEWSTS_DBERR; - writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET); + /* Try to set up intx irq */ - status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET); - dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status); - status &= BWD_IBIST_ERR_OFLOW; - writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET); + pci_intx(pdev, 1); - /* Releases the NTB state machine to allow the link to retrain */ - status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET); - dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status); - status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT; - writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET); + rc = request_irq(pdev->irq, ndev_irq_isr, IRQF_SHARED, + "ndev_irq_isr", ndev); + if (rc) + goto err_intx_request; + + dev_dbg(ndev_dev(ndev), "Using intx interrupts\n"); + ndev->db_vec_count = 1; + ndev->db_vec_shift = total_shift; + return 0; + +err_intx_request: + return rc; } -static void ntb_link_event(struct ntb_device *ndev, int link_state) +static void ndev_deinit_isr(struct intel_ntb_dev *ndev) { - unsigned int event; + struct pci_dev *pdev; + int i; - if (ndev->link_status == link_state) - return; + pdev = ndev_pdev(ndev); - if (link_state == NTB_LINK_UP) { - u16 status; - - dev_info(&ndev->pdev->dev, "Link Up\n"); - ndev->link_status = NTB_LINK_UP; - event = NTB_EVENT_HW_LINK_UP; - - if (is_ntb_atom(ndev) || - ndev->conn_type == NTB_CONN_TRANSPARENT) - status = readw(ndev->reg_ofs.lnk_stat); - else { - int rc = pci_read_config_word(ndev->pdev, - SNB_LINK_STATUS_OFFSET, - &status); - if (rc) - return; - } + /* Mask all doorbell interrupts */ + ndev->db_mask = ndev->db_valid_mask; + ndev->reg->db_iowrite(ndev->db_mask, + ndev->self_mmio + + ndev->self_reg->db_mask); - ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4; - ndev->link_speed = (status & NTB_LINK_SPEED_MASK); - dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n", - ndev->link_width, ndev->link_speed); + if (ndev->msix) { + i = ndev->db_vec_count; + while (i--) + free_irq(ndev->msix[i].vector, &ndev->vec[i]); + pci_disable_msix(pdev); + kfree(ndev->msix); + kfree(ndev->vec); } else { - dev_info(&ndev->pdev->dev, "Link Down\n"); - ndev->link_status = NTB_LINK_DOWN; - event = NTB_EVENT_HW_LINK_DOWN; - /* Don't modify link width/speed, we need it in link recovery */ + free_irq(pdev->irq, ndev); + if (pci_dev_msi_enabled(pdev)) + pci_disable_msi(pdev); } - - /* notify the upper layer if we have an event change */ - if (ndev->event_cb) - ndev->event_cb(ndev->ntb_transport, event); } -static int ntb_link_status(struct ntb_device *ndev) +static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, + size_t count, loff_t *offp) { - int link_state; + struct intel_ntb_dev *ndev; + void __iomem *mmio; + char *buf; + size_t buf_size; + ssize_t ret, off; + union { u64 v64; u32 v32; u16 v16; } u; - if (is_ntb_atom(ndev)) { - u32 ntb_cntl; + ndev = filp->private_data; + mmio = ndev->self_mmio; - ntb_cntl = readl(ndev->reg_ofs.lnk_cntl); - if (ntb_cntl & BWD_CNTL_LINK_DOWN) - link_state = NTB_LINK_DOWN; - else - link_state = NTB_LINK_UP; - } else { - u16 status; - int rc; + buf_size = min(count, 0x800ul); - rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET, - &status); - if (rc) - return rc; + buf = kmalloc(buf_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; - if (status & NTB_LINK_STATUS_ACTIVE) - link_state = NTB_LINK_UP; - else - link_state = NTB_LINK_DOWN; - } + off = 0; - ntb_link_event(ndev, link_state); + off += scnprintf(buf + off, buf_size - off, + "NTB Device Information:\n"); - return 0; -} + off += scnprintf(buf + off, buf_size - off, + "Connection Topology -\t%s\n", + ntb_topo_string(ndev->ntb.topo)); -static void bwd_link_recovery(struct work_struct *work) -{ - struct ntb_device *ndev = container_of(work, struct ntb_device, - lr_timer.work); - u32 status32; + off += scnprintf(buf + off, buf_size - off, + "B2B Offset -\t\t%#lx\n", ndev->b2b_off); + off += scnprintf(buf + off, buf_size - off, + "B2B MW Idx -\t\t%d\n", ndev->b2b_idx); + off += scnprintf(buf + off, buf_size - off, + "BAR4 Split -\t\t%s\n", + ndev->bar4_split ? "yes" : "no"); - bwd_recover_link(ndev); - /* There is a potential race between the 2 NTB devices recovering at the - * same time. If the times are the same, the link will not recover and - * the driver will be stuck in this loop forever. Add a random interval - * to the recovery time to prevent this race. - */ - msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME); - - status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET); - if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) - goto retry; - - status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET); - if (status32 & BWD_IBIST_ERR_OFLOW) - goto retry; - - status32 = readl(ndev->reg_ofs.lnk_cntl); - if (!(status32 & BWD_CNTL_LINK_DOWN)) { - unsigned char speed, width; - u16 status16; - - status16 = readw(ndev->reg_ofs.lnk_stat); - width = (status16 & NTB_LINK_WIDTH_MASK) >> 4; - speed = (status16 & NTB_LINK_SPEED_MASK); - if (ndev->link_width != width || ndev->link_speed != speed) - goto retry; + off += scnprintf(buf + off, buf_size - off, + "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl); + off += scnprintf(buf + off, buf_size - off, + "LNK STA -\t\t%#06x\n", ndev->lnk_sta); + + if (!ndev->reg->link_is_up(ndev)) { + off += scnprintf(buf + off, buf_size - off, + "Link Status -\t\tDown\n"); + } else { + off += scnprintf(buf + off, buf_size - off, + "Link Status -\t\tUp\n"); + off += scnprintf(buf + off, buf_size - off, + "Link Speed -\t\tPCI-E Gen %u\n", + NTB_LNK_STA_SPEED(ndev->lnk_sta)); + off += scnprintf(buf + off, buf_size - off, + "Link Width -\t\tx%u\n", + NTB_LNK_STA_WIDTH(ndev->lnk_sta)); } - schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT); - return; + off += scnprintf(buf + off, buf_size - off, + "Memory Window Count -\t%u\n", ndev->mw_count); + off += scnprintf(buf + off, buf_size - off, + "Scratchpad Count -\t%u\n", ndev->spad_count); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Count -\t%u\n", ndev->db_count); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Vector Count -\t%u\n", ndev->db_vec_count); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift); + + off += scnprintf(buf + off, buf_size - off, + "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); + + u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Mask -\t\t%#llx\n", u.v64); + + u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell); + off += scnprintf(buf + off, buf_size - off, + "Doorbell Bell -\t\t%#llx\n", u.v64); + + off += scnprintf(buf + off, buf_size - off, + "\nNTB Incoming XLAT:\n"); + + u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2)); + off += scnprintf(buf + off, buf_size - off, + "XLAT23 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); + off += scnprintf(buf + off, buf_size - off, + "XLAT45 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2)); + off += scnprintf(buf + off, buf_size - off, + "LMT23 -\t\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); + off += scnprintf(buf + off, buf_size - off, + "LMT45 -\t\t\t%#018llx\n", u.v64); + + if (pdev_is_snb(ndev->ntb.pdev)) { + if (ntb_topo_is_b2b(ndev->ntb.topo)) { + off += scnprintf(buf + off, buf_size - off, + "\nNTB Outgoing B2B XLAT:\n"); + + u.v64 = ioread64(mmio + SNB_PBAR23XLAT_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "B2B XLAT23 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + SNB_PBAR45XLAT_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "B2B XLAT45 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + SNB_PBAR23LMT_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "B2B LMT23 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + SNB_PBAR45LMT_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "B2B LMT45 -\t\t%#018llx\n", u.v64); + + off += scnprintf(buf + off, buf_size - off, + "\nNTB Secondary BAR:\n"); + + u.v64 = ioread64(mmio + SNB_SBAR0BASE_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "SBAR01 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + SNB_SBAR23BASE_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "SBAR23 -\t\t%#018llx\n", u.v64); + + u.v64 = ioread64(mmio + SNB_SBAR45BASE_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "SBAR45 -\t\t%#018llx\n", u.v64); + } + + off += scnprintf(buf + off, buf_size - off, + "\nSNB NTB Statistics:\n"); + + u.v16 = ioread16(mmio + SNB_USMEMMISS_OFFSET); + off += scnprintf(buf + off, buf_size - off, + "Upstream Memory Miss -\t%u\n", u.v16); + + off += scnprintf(buf + off, buf_size - off, + "\nSNB NTB Hardware Errors:\n"); + + if (!pci_read_config_word(ndev->ntb.pdev, + SNB_DEVSTS_OFFSET, &u.v16)) + off += scnprintf(buf + off, buf_size - off, + "DEVSTS -\t\t%#06x\n", u.v16); + + if (!pci_read_config_word(ndev->ntb.pdev, + SNB_LINK_STATUS_OFFSET, &u.v16)) + off += scnprintf(buf + off, buf_size - off, + "LNKSTS -\t\t%#06x\n", u.v16); -retry: - schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT); + if (!pci_read_config_dword(ndev->ntb.pdev, + SNB_UNCERRSTS_OFFSET, &u.v32)) + off += scnprintf(buf + off, buf_size - off, + "UNCERRSTS -\t\t%#06x\n", u.v32); + + if (!pci_read_config_dword(ndev->ntb.pdev, + SNB_CORERRSTS_OFFSET, &u.v32)) + off += scnprintf(buf + off, buf_size - off, + "CORERRSTS -\t\t%#06x\n", u.v32); + } + + ret = simple_read_from_buffer(ubuf, count, offp, buf, off); + kfree(buf); + return ret; } -/* BWD doesn't have link status interrupt, poll on that platform */ -static void bwd_link_poll(struct work_struct *work) +static void ndev_init_debugfs(struct intel_ntb_dev *ndev) { - struct ntb_device *ndev = container_of(work, struct ntb_device, - hb_timer.work); - unsigned long ts = jiffies; - - /* If we haven't gotten an interrupt in a while, check the BWD link - * status bit - */ - if (ts > ndev->last_ts + NTB_HB_TIMEOUT) { - int rc = ntb_link_status(ndev); - if (rc) - dev_err(&ndev->pdev->dev, - "Error determining link status\n"); - - /* Check to see if a link error is the cause of the link down */ - if (ndev->link_status == NTB_LINK_DOWN) { - u32 status32 = readl(ndev->reg_base + - BWD_LTSSMSTATEJMP_OFFSET); - if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) { - schedule_delayed_work(&ndev->lr_timer, 0); - return; - } - } + if (!debugfs_dir) { + ndev->debugfs_dir = NULL; + ndev->debugfs_info = NULL; + } else { + ndev->debugfs_dir = + debugfs_create_dir(ndev_name(ndev), debugfs_dir); + if (!ndev->debugfs_dir) + ndev->debugfs_info = NULL; + else + ndev->debugfs_info = + debugfs_create_file("info", S_IRUSR, + ndev->debugfs_dir, ndev, + &intel_ntb_debugfs_info); } +} - schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT); +static void ndev_deinit_debugfs(struct intel_ntb_dev *ndev) +{ + debugfs_remove_recursive(ndev->debugfs_dir); } -static int ntb_xeon_setup(struct ntb_device *ndev) +static int intel_ntb_mw_count(struct ntb_dev *ntb) { - switch (ndev->conn_type) { - case NTB_CONN_B2B: - ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET; - ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET; - ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET; - ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET; - ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET; - if (ndev->split_bar) - ndev->reg_ofs.bar5_xlat = - ndev->reg_base + SNB_SBAR5XLAT_OFFSET; - ndev->limits.max_spads = SNB_MAX_B2B_SPADS; + return ntb_ndev(ntb)->mw_count; +} - /* There is a Xeon hardware errata related to writes to - * SDOORBELL or B2BDOORBELL in conjunction with inbound access - * to NTB MMIO Space, which may hang the system. To workaround - * this use the second memory window to access the interrupt and - * scratch pad registers on the remote system. - */ - if (ndev->wa_flags & WA_SNB_ERR) { - if (!ndev->mw[ndev->limits.max_mw - 1].bar_sz) - return -EINVAL; - - ndev->limits.max_db_bits = SNB_MAX_DB_BITS; - ndev->reg_ofs.spad_write = - ndev->mw[ndev->limits.max_mw - 1].vbase + - SNB_SPAD_OFFSET; - ndev->reg_ofs.rdb = - ndev->mw[ndev->limits.max_mw - 1].vbase + - SNB_PDOORBELL_OFFSET; - - /* Set the Limit register to 4k, the minimum size, to - * prevent an illegal access - */ - writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base + - SNB_PBAR4LMT_OFFSET); - /* HW errata on the Limit registers. They can only be - * written when the base register is 4GB aligned and - * < 32bit. This should already be the case based on - * the driver defaults, but write the Limit registers - * first just in case. - */ - - ndev->limits.max_mw = SNB_ERRATA_MAX_MW; - } else { - /* HW Errata on bit 14 of b2bdoorbell register. Writes - * will not be mirrored to the remote system. Shrink - * the number of bits by one, since bit 14 is the last - * bit. - */ - ndev->limits.max_db_bits = SNB_MAX_DB_BITS - 1; - ndev->reg_ofs.spad_write = ndev->reg_base + - SNB_B2B_SPAD_OFFSET; - ndev->reg_ofs.rdb = ndev->reg_base + - SNB_B2B_DOORBELL_OFFSET; - - /* Disable the Limit register, just incase it is set to - * something silly. A 64bit write should handle it - * regardless of whether it has a split BAR or not. - */ - writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET); - /* HW errata on the Limit registers. They can only be - * written when the base register is 4GB aligned and - * < 32bit. This should already be the case based on - * the driver defaults, but write the Limit registers - * first just in case. - */ - if (ndev->split_bar) - ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW; - else - ndev->limits.max_mw = SNB_MAX_MW; - } +static int intel_ntb_mw_get_range(struct ntb_dev *ntb, int idx, + phys_addr_t *base, + resource_size_t *size, + resource_size_t *align, + resource_size_t *align_size) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); + int bar; - /* The Xeon errata workaround requires setting SBAR Base - * addresses to known values, so that the PBAR XLAT can be - * pointed at SBAR0 of the remote system. - */ - if (ndev->dev_type == NTB_DEV_USD) { - writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base + - SNB_PBAR2XLAT_OFFSET); - if (ndev->wa_flags & WA_SNB_ERR) - writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base + - SNB_PBAR4XLAT_OFFSET); - else { - if (ndev->split_bar) { - writel(SNB_MBAR4_DSD_ADDR, - ndev->reg_base + - SNB_PBAR4XLAT_OFFSET); - writel(SNB_MBAR5_DSD_ADDR, - ndev->reg_base + - SNB_PBAR5XLAT_OFFSET); - } else - writeq(SNB_MBAR4_DSD_ADDR, - ndev->reg_base + - SNB_PBAR4XLAT_OFFSET); - - /* B2B_XLAT_OFFSET is a 64bit register, but can - * only take 32bit writes - */ - writel(SNB_MBAR01_DSD_ADDR & 0xffffffff, - ndev->reg_base + SNB_B2B_XLAT_OFFSETL); - writel(SNB_MBAR01_DSD_ADDR >> 32, - ndev->reg_base + SNB_B2B_XLAT_OFFSETU); - } - - writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base + - SNB_SBAR0BASE_OFFSET); - writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base + - SNB_SBAR2BASE_OFFSET); - if (ndev->split_bar) { - writel(SNB_MBAR4_USD_ADDR, ndev->reg_base + - SNB_SBAR4BASE_OFFSET); - writel(SNB_MBAR5_USD_ADDR, ndev->reg_base + - SNB_SBAR5BASE_OFFSET); - } else - writeq(SNB_MBAR4_USD_ADDR, ndev->reg_base + - SNB_SBAR4BASE_OFFSET); - } else { - writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base + - SNB_PBAR2XLAT_OFFSET); - if (ndev->wa_flags & WA_SNB_ERR) - writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base + - SNB_PBAR4XLAT_OFFSET); - else { - if (ndev->split_bar) { - writel(SNB_MBAR4_USD_ADDR, - ndev->reg_base + - SNB_PBAR4XLAT_OFFSET); - writel(SNB_MBAR5_USD_ADDR, - ndev->reg_base + - SNB_PBAR5XLAT_OFFSET); - } else - writeq(SNB_MBAR4_USD_ADDR, - ndev->reg_base + - SNB_PBAR4XLAT_OFFSET); - - /* - * B2B_XLAT_OFFSET is a 64bit register, but can - * only take 32bit writes - */ - writel(SNB_MBAR01_USD_ADDR & 0xffffffff, - ndev->reg_base + SNB_B2B_XLAT_OFFSETL); - writel(SNB_MBAR01_USD_ADDR >> 32, - ndev->reg_base + SNB_B2B_XLAT_OFFSETU); - } - writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base + - SNB_SBAR0BASE_OFFSET); - writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base + - SNB_SBAR2BASE_OFFSET); - if (ndev->split_bar) { - writel(SNB_MBAR4_DSD_ADDR, ndev->reg_base + - SNB_SBAR4BASE_OFFSET); - writel(SNB_MBAR5_DSD_ADDR, ndev->reg_base + - SNB_SBAR5BASE_OFFSET); - } else - writeq(SNB_MBAR4_DSD_ADDR, ndev->reg_base + - SNB_SBAR4BASE_OFFSET); + if (idx >= ndev->b2b_idx && !ndev->b2b_off) + idx += 1; - } - break; - case NTB_CONN_RP: - if (ndev->wa_flags & WA_SNB_ERR) { - dev_err(&ndev->pdev->dev, - "NTB-RP disabled due to hardware errata.\n"); - return -EINVAL; - } + bar = ndev_mw_to_bar(ndev, idx); + if (bar < 0) + return bar; - /* Scratch pads need to have exclusive access from the primary - * or secondary side. Halve the num spads so that each side can - * have an equal amount. - */ - ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2; - ndev->limits.max_db_bits = SNB_MAX_DB_BITS; - /* Note: The SDOORBELL is the cause of the errata. You REALLY - * don't want to touch it. - */ - ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET; - ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET; - ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET; - /* Offset the start of the spads to correspond to whether it is - * primary or secondary - */ - ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET + - ndev->limits.max_spads * 4; - ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET; - ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET; - ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET; - if (ndev->split_bar) { - ndev->reg_ofs.bar5_xlat = - ndev->reg_base + SNB_SBAR5XLAT_OFFSET; - ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW; - } else - ndev->limits.max_mw = SNB_MAX_MW; - break; - case NTB_CONN_TRANSPARENT: - if (ndev->wa_flags & WA_SNB_ERR) { - dev_err(&ndev->pdev->dev, - "NTB-TRANSPARENT disabled due to hardware errata.\n"); - return -EINVAL; - } + if (base) + *base = pci_resource_start(ndev->ntb.pdev, bar) + + (idx == ndev->b2b_idx ? ndev->b2b_off : 0); - /* Scratch pads need to have exclusive access from the primary - * or secondary side. Halve the num spads so that each side can - * have an equal amount. - */ - ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2; - ndev->limits.max_db_bits = SNB_MAX_DB_BITS; - ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET; - ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET; - ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET; - ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET; - /* Offset the start of the spads to correspond to whether it is - * primary or secondary - */ - ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET + - ndev->limits.max_spads * 4; - ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET; - ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET; - - if (ndev->split_bar) { - ndev->reg_ofs.bar5_xlat = - ndev->reg_base + SNB_PBAR5XLAT_OFFSET; - ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW; - } else - ndev->limits.max_mw = SNB_MAX_MW; - break; - default: - /* - * we should never hit this. the detect function should've - * take cared of everything. - */ - return -EINVAL; - } + if (size) + *size = pci_resource_len(ndev->ntb.pdev, bar) - + (idx == ndev->b2b_idx ? ndev->b2b_off : 0); - ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET; - ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET; - ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET; + if (align) + *align = pci_resource_len(ndev->ntb.pdev, bar); - ndev->limits.msix_cnt = SNB_MSIX_CNT; - ndev->bits_per_vector = SNB_DB_BITS_PER_VEC; + if (align_size) + *align_size = 1; return 0; } -static int ntb_bwd_setup(struct ntb_device *ndev) +static int intel_ntb_mw_set_trans(struct ntb_dev *ntb, int idx, + dma_addr_t addr, resource_size_t size) { - int rc; - u32 val; + struct intel_ntb_dev *ndev = ntb_ndev(ntb); + unsigned long base_reg, xlat_reg, limit_reg; + resource_size_t bar_size, mw_size; + void __iomem *mmio; + u64 base, limit, reg_val; + int bar; - ndev->hw_type = BWD_HW; + if (idx >= ndev->b2b_idx && !ndev->b2b_off) + idx += 1; - rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val); - if (rc) - return rc; + bar = ndev_mw_to_bar(ndev, idx); + if (bar < 0) + return bar; - switch ((val & BWD_PPD_CONN_TYPE) >> 8) { - case NTB_CONN_B2B: - ndev->conn_type = NTB_CONN_B2B; - break; - case NTB_CONN_RP: - default: - dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n"); + bar_size = pci_resource_len(ndev->ntb.pdev, bar); + + if (idx == ndev->b2b_idx) + mw_size = bar_size - ndev->b2b_off; + else + mw_size = bar_size; + + /* hardware requires that addr is aligned to bar size */ + if (addr & (bar_size - 1)) return -EINVAL; + + /* make sure the range fits in the usable mw size */ + if (size > mw_size) + return -EINVAL; + + mmio = ndev->self_mmio; + base_reg = bar0_off(ndev->xlat_reg->bar0_base, bar); + xlat_reg = bar2_off(ndev->xlat_reg->bar2_xlat, bar); + limit_reg = bar2_off(ndev->xlat_reg->bar2_limit, bar); + + if (bar < 4 || !ndev->bar4_split) { + base = ioread64(mmio + base_reg); + + /* Set the limit if supported, if size is not mw_size */ + if (limit_reg && size != mw_size) + limit = base + size; + else + limit = 0; + + /* set and verify setting the translation address */ + iowrite64(addr, mmio + xlat_reg); + reg_val = ioread64(mmio + xlat_reg); + if (reg_val != addr) { + iowrite64(0, mmio + xlat_reg); + return -EIO; + } + + /* set and verify setting the limit */ + iowrite64(limit, mmio + limit_reg); + reg_val = ioread64(mmio + limit_reg); + if (reg_val != limit) { + iowrite64(base, mmio + limit_reg); + iowrite64(0, mmio + xlat_reg); + return -EIO; + } + } else { + /* split bar addr range must all be 32 bit */ + if (addr & (~0ull << 32)) + return -EINVAL; + if ((addr + size) & (~0ull << 32)) + return -EINVAL; + + base = ioread32(mmio + base_reg); + + /* Set the limit if supported, if size is not mw_size */ + if (limit_reg && size != mw_size) + limit = base + size; + else + limit = 0; + + /* set and verify setting the translation address */ + iowrite32(addr, mmio + xlat_reg); + reg_val = ioread32(mmio + xlat_reg); + if (reg_val != addr) { + iowrite32(0, mmio + xlat_reg); + return -EIO; + } + + /* set and verify setting the limit */ + iowrite32(limit, mmio + limit_reg); + reg_val = ioread32(mmio + limit_reg); + if (reg_val != limit) { + iowrite32(base, mmio + limit_reg); + iowrite32(0, mmio + xlat_reg); + return -EIO; + } } - if (val & BWD_PPD_DEV_TYPE) - ndev->dev_type = NTB_DEV_DSD; - else - ndev->dev_type = NTB_DEV_USD; + return 0; +} - /* Initiate PCI-E link training */ - rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET, - val | BWD_PPD_INIT_LINK); - if (rc) - return rc; +static int intel_ntb_link_is_up(struct ntb_dev *ntb, + enum ntb_speed *speed, + enum ntb_width *width) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET; - ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET; - ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET; - ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET; - ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET; - ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET; - ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET; - ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET; - ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET; - ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET; - ndev->limits.max_mw = BWD_MAX_MW; - ndev->limits.max_spads = BWD_MAX_SPADS; - ndev->limits.max_db_bits = BWD_MAX_DB_BITS; - ndev->limits.msix_cnt = BWD_MSIX_CNT; - ndev->bits_per_vector = BWD_DB_BITS_PER_VEC; - - /* Since bwd doesn't have a link interrupt, setup a poll timer */ - INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll); - INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery); - schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT); + if (ndev->reg->link_is_up(ndev)) { + if (speed) + *speed = NTB_LNK_STA_SPEED(ndev->lnk_sta); + if (width) + *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta); + return 1; + } else { + /* TODO MAYBE: is it possible to observe the link speed and + * width while link is training? */ + if (speed) + *speed = NTB_SPEED_NONE; + if (width) + *width = NTB_WIDTH_NONE; + return 0; + } +} + +static int intel_ntb_link_enable(struct ntb_dev *ntb, + enum ntb_speed max_speed, + enum ntb_width max_width) +{ + struct intel_ntb_dev *ndev; + u32 ntb_ctl; + + ndev = container_of(ntb, struct intel_ntb_dev, ntb); + + if (ndev->ntb.topo == NTB_TOPO_SEC) + return -EINVAL; + + dev_dbg(ndev_dev(ndev), + "Enabling link with max_speed %d max_width %d\n", + max_speed, max_width); + if (max_speed != NTB_SPEED_AUTO) + dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed); + if (max_width != NTB_WIDTH_AUTO) + dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width); + + ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); + ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK); + ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP; + ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP; + if (ndev->bar4_split) + ntb_ctl |= NTB_CTL_P2S_BAR5_SNOOP | NTB_CTL_S2P_BAR5_SNOOP; + iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); return 0; } -static int ntb_device_setup(struct ntb_device *ndev) +static int intel_ntb_link_disable(struct ntb_dev *ntb) { - int rc; + struct intel_ntb_dev *ndev; + u32 ntb_cntl; - if (is_ntb_xeon(ndev)) - rc = ntb_xeon_setup(ndev); - else if (is_ntb_atom(ndev)) - rc = ntb_bwd_setup(ndev); - else - rc = -ENODEV; + ndev = container_of(ntb, struct intel_ntb_dev, ntb); - if (rc) - return rc; + if (ndev->ntb.topo == NTB_TOPO_SEC) + return -EINVAL; - if (ndev->conn_type == NTB_CONN_B2B) - /* Enable Bus Master and Memory Space on the secondary side */ - writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, - ndev->reg_ofs.spci_cmd); + dev_dbg(ndev_dev(ndev), "Disabling link\n"); + + /* Bring NTB link down */ + ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); + ntb_cntl &= ~(NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP); + ntb_cntl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP); + if (ndev->bar4_split) + ntb_cntl &= ~(NTB_CTL_P2S_BAR5_SNOOP | NTB_CTL_S2P_BAR5_SNOOP); + ntb_cntl |= NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK; + iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl); return 0; } -static void ntb_device_free(struct ntb_device *ndev) +static int intel_ntb_db_is_unsafe(struct ntb_dev *ntb) { - if (is_ntb_atom(ndev)) { - cancel_delayed_work_sync(&ndev->hb_timer); - cancel_delayed_work_sync(&ndev->lr_timer); - } + return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_DB); } -static irqreturn_t bwd_callback_msix_irq(int irq, void *data) +static u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb) { - struct ntb_db_cb *db_cb = data; - struct ntb_device *ndev = db_cb->ndev; - unsigned long mask; + return ntb_ndev(ntb)->db_valid_mask; +} - dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq, - db_cb->db_num); +static int intel_ntb_db_vector_count(struct ntb_dev *ntb) +{ + struct intel_ntb_dev *ndev; - mask = readw(ndev->reg_ofs.ldb_mask); - set_bit(db_cb->db_num * ndev->bits_per_vector, &mask); - writew(mask, ndev->reg_ofs.ldb_mask); + ndev = container_of(ntb, struct intel_ntb_dev, ntb); - tasklet_schedule(&db_cb->irq_work); + return ndev->db_vec_count; +} - /* No need to check for the specific HB irq, any interrupt means - * we're connected. - */ - ndev->last_ts = jiffies; +static u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb); + if (db_vector < 0 || db_vector > ndev->db_vec_count) + return 0; - return IRQ_HANDLED; + return ndev->db_valid_mask & ndev_vec_mask(ndev, db_vector); } -static irqreturn_t xeon_callback_msix_irq(int irq, void *data) +static u64 intel_ntb_db_read(struct ntb_dev *ntb) { - struct ntb_db_cb *db_cb = data; - struct ntb_device *ndev = db_cb->ndev; - unsigned long mask; + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq, - db_cb->db_num); + return ndev_db_read(ndev, + ndev->self_mmio + + ndev->self_reg->db_bell); +} - mask = readw(ndev->reg_ofs.ldb_mask); - set_bit(db_cb->db_num * ndev->bits_per_vector, &mask); - writew(mask, ndev->reg_ofs.ldb_mask); +static int intel_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - tasklet_schedule(&db_cb->irq_work); + return ndev_db_write(ndev, db_bits, + ndev->self_mmio + + ndev->self_reg->db_bell); +} - /* On Sandybridge, there are 16 bits in the interrupt register - * but only 4 vectors. So, 5 bits are assigned to the first 3 - * vectors, with the 4th having a single bit for link - * interrupts. - */ - writew(((1 << ndev->bits_per_vector) - 1) << - (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb); +static int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - return IRQ_HANDLED; + return ndev_db_set_mask(ndev, db_bits, + ndev->self_mmio + + ndev->self_reg->db_mask); } -/* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */ -static irqreturn_t xeon_event_msix_irq(int irq, void *dev) +static int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) { - struct ntb_device *ndev = dev; - int rc; - - dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq); + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - rc = ntb_link_status(ndev); - if (rc) - dev_err(&ndev->pdev->dev, "Error determining link status\n"); + return ndev_db_clear_mask(ndev, db_bits, + ndev->self_mmio + + ndev->self_reg->db_mask); +} - /* bit 15 is always the link bit */ - writew(1 << SNB_LINK_DB, ndev->reg_ofs.ldb); +static int intel_ntb_peer_db_addr(struct ntb_dev *ntb, + phys_addr_t *db_addr, + resource_size_t *db_size) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - return IRQ_HANDLED; + return ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr, + ndev->peer_reg->db_bell); } -static irqreturn_t ntb_interrupt(int irq, void *dev) +static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) { - struct ntb_device *ndev = dev; - unsigned int i = 0; + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - if (is_ntb_atom(ndev)) { - u64 ldb = readq(ndev->reg_ofs.ldb); + return ndev_db_write(ndev, db_bits, + ndev->peer_mmio + + ndev->peer_reg->db_bell); +} - dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb); +static int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb) +{ + return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_SPAD); +} - while (ldb) { - i = __ffs(ldb); - ldb &= ldb - 1; - bwd_callback_msix_irq(irq, &ndev->db_cb[i]); - } - } else { - u16 ldb = readw(ndev->reg_ofs.ldb); +static int intel_ntb_spad_count(struct ntb_dev *ntb) +{ + struct intel_ntb_dev *ndev; - dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb); + ndev = container_of(ntb, struct intel_ntb_dev, ntb); - if (ldb & SNB_DB_HW_LINK) { - xeon_event_msix_irq(irq, dev); - ldb &= ~SNB_DB_HW_LINK; - } + return ndev->spad_count; +} - while (ldb) { - i = __ffs(ldb); - ldb &= ldb - 1; - xeon_callback_msix_irq(irq, &ndev->db_cb[i]); - } - } +static u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - return IRQ_HANDLED; + return ndev_spad_read(ndev, idx, + ndev->self_mmio + + ndev->self_reg->spad); } -static int ntb_setup_snb_msix(struct ntb_device *ndev, int msix_entries) +static int intel_ntb_spad_write(struct ntb_dev *ntb, + int idx, u32 val) { - struct pci_dev *pdev = ndev->pdev; - struct msix_entry *msix; - int rc, i; + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - if (msix_entries < ndev->limits.msix_cnt) - return -ENOSPC; + return ndev_spad_write(ndev, idx, val, + ndev->self_mmio + + ndev->self_reg->spad); +} - rc = pci_enable_msix_exact(pdev, ndev->msix_entries, msix_entries); - if (rc < 0) - return rc; +static int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int idx, + phys_addr_t *spad_addr) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - for (i = 0; i < msix_entries; i++) { - msix = &ndev->msix_entries[i]; - WARN_ON(!msix->vector); + return ndev_spad_addr(ndev, idx, spad_addr, ndev->peer_addr, + ndev->peer_reg->spad); +} - if (i == msix_entries - 1) { - rc = request_irq(msix->vector, - xeon_event_msix_irq, 0, - "ntb-event-msix", ndev); - if (rc) - goto err; - } else { - rc = request_irq(msix->vector, - xeon_callback_msix_irq, 0, - "ntb-callback-msix", - &ndev->db_cb[i]); - if (rc) - goto err; - } - } +static u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int idx) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); - ndev->num_msix = msix_entries; - ndev->max_cbs = msix_entries - 1; + return ndev_spad_read(ndev, idx, + ndev->peer_mmio + + ndev->peer_reg->spad); +} - return 0; +static int intel_ntb_peer_spad_write(struct ntb_dev *ntb, + int idx, u32 val) +{ + struct intel_ntb_dev *ndev = ntb_ndev(ntb); -err: - while (--i >= 0) { - /* Code never reaches here for entry nr 'ndev->num_msix - 1' */ - msix = &ndev->msix_entries[i]; - free_irq(msix->vector, &ndev->db_cb[i]); - } + return ndev_spad_write(ndev, idx, val, + ndev->peer_mmio + + ndev->peer_reg->spad); +} - pci_disable_msix(pdev); - ndev->num_msix = 0; +/* BWD */ - return rc; +static u64 bwd_db_ioread(void __iomem *mmio) +{ + return ioread64(mmio); +} + +static void bwd_db_iowrite(u64 bits, void __iomem *mmio) +{ + iowrite64(bits, mmio); } -static int ntb_setup_bwd_msix(struct ntb_device *ndev, int msix_entries) +static int bwd_poll_link(struct intel_ntb_dev *ndev) { - struct pci_dev *pdev = ndev->pdev; - struct msix_entry *msix; - int rc, i; + u32 ntb_ctl; - msix_entries = pci_enable_msix_range(pdev, ndev->msix_entries, - 1, msix_entries); - if (msix_entries < 0) - return msix_entries; + ntb_ctl = ioread32(ndev->self_mmio + BWD_NTBCNTL_OFFSET); - for (i = 0; i < msix_entries; i++) { - msix = &ndev->msix_entries[i]; - WARN_ON(!msix->vector); + if (ntb_ctl == ndev->ntb_ctl) + return 0; - rc = request_irq(msix->vector, bwd_callback_msix_irq, 0, - "ntb-callback-msix", &ndev->db_cb[i]); - if (rc) - goto err; - } + ndev->ntb_ctl = ntb_ctl; - ndev->num_msix = msix_entries; - ndev->max_cbs = msix_entries; + ndev->lnk_sta = ioread32(ndev->self_mmio + BWD_LINK_STATUS_OFFSET); - return 0; + return 1; +} -err: - while (--i >= 0) - free_irq(msix->vector, &ndev->db_cb[i]); +static int bwd_link_is_up(struct intel_ntb_dev *ndev) +{ + return BWD_NTB_CTL_ACTIVE(ndev->ntb_ctl); +} - pci_disable_msix(pdev); - ndev->num_msix = 0; +static int bwd_link_is_err(struct intel_ntb_dev *ndev) +{ + if (ioread32(ndev->self_mmio + BWD_LTSSMSTATEJMP_OFFSET) + & BWD_LTSSMSTATEJMP_FORCEDETECT) + return 1; - return rc; + if (ioread32(ndev->self_mmio + BWD_IBSTERRRCRVSTS0_OFFSET) + & BWD_IBIST_ERR_OFLOW) + return 1; + + return 0; } -static int ntb_setup_msix(struct ntb_device *ndev) +static inline enum ntb_topo bwd_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) { - struct pci_dev *pdev = ndev->pdev; - int msix_entries; - int rc, i; + switch (ppd & BWD_PPD_TOPO_MASK) { + case BWD_PPD_TOPO_B2B_USD: + dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd); + return NTB_TOPO_B2B_USD; + + case BWD_PPD_TOPO_B2B_DSD: + dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd); + return NTB_TOPO_B2B_DSD; + + case BWD_PPD_TOPO_PRI_USD: + case BWD_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ + case BWD_PPD_TOPO_SEC_USD: + case BWD_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ + dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd); + return NTB_TOPO_NONE; + } - msix_entries = pci_msix_vec_count(pdev); - if (msix_entries < 0) { - rc = msix_entries; - goto err; - } else if (msix_entries > ndev->limits.msix_cnt) { - rc = -EINVAL; - goto err; + dev_dbg(ndev_dev(ndev), "PPD %d invalid\n", ppd); + return NTB_TOPO_NONE; +} + +static void bwd_link_hb(struct work_struct *work) +{ + struct intel_ntb_dev *ndev = hb_ndev(work); + unsigned long poll_ts; + void __iomem *mmio; + u32 status32; + + poll_ts = ndev->last_ts + BWD_LINK_HB_TIMEOUT; + + /* Delay polling the link status if an interrupt was received, + * unless the cached link status says the link is down. + */ + if (time_after(poll_ts, jiffies) && bwd_link_is_up(ndev)) { + schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies); + return; } - ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries, - GFP_KERNEL); - if (!ndev->msix_entries) { - rc = -ENOMEM; - goto err; + if (bwd_poll_link(ndev)) + ntb_link_event(&ndev->ntb); + + if (bwd_link_is_up(ndev) || !bwd_link_is_err(ndev)) { + schedule_delayed_work(&ndev->hb_timer, BWD_LINK_HB_TIMEOUT); + return; } - for (i = 0; i < msix_entries; i++) - ndev->msix_entries[i].entry = i; + /* Link is down with error: recover the link! */ - if (is_ntb_atom(ndev)) - rc = ntb_setup_bwd_msix(ndev, msix_entries); - else - rc = ntb_setup_snb_msix(ndev, msix_entries); - if (rc) - goto err1; + mmio = ndev->self_mmio; - return 0; + /* Driver resets the NTB ModPhy lanes - magic! */ + iowrite8(0xe0, mmio + BWD_MODPHY_PCSREG6); + iowrite8(0x40, mmio + BWD_MODPHY_PCSREG4); + iowrite8(0x60, mmio + BWD_MODPHY_PCSREG4); + iowrite8(0x60, mmio + BWD_MODPHY_PCSREG6); -err1: - kfree(ndev->msix_entries); -err: - dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n"); - return rc; + /* Driver waits 100ms to allow the NTB ModPhy to settle */ + msleep(100); + + /* Clear AER Errors, write to clear */ + status32 = ioread32(mmio + BWD_ERRCORSTS_OFFSET); + dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32); + status32 &= PCI_ERR_COR_REP_ROLL; + iowrite32(status32, mmio + BWD_ERRCORSTS_OFFSET); + + /* Clear unexpected electrical idle event in LTSSM, write to clear */ + status32 = ioread32(mmio + BWD_LTSSMERRSTS0_OFFSET); + dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32); + status32 |= BWD_LTSSMERRSTS0_UNEXPECTEDEI; + iowrite32(status32, mmio + BWD_LTSSMERRSTS0_OFFSET); + + /* Clear DeSkew Buffer error, write to clear */ + status32 = ioread32(mmio + BWD_DESKEWSTS_OFFSET); + dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32); + status32 |= BWD_DESKEWSTS_DBERR; + iowrite32(status32, mmio + BWD_DESKEWSTS_OFFSET); + + status32 = ioread32(mmio + BWD_IBSTERRRCRVSTS0_OFFSET); + dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32); + status32 &= BWD_IBIST_ERR_OFLOW; + iowrite32(status32, mmio + BWD_IBSTERRRCRVSTS0_OFFSET); + + /* Releases the NTB state machine to allow the link to retrain */ + status32 = ioread32(mmio + BWD_LTSSMSTATEJMP_OFFSET); + dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32); + status32 &= ~BWD_LTSSMSTATEJMP_FORCEDETECT; + iowrite32(status32, mmio + BWD_LTSSMSTATEJMP_OFFSET); + + /* There is a potential race between the 2 NTB devices recovering at the + * same time. If the times are the same, the link will not recover and + * the driver will be stuck in this loop forever. Add a random interval + * to the recovery time to prevent this race. + */ + schedule_delayed_work(&ndev->hb_timer, BWD_LINK_RECOVERY_TIME + + prandom_u32() % BWD_LINK_RECOVERY_TIME); } -static int ntb_setup_msi(struct ntb_device *ndev) +static int bwd_init_isr(struct intel_ntb_dev *ndev) { - struct pci_dev *pdev = ndev->pdev; int rc; - rc = pci_enable_msi(pdev); + rc = ndev_init_isr(ndev, 1, BWD_DB_MSIX_VECTOR_COUNT, + BWD_DB_MSIX_VECTOR_SHIFT, BWD_DB_TOTAL_SHIFT); if (rc) return rc; - rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev); - if (rc) { - pci_disable_msi(pdev); - dev_err(&pdev->dev, "Error allocating MSI interrupt\n"); - return rc; - } + /* BWD doesn't have link status interrupt, poll on that platform */ + ndev->last_ts = jiffies; + INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_hb); + schedule_delayed_work(&ndev->hb_timer, BWD_LINK_HB_TIMEOUT); return 0; } -static int ntb_setup_intx(struct ntb_device *ndev) +static void bwd_deinit_isr(struct intel_ntb_dev *ndev) { - struct pci_dev *pdev = ndev->pdev; - int rc; + cancel_delayed_work_sync(&ndev->hb_timer); + ndev_deinit_isr(ndev); +} - /* Verify intx is enabled */ - pci_intx(pdev, 1); +static int bwd_init_ntb(struct intel_ntb_dev *ndev) +{ + ndev->mw_count = BWD_MW_COUNT; + ndev->spad_count = BWD_SPAD_COUNT; + ndev->db_count = BWD_DB_COUNT; - rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx", - ndev); - if (rc) - return rc; + switch (ndev->ntb.topo) { + case NTB_TOPO_B2B_USD: + case NTB_TOPO_B2B_DSD: + ndev->self_reg = &bwd_pri_reg; + ndev->peer_reg = &bwd_b2b_reg; + ndev->xlat_reg = &bwd_sec_xlat; + + /* Enable Bus Master and Memory Space on the secondary side */ + iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, + ndev->self_mmio + BWD_SPCICMD_OFFSET); + + break; + + default: + return -EINVAL; + } + + ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; return 0; } -static int ntb_setup_interrupts(struct ntb_device *ndev) +static int bwd_init_dev(struct intel_ntb_dev *ndev) { + u32 ppd; int rc; - /* On BWD, disable all interrupts. On SNB, disable all but Link - * Interrupt. The rest will be unmasked as callbacks are registered. - */ - if (is_ntb_atom(ndev)) - writeq(~0, ndev->reg_ofs.ldb_mask); - else { - u16 var = 1 << SNB_LINK_DB; - writew(~var, ndev->reg_ofs.ldb_mask); - } - - rc = ntb_setup_msix(ndev); - if (!rc) - goto done; + rc = pci_read_config_dword(ndev->ntb.pdev, BWD_PPD_OFFSET, &ppd); + if (rc) + return -EIO; - ndev->bits_per_vector = 1; - ndev->max_cbs = ndev->limits.max_db_bits; + ndev->ntb.topo = bwd_ppd_topo(ndev, ppd); + if (ndev->ntb.topo == NTB_TOPO_NONE) + return -EINVAL; - rc = ntb_setup_msi(ndev); - if (!rc) - goto done; + rc = bwd_init_ntb(ndev); + if (rc) + return rc; - rc = ntb_setup_intx(ndev); - if (rc) { - dev_err(&ndev->pdev->dev, "no usable interrupts\n"); + rc = bwd_init_isr(ndev); + if (rc) return rc; + + if (ndev->ntb.topo != NTB_TOPO_SEC) { + /* Initiate PCI-E link training */ + rc = pci_write_config_dword(ndev->ntb.pdev, BWD_PPD_OFFSET, + ppd | BWD_PPD_INIT_LINK); + if (rc) + return rc; } -done: return 0; } -static void ntb_free_interrupts(struct ntb_device *ndev) +static void bwd_deinit_dev(struct intel_ntb_dev *ndev) { - struct pci_dev *pdev = ndev->pdev; + bwd_deinit_isr(ndev); +} - /* mask interrupts */ - if (is_ntb_atom(ndev)) - writeq(~0, ndev->reg_ofs.ldb_mask); - else - writew(~0, ndev->reg_ofs.ldb_mask); +/* SNB */ - if (ndev->num_msix) { - struct msix_entry *msix; - u32 i; +static u64 snb_db_ioread(void __iomem *mmio) +{ + return (u64)ioread16(mmio); +} - for (i = 0; i < ndev->num_msix; i++) { - msix = &ndev->msix_entries[i]; - if (is_ntb_xeon(ndev) && i == ndev->num_msix - 1) - free_irq(msix->vector, ndev); - else - free_irq(msix->vector, &ndev->db_cb[i]); - } - pci_disable_msix(pdev); - kfree(ndev->msix_entries); - } else { - free_irq(pdev->irq, ndev); +static void snb_db_iowrite(u64 bits, void __iomem *mmio) +{ + iowrite16((u16)bits, mmio); +} - if (pci_dev_msi_enabled(pdev)) - pci_disable_msi(pdev); - } +static int snb_poll_link(struct intel_ntb_dev *ndev) +{ + u16 reg_val; + int rc; + + ndev->reg->db_iowrite(ndev->db_link_mask, + ndev->self_mmio + + ndev->self_reg->db_bell); + + rc = pci_read_config_word(ndev->ntb.pdev, + SNB_LINK_STATUS_OFFSET, ®_val); + if (rc) + return 0; + + if (reg_val == ndev->lnk_sta) + return 0; + + ndev->lnk_sta = reg_val; + + return 1; } -static int ntb_create_callbacks(struct ntb_device *ndev) +static int snb_link_is_up(struct intel_ntb_dev *ndev) { - int i; + return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); +} - /* Chicken-egg issue. We won't know how many callbacks are necessary - * until we see how many MSI-X vectors we get, but these pointers need - * to be passed into the MSI-X register function. So, we allocate the - * max, knowing that they might not all be used, to work around this. - */ - ndev->db_cb = kcalloc(ndev->limits.max_db_bits, - sizeof(struct ntb_db_cb), - GFP_KERNEL); - if (!ndev->db_cb) - return -ENOMEM; +static inline enum ntb_topo snb_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd) +{ + switch (ppd & SNB_PPD_TOPO_MASK) { + case SNB_PPD_TOPO_B2B_USD: + return NTB_TOPO_B2B_USD; + + case SNB_PPD_TOPO_B2B_DSD: + return NTB_TOPO_B2B_DSD; + + case SNB_PPD_TOPO_PRI_USD: + case SNB_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ + return NTB_TOPO_PRI; - for (i = 0; i < ndev->limits.max_db_bits; i++) { - ndev->db_cb[i].db_num = i; - ndev->db_cb[i].ndev = ndev; + case SNB_PPD_TOPO_SEC_USD: + case SNB_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ + return NTB_TOPO_SEC; } - return 0; + return NTB_TOPO_NONE; } -static void ntb_free_callbacks(struct ntb_device *ndev) +static inline int snb_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd) { - int i; + if (ppd & SNB_PPD_SPLIT_BAR_MASK) { + dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd); + return 1; + } + return 0; +} - for (i = 0; i < ndev->limits.max_db_bits; i++) - ntb_unregister_db_callback(ndev, i); +static int snb_init_isr(struct intel_ntb_dev *ndev) +{ + return ndev_init_isr(ndev, SNB_DB_MSIX_VECTOR_COUNT, + SNB_DB_MSIX_VECTOR_COUNT, + SNB_DB_MSIX_VECTOR_SHIFT, + SNB_DB_TOTAL_SHIFT); +} - kfree(ndev->db_cb); +static void snb_deinit_isr(struct intel_ntb_dev *ndev) +{ + ndev_deinit_isr(ndev); } -static ssize_t ntb_debugfs_read(struct file *filp, char __user *ubuf, - size_t count, loff_t *offp) +static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, + const struct intel_b2b_addr *addr, + const struct intel_b2b_addr *peer_addr) { - struct ntb_device *ndev; - char *buf; - ssize_t ret, offset, out_count; + struct pci_dev *pdev; + void __iomem *mmio; + resource_size_t bar_size; + phys_addr_t bar_addr; + int b2b_bar; + u8 bar_sz; + + pdev = ndev_pdev(ndev); + mmio = ndev->self_mmio; + + if (ndev->b2b_idx >= ndev->mw_count) { + dev_dbg(ndev_dev(ndev), "not using b2b mw\n"); + b2b_bar = 0; + ndev->b2b_off = 0; + } else { + b2b_bar = ndev_mw_to_bar(ndev, ndev->b2b_idx); + if (b2b_bar < 0) + return -EIO; - out_count = 500; + dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar); - buf = kmalloc(out_count, GFP_KERNEL); - if (!buf) - return -ENOMEM; + bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar); - ndev = filp->private_data; - offset = 0; - offset += snprintf(buf + offset, out_count - offset, - "NTB Device Information:\n"); - offset += snprintf(buf + offset, out_count - offset, - "Connection Type - \t\t%s\n", - ndev->conn_type == NTB_CONN_TRANSPARENT ? - "Transparent" : (ndev->conn_type == NTB_CONN_B2B) ? - "Back to back" : "Root Port"); - offset += snprintf(buf + offset, out_count - offset, - "Device Type - \t\t\t%s\n", - ndev->dev_type == NTB_DEV_USD ? - "DSD/USP" : "USD/DSP"); - offset += snprintf(buf + offset, out_count - offset, - "Max Number of Callbacks - \t%u\n", - ntb_max_cbs(ndev)); - offset += snprintf(buf + offset, out_count - offset, - "Link Status - \t\t\t%s\n", - ntb_hw_link_status(ndev) ? "Up" : "Down"); - if (ntb_hw_link_status(ndev)) { - offset += snprintf(buf + offset, out_count - offset, - "Link Speed - \t\t\tPCI-E Gen %u\n", - ndev->link_speed); - offset += snprintf(buf + offset, out_count - offset, - "Link Width - \t\t\tx%u\n", - ndev->link_width); - } + dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size); - if (is_ntb_xeon(ndev)) { - u32 status32; - u16 status16; - int rc; - - offset += snprintf(buf + offset, out_count - offset, - "\nNTB Device Statistics:\n"); - offset += snprintf(buf + offset, out_count - offset, - "Upstream Memory Miss - \t%u\n", - readw(ndev->reg_base + - SNB_USMEMMISS_OFFSET)); - - offset += snprintf(buf + offset, out_count - offset, - "\nNTB Hardware Errors:\n"); - - rc = pci_read_config_word(ndev->pdev, SNB_DEVSTS_OFFSET, - &status16); - if (!rc) - offset += snprintf(buf + offset, out_count - offset, - "DEVSTS - \t%#06x\n", status16); - - rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET, - &status16); - if (!rc) - offset += snprintf(buf + offset, out_count - offset, - "LNKSTS - \t%#06x\n", status16); - - rc = pci_read_config_dword(ndev->pdev, SNB_UNCERRSTS_OFFSET, - &status32); - if (!rc) - offset += snprintf(buf + offset, out_count - offset, - "UNCERRSTS - \t%#010x\n", status32); - - rc = pci_read_config_dword(ndev->pdev, SNB_CORERRSTS_OFFSET, - &status32); - if (!rc) - offset += snprintf(buf + offset, out_count - offset, - "CORERRSTS - \t%#010x\n", status32); + if (b2b_mw_share && SNB_B2B_MIN_SIZE <= bar_size >> 1) { + dev_dbg(ndev_dev(ndev), + "b2b using first half of bar\n"); + ndev->b2b_off = bar_size >> 1; + } else if (SNB_B2B_MIN_SIZE <= bar_size) { + dev_dbg(ndev_dev(ndev), + "b2b using whole bar\n"); + ndev->b2b_off = 0; + --ndev->mw_count; + } else { + dev_dbg(ndev_dev(ndev), + "b2b bar size is too small\n"); + return -EIO; + } } - if (offset > out_count) - offset = out_count; + /* Reset the secondary bar sizes to match the primary bar sizes, + * except disable or halve the size of the b2b secondary bar. + * + * Note: code for each specific bar size register, because the register + * offsets are not in a consistent order (bar5sz comes after ppd, odd). + */ + pci_read_config_byte(pdev, SNB_PBAR23SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz); + if (b2b_bar == 2) { + if (ndev->b2b_off) + bar_sz -= 1; + else + bar_sz = 0; + } + pci_write_config_byte(pdev, SNB_SBAR23SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, SNB_SBAR23SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz); + + if (!ndev->bar4_split) { + pci_read_config_byte(pdev, SNB_PBAR45SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz); + if (b2b_bar == 4) { + if (ndev->b2b_off) + bar_sz -= 1; + else + bar_sz = 0; + } + pci_write_config_byte(pdev, SNB_SBAR45SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, SNB_SBAR45SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz); + } else { + pci_read_config_byte(pdev, SNB_PBAR4SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz); + if (b2b_bar == 4) { + if (ndev->b2b_off) + bar_sz -= 1; + else + bar_sz = 0; + } + pci_write_config_byte(pdev, SNB_SBAR4SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, SNB_SBAR4SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz); + + pci_read_config_byte(pdev, SNB_PBAR5SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz); + if (b2b_bar == 5) { + if (ndev->b2b_off) + bar_sz -= 1; + else + bar_sz = 0; + } + pci_write_config_byte(pdev, SNB_SBAR5SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, SNB_SBAR5SZ_OFFSET, &bar_sz); + dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz); + } - ret = simple_read_from_buffer(ubuf, count, offp, buf, offset); - kfree(buf); - return ret; -} + /* SBAR01 hit by first part of the b2b bar */ + if (b2b_bar == 0) + bar_addr = addr->bar0_addr; + else if (b2b_bar == 2) + bar_addr = addr->bar2_addr64; + else if (b2b_bar == 4 && !ndev->bar4_split) + bar_addr = addr->bar4_addr64; + else if (b2b_bar == 4) + bar_addr = addr->bar4_addr32; + else if (b2b_bar == 5) + bar_addr = addr->bar5_addr32; + else + return -EIO; -static const struct file_operations ntb_debugfs_info = { - .owner = THIS_MODULE, - .open = simple_open, - .read = ntb_debugfs_read, -}; + dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr); + iowrite64(bar_addr, mmio + SNB_SBAR0BASE_OFFSET); -static void ntb_setup_debugfs(struct ntb_device *ndev) -{ - if (!debugfs_initialized()) - return; + /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar. + * The b2b bar is either disabled above, or configured half-size, and + * it starts at the PBAR xlat + offset. + */ - if (!debugfs_dir) - debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); + bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); + iowrite64(bar_addr, mmio + SNB_SBAR23BASE_OFFSET); + bar_addr = ioread64(mmio + SNB_SBAR23BASE_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr); + + if (!ndev->bar4_split) { + bar_addr = addr->bar4_addr64 + + (b2b_bar == 4 ? ndev->b2b_off : 0); + iowrite64(bar_addr, mmio + SNB_SBAR45BASE_OFFSET); + bar_addr = ioread64(mmio + SNB_SBAR45BASE_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr); + } else { + bar_addr = addr->bar4_addr32 + + (b2b_bar == 4 ? ndev->b2b_off : 0); + iowrite32(bar_addr, mmio + SNB_SBAR4BASE_OFFSET); + bar_addr = ioread32(mmio + SNB_SBAR4BASE_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr); + + bar_addr = addr->bar5_addr32 + + (b2b_bar == 5 ? ndev->b2b_off : 0); + iowrite32(bar_addr, mmio + SNB_SBAR5BASE_OFFSET); + bar_addr = ioread32(mmio + SNB_SBAR5BASE_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr); + } - ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev), - debugfs_dir); - if (ndev->debugfs_dir) - ndev->debugfs_info = debugfs_create_file("info", S_IRUSR, - ndev->debugfs_dir, - ndev, - &ntb_debugfs_info); -} + /* setup incoming bar limits == base addrs (zero length windows) */ -static void ntb_free_debugfs(struct ntb_device *ndev) -{ - debugfs_remove_recursive(ndev->debugfs_dir); + bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); + iowrite64(bar_addr, mmio + SNB_SBAR23LMT_OFFSET); + bar_addr = ioread64(mmio + SNB_SBAR23LMT_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr); - if (debugfs_dir && simple_empty(debugfs_dir)) { - debugfs_remove_recursive(debugfs_dir); - debugfs_dir = NULL; + if (!ndev->bar4_split) { + bar_addr = addr->bar4_addr64 + + (b2b_bar == 4 ? ndev->b2b_off : 0); + iowrite64(bar_addr, mmio + SNB_SBAR45LMT_OFFSET); + bar_addr = ioread64(mmio + SNB_SBAR45LMT_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr); + } else { + bar_addr = addr->bar4_addr32 + + (b2b_bar == 4 ? ndev->b2b_off : 0); + iowrite32(bar_addr, mmio + SNB_SBAR4LMT_OFFSET); + bar_addr = ioread32(mmio + SNB_SBAR4LMT_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr); + + bar_addr = addr->bar5_addr32 + + (b2b_bar == 5 ? ndev->b2b_off : 0); + iowrite32(bar_addr, mmio + SNB_SBAR5LMT_OFFSET); + bar_addr = ioread32(mmio + SNB_SBAR5LMT_OFFSET); + dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr); } -} -static void ntb_hw_link_up(struct ntb_device *ndev) -{ - if (ndev->conn_type == NTB_CONN_TRANSPARENT) - ntb_link_event(ndev, NTB_LINK_UP); - else { - u32 ntb_cntl; + /* zero incoming translation addrs */ + iowrite64(0, mmio + SNB_SBAR23XLAT_OFFSET); - /* Let's bring the NTB link up */ - ntb_cntl = readl(ndev->reg_ofs.lnk_cntl); - ntb_cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); - ntb_cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; - ntb_cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; - if (ndev->split_bar) - ntb_cntl |= NTB_CNTL_P2S_BAR5_SNOOP | - NTB_CNTL_S2P_BAR5_SNOOP; + if (!ndev->bar4_split) { + iowrite64(0, mmio + SNB_SBAR45XLAT_OFFSET); + } else { + iowrite32(0, mmio + SNB_SBAR4XLAT_OFFSET); + iowrite32(0, mmio + SNB_SBAR5XLAT_OFFSET); + } - writel(ntb_cntl, ndev->reg_ofs.lnk_cntl); + /* zero outgoing translation limits (whole bar size windows) */ + iowrite64(0, mmio + SNB_PBAR23LMT_OFFSET); + if (!ndev->bar4_split) { + iowrite64(0, mmio + SNB_PBAR45LMT_OFFSET); + } else { + iowrite32(0, mmio + SNB_PBAR4LMT_OFFSET); + iowrite32(0, mmio + SNB_PBAR5LMT_OFFSET); } -} -static void ntb_hw_link_down(struct ntb_device *ndev) -{ - u32 ntb_cntl; + /* set outgoing translation offsets */ + bar_addr = peer_addr->bar2_addr64; + iowrite64(bar_addr, mmio + SNB_PBAR23XLAT_OFFSET); + bar_addr = ioread64(mmio + SNB_PBAR23XLAT_OFFSET); + dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr); + + if (!ndev->bar4_split) { + bar_addr = peer_addr->bar4_addr64; + iowrite64(bar_addr, mmio + SNB_PBAR45XLAT_OFFSET); + bar_addr = ioread64(mmio + SNB_PBAR45XLAT_OFFSET); + dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr); + } else { + bar_addr = peer_addr->bar4_addr32; + iowrite32(bar_addr, mmio + SNB_PBAR4XLAT_OFFSET); + bar_addr = ioread32(mmio + SNB_PBAR4XLAT_OFFSET); + dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr); + + bar_addr = peer_addr->bar5_addr32; + iowrite32(bar_addr, mmio + SNB_PBAR5XLAT_OFFSET); + bar_addr = ioread32(mmio + SNB_PBAR5XLAT_OFFSET); + dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr); + } - if (ndev->conn_type == NTB_CONN_TRANSPARENT) { - ntb_link_event(ndev, NTB_LINK_DOWN); - return; + /* set the translation offset for b2b registers */ + if (b2b_bar == 0) + bar_addr = peer_addr->bar0_addr; + else if (b2b_bar == 2) + bar_addr = peer_addr->bar2_addr64; + else if (b2b_bar == 4 && !ndev->bar4_split) + bar_addr = peer_addr->bar4_addr64; + else if (b2b_bar == 4) + bar_addr = peer_addr->bar4_addr32; + else if (b2b_bar == 5) + bar_addr = peer_addr->bar5_addr32; + else + return -EIO; + + /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */ + dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr); + iowrite32(bar_addr, mmio + SNB_B2B_XLAT_OFFSETL); + iowrite32(bar_addr >> 32, mmio + SNB_B2B_XLAT_OFFSETU); + + if (b2b_bar) { + /* map peer ntb mmio config space registers */ + ndev->peer_mmio = pci_iomap(pdev, b2b_bar, + SNB_B2B_MIN_SIZE); + if (!ndev->peer_mmio) + return -EIO; } - /* Bring NTB link down */ - ntb_cntl = readl(ndev->reg_ofs.lnk_cntl); - ntb_cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); - ntb_cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); - if (ndev->split_bar) - ntb_cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | - NTB_CNTL_S2P_BAR5_SNOOP); - ntb_cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; - writel(ntb_cntl, ndev->reg_ofs.lnk_cntl); + return 0; } -static void ntb_max_mw_detect(struct ntb_device *ndev) +static int snb_init_ntb(struct intel_ntb_dev *ndev) { - if (ndev->split_bar) - ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW; + int rc; + + if (ndev->bar4_split) + ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT; else - ndev->limits.max_mw = SNB_MAX_MW; -} + ndev->mw_count = SNB_MW_COUNT; -static int ntb_xeon_detect(struct ntb_device *ndev) -{ - int rc, bars_mask; - u32 bars; - u8 ppd; + ndev->spad_count = SNB_SPAD_COUNT; + ndev->db_count = SNB_DB_COUNT; + ndev->db_link_mask = SNB_DB_LINK_BIT; - ndev->hw_type = SNB_HW; + switch (ndev->ntb.topo) { + case NTB_TOPO_PRI: + if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { + dev_err(ndev_dev(ndev), "NTB Primary config disabled\n"); + return -EINVAL; + } + /* use half the spads for the peer */ + ndev->spad_count >>= 1; + ndev->self_reg = &snb_pri_reg; + ndev->peer_reg = &snb_sec_reg; + ndev->xlat_reg = &snb_sec_xlat; + break; - rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &ppd); - if (rc) - return -EIO; + case NTB_TOPO_SEC: + if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { + dev_err(ndev_dev(ndev), "NTB Secondary config disabled\n"); + return -EINVAL; + } + /* use half the spads for the peer */ + ndev->spad_count >>= 1; + ndev->self_reg = &snb_sec_reg; + ndev->peer_reg = &snb_pri_reg; + ndev->xlat_reg = &snb_pri_xlat; + break; - if (ppd & SNB_PPD_DEV_TYPE) - ndev->dev_type = NTB_DEV_USD; - else - ndev->dev_type = NTB_DEV_DSD; + case NTB_TOPO_B2B_USD: + case NTB_TOPO_B2B_DSD: + ndev->self_reg = &snb_pri_reg; + ndev->peer_reg = &snb_b2b_reg; + ndev->xlat_reg = &snb_sec_xlat; - ndev->split_bar = (ppd & SNB_PPD_SPLIT_BAR) ? 1 : 0; + if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { + ndev->peer_reg = &snb_pri_reg; - switch (ppd & SNB_PPD_CONN_TYPE) { - case NTB_CONN_B2B: - dev_info(&ndev->pdev->dev, "Conn Type = B2B\n"); - ndev->conn_type = NTB_CONN_B2B; - break; - case NTB_CONN_RP: - dev_info(&ndev->pdev->dev, "Conn Type = RP\n"); - ndev->conn_type = NTB_CONN_RP; - break; - case NTB_CONN_TRANSPARENT: - dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n"); - ndev->conn_type = NTB_CONN_TRANSPARENT; - /* - * This mode is default to USD/DSP. HW does not report - * properly in transparent mode as it has no knowledge of - * NTB. We will just force correct here. - */ - ndev->dev_type = NTB_DEV_USD; + if (b2b_mw_idx < 0) + ndev->b2b_idx = b2b_mw_idx + ndev->mw_count; + else + ndev->b2b_idx = b2b_mw_idx; - /* - * This is a way for transparent BAR to figure out if we - * are doing split BAR or not. There is no way for the hw - * on the transparent side to know and set the PPD. - */ - bars_mask = pci_select_bars(ndev->pdev, IORESOURCE_MEM); - bars = hweight32(bars_mask); - if (bars == (HSX_SPLITBAR_MAX_MW + 1)) - ndev->split_bar = 1; + dev_dbg(ndev_dev(ndev), + "setting up b2b mw idx %d means %d\n", + b2b_mw_idx, ndev->b2b_idx); + + } else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) { + dev_warn(ndev_dev(ndev), "Reduce doorbell count by 1\n"); + ndev->db_count -= 1; + } + + if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { + rc = snb_setup_b2b_mw(ndev, + &snb_b2b_dsd_addr, + &snb_b2b_usd_addr); + } else { + rc = snb_setup_b2b_mw(ndev, + &snb_b2b_usd_addr, + &snb_b2b_dsd_addr); + } + if (rc) + return rc; + + /* Enable Bus Master and Memory Space on the secondary side */ + iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, + ndev->self_mmio + SNB_SPCICMD_OFFSET); break; + default: - dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", ppd); - return -ENODEV; + return -EINVAL; } - ntb_max_mw_detect(ndev); + ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; + + ndev->reg->db_iowrite(ndev->db_valid_mask, + ndev->self_mmio + + ndev->self_reg->db_mask); return 0; } -static int ntb_atom_detect(struct ntb_device *ndev) +static int snb_init_dev(struct intel_ntb_dev *ndev) { - int rc; - u32 ppd; + struct pci_dev *pdev; + u8 ppd; + int rc, mem; + + /* There is a Xeon hardware errata related to writes to SDOORBELL or + * B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, + * which may hang the system. To workaround this use the second memory + * window to access the interrupt and scratch pad registers on the + * remote system. + */ + ndev->hwerr_flags |= NTB_HWERR_SDOORBELL_LOCKUP; - ndev->hw_type = BWD_HW; - ndev->limits.max_mw = BWD_MAX_MW; + /* There is a hardware errata related to accessing any register in + * SB01BASE in the presence of bidirectional traffic crossing the NTB. + */ + ndev->hwerr_flags |= NTB_HWERR_SB01BASE_LOCKUP; + + /* HW Errata on bit 14 of b2bdoorbell register. Writes will not be + * mirrored to the remote system. Shrink the number of bits by one, + * since bit 14 is the last bit. + */ + ndev->hwerr_flags |= NTB_HWERR_B2BDOORBELL_BIT14; - rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &ppd); + ndev->reg = &snb_reg; + + pdev = ndev_pdev(ndev); + + rc = pci_read_config_byte(pdev, SNB_PPD_OFFSET, &ppd); if (rc) - return rc; + return -EIO; - switch ((ppd & BWD_PPD_CONN_TYPE) >> 8) { - case NTB_CONN_B2B: - dev_info(&ndev->pdev->dev, "Conn Type = B2B\n"); - ndev->conn_type = NTB_CONN_B2B; - break; - case NTB_CONN_RP: - default: - dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n"); + ndev->ntb.topo = snb_ppd_topo(ndev, ppd); + dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd, + ntb_topo_string(ndev->ntb.topo)); + if (ndev->ntb.topo == NTB_TOPO_NONE) return -EINVAL; + + if (ndev->ntb.topo != NTB_TOPO_SEC) { + ndev->bar4_split = snb_ppd_bar4_split(ndev, ppd); + dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n", + ppd, ndev->bar4_split); + } else { + /* This is a way for transparent BAR to figure out if we are + * doing split BAR or not. There is no way for the hw on the + * transparent side to know and set the PPD. + */ + mem = pci_select_bars(pdev, IORESOURCE_MEM); + ndev->bar4_split = hweight32(mem) == + HSX_SPLIT_BAR_MW_COUNT + 1; + dev_dbg(ndev_dev(ndev), "mem %#x bar4_split %d\n", + mem, ndev->bar4_split); } - if (ppd & BWD_PPD_DEV_TYPE) - ndev->dev_type = NTB_DEV_DSD; - else - ndev->dev_type = NTB_DEV_USD; + rc = snb_init_ntb(ndev); + if (rc) + return rc; - return 0; + return snb_init_isr(ndev); +} + +static void snb_deinit_dev(struct intel_ntb_dev *ndev) +{ + snb_deinit_isr(ndev); } -static int ntb_device_detect(struct ntb_device *ndev) +static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev) { int rc; - if (is_ntb_xeon(ndev)) - rc = ntb_xeon_detect(ndev); - else if (is_ntb_atom(ndev)) - rc = ntb_atom_detect(ndev); - else - rc = -ENODEV; + pci_set_drvdata(pdev, ndev); + + rc = pci_enable_device(pdev); + if (rc) + goto err_pci_enable; + + rc = pci_request_regions(pdev, NTB_NAME); + if (rc) + goto err_pci_regions; + + pci_set_master(pdev); + + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); + if (rc) { + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (rc) + goto err_dma_mask; + dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n"); + } - dev_info(&ndev->pdev->dev, "Device Type = %s\n", - ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP"); + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + if (rc) { + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + if (rc) + goto err_dma_mask; + dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n"); + } + + ndev->self_mmio = pci_iomap(pdev, 0, 0); + if (!ndev->self_mmio) { + rc = -EIO; + goto err_mmio; + } + ndev->peer_mmio = ndev->self_mmio; return 0; + +err_mmio: +err_dma_mask: + pci_clear_master(pdev); + pci_release_regions(pdev); +err_pci_regions: + pci_disable_device(pdev); +err_pci_enable: + pci_set_drvdata(pdev, NULL); + return rc; } -static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) +static void intel_ntb_deinit_pci(struct intel_ntb_dev *ndev) { - struct ntb_device *ndev; - int rc, i; + struct pci_dev *pdev = ndev_pdev(ndev); - ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL); - if (!ndev) - return -ENOMEM; + if (ndev->peer_mmio && ndev->peer_mmio != ndev->self_mmio) + pci_iounmap(pdev, ndev->peer_mmio); + pci_iounmap(pdev, ndev->self_mmio); - ndev->pdev = pdev; + pci_clear_master(pdev); + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); +} - ntb_set_errata_flags(ndev); +static inline void ndev_init_struct(struct intel_ntb_dev *ndev, + struct pci_dev *pdev) +{ + ndev->ntb.pdev = pdev; + ndev->ntb.topo = NTB_TOPO_NONE; + ndev->ntb.ops = &intel_ntb_ops; - ndev->link_status = NTB_LINK_DOWN; - pci_set_drvdata(pdev, ndev); - ntb_setup_debugfs(ndev); + ndev->b2b_off = 0; + ndev->b2b_idx = INT_MAX; - rc = pci_enable_device(pdev); - if (rc) - goto err; + ndev->bar4_split = 0; - pci_set_master(ndev->pdev); + ndev->mw_count = 0; + ndev->spad_count = 0; + ndev->db_count = 0; + ndev->db_vec_count = 0; + ndev->db_vec_shift = 0; - rc = ntb_device_detect(ndev); - if (rc) - goto err; + ndev->ntb_ctl = 0; + ndev->lnk_sta = 0; - ndev->mw = kcalloc(ndev->limits.max_mw, sizeof(struct ntb_mw), - GFP_KERNEL); - if (!ndev->mw) { - rc = -ENOMEM; - goto err1; - } + ndev->db_valid_mask = 0; + ndev->db_link_mask = 0; + ndev->db_mask = 0; - if (ndev->split_bar) - rc = pci_request_selected_regions(pdev, NTB_SPLITBAR_MASK, - KBUILD_MODNAME); - else - rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, - KBUILD_MODNAME); + spin_lock_init(&ndev->db_mask_lock); +} - if (rc) - goto err2; +static int intel_ntb_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct intel_ntb_dev *ndev; + int rc; - ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO); - if (!ndev->reg_base) { - dev_warn(&pdev->dev, "Cannot remap BAR 0\n"); - rc = -EIO; - goto err3; - } + if (pdev_is_bwd(pdev)) { + ndev = kzalloc(sizeof(*ndev), GFP_KERNEL); + if (!ndev) { + rc = -ENOMEM; + goto err_ndev; + } - for (i = 0; i < ndev->limits.max_mw; i++) { - ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i)); + ndev_init_struct(ndev, pdev); - /* - * with the errata we need to steal last of the memory - * windows for workarounds and they point to MMIO registers. - */ - if ((ndev->wa_flags & WA_SNB_ERR) && - (i == (ndev->limits.max_mw - 1))) { - ndev->mw[i].vbase = - ioremap_nocache(pci_resource_start(pdev, - MW_TO_BAR(i)), - ndev->mw[i].bar_sz); - } else { - ndev->mw[i].vbase = - ioremap_wc(pci_resource_start(pdev, - MW_TO_BAR(i)), - ndev->mw[i].bar_sz); - } + rc = intel_ntb_init_pci(ndev, pdev); + if (rc) + goto err_init_pci; + + rc = bwd_init_dev(ndev); + if (rc) + goto err_init_dev; - dev_info(&pdev->dev, "MW %d size %llu\n", i, - (unsigned long long) ndev->mw[i].bar_sz); - if (!ndev->mw[i].vbase) { - dev_warn(&pdev->dev, "Cannot remap BAR %d\n", - MW_TO_BAR(i)); - rc = -EIO; - goto err4; + } else if (pdev_is_snb(pdev)) { + ndev = kzalloc(sizeof(*ndev), GFP_KERNEL); + if (!ndev) { + rc = -ENOMEM; + goto err_ndev; } - } - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); - if (rc) { - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); - if (rc) - goto err4; + ndev_init_struct(ndev, pdev); - dev_warn(&pdev->dev, "Cannot DMA highmem\n"); - } + rc = intel_ntb_init_pci(ndev, pdev); + if (rc) + goto err_init_pci; - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); - if (rc) { - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + rc = snb_init_dev(ndev); if (rc) - goto err4; + goto err_init_dev; - dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n"); + } else { + rc = -EINVAL; + goto err_ndev; } - rc = ntb_device_setup(ndev); - if (rc) - goto err4; - - rc = ntb_create_callbacks(ndev); - if (rc) - goto err5; + ndev_reset_unsafe_flags(ndev); - rc = ntb_setup_interrupts(ndev); - if (rc) - goto err6; + ndev->reg->poll_link(ndev); - /* The scratchpad registers keep the values between rmmod/insmod, - * blast them now - */ - for (i = 0; i < ndev->limits.max_spads; i++) { - ntb_write_local_spad(ndev, i, 0); - ntb_write_remote_spad(ndev, i, 0); - } + ndev_init_debugfs(ndev); - rc = ntb_transport_init(pdev); + rc = ntb_register_device(&ndev->ntb); if (rc) - goto err7; - - ntb_hw_link_up(ndev); + goto err_register; return 0; -err7: - ntb_free_interrupts(ndev); -err6: - ntb_free_callbacks(ndev); -err5: - ntb_device_free(ndev); -err4: - for (i--; i >= 0; i--) - iounmap(ndev->mw[i].vbase); - iounmap(ndev->reg_base); -err3: - if (ndev->split_bar) - pci_release_selected_regions(pdev, NTB_SPLITBAR_MASK); - else - pci_release_selected_regions(pdev, NTB_BAR_MASK); -err2: - kfree(ndev->mw); -err1: - pci_disable_device(pdev); -err: - ntb_free_debugfs(ndev); +err_register: + ndev_deinit_debugfs(ndev); + if (pdev_is_bwd(pdev)) + bwd_deinit_dev(ndev); + else if (pdev_is_snb(pdev)) + snb_deinit_dev(ndev); +err_init_dev: + intel_ntb_deinit_pci(ndev); +err_init_pci: kfree(ndev); - - dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME); +err_ndev: return rc; } -static void ntb_pci_remove(struct pci_dev *pdev) +static void intel_ntb_pci_remove(struct pci_dev *pdev) { - struct ntb_device *ndev = pci_get_drvdata(pdev); - int i; + struct intel_ntb_dev *ndev = pci_get_drvdata(pdev); + + ntb_unregister_device(&ndev->ntb); + ndev_deinit_debugfs(ndev); + if (pdev_is_bwd(pdev)) + bwd_deinit_dev(ndev); + else if (pdev_is_snb(pdev)) + snb_deinit_dev(ndev); + intel_ntb_deinit_pci(ndev); + kfree(ndev); +} - ntb_hw_link_down(ndev); +static const struct intel_ntb_reg bwd_reg = { + .poll_link = bwd_poll_link, + .link_is_up = bwd_link_is_up, + .db_ioread = bwd_db_ioread, + .db_iowrite = bwd_db_iowrite, + .db_size = sizeof(u64), + .ntb_ctl = BWD_NTBCNTL_OFFSET, + .mw_bar = {2, 4}, +}; - ntb_transport_free(ndev->ntb_transport); +static const struct intel_ntb_alt_reg bwd_pri_reg = { + .db_bell = BWD_PDOORBELL_OFFSET, + .db_mask = BWD_PDBMSK_OFFSET, + .spad = BWD_SPAD_OFFSET, +}; - ntb_free_interrupts(ndev); - ntb_free_callbacks(ndev); - ntb_device_free(ndev); +static const struct intel_ntb_alt_reg bwd_b2b_reg = { + .db_bell = BWD_B2B_DOORBELL_OFFSET, + .spad = BWD_B2B_SPAD_OFFSET, +}; - /* need to reset max_mw limits so we can unmap properly */ - if (ndev->hw_type == SNB_HW) - ntb_max_mw_detect(ndev); +static const struct intel_ntb_xlat_reg bwd_sec_xlat = { + /* FIXME : .bar0_base = BWD_SBAR0BASE_OFFSET, */ + /* FIXME : .bar2_limit = BWD_SBAR2LMT_OFFSET, */ + .bar2_xlat = BWD_SBAR2XLAT_OFFSET, +}; - for (i = 0; i < ndev->limits.max_mw; i++) - iounmap(ndev->mw[i].vbase); +static const struct intel_ntb_reg snb_reg = { + .poll_link = snb_poll_link, + .link_is_up = snb_link_is_up, + .db_ioread = snb_db_ioread, + .db_iowrite = snb_db_iowrite, + .db_size = sizeof(u32), + .ntb_ctl = SNB_NTBCNTL_OFFSET, + .mw_bar = {2, 4, 5}, +}; - kfree(ndev->mw); - iounmap(ndev->reg_base); - if (ndev->split_bar) - pci_release_selected_regions(pdev, NTB_SPLITBAR_MASK); - else - pci_release_selected_regions(pdev, NTB_BAR_MASK); - pci_disable_device(pdev); - ntb_free_debugfs(ndev); - kfree(ndev); -} +static const struct intel_ntb_alt_reg snb_pri_reg = { + .db_bell = SNB_PDOORBELL_OFFSET, + .db_mask = SNB_PDBMSK_OFFSET, + .spad = SNB_SPAD_OFFSET, +}; + +static const struct intel_ntb_alt_reg snb_sec_reg = { + .db_bell = SNB_SDOORBELL_OFFSET, + .db_mask = SNB_SDBMSK_OFFSET, + /* second half of the scratchpads */ + .spad = SNB_SPAD_OFFSET + (SNB_SPAD_COUNT << 1), +}; -static struct pci_driver ntb_pci_driver = { +static const struct intel_ntb_alt_reg snb_b2b_reg = { + .db_bell = SNB_B2B_DOORBELL_OFFSET, + .spad = SNB_B2B_SPAD_OFFSET, +}; + +static const struct intel_ntb_xlat_reg snb_pri_xlat = { + /* Note: no primary .bar0_base visible to the secondary side. + * + * The secondary side cannot get the base address stored in primary + * bars. The base address is necessary to set the limit register to + * any value other than zero, or unlimited. + * + * WITHOUT THE BASE ADDRESS, THE SECONDARY SIDE CANNOT DISABLE the + * window by setting the limit equal to base, nor can it limit the size + * of the memory window by setting the limit to base + size. + */ + .bar2_limit = SNB_PBAR23LMT_OFFSET, + .bar2_xlat = SNB_PBAR23XLAT_OFFSET, +}; + +static const struct intel_ntb_xlat_reg snb_sec_xlat = { + .bar0_base = SNB_SBAR0BASE_OFFSET, + .bar2_limit = SNB_SBAR23LMT_OFFSET, + .bar2_xlat = SNB_SBAR23XLAT_OFFSET, +}; + +static const struct intel_b2b_addr snb_b2b_usd_addr = { + .bar2_addr64 = SNB_B2B_BAR2_USD_ADDR64, + .bar4_addr64 = SNB_B2B_BAR4_USD_ADDR64, + .bar4_addr32 = SNB_B2B_BAR4_USD_ADDR32, + .bar5_addr32 = SNB_B2B_BAR5_USD_ADDR32, +}; + +static const struct intel_b2b_addr snb_b2b_dsd_addr = { + .bar2_addr64 = SNB_B2B_BAR2_DSD_ADDR64, + .bar4_addr64 = SNB_B2B_BAR4_DSD_ADDR64, + .bar4_addr32 = SNB_B2B_BAR4_DSD_ADDR32, + .bar5_addr32 = SNB_B2B_BAR5_DSD_ADDR32, +}; + +/* operations for primary side of local ntb */ +static const struct ntb_dev_ops intel_ntb_ops = { + .mw_count = intel_ntb_mw_count, + .mw_get_range = intel_ntb_mw_get_range, + .mw_set_trans = intel_ntb_mw_set_trans, + .link_is_up = intel_ntb_link_is_up, + .link_enable = intel_ntb_link_enable, + .link_disable = intel_ntb_link_disable, + .db_is_unsafe = intel_ntb_db_is_unsafe, + .db_valid_mask = intel_ntb_db_valid_mask, + .db_vector_count = intel_ntb_db_vector_count, + .db_vector_mask = intel_ntb_db_vector_mask, + .db_read = intel_ntb_db_read, + .db_clear = intel_ntb_db_clear, + .db_set_mask = intel_ntb_db_set_mask, + .db_clear_mask = intel_ntb_db_clear_mask, + .peer_db_addr = intel_ntb_peer_db_addr, + .peer_db_set = intel_ntb_peer_db_set, + .spad_is_unsafe = intel_ntb_spad_is_unsafe, + .spad_count = intel_ntb_spad_count, + .spad_read = intel_ntb_spad_read, + .spad_write = intel_ntb_spad_write, + .peer_spad_addr = intel_ntb_peer_spad_addr, + .peer_spad_read = intel_ntb_peer_spad_read, + .peer_spad_write = intel_ntb_peer_spad_write, +}; + +static const struct file_operations intel_ntb_debugfs_info = { + .owner = THIS_MODULE, + .open = simple_open, + .read = ndev_debugfs_read, +}; + +static const struct pci_device_id intel_ntb_pci_tbl[] = { + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)}, + {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)}, + {0} +}; +MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl); + +static struct pci_driver intel_ntb_pci_driver = { .name = KBUILD_MODNAME, - .id_table = ntb_pci_tbl, - .probe = ntb_pci_probe, - .remove = ntb_pci_remove, + .id_table = intel_ntb_pci_tbl, + .probe = intel_ntb_pci_probe, + .remove = intel_ntb_pci_remove, }; -module_pci_driver(ntb_pci_driver); +static int __init intel_ntb_pci_driver_init(void) +{ + if (debugfs_initialized()) + debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); + + return pci_register_driver(&intel_ntb_pci_driver); +} +module_init(intel_ntb_pci_driver_init); + +static void __exit intel_ntb_pci_driver_exit(void) +{ + pci_unregister_driver(&intel_ntb_pci_driver); + + debugfs_remove_recursive(debugfs_dir); +} +module_exit(intel_ntb_pci_driver_exit); + diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h index 935610454f70..fec689dc95cf 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.h +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h @@ -5,6 +5,7 @@ * GPL LICENSE SUMMARY * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as @@ -13,6 +14,7 @@ * BSD LICENSE * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,341 +47,296 @@ * Contact Information: * Jon Mason */ -#include - -#define NTB_LINK_STATUS_ACTIVE 0x2000 -#define NTB_LINK_SPEED_MASK 0x000f -#define NTB_LINK_WIDTH_MASK 0x03f0 - -#define SNB_MSIX_CNT 4 -#define SNB_MAX_B2B_SPADS 16 -#define SNB_MAX_COMPAT_SPADS 16 -/* Reserve the uppermost bit for link interrupt */ -#define SNB_MAX_DB_BITS 15 -#define SNB_LINK_DB 15 -#define SNB_DB_BITS_PER_VEC 5 -#define HSX_SPLITBAR_MAX_MW 3 -#define SNB_MAX_MW 2 -#define SNB_ERRATA_MAX_MW 1 - -#define SNB_DB_HW_LINK 0x8000 - -#define SNB_UNCERRSTS_OFFSET 0x014C -#define SNB_CORERRSTS_OFFSET 0x0158 -#define SNB_LINK_STATUS_OFFSET 0x01A2 -#define SNB_PCICMD_OFFSET 0x0504 -#define SNB_DEVCTRL_OFFSET 0x0598 -#define SNB_DEVSTS_OFFSET 0x059A -#define SNB_SLINK_STATUS_OFFSET 0x05A2 - -#define SNB_PBAR2LMT_OFFSET 0x0000 -#define SNB_PBAR4LMT_OFFSET 0x0008 -#define SNB_PBAR5LMT_OFFSET 0x000C -#define SNB_PBAR2XLAT_OFFSET 0x0010 -#define SNB_PBAR4XLAT_OFFSET 0x0018 -#define SNB_PBAR5XLAT_OFFSET 0x001C -#define SNB_SBAR2LMT_OFFSET 0x0020 -#define SNB_SBAR4LMT_OFFSET 0x0028 -#define SNB_SBAR5LMT_OFFSET 0x002C -#define SNB_SBAR2XLAT_OFFSET 0x0030 -#define SNB_SBAR4XLAT_OFFSET 0x0038 -#define SNB_SBAR5XLAT_OFFSET 0x003C -#define SNB_SBAR0BASE_OFFSET 0x0040 -#define SNB_SBAR2BASE_OFFSET 0x0048 -#define SNB_SBAR4BASE_OFFSET 0x0050 -#define SNB_SBAR5BASE_OFFSET 0x0054 -#define SNB_NTBCNTL_OFFSET 0x0058 -#define SNB_SBDF_OFFSET 0x005C -#define SNB_PDOORBELL_OFFSET 0x0060 -#define SNB_PDBMSK_OFFSET 0x0062 -#define SNB_SDOORBELL_OFFSET 0x0064 -#define SNB_SDBMSK_OFFSET 0x0066 -#define SNB_USMEMMISS_OFFSET 0x0070 -#define SNB_SPAD_OFFSET 0x0080 -#define SNB_SPADSEMA4_OFFSET 0x00c0 -#define SNB_WCCNTRL_OFFSET 0x00e0 -#define SNB_B2B_SPAD_OFFSET 0x0100 -#define SNB_B2B_DOORBELL_OFFSET 0x0140 -#define SNB_B2B_XLAT_OFFSETL 0x0144 -#define SNB_B2B_XLAT_OFFSETU 0x0148 -/* - * The addresses are setup so the 32bit BARs can function. Thus - * the addresses are all in 32bit space - */ -#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL -#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL -#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL -#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL -#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL -#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL -#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL -#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL - -#define BWD_MSIX_CNT 34 -#define BWD_MAX_SPADS 16 -#define BWD_MAX_DB_BITS 34 -#define BWD_DB_BITS_PER_VEC 1 -#define BWD_MAX_MW 2 - -#define BWD_PCICMD_OFFSET 0xb004 -#define BWD_MBAR23_OFFSET 0xb018 -#define BWD_MBAR45_OFFSET 0xb020 -#define BWD_DEVCTRL_OFFSET 0xb048 -#define BWD_LINK_STATUS_OFFSET 0xb052 -#define BWD_ERRCORSTS_OFFSET 0xb110 - -#define BWD_SBAR2XLAT_OFFSET 0x0008 -#define BWD_SBAR4XLAT_OFFSET 0x0010 -#define BWD_PDOORBELL_OFFSET 0x0020 -#define BWD_PDBMSK_OFFSET 0x0028 -#define BWD_NTBCNTL_OFFSET 0x0060 -#define BWD_EBDF_OFFSET 0x0064 -#define BWD_SPAD_OFFSET 0x0080 -#define BWD_SPADSEMA_OFFSET 0x00c0 -#define BWD_STKYSPAD_OFFSET 0x00c4 -#define BWD_PBAR2XLAT_OFFSET 0x8008 -#define BWD_PBAR4XLAT_OFFSET 0x8010 -#define BWD_B2B_DOORBELL_OFFSET 0x8020 -#define BWD_B2B_SPAD_OFFSET 0x8080 -#define BWD_B2B_SPADSEMA_OFFSET 0x80c0 -#define BWD_B2B_STKYSPAD_OFFSET 0x80c4 - -#define BWD_MODPHY_PCSREG4 0x1c004 -#define BWD_MODPHY_PCSREG6 0x1c006 - -#define BWD_IP_BASE 0xC000 -#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024) -#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180) +#ifndef NTB_HW_INTEL_H +#define NTB_HW_INTEL_H + +#include +#include + +#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 +#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 +#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 +#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D +#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E +#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F +#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D +#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E +#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F +#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D +#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E +#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F +#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E + +/* SNB hardware (and JSF, IVT, HSX) */ + +#define SNB_PBAR23LMT_OFFSET 0x0000 +#define SNB_PBAR45LMT_OFFSET 0x0008 +#define SNB_PBAR4LMT_OFFSET 0x0008 +#define SNB_PBAR5LMT_OFFSET 0x000c +#define SNB_PBAR23XLAT_OFFSET 0x0010 +#define SNB_PBAR45XLAT_OFFSET 0x0018 +#define SNB_PBAR4XLAT_OFFSET 0x0018 +#define SNB_PBAR5XLAT_OFFSET 0x001c +#define SNB_SBAR23LMT_OFFSET 0x0020 +#define SNB_SBAR45LMT_OFFSET 0x0028 +#define SNB_SBAR4LMT_OFFSET 0x0028 +#define SNB_SBAR5LMT_OFFSET 0x002c +#define SNB_SBAR23XLAT_OFFSET 0x0030 +#define SNB_SBAR45XLAT_OFFSET 0x0038 +#define SNB_SBAR4XLAT_OFFSET 0x0038 +#define SNB_SBAR5XLAT_OFFSET 0x003c +#define SNB_SBAR0BASE_OFFSET 0x0040 +#define SNB_SBAR23BASE_OFFSET 0x0048 +#define SNB_SBAR45BASE_OFFSET 0x0050 +#define SNB_SBAR4BASE_OFFSET 0x0050 +#define SNB_SBAR5BASE_OFFSET 0x0054 +#define SNB_SBDF_OFFSET 0x005c +#define SNB_NTBCNTL_OFFSET 0x0058 +#define SNB_PDOORBELL_OFFSET 0x0060 +#define SNB_PDBMSK_OFFSET 0x0062 +#define SNB_SDOORBELL_OFFSET 0x0064 +#define SNB_SDBMSK_OFFSET 0x0066 +#define SNB_USMEMMISS_OFFSET 0x0070 +#define SNB_SPAD_OFFSET 0x0080 +#define SNB_PBAR23SZ_OFFSET 0x00d0 +#define SNB_PBAR45SZ_OFFSET 0x00d1 +#define SNB_PBAR4SZ_OFFSET 0x00d1 +#define SNB_SBAR23SZ_OFFSET 0x00d2 +#define SNB_SBAR45SZ_OFFSET 0x00d3 +#define SNB_SBAR4SZ_OFFSET 0x00d3 +#define SNB_PPD_OFFSET 0x00d4 +#define SNB_PBAR5SZ_OFFSET 0x00d5 +#define SNB_SBAR5SZ_OFFSET 0x00d6 +#define SNB_WCCNTRL_OFFSET 0x00e0 +#define SNB_UNCERRSTS_OFFSET 0x014c +#define SNB_CORERRSTS_OFFSET 0x0158 +#define SNB_LINK_STATUS_OFFSET 0x01a2 +#define SNB_SPCICMD_OFFSET 0x0504 +#define SNB_DEVCTRL_OFFSET 0x0598 +#define SNB_DEVSTS_OFFSET 0x059a +#define SNB_SLINK_STATUS_OFFSET 0x05a2 +#define SNB_B2B_SPAD_OFFSET 0x0100 +#define SNB_B2B_DOORBELL_OFFSET 0x0140 +#define SNB_B2B_XLAT_OFFSETL 0x0144 +#define SNB_B2B_XLAT_OFFSETU 0x0148 +#define SNB_PPD_CONN_MASK 0x03 +#define SNB_PPD_CONN_TRANSPARENT 0x00 +#define SNB_PPD_CONN_B2B 0x01 +#define SNB_PPD_CONN_RP 0x02 +#define SNB_PPD_DEV_MASK 0x10 +#define SNB_PPD_DEV_USD 0x00 +#define SNB_PPD_DEV_DSD 0x10 +#define SNB_PPD_SPLIT_BAR_MASK 0x40 + +#define SNB_PPD_TOPO_MASK (SNB_PPD_CONN_MASK | SNB_PPD_DEV_MASK) +#define SNB_PPD_TOPO_PRI_USD (SNB_PPD_CONN_RP | SNB_PPD_DEV_USD) +#define SNB_PPD_TOPO_PRI_DSD (SNB_PPD_CONN_RP | SNB_PPD_DEV_DSD) +#define SNB_PPD_TOPO_SEC_USD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_USD) +#define SNB_PPD_TOPO_SEC_DSD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_DSD) +#define SNB_PPD_TOPO_B2B_USD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_USD) +#define SNB_PPD_TOPO_B2B_DSD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_DSD) + +#define SNB_MW_COUNT 2 +#define HSX_SPLIT_BAR_MW_COUNT 3 +#define SNB_DB_COUNT 15 +#define SNB_DB_LINK 15 +#define SNB_DB_LINK_BIT BIT_ULL(SNB_DB_LINK) +#define SNB_DB_MSIX_VECTOR_COUNT 4 +#define SNB_DB_MSIX_VECTOR_SHIFT 5 +#define SNB_DB_TOTAL_SHIFT 16 +#define SNB_SPAD_COUNT 16 + +/* BWD hardware */ + +#define BWD_SBAR2XLAT_OFFSET 0x0008 +#define BWD_PDOORBELL_OFFSET 0x0020 +#define BWD_PDBMSK_OFFSET 0x0028 +#define BWD_NTBCNTL_OFFSET 0x0060 +#define BWD_SPAD_OFFSET 0x0080 +#define BWD_PPD_OFFSET 0x00d4 +#define BWD_PBAR2XLAT_OFFSET 0x8008 +#define BWD_B2B_DOORBELL_OFFSET 0x8020 +#define BWD_B2B_SPAD_OFFSET 0x8080 +#define BWD_SPCICMD_OFFSET 0xb004 +#define BWD_LINK_STATUS_OFFSET 0xb052 +#define BWD_ERRCORSTS_OFFSET 0xb110 +#define BWD_IP_BASE 0xc000 +#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024) +#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180) #define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040) #define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324) +#define BWD_MODPHY_PCSREG4 0x1c004 +#define BWD_MODPHY_PCSREG6 0x1c006 + +#define BWD_PPD_INIT_LINK 0x0008 +#define BWD_PPD_CONN_MASK 0x0300 +#define BWD_PPD_CONN_TRANSPARENT 0x0000 +#define BWD_PPD_CONN_B2B 0x0100 +#define BWD_PPD_CONN_RP 0x0200 +#define BWD_PPD_DEV_MASK 0x1000 +#define BWD_PPD_DEV_USD 0x0000 +#define BWD_PPD_DEV_DSD 0x1000 +#define BWD_PPD_TOPO_MASK (BWD_PPD_CONN_MASK | BWD_PPD_DEV_MASK) +#define BWD_PPD_TOPO_PRI_USD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_USD) +#define BWD_PPD_TOPO_PRI_DSD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_DSD) +#define BWD_PPD_TOPO_SEC_USD (BWD_PPD_CONN_RP | BWD_PPD_DEV_USD) +#define BWD_PPD_TOPO_SEC_DSD (BWD_PPD_CONN_RP | BWD_PPD_DEV_DSD) +#define BWD_PPD_TOPO_B2B_USD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_USD) +#define BWD_PPD_TOPO_B2B_DSD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_DSD) + +#define BWD_MW_COUNT 2 +#define BWD_DB_COUNT 34 +#define BWD_DB_VALID_MASK (BIT_ULL(BWD_DB_COUNT) - 1) +#define BWD_DB_MSIX_VECTOR_COUNT 34 +#define BWD_DB_MSIX_VECTOR_SHIFT 1 +#define BWD_DB_TOTAL_SHIFT 34 +#define BWD_SPAD_COUNT 16 + +#define BWD_NTB_CTL_DOWN_BIT BIT(16) +#define BWD_NTB_CTL_ACTIVE(x) !(x & BWD_NTB_CTL_DOWN_BIT) + +#define BWD_DESKEWSTS_DBERR BIT(15) +#define BWD_LTSSMERRSTS0_UNEXPECTEDEI BIT(20) +#define BWD_LTSSMSTATEJMP_FORCEDETECT BIT(2) +#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF + +#define BWD_LINK_HB_TIMEOUT msecs_to_jiffies(1000) +#define BWD_LINK_RECOVERY_TIME msecs_to_jiffies(500) + +/* Ntb control and link status */ + +#define NTB_CTL_CFG_LOCK BIT(0) +#define NTB_CTL_DISABLE BIT(1) +#define NTB_CTL_S2P_BAR2_SNOOP BIT(2) +#define NTB_CTL_P2S_BAR2_SNOOP BIT(4) +#define NTB_CTL_S2P_BAR4_SNOOP BIT(6) +#define NTB_CTL_P2S_BAR4_SNOOP BIT(8) +#define NTB_CTL_S2P_BAR5_SNOOP BIT(12) +#define NTB_CTL_P2S_BAR5_SNOOP BIT(14) + +#define NTB_LNK_STA_ACTIVE_BIT 0x2000 +#define NTB_LNK_STA_SPEED_MASK 0x000f +#define NTB_LNK_STA_WIDTH_MASK 0x03f0 +#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT)) +#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK) +#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4) + +/* Use the following addresses for translation between b2b ntb devices in case + * the hardware default values are not reliable. */ +#define SNB_B2B_BAR0_USD_ADDR 0x1000000000000000ull +#define SNB_B2B_BAR2_USD_ADDR64 0x2000000000000000ull +#define SNB_B2B_BAR4_USD_ADDR64 0x4000000000000000ull +#define SNB_B2B_BAR4_USD_ADDR32 0x20000000u +#define SNB_B2B_BAR5_USD_ADDR32 0x40000000u +#define SNB_B2B_BAR0_DSD_ADDR 0x9000000000000000ull +#define SNB_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull +#define SNB_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull +#define SNB_B2B_BAR4_DSD_ADDR32 0xa0000000u +#define SNB_B2B_BAR5_DSD_ADDR32 0xc0000000u + +/* The peer ntb secondary config space is 32KB fixed size */ +#define SNB_B2B_MIN_SIZE 0x8000 + +/* flags to indicate hardware errata */ +#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0) +#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1) +#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2) + +/* flags to indicate unsafe api */ +#define NTB_UNSAFE_DB BIT_ULL(0) +#define NTB_UNSAFE_SPAD BIT_ULL(1) + +struct intel_ntb_dev; + +struct intel_ntb_reg { + int (*poll_link)(struct intel_ntb_dev *ndev); + int (*link_is_up)(struct intel_ntb_dev *ndev); + u64 (*db_ioread)(void __iomem *mmio); + void (*db_iowrite)(u64 db_bits, void __iomem *mmio); + unsigned long ntb_ctl; + resource_size_t db_size; + int mw_bar[]; +}; -#define BWD_DESKEWSTS_DBERR (1 << 15) -#define BWD_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) -#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2) -#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF - -#define NTB_CNTL_CFG_LOCK (1 << 0) -#define NTB_CNTL_LINK_DISABLE (1 << 1) -#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) -#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) -#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) -#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) -#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) -#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14) -#define BWD_CNTL_LINK_DOWN (1 << 16) - -#define NTB_PPD_OFFSET 0x00D4 -#define SNB_PPD_CONN_TYPE 0x0003 -#define SNB_PPD_DEV_TYPE 0x0010 -#define SNB_PPD_SPLIT_BAR (1 << 6) -#define BWD_PPD_INIT_LINK 0x0008 -#define BWD_PPD_CONN_TYPE 0x0300 -#define BWD_PPD_DEV_TYPE 0x1000 -#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 -#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 -#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 -#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D -#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E -#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F -#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D -#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E -#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F -#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D -#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E -#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F -#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E - -#ifndef readq -static inline u64 readq(void __iomem *addr) -{ - return readl(addr) | (((u64) readl(addr + 4)) << 32LL); -} -#endif - -#ifndef writeq -static inline void writeq(u64 val, void __iomem *addr) -{ - writel(val & 0xffffffff, addr); - writel(val >> 32, addr + 4); -} -#endif +struct intel_ntb_alt_reg { + unsigned long db_bell; + unsigned long db_mask; + unsigned long spad; +}; -#define NTB_BAR_MMIO 0 -#define NTB_BAR_23 2 -#define NTB_BAR_4 4 -#define NTB_BAR_5 5 - -#define NTB_BAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\ - (1 << NTB_BAR_4)) -#define NTB_SPLITBAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\ - (1 << NTB_BAR_4) | (1 << NTB_BAR_5)) - -#define NTB_HB_TIMEOUT msecs_to_jiffies(1000) - -enum ntb_hw_event { - NTB_EVENT_SW_EVENT0 = 0, - NTB_EVENT_SW_EVENT1, - NTB_EVENT_SW_EVENT2, - NTB_EVENT_HW_ERROR, - NTB_EVENT_HW_LINK_UP, - NTB_EVENT_HW_LINK_DOWN, +struct intel_ntb_xlat_reg { + unsigned long bar0_base; + unsigned long bar2_xlat; + unsigned long bar2_limit; }; -struct ntb_mw { - dma_addr_t phys_addr; - void __iomem *vbase; - resource_size_t bar_sz; +struct intel_b2b_addr { + phys_addr_t bar0_addr; + phys_addr_t bar2_addr64; + phys_addr_t bar4_addr64; + phys_addr_t bar4_addr32; + phys_addr_t bar5_addr32; }; -struct ntb_db_cb { - int (*callback)(void *data, int db_num); - unsigned int db_num; - void *data; - struct ntb_device *ndev; - struct tasklet_struct irq_work; +struct intel_ntb_vec { + struct intel_ntb_dev *ndev; + int num; }; -#define WA_SNB_ERR 0x00000001 - -struct ntb_device { - struct pci_dev *pdev; - struct msix_entry *msix_entries; - void __iomem *reg_base; - struct ntb_mw *mw; - struct { - unsigned char max_mw; - unsigned char max_spads; - unsigned char max_db_bits; - unsigned char msix_cnt; - } limits; - struct { - void __iomem *ldb; - void __iomem *ldb_mask; - void __iomem *rdb; - void __iomem *bar2_xlat; - void __iomem *bar4_xlat; - void __iomem *bar5_xlat; - void __iomem *spad_write; - void __iomem *spad_read; - void __iomem *lnk_cntl; - void __iomem *lnk_stat; - void __iomem *spci_cmd; - } reg_ofs; - struct ntb_transport *ntb_transport; - void (*event_cb)(void *handle, enum ntb_hw_event event); - - struct ntb_db_cb *db_cb; - unsigned char hw_type; - unsigned char conn_type; - unsigned char dev_type; - unsigned char num_msix; - unsigned char bits_per_vector; - unsigned char max_cbs; - unsigned char link_width; - unsigned char link_speed; - unsigned char link_status; - unsigned char split_bar; - - struct delayed_work hb_timer; - unsigned long last_ts; - - struct delayed_work lr_timer; - - struct dentry *debugfs_dir; - struct dentry *debugfs_info; - - unsigned int wa_flags; +struct intel_ntb_dev { + struct ntb_dev ntb; + + /* offset of peer bar0 in b2b bar */ + unsigned long b2b_off; + /* mw idx used to access peer bar0 */ + unsigned int b2b_idx; + + /* BAR45 is split into BAR4 and BAR5 */ + bool bar4_split; + + u32 ntb_ctl; + u32 lnk_sta; + + unsigned char mw_count; + unsigned char spad_count; + unsigned char db_count; + unsigned char db_vec_count; + unsigned char db_vec_shift; + + u64 db_valid_mask; + u64 db_link_mask; + u64 db_mask; + + /* synchronize rmw access of db_mask and hw reg */ + spinlock_t db_mask_lock; + + struct msix_entry *msix; + struct intel_ntb_vec *vec; + + const struct intel_ntb_reg *reg; + const struct intel_ntb_alt_reg *self_reg; + const struct intel_ntb_alt_reg *peer_reg; + const struct intel_ntb_xlat_reg *xlat_reg; + void __iomem *self_mmio; + void __iomem *peer_mmio; + phys_addr_t peer_addr; + + unsigned long last_ts; + struct delayed_work hb_timer; + + unsigned long hwerr_flags; + unsigned long unsafe_flags; + unsigned long unsafe_flags_ignore; + + struct dentry *debugfs_dir; + struct dentry *debugfs_info; }; -/** - * ntb_max_cbs() - return the max callbacks - * @ndev: pointer to ntb_device instance - * - * Given the ntb pointer, return the maximum number of callbacks - * - * RETURNS: the maximum number of callbacks - */ -static inline unsigned char ntb_max_cbs(struct ntb_device *ndev) -{ - return ndev->max_cbs; -} - -/** - * ntb_max_mw() - return the max number of memory windows - * @ndev: pointer to ntb_device instance - * - * Given the ntb pointer, return the maximum number of memory windows - * - * RETURNS: the maximum number of memory windows - */ -static inline unsigned char ntb_max_mw(struct ntb_device *ndev) -{ - return ndev->limits.max_mw; -} - -/** - * ntb_hw_link_status() - return the hardware link status - * @ndev: pointer to ntb_device instance - * - * Returns true if the hardware is connected to the remote system - * - * RETURNS: true or false based on the hardware link state - */ -static inline bool ntb_hw_link_status(struct ntb_device *ndev) -{ - return ndev->link_status == NTB_LINK_UP; -} - -/** - * ntb_query_pdev() - return the pci_dev pointer - * @ndev: pointer to ntb_device instance - * - * Given the ntb pointer, return the pci_dev pointer for the NTB hardware device - * - * RETURNS: a pointer to the ntb pci_dev - */ -static inline struct pci_dev *ntb_query_pdev(struct ntb_device *ndev) -{ - return ndev->pdev; -} - -/** - * ntb_query_debugfs() - return the debugfs pointer - * @ndev: pointer to ntb_device instance - * - * Given the ntb pointer, return the debugfs directory pointer for the NTB - * hardware device - * - * RETURNS: a pointer to the debugfs directory - */ -static inline struct dentry *ntb_query_debugfs(struct ntb_device *ndev) -{ - return ndev->debugfs_dir; -} - -struct ntb_device *ntb_register_transport(struct pci_dev *pdev, - void *transport); -void ntb_unregister_transport(struct ntb_device *ndev); -void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr); -int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx, - void *data, int (*db_cb_func)(void *data, - int db_num)); -void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx); -int ntb_register_event_callback(struct ntb_device *ndev, - void (*event_cb_func)(void *handle, - enum ntb_hw_event event)); -void ntb_unregister_event_callback(struct ntb_device *ndev); -int ntb_get_max_spads(struct ntb_device *ndev); -int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val); -int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val); -int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val); -int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val); -resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw); -void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw); -u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw); -void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int idx); -void *ntb_find_transport(struct pci_dev *pdev); - -int ntb_transport_init(struct pci_dev *pdev); -void ntb_transport_free(void *transport); +#define ndev_pdev(ndev) ((ndev)->ntb.pdev) +#define ndev_name(ndev) pci_name(ndev_pdev(ndev)) +#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev) +#define ntb_ndev(ntb) container_of(ntb, struct intel_ntb_dev, ntb) +#define hb_ndev(work) container_of(work, struct intel_ntb_dev, hb_timer.work) + +#endif diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index c5f26cda9f97..9faf1c6029af 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -5,6 +5,7 @@ * GPL LICENSE SUMMARY * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as @@ -13,6 +14,7 @@ * BSD LICENSE * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -40,7 +42,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Intel PCIe NTB Linux driver + * PCIe NTB Transport Linux driver * * Contact Information: * Jon Mason @@ -56,9 +58,22 @@ #include #include #include -#include "hw/intel/ntb_hw_intel.h" +#include "linux/ntb.h" +#include "linux/ntb_transport.h" -#define NTB_TRANSPORT_VERSION 3 +#define NTB_TRANSPORT_VERSION 4 +#define NTB_TRANSPORT_VER "4" +#define NTB_TRANSPORT_NAME "ntb_transport" +#define NTB_TRANSPORT_DESC "Software Queue-Pair Transport over NTB" + +MODULE_DESCRIPTION(NTB_TRANSPORT_DESC); +MODULE_VERSION(NTB_TRANSPORT_VER); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Intel Corporation"); + +static unsigned long max_mw_size; +module_param(max_mw_size, ulong, 0644); +MODULE_PARM_DESC(max_mw_size, "Limit size of large memory windows"); static unsigned int transport_mtu = 0x401E; module_param(transport_mtu, uint, 0644); @@ -72,10 +87,12 @@ static unsigned int copy_bytes = 1024; module_param(copy_bytes, uint, 0644); MODULE_PARM_DESC(copy_bytes, "Threshold under which NTB will use the CPU to copy instead of DMA"); +static struct dentry *nt_debugfs_dir; + struct ntb_queue_entry { /* ntb_queue list reference */ struct list_head entry; - /* pointers to data to be transfered */ + /* pointers to data to be transferred */ void *cb_data; void *buf; unsigned int len; @@ -94,14 +111,16 @@ struct ntb_rx_info { }; struct ntb_transport_qp { - struct ntb_transport *transport; - struct ntb_device *ndev; + struct ntb_transport_ctx *transport; + struct ntb_dev *ndev; void *cb_data; struct dma_chan *dma_chan; bool client_ready; - bool qp_link; + bool link_is_up; + u8 qp_num; /* Only 64 QP's are allowed. 0-63 */ + u64 qp_bit; struct ntb_rx_info __iomem *rx_info; struct ntb_rx_info *remote_rx_info; @@ -127,6 +146,7 @@ struct ntb_transport_qp { unsigned int rx_max_entry; unsigned int rx_max_frame; dma_cookie_t last_cookie; + struct tasklet_struct rxc_db_work; void (*event_handler)(void *data, int status); struct delayed_work link_work; @@ -153,33 +173,44 @@ struct ntb_transport_qp { }; struct ntb_transport_mw { - size_t size; + phys_addr_t phys_addr; + resource_size_t phys_size; + resource_size_t xlat_align; + resource_size_t xlat_align_size; + void __iomem *vbase; + size_t xlat_size; + size_t buff_size; void *virt_addr; dma_addr_t dma_addr; }; struct ntb_transport_client_dev { struct list_head entry; + struct ntb_transport_ctx *nt; struct device dev; }; -struct ntb_transport { +struct ntb_transport_ctx { struct list_head entry; struct list_head client_devs; - struct ntb_device *ndev; - struct ntb_transport_mw *mw; - struct ntb_transport_qp *qps; - unsigned int max_qps; - unsigned long qp_bitmap; - bool transport_link; + struct ntb_dev *ndev; + + struct ntb_transport_mw *mw_vec; + struct ntb_transport_qp *qp_vec; + unsigned int mw_count; + unsigned int qp_count; + u64 qp_bitmap; + u64 qp_bitmap_free; + + bool link_is_up; struct delayed_work link_work; struct work_struct link_cleanup; }; enum { - DESC_DONE_FLAG = 1 << 0, - LINK_DOWN_FLAG = 1 << 1, + DESC_DONE_FLAG = BIT(0), + LINK_DOWN_FLAG = BIT(1), }; struct ntb_payload_header { @@ -200,68 +231,69 @@ enum { MAX_SPAD, }; -#define QP_TO_MW(ndev, qp) ((qp) % ntb_max_mw(ndev)) +#define dev_client_dev(__dev) \ + container_of((__dev), struct ntb_transport_client_dev, dev) + +#define drv_client(__drv) \ + container_of((__drv), struct ntb_transport_client, driver) + +#define QP_TO_MW(nt, qp) ((qp) % nt->mw_count) #define NTB_QP_DEF_NUM_ENTRIES 100 #define NTB_LINK_DOWN_TIMEOUT 10 -static int ntb_match_bus(struct device *dev, struct device_driver *drv) +static void ntb_transport_rxc_db(unsigned long data); +static const struct ntb_ctx_ops ntb_transport_ops; +static struct ntb_client ntb_transport_client; + +static int ntb_transport_bus_match(struct device *dev, + struct device_driver *drv) { return !strncmp(dev_name(dev), drv->name, strlen(drv->name)); } -static int ntb_client_probe(struct device *dev) +static int ntb_transport_bus_probe(struct device *dev) { - const struct ntb_client *drv = container_of(dev->driver, - struct ntb_client, driver); - struct pci_dev *pdev = container_of(dev->parent, struct pci_dev, dev); + const struct ntb_transport_client *client; int rc = -EINVAL; get_device(dev); - if (drv && drv->probe) - rc = drv->probe(pdev); + + client = drv_client(dev->driver); + rc = client->probe(dev); if (rc) put_device(dev); return rc; } -static int ntb_client_remove(struct device *dev) +static int ntb_transport_bus_remove(struct device *dev) { - const struct ntb_client *drv = container_of(dev->driver, - struct ntb_client, driver); - struct pci_dev *pdev = container_of(dev->parent, struct pci_dev, dev); + const struct ntb_transport_client *client; - if (drv && drv->remove) - drv->remove(pdev); + client = drv_client(dev->driver); + client->remove(dev); put_device(dev); return 0; } -static struct bus_type ntb_bus_type = { - .name = "ntb_bus", - .match = ntb_match_bus, - .probe = ntb_client_probe, - .remove = ntb_client_remove, +static struct bus_type ntb_transport_bus = { + .name = "ntb_transport", + .match = ntb_transport_bus_match, + .probe = ntb_transport_bus_probe, + .remove = ntb_transport_bus_remove, }; static LIST_HEAD(ntb_transport_list); -static int ntb_bus_init(struct ntb_transport *nt) +static int ntb_bus_init(struct ntb_transport_ctx *nt) { - if (list_empty(&ntb_transport_list)) { - int rc = bus_register(&ntb_bus_type); - if (rc) - return rc; - } - list_add(&nt->entry, &ntb_transport_list); - return 0; } -static void ntb_bus_remove(struct ntb_transport *nt) +static void ntb_bus_remove(struct ntb_transport_ctx *nt) { struct ntb_transport_client_dev *client_dev, *cd; @@ -273,29 +305,26 @@ static void ntb_bus_remove(struct ntb_transport *nt) } list_del(&nt->entry); - - if (list_empty(&ntb_transport_list)) - bus_unregister(&ntb_bus_type); } -static void ntb_client_release(struct device *dev) +static void ntb_transport_client_release(struct device *dev) { struct ntb_transport_client_dev *client_dev; - client_dev = container_of(dev, struct ntb_transport_client_dev, dev); + client_dev = dev_client_dev(dev); kfree(client_dev); } /** - * ntb_unregister_client_dev - Unregister NTB client device + * ntb_transport_unregister_client_dev - Unregister NTB client device * @device_name: Name of NTB client device * * Unregister an NTB client device with the NTB transport layer */ -void ntb_unregister_client_dev(char *device_name) +void ntb_transport_unregister_client_dev(char *device_name) { struct ntb_transport_client_dev *client, *cd; - struct ntb_transport *nt; + struct ntb_transport_ctx *nt; list_for_each_entry(nt, &ntb_transport_list, entry) list_for_each_entry_safe(client, cd, &nt->client_devs, entry) @@ -305,18 +334,18 @@ void ntb_unregister_client_dev(char *device_name) device_unregister(&client->dev); } } -EXPORT_SYMBOL_GPL(ntb_unregister_client_dev); +EXPORT_SYMBOL_GPL(ntb_transport_unregister_client_dev); /** - * ntb_register_client_dev - Register NTB client device + * ntb_transport_register_client_dev - Register NTB client device * @device_name: Name of NTB client device * * Register an NTB client device with the NTB transport layer */ -int ntb_register_client_dev(char *device_name) +int ntb_transport_register_client_dev(char *device_name) { struct ntb_transport_client_dev *client_dev; - struct ntb_transport *nt; + struct ntb_transport_ctx *nt; int rc, i = 0; if (list_empty(&ntb_transport_list)) @@ -325,7 +354,7 @@ int ntb_register_client_dev(char *device_name) list_for_each_entry(nt, &ntb_transport_list, entry) { struct device *dev; - client_dev = kzalloc(sizeof(struct ntb_transport_client_dev), + client_dev = kzalloc(sizeof(*client_dev), GFP_KERNEL); if (!client_dev) { rc = -ENOMEM; @@ -336,9 +365,9 @@ int ntb_register_client_dev(char *device_name) /* setup and register client devices */ dev_set_name(dev, "%s%d", device_name, i); - dev->bus = &ntb_bus_type; - dev->release = ntb_client_release; - dev->parent = &ntb_query_pdev(nt->ndev)->dev; + dev->bus = &ntb_transport_bus; + dev->release = ntb_transport_client_release; + dev->parent = &nt->ndev->dev; rc = device_register(dev); if (rc) { @@ -353,11 +382,11 @@ int ntb_register_client_dev(char *device_name) return 0; err: - ntb_unregister_client_dev(device_name); + ntb_transport_unregister_client_dev(device_name); return rc; } -EXPORT_SYMBOL_GPL(ntb_register_client_dev); +EXPORT_SYMBOL_GPL(ntb_transport_register_client_dev); /** * ntb_transport_register_client - Register NTB client driver @@ -367,9 +396,9 @@ EXPORT_SYMBOL_GPL(ntb_register_client_dev); * * RETURNS: An appropriate -ERRNO error value on error, or zero for success. */ -int ntb_transport_register_client(struct ntb_client *drv) +int ntb_transport_register_client(struct ntb_transport_client *drv) { - drv->driver.bus = &ntb_bus_type; + drv->driver.bus = &ntb_transport_bus; if (list_empty(&ntb_transport_list)) return -ENODEV; @@ -386,7 +415,7 @@ EXPORT_SYMBOL_GPL(ntb_transport_register_client); * * RETURNS: An appropriate -ERRNO error value on error, or zero for success. */ -void ntb_transport_unregister_client(struct ntb_client *drv) +void ntb_transport_unregister_client(struct ntb_transport_client *drv) { driver_unregister(&drv->driver); } @@ -452,8 +481,8 @@ static ssize_t debugfs_read(struct file *filp, char __user *ubuf, size_t count, "tx_max_entry - \t%u\n", qp->tx_max_entry); out_offset += snprintf(buf + out_offset, out_count - out_offset, - "\nQP Link %s\n", (qp->qp_link == NTB_LINK_UP) ? - "Up" : "Down"); + "\nQP Link %s\n", + qp->link_is_up ? "Up" : "Down"); if (out_offset > out_count) out_offset = out_count; @@ -497,26 +526,31 @@ out: return entry; } -static void ntb_transport_setup_qp_mw(struct ntb_transport *nt, - unsigned int qp_num) +static int ntb_transport_setup_qp_mw(struct ntb_transport_ctx *nt, + unsigned int qp_num) { - struct ntb_transport_qp *qp = &nt->qps[qp_num]; + struct ntb_transport_qp *qp = &nt->qp_vec[qp_num]; + struct ntb_transport_mw *mw; unsigned int rx_size, num_qps_mw; - u8 mw_num, mw_max; + unsigned int mw_num, mw_count, qp_count; unsigned int i; - mw_max = ntb_max_mw(nt->ndev); - mw_num = QP_TO_MW(nt->ndev, qp_num); + mw_count = nt->mw_count; + qp_count = nt->qp_count; - WARN_ON(nt->mw[mw_num].virt_addr == NULL); + mw_num = QP_TO_MW(nt, qp_num); + mw = &nt->mw_vec[mw_num]; + + if (!mw->virt_addr) + return -ENOMEM; - if (nt->max_qps % mw_max && mw_num + 1 < nt->max_qps / mw_max) - num_qps_mw = nt->max_qps / mw_max + 1; + if (qp_count % mw_count && mw_num + 1 < qp_count / mw_count) + num_qps_mw = qp_count / mw_count + 1; else - num_qps_mw = nt->max_qps / mw_max; + num_qps_mw = qp_count / mw_count; - rx_size = (unsigned int) nt->mw[mw_num].size / num_qps_mw; - qp->rx_buff = nt->mw[mw_num].virt_addr + qp_num / mw_max * rx_size; + rx_size = (unsigned int)mw->xlat_size / num_qps_mw; + qp->rx_buff = mw->virt_addr + rx_size * qp_num / mw_count; rx_size -= sizeof(struct ntb_rx_info); qp->remote_rx_info = qp->rx_buff + rx_size; @@ -530,49 +564,63 @@ static void ntb_transport_setup_qp_mw(struct ntb_transport *nt, /* setup the hdr offsets with 0's */ for (i = 0; i < qp->rx_max_entry; i++) { - void *offset = qp->rx_buff + qp->rx_max_frame * (i + 1) - - sizeof(struct ntb_payload_header); + void *offset = (qp->rx_buff + qp->rx_max_frame * (i + 1) - + sizeof(struct ntb_payload_header)); memset(offset, 0, sizeof(struct ntb_payload_header)); } qp->rx_pkts = 0; qp->tx_pkts = 0; qp->tx_index = 0; + + return 0; } -static void ntb_free_mw(struct ntb_transport *nt, int num_mw) +static void ntb_free_mw(struct ntb_transport_ctx *nt, int num_mw) { - struct ntb_transport_mw *mw = &nt->mw[num_mw]; - struct pci_dev *pdev = ntb_query_pdev(nt->ndev); + struct ntb_transport_mw *mw = &nt->mw_vec[num_mw]; + struct pci_dev *pdev = nt->ndev->pdev; if (!mw->virt_addr) return; - dma_free_coherent(&pdev->dev, mw->size, mw->virt_addr, mw->dma_addr); + ntb_mw_clear_trans(nt->ndev, num_mw); + dma_free_coherent(&pdev->dev, mw->buff_size, + mw->virt_addr, mw->dma_addr); + mw->xlat_size = 0; + mw->buff_size = 0; mw->virt_addr = NULL; } -static int ntb_set_mw(struct ntb_transport *nt, int num_mw, unsigned int size) +static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw, + unsigned int size) { - struct ntb_transport_mw *mw = &nt->mw[num_mw]; - struct pci_dev *pdev = ntb_query_pdev(nt->ndev); + struct ntb_transport_mw *mw = &nt->mw_vec[num_mw]; + struct pci_dev *pdev = nt->ndev->pdev; + unsigned int xlat_size, buff_size; + int rc; + + xlat_size = round_up(size, mw->xlat_align_size); + buff_size = round_up(size, mw->xlat_align); /* No need to re-setup */ - if (mw->size == ALIGN(size, 4096)) + if (mw->xlat_size == xlat_size) return 0; - if (mw->size != 0) + if (mw->buff_size) ntb_free_mw(nt, num_mw); - /* Alloc memory for receiving data. Must be 4k aligned */ - mw->size = ALIGN(size, 4096); + /* Alloc memory for receiving data. Must be aligned */ + mw->xlat_size = xlat_size; + mw->buff_size = buff_size; - mw->virt_addr = dma_alloc_coherent(&pdev->dev, mw->size, &mw->dma_addr, - GFP_KERNEL); + mw->virt_addr = dma_alloc_coherent(&pdev->dev, buff_size, + &mw->dma_addr, GFP_KERNEL); if (!mw->virt_addr) { - mw->size = 0; - dev_err(&pdev->dev, "Unable to allocate MW buffer of size %d\n", - (int) mw->size); + mw->xlat_size = 0; + mw->buff_size = 0; + dev_err(&pdev->dev, "Unable to alloc MW buff of size %d\n", + buff_size); return -ENOMEM; } @@ -582,34 +630,39 @@ static int ntb_set_mw(struct ntb_transport *nt, int num_mw, unsigned int size) * is a requirement of the hardware. It is recommended to setup CMA * for BAR sizes equal or greater than 4MB. */ - if (!IS_ALIGNED(mw->dma_addr, mw->size)) { - dev_err(&pdev->dev, "DMA memory %pad not aligned to BAR size\n", + if (!IS_ALIGNED(mw->dma_addr, mw->xlat_align)) { + dev_err(&pdev->dev, "DMA memory %pad is not aligned\n", &mw->dma_addr); ntb_free_mw(nt, num_mw); return -ENOMEM; } /* Notify HW the memory location of the receive buffer */ - ntb_set_mw_addr(nt->ndev, num_mw, mw->dma_addr); + rc = ntb_mw_set_trans(nt->ndev, num_mw, mw->dma_addr, mw->xlat_size); + if (rc) { + dev_err(&pdev->dev, "Unable to set mw%d translation", num_mw); + ntb_free_mw(nt, num_mw); + return -EIO; + } return 0; } static void ntb_qp_link_cleanup(struct ntb_transport_qp *qp) { - struct ntb_transport *nt = qp->transport; - struct pci_dev *pdev = ntb_query_pdev(nt->ndev); + struct ntb_transport_ctx *nt = qp->transport; + struct pci_dev *pdev = nt->ndev->pdev; - if (qp->qp_link == NTB_LINK_DOWN) { + if (qp->link_is_up) { cancel_delayed_work_sync(&qp->link_work); return; } - if (qp->event_handler) - qp->event_handler(qp->cb_data, NTB_LINK_DOWN); - dev_info(&pdev->dev, "qp %d: Link Down\n", qp->qp_num); - qp->qp_link = NTB_LINK_DOWN; + qp->link_is_up = false; + + if (qp->event_handler) + qp->event_handler(qp->cb_data, qp->link_is_up); } static void ntb_qp_link_cleanup_work(struct work_struct *work) @@ -617,11 +670,11 @@ static void ntb_qp_link_cleanup_work(struct work_struct *work) struct ntb_transport_qp *qp = container_of(work, struct ntb_transport_qp, link_cleanup); - struct ntb_transport *nt = qp->transport; + struct ntb_transport_ctx *nt = qp->transport; ntb_qp_link_cleanup(qp); - if (nt->transport_link == NTB_LINK_UP) + if (nt->link_is_up) schedule_delayed_work(&qp->link_work, msecs_to_jiffies(NTB_LINK_DOWN_TIMEOUT)); } @@ -631,180 +684,132 @@ static void ntb_qp_link_down(struct ntb_transport_qp *qp) schedule_work(&qp->link_cleanup); } -static void ntb_transport_link_cleanup(struct ntb_transport *nt) +static void ntb_transport_link_cleanup(struct ntb_transport_ctx *nt) { + struct ntb_transport_qp *qp; + u64 qp_bitmap_alloc; int i; + qp_bitmap_alloc = nt->qp_bitmap & ~nt->qp_bitmap_free; + /* Pass along the info to any clients */ - for (i = 0; i < nt->max_qps; i++) - if (!test_bit(i, &nt->qp_bitmap)) - ntb_qp_link_cleanup(&nt->qps[i]); + for (i = 0; i < nt->qp_count; i++) + if (qp_bitmap_alloc & BIT_ULL(i)) { + qp = &nt->qp_vec[i]; + ntb_qp_link_cleanup(qp); + cancel_work_sync(&qp->link_cleanup); + cancel_delayed_work_sync(&qp->link_work); + } - if (nt->transport_link == NTB_LINK_DOWN) + if (!nt->link_is_up) cancel_delayed_work_sync(&nt->link_work); - else - nt->transport_link = NTB_LINK_DOWN; /* The scratchpad registers keep the values if the remote side * goes down, blast them now to give them a sane value the next * time they are accessed */ for (i = 0; i < MAX_SPAD; i++) - ntb_write_local_spad(nt->ndev, i, 0); + ntb_spad_write(nt->ndev, i, 0); } static void ntb_transport_link_cleanup_work(struct work_struct *work) { - struct ntb_transport *nt = container_of(work, struct ntb_transport, - link_cleanup); + struct ntb_transport_ctx *nt = + container_of(work, struct ntb_transport_ctx, link_cleanup); ntb_transport_link_cleanup(nt); } -static void ntb_transport_event_callback(void *data, enum ntb_hw_event event) +static void ntb_transport_event_callback(void *data) { - struct ntb_transport *nt = data; + struct ntb_transport_ctx *nt = data; - switch (event) { - case NTB_EVENT_HW_LINK_UP: + if (ntb_link_is_up(nt->ndev, NULL, NULL) == 1) schedule_delayed_work(&nt->link_work, 0); - break; - case NTB_EVENT_HW_LINK_DOWN: + else schedule_work(&nt->link_cleanup); - break; - default: - BUG(); - } } static void ntb_transport_link_work(struct work_struct *work) { - struct ntb_transport *nt = container_of(work, struct ntb_transport, - link_work.work); - struct ntb_device *ndev = nt->ndev; - struct pci_dev *pdev = ntb_query_pdev(ndev); + struct ntb_transport_ctx *nt = + container_of(work, struct ntb_transport_ctx, link_work.work); + struct ntb_dev *ndev = nt->ndev; + struct pci_dev *pdev = ndev->pdev; + resource_size_t size; u32 val; - int rc, i; + int rc, i, spad; /* send the local info, in the opposite order of the way we read it */ - for (i = 0; i < ntb_max_mw(ndev); i++) { - rc = ntb_write_remote_spad(ndev, MW0_SZ_HIGH + (i * 2), - ntb_get_mw_size(ndev, i) >> 32); - if (rc) { - dev_err(&pdev->dev, "Error writing %u to remote spad %d\n", - (u32)(ntb_get_mw_size(ndev, i) >> 32), - MW0_SZ_HIGH + (i * 2)); - goto out; - } + for (i = 0; i < nt->mw_count; i++) { + size = nt->mw_vec[i].phys_size; - rc = ntb_write_remote_spad(ndev, MW0_SZ_LOW + (i * 2), - (u32) ntb_get_mw_size(ndev, i)); - if (rc) { - dev_err(&pdev->dev, "Error writing %u to remote spad %d\n", - (u32) ntb_get_mw_size(ndev, i), - MW0_SZ_LOW + (i * 2)); - goto out; - } - } + if (max_mw_size && size > max_mw_size) + size = max_mw_size; - rc = ntb_write_remote_spad(ndev, NUM_MWS, ntb_max_mw(ndev)); - if (rc) { - dev_err(&pdev->dev, "Error writing %x to remote spad %d\n", - ntb_max_mw(ndev), NUM_MWS); - goto out; - } + spad = MW0_SZ_HIGH + (i * 2); + ntb_peer_spad_write(ndev, spad, (u32)(size >> 32)); - rc = ntb_write_remote_spad(ndev, NUM_QPS, nt->max_qps); - if (rc) { - dev_err(&pdev->dev, "Error writing %x to remote spad %d\n", - nt->max_qps, NUM_QPS); - goto out; + spad = MW0_SZ_LOW + (i * 2); + ntb_peer_spad_write(ndev, spad, (u32)size); } - rc = ntb_write_remote_spad(ndev, VERSION, NTB_TRANSPORT_VERSION); - if (rc) { - dev_err(&pdev->dev, "Error writing %x to remote spad %d\n", - NTB_TRANSPORT_VERSION, VERSION); - goto out; - } + ntb_peer_spad_write(ndev, NUM_MWS, nt->mw_count); - /* Query the remote side for its info */ - rc = ntb_read_remote_spad(ndev, VERSION, &val); - if (rc) { - dev_err(&pdev->dev, "Error reading remote spad %d\n", VERSION); - goto out; - } + ntb_peer_spad_write(ndev, NUM_QPS, nt->qp_count); - if (val != NTB_TRANSPORT_VERSION) - goto out; - dev_dbg(&pdev->dev, "Remote version = %d\n", val); + ntb_peer_spad_write(ndev, VERSION, NTB_TRANSPORT_VERSION); - rc = ntb_read_remote_spad(ndev, NUM_QPS, &val); - if (rc) { - dev_err(&pdev->dev, "Error reading remote spad %d\n", NUM_QPS); + /* Query the remote side for its info */ + val = ntb_peer_spad_read(ndev, VERSION); + dev_dbg(&pdev->dev, "Remote version = %d\n", val); + if (val != NTB_TRANSPORT_VERSION) goto out; - } - if (val != nt->max_qps) - goto out; + val = ntb_peer_spad_read(ndev, NUM_QPS); dev_dbg(&pdev->dev, "Remote max number of qps = %d\n", val); - - rc = ntb_read_remote_spad(ndev, NUM_MWS, &val); - if (rc) { - dev_err(&pdev->dev, "Error reading remote spad %d\n", NUM_MWS); + if (val != nt->qp_count) goto out; - } - if (val != ntb_max_mw(ndev)) - goto out; + val = ntb_peer_spad_read(ndev, NUM_MWS); dev_dbg(&pdev->dev, "Remote number of mws = %d\n", val); + if (val != nt->mw_count) + goto out; - for (i = 0; i < ntb_max_mw(ndev); i++) { + for (i = 0; i < nt->mw_count; i++) { u64 val64; - rc = ntb_read_remote_spad(ndev, MW0_SZ_HIGH + (i * 2), &val); - if (rc) { - dev_err(&pdev->dev, "Error reading remote spad %d\n", - MW0_SZ_HIGH + (i * 2)); - goto out1; - } - - val64 = (u64) val << 32; - - rc = ntb_read_remote_spad(ndev, MW0_SZ_LOW + (i * 2), &val); - if (rc) { - dev_err(&pdev->dev, "Error reading remote spad %d\n", - MW0_SZ_LOW + (i * 2)); - goto out1; - } + val = ntb_peer_spad_read(ndev, MW0_SZ_HIGH + (i * 2)); + val64 = (u64)val << 32; + val = ntb_peer_spad_read(ndev, MW0_SZ_LOW + (i * 2)); val64 |= val; - dev_dbg(&pdev->dev, "Remote MW%d size = %llu\n", i, val64); + dev_dbg(&pdev->dev, "Remote MW%d size = %#llx\n", i, val64); rc = ntb_set_mw(nt, i, val64); if (rc) goto out1; } - nt->transport_link = NTB_LINK_UP; + nt->link_is_up = true; - for (i = 0; i < nt->max_qps; i++) { - struct ntb_transport_qp *qp = &nt->qps[i]; + for (i = 0; i < nt->qp_count; i++) { + struct ntb_transport_qp *qp = &nt->qp_vec[i]; ntb_transport_setup_qp_mw(nt, i); - if (qp->client_ready == NTB_LINK_UP) + if (qp->client_ready) schedule_delayed_work(&qp->link_work, 0); } return; out1: - for (i = 0; i < ntb_max_mw(ndev); i++) + for (i = 0; i < nt->mw_count; i++) ntb_free_mw(nt, i); out: - if (ntb_hw_link_status(ndev)) + if (ntb_link_is_up(ndev, NULL, NULL) == 1) schedule_delayed_work(&nt->link_work, msecs_to_jiffies(NTB_LINK_DOWN_TIMEOUT)); } @@ -814,73 +819,73 @@ static void ntb_qp_link_work(struct work_struct *work) struct ntb_transport_qp *qp = container_of(work, struct ntb_transport_qp, link_work.work); - struct pci_dev *pdev = ntb_query_pdev(qp->ndev); - struct ntb_transport *nt = qp->transport; - int rc, val; + struct pci_dev *pdev = qp->ndev->pdev; + struct ntb_transport_ctx *nt = qp->transport; + int val; - WARN_ON(nt->transport_link != NTB_LINK_UP); + WARN_ON(!nt->link_is_up); - rc = ntb_read_local_spad(nt->ndev, QP_LINKS, &val); - if (rc) { - dev_err(&pdev->dev, "Error reading spad %d\n", QP_LINKS); - return; - } + val = ntb_spad_read(nt->ndev, QP_LINKS); - rc = ntb_write_remote_spad(nt->ndev, QP_LINKS, val | 1 << qp->qp_num); - if (rc) - dev_err(&pdev->dev, "Error writing %x to remote spad %d\n", - val | 1 << qp->qp_num, QP_LINKS); + ntb_peer_spad_write(nt->ndev, QP_LINKS, val | BIT(qp->qp_num)); /* query remote spad for qp ready bits */ - rc = ntb_read_remote_spad(nt->ndev, QP_LINKS, &val); - if (rc) - dev_err(&pdev->dev, "Error reading remote spad %d\n", QP_LINKS); - + ntb_peer_spad_read(nt->ndev, QP_LINKS); dev_dbg(&pdev->dev, "Remote QP link status = %x\n", val); /* See if the remote side is up */ - if (1 << qp->qp_num & val) { - qp->qp_link = NTB_LINK_UP; - + if (val & BIT(qp->qp_num)) { dev_info(&pdev->dev, "qp %d: Link Up\n", qp->qp_num); + qp->link_is_up = true; + if (qp->event_handler) - qp->event_handler(qp->cb_data, NTB_LINK_UP); - } else if (nt->transport_link == NTB_LINK_UP) + qp->event_handler(qp->cb_data, qp->link_is_up); + } else if (nt->link_is_up) schedule_delayed_work(&qp->link_work, msecs_to_jiffies(NTB_LINK_DOWN_TIMEOUT)); } -static int ntb_transport_init_queue(struct ntb_transport *nt, +static int ntb_transport_init_queue(struct ntb_transport_ctx *nt, unsigned int qp_num) { struct ntb_transport_qp *qp; + struct ntb_transport_mw *mw; + phys_addr_t mw_base; + resource_size_t mw_size; unsigned int num_qps_mw, tx_size; - u8 mw_num, mw_max; + unsigned int mw_num, mw_count, qp_count; u64 qp_offset; - mw_max = ntb_max_mw(nt->ndev); - mw_num = QP_TO_MW(nt->ndev, qp_num); + mw_count = nt->mw_count; + qp_count = nt->qp_count; - qp = &nt->qps[qp_num]; + mw_num = QP_TO_MW(nt, qp_num); + mw = &nt->mw_vec[mw_num]; + + qp = &nt->qp_vec[qp_num]; qp->qp_num = qp_num; qp->transport = nt; qp->ndev = nt->ndev; - qp->qp_link = NTB_LINK_DOWN; - qp->client_ready = NTB_LINK_DOWN; + qp->link_is_up = false; + qp->client_ready = false; qp->event_handler = NULL; - if (nt->max_qps % mw_max && mw_num + 1 < nt->max_qps / mw_max) - num_qps_mw = nt->max_qps / mw_max + 1; + if (qp_count % mw_count && mw_num + 1 < qp_count / mw_count) + num_qps_mw = qp_count / mw_count + 1; else - num_qps_mw = nt->max_qps / mw_max; + num_qps_mw = qp_count / mw_count; + + mw_base = nt->mw_vec[mw_num].phys_addr; + mw_size = nt->mw_vec[mw_num].phys_size; - tx_size = (unsigned int) ntb_get_mw_size(qp->ndev, mw_num) / num_qps_mw; - qp_offset = qp_num / mw_max * tx_size; - qp->tx_mw = ntb_get_mw_vbase(nt->ndev, mw_num) + qp_offset; + tx_size = (unsigned int)mw_size / num_qps_mw; + qp_offset = tx_size * qp_num / mw_count; + + qp->tx_mw = nt->mw_vec[mw_num].vbase + qp_offset; if (!qp->tx_mw) return -EINVAL; - qp->tx_mw_phys = ntb_get_mw_base(qp->ndev, mw_num) + qp_offset; + qp->tx_mw_phys = mw_base + qp_offset; if (!qp->tx_mw_phys) return -EINVAL; @@ -891,16 +896,19 @@ static int ntb_transport_init_queue(struct ntb_transport *nt, qp->tx_max_frame = min(transport_mtu, tx_size / 2); qp->tx_max_entry = tx_size / qp->tx_max_frame; - if (ntb_query_debugfs(nt->ndev)) { + if (nt_debugfs_dir) { char debugfs_name[4]; snprintf(debugfs_name, 4, "qp%d", qp_num); qp->debugfs_dir = debugfs_create_dir(debugfs_name, - ntb_query_debugfs(nt->ndev)); + nt_debugfs_dir); qp->debugfs_stats = debugfs_create_file("stats", S_IRUSR, qp->debugfs_dir, qp, &ntb_qp_debugfs_stats); + } else { + qp->debugfs_dir = NULL; + qp->debugfs_stats = NULL; } INIT_DELAYED_WORK(&qp->link_work, ntb_qp_link_work); @@ -914,46 +922,84 @@ static int ntb_transport_init_queue(struct ntb_transport *nt, INIT_LIST_HEAD(&qp->rx_free_q); INIT_LIST_HEAD(&qp->tx_free_q); + tasklet_init(&qp->rxc_db_work, ntb_transport_rxc_db, + (unsigned long)qp); + return 0; } -int ntb_transport_init(struct pci_dev *pdev) +static int ntb_transport_probe(struct ntb_client *self, struct ntb_dev *ndev) { - struct ntb_transport *nt; + struct ntb_transport_ctx *nt; + struct ntb_transport_mw *mw; + unsigned int mw_count, qp_count; + u64 qp_bitmap; int rc, i; - nt = kzalloc(sizeof(struct ntb_transport), GFP_KERNEL); + if (ntb_db_is_unsafe(ndev)) + dev_dbg(&ndev->dev, + "doorbell is unsafe, proceed anyway...\n"); + if (ntb_spad_is_unsafe(ndev)) + dev_dbg(&ndev->dev, + "scratchpad is unsafe, proceed anyway...\n"); + + nt = kzalloc(sizeof(*nt), GFP_KERNEL); if (!nt) return -ENOMEM; - nt->ndev = ntb_register_transport(pdev, nt); - if (!nt->ndev) { - rc = -EIO; + nt->ndev = ndev; + + mw_count = ntb_mw_count(ndev); + + nt->mw_count = mw_count; + + nt->mw_vec = kcalloc(mw_count, sizeof(*nt->mw_vec), GFP_KERNEL); + if (!nt->mw_vec) { + rc = -ENOMEM; goto err; } - nt->mw = kcalloc(ntb_max_mw(nt->ndev), sizeof(struct ntb_transport_mw), - GFP_KERNEL); - if (!nt->mw) { - rc = -ENOMEM; - goto err1; + for (i = 0; i < mw_count; i++) { + mw = &nt->mw_vec[i]; + + rc = ntb_mw_get_range(ndev, i, &mw->phys_addr, &mw->phys_size, + &mw->xlat_align, &mw->xlat_align_size); + if (rc) + goto err1; + + mw->vbase = ioremap(mw->phys_addr, mw->phys_size); + if (!mw->vbase) { + rc = -ENOMEM; + goto err1; + } + + mw->buff_size = 0; + mw->xlat_size = 0; + mw->virt_addr = NULL; + mw->dma_addr = 0; } - if (max_num_clients) - nt->max_qps = min(ntb_max_cbs(nt->ndev), max_num_clients); - else - nt->max_qps = min(ntb_max_cbs(nt->ndev), ntb_max_mw(nt->ndev)); + qp_bitmap = ntb_db_valid_mask(ndev); + + qp_count = ilog2(qp_bitmap); + if (max_num_clients && max_num_clients < qp_count) + qp_count = max_num_clients; + else if (mw_count < qp_count) + qp_count = mw_count; + + qp_bitmap &= BIT_ULL(qp_count) - 1; + + nt->qp_count = qp_count; + nt->qp_bitmap = qp_bitmap; + nt->qp_bitmap_free = qp_bitmap; - nt->qps = kcalloc(nt->max_qps, sizeof(struct ntb_transport_qp), - GFP_KERNEL); - if (!nt->qps) { + nt->qp_vec = kcalloc(qp_count, sizeof(*nt->qp_vec), GFP_KERNEL); + if (!nt->qp_vec) { rc = -ENOMEM; goto err2; } - nt->qp_bitmap = ((u64) 1 << nt->max_qps) - 1; - - for (i = 0; i < nt->max_qps; i++) { + for (i = 0; i < qp_count; i++) { rc = ntb_transport_init_queue(nt, i); if (rc) goto err3; @@ -962,8 +1008,7 @@ int ntb_transport_init(struct pci_dev *pdev) INIT_DELAYED_WORK(&nt->link_work, ntb_transport_link_work); INIT_WORK(&nt->link_cleanup, ntb_transport_link_cleanup_work); - rc = ntb_register_event_callback(nt->ndev, - ntb_transport_event_callback); + rc = ntb_set_ctx(ndev, nt, &ntb_transport_ops); if (rc) goto err3; @@ -972,51 +1017,61 @@ int ntb_transport_init(struct pci_dev *pdev) if (rc) goto err4; - if (ntb_hw_link_status(nt->ndev)) - schedule_delayed_work(&nt->link_work, 0); + nt->link_is_up = false; + ntb_link_enable(ndev, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + ntb_link_event(ndev); return 0; err4: - ntb_unregister_event_callback(nt->ndev); + ntb_clear_ctx(ndev); err3: - kfree(nt->qps); + kfree(nt->qp_vec); err2: - kfree(nt->mw); + kfree(nt->mw_vec); err1: - ntb_unregister_transport(nt->ndev); + while (i--) { + mw = &nt->mw_vec[i]; + iounmap(mw->vbase); + } err: kfree(nt); return rc; } -void ntb_transport_free(void *transport) +static void ntb_transport_free(struct ntb_client *self, struct ntb_dev *ndev) { - struct ntb_transport *nt = transport; - struct ntb_device *ndev = nt->ndev; + struct ntb_transport_ctx *nt = ndev->ctx; + struct ntb_transport_qp *qp; + u64 qp_bitmap_alloc; int i; ntb_transport_link_cleanup(nt); + cancel_work_sync(&nt->link_cleanup); + cancel_delayed_work_sync(&nt->link_work); + + qp_bitmap_alloc = nt->qp_bitmap & ~nt->qp_bitmap_free; /* verify that all the qp's are freed */ - for (i = 0; i < nt->max_qps; i++) { - if (!test_bit(i, &nt->qp_bitmap)) - ntb_transport_free_queue(&nt->qps[i]); - debugfs_remove_recursive(nt->qps[i].debugfs_dir); + for (i = 0; i < nt->qp_count; i++) { + qp = &nt->qp_vec[i]; + if (qp_bitmap_alloc & BIT_ULL(i)) + ntb_transport_free_queue(qp); + debugfs_remove_recursive(qp->debugfs_dir); } - ntb_bus_remove(nt); + ntb_link_disable(ndev); + ntb_clear_ctx(ndev); - cancel_delayed_work_sync(&nt->link_work); - - ntb_unregister_event_callback(ndev); + ntb_bus_remove(nt); - for (i = 0; i < ntb_max_mw(ndev); i++) + for (i = nt->mw_count; i--; ) { ntb_free_mw(nt, i); + iounmap(nt->mw_vec[i].vbase); + } - kfree(nt->qps); - kfree(nt->mw); - ntb_unregister_transport(ndev); + kfree(nt->qp_vec); + kfree(nt->mw_vec); kfree(nt); } @@ -1028,15 +1083,13 @@ static void ntb_rx_copy_callback(void *data) unsigned int len = entry->len; struct ntb_payload_header *hdr = entry->rx_hdr; - /* Ensure that the data is fully copied out before clearing the flag */ - wmb(); hdr->flags = 0; iowrite32(entry->index, &qp->rx_info->entry); ntb_list_add(&qp->ntb_rx_free_q_lock, &entry->entry, &qp->rx_free_q); - if (qp->rx_handler && qp->client_ready == NTB_LINK_UP) + if (qp->rx_handler && qp->client_ready) qp->rx_handler(qp, qp->cb_data, cb_data, len); } @@ -1047,6 +1100,9 @@ static void ntb_memcpy_rx(struct ntb_queue_entry *entry, void *offset) memcpy(buf, offset, len); + /* Ensure that the data is fully copied out before clearing the flag */ + wmb(); + ntb_rx_copy_callback(entry); } @@ -1071,8 +1127,8 @@ static void ntb_async_rx(struct ntb_queue_entry *entry, void *offset, goto err_wait; device = chan->device; - pay_off = (size_t) offset & ~PAGE_MASK; - buff_off = (size_t) buf & ~PAGE_MASK; + pay_off = (size_t)offset & ~PAGE_MASK; + buff_off = (size_t)buf & ~PAGE_MASK; if (!is_dma_copy_aligned(device, pay_off, buff_off, len)) goto err_wait; @@ -1138,86 +1194,104 @@ static int ntb_process_rxc(struct ntb_transport_qp *qp) struct ntb_payload_header *hdr; struct ntb_queue_entry *entry; void *offset; + int rc; offset = qp->rx_buff + qp->rx_max_frame * qp->rx_index; hdr = offset + qp->rx_max_frame - sizeof(struct ntb_payload_header); - entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q); - if (!entry) { - dev_dbg(&ntb_query_pdev(qp->ndev)->dev, - "no buffer - HDR ver %u, len %d, flags %x\n", - hdr->ver, hdr->len, hdr->flags); - qp->rx_err_no_buf++; - return -ENOMEM; - } + dev_dbg(&qp->ndev->pdev->dev, "qp %d: RX ver %u len %d flags %x\n", + qp->qp_num, hdr->ver, hdr->len, hdr->flags); if (!(hdr->flags & DESC_DONE_FLAG)) { - ntb_list_add(&qp->ntb_rx_pend_q_lock, &entry->entry, - &qp->rx_pend_q); + dev_dbg(&qp->ndev->pdev->dev, "done flag not set\n"); qp->rx_ring_empty++; return -EAGAIN; } - if (hdr->ver != (u32) qp->rx_pkts) { - dev_dbg(&ntb_query_pdev(qp->ndev)->dev, - "qp %d: version mismatch, expected %llu - got %u\n", - qp->qp_num, qp->rx_pkts, hdr->ver); - ntb_list_add(&qp->ntb_rx_pend_q_lock, &entry->entry, - &qp->rx_pend_q); + if (hdr->flags & LINK_DOWN_FLAG) { + dev_dbg(&qp->ndev->pdev->dev, "link down flag set\n"); + ntb_qp_link_down(qp); + hdr->flags = 0; + iowrite32(qp->rx_index, &qp->rx_info->entry); + return 0; + } + + if (hdr->ver != (u32)qp->rx_pkts) { + dev_dbg(&qp->ndev->pdev->dev, + "version mismatch, expected %llu - got %u\n", + qp->rx_pkts, hdr->ver); qp->rx_err_ver++; return -EIO; } - if (hdr->flags & LINK_DOWN_FLAG) { - ntb_qp_link_down(qp); + entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q); + if (!entry) { + dev_dbg(&qp->ndev->pdev->dev, "no receive buffer\n"); + qp->rx_err_no_buf++; + rc = -ENOMEM; goto err; } - dev_dbg(&ntb_query_pdev(qp->ndev)->dev, - "rx offset %u, ver %u - %d payload received, buf size %d\n", - qp->rx_index, hdr->ver, hdr->len, entry->len); - - qp->rx_bytes += hdr->len; - qp->rx_pkts++; - if (hdr->len > entry->len) { - qp->rx_err_oflow++; - dev_dbg(&ntb_query_pdev(qp->ndev)->dev, - "RX overflow! Wanted %d got %d\n", + dev_dbg(&qp->ndev->pdev->dev, + "receive buffer overflow! Wanted %d got %d\n", hdr->len, entry->len); + qp->rx_err_oflow++; + rc = -EIO; goto err; } + dev_dbg(&qp->ndev->pdev->dev, + "RX OK index %u ver %u size %d into buf size %d\n", + qp->rx_index, hdr->ver, hdr->len, entry->len); + + qp->rx_bytes += hdr->len; + qp->rx_pkts++; + entry->index = qp->rx_index; entry->rx_hdr = hdr; ntb_async_rx(entry, offset, hdr->len); -out: qp->rx_index++; qp->rx_index %= qp->rx_max_entry; return 0; err: - ntb_list_add(&qp->ntb_rx_pend_q_lock, &entry->entry, &qp->rx_pend_q); - /* Ensure that the data is fully copied out before clearing the flag */ - wmb(); + /* FIXME: if this syncrhonous update of the rx_index gets ahead of + * asyncrhonous ntb_rx_copy_callback of previous entry, there are three + * scenarios: + * + * 1) The peer might miss this update, but observe the update + * from the memcpy completion callback. In this case, the buffer will + * not be freed on the peer to be reused for a different packet. The + * successful rx of a later packet would clear the condition, but the + * condition could persist if several rx fail in a row. + * + * 2) The peer may observe this update before the asyncrhonous copy of + * prior packets is completed. The peer may overwrite the buffers of + * the prior packets before they are copied. + * + * 3) Both: the peer may observe the update, and then observe the index + * decrement by the asynchronous completion callback. Who knows what + * badness that will cause. + */ hdr->flags = 0; iowrite32(qp->rx_index, &qp->rx_info->entry); - goto out; + return rc; } -static int ntb_transport_rxc_db(void *data, int db_num) +static void ntb_transport_rxc_db(unsigned long data) { - struct ntb_transport_qp *qp = data; + struct ntb_transport_qp *qp = (void *)data; int rc, i; - dev_dbg(&ntb_query_pdev(qp->ndev)->dev, "%s: doorbell %d received\n", - __func__, db_num); + dev_dbg(&qp->ndev->pdev->dev, "%s: doorbell %d received\n", + __func__, qp->qp_num); /* Limit the number of packets processed in a single interrupt to * provide fairness to others @@ -1231,7 +1305,21 @@ static int ntb_transport_rxc_db(void *data, int db_num) if (qp->dma_chan) dma_async_issue_pending(qp->dma_chan); - return i; + if (i == qp->rx_max_entry) { + /* there is more work to do */ + tasklet_schedule(&qp->rxc_db_work); + } else if (ntb_db_read(qp->ndev) & BIT_ULL(qp->qp_num)) { + /* the doorbell bit is set: clear it */ + ntb_db_clear(qp->ndev, BIT_ULL(qp->qp_num)); + /* ntb_db_read ensures ntb_db_clear write is committed */ + ntb_db_read(qp->ndev); + + /* an interrupt may have arrived between finishing + * ntb_process_rxc and clearing the doorbell bit: + * there might be some more work to do. + */ + tasklet_schedule(&qp->rxc_db_work); + } } static void ntb_tx_copy_callback(void *data) @@ -1240,11 +1328,9 @@ static void ntb_tx_copy_callback(void *data) struct ntb_transport_qp *qp = entry->qp; struct ntb_payload_header __iomem *hdr = entry->tx_hdr; - /* Ensure that the data is fully copied out before setting the flags */ - wmb(); iowrite32(entry->flags | DESC_DONE_FLAG, &hdr->flags); - ntb_ring_doorbell(qp->ndev, qp->qp_num); + ntb_peer_db_set(qp->ndev, BIT_ULL(qp->qp_num)); /* The entry length can only be zero if the packet is intended to be a * "link down" or similar. Since no payload is being sent in these @@ -1265,6 +1351,9 @@ static void ntb_memcpy_tx(struct ntb_queue_entry *entry, void __iomem *offset) { memcpy_toio(offset, entry->buf, entry->len); + /* Ensure that the data is fully copied out before setting the flags */ + wmb(); + ntb_tx_copy_callback(entry); } @@ -1288,7 +1377,7 @@ static void ntb_async_tx(struct ntb_transport_qp *qp, entry->tx_hdr = hdr; iowrite32(entry->len, &hdr->len); - iowrite32((u32) qp->tx_pkts, &hdr->ver); + iowrite32((u32)qp->tx_pkts, &hdr->ver); if (!chan) goto err; @@ -1298,8 +1387,8 @@ static void ntb_async_tx(struct ntb_transport_qp *qp, device = chan->device; dest = qp->tx_mw_phys + qp->tx_max_frame * qp->tx_index; - buff_off = (size_t) buf & ~PAGE_MASK; - dest_off = (size_t) dest & ~PAGE_MASK; + buff_off = (size_t)buf & ~PAGE_MASK; + dest_off = (size_t)dest & ~PAGE_MASK; if (!is_dma_copy_aligned(device, buff_off, dest_off, len)) goto err; @@ -1347,9 +1436,6 @@ err: static int ntb_process_tx(struct ntb_transport_qp *qp, struct ntb_queue_entry *entry) { - dev_dbg(&ntb_query_pdev(qp->ndev)->dev, "%lld - tx %u, entry len %d flags %x buff %p\n", - qp->tx_pkts, qp->tx_index, entry->len, entry->flags, - entry->buf); if (qp->tx_index == qp->remote_rx_info->entry) { qp->tx_ring_full++; return -EAGAIN; @@ -1376,14 +1462,14 @@ static int ntb_process_tx(struct ntb_transport_qp *qp, static void ntb_send_link_down(struct ntb_transport_qp *qp) { - struct pci_dev *pdev = ntb_query_pdev(qp->ndev); + struct pci_dev *pdev = qp->ndev->pdev; struct ntb_queue_entry *entry; int i, rc; - if (qp->qp_link == NTB_LINK_DOWN) + if (!qp->link_is_up) return; - qp->qp_link = NTB_LINK_DOWN; + qp->link_is_up = false; dev_info(&pdev->dev, "qp %d: Link Down\n", qp->qp_num); for (i = 0; i < NTB_LINK_DOWN_TIMEOUT; i++) { @@ -1422,18 +1508,21 @@ static void ntb_send_link_down(struct ntb_transport_qp *qp) * RETURNS: pointer to newly created ntb_queue, NULL on error. */ struct ntb_transport_qp * -ntb_transport_create_queue(void *data, struct pci_dev *pdev, +ntb_transport_create_queue(void *data, struct device *client_dev, const struct ntb_queue_handlers *handlers) { + struct ntb_dev *ndev; + struct pci_dev *pdev; + struct ntb_transport_ctx *nt; struct ntb_queue_entry *entry; struct ntb_transport_qp *qp; - struct ntb_transport *nt; + u64 qp_bit; unsigned int free_queue; - int rc, i; + int i; - nt = ntb_find_transport(pdev); - if (!nt) - goto err; + ndev = dev_ntb(client_dev->parent); + pdev = ndev->pdev; + nt = ndev->ctx; free_queue = ffs(nt->qp_bitmap); if (!free_queue) @@ -1442,9 +1531,11 @@ ntb_transport_create_queue(void *data, struct pci_dev *pdev, /* decrement free_queue to make it zero based */ free_queue--; - clear_bit(free_queue, &nt->qp_bitmap); + qp = &nt->qp_vec[free_queue]; + qp_bit = BIT_ULL(qp->qp_num); + + nt->qp_bitmap_free &= ~qp_bit; - qp = &nt->qps[free_queue]; qp->cb_data = data; qp->rx_handler = handlers->rx_handler; qp->tx_handler = handlers->tx_handler; @@ -1458,7 +1549,7 @@ ntb_transport_create_queue(void *data, struct pci_dev *pdev, } for (i = 0; i < NTB_QP_DEF_NUM_ENTRIES; i++) { - entry = kzalloc(sizeof(struct ntb_queue_entry), GFP_ATOMIC); + entry = kzalloc(sizeof(*entry), GFP_ATOMIC); if (!entry) goto err1; @@ -1468,7 +1559,7 @@ ntb_transport_create_queue(void *data, struct pci_dev *pdev, } for (i = 0; i < NTB_QP_DEF_NUM_ENTRIES; i++) { - entry = kzalloc(sizeof(struct ntb_queue_entry), GFP_ATOMIC); + entry = kzalloc(sizeof(*entry), GFP_ATOMIC); if (!entry) goto err2; @@ -1477,10 +1568,8 @@ ntb_transport_create_queue(void *data, struct pci_dev *pdev, &qp->tx_free_q); } - rc = ntb_register_db_callback(qp->ndev, free_queue, qp, - ntb_transport_rxc_db); - if (rc) - goto err2; + ntb_db_clear(qp->ndev, qp_bit); + ntb_db_clear_mask(qp->ndev, qp_bit); dev_info(&pdev->dev, "NTB Transport QP %d created\n", qp->qp_num); @@ -1494,7 +1583,7 @@ err1: kfree(entry); if (qp->dma_chan) dmaengine_put(); - set_bit(free_queue, &nt->qp_bitmap); + nt->qp_bitmap_free |= qp_bit; err: return NULL; } @@ -1508,13 +1597,15 @@ EXPORT_SYMBOL_GPL(ntb_transport_create_queue); */ void ntb_transport_free_queue(struct ntb_transport_qp *qp) { + struct ntb_transport_ctx *nt = qp->transport; struct pci_dev *pdev; struct ntb_queue_entry *entry; + u64 qp_bit; if (!qp) return; - pdev = ntb_query_pdev(qp->ndev); + pdev = qp->ndev->pdev; if (qp->dma_chan) { struct dma_chan *chan = qp->dma_chan; @@ -1531,10 +1622,18 @@ void ntb_transport_free_queue(struct ntb_transport_qp *qp) dmaengine_put(); } - ntb_unregister_db_callback(qp->ndev, qp->qp_num); + qp_bit = BIT_ULL(qp->qp_num); + + ntb_db_set_mask(qp->ndev, qp_bit); + tasklet_disable(&qp->rxc_db_work); cancel_delayed_work_sync(&qp->link_work); + qp->cb_data = NULL; + qp->rx_handler = NULL; + qp->tx_handler = NULL; + qp->event_handler = NULL; + while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q))) kfree(entry); @@ -1546,7 +1645,7 @@ void ntb_transport_free_queue(struct ntb_transport_qp *qp) while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q))) kfree(entry); - set_bit(qp->qp_num, &qp->transport->qp_bitmap); + nt->qp_bitmap_free |= qp_bit; dev_info(&pdev->dev, "NTB Transport QP %d freed\n", qp->qp_num); } @@ -1567,7 +1666,7 @@ void *ntb_transport_rx_remove(struct ntb_transport_qp *qp, unsigned int *len) struct ntb_queue_entry *entry; void *buf; - if (!qp || qp->client_ready == NTB_LINK_UP) + if (!qp || qp->client_ready) return NULL; entry = ntb_list_rm(&qp->ntb_rx_pend_q_lock, &qp->rx_pend_q); @@ -1636,7 +1735,7 @@ int ntb_transport_tx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, struct ntb_queue_entry *entry; int rc; - if (!qp || qp->qp_link != NTB_LINK_UP || !len) + if (!qp || !qp->link_is_up || !len) return -EINVAL; entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q); @@ -1670,9 +1769,9 @@ void ntb_transport_link_up(struct ntb_transport_qp *qp) if (!qp) return; - qp->client_ready = NTB_LINK_UP; + qp->client_ready = true; - if (qp->transport->transport_link == NTB_LINK_UP) + if (qp->transport->link_is_up) schedule_delayed_work(&qp->link_work, 0); } EXPORT_SYMBOL_GPL(ntb_transport_link_up); @@ -1688,27 +1787,20 @@ EXPORT_SYMBOL_GPL(ntb_transport_link_up); void ntb_transport_link_down(struct ntb_transport_qp *qp) { struct pci_dev *pdev; - int rc, val; + int val; if (!qp) return; - pdev = ntb_query_pdev(qp->ndev); - qp->client_ready = NTB_LINK_DOWN; + pdev = qp->ndev->pdev; + qp->client_ready = false; - rc = ntb_read_local_spad(qp->ndev, QP_LINKS, &val); - if (rc) { - dev_err(&pdev->dev, "Error reading spad %d\n", QP_LINKS); - return; - } + val = ntb_spad_read(qp->ndev, QP_LINKS); - rc = ntb_write_remote_spad(qp->ndev, QP_LINKS, - val & ~(1 << qp->qp_num)); - if (rc) - dev_err(&pdev->dev, "Error writing %x to remote spad %d\n", - val & ~(1 << qp->qp_num), QP_LINKS); + ntb_peer_spad_write(qp->ndev, QP_LINKS, + val & ~BIT(qp->qp_num)); - if (qp->qp_link == NTB_LINK_UP) + if (qp->link_is_up) ntb_send_link_down(qp); else cancel_delayed_work_sync(&qp->link_work); @@ -1728,7 +1820,7 @@ bool ntb_transport_link_query(struct ntb_transport_qp *qp) if (!qp) return false; - return qp->qp_link == NTB_LINK_UP; + return qp->link_is_up; } EXPORT_SYMBOL_GPL(ntb_transport_link_query); @@ -1774,3 +1866,69 @@ unsigned int ntb_transport_max_size(struct ntb_transport_qp *qp) return max; } EXPORT_SYMBOL_GPL(ntb_transport_max_size); + +static void ntb_transport_doorbell_callback(void *data, int vector) +{ + struct ntb_transport_ctx *nt = data; + struct ntb_transport_qp *qp; + u64 db_bits; + unsigned int qp_num; + + db_bits = (nt->qp_bitmap & ~nt->qp_bitmap_free & + ntb_db_vector_mask(nt->ndev, vector)); + + while (db_bits) { + qp_num = __ffs(db_bits); + qp = &nt->qp_vec[qp_num]; + + tasklet_schedule(&qp->rxc_db_work); + + db_bits &= ~BIT_ULL(qp_num); + } +} + +static const struct ntb_ctx_ops ntb_transport_ops = { + .link_event = ntb_transport_event_callback, + .db_event = ntb_transport_doorbell_callback, +}; + +static struct ntb_client ntb_transport_client = { + .ops = { + .probe = ntb_transport_probe, + .remove = ntb_transport_free, + }, +}; + +static int __init ntb_transport_init(void) +{ + int rc; + + if (debugfs_initialized()) + nt_debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); + + rc = bus_register(&ntb_transport_bus); + if (rc) + goto err_bus; + + rc = ntb_register_client(&ntb_transport_client); + if (rc) + goto err_client; + + return 0; + +err_client: + bus_unregister(&ntb_transport_bus); +err_bus: + debugfs_remove_recursive(nt_debugfs_dir); + return rc; +} +module_init(ntb_transport_init); + +static void __exit ntb_transport_exit(void) +{ + debugfs_remove_recursive(nt_debugfs_dir); + + ntb_unregister_client(&ntb_transport_client); + bus_unregister(&ntb_transport_bus); +} +module_exit(ntb_transport_exit); diff --git a/include/linux/ntb_transport.h b/include/linux/ntb_transport.h index f78b64cc09d5..2862861366a5 100644 --- a/include/linux/ntb_transport.h +++ b/include/linux/ntb_transport.h @@ -5,6 +5,7 @@ * GPL LICENSE SUMMARY * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as @@ -13,6 +14,7 @@ * BSD LICENSE * * Copyright(c) 2012 Intel Corporation. All rights reserved. + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -40,7 +42,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Intel PCIe NTB Linux driver + * PCIe NTB Transport Linux driver * * Contact Information: * Jon Mason @@ -48,21 +50,16 @@ struct ntb_transport_qp; -struct ntb_client { +struct ntb_transport_client { struct device_driver driver; - int (*probe)(struct pci_dev *pdev); - void (*remove)(struct pci_dev *pdev); + int (*probe)(struct device *client_dev); + void (*remove)(struct device *client_dev); }; -enum { - NTB_LINK_DOWN = 0, - NTB_LINK_UP, -}; - -int ntb_transport_register_client(struct ntb_client *drvr); -void ntb_transport_unregister_client(struct ntb_client *drvr); -int ntb_register_client_dev(char *device_name); -void ntb_unregister_client_dev(char *device_name); +int ntb_transport_register_client(struct ntb_transport_client *drvr); +void ntb_transport_unregister_client(struct ntb_transport_client *drvr); +int ntb_transport_register_client_dev(char *device_name); +void ntb_transport_unregister_client_dev(char *device_name); struct ntb_queue_handlers { void (*rx_handler)(struct ntb_transport_qp *qp, void *qp_data, @@ -75,7 +72,7 @@ struct ntb_queue_handlers { unsigned char ntb_transport_qp_num(struct ntb_transport_qp *qp); unsigned int ntb_transport_max_size(struct ntb_transport_qp *qp); struct ntb_transport_qp * -ntb_transport_create_queue(void *data, struct pci_dev *pdev, +ntb_transport_create_queue(void *data, struct device *client_dev, const struct ntb_queue_handlers *handlers); void ntb_transport_free_queue(struct ntb_transport_qp *qp); int ntb_transport_rx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, -- cgit v1.2.3 From 42fefc86a680f975e2816cd86c4ba50069766ef6 Mon Sep 17 00:00:00 2001 From: Allen Hubbe Date: Mon, 11 May 2015 05:45:30 -0400 Subject: NTB: Add parameters for Intel SNB B2B addresses Add module parameters for the addresses to be used in B2B topology. Signed-off-by: Allen Hubbe Signed-off-by: Jon Mason --- Documentation/ntb.txt | 10 +++++ drivers/ntb/hw/intel/ntb_hw_intel.c | 77 ++++++++++++++++++++++++++++--------- 2 files changed, 68 insertions(+), 19 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt index 725ba1e6c127..00a3f92832a5 100644 --- a/Documentation/ntb.txt +++ b/Documentation/ntb.txt @@ -56,3 +56,13 @@ Module Parameters: * b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if the memory window is large enough, still allow the client to use the second half of the memory window for address translation to the peer. +* snb\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use this + 64 bit address on the bus between the NTB devices for the window at + BAR2, on the upstream side of the link. +* snb\_b2b\_usd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_usd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_usd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar2\_addr64 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*. diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index 499222285439..c5ad7cb1706d 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c @@ -72,20 +72,6 @@ MODULE_AUTHOR("Intel Corporation"); #define bar0_off(base, bar) ((base) + ((bar) << 2)) #define bar2_off(base, bar) bar0_off(base, (bar) - 2) -static int b2b_mw_idx = -1; -module_param(b2b_mw_idx, int, 0644); -MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A " - "value of zero or positive starts from first mw idx, and a " - "negative value starts from last mw idx. Both sides MUST " - "set the same value here!"); - -static unsigned int b2b_mw_share; -module_param(b2b_mw_share, uint, 0644); -MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " - "ntb so that the peer ntb only occupies the first half of " - "the mw, so the second half can still be used as a mw. Both " - "sides MUST set the same value here!"); - static const struct intel_ntb_reg bwd_reg; static const struct intel_ntb_alt_reg bwd_pri_reg; static const struct intel_ntb_alt_reg bwd_sec_reg; @@ -98,14 +84,67 @@ static const struct intel_ntb_alt_reg snb_sec_reg; static const struct intel_ntb_alt_reg snb_b2b_reg; static const struct intel_ntb_xlat_reg snb_pri_xlat; static const struct intel_ntb_xlat_reg snb_sec_xlat; -static const struct intel_b2b_addr snb_b2b_usd_addr; -static const struct intel_b2b_addr snb_b2b_dsd_addr; - +static struct intel_b2b_addr snb_b2b_usd_addr; +static struct intel_b2b_addr snb_b2b_dsd_addr; static const struct ntb_dev_ops intel_ntb_ops; static const struct file_operations intel_ntb_debugfs_info; static struct dentry *debugfs_dir; +static int b2b_mw_idx = -1; +module_param(b2b_mw_idx, int, 0644); +MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A " + "value of zero or positive starts from first mw idx, and a " + "negative value starts from last mw idx. Both sides MUST " + "set the same value here!"); + +static unsigned int b2b_mw_share; +module_param(b2b_mw_share, uint, 0644); +MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " + "ntb so that the peer ntb only occupies the first half of " + "the mw, so the second half can still be used as a mw. Both " + "sides MUST set the same value here!"); + +module_param_named(snb_b2b_usd_bar2_addr64, + snb_b2b_usd_addr.bar2_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD BAR 2 64-bit address"); + +module_param_named(snb_b2b_usd_bar4_addr64, + snb_b2b_usd_addr.bar4_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD BAR 4 64-bit address"); + +module_param_named(snb_b2b_usd_bar4_addr32, + snb_b2b_usd_addr.bar4_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD split-BAR 4 32-bit address"); + +module_param_named(snb_b2b_usd_bar5_addr32, + snb_b2b_usd_addr.bar5_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD split-BAR 5 32-bit address"); + +module_param_named(snb_b2b_dsd_bar2_addr64, + snb_b2b_dsd_addr.bar2_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD BAR 2 64-bit address"); + +module_param_named(snb_b2b_dsd_bar4_addr64, + snb_b2b_dsd_addr.bar4_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD BAR 4 64-bit address"); + +module_param_named(snb_b2b_dsd_bar4_addr32, + snb_b2b_dsd_addr.bar4_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD split-BAR 4 32-bit address"); + +module_param_named(snb_b2b_dsd_bar5_addr32, + snb_b2b_dsd_addr.bar5_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD split-BAR 5 32-bit address"); + #ifndef ioread64 #ifdef readq #define ioread64 readq @@ -2073,14 +2112,14 @@ static const struct intel_ntb_xlat_reg snb_sec_xlat = { .bar2_xlat = SNB_SBAR23XLAT_OFFSET, }; -static const struct intel_b2b_addr snb_b2b_usd_addr = { +static struct intel_b2b_addr snb_b2b_usd_addr = { .bar2_addr64 = SNB_B2B_BAR2_USD_ADDR64, .bar4_addr64 = SNB_B2B_BAR4_USD_ADDR64, .bar4_addr32 = SNB_B2B_BAR4_USD_ADDR32, .bar5_addr32 = SNB_B2B_BAR5_USD_ADDR32, }; -static const struct intel_b2b_addr snb_b2b_dsd_addr = { +static struct intel_b2b_addr snb_b2b_dsd_addr = { .bar2_addr64 = SNB_B2B_BAR2_DSD_ADDR64, .bar4_addr64 = SNB_B2B_BAR4_DSD_ADDR64, .bar4_addr32 = SNB_B2B_BAR4_DSD_ADDR32, -- cgit v1.2.3 From 963de4739fb4f8fa8d5cd87969109a7d3282ed13 Mon Sep 17 00:00:00 2001 From: Allen Hubbe Date: Wed, 15 Apr 2015 11:12:41 -0400 Subject: NTB: Add ping pong test client This is a simple ping pong driver that exercises the scratch pads and doorbells of the ntb hardware. This driver may be used to test that your ntb hardware and drivers are functioning at a basic level. Signed-off-by: Allen Hubbe Signed-off-by: Jon Mason --- Documentation/ntb.txt | 27 +++++ drivers/ntb/Kconfig | 2 + drivers/ntb/Makefile | 2 +- drivers/ntb/test/Kconfig | 8 ++ drivers/ntb/test/Makefile | 1 + drivers/ntb/test/ntb_pingpong.c | 250 ++++++++++++++++++++++++++++++++++++++++ 6 files changed, 289 insertions(+), 1 deletion(-) create mode 100644 drivers/ntb/test/Kconfig create mode 100644 drivers/ntb/test/Makefile create mode 100644 drivers/ntb/test/ntb_pingpong.c (limited to 'Documentation') diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt index 00a3f92832a5..e5d1591478ca 100644 --- a/Documentation/ntb.txt +++ b/Documentation/ntb.txt @@ -37,6 +37,33 @@ Transport queue pair. Network data is copied between socket buffers and the Transport queue pair buffer. The Transport client may be used for other things besides Netdev, however no other applications have yet been written. +### NTB Ping Pong Test Client (ntb\_pingpong) + +The Ping Pong test client serves as a demonstration to exercise the doorbell +and scratchpad registers of NTB hardware, and as an example simple NTB client. +Ping Pong enables the link when started, waits for the NTB link to come up, and +then proceeds to read and write the doorbell scratchpad registers of the NTB. +The peers interrupt each other using a bit mask of doorbell bits, which is +shifted by one in each round, to test the behavior of multiple doorbell bits +and interrupt vectors. The Ping Pong driver also reads the first local +scratchpad, and writes the value plus one to the first peer scratchpad, each +round before writing the peer doorbell register. + +Module Parameters: + +* unsafe - Some hardware has known issues with scratchpad and doorbell + registers. By default, Ping Pong will not attempt to exercise such + hardware. You may override this behavior at your own risk by setting + unsafe=1. +* delay\_ms - Specify the delay between receiving a doorbell + interrupt event and setting the peer doorbell register for the next + round. +* init\_db - Specify the doorbell bits to start new series of rounds. A new + series begins once all the doorbell bits have been shifted out of + range. +* dyndbg - It is suggested to specify dyndbg=+p when loading this module, and + then to observe debugging output on the console. + ## NTB Hardware Drivers NTB hardware drivers should register devices with the NTB core driver. After diff --git a/drivers/ntb/Kconfig b/drivers/ntb/Kconfig index 53b042429673..95944e52fa36 100644 --- a/drivers/ntb/Kconfig +++ b/drivers/ntb/Kconfig @@ -14,6 +14,8 @@ if NTB source "drivers/ntb/hw/Kconfig" +source "drivers/ntb/test/Kconfig" + config NTB_TRANSPORT tristate "NTB Transport Client" help diff --git a/drivers/ntb/Makefile b/drivers/ntb/Makefile index b9fa663ecfec..1921dec1949d 100644 --- a/drivers/ntb/Makefile +++ b/drivers/ntb/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_NTB) += ntb.o hw/ +obj-$(CONFIG_NTB) += ntb.o hw/ test/ obj-$(CONFIG_NTB_TRANSPORT) += ntb_transport.o diff --git a/drivers/ntb/test/Kconfig b/drivers/ntb/test/Kconfig new file mode 100644 index 000000000000..72d255d220c8 --- /dev/null +++ b/drivers/ntb/test/Kconfig @@ -0,0 +1,8 @@ +config NTB_PINGPONG + tristate "NTB Ping Pong Test Client" + help + This is a simple ping pong driver that exercises the scratchpads and + doorbells of the ntb hardware. This driver may be used to test that + your ntb hardware and drivers are functioning at a basic level. + + If unsure, say N. diff --git a/drivers/ntb/test/Makefile b/drivers/ntb/test/Makefile new file mode 100644 index 000000000000..b32309307771 --- /dev/null +++ b/drivers/ntb/test/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_NTB_PINGPONG) += ntb_pingpong.o diff --git a/drivers/ntb/test/ntb_pingpong.c b/drivers/ntb/test/ntb_pingpong.c new file mode 100644 index 000000000000..fe1600566981 --- /dev/null +++ b/drivers/ntb/test/ntb_pingpong.c @@ -0,0 +1,250 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * BSD LICENSE + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copy + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * PCIe NTB Pingpong Linux driver + * + * Contact Information: + * Allen Hubbe + */ + +/* Note: load this module with option 'dyndbg=+p' */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "ntb_pingpong" +#define DRIVER_DESCRIPTION "PCIe NTB Simple Pingpong Client" + +#define DRIVER_LICENSE "Dual BSD/GPL" +#define DRIVER_VERSION "1.0" +#define DRIVER_RELDATE "24 March 2015" +#define DRIVER_AUTHOR "Allen Hubbe " + +MODULE_LICENSE(DRIVER_LICENSE); +MODULE_VERSION(DRIVER_VERSION); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESCRIPTION); + +static unsigned int unsafe; +module_param(unsafe, uint, 0644); +MODULE_PARM_DESC(unsafe, "Run even though ntb operations may be unsafe"); + +static unsigned int delay_ms = 1000; +module_param(delay_ms, uint, 0644); +MODULE_PARM_DESC(delay_ms, "Milliseconds to delay the response to peer"); + +static unsigned long db_init = 0x7; +module_param(db_init, ulong, 0644); +MODULE_PARM_DESC(delay_ms, "Initial doorbell bits to ring on the peer"); + +struct pp_ctx { + struct ntb_dev *ntb; + u64 db_bits; + /* synchronize access to db_bits by ping and pong */ + spinlock_t db_lock; + struct timer_list db_timer; + unsigned long db_delay; +}; + +static void pp_ping(unsigned long ctx) +{ + struct pp_ctx *pp = (void *)ctx; + unsigned long irqflags; + u64 db_bits, db_mask; + u32 spad_rd, spad_wr; + + spin_lock_irqsave(&pp->db_lock, irqflags); + { + db_mask = ntb_db_valid_mask(pp->ntb); + db_bits = ntb_db_read(pp->ntb); + + if (db_bits) { + dev_dbg(&pp->ntb->dev, + "Masked pongs %#llx\n", + db_bits); + ntb_db_clear(pp->ntb, db_bits); + } + + db_bits = ((pp->db_bits | db_bits) << 1) & db_mask; + + if (!db_bits) + db_bits = db_init; + + spad_rd = ntb_spad_read(pp->ntb, 0); + spad_wr = spad_rd + 1; + + dev_dbg(&pp->ntb->dev, + "Ping bits %#llx read %#x write %#x\n", + db_bits, spad_rd, spad_wr); + + ntb_peer_spad_write(pp->ntb, 0, spad_wr); + ntb_peer_db_set(pp->ntb, db_bits); + ntb_db_clear_mask(pp->ntb, db_mask); + + pp->db_bits = 0; + } + spin_unlock_irqrestore(&pp->db_lock, irqflags); +} + +static void pp_link_event(void *ctx) +{ + struct pp_ctx *pp = ctx; + + if (ntb_link_is_up(pp->ntb, NULL, NULL) == 1) { + dev_dbg(&pp->ntb->dev, "link is up\n"); + pp_ping((unsigned long)pp); + } else { + dev_dbg(&pp->ntb->dev, "link is down\n"); + del_timer(&pp->db_timer); + } +} + +static void pp_db_event(void *ctx, int vec) +{ + struct pp_ctx *pp = ctx; + u64 db_bits, db_mask; + unsigned long irqflags; + + spin_lock_irqsave(&pp->db_lock, irqflags); + { + db_mask = ntb_db_vector_mask(pp->ntb, vec); + db_bits = db_mask & ntb_db_read(pp->ntb); + ntb_db_set_mask(pp->ntb, db_mask); + ntb_db_clear(pp->ntb, db_bits); + + pp->db_bits |= db_bits; + + mod_timer(&pp->db_timer, jiffies + pp->db_delay); + + dev_dbg(&pp->ntb->dev, + "Pong vec %d bits %#llx\n", + vec, db_bits); + } + spin_unlock_irqrestore(&pp->db_lock, irqflags); +} + +static const struct ntb_ctx_ops pp_ops = { + .link_event = pp_link_event, + .db_event = pp_db_event, +}; + +static int pp_probe(struct ntb_client *client, + struct ntb_dev *ntb) +{ + struct pp_ctx *pp; + int rc; + + if (ntb_db_is_unsafe(ntb)) { + dev_dbg(&ntb->dev, "doorbell is unsafe\n"); + if (!unsafe) { + rc = -EINVAL; + goto err_pp; + } + } + + if (ntb_spad_is_unsafe(ntb)) { + dev_dbg(&ntb->dev, "scratchpad is unsafe\n"); + if (!unsafe) { + rc = -EINVAL; + goto err_pp; + } + } + + pp = kmalloc(sizeof(*pp), GFP_KERNEL); + if (!pp) { + rc = -ENOMEM; + goto err_pp; + } + + pp->ntb = ntb; + pp->db_bits = 0; + spin_lock_init(&pp->db_lock); + setup_timer(&pp->db_timer, pp_ping, (unsigned long)pp); + pp->db_delay = msecs_to_jiffies(delay_ms); + + rc = ntb_set_ctx(ntb, pp, &pp_ops); + if (rc) + goto err_ctx; + + ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + ntb_link_event(ntb); + + return 0; + +err_ctx: + kfree(pp); +err_pp: + return rc; +} + +static void pp_remove(struct ntb_client *client, + struct ntb_dev *ntb) +{ + struct pp_ctx *pp = ntb->ctx; + + ntb_clear_ctx(ntb); + del_timer_sync(&pp->db_timer); + ntb_link_disable(ntb); + + kfree(pp); +} + +static struct ntb_client pp_client = { + .ops = { + .probe = pp_probe, + .remove = pp_remove, + }, +}; +module_ntb_client(pp_client); -- cgit v1.2.3 From 578b881ba9c4b253482903bf8fae438318f5629b Mon Sep 17 00:00:00 2001 From: Allen Hubbe Date: Thu, 21 May 2015 02:51:39 -0400 Subject: NTB: Add tool test client This is a simple debugging driver that enables the doorbell and scratch pad registers to be read and written from the debugfs. This tool enables more complicated debugging to be scripted from user space. This driver may be used to test that your ntb hardware and drivers are functioning at a basic level. Signed-off-by: Allen Hubbe Signed-off-by: Jon Mason --- Documentation/ntb.txt | 32 +++ drivers/ntb/test/Kconfig | 11 + drivers/ntb/test/Makefile | 1 + drivers/ntb/test/ntb_tool.c | 556 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 600 insertions(+) create mode 100644 drivers/ntb/test/ntb_tool.c (limited to 'Documentation') diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt index e5d1591478ca..b48249a7b607 100644 --- a/Documentation/ntb.txt +++ b/Documentation/ntb.txt @@ -64,6 +64,38 @@ Module Parameters: * dyndbg - It is suggested to specify dyndbg=+p when loading this module, and then to observe debugging output on the console. +### NTB Tool Test Client (ntb\_tool) + +The Tool test client serves for debugging, primarily, ntb hardware and drivers. +The Tool provides access through debugfs for reading, setting, and clearing the +NTB doorbell, and reading and writing scratchpads. + +The Tool does not currently have any module parameters. + +Debugfs Files: + +* *debugfs*/ntb\_tool/*hw*/ - A directory in debugfs will be created for each + NTB device probed by the tool. This directory is shortened to *hw* + below. +* *hw*/db - This file is used to read, set, and clear the local doorbell. Not + all operations may be supported by all hardware. To read the doorbell, + read the file. To set the doorbell, write `s` followed by the bits to + set (eg: `echo 's 0x0101' > db`). To clear the doorbell, write `c` + followed by the bits to clear. +* *hw*/mask - This file is used to read, set, and clear the local doorbell mask. + See *db* for details. +* *hw*/peer\_db - This file is used to read, set, and clear the peer doorbell. + See *db* for details. +* *hw*/peer\_mask - This file is used to read, set, and clear the peer doorbell + mask. See *db* for details. +* *hw*/spad - This file is used to read and write local scratchpads. To read + the values of all scratchpads, read the file. To write values, write a + series of pairs of scratchpad number and value + (eg: `echo '4 0x123 7 0xabc' > spad` + # to set scratchpads `4` and `7` to `0x123` and `0xabc`, respectively). +* *hw*/peer\_spad - This file is used to read and write peer scratchpads. See + *spad* for details. + ## NTB Hardware Drivers NTB hardware drivers should register devices with the NTB core driver. After diff --git a/drivers/ntb/test/Kconfig b/drivers/ntb/test/Kconfig index 72d255d220c8..01852f98a843 100644 --- a/drivers/ntb/test/Kconfig +++ b/drivers/ntb/test/Kconfig @@ -6,3 +6,14 @@ config NTB_PINGPONG your ntb hardware and drivers are functioning at a basic level. If unsure, say N. + +config NTB_TOOL + tristate "NTB Debugging Tool Test Client" + help + This is a simple debugging driver that enables the doorbell and + scratchpad registers to be read and written from the debugfs. This + enables more complicated debugging to be scripted from user space. + This driver may be used to test that your ntb hardware and drivers are + functioning at a basic level. + + If unsure, say N. diff --git a/drivers/ntb/test/Makefile b/drivers/ntb/test/Makefile index b32309307771..0ea32a324b6c 100644 --- a/drivers/ntb/test/Makefile +++ b/drivers/ntb/test/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_NTB_PINGPONG) += ntb_pingpong.o +obj-$(CONFIG_NTB_TOOL) += ntb_tool.o diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c new file mode 100644 index 000000000000..6f5dc6ca673d --- /dev/null +++ b/drivers/ntb/test/ntb_tool.c @@ -0,0 +1,556 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * BSD LICENSE + * + * Copyright (C) 2015 EMC Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copy + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * PCIe NTB Debugging Tool Linux driver + * + * Contact Information: + * Allen Hubbe + */ + +/* + * How to use this tool, by example. + * + * Assuming $DBG_DIR is something like: + * '/sys/kernel/debug/ntb_tool/0000:00:03.0' + * + * Eg: check if clearing the doorbell mask generates an interrupt. + * + * # Set the doorbell mask + * root@self# echo 's 1' > $DBG_DIR/mask + * + * # Ring the doorbell from the peer + * root@peer# echo 's 1' > $DBG_DIR/peer_db + * + * # Clear the doorbell mask + * root@self# echo 'c 1' > $DBG_DIR/mask + * + * Observe debugging output in dmesg or your console. You should see a + * doorbell event triggered by clearing the mask. If not, this may indicate an + * issue with the hardware that needs to be worked around in the driver. + * + * Eg: read and write scratchpad registers + * + * root@peer# echo '0 0x01010101 1 0x7f7f7f7f' > $DBG_DIR/peer_spad + * + * root@self# cat $DBG_DIR/spad + * + * Observe that spad 0 and 1 have the values set by the peer. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "ntb_tool" +#define DRIVER_DESCRIPTION "PCIe NTB Debugging Tool" + +#define DRIVER_LICENSE "Dual BSD/GPL" +#define DRIVER_VERSION "1.0" +#define DRIVER_RELDATE "22 April 2015" +#define DRIVER_AUTHOR "Allen Hubbe " + +MODULE_LICENSE(DRIVER_LICENSE); +MODULE_VERSION(DRIVER_VERSION); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESCRIPTION); + +static struct dentry *tool_dbgfs; + +struct tool_ctx { + struct ntb_dev *ntb; + struct dentry *dbgfs; +}; + +#define SPAD_FNAME_SIZE 0x10 +#define INT_PTR(x) ((void *)(unsigned long)x) +#define PTR_INT(x) ((int)(unsigned long)x) + +#define TOOL_FOPS_RDWR(__name, __read, __write) \ + const struct file_operations __name = { \ + .owner = THIS_MODULE, \ + .open = simple_open, \ + .read = __read, \ + .write = __write, \ + } + +static void tool_link_event(void *ctx) +{ + struct tool_ctx *tc = ctx; + enum ntb_speed speed; + enum ntb_width width; + int up; + + up = ntb_link_is_up(tc->ntb, &speed, &width); + + dev_dbg(&tc->ntb->dev, "link is %s speed %d width %d\n", + up ? "up" : "down", speed, width); +} + +static void tool_db_event(void *ctx, int vec) +{ + struct tool_ctx *tc = ctx; + u64 db_bits, db_mask; + + db_mask = ntb_db_vector_mask(tc->ntb, vec); + db_bits = ntb_db_read(tc->ntb); + + dev_dbg(&tc->ntb->dev, "doorbell vec %d mask %#llx bits %#llx\n", + vec, db_mask, db_bits); +} + +static const struct ntb_ctx_ops tool_ops = { + .link_event = tool_link_event, + .db_event = tool_db_event, +}; + +static ssize_t tool_dbfn_read(struct tool_ctx *tc, char __user *ubuf, + size_t size, loff_t *offp, + u64 (*db_read_fn)(struct ntb_dev *)) +{ + size_t buf_size; + char *buf; + ssize_t pos, rc; + + if (!db_read_fn) + return -EINVAL; + + buf_size = min_t(size_t, size, 0x20); + + buf = kmalloc(buf_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + pos = scnprintf(buf, buf_size, "%#llx\n", + db_read_fn(tc->ntb)); + + rc = simple_read_from_buffer(ubuf, size, offp, buf, pos); + + kfree(buf); + + return rc; +} + +static ssize_t tool_dbfn_write(struct tool_ctx *tc, + const char __user *ubuf, + size_t size, loff_t *offp, + int (*db_set_fn)(struct ntb_dev *, u64), + int (*db_clear_fn)(struct ntb_dev *, u64)) +{ + u64 db_bits; + char *buf, cmd; + ssize_t rc; + int n; + + buf = kmalloc(size + 1, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + rc = simple_write_to_buffer(buf, size, offp, ubuf, size); + if (rc < 0) { + kfree(buf); + return rc; + } + + buf[size] = 0; + + n = sscanf(buf, "%c %lli", &cmd, &db_bits); + + kfree(buf); + + if (n != 2) { + rc = -EINVAL; + } else if (cmd == 's') { + if (!db_set_fn) + rc = -EINVAL; + else + rc = db_set_fn(tc->ntb, db_bits); + } else if (cmd == 'c') { + if (!db_clear_fn) + rc = -EINVAL; + else + rc = db_clear_fn(tc->ntb, db_bits); + } else { + rc = -EINVAL; + } + + return rc ? : size; +} + +static ssize_t tool_spadfn_read(struct tool_ctx *tc, char __user *ubuf, + size_t size, loff_t *offp, + u32 (*spad_read_fn)(struct ntb_dev *, int)) +{ + size_t buf_size; + char *buf; + ssize_t pos, rc; + int i, spad_count; + + if (!spad_read_fn) + return -EINVAL; + + buf_size = min_t(size_t, size, 0x100); + + buf = kmalloc(buf_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + pos = 0; + + spad_count = ntb_spad_count(tc->ntb); + for (i = 0; i < spad_count; ++i) { + pos += scnprintf(buf + pos, buf_size - pos, "%d\t%#x\n", + i, spad_read_fn(tc->ntb, i)); + } + + rc = simple_read_from_buffer(ubuf, size, offp, buf, pos); + + kfree(buf); + + return rc; +} + +static ssize_t tool_spadfn_write(struct tool_ctx *tc, + const char __user *ubuf, + size_t size, loff_t *offp, + int (*spad_write_fn)(struct ntb_dev *, + int, u32)) +{ + int spad_idx; + u32 spad_val; + char *buf; + int pos, n; + ssize_t rc; + + if (!spad_write_fn) { + dev_dbg(&tc->ntb->dev, "no spad write fn\n"); + return -EINVAL; + } + + buf = kmalloc(size + 1, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + rc = simple_write_to_buffer(buf, size, offp, ubuf, size); + if (rc < 0) { + kfree(buf); + return rc; + } + + buf[size] = 0; + + n = sscanf(buf, "%d %i%n", &spad_idx, &spad_val, &pos); + while (n == 2) { + rc = spad_write_fn(tc->ntb, spad_idx, spad_val); + if (rc) + break; + + n = sscanf(buf + pos, "%d %i%n", &spad_idx, &spad_val, &pos); + } + + if (n < 0) + rc = n; + + kfree(buf); + + return rc ? : size; +} + +static ssize_t tool_db_read(struct file *filep, char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_read(tc, ubuf, size, offp, + tc->ntb->ops->db_read); +} + +static ssize_t tool_db_write(struct file *filep, const char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_write(tc, ubuf, size, offp, + tc->ntb->ops->db_set, + tc->ntb->ops->db_clear); +} + +static TOOL_FOPS_RDWR(tool_db_fops, + tool_db_read, + tool_db_write); + +static ssize_t tool_mask_read(struct file *filep, char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_read(tc, ubuf, size, offp, + tc->ntb->ops->db_read_mask); +} + +static ssize_t tool_mask_write(struct file *filep, const char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_write(tc, ubuf, size, offp, + tc->ntb->ops->db_set_mask, + tc->ntb->ops->db_clear_mask); +} + +static TOOL_FOPS_RDWR(tool_mask_fops, + tool_mask_read, + tool_mask_write); + +static ssize_t tool_peer_db_read(struct file *filep, char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_read(tc, ubuf, size, offp, + tc->ntb->ops->peer_db_read); +} + +static ssize_t tool_peer_db_write(struct file *filep, const char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_write(tc, ubuf, size, offp, + tc->ntb->ops->peer_db_set, + tc->ntb->ops->peer_db_clear); +} + +static TOOL_FOPS_RDWR(tool_peer_db_fops, + tool_peer_db_read, + tool_peer_db_write); + +static ssize_t tool_peer_mask_read(struct file *filep, char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_read(tc, ubuf, size, offp, + tc->ntb->ops->peer_db_read_mask); +} + +static ssize_t tool_peer_mask_write(struct file *filep, const char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_dbfn_write(tc, ubuf, size, offp, + tc->ntb->ops->peer_db_set_mask, + tc->ntb->ops->peer_db_clear_mask); +} + +static TOOL_FOPS_RDWR(tool_peer_mask_fops, + tool_peer_mask_read, + tool_peer_mask_write); + +static ssize_t tool_spad_read(struct file *filep, char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_spadfn_read(tc, ubuf, size, offp, + tc->ntb->ops->spad_read); +} + +static ssize_t tool_spad_write(struct file *filep, const char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_spadfn_write(tc, ubuf, size, offp, + tc->ntb->ops->spad_write); +} + +static TOOL_FOPS_RDWR(tool_spad_fops, + tool_spad_read, + tool_spad_write); + +static ssize_t tool_peer_spad_read(struct file *filep, char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_spadfn_read(tc, ubuf, size, offp, + tc->ntb->ops->peer_spad_read); +} + +static ssize_t tool_peer_spad_write(struct file *filep, const char __user *ubuf, + size_t size, loff_t *offp) +{ + struct tool_ctx *tc = filep->private_data; + + return tool_spadfn_write(tc, ubuf, size, offp, + tc->ntb->ops->peer_spad_write); +} + +static TOOL_FOPS_RDWR(tool_peer_spad_fops, + tool_peer_spad_read, + tool_peer_spad_write); + +static void tool_setup_dbgfs(struct tool_ctx *tc) +{ + /* This modules is useless without dbgfs... */ + if (!tool_dbgfs) { + tc->dbgfs = NULL; + return; + } + + tc->dbgfs = debugfs_create_dir(dev_name(&tc->ntb->dev), + tool_dbgfs); + if (!tc->dbgfs) + return; + + debugfs_create_file("db", S_IRUSR | S_IWUSR, tc->dbgfs, + tc, &tool_db_fops); + + debugfs_create_file("mask", S_IRUSR | S_IWUSR, tc->dbgfs, + tc, &tool_mask_fops); + + debugfs_create_file("peer_db", S_IRUSR | S_IWUSR, tc->dbgfs, + tc, &tool_peer_db_fops); + + debugfs_create_file("peer_mask", S_IRUSR | S_IWUSR, tc->dbgfs, + tc, &tool_peer_mask_fops); + + debugfs_create_file("spad", S_IRUSR | S_IWUSR, tc->dbgfs, + tc, &tool_spad_fops); + + debugfs_create_file("peer_spad", S_IRUSR | S_IWUSR, tc->dbgfs, + tc, &tool_peer_spad_fops); +} + +static int tool_probe(struct ntb_client *self, struct ntb_dev *ntb) +{ + struct tool_ctx *tc; + int rc; + + if (ntb_db_is_unsafe(ntb)) + dev_dbg(&ntb->dev, "doorbell is unsafe\n"); + + if (ntb_spad_is_unsafe(ntb)) + dev_dbg(&ntb->dev, "scratchpad is unsafe\n"); + + tc = kmalloc(sizeof(*tc), GFP_KERNEL); + if (!tc) { + rc = -ENOMEM; + goto err_tc; + } + + tc->ntb = ntb; + + tool_setup_dbgfs(tc); + + rc = ntb_set_ctx(ntb, tc, &tool_ops); + if (rc) + goto err_ctx; + + ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + ntb_link_event(ntb); + + return 0; + +err_ctx: + debugfs_remove_recursive(tc->dbgfs); + kfree(tc); +err_tc: + return rc; +} + +static void tool_remove(struct ntb_client *self, struct ntb_dev *ntb) +{ + struct tool_ctx *tc = ntb->ctx; + + ntb_clear_ctx(ntb); + ntb_link_disable(ntb); + + debugfs_remove_recursive(tc->dbgfs); + kfree(tc); +} + +static struct ntb_client tool_client = { + .ops = { + .probe = tool_probe, + .remove = tool_remove, + }, +}; + +static int __init tool_init(void) +{ + int rc; + + if (debugfs_initialized()) + tool_dbgfs = debugfs_create_dir(KBUILD_MODNAME, NULL); + + rc = ntb_register_client(&tool_client); + if (rc) + goto err_client; + + return 0; + +err_client: + debugfs_remove_recursive(tool_dbgfs); + return rc; +} +module_init(tool_init); + +static void __exit tool_exit(void) +{ + ntb_unregister_client(&tool_client); + debugfs_remove_recursive(tool_dbgfs); +} +module_exit(tool_exit); -- cgit v1.2.3 From 2f887b9a44015a8146d52e40bef9e2b7bc6cd275 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Wed, 20 May 2015 12:55:47 -0400 Subject: NTB: Rename Intel code names to platform names Instead of using the platform code names, use the correct platform names to identify the respective Intel NTB hardware. Signed-off-by: Dave Jiang Signed-off-by: Jon Mason --- Documentation/ntb.txt | 20 +- drivers/ntb/hw/intel/ntb_hw_intel.c | 620 ++++++++++++++++++------------------ drivers/ntb/hw/intel/ntb_hw_intel.h | 290 ++++++++--------- 3 files changed, 465 insertions(+), 465 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt index b48249a7b607..1d9bbabb6c79 100644 --- a/Documentation/ntb.txt +++ b/Documentation/ntb.txt @@ -115,13 +115,13 @@ Module Parameters: * b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if the memory window is large enough, still allow the client to use the second half of the memory window for address translation to the peer. -* snb\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use this - 64 bit address on the bus between the NTB devices for the window at - BAR2, on the upstream side of the link. -* snb\_b2b\_usd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*. -* snb\_b2b\_usd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*. -* snb\_b2b\_usd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*. -* snb\_b2b\_dsd\_bar2\_addr64 - See *snb\_b2b\_bar2\_addr64*. -* snb\_b2b\_dsd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*. -* snb\_b2b\_dsd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*. -* snb\_b2b\_dsd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* xeon\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use + this 64 bit address on the bus between the NTB devices for the window + at BAR2, on the upstream side of the link. +* xeon\_b2b\_usd\_bar4\_addr64 - See *xeon\_b2b\_bar2\_addr64*. +* xeon\_b2b\_usd\_bar4\_addr32 - See *xeon\_b2b\_bar2\_addr64*. +* xeon\_b2b\_usd\_bar5\_addr32 - See *xeon\_b2b\_bar2\_addr64*. +* xeon\_b2b\_dsd\_bar2\_addr64 - See *xeon\_b2b\_bar2\_addr64*. +* xeon\_b2b\_dsd\_bar4\_addr64 - See *xeon\_b2b\_bar2\_addr64*. +* xeon\_b2b\_dsd\_bar4\_addr32 - See *xeon\_b2b\_bar2\_addr64*. +* xeon\_b2b\_dsd\_bar5\_addr32 - See *xeon\_b2b\_bar2\_addr64*. diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index 236b7d33b5af..eeaa1e8f8bd8 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c @@ -72,20 +72,20 @@ MODULE_AUTHOR("Intel Corporation"); #define bar0_off(base, bar) ((base) + ((bar) << 2)) #define bar2_off(base, bar) bar0_off(base, (bar) - 2) -static const struct intel_ntb_reg bwd_reg; -static const struct intel_ntb_alt_reg bwd_pri_reg; -static const struct intel_ntb_alt_reg bwd_sec_reg; -static const struct intel_ntb_alt_reg bwd_b2b_reg; -static const struct intel_ntb_xlat_reg bwd_pri_xlat; -static const struct intel_ntb_xlat_reg bwd_sec_xlat; -static const struct intel_ntb_reg snb_reg; -static const struct intel_ntb_alt_reg snb_pri_reg; -static const struct intel_ntb_alt_reg snb_sec_reg; -static const struct intel_ntb_alt_reg snb_b2b_reg; -static const struct intel_ntb_xlat_reg snb_pri_xlat; -static const struct intel_ntb_xlat_reg snb_sec_xlat; -static struct intel_b2b_addr snb_b2b_usd_addr; -static struct intel_b2b_addr snb_b2b_dsd_addr; +static const struct intel_ntb_reg atom_reg; +static const struct intel_ntb_alt_reg atom_pri_reg; +static const struct intel_ntb_alt_reg atom_sec_reg; +static const struct intel_ntb_alt_reg atom_b2b_reg; +static const struct intel_ntb_xlat_reg atom_pri_xlat; +static const struct intel_ntb_xlat_reg atom_sec_xlat; +static const struct intel_ntb_reg xeon_reg; +static const struct intel_ntb_alt_reg xeon_pri_reg; +static const struct intel_ntb_alt_reg xeon_sec_reg; +static const struct intel_ntb_alt_reg xeon_b2b_reg; +static const struct intel_ntb_xlat_reg xeon_pri_xlat; +static const struct intel_ntb_xlat_reg xeon_sec_xlat; +static struct intel_b2b_addr xeon_b2b_usd_addr; +static struct intel_b2b_addr xeon_b2b_dsd_addr; static const struct ntb_dev_ops intel_ntb_ops; static const struct file_operations intel_ntb_debugfs_info; @@ -105,45 +105,45 @@ MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " "the mw, so the second half can still be used as a mw. Both " "sides MUST set the same value here!"); -module_param_named(snb_b2b_usd_bar2_addr64, - snb_b2b_usd_addr.bar2_addr64, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, - "SNB B2B USD BAR 2 64-bit address"); - -module_param_named(snb_b2b_usd_bar4_addr64, - snb_b2b_usd_addr.bar4_addr64, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, - "SNB B2B USD BAR 4 64-bit address"); - -module_param_named(snb_b2b_usd_bar4_addr32, - snb_b2b_usd_addr.bar4_addr32, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, - "SNB B2B USD split-BAR 4 32-bit address"); - -module_param_named(snb_b2b_usd_bar5_addr32, - snb_b2b_usd_addr.bar5_addr32, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, - "SNB B2B USD split-BAR 5 32-bit address"); - -module_param_named(snb_b2b_dsd_bar2_addr64, - snb_b2b_dsd_addr.bar2_addr64, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, - "SNB B2B DSD BAR 2 64-bit address"); - -module_param_named(snb_b2b_dsd_bar4_addr64, - snb_b2b_dsd_addr.bar4_addr64, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, - "SNB B2B DSD BAR 4 64-bit address"); - -module_param_named(snb_b2b_dsd_bar4_addr32, - snb_b2b_dsd_addr.bar4_addr32, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, - "SNB B2B DSD split-BAR 4 32-bit address"); - -module_param_named(snb_b2b_dsd_bar5_addr32, - snb_b2b_dsd_addr.bar5_addr32, ullong, 0644); -MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, - "SNB B2B DSD split-BAR 5 32-bit address"); +module_param_named(xeon_b2b_usd_bar2_addr64, + xeon_b2b_usd_addr.bar2_addr64, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, + "XEON B2B USD BAR 2 64-bit address"); + +module_param_named(xeon_b2b_usd_bar4_addr64, + xeon_b2b_usd_addr.bar4_addr64, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, + "XEON B2B USD BAR 4 64-bit address"); + +module_param_named(xeon_b2b_usd_bar4_addr32, + xeon_b2b_usd_addr.bar4_addr32, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, + "XEON B2B USD split-BAR 4 32-bit address"); + +module_param_named(xeon_b2b_usd_bar5_addr32, + xeon_b2b_usd_addr.bar5_addr32, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, + "XEON B2B USD split-BAR 5 32-bit address"); + +module_param_named(xeon_b2b_dsd_bar2_addr64, + xeon_b2b_dsd_addr.bar2_addr64, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, + "XEON B2B DSD BAR 2 64-bit address"); + +module_param_named(xeon_b2b_dsd_bar4_addr64, + xeon_b2b_dsd_addr.bar4_addr64, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, + "XEON B2B DSD BAR 4 64-bit address"); + +module_param_named(xeon_b2b_dsd_bar4_addr32, + xeon_b2b_dsd_addr.bar4_addr32, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, + "XEON B2B DSD split-BAR 4 32-bit address"); + +module_param_named(xeon_b2b_dsd_bar5_addr32, + xeon_b2b_dsd_addr.bar5_addr32, ullong, 0644); +MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, + "XEON B2B DSD split-BAR 5 32-bit address"); #ifndef ioread64 #ifdef readq @@ -174,7 +174,7 @@ static inline void _iowrite64(u64 val, void __iomem *mmio) #endif #endif -static inline int pdev_is_bwd(struct pci_dev *pdev) +static inline int pdev_is_atom(struct pci_dev *pdev) { switch (pdev->device) { case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD: @@ -183,7 +183,7 @@ static inline int pdev_is_bwd(struct pci_dev *pdev) return 0; } -static inline int pdev_is_snb(struct pci_dev *pdev) +static inline int pdev_is_xeon(struct pci_dev *pdev) { switch (pdev->device) { case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: @@ -636,70 +636,70 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, off += scnprintf(buf + off, buf_size - off, "LMT45 -\t\t\t%#018llx\n", u.v64); - if (pdev_is_snb(ndev->ntb.pdev)) { + if (pdev_is_xeon(ndev->ntb.pdev)) { if (ntb_topo_is_b2b(ndev->ntb.topo)) { off += scnprintf(buf + off, buf_size - off, "\nNTB Outgoing B2B XLAT:\n"); - u.v64 = ioread64(mmio + SNB_PBAR23XLAT_OFFSET); + u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET); off += scnprintf(buf + off, buf_size - off, "B2B XLAT23 -\t\t%#018llx\n", u.v64); - u.v64 = ioread64(mmio + SNB_PBAR45XLAT_OFFSET); + u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET); off += scnprintf(buf + off, buf_size - off, "B2B XLAT45 -\t\t%#018llx\n", u.v64); - u.v64 = ioread64(mmio + SNB_PBAR23LMT_OFFSET); + u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET); off += scnprintf(buf + off, buf_size - off, "B2B LMT23 -\t\t%#018llx\n", u.v64); - u.v64 = ioread64(mmio + SNB_PBAR45LMT_OFFSET); + u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET); off += scnprintf(buf + off, buf_size - off, "B2B LMT45 -\t\t%#018llx\n", u.v64); off += scnprintf(buf + off, buf_size - off, "\nNTB Secondary BAR:\n"); - u.v64 = ioread64(mmio + SNB_SBAR0BASE_OFFSET); + u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET); off += scnprintf(buf + off, buf_size - off, "SBAR01 -\t\t%#018llx\n", u.v64); - u.v64 = ioread64(mmio + SNB_SBAR23BASE_OFFSET); + u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET); off += scnprintf(buf + off, buf_size - off, "SBAR23 -\t\t%#018llx\n", u.v64); - u.v64 = ioread64(mmio + SNB_SBAR45BASE_OFFSET); + u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET); off += scnprintf(buf + off, buf_size - off, "SBAR45 -\t\t%#018llx\n", u.v64); } off += scnprintf(buf + off, buf_size - off, - "\nSNB NTB Statistics:\n"); + "\nXEON NTB Statistics:\n"); - u.v16 = ioread16(mmio + SNB_USMEMMISS_OFFSET); + u.v16 = ioread16(mmio + XEON_USMEMMISS_OFFSET); off += scnprintf(buf + off, buf_size - off, "Upstream Memory Miss -\t%u\n", u.v16); off += scnprintf(buf + off, buf_size - off, - "\nSNB NTB Hardware Errors:\n"); + "\nXEON NTB Hardware Errors:\n"); if (!pci_read_config_word(ndev->ntb.pdev, - SNB_DEVSTS_OFFSET, &u.v16)) + XEON_DEVSTS_OFFSET, &u.v16)) off += scnprintf(buf + off, buf_size - off, "DEVSTS -\t\t%#06x\n", u.v16); if (!pci_read_config_word(ndev->ntb.pdev, - SNB_LINK_STATUS_OFFSET, &u.v16)) + XEON_LINK_STATUS_OFFSET, &u.v16)) off += scnprintf(buf + off, buf_size - off, "LNKSTS -\t\t%#06x\n", u.v16); if (!pci_read_config_dword(ndev->ntb.pdev, - SNB_UNCERRSTS_OFFSET, &u.v32)) + XEON_UNCERRSTS_OFFSET, &u.v32)) off += scnprintf(buf + off, buf_size - off, "UNCERRSTS -\t\t%#06x\n", u.v32); if (!pci_read_config_dword(ndev->ntb.pdev, - SNB_CORERRSTS_OFFSET, &u.v32)) + XEON_CORERRSTS_OFFSET, &u.v32)) off += scnprintf(buf + off, buf_size - off, "CORERRSTS -\t\t%#06x\n", u.v32); } @@ -1091,67 +1091,67 @@ static int intel_ntb_peer_spad_write(struct ntb_dev *ntb, ndev->peer_reg->spad); } -/* BWD */ +/* ATOM */ -static u64 bwd_db_ioread(void __iomem *mmio) +static u64 atom_db_ioread(void __iomem *mmio) { return ioread64(mmio); } -static void bwd_db_iowrite(u64 bits, void __iomem *mmio) +static void atom_db_iowrite(u64 bits, void __iomem *mmio) { iowrite64(bits, mmio); } -static int bwd_poll_link(struct intel_ntb_dev *ndev) +static int atom_poll_link(struct intel_ntb_dev *ndev) { u32 ntb_ctl; - ntb_ctl = ioread32(ndev->self_mmio + BWD_NTBCNTL_OFFSET); + ntb_ctl = ioread32(ndev->self_mmio + ATOM_NTBCNTL_OFFSET); if (ntb_ctl == ndev->ntb_ctl) return 0; ndev->ntb_ctl = ntb_ctl; - ndev->lnk_sta = ioread32(ndev->self_mmio + BWD_LINK_STATUS_OFFSET); + ndev->lnk_sta = ioread32(ndev->self_mmio + ATOM_LINK_STATUS_OFFSET); return 1; } -static int bwd_link_is_up(struct intel_ntb_dev *ndev) +static int atom_link_is_up(struct intel_ntb_dev *ndev) { - return BWD_NTB_CTL_ACTIVE(ndev->ntb_ctl); + return ATOM_NTB_CTL_ACTIVE(ndev->ntb_ctl); } -static int bwd_link_is_err(struct intel_ntb_dev *ndev) +static int atom_link_is_err(struct intel_ntb_dev *ndev) { - if (ioread32(ndev->self_mmio + BWD_LTSSMSTATEJMP_OFFSET) - & BWD_LTSSMSTATEJMP_FORCEDETECT) + if (ioread32(ndev->self_mmio + ATOM_LTSSMSTATEJMP_OFFSET) + & ATOM_LTSSMSTATEJMP_FORCEDETECT) return 1; - if (ioread32(ndev->self_mmio + BWD_IBSTERRRCRVSTS0_OFFSET) - & BWD_IBIST_ERR_OFLOW) + if (ioread32(ndev->self_mmio + ATOM_IBSTERRRCRVSTS0_OFFSET) + & ATOM_IBIST_ERR_OFLOW) return 1; return 0; } -static inline enum ntb_topo bwd_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) +static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) { - switch (ppd & BWD_PPD_TOPO_MASK) { - case BWD_PPD_TOPO_B2B_USD: + switch (ppd & ATOM_PPD_TOPO_MASK) { + case ATOM_PPD_TOPO_B2B_USD: dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd); return NTB_TOPO_B2B_USD; - case BWD_PPD_TOPO_B2B_DSD: + case ATOM_PPD_TOPO_B2B_DSD: dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd); return NTB_TOPO_B2B_DSD; - case BWD_PPD_TOPO_PRI_USD: - case BWD_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ - case BWD_PPD_TOPO_SEC_USD: - case BWD_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ + case ATOM_PPD_TOPO_PRI_USD: + case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ + case ATOM_PPD_TOPO_SEC_USD: + case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd); return NTB_TOPO_NONE; } @@ -1160,28 +1160,28 @@ static inline enum ntb_topo bwd_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) return NTB_TOPO_NONE; } -static void bwd_link_hb(struct work_struct *work) +static void atom_link_hb(struct work_struct *work) { struct intel_ntb_dev *ndev = hb_ndev(work); unsigned long poll_ts; void __iomem *mmio; u32 status32; - poll_ts = ndev->last_ts + BWD_LINK_HB_TIMEOUT; + poll_ts = ndev->last_ts + ATOM_LINK_HB_TIMEOUT; /* Delay polling the link status if an interrupt was received, * unless the cached link status says the link is down. */ - if (time_after(poll_ts, jiffies) && bwd_link_is_up(ndev)) { + if (time_after(poll_ts, jiffies) && atom_link_is_up(ndev)) { schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies); return; } - if (bwd_poll_link(ndev)) + if (atom_poll_link(ndev)) ntb_link_event(&ndev->ntb); - if (bwd_link_is_up(ndev) || !bwd_link_is_err(ndev)) { - schedule_delayed_work(&ndev->hb_timer, BWD_LINK_HB_TIMEOUT); + if (atom_link_is_up(ndev) || !atom_link_is_err(ndev)) { + schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT); return; } @@ -1190,91 +1190,91 @@ static void bwd_link_hb(struct work_struct *work) mmio = ndev->self_mmio; /* Driver resets the NTB ModPhy lanes - magic! */ - iowrite8(0xe0, mmio + BWD_MODPHY_PCSREG6); - iowrite8(0x40, mmio + BWD_MODPHY_PCSREG4); - iowrite8(0x60, mmio + BWD_MODPHY_PCSREG4); - iowrite8(0x60, mmio + BWD_MODPHY_PCSREG6); + iowrite8(0xe0, mmio + ATOM_MODPHY_PCSREG6); + iowrite8(0x40, mmio + ATOM_MODPHY_PCSREG4); + iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG4); + iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG6); /* Driver waits 100ms to allow the NTB ModPhy to settle */ msleep(100); /* Clear AER Errors, write to clear */ - status32 = ioread32(mmio + BWD_ERRCORSTS_OFFSET); + status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET); dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32); status32 &= PCI_ERR_COR_REP_ROLL; - iowrite32(status32, mmio + BWD_ERRCORSTS_OFFSET); + iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET); /* Clear unexpected electrical idle event in LTSSM, write to clear */ - status32 = ioread32(mmio + BWD_LTSSMERRSTS0_OFFSET); + status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET); dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32); - status32 |= BWD_LTSSMERRSTS0_UNEXPECTEDEI; - iowrite32(status32, mmio + BWD_LTSSMERRSTS0_OFFSET); + status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; + iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET); /* Clear DeSkew Buffer error, write to clear */ - status32 = ioread32(mmio + BWD_DESKEWSTS_OFFSET); + status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET); dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32); - status32 |= BWD_DESKEWSTS_DBERR; - iowrite32(status32, mmio + BWD_DESKEWSTS_OFFSET); + status32 |= ATOM_DESKEWSTS_DBERR; + iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET); - status32 = ioread32(mmio + BWD_IBSTERRRCRVSTS0_OFFSET); + status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET); dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32); - status32 &= BWD_IBIST_ERR_OFLOW; - iowrite32(status32, mmio + BWD_IBSTERRRCRVSTS0_OFFSET); + status32 &= ATOM_IBIST_ERR_OFLOW; + iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET); /* Releases the NTB state machine to allow the link to retrain */ - status32 = ioread32(mmio + BWD_LTSSMSTATEJMP_OFFSET); + status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET); dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32); - status32 &= ~BWD_LTSSMSTATEJMP_FORCEDETECT; - iowrite32(status32, mmio + BWD_LTSSMSTATEJMP_OFFSET); + status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; + iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET); /* There is a potential race between the 2 NTB devices recovering at the * same time. If the times are the same, the link will not recover and * the driver will be stuck in this loop forever. Add a random interval * to the recovery time to prevent this race. */ - schedule_delayed_work(&ndev->hb_timer, BWD_LINK_RECOVERY_TIME - + prandom_u32() % BWD_LINK_RECOVERY_TIME); + schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_RECOVERY_TIME + + prandom_u32() % ATOM_LINK_RECOVERY_TIME); } -static int bwd_init_isr(struct intel_ntb_dev *ndev) +static int atom_init_isr(struct intel_ntb_dev *ndev) { int rc; - rc = ndev_init_isr(ndev, 1, BWD_DB_MSIX_VECTOR_COUNT, - BWD_DB_MSIX_VECTOR_SHIFT, BWD_DB_TOTAL_SHIFT); + rc = ndev_init_isr(ndev, 1, ATOM_DB_MSIX_VECTOR_COUNT, + ATOM_DB_MSIX_VECTOR_SHIFT, ATOM_DB_TOTAL_SHIFT); if (rc) return rc; - /* BWD doesn't have link status interrupt, poll on that platform */ + /* ATOM doesn't have link status interrupt, poll on that platform */ ndev->last_ts = jiffies; - INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_hb); - schedule_delayed_work(&ndev->hb_timer, BWD_LINK_HB_TIMEOUT); + INIT_DELAYED_WORK(&ndev->hb_timer, atom_link_hb); + schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT); return 0; } -static void bwd_deinit_isr(struct intel_ntb_dev *ndev) +static void atom_deinit_isr(struct intel_ntb_dev *ndev) { cancel_delayed_work_sync(&ndev->hb_timer); ndev_deinit_isr(ndev); } -static int bwd_init_ntb(struct intel_ntb_dev *ndev) +static int atom_init_ntb(struct intel_ntb_dev *ndev) { - ndev->mw_count = BWD_MW_COUNT; - ndev->spad_count = BWD_SPAD_COUNT; - ndev->db_count = BWD_DB_COUNT; + ndev->mw_count = ATOM_MW_COUNT; + ndev->spad_count = ATOM_SPAD_COUNT; + ndev->db_count = ATOM_DB_COUNT; switch (ndev->ntb.topo) { case NTB_TOPO_B2B_USD: case NTB_TOPO_B2B_DSD: - ndev->self_reg = &bwd_pri_reg; - ndev->peer_reg = &bwd_b2b_reg; - ndev->xlat_reg = &bwd_sec_xlat; + ndev->self_reg = &atom_pri_reg; + ndev->peer_reg = &atom_b2b_reg; + ndev->xlat_reg = &atom_sec_xlat; /* Enable Bus Master and Memory Space on the secondary side */ iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, - ndev->self_mmio + BWD_SPCICMD_OFFSET); + ndev->self_mmio + ATOM_SPCICMD_OFFSET); break; @@ -1287,31 +1287,31 @@ static int bwd_init_ntb(struct intel_ntb_dev *ndev) return 0; } -static int bwd_init_dev(struct intel_ntb_dev *ndev) +static int atom_init_dev(struct intel_ntb_dev *ndev) { u32 ppd; int rc; - rc = pci_read_config_dword(ndev->ntb.pdev, BWD_PPD_OFFSET, &ppd); + rc = pci_read_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, &ppd); if (rc) return -EIO; - ndev->ntb.topo = bwd_ppd_topo(ndev, ppd); + ndev->ntb.topo = atom_ppd_topo(ndev, ppd); if (ndev->ntb.topo == NTB_TOPO_NONE) return -EINVAL; - rc = bwd_init_ntb(ndev); + rc = atom_init_ntb(ndev); if (rc) return rc; - rc = bwd_init_isr(ndev); + rc = atom_init_isr(ndev); if (rc) return rc; if (ndev->ntb.topo != NTB_TOPO_SEC) { /* Initiate PCI-E link training */ - rc = pci_write_config_dword(ndev->ntb.pdev, BWD_PPD_OFFSET, - ppd | BWD_PPD_INIT_LINK); + rc = pci_write_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, + ppd | ATOM_PPD_INIT_LINK); if (rc) return rc; } @@ -1319,24 +1319,24 @@ static int bwd_init_dev(struct intel_ntb_dev *ndev) return 0; } -static void bwd_deinit_dev(struct intel_ntb_dev *ndev) +static void atom_deinit_dev(struct intel_ntb_dev *ndev) { - bwd_deinit_isr(ndev); + atom_deinit_isr(ndev); } -/* SNB */ +/* XEON */ -static u64 snb_db_ioread(void __iomem *mmio) +static u64 xeon_db_ioread(void __iomem *mmio) { return (u64)ioread16(mmio); } -static void snb_db_iowrite(u64 bits, void __iomem *mmio) +static void xeon_db_iowrite(u64 bits, void __iomem *mmio) { iowrite16((u16)bits, mmio); } -static int snb_poll_link(struct intel_ntb_dev *ndev) +static int xeon_poll_link(struct intel_ntb_dev *ndev) { u16 reg_val; int rc; @@ -1346,7 +1346,7 @@ static int snb_poll_link(struct intel_ntb_dev *ndev) ndev->self_reg->db_bell); rc = pci_read_config_word(ndev->ntb.pdev, - SNB_LINK_STATUS_OFFSET, ®_val); + XEON_LINK_STATUS_OFFSET, ®_val); if (rc) return 0; @@ -1358,7 +1358,7 @@ static int snb_poll_link(struct intel_ntb_dev *ndev) return 1; } -static int snb_link_is_up(struct intel_ntb_dev *ndev) +static int xeon_link_is_up(struct intel_ntb_dev *ndev) { if (ndev->ntb.topo == NTB_TOPO_SEC) return 1; @@ -1366,52 +1366,52 @@ static int snb_link_is_up(struct intel_ntb_dev *ndev) return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); } -static inline enum ntb_topo snb_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd) +static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd) { - switch (ppd & SNB_PPD_TOPO_MASK) { - case SNB_PPD_TOPO_B2B_USD: + switch (ppd & XEON_PPD_TOPO_MASK) { + case XEON_PPD_TOPO_B2B_USD: return NTB_TOPO_B2B_USD; - case SNB_PPD_TOPO_B2B_DSD: + case XEON_PPD_TOPO_B2B_DSD: return NTB_TOPO_B2B_DSD; - case SNB_PPD_TOPO_PRI_USD: - case SNB_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ + case XEON_PPD_TOPO_PRI_USD: + case XEON_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ return NTB_TOPO_PRI; - case SNB_PPD_TOPO_SEC_USD: - case SNB_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ + case XEON_PPD_TOPO_SEC_USD: + case XEON_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ return NTB_TOPO_SEC; } return NTB_TOPO_NONE; } -static inline int snb_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd) +static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd) { - if (ppd & SNB_PPD_SPLIT_BAR_MASK) { + if (ppd & XEON_PPD_SPLIT_BAR_MASK) { dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd); return 1; } return 0; } -static int snb_init_isr(struct intel_ntb_dev *ndev) +static int xeon_init_isr(struct intel_ntb_dev *ndev) { - return ndev_init_isr(ndev, SNB_DB_MSIX_VECTOR_COUNT, - SNB_DB_MSIX_VECTOR_COUNT, - SNB_DB_MSIX_VECTOR_SHIFT, - SNB_DB_TOTAL_SHIFT); + return ndev_init_isr(ndev, XEON_DB_MSIX_VECTOR_COUNT, + XEON_DB_MSIX_VECTOR_COUNT, + XEON_DB_MSIX_VECTOR_SHIFT, + XEON_DB_TOTAL_SHIFT); } -static void snb_deinit_isr(struct intel_ntb_dev *ndev) +static void xeon_deinit_isr(struct intel_ntb_dev *ndev) { ndev_deinit_isr(ndev); } -static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, - const struct intel_b2b_addr *addr, - const struct intel_b2b_addr *peer_addr) +static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev, + const struct intel_b2b_addr *addr, + const struct intel_b2b_addr *peer_addr) { struct pci_dev *pdev; void __iomem *mmio; @@ -1438,11 +1438,11 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size); - if (b2b_mw_share && SNB_B2B_MIN_SIZE <= bar_size >> 1) { + if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) { dev_dbg(ndev_dev(ndev), "b2b using first half of bar\n"); ndev->b2b_off = bar_size >> 1; - } else if (SNB_B2B_MIN_SIZE <= bar_size) { + } else if (XEON_B2B_MIN_SIZE <= bar_size) { dev_dbg(ndev_dev(ndev), "b2b using whole bar\n"); ndev->b2b_off = 0; @@ -1460,7 +1460,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, * Note: code for each specific bar size register, because the register * offsets are not in a consistent order (bar5sz comes after ppd, odd). */ - pci_read_config_byte(pdev, SNB_PBAR23SZ_OFFSET, &bar_sz); + pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz); if (b2b_bar == 2) { if (ndev->b2b_off) @@ -1468,12 +1468,12 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, else bar_sz = 0; } - pci_write_config_byte(pdev, SNB_SBAR23SZ_OFFSET, bar_sz); - pci_read_config_byte(pdev, SNB_SBAR23SZ_OFFSET, &bar_sz); + pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz); if (!ndev->bar4_split) { - pci_read_config_byte(pdev, SNB_PBAR45SZ_OFFSET, &bar_sz); + pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz); if (b2b_bar == 4) { if (ndev->b2b_off) @@ -1481,11 +1481,11 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, else bar_sz = 0; } - pci_write_config_byte(pdev, SNB_SBAR45SZ_OFFSET, bar_sz); - pci_read_config_byte(pdev, SNB_SBAR45SZ_OFFSET, &bar_sz); + pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz); } else { - pci_read_config_byte(pdev, SNB_PBAR4SZ_OFFSET, &bar_sz); + pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz); if (b2b_bar == 4) { if (ndev->b2b_off) @@ -1493,11 +1493,11 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, else bar_sz = 0; } - pci_write_config_byte(pdev, SNB_SBAR4SZ_OFFSET, bar_sz); - pci_read_config_byte(pdev, SNB_SBAR4SZ_OFFSET, &bar_sz); + pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz); - pci_read_config_byte(pdev, SNB_PBAR5SZ_OFFSET, &bar_sz); + pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz); if (b2b_bar == 5) { if (ndev->b2b_off) @@ -1505,8 +1505,8 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, else bar_sz = 0; } - pci_write_config_byte(pdev, SNB_SBAR5SZ_OFFSET, bar_sz); - pci_read_config_byte(pdev, SNB_SBAR5SZ_OFFSET, &bar_sz); + pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz); + pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz); dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz); } @@ -1525,7 +1525,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, return -EIO; dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr); - iowrite64(bar_addr, mmio + SNB_SBAR0BASE_OFFSET); + iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET); /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar. * The b2b bar is either disabled above, or configured half-size, and @@ -1533,96 +1533,96 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, */ bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); - iowrite64(bar_addr, mmio + SNB_SBAR23BASE_OFFSET); - bar_addr = ioread64(mmio + SNB_SBAR23BASE_OFFSET); + iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET); + bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr); if (!ndev->bar4_split) { bar_addr = addr->bar4_addr64 + (b2b_bar == 4 ? ndev->b2b_off : 0); - iowrite64(bar_addr, mmio + SNB_SBAR45BASE_OFFSET); - bar_addr = ioread64(mmio + SNB_SBAR45BASE_OFFSET); + iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET); + bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr); } else { bar_addr = addr->bar4_addr32 + (b2b_bar == 4 ? ndev->b2b_off : 0); - iowrite32(bar_addr, mmio + SNB_SBAR4BASE_OFFSET); - bar_addr = ioread32(mmio + SNB_SBAR4BASE_OFFSET); + iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET); + bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr); bar_addr = addr->bar5_addr32 + (b2b_bar == 5 ? ndev->b2b_off : 0); - iowrite32(bar_addr, mmio + SNB_SBAR5BASE_OFFSET); - bar_addr = ioread32(mmio + SNB_SBAR5BASE_OFFSET); + iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET); + bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr); } /* setup incoming bar limits == base addrs (zero length windows) */ bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); - iowrite64(bar_addr, mmio + SNB_SBAR23LMT_OFFSET); - bar_addr = ioread64(mmio + SNB_SBAR23LMT_OFFSET); + iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET); + bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr); if (!ndev->bar4_split) { bar_addr = addr->bar4_addr64 + (b2b_bar == 4 ? ndev->b2b_off : 0); - iowrite64(bar_addr, mmio + SNB_SBAR45LMT_OFFSET); - bar_addr = ioread64(mmio + SNB_SBAR45LMT_OFFSET); + iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET); + bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr); } else { bar_addr = addr->bar4_addr32 + (b2b_bar == 4 ? ndev->b2b_off : 0); - iowrite32(bar_addr, mmio + SNB_SBAR4LMT_OFFSET); - bar_addr = ioread32(mmio + SNB_SBAR4LMT_OFFSET); + iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET); + bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr); bar_addr = addr->bar5_addr32 + (b2b_bar == 5 ? ndev->b2b_off : 0); - iowrite32(bar_addr, mmio + SNB_SBAR5LMT_OFFSET); - bar_addr = ioread32(mmio + SNB_SBAR5LMT_OFFSET); + iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET); + bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET); dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr); } /* zero incoming translation addrs */ - iowrite64(0, mmio + SNB_SBAR23XLAT_OFFSET); + iowrite64(0, mmio + XEON_SBAR23XLAT_OFFSET); if (!ndev->bar4_split) { - iowrite64(0, mmio + SNB_SBAR45XLAT_OFFSET); + iowrite64(0, mmio + XEON_SBAR45XLAT_OFFSET); } else { - iowrite32(0, mmio + SNB_SBAR4XLAT_OFFSET); - iowrite32(0, mmio + SNB_SBAR5XLAT_OFFSET); + iowrite32(0, mmio + XEON_SBAR4XLAT_OFFSET); + iowrite32(0, mmio + XEON_SBAR5XLAT_OFFSET); } /* zero outgoing translation limits (whole bar size windows) */ - iowrite64(0, mmio + SNB_PBAR23LMT_OFFSET); + iowrite64(0, mmio + XEON_PBAR23LMT_OFFSET); if (!ndev->bar4_split) { - iowrite64(0, mmio + SNB_PBAR45LMT_OFFSET); + iowrite64(0, mmio + XEON_PBAR45LMT_OFFSET); } else { - iowrite32(0, mmio + SNB_PBAR4LMT_OFFSET); - iowrite32(0, mmio + SNB_PBAR5LMT_OFFSET); + iowrite32(0, mmio + XEON_PBAR4LMT_OFFSET); + iowrite32(0, mmio + XEON_PBAR5LMT_OFFSET); } /* set outgoing translation offsets */ bar_addr = peer_addr->bar2_addr64; - iowrite64(bar_addr, mmio + SNB_PBAR23XLAT_OFFSET); - bar_addr = ioread64(mmio + SNB_PBAR23XLAT_OFFSET); + iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET); + bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET); dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr); if (!ndev->bar4_split) { bar_addr = peer_addr->bar4_addr64; - iowrite64(bar_addr, mmio + SNB_PBAR45XLAT_OFFSET); - bar_addr = ioread64(mmio + SNB_PBAR45XLAT_OFFSET); + iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET); + bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET); dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr); } else { bar_addr = peer_addr->bar4_addr32; - iowrite32(bar_addr, mmio + SNB_PBAR4XLAT_OFFSET); - bar_addr = ioread32(mmio + SNB_PBAR4XLAT_OFFSET); + iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET); + bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET); dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr); bar_addr = peer_addr->bar5_addr32; - iowrite32(bar_addr, mmio + SNB_PBAR5XLAT_OFFSET); - bar_addr = ioread32(mmio + SNB_PBAR5XLAT_OFFSET); + iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET); + bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET); dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr); } @@ -1642,13 +1642,13 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */ dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr); - iowrite32(bar_addr, mmio + SNB_B2B_XLAT_OFFSETL); - iowrite32(bar_addr >> 32, mmio + SNB_B2B_XLAT_OFFSETU); + iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL); + iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU); if (b2b_bar) { /* map peer ntb mmio config space registers */ ndev->peer_mmio = pci_iomap(pdev, b2b_bar, - SNB_B2B_MIN_SIZE); + XEON_B2B_MIN_SIZE); if (!ndev->peer_mmio) return -EIO; } @@ -1656,7 +1656,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, return 0; } -static int snb_init_ntb(struct intel_ntb_dev *ndev) +static int xeon_init_ntb(struct intel_ntb_dev *ndev) { int rc; u32 ntb_ctl; @@ -1664,11 +1664,11 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev) if (ndev->bar4_split) ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT; else - ndev->mw_count = SNB_MW_COUNT; + ndev->mw_count = XEON_MW_COUNT; - ndev->spad_count = SNB_SPAD_COUNT; - ndev->db_count = SNB_DB_COUNT; - ndev->db_link_mask = SNB_DB_LINK_BIT; + ndev->spad_count = XEON_SPAD_COUNT; + ndev->db_count = XEON_DB_COUNT; + ndev->db_link_mask = XEON_DB_LINK_BIT; switch (ndev->ntb.topo) { case NTB_TOPO_PRI: @@ -1684,9 +1684,9 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev) /* use half the spads for the peer */ ndev->spad_count >>= 1; - ndev->self_reg = &snb_pri_reg; - ndev->peer_reg = &snb_sec_reg; - ndev->xlat_reg = &snb_sec_xlat; + ndev->self_reg = &xeon_pri_reg; + ndev->peer_reg = &xeon_sec_reg; + ndev->xlat_reg = &xeon_sec_xlat; break; case NTB_TOPO_SEC: @@ -1696,19 +1696,19 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev) } /* use half the spads for the peer */ ndev->spad_count >>= 1; - ndev->self_reg = &snb_sec_reg; - ndev->peer_reg = &snb_pri_reg; - ndev->xlat_reg = &snb_pri_xlat; + ndev->self_reg = &xeon_sec_reg; + ndev->peer_reg = &xeon_pri_reg; + ndev->xlat_reg = &xeon_pri_xlat; break; case NTB_TOPO_B2B_USD: case NTB_TOPO_B2B_DSD: - ndev->self_reg = &snb_pri_reg; - ndev->peer_reg = &snb_b2b_reg; - ndev->xlat_reg = &snb_sec_xlat; + ndev->self_reg = &xeon_pri_reg; + ndev->peer_reg = &xeon_b2b_reg; + ndev->xlat_reg = &xeon_sec_xlat; if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { - ndev->peer_reg = &snb_pri_reg; + ndev->peer_reg = &xeon_pri_reg; if (b2b_mw_idx < 0) ndev->b2b_idx = b2b_mw_idx + ndev->mw_count; @@ -1725,20 +1725,20 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev) } if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { - rc = snb_setup_b2b_mw(ndev, - &snb_b2b_dsd_addr, - &snb_b2b_usd_addr); + rc = xeon_setup_b2b_mw(ndev, + &xeon_b2b_dsd_addr, + &xeon_b2b_usd_addr); } else { - rc = snb_setup_b2b_mw(ndev, - &snb_b2b_usd_addr, - &snb_b2b_dsd_addr); + rc = xeon_setup_b2b_mw(ndev, + &xeon_b2b_usd_addr, + &xeon_b2b_dsd_addr); } if (rc) return rc; /* Enable Bus Master and Memory Space on the secondary side */ iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, - ndev->self_mmio + SNB_SPCICMD_OFFSET); + ndev->self_mmio + XEON_SPCICMD_OFFSET); break; @@ -1755,7 +1755,7 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev) return 0; } -static int snb_init_dev(struct intel_ntb_dev *ndev) +static int xeon_init_dev(struct intel_ntb_dev *ndev) { struct pci_dev *pdev; u8 ppd; @@ -1821,20 +1821,20 @@ static int snb_init_dev(struct intel_ntb_dev *ndev) break; } - ndev->reg = &snb_reg; + ndev->reg = &xeon_reg; - rc = pci_read_config_byte(pdev, SNB_PPD_OFFSET, &ppd); + rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd); if (rc) return -EIO; - ndev->ntb.topo = snb_ppd_topo(ndev, ppd); + ndev->ntb.topo = xeon_ppd_topo(ndev, ppd); dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd, ntb_topo_string(ndev->ntb.topo)); if (ndev->ntb.topo == NTB_TOPO_NONE) return -EINVAL; if (ndev->ntb.topo != NTB_TOPO_SEC) { - ndev->bar4_split = snb_ppd_bar4_split(ndev, ppd); + ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd); dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n", ppd, ndev->bar4_split); } else { @@ -1849,16 +1849,16 @@ static int snb_init_dev(struct intel_ntb_dev *ndev) mem, ndev->bar4_split); } - rc = snb_init_ntb(ndev); + rc = xeon_init_ntb(ndev); if (rc) return rc; - return snb_init_isr(ndev); + return xeon_init_isr(ndev); } -static void snb_deinit_dev(struct intel_ntb_dev *ndev) +static void xeon_deinit_dev(struct intel_ntb_dev *ndev) { - snb_deinit_isr(ndev); + xeon_deinit_isr(ndev); } static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev) @@ -1963,7 +1963,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, node = dev_to_node(&pdev->dev); - if (pdev_is_bwd(pdev)) { + if (pdev_is_atom(pdev)) { ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); if (!ndev) { rc = -ENOMEM; @@ -1976,11 +1976,11 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, if (rc) goto err_init_pci; - rc = bwd_init_dev(ndev); + rc = atom_init_dev(ndev); if (rc) goto err_init_dev; - } else if (pdev_is_snb(pdev)) { + } else if (pdev_is_xeon(pdev)) { ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); if (!ndev) { rc = -ENOMEM; @@ -1993,7 +1993,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, if (rc) goto err_init_pci; - rc = snb_init_dev(ndev); + rc = xeon_init_dev(ndev); if (rc) goto err_init_dev; @@ -2016,10 +2016,10 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, err_register: ndev_deinit_debugfs(ndev); - if (pdev_is_bwd(pdev)) - bwd_deinit_dev(ndev); - else if (pdev_is_snb(pdev)) - snb_deinit_dev(ndev); + if (pdev_is_atom(pdev)) + atom_deinit_dev(ndev); + else if (pdev_is_xeon(pdev)) + xeon_deinit_dev(ndev); err_init_dev: intel_ntb_deinit_pci(ndev); err_init_pci: @@ -2034,70 +2034,70 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev) ntb_unregister_device(&ndev->ntb); ndev_deinit_debugfs(ndev); - if (pdev_is_bwd(pdev)) - bwd_deinit_dev(ndev); - else if (pdev_is_snb(pdev)) - snb_deinit_dev(ndev); + if (pdev_is_atom(pdev)) + atom_deinit_dev(ndev); + else if (pdev_is_xeon(pdev)) + xeon_deinit_dev(ndev); intel_ntb_deinit_pci(ndev); kfree(ndev); } -static const struct intel_ntb_reg bwd_reg = { - .poll_link = bwd_poll_link, - .link_is_up = bwd_link_is_up, - .db_ioread = bwd_db_ioread, - .db_iowrite = bwd_db_iowrite, +static const struct intel_ntb_reg atom_reg = { + .poll_link = atom_poll_link, + .link_is_up = atom_link_is_up, + .db_ioread = atom_db_ioread, + .db_iowrite = atom_db_iowrite, .db_size = sizeof(u64), - .ntb_ctl = BWD_NTBCNTL_OFFSET, + .ntb_ctl = ATOM_NTBCNTL_OFFSET, .mw_bar = {2, 4}, }; -static const struct intel_ntb_alt_reg bwd_pri_reg = { - .db_bell = BWD_PDOORBELL_OFFSET, - .db_mask = BWD_PDBMSK_OFFSET, - .spad = BWD_SPAD_OFFSET, +static const struct intel_ntb_alt_reg atom_pri_reg = { + .db_bell = ATOM_PDOORBELL_OFFSET, + .db_mask = ATOM_PDBMSK_OFFSET, + .spad = ATOM_SPAD_OFFSET, }; -static const struct intel_ntb_alt_reg bwd_b2b_reg = { - .db_bell = BWD_B2B_DOORBELL_OFFSET, - .spad = BWD_B2B_SPAD_OFFSET, +static const struct intel_ntb_alt_reg atom_b2b_reg = { + .db_bell = ATOM_B2B_DOORBELL_OFFSET, + .spad = ATOM_B2B_SPAD_OFFSET, }; -static const struct intel_ntb_xlat_reg bwd_sec_xlat = { - /* FIXME : .bar0_base = BWD_SBAR0BASE_OFFSET, */ - /* FIXME : .bar2_limit = BWD_SBAR2LMT_OFFSET, */ - .bar2_xlat = BWD_SBAR2XLAT_OFFSET, +static const struct intel_ntb_xlat_reg atom_sec_xlat = { + /* FIXME : .bar0_base = ATOM_SBAR0BASE_OFFSET, */ + /* FIXME : .bar2_limit = ATOM_SBAR2LMT_OFFSET, */ + .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, }; -static const struct intel_ntb_reg snb_reg = { - .poll_link = snb_poll_link, - .link_is_up = snb_link_is_up, - .db_ioread = snb_db_ioread, - .db_iowrite = snb_db_iowrite, +static const struct intel_ntb_reg xeon_reg = { + .poll_link = xeon_poll_link, + .link_is_up = xeon_link_is_up, + .db_ioread = xeon_db_ioread, + .db_iowrite = xeon_db_iowrite, .db_size = sizeof(u32), - .ntb_ctl = SNB_NTBCNTL_OFFSET, + .ntb_ctl = XEON_NTBCNTL_OFFSET, .mw_bar = {2, 4, 5}, }; -static const struct intel_ntb_alt_reg snb_pri_reg = { - .db_bell = SNB_PDOORBELL_OFFSET, - .db_mask = SNB_PDBMSK_OFFSET, - .spad = SNB_SPAD_OFFSET, +static const struct intel_ntb_alt_reg xeon_pri_reg = { + .db_bell = XEON_PDOORBELL_OFFSET, + .db_mask = XEON_PDBMSK_OFFSET, + .spad = XEON_SPAD_OFFSET, }; -static const struct intel_ntb_alt_reg snb_sec_reg = { - .db_bell = SNB_SDOORBELL_OFFSET, - .db_mask = SNB_SDBMSK_OFFSET, +static const struct intel_ntb_alt_reg xeon_sec_reg = { + .db_bell = XEON_SDOORBELL_OFFSET, + .db_mask = XEON_SDBMSK_OFFSET, /* second half of the scratchpads */ - .spad = SNB_SPAD_OFFSET + (SNB_SPAD_COUNT << 1), + .spad = XEON_SPAD_OFFSET + (XEON_SPAD_COUNT << 1), }; -static const struct intel_ntb_alt_reg snb_b2b_reg = { - .db_bell = SNB_B2B_DOORBELL_OFFSET, - .spad = SNB_B2B_SPAD_OFFSET, +static const struct intel_ntb_alt_reg xeon_b2b_reg = { + .db_bell = XEON_B2B_DOORBELL_OFFSET, + .spad = XEON_B2B_SPAD_OFFSET, }; -static const struct intel_ntb_xlat_reg snb_pri_xlat = { +static const struct intel_ntb_xlat_reg xeon_pri_xlat = { /* Note: no primary .bar0_base visible to the secondary side. * * The secondary side cannot get the base address stored in primary @@ -2108,28 +2108,28 @@ static const struct intel_ntb_xlat_reg snb_pri_xlat = { * window by setting the limit equal to base, nor can it limit the size * of the memory window by setting the limit to base + size. */ - .bar2_limit = SNB_PBAR23LMT_OFFSET, - .bar2_xlat = SNB_PBAR23XLAT_OFFSET, + .bar2_limit = XEON_PBAR23LMT_OFFSET, + .bar2_xlat = XEON_PBAR23XLAT_OFFSET, }; -static const struct intel_ntb_xlat_reg snb_sec_xlat = { - .bar0_base = SNB_SBAR0BASE_OFFSET, - .bar2_limit = SNB_SBAR23LMT_OFFSET, - .bar2_xlat = SNB_SBAR23XLAT_OFFSET, +static const struct intel_ntb_xlat_reg xeon_sec_xlat = { + .bar0_base = XEON_SBAR0BASE_OFFSET, + .bar2_limit = XEON_SBAR23LMT_OFFSET, + .bar2_xlat = XEON_SBAR23XLAT_OFFSET, }; -static struct intel_b2b_addr snb_b2b_usd_addr = { - .bar2_addr64 = SNB_B2B_BAR2_USD_ADDR64, - .bar4_addr64 = SNB_B2B_BAR4_USD_ADDR64, - .bar4_addr32 = SNB_B2B_BAR4_USD_ADDR32, - .bar5_addr32 = SNB_B2B_BAR5_USD_ADDR32, +static struct intel_b2b_addr xeon_b2b_usd_addr = { + .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64, + .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64, + .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32, + .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32, }; -static struct intel_b2b_addr snb_b2b_dsd_addr = { - .bar2_addr64 = SNB_B2B_BAR2_DSD_ADDR64, - .bar4_addr64 = SNB_B2B_BAR4_DSD_ADDR64, - .bar4_addr32 = SNB_B2B_BAR4_DSD_ADDR32, - .bar5_addr32 = SNB_B2B_BAR5_DSD_ADDR32, +static struct intel_b2b_addr xeon_b2b_dsd_addr = { + .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64, + .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64, + .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32, + .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32, }; /* operations for primary side of local ntb */ diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h index fec689dc95cf..7ddaf387b679 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.h +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h @@ -68,141 +68,141 @@ #define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F #define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E -/* SNB hardware (and JSF, IVT, HSX) */ - -#define SNB_PBAR23LMT_OFFSET 0x0000 -#define SNB_PBAR45LMT_OFFSET 0x0008 -#define SNB_PBAR4LMT_OFFSET 0x0008 -#define SNB_PBAR5LMT_OFFSET 0x000c -#define SNB_PBAR23XLAT_OFFSET 0x0010 -#define SNB_PBAR45XLAT_OFFSET 0x0018 -#define SNB_PBAR4XLAT_OFFSET 0x0018 -#define SNB_PBAR5XLAT_OFFSET 0x001c -#define SNB_SBAR23LMT_OFFSET 0x0020 -#define SNB_SBAR45LMT_OFFSET 0x0028 -#define SNB_SBAR4LMT_OFFSET 0x0028 -#define SNB_SBAR5LMT_OFFSET 0x002c -#define SNB_SBAR23XLAT_OFFSET 0x0030 -#define SNB_SBAR45XLAT_OFFSET 0x0038 -#define SNB_SBAR4XLAT_OFFSET 0x0038 -#define SNB_SBAR5XLAT_OFFSET 0x003c -#define SNB_SBAR0BASE_OFFSET 0x0040 -#define SNB_SBAR23BASE_OFFSET 0x0048 -#define SNB_SBAR45BASE_OFFSET 0x0050 -#define SNB_SBAR4BASE_OFFSET 0x0050 -#define SNB_SBAR5BASE_OFFSET 0x0054 -#define SNB_SBDF_OFFSET 0x005c -#define SNB_NTBCNTL_OFFSET 0x0058 -#define SNB_PDOORBELL_OFFSET 0x0060 -#define SNB_PDBMSK_OFFSET 0x0062 -#define SNB_SDOORBELL_OFFSET 0x0064 -#define SNB_SDBMSK_OFFSET 0x0066 -#define SNB_USMEMMISS_OFFSET 0x0070 -#define SNB_SPAD_OFFSET 0x0080 -#define SNB_PBAR23SZ_OFFSET 0x00d0 -#define SNB_PBAR45SZ_OFFSET 0x00d1 -#define SNB_PBAR4SZ_OFFSET 0x00d1 -#define SNB_SBAR23SZ_OFFSET 0x00d2 -#define SNB_SBAR45SZ_OFFSET 0x00d3 -#define SNB_SBAR4SZ_OFFSET 0x00d3 -#define SNB_PPD_OFFSET 0x00d4 -#define SNB_PBAR5SZ_OFFSET 0x00d5 -#define SNB_SBAR5SZ_OFFSET 0x00d6 -#define SNB_WCCNTRL_OFFSET 0x00e0 -#define SNB_UNCERRSTS_OFFSET 0x014c -#define SNB_CORERRSTS_OFFSET 0x0158 -#define SNB_LINK_STATUS_OFFSET 0x01a2 -#define SNB_SPCICMD_OFFSET 0x0504 -#define SNB_DEVCTRL_OFFSET 0x0598 -#define SNB_DEVSTS_OFFSET 0x059a -#define SNB_SLINK_STATUS_OFFSET 0x05a2 -#define SNB_B2B_SPAD_OFFSET 0x0100 -#define SNB_B2B_DOORBELL_OFFSET 0x0140 -#define SNB_B2B_XLAT_OFFSETL 0x0144 -#define SNB_B2B_XLAT_OFFSETU 0x0148 -#define SNB_PPD_CONN_MASK 0x03 -#define SNB_PPD_CONN_TRANSPARENT 0x00 -#define SNB_PPD_CONN_B2B 0x01 -#define SNB_PPD_CONN_RP 0x02 -#define SNB_PPD_DEV_MASK 0x10 -#define SNB_PPD_DEV_USD 0x00 -#define SNB_PPD_DEV_DSD 0x10 -#define SNB_PPD_SPLIT_BAR_MASK 0x40 - -#define SNB_PPD_TOPO_MASK (SNB_PPD_CONN_MASK | SNB_PPD_DEV_MASK) -#define SNB_PPD_TOPO_PRI_USD (SNB_PPD_CONN_RP | SNB_PPD_DEV_USD) -#define SNB_PPD_TOPO_PRI_DSD (SNB_PPD_CONN_RP | SNB_PPD_DEV_DSD) -#define SNB_PPD_TOPO_SEC_USD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_USD) -#define SNB_PPD_TOPO_SEC_DSD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_DSD) -#define SNB_PPD_TOPO_B2B_USD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_USD) -#define SNB_PPD_TOPO_B2B_DSD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_DSD) - -#define SNB_MW_COUNT 2 +/* Intel Xeon hardware */ + +#define XEON_PBAR23LMT_OFFSET 0x0000 +#define XEON_PBAR45LMT_OFFSET 0x0008 +#define XEON_PBAR4LMT_OFFSET 0x0008 +#define XEON_PBAR5LMT_OFFSET 0x000c +#define XEON_PBAR23XLAT_OFFSET 0x0010 +#define XEON_PBAR45XLAT_OFFSET 0x0018 +#define XEON_PBAR4XLAT_OFFSET 0x0018 +#define XEON_PBAR5XLAT_OFFSET 0x001c +#define XEON_SBAR23LMT_OFFSET 0x0020 +#define XEON_SBAR45LMT_OFFSET 0x0028 +#define XEON_SBAR4LMT_OFFSET 0x0028 +#define XEON_SBAR5LMT_OFFSET 0x002c +#define XEON_SBAR23XLAT_OFFSET 0x0030 +#define XEON_SBAR45XLAT_OFFSET 0x0038 +#define XEON_SBAR4XLAT_OFFSET 0x0038 +#define XEON_SBAR5XLAT_OFFSET 0x003c +#define XEON_SBAR0BASE_OFFSET 0x0040 +#define XEON_SBAR23BASE_OFFSET 0x0048 +#define XEON_SBAR45BASE_OFFSET 0x0050 +#define XEON_SBAR4BASE_OFFSET 0x0050 +#define XEON_SBAR5BASE_OFFSET 0x0054 +#define XEON_SBDF_OFFSET 0x005c +#define XEON_NTBCNTL_OFFSET 0x0058 +#define XEON_PDOORBELL_OFFSET 0x0060 +#define XEON_PDBMSK_OFFSET 0x0062 +#define XEON_SDOORBELL_OFFSET 0x0064 +#define XEON_SDBMSK_OFFSET 0x0066 +#define XEON_USMEMMISS_OFFSET 0x0070 +#define XEON_SPAD_OFFSET 0x0080 +#define XEON_PBAR23SZ_OFFSET 0x00d0 +#define XEON_PBAR45SZ_OFFSET 0x00d1 +#define XEON_PBAR4SZ_OFFSET 0x00d1 +#define XEON_SBAR23SZ_OFFSET 0x00d2 +#define XEON_SBAR45SZ_OFFSET 0x00d3 +#define XEON_SBAR4SZ_OFFSET 0x00d3 +#define XEON_PPD_OFFSET 0x00d4 +#define XEON_PBAR5SZ_OFFSET 0x00d5 +#define XEON_SBAR5SZ_OFFSET 0x00d6 +#define XEON_WCCNTRL_OFFSET 0x00e0 +#define XEON_UNCERRSTS_OFFSET 0x014c +#define XEON_CORERRSTS_OFFSET 0x0158 +#define XEON_LINK_STATUS_OFFSET 0x01a2 +#define XEON_SPCICMD_OFFSET 0x0504 +#define XEON_DEVCTRL_OFFSET 0x0598 +#define XEON_DEVSTS_OFFSET 0x059a +#define XEON_SLINK_STATUS_OFFSET 0x05a2 +#define XEON_B2B_SPAD_OFFSET 0x0100 +#define XEON_B2B_DOORBELL_OFFSET 0x0140 +#define XEON_B2B_XLAT_OFFSETL 0x0144 +#define XEON_B2B_XLAT_OFFSETU 0x0148 +#define XEON_PPD_CONN_MASK 0x03 +#define XEON_PPD_CONN_TRANSPARENT 0x00 +#define XEON_PPD_CONN_B2B 0x01 +#define XEON_PPD_CONN_RP 0x02 +#define XEON_PPD_DEV_MASK 0x10 +#define XEON_PPD_DEV_USD 0x00 +#define XEON_PPD_DEV_DSD 0x10 +#define XEON_PPD_SPLIT_BAR_MASK 0x40 + +#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK) +#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD) +#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD) +#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD) +#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD) +#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD) +#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD) + +#define XEON_MW_COUNT 2 #define HSX_SPLIT_BAR_MW_COUNT 3 -#define SNB_DB_COUNT 15 -#define SNB_DB_LINK 15 -#define SNB_DB_LINK_BIT BIT_ULL(SNB_DB_LINK) -#define SNB_DB_MSIX_VECTOR_COUNT 4 -#define SNB_DB_MSIX_VECTOR_SHIFT 5 -#define SNB_DB_TOTAL_SHIFT 16 -#define SNB_SPAD_COUNT 16 - -/* BWD hardware */ - -#define BWD_SBAR2XLAT_OFFSET 0x0008 -#define BWD_PDOORBELL_OFFSET 0x0020 -#define BWD_PDBMSK_OFFSET 0x0028 -#define BWD_NTBCNTL_OFFSET 0x0060 -#define BWD_SPAD_OFFSET 0x0080 -#define BWD_PPD_OFFSET 0x00d4 -#define BWD_PBAR2XLAT_OFFSET 0x8008 -#define BWD_B2B_DOORBELL_OFFSET 0x8020 -#define BWD_B2B_SPAD_OFFSET 0x8080 -#define BWD_SPCICMD_OFFSET 0xb004 -#define BWD_LINK_STATUS_OFFSET 0xb052 -#define BWD_ERRCORSTS_OFFSET 0xb110 -#define BWD_IP_BASE 0xc000 -#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024) -#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180) -#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040) -#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324) -#define BWD_MODPHY_PCSREG4 0x1c004 -#define BWD_MODPHY_PCSREG6 0x1c006 - -#define BWD_PPD_INIT_LINK 0x0008 -#define BWD_PPD_CONN_MASK 0x0300 -#define BWD_PPD_CONN_TRANSPARENT 0x0000 -#define BWD_PPD_CONN_B2B 0x0100 -#define BWD_PPD_CONN_RP 0x0200 -#define BWD_PPD_DEV_MASK 0x1000 -#define BWD_PPD_DEV_USD 0x0000 -#define BWD_PPD_DEV_DSD 0x1000 -#define BWD_PPD_TOPO_MASK (BWD_PPD_CONN_MASK | BWD_PPD_DEV_MASK) -#define BWD_PPD_TOPO_PRI_USD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_USD) -#define BWD_PPD_TOPO_PRI_DSD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_DSD) -#define BWD_PPD_TOPO_SEC_USD (BWD_PPD_CONN_RP | BWD_PPD_DEV_USD) -#define BWD_PPD_TOPO_SEC_DSD (BWD_PPD_CONN_RP | BWD_PPD_DEV_DSD) -#define BWD_PPD_TOPO_B2B_USD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_USD) -#define BWD_PPD_TOPO_B2B_DSD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_DSD) - -#define BWD_MW_COUNT 2 -#define BWD_DB_COUNT 34 -#define BWD_DB_VALID_MASK (BIT_ULL(BWD_DB_COUNT) - 1) -#define BWD_DB_MSIX_VECTOR_COUNT 34 -#define BWD_DB_MSIX_VECTOR_SHIFT 1 -#define BWD_DB_TOTAL_SHIFT 34 -#define BWD_SPAD_COUNT 16 - -#define BWD_NTB_CTL_DOWN_BIT BIT(16) -#define BWD_NTB_CTL_ACTIVE(x) !(x & BWD_NTB_CTL_DOWN_BIT) - -#define BWD_DESKEWSTS_DBERR BIT(15) -#define BWD_LTSSMERRSTS0_UNEXPECTEDEI BIT(20) -#define BWD_LTSSMSTATEJMP_FORCEDETECT BIT(2) -#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF - -#define BWD_LINK_HB_TIMEOUT msecs_to_jiffies(1000) -#define BWD_LINK_RECOVERY_TIME msecs_to_jiffies(500) +#define XEON_DB_COUNT 15 +#define XEON_DB_LINK 15 +#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK) +#define XEON_DB_MSIX_VECTOR_COUNT 4 +#define XEON_DB_MSIX_VECTOR_SHIFT 5 +#define XEON_DB_TOTAL_SHIFT 16 +#define XEON_SPAD_COUNT 16 + +/* Intel Atom hardware */ + +#define ATOM_SBAR2XLAT_OFFSET 0x0008 +#define ATOM_PDOORBELL_OFFSET 0x0020 +#define ATOM_PDBMSK_OFFSET 0x0028 +#define ATOM_NTBCNTL_OFFSET 0x0060 +#define ATOM_SPAD_OFFSET 0x0080 +#define ATOM_PPD_OFFSET 0x00d4 +#define ATOM_PBAR2XLAT_OFFSET 0x8008 +#define ATOM_B2B_DOORBELL_OFFSET 0x8020 +#define ATOM_B2B_SPAD_OFFSET 0x8080 +#define ATOM_SPCICMD_OFFSET 0xb004 +#define ATOM_LINK_STATUS_OFFSET 0xb052 +#define ATOM_ERRCORSTS_OFFSET 0xb110 +#define ATOM_IP_BASE 0xc000 +#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024) +#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180) +#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040) +#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324) +#define ATOM_MODPHY_PCSREG4 0x1c004 +#define ATOM_MODPHY_PCSREG6 0x1c006 + +#define ATOM_PPD_INIT_LINK 0x0008 +#define ATOM_PPD_CONN_MASK 0x0300 +#define ATOM_PPD_CONN_TRANSPARENT 0x0000 +#define ATOM_PPD_CONN_B2B 0x0100 +#define ATOM_PPD_CONN_RP 0x0200 +#define ATOM_PPD_DEV_MASK 0x1000 +#define ATOM_PPD_DEV_USD 0x0000 +#define ATOM_PPD_DEV_DSD 0x1000 +#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK) +#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD) +#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD) +#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD) +#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD) +#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD) +#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD) + +#define ATOM_MW_COUNT 2 +#define ATOM_DB_COUNT 34 +#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1) +#define ATOM_DB_MSIX_VECTOR_COUNT 34 +#define ATOM_DB_MSIX_VECTOR_SHIFT 1 +#define ATOM_DB_TOTAL_SHIFT 34 +#define ATOM_SPAD_COUNT 16 + +#define ATOM_NTB_CTL_DOWN_BIT BIT(16) +#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT) + +#define ATOM_DESKEWSTS_DBERR BIT(15) +#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20) +#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2) +#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF + +#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000) +#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500) /* Ntb control and link status */ @@ -224,19 +224,19 @@ /* Use the following addresses for translation between b2b ntb devices in case * the hardware default values are not reliable. */ -#define SNB_B2B_BAR0_USD_ADDR 0x1000000000000000ull -#define SNB_B2B_BAR2_USD_ADDR64 0x2000000000000000ull -#define SNB_B2B_BAR4_USD_ADDR64 0x4000000000000000ull -#define SNB_B2B_BAR4_USD_ADDR32 0x20000000u -#define SNB_B2B_BAR5_USD_ADDR32 0x40000000u -#define SNB_B2B_BAR0_DSD_ADDR 0x9000000000000000ull -#define SNB_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull -#define SNB_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull -#define SNB_B2B_BAR4_DSD_ADDR32 0xa0000000u -#define SNB_B2B_BAR5_DSD_ADDR32 0xc0000000u +#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull +#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull +#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull +#define XEON_B2B_BAR4_USD_ADDR32 0x20000000u +#define XEON_B2B_BAR5_USD_ADDR32 0x40000000u +#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull +#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull +#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull +#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000u +#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000u /* The peer ntb secondary config space is 32KB fixed size */ -#define SNB_B2B_MIN_SIZE 0x8000 +#define XEON_B2B_MIN_SIZE 0x8000 /* flags to indicate hardware errata */ #define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0) -- cgit v1.2.3 From 44f4c054cae646a9296da05cdfe7d6e786f73d46 Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Fri, 3 Jul 2015 10:40:38 -0400 Subject: dax: Add block size note to documentation For block devices which are small enough, mkfs will default to creating a filesystem with block sizes smaller than page size. Signed-off-by: Matthew Wilcox Signed-off-by: Al Viro --- Documentation/filesystems/dax.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/filesystems/dax.txt b/Documentation/filesystems/dax.txt index baf41118660d..7af2851d667c 100644 --- a/Documentation/filesystems/dax.txt +++ b/Documentation/filesystems/dax.txt @@ -18,8 +18,10 @@ Usage ----- If you have a block device which supports DAX, you can make a filesystem -on it as usual. When mounting it, use the -o dax option manually -or add 'dax' to the options in /etc/fstab. +on it as usual. The DAX code currently only supports files with a block +size equal to your kernel's PAGE_SIZE, so you may need to specify a block +size when creating the filesystem. When mounting it, use the "-o dax" +option on the command line or add 'dax' to the options in /etc/fstab. Implementation Tips for Block Driver Writers -- cgit v1.2.3 From d90a45b1e005da3351de795d2ba6d52dc5a28837 Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Fri, 15 May 2015 18:38:51 +0200 Subject: Documentation: sunxi: Update Allwinner SoC documentation There are some new Allwinner SoCs available, namely A33, A83T and H3. Update the documentation to mention those and the related documents. Signed-off-by: Jens Kuske Signed-off-by: Maxime Ripard --- Documentation/arm/sunxi/README | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index 1fe2d7fd4108..5e38e1582f95 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -36,7 +36,7 @@ SunXi family + User Manual http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf - - Allwinner A23 + - Allwinner A23 (sun8i) + Datasheet http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf + User Manual @@ -55,7 +55,23 @@ SunXi family + User Manual http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf + - Allwinner A33 (sun8i) + + Datasheet + http://dl.linux-sunxi.org/A33/A33%20Datasheet%20release%201.1.pdf + + User Manual + http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf + + - Allwinner H3 (sun8i) + + Datasheet + http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf + * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 + Datasheet http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf + + * Octa ARM Cortex-A7 based SoCs + - Allwinner A83T + + Not Supported + + Datasheet + http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf -- cgit v1.2.3 From 14a882df14a5ae859b245bc708ce3fce47a91594 Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Fri, 15 May 2015 18:38:55 +0200 Subject: ARM: sunxi: Introduce Allwinner H3 support The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar to other sun8i family SoCs like the A23. Signed-off-by: Jens Kuske Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/sunxi.c | 4 +++- 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index 42941fdefb11..3cb4b946ff2b 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -9,4 +9,5 @@ using one of the following compatible strings: allwinner,sun6i-a31 allwinner,sun7i-a20 allwinner,sun8i-a23 + allwinner,sun8i-h3 allwinner,sun9i-a80 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 81502b90dd91..4efe2d43a126 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -35,7 +35,7 @@ config MACH_SUN7I select SUN5I_HSTIMER config MACH_SUN8I - bool "Allwinner A23 (sun8i) SoCs support" + bool "Allwinner sun8i Family SoCs support" default ARCH_SUNXI select ARM_GIC select MFD_SUN6I_PRCM diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 1bc811a74a9f..82709020c57c 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -67,10 +67,12 @@ MACHINE_END static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a23", + "allwinner,sun8i-h3", NULL, }; -DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family") +DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family") + .init_time = sun6i_timer_init, .dt_compat = sun8i_board_dt_compat, .init_late = sunxi_dt_cpufreq_init, MACHINE_END -- cgit v1.2.3 From 159870d2413c92622790e9cecbce95099bed539a Mon Sep 17 00:00:00 2001 From: Vishnu Patekar Date: Sat, 30 May 2015 16:55:01 +0200 Subject: ARM: sunxi: Add Machine support for A33 Add machine support for the Allwinner A33 quad core cortex-a7 based SoC, which is similar to the A23 SoC. Signed-off-by: Vishnu Patekar Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Tested-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/sunxi.c | 1 + drivers/clk/sunxi/clk-sunxi.c | 1 + 3 files changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index 3cb4b946ff2b..67da20539540 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -9,5 +9,6 @@ using one of the following compatible strings: allwinner,sun6i-a31 allwinner,sun7i-a20 allwinner,sun8i-a23 + allwinner,sun8i-a33 allwinner,sun8i-h3 allwinner,sun9i-a80 diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 82709020c57c..65bab2876343 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -67,6 +67,7 @@ MACHINE_END static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a23", + "allwinner,sun8i-a33", "allwinner,sun8i-h3", NULL, }; diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 7e1e2bd189b6..6d25e4e9dfec 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -1389,6 +1389,7 @@ static void __init sun6i_init_clocks(struct device_node *node) CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks); CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks); +CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks); static void __init sun9i_init_clocks(struct device_node *node) { -- cgit v1.2.3 From fff75ee150104fdc29d86a75a5511482a981c27b Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 6 May 2015 12:25:33 -0500 Subject: ARM: dts: am4372: Add emif node Add node for TI AM4372 EMIF. Without this we get a warning with the recent commit fabbe6df (ARM: OMAP: AM43xx hwmod: Add data for am43xx emif hwmod). Signed-off-by: Dave Gerlach Tested-by: Felipe Balbi Acked-by: Felipe Balbi [tony@atomide.com: updated comments] Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/memory-controllers/ti/emif.txt | 1 + arch/arm/boot/dts/am4372.dtsi | 6 ++++++ 2 files changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 938f8e1ba205..0db60470ebb6 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -8,6 +8,7 @@ of the EMIF IP and memory parts attached to it. Required properties: - compatible : Should be of the form "ti,emif-" where is the IP revision of the specific EMIF instance. + For am437x should be ti,emif-am4372. - phy-type : indicating the DDR phy type. Following are the allowed values diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index c80a3e233792..9521a3827021 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -132,6 +132,12 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am4372"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + edma: edma@49000000 { compatible = "ti,edma3"; ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; -- cgit v1.2.3 From b51f9b103f58db2c5c0a20d6cee26c8bc255d3ae Mon Sep 17 00:00:00 2001 From: Uwe Geuder Date: Mon, 29 Jun 2015 23:35:05 +0300 Subject: PM / hibernate: clarify resume documentation it was not the whole truth that kernel mode cannot be used with swap on LVM Signed-off-by: Uwe Geuder Acked-by: Pavel Machek Signed-off-by: Rafael J. Wysocki --- Documentation/power/swsusp.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/power/swsusp.txt b/Documentation/power/swsusp.txt index f732a8321e8a..8cc17ca71813 100644 --- a/Documentation/power/swsusp.txt +++ b/Documentation/power/swsusp.txt @@ -410,8 +410,17 @@ Documentation/usb/persist.txt. Q: Can I suspend-to-disk using a swap partition under LVM? -A: No. You can suspend successfully, but you'll not be able to -resume. uswsusp should be able to work with LVM. See suspend.sf.net. +A: Yes and No. You can suspend successfully, but the kernel will not be able +to resume on its own. You need an initramfs that can recognize the resume +situation, activate the logical volume containing the swap volume (but not +touch any filesystems!), and eventually call + +echo -n "$major:$minor" > /sys/power/resume + +where $major and $minor are the respective major and minor device numbers of +the swap volume. + +uswsusp works with LVM, too. See http://suspend.sourceforge.net/ Q: I upgraded the kernel from 2.6.15 to 2.6.16. Both kernels were compiled with the similar configuration files. Anyway I found that -- cgit v1.2.3