From dc8ea9204b242cd93e63585396ac7d13f622802d Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 30 Mar 2023 18:32:56 +0100 Subject: dt-bindings: move cache controller bindings to a cache directory There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/l2c2x0.yaml | 242 --------------------- .../devicetree/bindings/arm/mrvl/feroceon.txt | 16 -- .../devicetree/bindings/arm/mrvl/tauros2.txt | 17 -- .../devicetree/bindings/arm/msm/qcom,llcc.yaml | 65 ------ .../socionext/socionext,uniphier-system-cache.yaml | 101 --------- .../bindings/cache/baikal,bt1-l2-ctl.yaml | 63 ++++++ .../bindings/cache/freescale-l2cache.txt | 55 +++++ .../devicetree/bindings/cache/l2c2x0.yaml | 242 +++++++++++++++++++++ .../bindings/cache/marvell,feroceon-cache.txt | 16 ++ .../bindings/cache/marvell,tauros2-cache.txt | 17 ++ .../devicetree/bindings/cache/qcom,llcc.yaml | 65 ++++++ .../devicetree/bindings/cache/sifive,ccache0.yaml | 170 +++++++++++++++ .../cache/socionext,uniphier-system-cache.yaml | 101 +++++++++ .../memory-controllers/baikal,bt1-l2-ctl.yaml | 63 ------ .../devicetree/bindings/powerpc/fsl/l2cache.txt | 55 ----- .../devicetree/bindings/riscv/sifive,ccache0.yaml | 170 --------------- 16 files changed, 729 insertions(+), 729 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.yaml delete mode 100644 Documentation/devicetree/bindings/arm/mrvl/feroceon.txt delete mode 100644 Documentation/devicetree/bindings/arm/mrvl/tauros2.txt delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml delete mode 100644 Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml create mode 100644 Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml create mode 100644 Documentation/devicetree/bindings/cache/freescale-l2cache.txt create mode 100644 Documentation/devicetree/bindings/cache/l2c2x0.yaml create mode 100644 Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt create mode 100644 Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt create mode 100644 Documentation/devicetree/bindings/cache/qcom,llcc.yaml create mode 100644 Documentation/devicetree/bindings/cache/sifive,ccache0.yaml create mode 100644 Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt delete mode 100644 Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml deleted file mode 100644 index 6b8f4d4fa580..000000000000 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ /dev/null @@ -1,242 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/l2c2x0.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: ARM L2 Cache Controller - -maintainers: - - Rob Herring - -description: |+ - ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ - PL220/PL310 and variants) based level 2 cache controller. All these various - implementations of the L2 cache controller have compatible programming - models (Note 1). Some of the properties that are just prefixed "cache-*" are - taken from section 3.7.3 of the Devicetree Specification which can be found - at: - https://www.devicetree.org/specifications/ - - Note 1: The description in this document doesn't apply to integrated L2 - cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These - integrated L2 controllers are assumed to be all preconfigured by - early secure boot code. Thus no need to deal with their configuration - in the kernel at all. - -allOf: - - $ref: /schemas/cache-controller.yaml# - -properties: - compatible: - oneOf: - - enum: - - arm,pl310-cache - - arm,l220-cache - - arm,l210-cache - # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" - - bcm,bcm11351-a2-pl310-cache - # For Broadcom bcm11351 chipset where an - # offset needs to be added to the address before passing down to the L2 - # cache controller - - brcm,bcm11351-a2-pl310-cache - # Marvell Controller designed to be - # compatible with the ARM one, with system cache mode (meaning - # maintenance operations on L1 are broadcasted to the L2 and L2 - # performs the same operation). - - marvell,aurora-system-cache - # Marvell Controller designed to be - # compatible with the ARM one with outer cache mode. - - marvell,aurora-outer-cache - - items: - # Marvell Tauros3 cache controller, compatible - # with arm,pl310-cache controller. - - const: marvell,tauros3-cache - - const: arm,pl310-cache - - cache-level: - const: 2 - - cache-unified: true - cache-size: true - cache-sets: true - cache-block-size: true - cache-line-size: true - - reg: - maxItems: 1 - - arm,data-latency: - description: Cycles of latency for Data RAM accesses. Specifies 3 cells of - read, write and setup latencies. Minimum valid values are 1. Controllers - without setup latency control should use a value of 0. - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 2 - maxItems: 3 - items: - minimum: 0 - maximum: 8 - - arm,tag-latency: - description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of - read, write and setup latencies. Controllers without setup latency control - should use 0. Controllers without separate read and write Tag RAM latency - values should only use the first cell. - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 3 - items: - minimum: 0 - maximum: 8 - - arm,dirty-latency: - description: Cycles of latency for Dirty RAMs. This is a single cell. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - maximum: 8 - - arm,filter-ranges: - description: Starting address and length of window to - filter. Addresses in the filter window are directed to the M1 port. Other - addresses will go to the M0 port. - $ref: /schemas/types.yaml#/definitions/uint32-array - items: - minItems: 2 - maxItems: 2 - - arm,io-coherent: - description: indicates that the system is operating in an hardware - I/O coherent mode. Valid only when the arm,pl310-cache compatible - string is used. - type: boolean - - interrupts: - # Either a single combined interrupt or up to 9 individual interrupts - minItems: 1 - maxItems: 9 - - cache-id-part: - description: cache id part number to be used if it is not present - on hardware - $ref: /schemas/types.yaml#/definitions/uint32 - - wt-override: - description: If present then L2 is forced to Write through mode - type: boolean - - arm,double-linefill: - description: Override double linefill enable setting. Enable if - non-zero, disable if zero. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,double-linefill-incr: - description: Override double linefill on INCR read. Enable - if non-zero, disable if zero. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,double-linefill-wrap: - description: Override double linefill on WRAP read. Enable - if non-zero, disable if zero. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,prefetch-drop: - description: Override prefetch drop enable setting. Enable if non-zero, - disable if zero. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,prefetch-offset: - description: Override prefetch offset value. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] - - arm,shared-override: - description: The default behavior of the L220 or PL310 cache - controllers with respect to the shareable attribute is to transform "normal - memory non-cacheable transactions" into "cacheable no allocate" (for reads) - or "write through no write allocate" (for writes). - On systems where this may cause DMA buffer corruption, this property must - be specified to indicate that such transforms are precluded. - type: boolean - - arm,parity-enable: - description: enable parity checking on the L2 cache (L220 or PL310). - type: boolean - - arm,parity-disable: - description: disable parity checking on the L2 cache (L220 or PL310). - type: boolean - - marvell,ecc-enable: - description: enable ECC protection on the L2 cache - type: boolean - - arm,outer-sync-disable: - description: disable the outer sync operation on the L2 cache. - Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that - will randomly hang unless outer sync operations are disabled. - type: boolean - - prefetch-data: - description: | - Data prefetch. Value: <0> (forcibly disable), <1> - (forcibly enable), property absent (retain settings set by firmware) - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - prefetch-instr: - description: | - Instruction prefetch. Value: <0> (forcibly disable), - <1> (forcibly enable), property absent (retain settings set by - firmware) - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,dynamic-clock-gating: - description: | - L2 dynamic clock gating. Value: <0> (forcibly - disable), <1> (forcibly enable), property absent (OS specific behavior, - preferably retain firmware settings) - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,standby-mode: - description: L2 standby mode enable. Value <0> (forcibly disable), - <1> (forcibly enable), property absent (OS specific behavior, - preferably retain firmware settings) - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - arm,early-bresp-disable: - description: Disable the CA9 optimization Early BRESP (PL310) - type: boolean - - arm,full-line-zero-disable: - description: Disable the CA9 optimization Full line of zero - write (PL310) - type: boolean - -required: - - compatible - - cache-unified - - reg - -additionalProperties: false - -examples: - - | - cache-controller@fff12000 { - compatible = "arm,pl310-cache"; - reg = <0xfff12000 0x1000>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <2 2 2>; - arm,filter-ranges = <0x80000000 0x8000000>; - cache-unified; - cache-level = <2>; - interrupts = <45>; - }; - -... diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt deleted file mode 100644 index 0d244b999d10..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell Feroceon Cache - -Required properties: -- compatible : Should be either "marvell,feroceon-cache" or - "marvell,kirkwood-cache". - -Optional properties: -- reg : Address of the L2 cache control register. Mandatory for - "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" - - -Example: - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt deleted file mode 100644 index 31af1cbb60bd..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Marvell Tauros2 Cache - -Required properties: -- compatible : Should be "marvell,tauros2-cache". -- marvell,tauros2-cache-features : Specify the features supported for the - tauros2 cache. - The features including - CACHE_TAUROS2_PREFETCH_ON (1 << 0) - CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) - The definition can be found at - arch/arm/include/asm/hardware/cache-tauros2.h - -Example: - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml deleted file mode 100644 index 38efcad56dbd..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ /dev/null @@ -1,65 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Last Level Cache Controller - -maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan - -description: | - LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, - that can be shared by multiple clients. Clients here are different cores in the - SoC, the idea is to minimize the local caches at the clients and migrate to - common pool of memory. Cache memory is divided into partitions called slices - which are assigned to clients. Clients can query the slice details, activate - and deactivate them. - -properties: - compatible: - enum: - - qcom,sc7180-llcc - - qcom,sc7280-llcc - - qcom,sc8180x-llcc - - qcom,sc8280xp-llcc - - qcom,sdm845-llcc - - qcom,sm6350-llcc - - qcom,sm8150-llcc - - qcom,sm8250-llcc - - qcom,sm8350-llcc - - qcom,sm8450-llcc - - qcom,sm8550-llcc - - reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region - - reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base - - interrupts: - maxItems: 1 - -required: - - compatible - - reg - - reg-names - -additionalProperties: false - -examples: - - | - #include - - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml deleted file mode 100644 index 6096c082d56d..000000000000 --- a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml +++ /dev/null @@ -1,101 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: UniPhier outer cache controller - -description: | - UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache - controller system. All of them have a level 2 cache controller, and some - have a level 3 cache controller as well. - -maintainers: - - Masahiro Yamada - -properties: - compatible: - const: socionext,uniphier-system-cache - - reg: - description: | - should contain 3 regions: control register, revision register, - operation register, in this order. - maxItems: 3 - - interrupts: - description: | - Interrupts can be used to notify the completion of cache operations. - The number of interrupts should match to the number of CPU cores. - The specified interrupts correspond to CPU0, CPU1, ... in this order. - minItems: 1 - maxItems: 4 - - cache-unified: true - - cache-size: true - - cache-sets: true - - cache-line-size: true - - cache-level: - minimum: 2 - maximum: 3 - - next-level-cache: true - -allOf: - - $ref: /schemas/cache-controller.yaml# - -additionalProperties: false - -required: - - compatible - - reg - - interrupts - - cache-unified - - cache-size - - cache-sets - - cache-line-size - - cache-level - -examples: - - | - // System with L2. - cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <0x140000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - | - // System with L2 and L3. - // L2 should specify the next level cache by 'next-level-cache'. - l2: cache-controller@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: cache-controller@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; diff --git a/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml new file mode 100644 index 000000000000..ec4f367bc0b4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 L2-cache Control Block + +maintainers: + - Serge Semin + +description: | + By means of the System Controller Baikal-T1 SoC exposes a few settings to + tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible + to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 + L2-cache controller block is responsible for the tuning. Its DT node is + supposed to be a child of the system controller. + +properties: + compatible: + const: baikal,bt1-l2-ctl + + reg: + maxItems: 1 + + baikal,l2-ws-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Way-select RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-tag-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Tag RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-data-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Data RAM accesses + default: 1 + minimum: 0 + maximum: 3 + +additionalProperties: false + +required: + - compatible + +examples: + - | + l2@1f04d028 { + compatible = "baikal,bt1-l2-ctl"; + reg = <0x1f04d028 0x004>; + + baikal,l2-ws-latency = <1>; + baikal,l2-tag-latency = <1>; + baikal,l2-data-latency = <2>; + }; +... diff --git a/Documentation/devicetree/bindings/cache/freescale-l2cache.txt b/Documentation/devicetree/bindings/cache/freescale-l2cache.txt new file mode 100644 index 000000000000..22ad012660e9 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/freescale-l2cache.txt @@ -0,0 +1,55 @@ +Freescale L2 Cache Controller + +L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. +The cache bindings explained below are Devicetree Specification compliant + +Required Properties: + +- compatible : Should include one of the following: + "fsl,b4420-l2-cache-controller" + "fsl,b4860-l2-cache-controller" + "fsl,bsc9131-l2-cache-controller" + "fsl,bsc9132-l2-cache-controller" + "fsl,c293-l2-cache-controller" + "fsl,mpc8536-l2-cache-controller" + "fsl,mpc8540-l2-cache-controller" + "fsl,mpc8541-l2-cache-controller" + "fsl,mpc8544-l2-cache-controller" + "fsl,mpc8548-l2-cache-controller" + "fsl,mpc8555-l2-cache-controller" + "fsl,mpc8560-l2-cache-controller" + "fsl,mpc8568-l2-cache-controller" + "fsl,mpc8569-l2-cache-controller" + "fsl,mpc8572-l2-cache-controller" + "fsl,p1010-l2-cache-controller" + "fsl,p1011-l2-cache-controller" + "fsl,p1012-l2-cache-controller" + "fsl,p1013-l2-cache-controller" + "fsl,p1014-l2-cache-controller" + "fsl,p1015-l2-cache-controller" + "fsl,p1016-l2-cache-controller" + "fsl,p1020-l2-cache-controller" + "fsl,p1021-l2-cache-controller" + "fsl,p1022-l2-cache-controller" + "fsl,p1023-l2-cache-controller" + "fsl,p1024-l2-cache-controller" + "fsl,p1025-l2-cache-controller" + "fsl,p2010-l2-cache-controller" + "fsl,p2020-l2-cache-controller" + "fsl,t2080-l2-cache-controller" + "fsl,t4240-l2-cache-controller" + and "cache". +- reg : Address and size of L2 cache controller registers +- cache-size : Size of the entire L2 cache +- interrupts : Error interrupt of L2 controller +- cache-line-size : Size of L2 cache lines + +Example: + + L2: l2-cache-controller@20000 { + compatible = "fsl,bsc9132-l2-cache-controller", "cache"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2,256K + interrupts = <16 2 1 0>; + }; diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml new file mode 100644 index 000000000000..d7840a5c4037 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/l2c2x0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM L2 Cache Controller + +maintainers: + - Rob Herring + +description: |+ + ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ + PL220/PL310 and variants) based level 2 cache controller. All these various + implementations of the L2 cache controller have compatible programming + models (Note 1). Some of the properties that are just prefixed "cache-*" are + taken from section 3.7.3 of the Devicetree Specification which can be found + at: + https://www.devicetree.org/specifications/ + + Note 1: The description in this document doesn't apply to integrated L2 + cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These + integrated L2 controllers are assumed to be all preconfigured by + early secure boot code. Thus no need to deal with their configuration + in the kernel at all. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - arm,pl310-cache + - arm,l220-cache + - arm,l210-cache + # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + - bcm,bcm11351-a2-pl310-cache + # For Broadcom bcm11351 chipset where an + # offset needs to be added to the address before passing down to the L2 + # cache controller + - brcm,bcm11351-a2-pl310-cache + # Marvell Controller designed to be + # compatible with the ARM one, with system cache mode (meaning + # maintenance operations on L1 are broadcasted to the L2 and L2 + # performs the same operation). + - marvell,aurora-system-cache + # Marvell Controller designed to be + # compatible with the ARM one with outer cache mode. + - marvell,aurora-outer-cache + - items: + # Marvell Tauros3 cache controller, compatible + # with arm,pl310-cache controller. + - const: marvell,tauros3-cache + - const: arm,pl310-cache + + cache-level: + const: 2 + + cache-unified: true + cache-size: true + cache-sets: true + cache-block-size: true + cache-line-size: true + + reg: + maxItems: 1 + + arm,data-latency: + description: Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 3 + items: + minimum: 0 + maximum: 8 + + arm,tag-latency: + description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 8 + + arm,dirty-latency: + description: Cycles of latency for Dirty RAMs. This is a single cell. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + + arm,filter-ranges: + description: Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 2 + maxItems: 2 + + arm,io-coherent: + description: indicates that the system is operating in an hardware + I/O coherent mode. Valid only when the arm,pl310-cache compatible + string is used. + type: boolean + + interrupts: + # Either a single combined interrupt or up to 9 individual interrupts + minItems: 1 + maxItems: 9 + + cache-id-part: + description: cache id part number to be used if it is not present + on hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + wt-override: + description: If present then L2 is forced to Write through mode + type: boolean + + arm,double-linefill: + description: Override double linefill enable setting. Enable if + non-zero, disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,double-linefill-incr: + description: Override double linefill on INCR read. Enable + if non-zero, disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,double-linefill-wrap: + description: Override double linefill on WRAP read. Enable + if non-zero, disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,prefetch-drop: + description: Override prefetch drop enable setting. Enable if non-zero, + disable if zero. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,prefetch-offset: + description: Override prefetch offset value. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] + + arm,shared-override: + description: The default behavior of the L220 or PL310 cache + controllers with respect to the shareable attribute is to transform "normal + memory non-cacheable transactions" into "cacheable no allocate" (for reads) + or "write through no write allocate" (for writes). + On systems where this may cause DMA buffer corruption, this property must + be specified to indicate that such transforms are precluded. + type: boolean + + arm,parity-enable: + description: enable parity checking on the L2 cache (L220 or PL310). + type: boolean + + arm,parity-disable: + description: disable parity checking on the L2 cache (L220 or PL310). + type: boolean + + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + + arm,outer-sync-disable: + description: disable the outer sync operation on the L2 cache. + Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that + will randomly hang unless outer sync operations are disabled. + type: boolean + + prefetch-data: + description: | + Data prefetch. Value: <0> (forcibly disable), <1> + (forcibly enable), property absent (retain settings set by firmware) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + prefetch-instr: + description: | + Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,dynamic-clock-gating: + description: | + L2 dynamic clock gating. Value: <0> (forcibly + disable), <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,standby-mode: + description: L2 standby mode enable. Value <0> (forcibly disable), + <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + arm,early-bresp-disable: + description: Disable the CA9 optimization Early BRESP (PL310) + type: boolean + + arm,full-line-zero-disable: + description: Disable the CA9 optimization Full line of zero + write (PL310) + type: boolean + +required: + - compatible + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@fff12000 { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; + }; + +... diff --git a/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt b/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt new file mode 100644 index 000000000000..0d244b999d10 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt @@ -0,0 +1,16 @@ +* Marvell Feroceon Cache + +Required properties: +- compatible : Should be either "marvell,feroceon-cache" or + "marvell,kirkwood-cache". + +Optional properties: +- reg : Address of the L2 cache control register. Mandatory for + "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" + + +Example: + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt new file mode 100644 index 000000000000..31af1cbb60bd --- /dev/null +++ b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt @@ -0,0 +1,17 @@ +* Marvell Tauros2 Cache + +Required properties: +- compatible : Should be "marvell,tauros2-cache". +- marvell,tauros2-cache-features : Specify the features supported for the + tauros2 cache. + The features including + CACHE_TAUROS2_PREFETCH_ON (1 << 0) + CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + The definition can be found at + arch/arm/include/asm/hardware/cache-tauros2.h + +Example: + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml new file mode 100644 index 000000000000..14eb5175dac4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Last Level Cache Controller + +maintainers: + - Rishabh Bhatnagar + - Sai Prakash Ranjan + +description: | + LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, + that can be shared by multiple clients. Clients here are different cores in the + SoC, the idea is to minimize the local caches at the clients and migrate to + common pool of memory. Cache memory is divided into partitions called slices + which are assigned to clients. Clients can query the slice details, activate + and deactivate them. + +properties: + compatible: + enum: + - qcom,sc7180-llcc + - qcom,sc7280-llcc + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + - qcom,sdm845-llcc + - qcom,sm6350-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + - qcom,sm8550-llcc + + reg: + items: + - description: LLCC base register region + - description: LLCC broadcast base register region + + reg-names: + items: + - const: llcc_base + - const: llcc_broadcast_base + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + #include + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml new file mode 100644 index 000000000000..8a6a78e1a7ab --- /dev/null +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Composable Cache Controller + +maintainers: + - Paul Walmsley + +description: + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also + acts as directory-based coherency manager. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +select: + properties: + compatible: + contains: + enum: + - sifive,ccache0 + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache + + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - enum: + - sifive,ccache0 + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache + - const: cache + - items: + - const: starfive,jh7110-ccache + - const: sifive,ccache0 + - const: cache + - items: + - const: microchip,mpfs-ccache + - const: sifive,fu540-c000-ccache + - const: cache + + cache-block-size: + const: 64 + + cache-level: + enum: [2, 3] + + cache-sets: + enum: [1024, 2048] + + cache-size: + const: 2097152 + + cache-unified: true + + interrupts: + minItems: 3 + items: + - description: DirError interrupt + - description: DataError interrupt + - description: DataFail interrupt + - description: DirFail interrupt + + reg: + maxItems: 1 + + next-level-cache: true + + memory-region: + maxItems: 1 + description: | + The reference to the reserved-memory for the L2 Loosely Integrated Memory region. + The reserved memory node should be defined as per the bindings in reserved-memory.txt. + +allOf: + - $ref: /schemas/cache-controller.yaml# + + - if: + properties: + compatible: + contains: + enum: + - sifive,fu740-c000-ccache + - starfive,jh7110-ccache + - microchip,mpfs-ccache + + then: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError, DataFail, DirFail signals. + minItems: 4 + + else: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - sifive,fu740-c000-ccache + - starfive,jh7110-ccache + + then: + properties: + cache-sets: + const: 2048 + + else: + properties: + cache-sets: + const: 1024 + + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + +additionalProperties: false + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + reg = <0x2010000 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <1>, + <2>, + <3>; + next-level-cache = <&L25>; + memory-region = <&l2_lim>; + }; diff --git a/Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml new file mode 100644 index 000000000000..3196263685a3 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier outer cache controller + +description: | + UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache + controller system. All of them have a level 2 cache controller, and some + have a level 3 cache controller as well. + +maintainers: + - Masahiro Yamada + +properties: + compatible: + const: socionext,uniphier-system-cache + + reg: + description: | + should contain 3 regions: control register, revision register, + operation register, in this order. + maxItems: 3 + + interrupts: + description: | + Interrupts can be used to notify the completion of cache operations. + The number of interrupts should match to the number of CPU cores. + The specified interrupts correspond to CPU0, CPU1, ... in this order. + minItems: 1 + maxItems: 4 + + cache-unified: true + + cache-size: true + + cache-sets: true + + cache-line-size: true + + cache-level: + minimum: 2 + maximum: 3 + + next-level-cache: true + +allOf: + - $ref: /schemas/cache-controller.yaml# + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-unified + - cache-size + - cache-sets + - cache-line-size + - cache-level + +examples: + - | + // System with L2. + cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <0x140000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; + - | + // System with L2 and L3. + // L2 should specify the next level cache by 'next-level-cache'. + l2: cache-controller@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: cache-controller@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml deleted file mode 100644 index 1fca282f64a2..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml +++ /dev/null @@ -1,63 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Baikal-T1 L2-cache Control Block - -maintainers: - - Serge Semin - -description: | - By means of the System Controller Baikal-T1 SoC exposes a few settings to - tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible - to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 - L2-cache controller block is responsible for the tuning. Its DT node is - supposed to be a child of the system controller. - -properties: - compatible: - const: baikal,bt1-l2-ctl - - reg: - maxItems: 1 - - baikal,l2-ws-latency: - $ref: /schemas/types.yaml#/definitions/uint32 - description: Cycles of latency for Way-select RAM accesses - default: 0 - minimum: 0 - maximum: 3 - - baikal,l2-tag-latency: - $ref: /schemas/types.yaml#/definitions/uint32 - description: Cycles of latency for Tag RAM accesses - default: 0 - minimum: 0 - maximum: 3 - - baikal,l2-data-latency: - $ref: /schemas/types.yaml#/definitions/uint32 - description: Cycles of latency for Data RAM accesses - default: 1 - minimum: 0 - maximum: 3 - -additionalProperties: false - -required: - - compatible - -examples: - - | - l2@1f04d028 { - compatible = "baikal,bt1-l2-ctl"; - reg = <0x1f04d028 0x004>; - - baikal,l2-ws-latency = <1>; - baikal,l2-tag-latency = <1>; - baikal,l2-data-latency = <2>; - }; -... diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt deleted file mode 100644 index 22ad012660e9..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt +++ /dev/null @@ -1,55 +0,0 @@ -Freescale L2 Cache Controller - -L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. -The cache bindings explained below are Devicetree Specification compliant - -Required Properties: - -- compatible : Should include one of the following: - "fsl,b4420-l2-cache-controller" - "fsl,b4860-l2-cache-controller" - "fsl,bsc9131-l2-cache-controller" - "fsl,bsc9132-l2-cache-controller" - "fsl,c293-l2-cache-controller" - "fsl,mpc8536-l2-cache-controller" - "fsl,mpc8540-l2-cache-controller" - "fsl,mpc8541-l2-cache-controller" - "fsl,mpc8544-l2-cache-controller" - "fsl,mpc8548-l2-cache-controller" - "fsl,mpc8555-l2-cache-controller" - "fsl,mpc8560-l2-cache-controller" - "fsl,mpc8568-l2-cache-controller" - "fsl,mpc8569-l2-cache-controller" - "fsl,mpc8572-l2-cache-controller" - "fsl,p1010-l2-cache-controller" - "fsl,p1011-l2-cache-controller" - "fsl,p1012-l2-cache-controller" - "fsl,p1013-l2-cache-controller" - "fsl,p1014-l2-cache-controller" - "fsl,p1015-l2-cache-controller" - "fsl,p1016-l2-cache-controller" - "fsl,p1020-l2-cache-controller" - "fsl,p1021-l2-cache-controller" - "fsl,p1022-l2-cache-controller" - "fsl,p1023-l2-cache-controller" - "fsl,p1024-l2-cache-controller" - "fsl,p1025-l2-cache-controller" - "fsl,p2010-l2-cache-controller" - "fsl,p2020-l2-cache-controller" - "fsl,t2080-l2-cache-controller" - "fsl,t4240-l2-cache-controller" - and "cache". -- reg : Address and size of L2 cache controller registers -- cache-size : Size of the entire L2 cache -- interrupts : Error interrupt of L2 controller -- cache-line-size : Size of L2 cache lines - -Example: - - L2: l2-cache-controller@20000 { - compatible = "fsl,bsc9132-l2-cache-controller", "cache"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x40000>; // L2,256K - interrupts = <16 2 1 0>; - }; diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml deleted file mode 100644 index eb6ab73c0f31..000000000000 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ /dev/null @@ -1,170 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -# Copyright (C) 2020 SiFive, Inc. -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: SiFive Composable Cache Controller - -maintainers: - - Paul Walmsley - -description: - The SiFive Composable Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Composable Cache Controller also - acts as directory-based coherency manager. - All the properties in ePAPR/DeviceTree specification applies for this platform. - -select: - properties: - compatible: - contains: - enum: - - sifive,ccache0 - - sifive,fu540-c000-ccache - - sifive,fu740-c000-ccache - - required: - - compatible - -properties: - compatible: - oneOf: - - items: - - enum: - - sifive,ccache0 - - sifive,fu540-c000-ccache - - sifive,fu740-c000-ccache - - const: cache - - items: - - const: starfive,jh7110-ccache - - const: sifive,ccache0 - - const: cache - - items: - - const: microchip,mpfs-ccache - - const: sifive,fu540-c000-ccache - - const: cache - - cache-block-size: - const: 64 - - cache-level: - enum: [2, 3] - - cache-sets: - enum: [1024, 2048] - - cache-size: - const: 2097152 - - cache-unified: true - - interrupts: - minItems: 3 - items: - - description: DirError interrupt - - description: DataError interrupt - - description: DataFail interrupt - - description: DirFail interrupt - - reg: - maxItems: 1 - - next-level-cache: true - - memory-region: - maxItems: 1 - description: | - The reference to the reserved-memory for the L2 Loosely Integrated Memory region. - The reserved memory node should be defined as per the bindings in reserved-memory.txt. - -allOf: - - $ref: /schemas/cache-controller.yaml# - - - if: - properties: - compatible: - contains: - enum: - - sifive,fu740-c000-ccache - - starfive,jh7110-ccache - - microchip,mpfs-ccache - - then: - properties: - interrupts: - description: | - Must contain entries for DirError, DataError, DataFail, DirFail signals. - minItems: 4 - - else: - properties: - interrupts: - description: | - Must contain entries for DirError, DataError and DataFail signals. - maxItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - sifive,fu740-c000-ccache - - starfive,jh7110-ccache - - then: - properties: - cache-sets: - const: 2048 - - else: - properties: - cache-sets: - const: 1024 - - - if: - properties: - compatible: - contains: - const: sifive,ccache0 - - then: - properties: - cache-level: - enum: [2, 3] - - else: - properties: - cache-level: - const: 2 - -additionalProperties: false - -required: - - compatible - - cache-block-size - - cache-level - - cache-sets - - cache-size - - cache-unified - - interrupts - - reg - -examples: - - | - cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - reg = <0x2010000 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <1>, - <2>, - <3>; - next-level-cache = <&L25>; - memory-region = <&l2_lim>; - }; -- cgit v1.2.3