From ba5295e55dd941425b10924f4f5c7af6eac4a1cb Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Tue, 9 Dec 2014 09:28:09 +0100 Subject: ASoC: pcm512x: Also support PCM514x devices Signed-off-by: Peter Rosin Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/pcm512x.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt index faff75e64573..98e0d34915e8 100644 --- a/Documentation/devicetree/bindings/sound/pcm512x.txt +++ b/Documentation/devicetree/bindings/sound/pcm512x.txt @@ -5,7 +5,8 @@ on the board). Required properties: - - compatible : One of "ti,pcm5121" or "ti,pcm5122" + - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or + "ti,pcm5142" - reg : the I2C address of the device for I2C, the chip select number for SPI. -- cgit v1.2.3 From d8b58e0b5322f91eb6fcffc337a74083a24c7149 Mon Sep 17 00:00:00 2001 From: Andrew Jackson Date: Tue, 30 Dec 2014 10:55:47 +0000 Subject: ASoC: dwc: Add documentation for I2S DT Add documentation for Designware I2S hardware block. The block requires one clock (for audio sampling) and DMA channels for receive and transmit. Signed-off-by: Andrew Jackson Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/designware-i2s.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt new file mode 100644 index 000000000000..7bb54247f8e8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/designware-i2s.txt @@ -0,0 +1,31 @@ +DesignWare I2S controller + +Required properties: + - compatible : Must be "snps,designware-i2s" + - reg : Must contain the I2S core's registers location and length + - clocks : Pairs of phandle and specifier referencing the controller's + clocks. The controller expects one clock: the clock used as the sampling + rate reference clock sample. + - clock-names : "i2sclk" for the sample rate reference clock. + - dmas: Pairs of phandle and specifier for the DMA channels that are used by + the core. The core expects one or two dma channels: one for transmit and + one for receive. + - dma-names : "tx" for the transmit channel, "rx" for the receive channel. + +For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' +properties please check: + * resource-names.txt + * clock/clock-bindings.txt + * dma/dma.txt + +Example: + + soc_i2s: i2s@7ff90000 { + compatible = "snps,designware-i2s"; + reg = <0x0 0x7ff90000 0x0 0x1000>; + clocks = <&scpi_i2sclk 0>; + clock-names = "i2sclk"; + #sound-dai-cells = <0>; + dmas = <&dma0 5>; + dma-names = "tx"; + }; -- cgit v1.2.3 From a37f1b8fdc912600c24f9d0d45d7046e50a031e4 Mon Sep 17 00:00:00 2001 From: Anatol Pomozov Date: Tue, 30 Dec 2014 11:12:35 -0800 Subject: ASoC: tegra: Add platform driver for rt5677 audio codec The driver supports NVIDIA Tegra Ryu board Sponsored: Google ChromeOS Signed-off-by: Anatol Pomozov Signed-off-by: Mark Brown --- .../bindings/sound/nvidia,tegra-audio-rt5677.txt | 67 ++++ sound/soc/tegra/Kconfig | 10 + sound/soc/tegra/Makefile | 2 + sound/soc/tegra/tegra_rt5677.c | 347 +++++++++++++++++++++ 4 files changed, 426 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt create mode 100644 sound/soc/tegra/tegra_rt5677.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt new file mode 100644 index 000000000000..a4589cda214e --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5677.txt @@ -0,0 +1,67 @@ +NVIDIA Tegra audio complex, with RT5677 CODEC + +Required properties: +- compatible : "nvidia,tegra-audio-rt5677" +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + - pll_a + - pll_a_out0 + - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) +- nvidia,model : The user-visible name of this sound complex. +- nvidia,audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names for sources and + sinks are the RT5677's pins (as documented in its binding), and the jacks + on the board: + + * Headphone + * Speaker + * Headset Mic + * Internal Mic 1 + * Internal Mic 2 + +- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's + connected to the CODEC. +- nvidia,audio-codec : The phandle of the RT5677 audio codec. This binding + assumes that AIF1 on the CODEC is connected to Tegra. + +Optional properties: +- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in +- nvidia,hp-en-gpios : The GPIO that enables headphone amplifier +- nvidia,mic-present-gpios: The GPIO that mic jack is plugged in +- nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal + +Example: + +sound { + compatible = "nvidia,tegra-audio-rt5677-ryu", + "nvidia,tegra-audio-rt5677"; + nvidia,model = "NVIDIA Tegra Ryu"; + + nvidia,audio-routing = + "Headphone", "LOUT2", + "Headphone", "LOUT1", + "Headset Mic", "MICBIAS1", + "IN1P", "Headset Mic", + "IN1N", "Headset Mic", + "DMIC L1", "Internal Mic 1", + "DMIC R1", "Internal Mic 1", + "DMIC L2", "Internal Mic 2", + "DMIC R2", "Internal Mic 2", + "Speaker", "PDM1L", + "Speaker", "PDM1R"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5677>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + nvidia,mic-present-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + nvidia,hp-en-gpios = <&rt5677 1 GPIO_ACTIVE_HIGH>; + nvidia,dmic-clk-en-gpios = <&rt5677 2 GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; +}; diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig index 31198cf7f88d..a6768f832c6f 100644 --- a/sound/soc/tegra/Kconfig +++ b/sound/soc/tegra/Kconfig @@ -128,3 +128,13 @@ config SND_SOC_TEGRA_MAX98090 help Say Y or M here if you want to add support for SoC audio on Tegra boards using the MAX98090 codec, such as Venice2. + +config SND_SOC_TEGRA_RT5677 + tristate "SoC Audio support for Tegra boards using a RT5677 codec" + depends on SND_SOC_TEGRA && I2C && GPIOLIB + select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC + select SND_SOC_TEGRA30_I2S if ARCH_TEGRA_3x_SOC + select SND_SOC_RT5677 + help + Say Y or M here if you want to add support for SoC audio on Tegra + boards using the RT5677 codec, such as Ryu. diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile index 5ae588cd96c4..9171655ad843 100644 --- a/sound/soc/tegra/Makefile +++ b/sound/soc/tegra/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_SND_SOC_TEGRA30_I2S) += snd-soc-tegra30-i2s.o # Tegra machine Support snd-soc-tegra-rt5640-objs := tegra_rt5640.o +snd-soc-tegra-rt5677-objs := tegra_rt5677.o snd-soc-tegra-wm8753-objs := tegra_wm8753.o snd-soc-tegra-wm8903-objs := tegra_wm8903.o snd-soc-tegra-wm9712-objs := tegra_wm9712.o @@ -27,6 +28,7 @@ snd-soc-tegra-alc5632-objs := tegra_alc5632.o snd-soc-tegra-max98090-objs := tegra_max98090.o obj-$(CONFIG_SND_SOC_TEGRA_RT5640) += snd-soc-tegra-rt5640.o +obj-$(CONFIG_SND_SOC_TEGRA_RT5677) += snd-soc-tegra-rt5677.o obj-$(CONFIG_SND_SOC_TEGRA_WM8753) += snd-soc-tegra-wm8753.o obj-$(CONFIG_SND_SOC_TEGRA_WM8903) += snd-soc-tegra-wm8903.o obj-$(CONFIG_SND_SOC_TEGRA_WM9712) += snd-soc-tegra-wm9712.o diff --git a/sound/soc/tegra/tegra_rt5677.c b/sound/soc/tegra/tegra_rt5677.c new file mode 100644 index 000000000000..e4cf978a6e3a --- /dev/null +++ b/sound/soc/tegra/tegra_rt5677.c @@ -0,0 +1,347 @@ +/* +* tegra_rt5677.c - Tegra machine ASoC driver for boards using RT5677 codec. + * + * Copyright (c) 2014, The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * Based on code copyright/by: + * + * Copyright (C) 2010-2012 - NVIDIA, Inc. + * Copyright (C) 2011 The AC100 Kernel Team + * (c) 2009, 2010 Nvidia Graphics Pvt. Ltd. + * Copyright 2007 Wolfson Microelectronics PLC. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "../codecs/rt5677.h" + +#include "tegra_asoc_utils.h" + +#define DRV_NAME "tegra-snd-rt5677" + +struct tegra_rt5677 { + struct tegra_asoc_utils_data util_data; + int gpio_hp_det; + int gpio_hp_en; + int gpio_mic_present; + int gpio_dmic_clk_en; +}; + +static int tegra_rt5677_asoc_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_card *card = rtd->card; + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(card); + int srate, mclk, err; + + srate = params_rate(params); + mclk = 256 * srate; + + err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); + if (err < 0) { + dev_err(card->dev, "Can't configure clocks\n"); + return err; + } + + err = snd_soc_dai_set_sysclk(codec_dai, RT5677_SCLK_S_MCLK, mclk, + SND_SOC_CLOCK_IN); + if (err < 0) { + dev_err(card->dev, "codec_dai clock not set\n"); + return err; + } + + return 0; +} + +static int tegra_rt5677_event_hp(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *k, int event) +{ + struct snd_soc_dapm_context *dapm = w->dapm; + struct snd_soc_card *card = dapm->card; + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(card); + + if (!gpio_is_valid(machine->gpio_hp_en)) + return 0; + + gpio_set_value_cansleep(machine->gpio_hp_en, + SND_SOC_DAPM_EVENT_ON(event)); + + return 0; +} + +static struct snd_soc_ops tegra_rt5677_ops = { + .hw_params = tegra_rt5677_asoc_hw_params, +}; + +static struct snd_soc_jack tegra_rt5677_hp_jack; + +static struct snd_soc_jack_pin tegra_rt5677_hp_jack_pins = { + .pin = "Headphone", + .mask = SND_JACK_HEADPHONE, +}; +static struct snd_soc_jack_gpio tegra_rt5677_hp_jack_gpio = { + .name = "Headphone detection", + .report = SND_JACK_HEADPHONE, + .debounce_time = 150, +}; + +static struct snd_soc_jack tegra_rt5677_mic_jack; + +static struct snd_soc_jack_pin tegra_rt5677_mic_jack_pins = { + .pin = "Headset Mic", + .mask = SND_JACK_MICROPHONE, +}; + +static struct snd_soc_jack_gpio tegra_rt5677_mic_jack_gpio = { + .name = "Headset Mic detection", + .report = SND_JACK_MICROPHONE, + .debounce_time = 150, + .invert = 1 +}; + +static const struct snd_soc_dapm_widget tegra_rt5677_dapm_widgets[] = { + SND_SOC_DAPM_SPK("Speaker", NULL), + SND_SOC_DAPM_HP("Headphone", tegra_rt5677_event_hp), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Internal Mic 1", NULL), + SND_SOC_DAPM_MIC("Internal Mic 2", NULL), +}; + +static const struct snd_kcontrol_new tegra_rt5677_controls[] = { + SOC_DAPM_PIN_SWITCH("Speaker"), + SOC_DAPM_PIN_SWITCH("Headphone"), + SOC_DAPM_PIN_SWITCH("Headset Mic"), + SOC_DAPM_PIN_SWITCH("Internal Mic 1"), + SOC_DAPM_PIN_SWITCH("Internal Mic 2"), +}; + +static int tegra_rt5677_asoc_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_codec *codec = codec_dai->codec; + struct snd_soc_dapm_context *dapm = &codec->dapm; + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(rtd->card); + + snd_soc_jack_new(codec, "Headphone Jack", SND_JACK_HEADPHONE, + &tegra_rt5677_hp_jack); + snd_soc_jack_add_pins(&tegra_rt5677_hp_jack, 1, + &tegra_rt5677_hp_jack_pins); + + if (gpio_is_valid(machine->gpio_hp_det)) { + tegra_rt5677_hp_jack_gpio.gpio = machine->gpio_hp_det; + snd_soc_jack_add_gpios(&tegra_rt5677_hp_jack, 1, + &tegra_rt5677_hp_jack_gpio); + } + + + snd_soc_jack_new(codec, "Mic Jack", SND_JACK_MICROPHONE, + &tegra_rt5677_mic_jack); + snd_soc_jack_add_pins(&tegra_rt5677_mic_jack, 1, + &tegra_rt5677_mic_jack_pins); + + if (gpio_is_valid(machine->gpio_mic_present)) { + tegra_rt5677_mic_jack_gpio.gpio = machine->gpio_mic_present; + snd_soc_jack_add_gpios(&tegra_rt5677_mic_jack, 1, + &tegra_rt5677_mic_jack_gpio); + } + + snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); + + return 0; +} + +static int tegra_rt5677_card_remove(struct snd_soc_card *card) +{ + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(card); + + if (gpio_is_valid(machine->gpio_hp_det)) { + snd_soc_jack_free_gpios(&tegra_rt5677_hp_jack, 1, + &tegra_rt5677_hp_jack_gpio); + } + + if (gpio_is_valid(machine->gpio_mic_present)) { + snd_soc_jack_free_gpios(&tegra_rt5677_mic_jack, 1, + &tegra_rt5677_mic_jack_gpio); + } + + return 0; +} + +static struct snd_soc_dai_link tegra_rt5677_dai = { + .name = "RT5677", + .stream_name = "RT5677 PCM", + .codec_dai_name = "rt5677-aif1", + .init = tegra_rt5677_asoc_init, + .ops = &tegra_rt5677_ops, + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, +}; + +static struct snd_soc_card snd_soc_tegra_rt5677 = { + .name = "tegra-rt5677", + .owner = THIS_MODULE, + .remove = tegra_rt5677_card_remove, + .dai_link = &tegra_rt5677_dai, + .num_links = 1, + .controls = tegra_rt5677_controls, + .num_controls = ARRAY_SIZE(tegra_rt5677_controls), + .dapm_widgets = tegra_rt5677_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(tegra_rt5677_dapm_widgets), + .fully_routed = true, +}; + +static int tegra_rt5677_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct snd_soc_card *card = &snd_soc_tegra_rt5677; + struct tegra_rt5677 *machine; + int ret; + + machine = devm_kzalloc(&pdev->dev, + sizeof(struct tegra_rt5677), GFP_KERNEL); + if (!machine) + return -ENOMEM; + + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, machine); + + machine->gpio_hp_det = of_get_named_gpio(np, "nvidia,hp-det-gpios", 0); + if (machine->gpio_hp_det == -EPROBE_DEFER) + return -EPROBE_DEFER; + + machine->gpio_mic_present = of_get_named_gpio(np, + "nvidia,mic-present-gpios", 0); + if (machine->gpio_mic_present == -EPROBE_DEFER) + return -EPROBE_DEFER; + + machine->gpio_hp_en = of_get_named_gpio(np, "nvidia,hp-en-gpios", 0); + if (machine->gpio_hp_en == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (gpio_is_valid(machine->gpio_hp_en)) { + ret = devm_gpio_request_one(&pdev->dev, machine->gpio_hp_en, + GPIOF_OUT_INIT_LOW, "hp_en"); + if (ret) { + dev_err(card->dev, "cannot get hp_en gpio\n"); + return ret; + } + } + + machine->gpio_dmic_clk_en = of_get_named_gpio(np, + "nvidia,dmic-clk-en-gpios", 0); + if (machine->gpio_dmic_clk_en == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (gpio_is_valid(machine->gpio_dmic_clk_en)) { + ret = devm_gpio_request_one(&pdev->dev, + machine->gpio_dmic_clk_en, + GPIOF_OUT_INIT_HIGH, "dmic_clk_en"); + if (ret) { + dev_err(card->dev, "cannot get dmic_clk_en gpio\n"); + return ret; + } + } + + ret = snd_soc_of_parse_card_name(card, "nvidia,model"); + if (ret) + goto err; + + ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing"); + if (ret) + goto err; + + tegra_rt5677_dai.codec_of_node = of_parse_phandle(np, + "nvidia,audio-codec", 0); + if (!tegra_rt5677_dai.codec_of_node) { + dev_err(&pdev->dev, + "Property 'nvidia,audio-codec' missing or invalid\n"); + ret = -EINVAL; + goto err; + } + + tegra_rt5677_dai.cpu_of_node = of_parse_phandle(np, + "nvidia,i2s-controller", 0); + if (!tegra_rt5677_dai.cpu_of_node) { + dev_err(&pdev->dev, + "Property 'nvidia,i2s-controller' missing or invalid\n"); + ret = -EINVAL; + goto err; + } + tegra_rt5677_dai.platform_of_node = tegra_rt5677_dai.cpu_of_node; + + ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev); + if (ret) + goto err; + + ret = snd_soc_register_card(card); + if (ret) { + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", + ret); + goto err_fini_utils; + } + + return 0; + +err_fini_utils: + tegra_asoc_utils_fini(&machine->util_data); +err: + return ret; +} + +static int tegra_rt5677_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(card); + + snd_soc_unregister_card(card); + + tegra_asoc_utils_fini(&machine->util_data); + + return 0; +} + +static const struct of_device_id tegra_rt5677_of_match[] = { + { .compatible = "nvidia,tegra-audio-rt5677", }, + {}, +}; + +static struct platform_driver tegra_rt5677_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &snd_soc_pm_ops, + .of_match_table = tegra_rt5677_of_match, + }, + .probe = tegra_rt5677_probe, + .remove = tegra_rt5677_remove, +}; +module_platform_driver(tegra_rt5677_driver); + +MODULE_AUTHOR("Anatol Pomozov "); +MODULE_DESCRIPTION("Tegra+RT5677 machine ASoC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, tegra_rt5677_of_match); -- cgit v1.2.3 From 57b7068de5d0cca8ac6e21085b843c1bbd49d3f4 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Fri, 26 Dec 2014 20:19:38 +0300 Subject: ASoC: add xtensa xtfpga I2S interface and platform XTFPGA boards provides an audio subsystem that consists of TI CDCE706 clock synthesizer, I2S transmitter and TLV320AIC23 audio codec. I2S transmitter has MMIO-based interface that resembles that of the OpenCores I2S transmitter. I2S transmitter is always a master on I2S bus. There's no specialized audio DMA, sample data are transferred to I2S transmitter FIFO by CPU through memory-mapped queue interface. Signed-off-by: Max Filippov Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/cdns,xtfpga-i2s.txt | 18 + MAINTAINERS | 1 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/xtensa/Kconfig | 7 + sound/soc/xtensa/Makefile | 3 + sound/soc/xtensa/xtfpga-i2s.c | 675 +++++++++++++++++++++ 7 files changed, 706 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt create mode 100644 sound/soc/xtensa/Kconfig create mode 100644 sound/soc/xtensa/Makefile create mode 100644 sound/soc/xtensa/xtfpga-i2s.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt new file mode 100644 index 000000000000..befd125d18bb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt @@ -0,0 +1,18 @@ +Bindings for I2S controller built into xtfpga Xtensa bitstreams. + +Required properties: +- compatible: shall be "cdns,xtfpga-i2s". +- reg: memory region (address and length) with device registers. +- interrupts: interrupt for the device. +- clocks: phandle to the clk used as master clock. I2S bus clock + is derived from it. + +Examples: + + i2s0: xtfpga-i2s@0d080000 { + #sound-dai-cells = <0>; + compatible = "cdns,xtfpga-i2s"; + reg = <0x0d080000 0x40>; + interrupts = <2 1>; + clocks = <&cdce706 4>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index ddb9ac8d32b3..f1eb40f8926c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10628,6 +10628,7 @@ M: Max Filippov L: linux-xtensa@linux-xtensa.org S: Maintained F: drivers/spi/spi-xtensa-xtfpga.c +F: sound/soc/xtensa/xtfpga-i2s.c YAM DRIVER FOR AX.25 M: Jean-Paul Roubelat diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 7d5d6444a837..dcc79aa0236b 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -55,6 +55,7 @@ source "sound/soc/spear/Kconfig" source "sound/soc/tegra/Kconfig" source "sound/soc/txx9/Kconfig" source "sound/soc/ux500/Kconfig" +source "sound/soc/xtensa/Kconfig" # Supported codecs source "sound/soc/codecs/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 865e090c8061..5b3c8f67c8db 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_SND_SOC) += spear/ obj-$(CONFIG_SND_SOC) += tegra/ obj-$(CONFIG_SND_SOC) += txx9/ obj-$(CONFIG_SND_SOC) += ux500/ +obj-$(CONFIG_SND_SOC) += xtensa/ diff --git a/sound/soc/xtensa/Kconfig b/sound/soc/xtensa/Kconfig new file mode 100644 index 000000000000..c201beb36de6 --- /dev/null +++ b/sound/soc/xtensa/Kconfig @@ -0,0 +1,7 @@ +config SND_SOC_XTFPGA_I2S + tristate "XTFPGA I2S master" + select REGMAP_MMIO + help + Say Y or M if you want to add support for codecs attached to the + I2S interface on XTFPGA daughter board. You will also need to select + the drivers for the rest of XTFPGA audio subsystem. diff --git a/sound/soc/xtensa/Makefile b/sound/soc/xtensa/Makefile new file mode 100644 index 000000000000..15efbf914226 --- /dev/null +++ b/sound/soc/xtensa/Makefile @@ -0,0 +1,3 @@ +snd-soc-xtfpga-i2s-objs := xtfpga-i2s.o + +obj-$(CONFIG_SND_SOC_XTFPGA_I2S) += snd-soc-xtfpga-i2s.o diff --git a/sound/soc/xtensa/xtfpga-i2s.c b/sound/soc/xtensa/xtfpga-i2s.c new file mode 100644 index 000000000000..1cfb19e12949 --- /dev/null +++ b/sound/soc/xtensa/xtfpga-i2s.c @@ -0,0 +1,675 @@ +/* + * Xtfpga I2S controller driver + * + * Copyright (c) 2014 Cadence Design Systems Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "xtfpga-i2s" + +#define XTFPGA_I2S_VERSION 0x00 +#define XTFPGA_I2S_CONFIG 0x04 +#define XTFPGA_I2S_INT_MASK 0x08 +#define XTFPGA_I2S_INT_STATUS 0x0c +#define XTFPGA_I2S_CHAN0_DATA 0x10 +#define XTFPGA_I2S_CHAN1_DATA 0x14 +#define XTFPGA_I2S_CHAN2_DATA 0x18 +#define XTFPGA_I2S_CHAN3_DATA 0x1c + +#define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1 +#define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2 +#define XTFPGA_I2S_CONFIG_LEFT 0x4 +#define XTFPGA_I2S_CONFIG_RATIO_BASE 8 +#define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00 +#define XTFPGA_I2S_CONFIG_RES_BASE 16 +#define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000 +#define XTFPGA_I2S_CONFIG_LEVEL_BASE 24 +#define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000 +#define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28 + +#define XTFPGA_I2S_INT_UNDERRUN 0x1 +#define XTFPGA_I2S_INT_LEVEL 0x2 +#define XTFPGA_I2S_INT_VALID 0x3 + +#define XTFPGA_I2S_FIFO_SIZE 8192 + +/* + * I2S controller operation: + * + * Enabling TX: output 1 period of zeros (starting with left channel) + * and then queued data. + * + * Level status and interrupt: whenever FIFO level is below FIFO trigger, + * level status is 1 and an IRQ is asserted (if enabled). + * + * Underrun status and interrupt: whenever FIFO is empty, underrun status + * is 1 and an IRQ is asserted (if enabled). + */ +struct xtfpga_i2s { + struct device *dev; + struct clk *clk; + struct regmap *regmap; + void __iomem *regs; + + /* current playback substream. NULL if not playing. + * + * Access to that field is synchronized between the interrupt handler + * and userspace through RCU. + * + * Interrupt handler (threaded part) does PIO on substream data in RCU + * read-side critical section. Trigger callback sets and clears the + * pointer when the playback is started and stopped with + * rcu_assign_pointer. When userspace is about to free the playback + * stream in the pcm_close callback it synchronizes with the interrupt + * handler by means of synchronize_rcu call. + */ + struct snd_pcm_substream *tx_substream; + unsigned (*tx_fn)(struct xtfpga_i2s *i2s, + struct snd_pcm_runtime *runtime, + unsigned tx_ptr); + unsigned tx_ptr; /* next frame index in the sample buffer */ + + /* current fifo level estimate. + * Doesn't have to be perfectly accurate, but must be not less than + * the actual FIFO level in order to avoid stall on push attempt. + */ + unsigned tx_fifo_level; + + /* FIFO level at which level interrupt occurs */ + unsigned tx_fifo_low; + + /* maximal FIFO level */ + unsigned tx_fifo_high; +}; + +static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg) +{ + return reg >= XTFPGA_I2S_CONFIG; +} + +static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg) +{ + return reg < XTFPGA_I2S_CHAN0_DATA; +} + +static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg == XTFPGA_I2S_INT_STATUS; +} + +static const struct regmap_config xtfpga_i2s_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = XTFPGA_I2S_CHAN3_DATA, + .writeable_reg = xtfpga_i2s_wr_reg, + .readable_reg = xtfpga_i2s_rd_reg, + .volatile_reg = xtfpga_i2s_volatile_reg, + .cache_type = REGCACHE_FLAT, +}; + +/* Generate functions that do PIO from TX DMA area to FIFO for all supported + * stream formats. + * Functions will be called xtfpga_pcm_tx_x, e.g. + * xtfpga_pcm_tx_2x16 for 16-bit stereo. + * + * FIFO consists of 32-bit words, one word per channel, always 2 channels. + * If I2S interface is configured with smaller sample resolution, only + * the LSB of each word is used. + */ +#define xtfpga_pcm_tx_fn(channels, sample_bits) \ +static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \ + struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \ + unsigned tx_ptr) \ +{ \ + const u##sample_bits (*p)[channels] = \ + (void *)runtime->dma_area; \ +\ + for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \ + i2s->tx_fifo_level += 2) { \ + iowrite32(p[tx_ptr][0], \ + i2s->regs + XTFPGA_I2S_CHAN0_DATA); \ + iowrite32(p[tx_ptr][channels - 1], \ + i2s->regs + XTFPGA_I2S_CHAN0_DATA); \ + if (++tx_ptr >= runtime->buffer_size) \ + tx_ptr = 0; \ + } \ + return tx_ptr; \ +} + +xtfpga_pcm_tx_fn(1, 16) +xtfpga_pcm_tx_fn(2, 16) +xtfpga_pcm_tx_fn(1, 32) +xtfpga_pcm_tx_fn(2, 32) + +#undef xtfpga_pcm_tx_fn + +static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s) +{ + struct snd_pcm_substream *tx_substream; + bool tx_active; + + rcu_read_lock(); + tx_substream = rcu_dereference(i2s->tx_substream); + tx_active = tx_substream && snd_pcm_running(tx_substream); + if (tx_active) { + unsigned tx_ptr = ACCESS_ONCE(i2s->tx_ptr); + unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime, + tx_ptr); + + cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr); + } + rcu_read_unlock(); + + return tx_active; +} + +static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s) +{ + unsigned int_status; + unsigned i; + + regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, + &int_status); + + for (i = 0; i < 2; ++i) { + bool tx_active = xtfpga_pcm_push_tx(i2s); + + regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, + XTFPGA_I2S_INT_VALID); + if (tx_active) + regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, + &int_status); + + if (!tx_active || + !(int_status & XTFPGA_I2S_INT_LEVEL)) + break; + + /* After the push the level IRQ is still asserted, + * means FIFO level is below tx_fifo_low. Estimate + * it as tx_fifo_low. + */ + i2s->tx_fifo_level = i2s->tx_fifo_low; + } + + if (!(int_status & XTFPGA_I2S_INT_LEVEL)) + regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, + XTFPGA_I2S_INT_VALID); + else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN)) + regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, + XTFPGA_I2S_INT_UNDERRUN); + + if (!(int_status & XTFPGA_I2S_INT_UNDERRUN)) + regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, + XTFPGA_I2S_CONFIG_INT_ENABLE | + XTFPGA_I2S_CONFIG_TX_ENABLE, + XTFPGA_I2S_CONFIG_INT_ENABLE | + XTFPGA_I2S_CONFIG_TX_ENABLE); + else + regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, + XTFPGA_I2S_CONFIG_INT_ENABLE | + XTFPGA_I2S_CONFIG_TX_ENABLE, 0); +} + +static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id) +{ + struct xtfpga_i2s *i2s = dev_id; + struct snd_pcm_substream *tx_substream; + unsigned config, int_status, int_mask; + + regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config); + regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask); + regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status); + + if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) || + !(int_status & int_mask & XTFPGA_I2S_INT_VALID)) + return IRQ_NONE; + + /* Update FIFO level estimate in accordance with interrupt status + * register. + */ + if (int_status & XTFPGA_I2S_INT_UNDERRUN) { + i2s->tx_fifo_level = 0; + regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, + XTFPGA_I2S_CONFIG_TX_ENABLE, 0); + } else { + /* The FIFO isn't empty, but is below tx_fifo_low. Estimate + * it as tx_fifo_low. + */ + i2s->tx_fifo_level = i2s->tx_fifo_low; + } + + rcu_read_lock(); + tx_substream = rcu_dereference(i2s->tx_substream); + + if (tx_substream && snd_pcm_running(tx_substream)) { + snd_pcm_period_elapsed(tx_substream); + if (int_status & XTFPGA_I2S_INT_UNDERRUN) + dev_dbg_ratelimited(i2s->dev, "%s: underrun\n", + __func__); + } + rcu_read_unlock(); + + /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is + * not empty. + */ + xtfpga_pcm_refill_fifo(i2s); + + return IRQ_HANDLED; +} + +static int xtfpga_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai); + + snd_soc_dai_set_dma_data(dai, substream, i2s); + return 0; +} + +static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai); + unsigned srate = params_rate(params); + unsigned channels = params_channels(params); + unsigned period_size = params_period_size(params); + unsigned sample_size = snd_pcm_format_width(params_format(params)); + unsigned freq, ratio, level; + int err; + + regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, + XTFPGA_I2S_CONFIG_RES_MASK, + sample_size << XTFPGA_I2S_CONFIG_RES_BASE); + + freq = 256 * srate; + err = clk_set_rate(i2s->clk, freq); + if (err < 0) + return err; + + /* ratio field of the config register controls MCLK->I2S clock + * derivation: I2S clock = MCLK / (2 * (ratio + 2)). + * + * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo + * and 2 for 16 bit stereo. + */ + ratio = (freq - (srate * sample_size * 8)) / + (srate * sample_size * 4); + + regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, + XTFPGA_I2S_CONFIG_RATIO_MASK, + ratio << XTFPGA_I2S_CONFIG_RATIO_BASE); + + i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2; + + /* period_size * 2: FIFO always gets 2 samples per frame */ + for (level = 1; + i2s->tx_fifo_low / 2 >= period_size * 2 && + level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >> + XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level) + i2s->tx_fifo_low /= 2; + + i2s->tx_fifo_high = 2 * i2s->tx_fifo_low; + + regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG, + XTFPGA_I2S_CONFIG_LEVEL_MASK, + level << XTFPGA_I2S_CONFIG_LEVEL_BASE); + + dev_dbg(i2s->dev, + "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n", + __func__, srate, channels, sample_size, period_size); + dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n", + __func__, freq, ratio, level); + + return 0; +} + +static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai, + unsigned int fmt) +{ + if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) + return -EINVAL; + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) + return -EINVAL; + if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S) + return -EINVAL; + + return 0; +} + +/* PCM */ + +static const struct snd_pcm_hardware xtfpga_pcm_hardware = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_BLOCK_TRANSFER, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 1, + .channels_max = 2, + .period_bytes_min = 2, + .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8, + .periods_min = 2, + .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2, + .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8, + .fifo_size = 16, +}; + +static int xtfpga_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + void *p; + + snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware); + p = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); + runtime->private_data = p; + + return 0; +} + +static int xtfpga_pcm_close(struct snd_pcm_substream *substream) +{ + synchronize_rcu(); + return 0; +} + +static int xtfpga_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + int ret; + struct snd_pcm_runtime *runtime = substream->runtime; + struct xtfpga_i2s *i2s = runtime->private_data; + unsigned channels = params_channels(hw_params); + + switch (channels) { + case 1: + case 2: + break; + + default: + return -EINVAL; + + } + + switch (params_format(hw_params)) { + case SNDRV_PCM_FORMAT_S16_LE: + i2s->tx_fn = (channels == 1) ? + xtfpga_pcm_tx_1x16 : + xtfpga_pcm_tx_2x16; + break; + + case SNDRV_PCM_FORMAT_S32_LE: + i2s->tx_fn = (channels == 1) ? + xtfpga_pcm_tx_1x32 : + xtfpga_pcm_tx_2x32; + break; + + default: + return -EINVAL; + } + + ret = snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); + return ret; +} + +static int xtfpga_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + int ret = 0; + struct snd_pcm_runtime *runtime = substream->runtime; + struct xtfpga_i2s *i2s = runtime->private_data; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + ACCESS_ONCE(i2s->tx_ptr) = 0; + rcu_assign_pointer(i2s->tx_substream, substream); + xtfpga_pcm_refill_fifo(i2s); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + rcu_assign_pointer(i2s->tx_substream, NULL); + break; + + default: + ret = -EINVAL; + break; + } + return ret; +} + +static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct xtfpga_i2s *i2s = runtime->private_data; + snd_pcm_uframes_t pos = ACCESS_ONCE(i2s->tx_ptr); + + return pos < runtime->buffer_size ? pos : 0; +} + +static int xtfpga_pcm_new(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_card *card = rtd->card->snd_card; + size_t size = xtfpga_pcm_hardware.buffer_bytes_max; + + return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, + SNDRV_DMA_TYPE_DEV, + card->dev, size, size); +} + +static void xtfpga_pcm_free(struct snd_pcm *pcm) +{ + snd_pcm_lib_preallocate_free_for_all(pcm); +} + +static const struct snd_pcm_ops xtfpga_pcm_ops = { + .open = xtfpga_pcm_open, + .close = xtfpga_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = xtfpga_pcm_hw_params, + .trigger = xtfpga_pcm_trigger, + .pointer = xtfpga_pcm_pointer, +}; + +static const struct snd_soc_platform_driver xtfpga_soc_platform = { + .pcm_new = xtfpga_pcm_new, + .pcm_free = xtfpga_pcm_free, + .ops = &xtfpga_pcm_ops, +}; + +static const struct snd_soc_component_driver xtfpga_i2s_component = { + .name = DRV_NAME, +}; + +static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = { + .startup = xtfpga_i2s_startup, + .hw_params = xtfpga_i2s_hw_params, + .set_fmt = xtfpga_i2s_set_fmt, +}; + +static struct snd_soc_dai_driver xtfpga_i2s_dai[] = { + { + .name = "xtfpga-i2s", + .id = 0, + .playback = { + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .ops = &xtfpga_i2s_dai_ops, + }, +}; + +static int xtfpga_i2s_runtime_suspend(struct device *dev) +{ + struct xtfpga_i2s *i2s = dev_get_drvdata(dev); + + clk_disable_unprepare(i2s->clk); + return 0; +} + +static int xtfpga_i2s_runtime_resume(struct device *dev) +{ + struct xtfpga_i2s *i2s = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(i2s->clk); + if (ret) { + dev_err(dev, "clk_prepare_enable failed: %d\n", ret); + return ret; + } + return 0; +} + +static int xtfpga_i2s_probe(struct platform_device *pdev) +{ + struct xtfpga_i2s *i2s; + struct resource *mem; + int err, irq; + + i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); + if (!i2s) { + err = -ENOMEM; + goto err; + } + platform_set_drvdata(pdev, i2s); + i2s->dev = &pdev->dev; + dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2s->regs = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(i2s->regs)) { + err = PTR_ERR(i2s->regs); + goto err; + } + + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs, + &xtfpga_i2s_regmap_config); + if (IS_ERR(i2s->regmap)) { + dev_err(&pdev->dev, "regmap init failed\n"); + err = PTR_ERR(i2s->regmap); + goto err; + } + + i2s->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(i2s->clk)) { + dev_err(&pdev->dev, "couldn't get clock\n"); + err = PTR_ERR(i2s->clk); + goto err; + } + + regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, + (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE)); + regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID); + regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); + err = irq; + goto err; + } + err = devm_request_threaded_irq(&pdev->dev, irq, NULL, + xtfpga_i2s_threaded_irq_handler, + IRQF_SHARED | IRQF_ONESHOT, + pdev->name, i2s); + if (err < 0) { + dev_err(&pdev->dev, "request_irq failed\n"); + goto err; + } + + err = snd_soc_register_platform(&pdev->dev, &xtfpga_soc_platform); + if (err < 0) { + dev_err(&pdev->dev, "couldn't register platform\n"); + goto err; + } + err = devm_snd_soc_register_component(&pdev->dev, + &xtfpga_i2s_component, + xtfpga_i2s_dai, + ARRAY_SIZE(xtfpga_i2s_dai)); + if (err < 0) { + dev_err(&pdev->dev, "couldn't register component\n"); + goto err_unregister_platform; + } + + pm_runtime_enable(&pdev->dev); + if (!pm_runtime_enabled(&pdev->dev)) { + err = xtfpga_i2s_runtime_resume(&pdev->dev); + if (err) + goto err_pm_disable; + } + return 0; + +err_pm_disable: + pm_runtime_disable(&pdev->dev); +err_unregister_platform: + snd_soc_unregister_platform(&pdev->dev); +err: + dev_err(&pdev->dev, "%s: err = %d\n", __func__, err); + return err; +} + +static int xtfpga_i2s_remove(struct platform_device *pdev) +{ + struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev); + + snd_soc_unregister_platform(&pdev->dev); + if (i2s->regmap && !IS_ERR(i2s->regmap)) { + regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0); + regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0); + regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, + XTFPGA_I2S_INT_VALID); + } + pm_runtime_disable(&pdev->dev); + if (!pm_runtime_status_suspended(&pdev->dev)) + xtfpga_i2s_runtime_suspend(&pdev->dev); + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id xtfpga_i2s_of_match[] = { + { .compatible = "cdns,xtfpga-i2s", }, + {}, +}; +MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match); +#endif + +static const struct dev_pm_ops xtfpga_i2s_pm_ops = { + SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend, + xtfpga_i2s_runtime_resume, NULL) +}; + +static struct platform_driver xtfpga_i2s_driver = { + .probe = xtfpga_i2s_probe, + .remove = xtfpga_i2s_remove, + .driver = { + .name = "xtfpga-i2s", + .of_match_table = of_match_ptr(xtfpga_i2s_of_match), + .pm = &xtfpga_i2s_pm_ops, + }, +}; + +module_platform_driver(xtfpga_i2s_driver); + +MODULE_AUTHOR("Max Filippov "); +MODULE_DESCRIPTION("xtfpga I2S controller driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 0d40c61279510b8ce2368e1c6adcc2c4dc1af279 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 14 Jan 2015 19:42:38 +0100 Subject: ASoC: samsung: i2s: Add clk provider DT binding documentation The new DT properties required for the I2S device node to be referred as a clock provider and corresponding clock indices definition is added. Signed-off-by: Sylwester Nawrocki Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/samsung-i2s.txt | 22 ++++++++++++++++++++++ include/dt-bindings/sound/samsung-i2s.h | 8 ++++++++ 2 files changed, 30 insertions(+) create mode 100644 include/dt-bindings/sound/samsung-i2s.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index d188296bb6ec..09e0e18591ae 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt @@ -33,6 +33,25 @@ Required SoC Specific Properties: "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2 doesn't have any such mux. +- #clock-cells: should be 1, this property must be present if the I2S device + is a clock provider in terms of the common clock bindings, described in + ../clock/clock-bindings.txt. +- clock-output-names: from the common clock bindings, names of the CDCLK + I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1", + "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively. + +There are following clocks available at the I2S device nodes: + CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock, + CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the + IISPSR register), + CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in + IISMOD register). + +Refer to the SoC datasheet for availability of the above clocks. +The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available +in the IIS Multi Audio Interface (I2S0). +Note: Old DTs may not have the #clock-cells, clock-output-names properties +and then not use the I2S node as a clock supplier. Optional SoC Specific Properties: @@ -41,6 +60,7 @@ Optional SoC Specific Properties: - pinctrl-0: Should specify pin control groups used for this controller. - pinctrl-names: Should contain only one value - "default". + Example: i2s0: i2s@03830000 { @@ -54,6 +74,8 @@ i2s0: i2s@03830000 { <&clock_audss EXYNOS_I2S_BUS>, <&clock_audss EXYNOS_SCLK_I2S>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells; + clock-output-names = "i2s_cdclk0"; samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; diff --git a/include/dt-bindings/sound/samsung-i2s.h b/include/dt-bindings/sound/samsung-i2s.h new file mode 100644 index 000000000000..0c69818d530c --- /dev/null +++ b/include/dt-bindings/sound/samsung-i2s.h @@ -0,0 +1,8 @@ +#ifndef _DT_BINDINGS_SAMSUNG_I2S_H +#define _DT_BINDINGS_SAMSUNG_I2S_H + +#define CLK_I2S_CDCLK 0 +#define CLK_I2S_RCLK_SRC 1 +#define CLK_I2S_RCLK_PSR 2 + +#endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ -- cgit v1.2.3 From f9911803e82a32c126c40dd6246ade2faf472cbc Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 13 Jan 2015 21:16:34 +0200 Subject: ASoC: simple-card: Enable and disable DAI clocks as needed Call clk_prepare_enable() and clk_disable_unprepare() for cpu dai clock and codec dai clock in dai statup and shutdown callbacks. This to make sure the related clock are enabled when the audio device is used. Signed-off-by: Jyri Sarha Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/simple-card.txt | 5 ++++ include/sound/simple_card.h | 1 + sound/soc/generic/simple-card.c | 34 ++++++++++++++++++++++ 3 files changed, 40 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt index c3cba600bf11..73bf314f7240 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-card.txt @@ -75,6 +75,11 @@ Optional CPU/CODEC subnodes properties: it can be specified via "clocks" if system has clock node (= common clock), or "system-clock-frequency" (if system doens't support common clock) + If a clock is specified, it is + enabled with clk_prepare_enable() + in dai startup() and disabled with + clk_disable_unprepare() in dai + shutdown(). Example 1 - single DAI link: diff --git a/include/sound/simple_card.h b/include/sound/simple_card.h index 9b0ac77177b6..1255ddb1d3e2 100644 --- a/include/sound/simple_card.h +++ b/include/sound/simple_card.h @@ -20,6 +20,7 @@ struct asoc_simple_dai { unsigned int sysclk; int slots; int slot_width; + struct clk *clk; }; struct asoc_simple_card_info { diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index fb9240fdc9b7..cb3998d96cca 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -39,6 +39,37 @@ struct simple_card_data { #define simple_priv_to_link(priv, i) ((priv)->snd_card.dai_link + i) #define simple_priv_to_props(priv, i) ((priv)->dai_props + i) +static int asoc_simple_card_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct simple_card_data *priv = snd_soc_card_get_drvdata(rtd->card); + struct simple_dai_props *dai_props = + &priv->dai_props[rtd - rtd->card->rtd]; + int ret; + + ret = clk_prepare_enable(dai_props->cpu_dai.clk); + if (ret) + return ret; + + ret = clk_prepare_enable(dai_props->codec_dai.clk); + if (ret) + clk_disable_unprepare(dai_props->cpu_dai.clk); + + return ret; +} + +static void asoc_simple_card_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct simple_card_data *priv = snd_soc_card_get_drvdata(rtd->card); + struct simple_dai_props *dai_props = + &priv->dai_props[rtd - rtd->card->rtd]; + + clk_disable_unprepare(dai_props->cpu_dai.clk); + + clk_disable_unprepare(dai_props->codec_dai.clk); +} + static int asoc_simple_card_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { @@ -58,6 +89,8 @@ static int asoc_simple_card_hw_params(struct snd_pcm_substream *substream, } static struct snd_soc_ops asoc_simple_card_ops = { + .startup = asoc_simple_card_startup, + .shutdown = asoc_simple_card_shutdown, .hw_params = asoc_simple_card_hw_params, }; @@ -219,6 +252,7 @@ asoc_simple_card_sub_parse_of(struct device_node *np, } dai->sysclk = clk_get_rate(clk); + dai->clk = clk; } else if (!of_property_read_u32(np, "system-clock-frequency", &val)) { dai->sysclk = val; } else { -- cgit v1.2.3 From f04b1e760a51120f358826d815d12c3f8ecdf1b4 Mon Sep 17 00:00:00 2001 From: Thomas Niederprüm Date: Thu, 22 Jan 2015 00:01:58 +0100 Subject: ASoC: sta32x: add device tree binding. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit make the sta32x driver usable with device tree configs. Code is heavily based on the sta350 driver. Signed-off-by: Thomas Niederprüm Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/st,sta32x.txt | 92 ++++++++++++++++++ include/sound/sta32x.h | 18 +++- sound/soc/codecs/sta32x.c | 108 ++++++++++++++++++++- 3 files changed, 211 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/st,sta32x.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/st,sta32x.txt b/Documentation/devicetree/bindings/sound/st,sta32x.txt new file mode 100644 index 000000000000..255de3ae5b2f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/st,sta32x.txt @@ -0,0 +1,92 @@ +STA32X audio CODEC + +The driver for this device only supports I2C. + +Required properties: + + - compatible: "st,sta32x" + - reg: the I2C address of the device for I2C + - reset-gpios: a GPIO spec for the reset pin. If specified, it will be + deasserted before communication to the codec starts. + + - power-down-gpios: a GPIO spec for the power down pin. If specified, + it will be deasserted before communication to the codec + starts. + + - Vdda-supply: regulator spec, providing 3.3V + - Vdd3-supply: regulator spec, providing 3.3V + - Vcc-supply: regulator spec, providing 5V - 26V + +Optional properties: + + - st,output-conf: number, Selects the output configuration: + 0: 2-channel (full-bridge) power, 2-channel data-out + 1: 2 (half-bridge). 1 (full-bridge) on-board power + 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX + 3: 1 Channel Mono-Parallel + If parameter is missing, mode 0 will be enabled. + This property has to be specified as '/bits/ 8' value. + + - st,ch1-output-mapping: Channel 1 output mapping + - st,ch2-output-mapping: Channel 2 output mapping + - st,ch3-output-mapping: Channel 3 output mapping + 0: Channel 1 + 1: Channel 2 + 2: Channel 3 + If parameter is missing, channel 1 is chosen. + This properties have to be specified as '/bits/ 8' values. + + - st,thermal-warning-recover: + If present, thermal warning recovery is enabled. + + - st,thermal-warning-adjustment: + If present, thermal warning adjustment is enabled. + + - st,fault-detect-recovery: + If present, then fault recovery will be enabled. + + - st,drop-compensation-ns: number + Only required for "st,ffx-power-output-mode" == + "variable-drop-compensation". + Specifies the drop compensation in nanoseconds. + The value must be in the range of 0..300, and only + multiples of 20 are allowed. Default is 140ns. + + - st,max-power-use-mpcc: + If present, then MPCC bits are used for MPC coefficients, + otherwise standard MPC coefficients are used. + + - st,max-power-corr: + If present, power bridge correction for THD reduction near maximum + power output is enabled. + + - st,am-reduction-mode: + If present, FFX mode runs in AM reduction mode, otherwise normal + FFX mode is used. + + - st,odd-pwm-speed-mode: + If present, PWM speed mode run on odd speed mode (341.3 kHz) on all + channels. If not present, normal PWM spped mode (384 kHz) will be used. + + - st,invalid-input-detect-mute: + If present, automatic invalid input detect mute is enabled. + +Example: + +codec: sta32x@38 { + compatible = "st,sta32x"; + reg = <0x1c>; + reset-gpios = <&gpio1 19 0>; + power-down-gpios = <&gpio1 16 0>; + st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel + // (full-bridge) power, + // 2-channel data-out + st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1 + st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1 + st,ch3-output-mapping = /bits/ 8 <0>; // set channel 3 output ch 1 + st,max-power-correction; // enables power bridge + // correction for THD reduction + // near maximum power output + st,invalid-input-detect-mute; // mute if no valid digital + // audio signal is provided. +}; diff --git a/include/sound/sta32x.h b/include/sound/sta32x.h index 8d93b0357a14..a894f7d17b1a 100644 --- a/include/sound/sta32x.h +++ b/include/sound/sta32x.h @@ -24,12 +24,20 @@ #define STA32X_THERMAL_RECOVERY_ENABLE 2 struct sta32x_platform_data { - int output_conf; - int ch1_output_mapping; - int ch2_output_mapping; - int ch3_output_mapping; - int thermal_conf; + u8 output_conf; + u8 ch1_output_mapping; + u8 ch2_output_mapping; + u8 ch3_output_mapping; int needs_esd_watchdog; + u8 drop_compensation_ns; + unsigned int thermal_warning_recovery:1; + unsigned int thermal_warning_adjustment:1; + unsigned int fault_detect_recovery:1; + unsigned int max_power_use_mpcc:1; + unsigned int max_power_correction:1; + unsigned int am_reduction_mode:1; + unsigned int odd_pwm_speed_mode:1; + unsigned int invalid_input_detect_mute:1; }; #endif /* __LINUX_SND__STA32X_H */ diff --git a/sound/soc/codecs/sta32x.c b/sound/soc/codecs/sta32x.c index ec2372498c92..669b67f8cee3 100644 --- a/sound/soc/codecs/sta32x.c +++ b/sound/soc/codecs/sta32x.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include #include @@ -893,15 +895,49 @@ static int sta32x_probe(struct snd_soc_codec *codec) dev_err(codec->dev, "Failed to startup device\n"); return ret; } - /* set thermal warning adjustment and recovery */ + + /* CONFA */ if (!pdata->thermal_warning_recovery) thermal |= STA32X_CONFA_TWAB; if (!pdata->thermal_warning_adjustment) thermal |= STA32X_CONFA_TWRB; + if (!pdata->fault_detect_recovery) + thermal |= STA32X_CONFA_FDRB; regmap_update_bits(sta32x->regmap, STA32X_CONFA, - STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, + STA32X_CONFA_TWAB | STA32X_CONFA_TWRB | + STA32X_CONFA_FDRB, thermal); + /* CONFC */ + regmap_update_bits(sta32x->regmap, STA32X_CONFC, + STA32X_CONFC_CSZ_MASK, + pdata->drop_compensation_ns + << STA32X_CONFC_CSZ_SHIFT); + + /* CONFE */ + regmap_update_bits(sta32x->regmap, STA32X_CONFE, + STA32X_CONFE_MPCV, + pdata->max_power_use_mpcc ? + STA32X_CONFE_MPCV : 0); + regmap_update_bits(sta32x->regmap, STA32X_CONFE, + STA32X_CONFE_MPC, + pdata->max_power_correction ? + STA32X_CONFE_MPC : 0); + regmap_update_bits(sta32x->regmap, STA32X_CONFE, + STA32X_CONFE_AME, + pdata->am_reduction_mode ? + STA32X_CONFE_AME : 0); + regmap_update_bits(sta32x->regmap, STA32X_CONFE, + STA32X_CONFE_PWMS, + pdata->odd_pwm_speed_mode ? + STA32X_CONFE_PWMS : 0); + + /* CONFF */ + regmap_update_bits(sta32x->regmap, STA32X_CONFF, + STA32X_CONFF_IDE, + pdata->invalid_input_detect_mute ? + STA32X_CONFF_IDE : 0); + /* select output configuration */ regmap_update_bits(sta32x->regmap, STA32X_CONFF, STA32X_CONFF_OCFG_MASK, @@ -977,7 +1013,66 @@ static const struct regmap_config sta32x_regmap = { .rd_table = &sta32x_read_regs, .volatile_table = &sta32x_volatile_regs, }; + +#ifdef CONFIG_OF +static const struct of_device_id st32x_dt_ids[] = { + { .compatible = "st,sta32x", }, + { } }; +MODULE_DEVICE_TABLE(of, st32x_dt_ids); + +static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x) +{ + struct device_node *np = dev->of_node; + struct sta32x_platform_data *pdata; + u16 tmp; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + of_property_read_u8(np, "st,output-conf", + &pdata->output_conf); + of_property_read_u8(np, "st,ch1-output-mapping", + &pdata->ch1_output_mapping); + of_property_read_u8(np, "st,ch2-output-mapping", + &pdata->ch2_output_mapping); + of_property_read_u8(np, "st,ch3-output-mapping", + &pdata->ch3_output_mapping); + + if (of_get_property(np, "st,thermal-warning-recovery", NULL)) + pdata->thermal_warning_recovery = 1; + if (of_get_property(np, "st,thermal-warning-adjustment", NULL)) + pdata->thermal_warning_adjustment = 1; + if (of_get_property(np, "st,needs_esd_watchdog", NULL)) + pdata->needs_esd_watchdog = 1; + + tmp = 140; + of_property_read_u16(np, "st,drop-compensation-ns", &tmp); + pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20; + + /* CONFE */ + if (of_get_property(np, "st,max-power-use-mpcc", NULL)) + pdata->max_power_use_mpcc = 1; + + if (of_get_property(np, "st,max-power-correction", NULL)) + pdata->max_power_correction = 1; + + if (of_get_property(np, "st,am-reduction-mode", NULL)) + pdata->am_reduction_mode = 1; + + if (of_get_property(np, "st,odd-pwm-speed-mode", NULL)) + pdata->odd_pwm_speed_mode = 1; + + /* CONFF */ + if (of_get_property(np, "st,invalid-input-detect-mute", NULL)) + pdata->invalid_input_detect_mute = 1; + + sta32x->pdata = pdata; + + return 0; +} +#endif static int sta32x_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) @@ -994,6 +1089,14 @@ static int sta32x_i2c_probe(struct i2c_client *i2c, mutex_init(&sta32x->coeff_lock); sta32x->pdata = dev_get_platdata(dev); +#ifdef CONFIG_OF + if (dev->of_node) { + ret = sta32x_probe_dt(dev, sta32x); + if (ret < 0) + return ret; + } +#endif + /* GPIOs */ sta32x->gpiod_nreset = devm_gpiod_get(dev, "reset"); if (IS_ERR(sta32x->gpiod_nreset)) { @@ -1051,6 +1154,7 @@ static struct i2c_driver sta32x_i2c_driver = { .driver = { .name = "sta32x", .owner = THIS_MODULE, + .of_match_table = of_match_ptr(st32x_dt_ids), }, .probe = sta32x_i2c_probe, .remove = sta32x_i2c_remove, -- cgit v1.2.3 From 39552d7ad1409d07ef278a97adbfbee02a272d25 Mon Sep 17 00:00:00 2001 From: Anatol Pomozov Date: Thu, 22 Jan 2015 15:47:24 -0800 Subject: ASoC: ts3a227e: Add dts property that allows to specify micbias voltage The voltage controls key press threshold. Signed-off-by: Anatol Pomozov Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/ts3a227e.txt | 5 ++++ sound/soc/codecs/ts3a227e.c | 27 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ts3a227e.txt b/Documentation/devicetree/bindings/sound/ts3a227e.txt index e8bf23eb1803..a836881d9608 100644 --- a/Documentation/devicetree/bindings/sound/ts3a227e.txt +++ b/Documentation/devicetree/bindings/sound/ts3a227e.txt @@ -13,6 +13,11 @@ Required properties: - interrupt-parent: The parent interrupt controller - interrupts: Interrupt number for /INT pin from the 227e +Optional properies: + - ti,micbias: Intended MICBIAS voltage (datasheet section 9.6.7). + Select 0/1/2/3/4/5/6/7 to specify MACBIAS voltage + 2.1V/2.2V/2.3V/2.4V/2.5V/2.6V/2.7V/2.8V + Default value is "1" (2.2V). Examples: diff --git a/sound/soc/codecs/ts3a227e.c b/sound/soc/codecs/ts3a227e.c index b55034f63de5..65f8ec2094fb 100644 --- a/sound/soc/codecs/ts3a227e.c +++ b/sound/soc/codecs/ts3a227e.c @@ -79,6 +79,10 @@ static const int ts3a227e_buttons[] = { /* TS3A227E_REG_SETTING_2 0x05 */ #define KP_ENABLE 0x04 +/* TS3A227E_REG_SETTING_3 0x06 */ +#define MICBIAS_SETTING_SFT (3) +#define MICBIAS_SETTING_MASK (0x7 << MICBIAS_SETTING_SFT) + /* TS3A227E_REG_ACCESSORY_STATUS 0x0b */ #define TYPE_3_POLE 0x01 #define TYPE_4_POLE_OMTP 0x02 @@ -248,6 +252,21 @@ static const struct regmap_config ts3a227e_regmap_config = { .num_reg_defaults = ARRAY_SIZE(ts3a227e_reg_defaults), }; +static int ts3a227e_parse_dt(struct ts3a227e *ts3a227e, struct device_node *np) +{ + u32 micbias; + int err; + + err = of_property_read_u32(np, "ti,micbias", &micbias); + if (!err) { + regmap_update_bits(ts3a227e->regmap, TS3A227E_REG_SETTING_3, + MICBIAS_SETTING_MASK, + (micbias & 0x07) << MICBIAS_SETTING_SFT); + } + + return 0; +} + static int ts3a227e_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { @@ -265,6 +284,14 @@ static int ts3a227e_i2c_probe(struct i2c_client *i2c, if (IS_ERR(ts3a227e->regmap)) return PTR_ERR(ts3a227e->regmap); + if (dev->of_node) { + ret = ts3a227e_parse_dt(ts3a227e, dev->of_node); + if (ret) { + dev_err(dev, "Failed to parse device tree: %d\n", ret); + return ret; + } + } + ret = devm_request_threaded_irq(dev, i2c->irq, NULL, ts3a227e_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, "TS3A227E", ts3a227e); -- cgit v1.2.3 From f086ba9d5389cc9a309958c9e7c92460f1cfca5e Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Wed, 28 Jan 2015 15:16:10 +0100 Subject: ASoC: pcm512x: Support mastering BCLK/LRCLK using the PLL Using the PLL in master mode requires using an external connection between one of the GPIO pins (configured as PLL/4 output) and the SCK pin. It also requires the external clock to be fed to some other GPIO pin instead of the SCK pin. This is described for the PCM5122 chip in the answers to the forum post "PCM5122 DAC as I2S master troubles with PLL mode" at the TI E2E community pages (1). The clocking functionality is also much better described in the datasheet for the chip PCM5242, which seems to be register compatible with PCM512x and PCM514x (which both have severely lacking datasheets). (1) http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/267830 Signed-off-by: Peter Rosin Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/pcm512x.txt | 25 +- sound/soc/codecs/pcm512x.c | 458 +++++++++++++++++++-- sound/soc/codecs/pcm512x.h | 44 +- 3 files changed, 501 insertions(+), 26 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt index 98e0d34915e8..3aae3b41bd8e 100644 --- a/Documentation/devicetree/bindings/sound/pcm512x.txt +++ b/Documentation/devicetree/bindings/sound/pcm512x.txt @@ -17,9 +17,16 @@ Required properties: Optional properties: - clocks : A clock specifier for the clock connected as SCLK. If this - is absent the device will be configured to clock from BCLK. + is absent the device will be configured to clock from BCLK. If pll-in + and pll-out are specified in addition to a clock, the device is + configured to accept clock input on a specified gpio pin. -Example: + - pll-in, pll-out : gpio pins used to connect the pll using <1> + through <6>. The device will be configured for clock input on the + given pll-in pin and PLL output on the given pll-out pin. An + external connection from the pll-out pin to the SCLK pin is assumed. + +Examples: pcm5122: pcm5122@4c { compatible = "ti,pcm5122"; @@ -29,3 +36,17 @@ Example: DVDD-supply = <®_1v8>; CPVDD-supply = <®_3v3>; }; + + + pcm5142: pcm5142@4c { + compatible = "ti,pcm5142"; + reg = <0x4c>; + + AVDD-supply = <®_3v3_analog>; + DVDD-supply = <®_1v8>; + CPVDD-supply = <®_3v3>; + + clocks = <&sck>; + pll-in = <3>; + pll-out = <6>; + }; diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c index 526e6b30cdde..66dd036f0141 100644 --- a/sound/soc/codecs/pcm512x.c +++ b/sound/soc/codecs/pcm512x.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,11 @@ #include "pcm512x.h" +#define DIV_ROUND_DOWN_ULL(ll, d) \ + ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) +#define DIV_ROUND_CLOSEST_ULL(ll, d) \ + ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) + #define PCM512x_NUM_SUPPLIES 3 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { "AVDD", @@ -41,6 +47,13 @@ struct pcm512x_priv { struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; int fmt; + int pll_in; + int pll_out; + int pll_r; + int pll_j; + int pll_d; + int pll_p; + unsigned long real_pll; }; /* @@ -92,7 +105,13 @@ static const struct reg_default pcm512x_reg_defaults[] = { { PCM512x_VCOM_CTRL_2, 0x01 }, { PCM512x_BCLK_LRCLK_CFG, 0x00 }, { PCM512x_MASTER_MODE, 0x7c }, + { PCM512x_GPIO_PLLIN, 0x00 }, { PCM512x_SYNCHRONIZE, 0x10 }, + { PCM512x_PLL_COEFF_0, 0x00 }, + { PCM512x_PLL_COEFF_1, 0x00 }, + { PCM512x_PLL_COEFF_2, 0x00 }, + { PCM512x_PLL_COEFF_3, 0x00 }, + { PCM512x_PLL_COEFF_4, 0x00 }, { PCM512x_DSP_CLKDIV, 0x00 }, { PCM512x_DAC_CLKDIV, 0x00 }, { PCM512x_NCP_CLKDIV, 0x00 }, @@ -119,6 +138,7 @@ static bool pcm512x_readable(struct device *dev, unsigned int reg) case PCM512x_MASTER_MODE: case PCM512x_PLL_REF: case PCM512x_DAC_REF: + case PCM512x_GPIO_PLLIN: case PCM512x_SYNCHRONIZE: case PCM512x_PLL_COEFF_0: case PCM512x_PLL_COEFF_1: @@ -160,6 +180,7 @@ static bool pcm512x_readable(struct device *dev, unsigned int reg) case PCM512x_RATE_DET_2: case PCM512x_RATE_DET_3: case PCM512x_RATE_DET_4: + case PCM512x_CLOCK_STATUS: case PCM512x_ANALOG_MUTE_DET: case PCM512x_GPIN: case PCM512x_DIGITAL_MUTE_DET: @@ -171,6 +192,8 @@ static bool pcm512x_readable(struct device *dev, unsigned int reg) case PCM512x_VCOM_CTRL_1: case PCM512x_VCOM_CTRL_2: case PCM512x_CRAM_CTRL: + case PCM512x_FLEX_A: + case PCM512x_FLEX_B: return true; default: /* There are 256 raw register addresses */ @@ -187,6 +210,7 @@ static bool pcm512x_volatile(struct device *dev, unsigned int reg) case PCM512x_RATE_DET_2: case PCM512x_RATE_DET_3: case PCM512x_RATE_DET_4: + case PCM512x_CLOCK_STATUS: case PCM512x_ANALOG_MUTE_DET: case PCM512x_GPIN: case PCM512x_DIGITAL_MUTE_DET: @@ -330,6 +354,38 @@ static const struct snd_pcm_hw_constraint_list constraints_slave = { .list = pcm512x_dai_rates, }; +static const struct snd_interval pcm512x_dai_ranges_64bpf[] = { + { + .min = 8000, + .max = 195312, + }, { + .min = 250000, + .max = 390625, + }, +}; + +static struct snd_pcm_hw_constraint_ranges constraints_64bpf = { + .count = ARRAY_SIZE(pcm512x_dai_ranges_64bpf), + .ranges = pcm512x_dai_ranges_64bpf, +}; + +static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule) +{ + struct snd_pcm_hw_constraint_ranges *r = rule->private; + int frame_size; + + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) + return frame_size; + + if (frame_size != 64) + return 0; + + return snd_interval_ranges(hw_param_interval(params, rule->var), + r->count, r->ranges, r->mask); +} + static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { @@ -345,6 +401,14 @@ static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, return PTR_ERR(pcm512x->sclk); } + if (pcm512x->pll_out) + return snd_pcm_hw_rule_add(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + pcm512x_hw_rule_rate, + (void *)&constraints_64bpf, + SNDRV_PCM_HW_PARAM_FRAME_BITS, + SNDRV_PCM_HW_PARAM_CHANNELS, -1); + constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), GFP_KERNEL); if (!constraints_no_pll) @@ -445,12 +509,164 @@ static int pcm512x_set_bias_level(struct snd_soc_codec *codec, return 0; } +static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, + unsigned long bclk_rate) +{ + struct device *dev = dai->dev; + unsigned long sck_rate; + int pow2; + + /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ + /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ + + /* select sck_rate as a multiple of bclk_rate but still with + * as many factors of 2 as possible, as that makes it easier + * to find a fast DAC rate + */ + pow2 = 1 << fls((25000000 - 16000000) / bclk_rate); + for (; pow2; pow2 >>= 1) { + sck_rate = rounddown(25000000, bclk_rate * pow2); + if (sck_rate >= 16000000) + break; + } + if (!pow2) { + dev_err(dev, "Impossible to generate a suitable SCK\n"); + return 0; + } + + dev_dbg(dev, "sck_rate %lu\n", sck_rate); + return sck_rate; +} + +/* pll_rate = pllin_rate * R * J.D / P + * 1 <= R <= 16 + * 1 <= J <= 63 + * 0 <= D <= 9999 + * 1 <= P <= 15 + * 64 MHz <= pll_rate <= 100 MHz + * if D == 0 + * 1 MHz <= pllin_rate / P <= 20 MHz + * else if D > 0 + * 6.667 MHz <= pllin_rate / P <= 20 MHz + * 4 <= J <= 11 + * R = 1 + */ +static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, + unsigned long pllin_rate, + unsigned long pll_rate) +{ + struct device *dev = dai->dev; + struct snd_soc_codec *codec = dai->codec; + struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); + unsigned long common; + int R, J, D, P; + unsigned long K; /* 10000 * J.D */ + unsigned long num; + unsigned long den; + + common = gcd(pll_rate, pllin_rate); + dev_dbg(dev, "pll %lu pllin %lu common %lu\n", + pll_rate, pllin_rate, common); + num = pll_rate / common; + den = pllin_rate / common; + + /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ + if (pllin_rate / den > 20000000 && num < 8) { + num *= 20000000 / (pllin_rate / den); + den *= 20000000 / (pllin_rate / den); + } + dev_dbg(dev, "num / den = %lu / %lu\n", num, den); + + P = den; + if (den <= 15 && num <= 16 * 63 + && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { + /* Try the case with D = 0 */ + D = 0; + /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ + for (R = 16; R; R--) { + if (num % R) + continue; + J = num / R; + if (J == 0 || J > 63) + continue; + + dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); + pcm512x->real_pll = pll_rate; + goto done; + } + /* no luck */ + } + + R = 1; + + if (num > 0xffffffffUL / 10000) + goto fallback; + + /* Try to find an exact pll_rate using the D > 0 case */ + common = gcd(10000 * num, den); + num = 10000 * num / common; + den /= common; + dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); + + for (P = den; P <= 15; P++) { + if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) + continue; + if (num * P % den) + continue; + K = num * P / den; + /* J == 12 is ok if D == 0 */ + if (K < 40000 || K > 120000) + continue; + + J = K / 10000; + D = K % 10000; + dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); + pcm512x->real_pll = pll_rate; + goto done; + } + + /* Fall back to an approximate pll_rate */ + +fallback: + /* find smallest possible P */ + P = DIV_ROUND_UP(pllin_rate, 20000000); + if (!P) + P = 1; + else if (P > 15) { + dev_err(dev, "Need a slower clock as pll-input\n"); + return -EINVAL; + } + if (pllin_rate / P < 6667000) { + dev_err(dev, "Need a faster clock as pll-input\n"); + return -EINVAL; + } + K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); + if (K < 40000) + K = 40000; + /* J == 12 is ok if D == 0 */ + if (K > 120000) + K = 120000; + J = K / 10000; + D = K % 10000; + dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); + pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); + +done: + pcm512x->pll_r = R; + pcm512x->pll_j = J; + pcm512x->pll_d = D; + pcm512x->pll_p = P; + return 0; +} + static int pcm512x_set_dividers(struct snd_soc_dai *dai, struct snd_pcm_hw_params *params) { struct device *dev = dai->dev; struct snd_soc_codec *codec = dai->codec; struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); + unsigned long pllin_rate = 0; + unsigned long pll_rate; unsigned long sck_rate; unsigned long mck_rate; unsigned long bclk_rate; @@ -475,11 +691,74 @@ static int pcm512x_set_dividers(struct snd_soc_dai *dai, return -EINVAL; } - sck_rate = clk_get_rate(pcm512x->sclk); - bclk_div = params->rate_den * 64 / lrclk_div; - bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); + if (!pcm512x->pll_out) { + sck_rate = clk_get_rate(pcm512x->sclk); + bclk_div = params->rate_den * 64 / lrclk_div; + bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); - mck_rate = sck_rate; + mck_rate = sck_rate; + } else { + ret = snd_soc_params_to_bclk(params); + if (ret < 0) { + dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); + return ret; + } + if (ret == 0) { + dev_err(dev, "No BCLK?\n"); + return -EINVAL; + } + bclk_rate = ret; + + pllin_rate = clk_get_rate(pcm512x->sclk); + + sck_rate = pcm512x_find_sck(dai, bclk_rate); + if (!sck_rate) + return -EINVAL; + pll_rate = 4 * sck_rate; + + ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); + if (ret != 0) + return ret; + + ret = regmap_write(pcm512x->regmap, + PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); + if (ret != 0) { + dev_err(dev, "Failed to write PLL P: %d\n", ret); + return ret; + } + + ret = regmap_write(pcm512x->regmap, + PCM512x_PLL_COEFF_1, pcm512x->pll_j); + if (ret != 0) { + dev_err(dev, "Failed to write PLL J: %d\n", ret); + return ret; + } + + ret = regmap_write(pcm512x->regmap, + PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); + if (ret != 0) { + dev_err(dev, "Failed to write PLL D msb: %d\n", ret); + return ret; + } + + ret = regmap_write(pcm512x->regmap, + PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); + if (ret != 0) { + dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); + return ret; + } + + ret = regmap_write(pcm512x->regmap, + PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); + if (ret != 0) { + dev_err(dev, "Failed to write PLL R: %d\n", ret); + return ret; + } + + mck_rate = pcm512x->real_pll; + + bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); + } if (bclk_div > 128) { dev_err(dev, "Failed to find BCLK divider\n"); @@ -616,6 +895,7 @@ static int pcm512x_hw_params(struct snd_pcm_substream *substream, struct snd_soc_codec *codec = dai->codec; struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); int alen; + int gpio; int ret; dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n", @@ -676,26 +956,55 @@ static int pcm512x_hw_params(struct snd_pcm_substream *substream, return ret; } - ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, - PCM512x_IDFS | PCM512x_IDBK - | PCM512x_IDSK | PCM512x_IDCH - | PCM512x_IDCM | PCM512x_DCAS - | PCM512x_IPLK, - PCM512x_IDFS | PCM512x_IDBK - | PCM512x_IDSK | PCM512x_IDCH - | PCM512x_DCAS | PCM512x_IPLK); - if (ret != 0) { - dev_err(codec->dev, - "Failed to ignore auto-clock failures: %d\n", - ret); - return ret; - } + if (pcm512x->pll_out) { + ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); + if (ret != 0) { + dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret); + return ret; + } - ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, - PCM512x_PLLE, 0); - if (ret != 0) { - dev_err(codec->dev, "Failed to disable pll: %d\n", ret); - return ret; + ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); + if (ret != 0) { + dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret); + return ret; + } + + ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, + PCM512x_IDFS | PCM512x_IDBK + | PCM512x_IDSK | PCM512x_IDCH + | PCM512x_IDCM | PCM512x_DCAS + | PCM512x_IPLK, + PCM512x_IDFS | PCM512x_IDBK + | PCM512x_IDSK | PCM512x_IDCH + | PCM512x_DCAS); + if (ret != 0) { + dev_err(codec->dev, + "Failed to ignore auto-clock failures: %d\n", + ret); + return ret; + } + } else { + ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, + PCM512x_IDFS | PCM512x_IDBK + | PCM512x_IDSK | PCM512x_IDCH + | PCM512x_IDCM | PCM512x_DCAS + | PCM512x_IPLK, + PCM512x_IDFS | PCM512x_IDBK + | PCM512x_IDSK | PCM512x_IDCH + | PCM512x_DCAS | PCM512x_IPLK); + if (ret != 0) { + dev_err(codec->dev, + "Failed to ignore auto-clock failures: %d\n", + ret); + return ret; + } + + ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, + PCM512x_PLLE, 0); + if (ret != 0) { + dev_err(codec->dev, "Failed to disable pll: %d\n", ret); + return ret; + } } ret = pcm512x_set_dividers(dai, params); @@ -709,6 +1018,33 @@ static int pcm512x_hw_params(struct snd_pcm_substream *substream, return ret; } + if (pcm512x->pll_out) { + ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, + PCM512x_SREF, PCM512x_SREF_GPIO); + if (ret != 0) { + dev_err(codec->dev, + "Failed to set gpio as pllref: %d\n", ret); + return ret; + } + + gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; + ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, + PCM512x_GREF, gpio); + if (ret != 0) { + dev_err(codec->dev, + "Failed to set gpio %d as pllin: %d\n", + pcm512x->pll_in, ret); + return ret; + } + + ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, + PCM512x_PLLE, PCM512x_PLLE); + if (ret != 0) { + dev_err(codec->dev, "Failed to enable pll: %d\n", ret); + return ret; + } + } + ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, PCM512x_BCKO | PCM512x_LRKO); @@ -725,6 +1061,45 @@ static int pcm512x_hw_params(struct snd_pcm_substream *substream, return ret; } + if (pcm512x->pll_out) { + gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); + ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, + gpio, gpio); + if (ret != 0) { + dev_err(codec->dev, "Failed to enable gpio %d: %d\n", + pcm512x->pll_out, ret); + return ret; + } + + gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; + ret = regmap_update_bits(pcm512x->regmap, gpio, + PCM512x_GxSL, PCM512x_GxSL_PLLCK); + if (ret != 0) { + dev_err(codec->dev, "Failed to output pll on %d: %d\n", + ret, pcm512x->pll_out); + return ret; + } + + gpio = PCM512x_G1OE << (4 - 1); + ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, + gpio, gpio); + if (ret != 0) { + dev_err(codec->dev, "Failed to enable gpio %d: %d\n", + 4, ret); + return ret; + } + + gpio = PCM512x_GPIO_OUTPUT_1 + 4 - 1; + ret = regmap_update_bits(pcm512x->regmap, gpio, + PCM512x_GxSL, PCM512x_GxSL_PLLLK); + if (ret != 0) { + dev_err(codec->dev, + "Failed to output pll lock on %d: %d\n", + ret, 4); + return ret; + } + } + ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, PCM512x_RQSY, PCM512x_RQSY_HALT); if (ret != 0) { @@ -815,6 +1190,7 @@ int pcm512x_probe(struct device *dev, struct regmap *regmap) { struct pcm512x_priv *pcm512x; int i, ret; + u32 val; pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); if (!pcm512x) @@ -892,6 +1268,42 @@ int pcm512x_probe(struct device *dev, struct regmap *regmap) pm_runtime_enable(dev); pm_runtime_idle(dev); +#ifdef CONFIG_OF + if (dev->of_node) { + const struct device_node *np = dev->of_node; + + if (of_property_read_u32(np, "pll-in", &val) >= 0) { + if (val > 6) { + dev_err(dev, "Invalid pll-in\n"); + ret = -EINVAL; + goto err_clk; + } + pcm512x->pll_in = val; + } + + if (of_property_read_u32(np, "pll-out", &val) >= 0) { + if (val > 6) { + dev_err(dev, "Invalid pll-out\n"); + ret = -EINVAL; + goto err_clk; + } + pcm512x->pll_out = val; + } + + if (!pcm512x->pll_in != !pcm512x->pll_out) { + dev_err(dev, + "Error: both pll-in and pll-out, or none\n"); + ret = -EINVAL; + goto err_clk; + } + if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { + dev_err(dev, "Error: pll-in == pll-out\n"); + ret = -EINVAL; + goto err_clk; + } + } +#endif + ret = snd_soc_register_codec(dev, &pcm512x_codec_driver, &pcm512x_dai, 1); if (ret != 0) { diff --git a/sound/soc/codecs/pcm512x.h b/sound/soc/codecs/pcm512x.h index fa538d5aabf2..eba5adc2cdb1 100644 --- a/sound/soc/codecs/pcm512x.h +++ b/sound/soc/codecs/pcm512x.h @@ -38,6 +38,7 @@ #define PCM512x_MASTER_MODE (PCM512x_PAGE_BASE(0) + 12) #define PCM512x_PLL_REF (PCM512x_PAGE_BASE(0) + 13) #define PCM512x_DAC_REF (PCM512x_PAGE_BASE(0) + 14) +#define PCM512x_GPIO_PLLIN (PCM512x_PAGE_BASE(0) + 18) #define PCM512x_SYNCHRONIZE (PCM512x_PAGE_BASE(0) + 19) #define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_BASE(0) + 20) #define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_BASE(0) + 21) @@ -79,6 +80,7 @@ #define PCM512x_RATE_DET_2 (PCM512x_PAGE_BASE(0) + 92) #define PCM512x_RATE_DET_3 (PCM512x_PAGE_BASE(0) + 93) #define PCM512x_RATE_DET_4 (PCM512x_PAGE_BASE(0) + 94) +#define PCM512x_CLOCK_STATUS (PCM512x_PAGE_BASE(0) + 95) #define PCM512x_ANALOG_MUTE_DET (PCM512x_PAGE_BASE(0) + 108) #define PCM512x_GPIN (PCM512x_PAGE_BASE(0) + 119) #define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAGE_BASE(0) + 120) @@ -93,7 +95,10 @@ #define PCM512x_CRAM_CTRL (PCM512x_PAGE_BASE(44) + 1) -#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(44) + 1) +#define PCM512x_FLEX_A (PCM512x_PAGE_BASE(253) + 63) +#define PCM512x_FLEX_B (PCM512x_PAGE_BASE(253) + 64) + +#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(253) + 64) /* Page 0, Register 1 - reset */ #define PCM512x_RSTR (1 << 0) @@ -121,6 +126,14 @@ #define PCM512x_DEMP (1 << 4) #define PCM512x_DEMP_SHIFT 4 +/* Page 0, Register 8 - GPIO output enable */ +#define PCM512x_G1OE (1 << 0) +#define PCM512x_G2OE (1 << 1) +#define PCM512x_G3OE (1 << 2) +#define PCM512x_G4OE (1 << 3) +#define PCM512x_G5OE (1 << 4) +#define PCM512x_G6OE (1 << 5) + /* Page 0, Register 9 - BCK, LRCLK configuration */ #define PCM512x_LRKO (1 << 0) #define PCM512x_LRKO_SHIFT 0 @@ -150,6 +163,16 @@ #define PCM512x_SDAC_SCK (3 << 4) #define PCM512x_SDAC_BCK (4 << 4) +/* Page 0, Register 18 - GPIO source for PLL */ +#define PCM512x_GREF (7 << 0) +#define PCM512x_GREF_SHIFT 0 +#define PCM512x_GREF_GPIO1 (0 << 0) +#define PCM512x_GREF_GPIO2 (1 << 0) +#define PCM512x_GREF_GPIO3 (2 << 0) +#define PCM512x_GREF_GPIO4 (3 << 0) +#define PCM512x_GREF_GPIO5 (4 << 0) +#define PCM512x_GREF_GPIO6 (5 << 0) + /* Page 0, Register 19 - synchronize */ #define PCM512x_RQSY (1 << 0) #define PCM512x_RQSY_RESUME (0 << 0) @@ -209,6 +232,25 @@ #define PCM512x_AMLE_SHIFT 1 #define PCM512x_AMRE_SHIFT 0 +/* Page 0, Register 80-85, GPIO output selection */ +#define PCM512x_GxSL (31 << 0) +#define PCM512x_GxSL_SHIFT 0 +#define PCM512x_GxSL_OFF (0 << 0) +#define PCM512x_GxSL_DSP (1 << 0) +#define PCM512x_GxSL_REG (2 << 0) +#define PCM512x_GxSL_AMUTB (3 << 0) +#define PCM512x_GxSL_AMUTL (4 << 0) +#define PCM512x_GxSL_AMUTR (5 << 0) +#define PCM512x_GxSL_CLKI (6 << 0) +#define PCM512x_GxSL_SDOUT (7 << 0) +#define PCM512x_GxSL_ANMUL (8 << 0) +#define PCM512x_GxSL_ANMUR (9 << 0) +#define PCM512x_GxSL_PLLLK (10 << 0) +#define PCM512x_GxSL_CPCLK (11 << 0) +#define PCM512x_GxSL_UV0_7 (14 << 0) +#define PCM512x_GxSL_UV0_3 (15 << 0) +#define PCM512x_GxSL_PLLCK (16 << 0) + /* Page 1, Register 2 - analog volume control */ #define PCM512x_RAGN_SHIFT 0 #define PCM512x_LAGN_SHIFT 4 -- cgit v1.2.3 From 4d4f175ac68207b0acd3c56c5e969d9d6d2887fb Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 27 Jan 2015 11:36:40 +0800 Subject: ASoC: wm8904: add new compatible string The "wlf,wm8912" compatible string is used for wm8912, which share driver with wm8904, however, the data type is different. Signed-off-by: Bo Shen Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/wm8904.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/wm8904.txt b/Documentation/devicetree/bindings/sound/wm8904.txt index e99f4097c83c..66bf261423b9 100644 --- a/Documentation/devicetree/bindings/sound/wm8904.txt +++ b/Documentation/devicetree/bindings/sound/wm8904.txt @@ -3,7 +3,7 @@ WM8904 audio CODEC This device supports I2C only. Required properties: - - compatible: "wlf,wm8904" + - compatible: "wlf,wm8904" or "wlf,wm8912" - reg: the I2C address of the device. - clock-names: "mclk" - clocks: reference to -- cgit v1.2.3 From 9503112d909cbbc2865a28c2586c436254169da8 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Mon, 2 Feb 2015 16:48:05 +0200 Subject: ASoC: tlv320aic3x: Add support for tlv320aic3104 Disables GPIO support and LINE2 input and renames Mic3 input to Mic2, if tlv320aic3104 mode is seleced. Devicetree binding document is updated accordingly. Signed-off-by: Jyri Sarha Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/tlv320aic3x.txt | 10 +- sound/soc/codecs/tlv320aic3x.c | 345 +++++++++++++++------ 2 files changed, 253 insertions(+), 102 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt index 5e6040c2c2e9..47a213c411ce 100644 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt +++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt @@ -9,6 +9,7 @@ Required properties: "ti,tlv320aic33" - TLV320AIC33 "ti,tlv320aic3007" - TLV320AIC3007 "ti,tlv320aic3106" - TLV320AIC3106 + "ti,tlv320aic3104" - TLV320AIC3104 - reg - - I2C slave address @@ -18,6 +19,7 @@ Optional properties: - gpio-reset - gpio pin number used for codec reset - ai3x-gpio-func - - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality + - Not supported on tlv320aic3104 - ai3x-micbias-vg - MicBias Voltage required. 1 - MICBIAS output is powered to 2.0V, 2 - MICBIAS output is powered to 2.5V, @@ -36,7 +38,13 @@ CODEC output pins: * HPLCOM * HPRCOM -CODEC input pins: +CODEC input pins for TLV320AIC3104: + * MIC2L + * MIC2R + * LINE1L + * LINE1R + +CODEC input pins for other compatible codecs: * MIC3L * MIC3R * LINE1L diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index b7ebce054b4e..cb92cdba0324 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -87,6 +87,7 @@ struct aic3x_priv { #define AIC3X_MODEL_3X 0 #define AIC3X_MODEL_33 1 #define AIC3X_MODEL_3007 2 +#define AIC3X_MODEL_3104 3 u16 model; /* Selects the micbias voltage */ @@ -316,52 +317,37 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = { * only for swapped L-to-R and R-to-L routes. See below stereo controls * for direct L-to-L and R-to-R routes. */ - SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", - LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), - SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", - LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), - SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", - LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), - SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", - LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), - SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", - LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), - SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", - LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), /* Stereo output controls for direct L-to-L and R-to-R routes */ - SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", - LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, - 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), @@ -369,9 +355,6 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = { DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), - SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", - LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, - 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), @@ -379,9 +362,6 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = { DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), - SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", - LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, - 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), @@ -424,6 +404,45 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = { SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum), }; +/* For other than tlv320aic3104 */ +static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = { + /* + * Output controls that map to output mixer switches. Note these are + * only for swapped L-to-R and R-to-L routes. See below stereo controls + * for direct L-to-L and R-to-R routes. + */ + SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", + LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), + + SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", + LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), + + SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", + LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), + + SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", + LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), + + SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", + LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), + + SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", + LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), + + /* Stereo output controls for direct L-to-L and R-to-R routes */ + SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", + LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, + 0, 118, 1, output_stage_tlv), + + SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", + LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, + 0, 118, 1, output_stage_tlv), + + SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", + LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, + 0, 118, 1, output_stage_tlv), +}; + static const struct snd_kcontrol_new aic3x_mono_controls[] = { SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, @@ -464,22 +483,24 @@ SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum); /* Left Line Mixer */ static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { - SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), - SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), + /* Not on tlv320aic3104 */ + SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), + SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), }; /* Right Line Mixer */ static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { - SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), - SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), + /* Not on tlv320aic3104 */ + SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), + SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), }; /* Mono Mixer */ @@ -494,42 +515,46 @@ static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { /* Left HP Mixer */ static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { - SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), - SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), + /* Not on tlv320aic3104 */ + SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), + SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), }; /* Right HP Mixer */ static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { - SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), - SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), + /* Not on tlv320aic3104 */ + SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), + SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), }; /* Left HPCOM Mixer */ static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { - SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), - SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), + /* Not on tlv320aic3104 */ + SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), + SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), }; /* Right HPCOM Mixer */ static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { - SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), - SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), + /* Not on tlv320aic3104 */ + SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), + SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), }; /* Left PGA Mixer */ @@ -550,6 +575,22 @@ static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), }; +/* Left PGA Mixer for tlv320aic3104 */ +static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = { + SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), + SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), + SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), + SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), +}; + +/* Right PGA Mixer for tlv320aic3104 */ +static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = { + SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), + SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), + SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), + SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), +}; + /* Left Line1 Mux */ static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum); @@ -593,26 +634,56 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { /* Inputs to Left ADC */ SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), - SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, - &aic3x_left_pga_mixer_controls[0], - ARRAY_SIZE(aic3x_left_pga_mixer_controls)), SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_line1l_mux_controls), SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_line1r_mux_controls), - SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, - &aic3x_left_line2_mux_controls), /* Inputs to Right ADC */ SND_SOC_DAPM_ADC("Right ADC", "Right Capture", LINE1R_2_RADC_CTRL, 2, 0), - SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, - &aic3x_right_pga_mixer_controls[0], - ARRAY_SIZE(aic3x_right_pga_mixer_controls)), SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_line1l_mux_controls), SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_line1r_mux_controls), + + /* Mic Bias */ + SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, + mic_bias_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_OUTPUT("LLOUT"), + SND_SOC_DAPM_OUTPUT("RLOUT"), + SND_SOC_DAPM_OUTPUT("HPLOUT"), + SND_SOC_DAPM_OUTPUT("HPROUT"), + SND_SOC_DAPM_OUTPUT("HPLCOM"), + SND_SOC_DAPM_OUTPUT("HPRCOM"), + + SND_SOC_DAPM_INPUT("LINE1L"), + SND_SOC_DAPM_INPUT("LINE1R"), + + /* + * Virtual output pin to detection block inside codec. This can be + * used to keep codec bias on if gpio or detection features are needed. + * Force pin on or construct a path with an input jack and mic bias + * widgets. + */ + SND_SOC_DAPM_OUTPUT("Detection"), +}; + +/* For other than tlv320aic3104 */ +static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = { + /* Inputs to Left ADC */ + SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_left_pga_mixer_controls[0], + ARRAY_SIZE(aic3x_left_pga_mixer_controls)), + SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, + &aic3x_left_line2_mux_controls), + + /* Inputs to Right ADC */ + SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_right_pga_mixer_controls[0], + ARRAY_SIZE(aic3x_right_pga_mixer_controls)), SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_line2_mux_controls), @@ -637,11 +708,6 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), - /* Mic Bias */ - SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, - mic_bias_event, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - /* Output mixers */ SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, &aic3x_left_line_mixer_controls[0], @@ -662,27 +728,46 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { &aic3x_right_hpcom_mixer_controls[0], ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), - SND_SOC_DAPM_OUTPUT("LLOUT"), - SND_SOC_DAPM_OUTPUT("RLOUT"), - SND_SOC_DAPM_OUTPUT("HPLOUT"), - SND_SOC_DAPM_OUTPUT("HPROUT"), - SND_SOC_DAPM_OUTPUT("HPLCOM"), - SND_SOC_DAPM_OUTPUT("HPRCOM"), - SND_SOC_DAPM_INPUT("MIC3L"), SND_SOC_DAPM_INPUT("MIC3R"), - SND_SOC_DAPM_INPUT("LINE1L"), - SND_SOC_DAPM_INPUT("LINE1R"), SND_SOC_DAPM_INPUT("LINE2L"), SND_SOC_DAPM_INPUT("LINE2R"), +}; - /* - * Virtual output pin to detection block inside codec. This can be - * used to keep codec bias on if gpio or detection features are needed. - * Force pin on or construct a path with an input jack and mic bias - * widgets. - */ - SND_SOC_DAPM_OUTPUT("Detection"), +/* For tlv320aic3104 */ +static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = { + /* Inputs to Left ADC */ + SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, + &aic3104_left_pga_mixer_controls[0], + ARRAY_SIZE(aic3104_left_pga_mixer_controls)), + + /* Inputs to Right ADC */ + SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, + &aic3104_right_pga_mixer_controls[0], + ARRAY_SIZE(aic3104_right_pga_mixer_controls)), + + /* Output mixers */ + SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_left_line_mixer_controls[0], + ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2), + SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_right_line_mixer_controls[0], + ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2), + SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_left_hp_mixer_controls[0], + ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2), + SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_right_hp_mixer_controls[0], + ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2), + SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_left_hpcom_mixer_controls[0], + ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2), + SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, + &aic3x_right_hpcom_mixer_controls[0], + ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2), + + SND_SOC_DAPM_INPUT("MIC2L"), + SND_SOC_DAPM_INPUT("MIC2R"), }; static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = { @@ -712,17 +797,10 @@ static const struct snd_soc_dapm_route intercon[] = { {"Left Line1R Mux", "single-ended", "LINE1R"}, {"Left Line1R Mux", "differential", "LINE1R"}, - {"Left Line2L Mux", "single-ended", "LINE2L"}, - {"Left Line2L Mux", "differential", "LINE2L"}, - {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, - {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, - {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, - {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, {"Left ADC", NULL, "Left PGA Mixer"}, - {"Left ADC", NULL, "GPIO1 dmic modclk"}, /* Right Input */ {"Right Line1R Mux", "single-ended", "LINE1R"}, @@ -730,25 +808,10 @@ static const struct snd_soc_dapm_route intercon[] = { {"Right Line1L Mux", "single-ended", "LINE1L"}, {"Right Line1L Mux", "differential", "LINE1L"}, - {"Right Line2R Mux", "single-ended", "LINE2R"}, - {"Right Line2R Mux", "differential", "LINE2R"}, - {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, - {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, - {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, - {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, {"Right ADC", NULL, "Right PGA Mixer"}, - {"Right ADC", NULL, "GPIO1 dmic modclk"}, - - /* - * Logical path between digital mic enable and GPIO1 modulator clock - * output function - */ - {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, - {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, - {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, /* Left DAC Output */ {"Left DAC Mux", "DAC_L1", "Left DAC"}, @@ -761,10 +824,8 @@ static const struct snd_soc_dapm_route intercon[] = { {"Right DAC Mux", "DAC_R3", "Right DAC"}, /* Left Line Output */ - {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, - {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, @@ -773,10 +834,8 @@ static const struct snd_soc_dapm_route intercon[] = { {"LLOUT", NULL, "Left Line Out"}, /* Right Line Output */ - {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, - {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, @@ -785,10 +844,8 @@ static const struct snd_soc_dapm_route intercon[] = { {"RLOUT", NULL, "Right Line Out"}, /* Left HP Output */ - {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, - {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, @@ -797,10 +854,8 @@ static const struct snd_soc_dapm_route intercon[] = { {"HPLOUT", NULL, "Left HP Out"}, /* Right HP Output */ - {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, - {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, @@ -809,10 +864,8 @@ static const struct snd_soc_dapm_route intercon[] = { {"HPROUT", NULL, "Right HP Out"}, /* Left HPCOM Output */ - {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, - {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, @@ -823,10 +876,8 @@ static const struct snd_soc_dapm_route intercon[] = { {"HPLCOM", NULL, "Left HP Com"}, /* Right HPCOM Output */ - {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, - {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, @@ -839,6 +890,72 @@ static const struct snd_soc_dapm_route intercon[] = { {"HPRCOM", NULL, "Right HP Com"}, }; +/* For other than tlv320aic3104 */ +static const struct snd_soc_dapm_route intercon_extra[] = { + /* Left Input */ + {"Left Line2L Mux", "single-ended", "LINE2L"}, + {"Left Line2L Mux", "differential", "LINE2L"}, + + {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, + {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, + {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, + + {"Left ADC", NULL, "GPIO1 dmic modclk"}, + + /* Right Input */ + {"Right Line2R Mux", "single-ended", "LINE2R"}, + {"Right Line2R Mux", "differential", "LINE2R"}, + + {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, + {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, + {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, + + {"Right ADC", NULL, "GPIO1 dmic modclk"}, + + /* + * Logical path between digital mic enable and GPIO1 modulator clock + * output function + */ + {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, + {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, + {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, + + /* Left Line Output */ + {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, + {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, + + /* Right Line Output */ + {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, + {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, + + /* Left HP Output */ + {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, + {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, + + /* Right HP Output */ + {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, + {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, + + /* Left HPCOM Output */ + {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, + {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, + + /* Right HPCOM Output */ + {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, + {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, +}; + +/* For other than tlv320aic3104 */ +static const struct snd_soc_dapm_route intercon_extra_3104[] = { + /* Left Input */ + {"Left PGA Mixer", "Mic2L Switch", "MIC2L"}, + {"Left PGA Mixer", "Mic2R Switch", "MIC2R"}, + + /* Right Input */ + {"Right PGA Mixer", "Mic2L Switch", "MIC2L"}, + {"Right PGA Mixer", "Mic2R Switch", "MIC2R"}, +}; + static const struct snd_soc_dapm_route intercon_mono[] = { /* Mono Output */ {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, @@ -867,17 +984,31 @@ static int aic3x_add_widgets(struct snd_soc_codec *codec) switch (aic3x->model) { case AIC3X_MODEL_3X: case AIC3X_MODEL_33: + snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, + ARRAY_SIZE(aic3x_extra_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon_extra, + ARRAY_SIZE(intercon_extra)); snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets, ARRAY_SIZE(aic3x_dapm_mono_widgets)); snd_soc_dapm_add_routes(dapm, intercon_mono, ARRAY_SIZE(intercon_mono)); break; case AIC3X_MODEL_3007: + snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, + ARRAY_SIZE(aic3x_extra_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon_extra, + ARRAY_SIZE(intercon_extra)); snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, ARRAY_SIZE(aic3007_dapm_widgets)); snd_soc_dapm_add_routes(dapm, intercon_3007, ARRAY_SIZE(intercon_3007)); break; + case AIC3X_MODEL_3104: + snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets, + ARRAY_SIZE(aic3104_extra_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, intercon_extra_3104, + ARRAY_SIZE(intercon_extra_3104)); + break; } return 0; @@ -1438,23 +1569,33 @@ static int aic3x_probe(struct snd_soc_codec *codec) aic3x_init(codec); if (aic3x->setup) { - /* setup GPIO functions */ - snd_soc_write(codec, AIC3X_GPIO1_REG, - (aic3x->setup->gpio_func[0] & 0xf) << 4); - snd_soc_write(codec, AIC3X_GPIO2_REG, - (aic3x->setup->gpio_func[1] & 0xf) << 4); + if (aic3x->model != AIC3X_MODEL_3104) { + /* setup GPIO functions */ + snd_soc_write(codec, AIC3X_GPIO1_REG, + (aic3x->setup->gpio_func[0] & 0xf) << 4); + snd_soc_write(codec, AIC3X_GPIO2_REG, + (aic3x->setup->gpio_func[1] & 0xf) << 4); + } else { + dev_warn(codec->dev, "GPIO functionality is not supported on tlv320aic3104\n"); + } } switch (aic3x->model) { case AIC3X_MODEL_3X: case AIC3X_MODEL_33: + snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, + ARRAY_SIZE(aic3x_extra_snd_controls)); snd_soc_add_codec_controls(codec, aic3x_mono_controls, ARRAY_SIZE(aic3x_mono_controls)); break; case AIC3X_MODEL_3007: + snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, + ARRAY_SIZE(aic3x_extra_snd_controls)); snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); break; + case AIC3X_MODEL_3104: + break; } /* set mic bias voltage */ @@ -1522,6 +1663,7 @@ static const struct i2c_device_id aic3x_i2c_id[] = { { "tlv320aic33", AIC3X_MODEL_33 }, { "tlv320aic3007", AIC3X_MODEL_3007 }, { "tlv320aic3106", AIC3X_MODEL_3X }, + { "tlv320aic3104", AIC3X_MODEL_3104 }, { } }; MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); @@ -1673,6 +1815,7 @@ static const struct of_device_id tlv320aic3x_of_match[] = { { .compatible = "ti,tlv320aic33" }, { .compatible = "ti,tlv320aic3007" }, { .compatible = "ti,tlv320aic3106" }, + { .compatible = "ti,tlv320aic3104" }, {}, }; MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); -- cgit v1.2.3 From 6fb4aebee9d128f1c61c3bc9e6a0132b12ab563c Mon Sep 17 00:00:00 2001 From: Zubair Lutfullah Kakakhel Date: Tue, 3 Feb 2015 10:55:58 +0000 Subject: ASoC: jz4740: Add binding documentation for jz4740-i2s This patch adds binding for the jz4740-i2s driver. Signed-off-by: Zubair Lutfullah Kakakhel Acked-by: Lars-Peter Clausen Signed-off-by: Mark Brown --- .../bindings/sound/ingenic,jz4740-i2s.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt b/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt new file mode 100644 index 000000000000..b41433386e2f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ingenic,jz4740-i2s.txt @@ -0,0 +1,23 @@ +Ingenic JZ4740 I2S controller + +Required properties: +- compatible : "ingenic,jz4740-i2s" +- reg : I2S registers location and length +- clocks : AIC and I2S PLL clock specifiers. +- clock-names: "aic" and "i2s" +- dmas: DMA controller phandle and DMA request line for I2S Tx and Rx channels +- dma-names: Must be "tx" and "rx" + +Example: + +i2s: i2s@10020000 { + compatible = "ingenic,jz4740-i2s"; + reg = <0x10020000 0x94>; + + clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2SPLL>; + clock-names = "aic", "i2s"; + + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; + +}; -- cgit v1.2.3 From c028d4165fe56fc51efb53dd4b04aa157d005dc5 Mon Sep 17 00:00:00 2001 From: Kenneth Westfield Date: Thu, 5 Feb 2015 12:53:38 -0800 Subject: ASoC: max98357a: Document MAX98357A bindings Add documentation to the sound directory of the device-tree bindings for the Maxim MAX98357A audio DAC. Signed-off-by: Kenneth Westfield Acked-by: Banajit Goswami Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/max98357a.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/max98357a.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/max98357a.txt b/Documentation/devicetree/bindings/sound/max98357a.txt new file mode 100644 index 000000000000..a7a149a236e5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/max98357a.txt @@ -0,0 +1,14 @@ +Maxim MAX98357A audio DAC + +This node models the Maxim MAX98357A DAC. + +Required properties: +- compatible : "maxim,max98357a" +- sdmode-gpios : GPIO specifier for the GPIO -> DAC SDMODE pin + +Example: + +max98357a { + compatible = "maxim,max98357a"; + sdmode-gpios = <&qcom_pinmux 25 0>; +}; -- cgit v1.2.3