From 523d3de41f02141f6f6cd497d07946a2837432cf Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 21 Aug 2017 10:05:01 +0200 Subject: clk: samsung: exynos5433: Add support for runtime PM Add runtime pm support for all clock controller units (CMU), which belong to power domains and require special handling during on/off operations. Typically special values has to be written to MUX registers to change internal clocks parents to OSC clock before turning power off. During such operation all clocks, which enter CMU has to be enabled to let MUX to stabilize. Also for each CMU there is one special parent clock, which has to be enabled all the time when any access to CMU registers is being done. This patch solves most of the mysterious external abort and freeze issues caused by a lack of proper parent CMU clock enabled or incorrect turn off procedure. Signed-off-by: Marek Szyprowski Reviewed-by: Ulf Hansson Reviewed-by: Chanwoo Choi Tested-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/1503302703-13801-4-git-send-email-m.szyprowski@samsung.com --- .../devicetree/bindings/clock/exynos5433-clock.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index 1dc80f8811fe..5c7dd12e667a 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -168,6 +168,11 @@ Required Properties: - aclk_cam1_400 - aclk_cam1_552 +Optional properties: + - power-domains: a phandle to respective power domain node as described by + generic PM domain bindings (see power/power_domain.txt for more + information). + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -270,6 +275,7 @@ Example 2: Examples of clock controller nodes are listed below. clocks = <&xxti>, <&cmu_top CLK_ACLK_G2D_266>, <&cmu_top CLK_ACLK_G2D_400>; + power-domains = <&pd_g2d>; }; cmu_disp: clock-controller@13b90000 { @@ -295,6 +301,7 @@ Example 2: Examples of clock controller nodes are listed below. <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, <&cmu_mif CLK_ACLK_DISP_333>; + power-domains = <&pd_disp>; }; cmu_aud: clock-controller@114c0000 { @@ -304,6 +311,7 @@ Example 2: Examples of clock controller nodes are listed below. clock-names = "oscclk", "fout_aud_pll"; clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; + power-domains = <&pd_aud>; }; cmu_bus0: clock-controller@13600000 { @@ -340,6 +348,7 @@ Example 2: Examples of clock controller nodes are listed below. clock-names = "oscclk", "aclk_g3d_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + power-domains = <&pd_g3d>; }; cmu_gscl: clock-controller@13cf0000 { @@ -353,6 +362,7 @@ Example 2: Examples of clock controller nodes are listed below. clocks = <&xxti>, <&cmu_top CLK_ACLK_GSCL_111>, <&cmu_top CLK_ACLK_GSCL_333>; + power-domains = <&pd_gscl>; }; cmu_apollo: clock-controller@11900000 { @@ -384,6 +394,7 @@ Example 2: Examples of clock controller nodes are listed below. clocks = <&xxti>, <&cmu_top CLK_SCLK_JPEG_MSCL>, <&cmu_top CLK_ACLK_MSCL_400>; + power-domains = <&pd_mscl>; }; cmu_mfc: clock-controller@15280000 { @@ -393,6 +404,7 @@ Example 2: Examples of clock controller nodes are listed below. clock-names = "oscclk", "aclk_mfc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + power-domains = <&pd_mfc>; }; cmu_hevc: clock-controller@14f80000 { @@ -402,6 +414,7 @@ Example 2: Examples of clock controller nodes are listed below. clock-names = "oscclk", "aclk_hevc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + power-domains = <&pd_hevc>; }; cmu_isp: clock-controller@146d0000 { @@ -415,6 +428,7 @@ Example 2: Examples of clock controller nodes are listed below. clocks = <&xxti>, <&cmu_top CLK_ACLK_ISP_DIS_400>, <&cmu_top CLK_ACLK_ISP_400>; + power-domains = <&pd_isp>; }; cmu_cam0: clock-controller@120d0000 { @@ -430,6 +444,7 @@ Example 2: Examples of clock controller nodes are listed below. <&cmu_top CLK_ACLK_CAM0_333>, <&cmu_top CLK_ACLK_CAM0_400>, <&cmu_top CLK_ACLK_CAM0_552>; + power-domains = <&pd_cam0>; }; cmu_cam1: clock-controller@145d0000 { @@ -451,6 +466,7 @@ Example 2: Examples of clock controller nodes are listed below. <&cmu_top CLK_ACLK_CAM1_333>, <&cmu_top CLK_ACLK_CAM1_400>, <&cmu_top CLK_ACLK_CAM1_552>; + power-domains = <&pd_cam1>; }; Example 3: UART controller node that consumes the clock generated by the clock -- cgit v1.2.3 From ae432a9b314e07d486acfadc4df2f922721e6757 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 21 Aug 2017 10:05:03 +0200 Subject: clk: samsung: exynos-audss: Add support for runtime PM This patch adds support for runtime PM to Exynos Audio SubSystem driver to enable full support for audio power domain on Exynos5 SoCs. The main change is moving register saving and restoring code from system sleep PM ops to runtime PM ops and implementing system sleep PM ops with generic pm_runtime_force_suspend/resume helpers. Runtime PM of the Exynos AudSS device is managed from clock core depending on the preparation status of the provided clocks. Signed-off-by: Marek Szyprowski Reviewed-by: Ulf Hansson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Signed-off-by: Michael Turquette Link: lkml.kernel.org/r/1503302703-13801-6-git-send-email-m.szyprowski@samsung.com --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 6 +++ drivers/clk/samsung/clk-exynos-audss.c | 51 ++++++++++++++-------- 2 files changed, 40 insertions(+), 17 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 0c3d6015868d..f3635d5aeba4 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -33,6 +33,12 @@ Required Properties: - clock-names: Aliases for the above clocks. They should be "pll_ref", "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. +Optional Properties: + + - power-domains: a phandle to respective power domain node as described by + generic PM domain bindings (see power/power_domain.txt for more + information). + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 6be52fb46ff3..ab494c104ce6 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -18,6 +18,7 @@ #include #include #include +#include #include @@ -36,14 +37,13 @@ static struct clk *epll; #define ASS_CLK_DIV 0x4 #define ASS_CLK_GATE 0x8 -#ifdef CONFIG_PM_SLEEP static unsigned long reg_save[][2] = { { ASS_CLK_SRC, 0 }, { ASS_CLK_DIV, 0 }, { ASS_CLK_GATE, 0 }, }; -static int exynos_audss_clk_suspend(struct device *dev) +static int __maybe_unused exynos_audss_clk_suspend(struct device *dev) { int i; @@ -53,7 +53,7 @@ static int exynos_audss_clk_suspend(struct device *dev) return 0; } -static int exynos_audss_clk_resume(struct device *dev) +static int __maybe_unused exynos_audss_clk_resume(struct device *dev) { int i; @@ -62,7 +62,6 @@ static int exynos_audss_clk_resume(struct device *dev) return 0; } -#endif /* CONFIG_PM_SLEEP */ struct exynos_audss_clk_drvdata { unsigned int has_adma_clk:1; @@ -179,7 +178,18 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } } } - clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", + + /* + * Enable runtime PM here to allow the clock core using runtime PM + * for the registered clocks. Additionally, we increase the runtime + * PM usage count before registering the clocks, to prevent the + * clock core from runtime suspending the device. + */ + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); @@ -190,48 +200,48 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) mout_i2s_p[2] = __clk_get_name(sclk_audio); - clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s", + clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); - clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp", + clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); - clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, + clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, "dout_aud_bus", "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); - clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s", + clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s", "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, &lock); - clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk", + clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 0, 0, &lock); - clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus", + clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", "dout_aud_bus", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 2, 0, &lock); - clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s", + clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", "dout_i2s", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 3, 0, &lock); - clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus", + clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus", "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); - clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm", + clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm", sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); if (variant->has_adma_clk) { - clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma", + clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 9, 0, &lock); } @@ -251,10 +261,14 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) goto unregister; } + pm_runtime_put_sync(dev); + return 0; unregister: exynos_audss_clk_teardown(); + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); if (!IS_ERR(epll)) clk_disable_unprepare(epll); @@ -267,6 +281,7 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) of_clk_del_provider(pdev->dev.of_node); exynos_audss_clk_teardown(); + pm_runtime_disable(&pdev->dev); if (!IS_ERR(epll)) clk_disable_unprepare(epll); @@ -275,8 +290,10 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) } static const struct dev_pm_ops exynos_audss_clk_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_audss_clk_suspend, - exynos_audss_clk_resume) + SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume, + NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static struct platform_driver exynos_audss_clk_driver = { -- cgit v1.2.3 From 8d532d36ac02a39c618abd1ee90a600a98274730 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sat, 2 Sep 2017 19:39:15 +0200 Subject: dt-bindings: iio: pressure: add LPS33HW and LPS35HW device bindings Signed-off-by: Lorenzo Bianconi Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st-sensors.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index 9ec6f5ce54fc..678c035d9ed6 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -71,3 +71,5 @@ Pressure sensors: - st,lps25h-press - st,lps331ap-press - st,lps22hb-press +- st,lps33hw +- st,lps35hw -- cgit v1.2.3 From 50544f39018f8c75778d84228535bf4a0d588583 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 26 Aug 2017 12:21:42 +0530 Subject: dt-bindings: Add vendor prefix for Amarula Solutions Added 'amarula' as a vendor prefix for Amarula Solutions, specialist in Embedded and Opensource solutions. Signed-off-by: Jagan Teki Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ea1fd4232ab..192709de8632 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -18,6 +18,7 @@ al Annapurna Labs allwinner Allwinner Technology Co., Ltd. alphascale AlphaScale Integrated Circuits Systems, Inc. altr Altera Corp. +amarula Amarula Solutions amazon Amazon.com, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. -- cgit v1.2.3 From 15306b752f5a91ade95882aba83022f54fbaa433 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 26 Aug 2017 15:39:24 +0530 Subject: ARM: dts: rockchip: Add rk3288 vyasa board This patch adds initial support for rk3288 based Vyasa board, which is made by Amarula Solutions. Signed-off-by: Jagan Teki Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/rk3288-vyasa.dts | 311 +++++++++++++++++++++ 3 files changed, 317 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rk3288-vyasa.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index b003148e2945..326d24bca1a9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -1,5 +1,9 @@ Rockchip platforms device tree bindings --------------------------------------- +- Amarula Vyasa RK3288 board + Required root node properties: + - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; + - Asus Tinker board Required root node properties: - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faf46abaa4a2..0d8eea43e1b5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -767,7 +767,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3288-veyron-pinky.dtb \ - rk3288-veyron-speedy.dtb + rk3288-veyron-speedy.dtb \ + rk3288-vyasa.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts new file mode 100644 index 000000000000..1fd5e2f3542e --- /dev/null +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -0,0 +1,311 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288.dtsi" + +/ { + model = "Amarula Vyasa-RK3288"; + compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + + regulators { + vdd_cpu: vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_codec: LDO_REG2 { + regulator-name = "vcc_codec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_gps: LDO_REG4 { + regulator-name = "vcc_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc10_lcd: LDO_REG6 { + regulator-name = "vcc10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_sd: SWITCH_REG1 { + regulator-name = "vcc33_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic-int { + rockchip,pins = ; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; -- cgit v1.2.3 From 912620c02c314a697b05d52263212c24a2a6b05b Mon Sep 17 00:00:00 2001 From: Tomas Novotny Date: Mon, 26 Jun 2017 16:30:16 +0200 Subject: dt-bindings: add vendor prefix for Touchless Biometric Systems AG TBS is a company providing biometrics products and solution in Access control and time management. Signed-off-by: Tomas Novotny Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ea1fd4232ab..26d105625d38 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -329,6 +329,7 @@ swir Sierra Wireless syna Synaptics Inc. synology Synology, Inc. tbs TBS Technologies +tbs-biometrics Touchless Biometric Systems AG tcg Trusted Computing Group tcl Toby Churchill Ltd. technexion TechNexion -- cgit v1.2.3 From 17760376ae31e06f66b3c3b8981f5978d4c53150 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Sep 2017 23:37:18 +0300 Subject: soc: renesas: rcar-rst: add R8A77970 support Add support for R-Car V3M (R8A77970) to the R-Car RST driver -- this driver is needed for the clock driver to work. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + drivers/soc/renesas/Kconfig | 3 ++- drivers/soc/renesas/rcar-rst.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index e5a03ffe04fb..a8014f3ab8ba 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -26,6 +26,7 @@ Required properties: - "renesas,r8a7794-rst" (R-Car E2) - "renesas,r8a7795-rst" (R-Car H3) - "renesas,r8a7796-rst" (R-Car M3-W) + - "renesas,r8a77970-rst" (R-Car V3M) - "renesas,r8a77995-rst" (R-Car D3) - reg: Address start and address range for the device. diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 567414cb42ba..f0d562a7c4d3 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -3,7 +3,8 @@ config SOC_RENESAS default y if ARCH_RENESAS select SOC_BUS select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \ - ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77995 + ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \ + ARCH_R8A77995 select SYSC_R8A7743 if ARCH_R8A7743 select SYSC_R8A7745 if ARCH_R8A7745 select SYSC_R8A7779 if ARCH_R8A7779 diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index baa47014e96b..3316b028f231 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -41,6 +41,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { /* R-Car Gen3 is handled like R-Car Gen2 */ { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 }, + { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 }, { /* sentinel */ } }; -- cgit v1.2.3 From 055fb568157c3a6754228138b3ca51247cb4f466 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 22 Aug 2017 14:52:19 +0100 Subject: dt-bindings: apmu: Document r8a7745 support Document APMU and SMP enable method for RZ/G1E (also known as r8a7745) SoC. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/power/renesas,apmu.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt index af21502e939c..f747f95eee58 100644 --- a/Documentation/devicetree/bindings/power/renesas,apmu.txt +++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt @@ -8,6 +8,7 @@ Required properties: - compatible: Should be "renesas,-apmu", "renesas,apmu" as fallback. Examples with soctypes are: - "renesas,r8a7743-apmu" (RZ/G1M) + - "renesas,r8a7745-apmu" (RZ/G1E) - "renesas,r8a7790-apmu" (R-Car H2) - "renesas,r8a7791-apmu" (R-Car M2-W) - "renesas,r8a7792-apmu" (R-Car V2H) -- cgit v1.2.3 From 8ac491a5d0934bf1a77db155d759c682ab790c45 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 30 Aug 2017 11:53:01 +0200 Subject: dt-bindings: display: renesas: dw-hdmi: Drop bogus node name suffix Node names should not use numerical suffixes if the nodes can be distinguished by unit-address. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt index b1a8929c2536..3a72a103a18a 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt @@ -37,7 +37,7 @@ Optional properties: Example: - hdmi0: hdmi0@fead0000 { + hdmi0: hdmi@fead0000 { compatible = "renesas,r8a7795-dw-hdmi"; reg = <0 0xfead0000 0 0x10000>; interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From 443c1631172a7a6dc19c1657425354327858a548 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Aug 2017 14:56:49 +0200 Subject: ARM: shmobile: Document R-Car V3M SoC DT bindings Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index ae75cb3b1331..a1f06711a4dd 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -39,6 +39,8 @@ SoCs: compatible = "renesas,r8a7795" - R-Car M3-W (R8A77960) compatible = "renesas,r8a7796" + - R-Car V3M (R8A77970) + compatible = "renesas,r8a77970" - R-Car D3 (R8A77995) compatible = "renesas,r8a77995" -- cgit v1.2.3 From bab9b2a74fe9da96e895e0919f625679a0a8c964 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Sep 2017 23:37:20 +0300 Subject: soc: renesas: rcar-sysc: add R8A77970 support Add support for R-Car V3M (R8A77970) SoC power areas to the R-Car SYSC driver. Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../bindings/power/renesas,rcar-sysc.txt | 1 + drivers/soc/renesas/Kconfig | 5 +++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a77970-sysc.c | 39 ++++++++++++++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 ++ drivers/soc/renesas/rcar-sysc.h | 1 + 6 files changed, 50 insertions(+) create mode 100644 drivers/soc/renesas/r8a77970-sysc.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 98cc8c09d02d..8690f10426a3 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -17,6 +17,7 @@ Required properties: - "renesas,r8a7794-sysc" (R-Car E2) - "renesas,r8a7795-sysc" (R-Car H3) - "renesas,r8a7796-sysc" (R-Car M3-W) + - "renesas,r8a77970-sysc" (R-Car V3M) - "renesas,r8a77995-sysc" (R-Car D3) - reg: Address start and address range for the device. - #power-domain-cells: Must be 1. diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index f0d562a7c4d3..09550b1da56d 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -14,6 +14,7 @@ config SOC_RENESAS select SYSC_R8A7794 if ARCH_R8A7794 select SYSC_R8A7795 if ARCH_R8A7795 select SYSC_R8A7796 if ARCH_R8A7796 + select SYSC_R8A77970 if ARCH_R8A77970 select SYSC_R8A77995 if ARCH_R8A77995 if SOC_RENESAS @@ -55,6 +56,10 @@ config SYSC_R8A7796 bool "R-Car M3-W System Controller support" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A77970 + bool "R-Car V3M System Controller support" if COMPILE_TEST + select SYSC_RCAR + config SYSC_R8A77995 bool "R-Car D3 System Controller support" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 6b6e7f16104c..8334af1d231b 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o +obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o # Family diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c new file mode 100644 index 000000000000..8c614164718e --- /dev/null +++ b/drivers/soc/renesas/r8a77970-sysc.c @@ -0,0 +1,39 @@ +/* + * Renesas R-Car V3M System Controller + * + * Copyright (C) 2017 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a77970_areas[] __initconst = { + { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON, + PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU, + PD_CPU_NOCR }, + { "cr7", 0x240, 0, R8A77970_PD_CR7, R8A77970_PD_ALWAYS_ON }, + { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON }, + { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_ALWAYS_ON }, + { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A2IR0 }, + { "a2ir2", 0x400, 2, R8A77970_PD_A2IR2, R8A77970_PD_A2IR0 }, + { "a2ir3", 0x400, 3, R8A77970_PD_A2IR3, R8A77970_PD_A2IR0 }, + { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_ALWAYS_ON }, + { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A2SC0 }, +}; + +const struct rcar_sysc_info r8a77970_sysc_info __initconst = { + .areas = r8a77970_areas, + .num_areas = ARRAY_SIZE(r8a77970_areas), +}; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index c8406e81640f..55a47e509e49 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] = { #ifdef CONFIG_SYSC_R8A7796 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info }, #endif +#ifdef CONFIG_SYSC_R8A77970 + { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info }, +#endif #ifdef CONFIG_SYSC_R8A77995 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info }, #endif diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h index 2f524922c4d2..9d9daf9eb91b 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h @@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info; extern const struct rcar_sysc_info r8a7794_sysc_info; extern const struct rcar_sysc_info r8a7795_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info; +extern const struct rcar_sysc_info r8a77970_sysc_info; extern const struct rcar_sysc_info r8a77995_sysc_info; -- cgit v1.2.3 From 376349232a93645624426db782cafe688054e6d6 Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Thu, 14 Sep 2017 17:28:42 +0300 Subject: ARC: reset: introduce AXS10x reset driver ARC AXS10x boards support custom IP-block which allows to control reset signals of selected peripherals. For example DW GMAC, etc... This block is controlled via memory-mapped register (AKA CREG) which represents up-to 32 reset lines. This regiter is self-clearing so we don't need to deassert line after reset. As of today only the following lines are used: - DW GMAC - line 5 Signed-off-by: Eugeniy Paltsev Signed-off-by: Philipp Zabel --- .../bindings/reset/snps,axs10x-reset.txt | 33 +++++++++ MAINTAINERS | 6 ++ drivers/reset/Kconfig | 6 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-axs10x.c | 83 ++++++++++++++++++++++ 5 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt create mode 100644 drivers/reset/reset-axs10x.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt new file mode 100644 index 000000000000..32d8435a41df --- /dev/null +++ b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt @@ -0,0 +1,33 @@ +Binding for the AXS10x reset controller + +This binding describes the ARC AXS10x boards custom IP-block which allows +to control reset signals of selected peripherals. For example DW GMAC, etc... +This block is controlled via memory-mapped register (AKA CREG) which +represents up-to 32 reset lines. + +As of today only the following lines are used: + - DW GMAC - line 5 + +This binding uses the common reset binding[1]. + +[1] Documentation/devicetree/bindings/reset/reset.txt + +Required properties: +- compatible: should be "snps,axs10x-reset". +- reg: should always contain pair address - length: for creg reset + bits register. +- #reset-cells: from common reset binding; Should always be set to 1. + +Example: + reset: reset-controller@11220 { + compatible = "snps,axs10x-reset"; + #reset-cells = <1>; + reg = <0x11220 0x4>; + }; + +Specifying reset lines connected to IP modules: + ethernet@.... { + .... + resets = <&reset 5>; + .... + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2281af4b41b6..2cf502eeb774 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12883,6 +12883,12 @@ F: arch/arc/plat-axs10x F: arch/arc/boot/dts/ax* F: Documentation/devicetree/bindings/arc/axs10* +SYNOPSYS AXS10x RESET CONTROLLER DRIVER +M: Eugeniy Paltsev +S: Supported +F: drivers/reset/reset-axs10x.c +F: Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt + SYNOPSYS DESIGNWARE DMAC DRIVER M: Viresh Kumar M: Andy Shevchenko diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index e0c393214264..23ec43f99d9a 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -28,6 +28,12 @@ config RESET_ATH79 This enables the ATH79 reset controller driver that supports the AR71xx SoC reset controller. +config RESET_AXS10X + bool "AXS10x Reset Driver" if COMPILE_TEST + default ARC_PLAT_AXS10X + help + This enables the reset controller driver for AXS10x. + config RESET_BERLIN bool "Berlin Reset Driver" if COMPILE_TEST default ARCH_BERLIN diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index d368367110e5..7579dba7b185 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o +obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c new file mode 100644 index 000000000000..afb298e46bd9 --- /dev/null +++ b/drivers/reset/reset-axs10x.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 Synopsys. + * + * Synopsys AXS10x reset driver. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +#define to_axs10x_rst(p) container_of((p), struct axs10x_rst, rcdev) + +#define AXS10X_MAX_RESETS 32 + +struct axs10x_rst { + void __iomem *regs_rst; + spinlock_t lock; + struct reset_controller_dev rcdev; +}; + +static int axs10x_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct axs10x_rst *rst = to_axs10x_rst(rcdev); + unsigned long flags; + + spin_lock_irqsave(&rst->lock, flags); + writel(BIT(id), rst->regs_rst); + spin_unlock_irqrestore(&rst->lock, flags); + + return 0; +} + +static const struct reset_control_ops axs10x_reset_ops = { + .reset = axs10x_reset_reset, +}; + +static int axs10x_reset_probe(struct platform_device *pdev) +{ + struct axs10x_rst *rst; + struct resource *mem; + + rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(rst->regs_rst)) + return PTR_ERR(rst->regs_rst); + + spin_lock_init(&rst->lock); + + rst->rcdev.owner = THIS_MODULE; + rst->rcdev.ops = &axs10x_reset_ops; + rst->rcdev.of_node = pdev->dev.of_node; + rst->rcdev.nr_resets = AXS10X_MAX_RESETS; + + return devm_reset_controller_register(&pdev->dev, &rst->rcdev); +} + +static const struct of_device_id axs10x_reset_dt_match[] = { + { .compatible = "snps,axs10x-reset" }, + { }, +}; + +static struct platform_driver axs10x_reset_driver = { + .probe = axs10x_reset_probe, + .driver = { + .name = "axs10x-reset", + .of_match_table = axs10x_reset_dt_match, + }, +}; +builtin_platform_driver(axs10x_reset_driver); + +MODULE_AUTHOR("Eugeniy Paltsev "); +MODULE_DESCRIPTION("Synopsys AXS10x reset driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 785ec87483d1e24a012ecf642ee7d07c4118f142 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Sep 2017 23:02:08 +0300 Subject: ravb: document R8A77970 bindings R-Car V3M (R8A77970) SoC also has the R-Car gen3 compatible EtherAVB device, so document the SoC specific bindings. Signed-off-by: Sergei Shtylyov Acked-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index 16723535e1aa..2689211d324c 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -17,6 +17,7 @@ Required properties: - "renesas,etheravb-r8a7795" for the R8A7795 SoC. - "renesas,etheravb-r8a7796" for the R8A7796 SoC. + - "renesas,etheravb-r8a77970" for the R8A77970 SoC. - "renesas,etheravb-rcar-gen3" as a fallback for the above R-Car Gen3 devices. @@ -40,7 +41,7 @@ Optional properties: - interrupt-parent: the phandle for the interrupt controller that services interrupts for this device. - interrupt-names: A list of interrupt names. - For the R8A779[56] SoCs this property is mandatory; + For the R-Car Gen 3 SoCs this property is mandatory; it should include one entry per channel, named "ch%u", where %u is the channel number ranging from 0 to 24. For other SoCs this property is optional; if present -- cgit v1.2.3 From f231c4178a655b09c1fe4dce4b09de7b867c20af Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 14 Sep 2017 09:06:38 +0900 Subject: dt-bindings: net: renesas-ravb: Add support for R8A77995 RAVB Add a new compatible string for the R8A77995 (R-Car D3) RAVB. Signed-off-by: Yoshihiro Shimoda Acked-by: Geert Uytterhoeven Acked-by: Sergei Shtylyov Acked-by: Simon Horman Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index 2689211d324c..c902261893b9 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -18,6 +18,7 @@ Required properties: - "renesas,etheravb-r8a7795" for the R8A7795 SoC. - "renesas,etheravb-r8a7796" for the R8A7796 SoC. - "renesas,etheravb-r8a77970" for the R8A77970 SoC. + - "renesas,etheravb-r8a77995" for the R8A77995 SoC. - "renesas,etheravb-rcar-gen3" as a fallback for the above R-Car Gen3 devices. -- cgit v1.2.3 From 367f15d3130e0d6c6818a4ace2463914e8c78e2c Mon Sep 17 00:00:00 2001 From: Markus Mayer Date: Thu, 24 Aug 2017 16:36:25 -0700 Subject: dt-bindings: Add bindings for Broadcom STB DRAM Sensors Provide bindings for the Broadcom STB DDR PHY Front End (DPFE). Signed-off-by: Markus Mayer Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- .../bindings/memory-controllers/brcm,dpfe-cpu.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt b/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt new file mode 100644 index 000000000000..82d923ef413f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt @@ -0,0 +1,27 @@ +DDR PHY Front End (DPFE) for Broadcom STB +========================================= + +DPFE and the DPFE firmware provide an interface for the host CPU to +communicate with the DCPU, which resides inside the DDR PHY. + +There are three memory regions for interacting with the DCPU. These are +specified in a single reg property. + +Required properties: + - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu" + or "brcm,dpfe-cpu" + - reg: must reference three register ranges + - start address and length of the DCPU register space + - start address and length of the DCPU data memory space + - start address and length of the DCPU instruction memory space + - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem"; + they must be in the same order as the register declarations + +Example: + dpfe_cpu0: dpfe-cpu@f1132000 { + compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu"; + reg = <0xf1132000 0x180 + 0xf1134000 0x1000 + 0xf1138000 0x4000>; + reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem"; + }; -- cgit v1.2.3 From 9600c2340ded841076367cc78fdd2b65e1cf8ed8 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 15 Jun 2017 13:39:51 -0700 Subject: dt-bindings: ARM: brcmstb: Update Broadcom STB Power Management binding Update the Broadcom STB Power Management binding document with new compatible strings for the DDR PHY and memory controller found on newer chips. Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index 0d0c1ae81bed..790e6b0b8306 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY. Required properties: - compatible : should contain one of these + "brcm,brcmstb-ddr-phy-v71.1" + "brcm,brcmstb-ddr-phy-v72.0" "brcm,brcmstb-ddr-phy-v225.1" "brcm,brcmstb-ddr-phy-v240.1" "brcm,brcmstb-ddr-phy-v240.2" @@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh Power-Down (SRPD), among other things. Required properties: -- compatible : should contain "brcm,brcmstb-memc-ddr" +- compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range Example: -- cgit v1.2.3 From 0e1bfb72b076b07dc844bf33c19d62a3075f540f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 30 Aug 2017 11:57:31 +0200 Subject: v4l: vsp1: Use generic node name Use the preferred generic node name in the example. Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/media/renesas,vsp1.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.txt b/Documentation/devicetree/bindings/media/renesas,vsp1.txt index 9b695bcbf219..16427017cb45 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.txt +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.txt @@ -22,7 +22,7 @@ Optional properties: Example: R8A7790 (R-Car H2) VSP1-S node - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From 716f1c8992ebbb321c5ad1ff6823a9e9074007e8 Mon Sep 17 00:00:00 2001 From: YuanCheng Cheng Date: Sat, 9 Sep 2017 19:40:58 +0800 Subject: dt-bindings: vendor-prefixes: Add nutsboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit NutsBoard (http://nutsboard.org/) is an organization and focus on ARM based embedded boards with open source software. Signed-off-by: YuanCheng Cheng Reviewed-by: Fabio Estevam Reviewed-by: Andreas Färber Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ea1fd4232ab..f461616cf85f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -235,6 +235,7 @@ nintendo Nintendo nlt NLT Technologies, Ltd. nokia Nokia nordic Nordic Semiconductor +nutsboard NutsBoard nuvoton Nuvoton Technology Corporation nvd New Vision Display nvidia NVIDIA -- cgit v1.2.3 From 0bf4b3fadb5663959605d584410412dce53406cc Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 11 Sep 2017 09:30:23 +0100 Subject: of: add vendor prefix for Silicon Storage Technology Inc. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Silicon Storage Technology Inc. to the list of devicetree vendor prefixes. Signed-off-by: Fabrizio Castro Reviewed-by: Andreas Färber Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index f461616cf85f..c6ef403e6321 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -318,6 +318,7 @@ solomon Solomon Systech Limited sony Sony Corporation spansion Spansion Inc. sprd Spreadtrum Communications Inc. +sst Silicon Storage Technology, Inc. st STMicroelectronics starry Starry Electronic Technology (ShenZhen) Co., LTD startek Startek -- cgit v1.2.3 From 8d46e28fb5081b49c5b24c814ad464fb99359d58 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 9 Sep 2017 00:34:20 +0300 Subject: clk: renesas: cpg-mssr: Add R8A77970 support Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 5 +- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a77970-cpg-mssr.c | 199 +++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 6 files changed, 215 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/renesas/r8a77970-cpg-mssr.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index 316e13686568..f1890d0777a6 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -22,6 +22,7 @@ Required Properties: - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) + - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - reg: Base address and length of the memory resource used by the CPG/MSSR @@ -31,8 +32,8 @@ Required Properties: clock-names - clock-names: List of external parent clock names. Valid names are: - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, - r8a7795, r8a7796, r8a77995) - - "extalr" (r8a7795, r8a7796) + r8a7795, r8a7796, r8a77970, r8a77995) + - "extalr" (r8a7795, r8a7796, r8a77970) - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794) - #clock-cells: Must be 2 diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index acbb38151ba1..43b5a89c4b28 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -15,6 +15,7 @@ config CLK_RENESAS select CLK_R8A7794 if ARCH_R8A7794 select CLK_R8A7795 if ARCH_R8A7795 select CLK_R8A7796 if ARCH_R8A7796 + select CLK_R8A77970 if ARCH_R8A77970 select CLK_R8A77995 if ARCH_R8A77995 select CLK_SH73A0 if ARCH_SH73A0 @@ -95,6 +96,10 @@ config CLK_R8A7796 bool "R-Car M3-W clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG +config CLK_R8A77970 + bool "R-Car V3M clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A77995 bool "R-Car D3 clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 9bda3ec5b199..306861c74a87 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c new file mode 100644 index 000000000000..72f98527473a --- /dev/null +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -0,0 +1,199 @@ +/* + * r8a77970 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2017 Cogent Embedded Inc. + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77970_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL3, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + + /* Core Clock Outputs */ + DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1), + DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1), + DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1), + + DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), + + DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014), + DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + + DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1), + DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1), +}; + +static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = { + DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), + DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), + DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), + DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), + DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), + DEF_MOD("msiof3", 208, R8A77970_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77970_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77970_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77970_CLK_MSO), + DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), + DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), + DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), + DEF_MOD("rwdt", 402, R8A77970_CLK_R), + DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), + DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), + DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), + DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), + DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), + DEF_MOD("thermal", 522, R8A77970_CLK_CP), + DEF_MOD("pwm", 523, R8A77970_CLK_S2D4), + DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1), + DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1), + DEF_MOD("csi40", 716, R8A77970_CLK_CSI0), + DEF_MOD("du0", 724, R8A77970_CLK_S2D1), + DEF_MOD("vin3", 808, R8A77970_CLK_S2D1), + DEF_MOD("vin2", 809, R8A77970_CLK_S2D1), + DEF_MOD("vin1", 810, R8A77970_CLK_S2D1), + DEF_MOD("vin0", 811, R8A77970_CLK_S2D1), + DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2), + DEF_MOD("gpio5", 907, R8A77970_CLK_CP), + DEF_MOD("gpio4", 908, R8A77970_CLK_CP), + DEF_MOD("gpio3", 909, R8A77970_CLK_CP), + DEF_MOD("gpio2", 910, R8A77970_CLK_CP), + DEF_MOD("gpio1", 911, R8A77970_CLK_CP), + DEF_MOD("gpio0", 912, R8A77970_CLK_CP), + DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), + DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), + DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), + DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), + DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2), + DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2), +}; + +static const unsigned int r8a77970_crit_mod_clks[] __initconst = { + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL3 + * 14 13 19 (MHz) + *------------------------------------------------- + * 0 0 0 16.66 x 1 x192 x192 x96 + * 0 0 1 16.66 x 1 x192 x192 x80 + * 0 1 0 20 x 1 x160 x160 x80 + * 0 1 1 20 x 1 x160 x160 x66 + * 1 0 0 27 / 2 x236 x236 x118 + * 1 0 1 27 / 2 x236 x236 x98 + * 1 1 0 33.33 / 2 x192 x192 x96 + * 1 1 1 33.33 / 2 x192 x192 x80 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ + (((md) & BIT(13)) >> 12) | \ + (((md) & BIT(19)) >> 19)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 96, 1, }, + { 1, 192, 1, 80, 1, }, + { 1, 160, 1, 80, 1, }, + { 1, 160, 1, 66, 1, }, + { 2, 236, 1, 118, 1, }, + { 2, 236, 1, 98, 1, }, + { 2, 192, 1, 96, 1, }, + { 2, 192, 1, 80, 1, }, +}; + +static int __init r8a77970_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a77970_core_clks, + .num_core_clks = ARRAY_SIZE(r8a77970_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a77970_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks), + .num_hw_mod_clks = 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks = r8a77970_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks), + + /* Callbacks */ + .init = r8a77970_cpg_mssr_init, + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index e580a5e6346c..1779b0cc7a2a 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -680,6 +680,12 @@ static const struct of_device_id cpg_mssr_match[] = { .data = &r8a7796_cpg_mssr_info, }, #endif +#ifdef CONFIG_CLK_R8A77970 + { + .compatible = "renesas,r8a77970-cpg-mssr", + .data = &r8a77970_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A77995 { .compatible = "renesas,r8a77995-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 94b9071d1061..66528ce3eb37 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -138,6 +138,7 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; extern const struct cpg_mssr_info r8a7794_cpg_mssr_info; extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; +extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; -- cgit v1.2.3 From 2f329595b8db42ceb3de93595a740ac7b24eddba Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Fri, 15 Sep 2017 15:29:15 +0800 Subject: spi: Add Spreadtrum ADI controller documentation This patch adds the binding documentation for Spreadtrum ADI controller device. Signed-off-by: Baolin Wang Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-sprd-adi.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-sprd-adi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt new file mode 100644 index 000000000000..8de589b376ce --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt @@ -0,0 +1,58 @@ +Spreadtrum ADI controller + +ADI is the abbreviation of Anolog-Digital interface, which is used to access +analog chip (such as PMIC) from digital chip. ADI controller follows the SPI +framework for its hardware implementation is alike to SPI bus and its timing +is compatile to SPI timing. + +ADI controller has 50 channels including 2 software read/write channels and +48 hardware channels to access analog chip. For 2 software read/write channels, +users should set ADI registers to access analog chip. For hardware channels, +we can configure them to allow other hardware components to use it independently, +which means we can just link one analog chip address to one hardware channel, +then users can access the mapped analog chip address by this hardware channel +triggered by hardware components instead of ADI software channels. + +Thus we introduce one property named "sprd,hw-channels" to configure hardware +channels, the first value specifies the hardware channel id which is used to +transfer data triggered by hardware automatically, and the second value specifies +the analog chip address where user want to access by hardware components. + +Since we have multi-subsystems will use unique ADI to access analog chip, when +one system is reading/writing data by ADI software channels, that should be under +one hardware spinlock protection to prevent other systems from reading/writing +data by ADI software channels at the same time, or two parallel routine of setting +ADI registers will make ADI controller registers chaos to lead incorrect results. +Then we need one hardware spinlock to synchronize between the multiple subsystems. + +Required properties: +- compatible: Should be "sprd,sc9860-adi". +- reg: Offset and length of ADI-SPI controller register space. +- hwlocks: Reference to a phandle of a hwlock provider node. +- hwlock-names: Reference to hwlock name strings defined in the same order + as the hwlocks, should be "adi". +- #address-cells: Number of cells required to define a chip select address + on the ADI-SPI bus. Should be set to 1. +- #size-cells: Size of cells required to define a chip select address size + on the ADI-SPI bus. Should be set to 0. + +Optional properties: +- sprd,hw-channels: This is an array of channel values up to 49 channels. + The first value specifies the hardware channel id which is used to + transfer data triggered by hardware automatically, and the second + value specifies the analog chip address where user want to access + by hardware components. + +SPI slave nodes must be children of the SPI controller node and can contain +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. + +Example: + adi_bus: spi@40030000 { + compatible = "sprd,sc9860-adi"; + reg = <0 0x40030000 0 0x10000>; + hwlocks = <&hwlock1 0>; + hwlock-names = "adi"; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <30 0x8c20>; + }; -- cgit v1.2.3 From 457c25efc592bb5539e18161c505f7a865013fb7 Mon Sep 17 00:00:00 2001 From: Oder Chiou Date: Mon, 18 Sep 2017 18:14:26 +0800 Subject: ASoC: rt5663: Add the function of impedance sensing Support the function of impedance sensing. It could be set the matrix row number of the impedance sensing table and the related parameters in the DTS. Signed-off-by: Oder Chiou Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5663.txt | 16 ++ include/sound/rt5663.h | 3 + sound/soc/codecs/rt5663.c | 218 ++++++++++++++++++++- 3 files changed, 233 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt index ff381718c517..497bcfc58b71 100644 --- a/Documentation/devicetree/bindings/sound/rt5663.txt +++ b/Documentation/devicetree/bindings/sound/rt5663.txt @@ -19,6 +19,22 @@ Optional properties: Based on the different PCB layout, add the manual offset value to compensate the DC offset for each L and R channel, and they are different between headphone and headset. +- "realtek,impedance_sensing_num" + The matrix row number of the impedance sensing table. + If the value is 0, it means the impedance sensing is not supported. +- "realtek,impedance_sensing_table" + The matrix rows of the impedance sensing table are consisted by impedance + minimum, impedance maximun, volume, DC offset w/o and w/ mic of each L and + R channel accordingly. Example is shown as following. + < 0 300 7 0xffd160 0xffd1c0 0xff8a10 0xff8ab0 + 301 65535 4 0xffe470 0xffe470 0xffb8e0 0xffb8e0> + The first and second column are defined for the impedance range. If the + detected impedance value is in the range, then the volume value of the + third column will be set to codec. In our codec design, each volume value + should compensate different DC offset to avoid the pop sound, and it is + also different between headphone and headset. In the example, the + "realtek,impedance_sensing_num" is 2. It means that there are 2 ranges of + impedance in the impedance sensing function. Pins on the device (for linking into audio routes) for RT5663: diff --git a/include/sound/rt5663.h b/include/sound/rt5663.h index 7d00e5849706..7b90a8f1034c 100644 --- a/include/sound/rt5663.h +++ b/include/sound/rt5663.h @@ -16,6 +16,9 @@ struct rt5663_platform_data { unsigned int dc_offset_r_manual; unsigned int dc_offset_l_manual_mic; unsigned int dc_offset_r_manual_mic; + + unsigned int impedance_sensing_num; + unsigned int *impedance_sensing_table; }; #endif diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c index ab9e0ebff5a7..767f219f6c42 100644 --- a/sound/soc/codecs/rt5663.c +++ b/sound/soc/codecs/rt5663.c @@ -38,6 +38,16 @@ enum { CODEC_VER_0, }; +struct impedance_mapping_table { + unsigned int imp_min; + unsigned int imp_max; + unsigned int vol; + unsigned int dc_offset_l_manual; + unsigned int dc_offset_r_manual; + unsigned int dc_offset_l_manual_mic; + unsigned int dc_offset_r_manual_mic; +}; + struct rt5663_priv { struct snd_soc_codec *codec; struct rt5663_platform_data pdata; @@ -45,6 +55,7 @@ struct rt5663_priv { struct delayed_work jack_detect_work; struct snd_soc_jack *hs_jack; struct timer_list btn_check_timer; + struct impedance_mapping_table *imp_table; int codec_ver; int sysclk; @@ -1575,6 +1586,9 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert) rt5663->jack_type = SND_JACK_HEADSET; rt5663_enable_push_button_irq(codec, true); + if (rt5663->pdata.impedance_sensing_num) + break; + if (rt5663->pdata.dc_offset_l_manual_mic) { regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, rt5663->pdata.dc_offset_l_manual_mic >> @@ -1596,6 +1610,9 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert) default: rt5663->jack_type = SND_JACK_HEADPHONE; + if (rt5663->pdata.impedance_sensing_num) + break; + if (rt5663->pdata.dc_offset_l_manual) { regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, rt5663->pdata.dc_offset_l_manual >> 16); @@ -1623,6 +1640,177 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert) return rt5663->jack_type; } +static int rt5663_impedance_sensing(struct snd_soc_codec *codec) +{ + struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); + unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80; + + for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) { + if (rt5663->imp_table[i].vol == 7) + break; + } + + if (rt5663->jack_type == SND_JACK_HEADSET) { + snd_soc_write(codec, RT5663_MIC_DECRO_2, + rt5663->imp_table[i].dc_offset_l_manual_mic >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_3, + rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff); + snd_soc_write(codec, RT5663_MIC_DECRO_5, + rt5663->imp_table[i].dc_offset_r_manual_mic >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_6, + rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff); + } else { + snd_soc_write(codec, RT5663_MIC_DECRO_2, + rt5663->imp_table[i].dc_offset_l_manual >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_3, + rt5663->imp_table[i].dc_offset_l_manual & 0xffff); + snd_soc_write(codec, RT5663_MIC_DECRO_5, + rt5663->imp_table[i].dc_offset_r_manual >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_6, + rt5663->imp_table[i].dc_offset_r_manual & 0xffff); + } + + reg84 = snd_soc_read(codec, RT5663_ASRC_2); + reg26 = snd_soc_read(codec, RT5663_STO1_ADC_MIXER); + reg2fa = snd_soc_read(codec, RT5663_DUMMY_1); + reg91 = snd_soc_read(codec, RT5663_HP_CHARGE_PUMP_1); + reg10 = snd_soc_read(codec, RT5663_RECMIX); + reg80 = snd_soc_read(codec, RT5663_GLB_CLK); + + snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000, 0); + snd_soc_write(codec, RT5663_ASRC_2, 0); + snd_soc_write(codec, RT5663_STO1_ADC_MIXER, 0x4040); + snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, + RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | + RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, + RT5663_PWR_VREF1 | RT5663_PWR_VREF2); + usleep_range(10000, 10005); + snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, + RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, + RT5663_PWR_FV1 | RT5663_PWR_FV2); + snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, + RT5663_SCLK_SRC_RCCLK); + snd_soc_update_bits(codec, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK, + RT5663_DIG_25M_CLK_EN); + snd_soc_update_bits(codec, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0); + snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00); + snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc); + snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_1, 0x1232); + snd_soc_write(codec, RT5663_HP_LOGIC_2, 0x0005); + snd_soc_write(codec, RT5663_DEPOP_2, 0x3003); + snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0030); + snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0x0003); + snd_soc_update_bits(codec, RT5663_PWR_DIG_2, + RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, + RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F); + snd_soc_update_bits(codec, RT5663_PWR_DIG_1, + RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | + RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 | + RT5663_PWR_ADC_R1, + RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | + RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 | + RT5663_PWR_ADC_R1); + msleep(40); + snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, + RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, + RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2); + msleep(30); + snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371); + snd_soc_write(codec, RT5663_STO_DAC_MIXER, 0); + snd_soc_write(codec, RT5663_BYPASS_STO_DAC, 0x000c); + snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa); + snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224); + snd_soc_write(codec, RT5663_HP_OUT_EN, 0x8088); + snd_soc_write(codec, RT5663_CHOP_ADC, 0x3000); + snd_soc_write(codec, RT5663_ADDA_RST, 0xc000); + snd_soc_write(codec, RT5663_STO1_HPF_ADJ1, 0x3320); + snd_soc_write(codec, RT5663_HP_CALIB_2, 0x00c9); + snd_soc_write(codec, RT5663_DUMMY_1, 0x004c); + snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7733); + snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777); + snd_soc_write(codec, RT5663_STO_DRE_9, 0x0007); + snd_soc_write(codec, RT5663_STO_DRE_10, 0x0007); + snd_soc_write(codec, RT5663_DUMMY_2, 0x02a4); + snd_soc_write(codec, RT5663_RECMIX, 0x0005); + snd_soc_write(codec, RT5663_HP_IMP_SEN_1, 0x4334); + snd_soc_update_bits(codec, RT5663_IRQ_3, 0x0004, 0x0004); + snd_soc_write(codec, RT5663_HP_LOGIC_1, 0x2200); + snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x3000); + snd_soc_write(codec, RT5663_HP_LOGIC_1, 0x6200); + + for (i = 0; i < 100; i++) { + msleep(20); + if (snd_soc_read(codec, RT5663_INT_ST_1) & 0x2) + break; + } + + value = snd_soc_read(codec, RT5663_HP_IMP_SEN_4); + + snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0); + snd_soc_write(codec, RT5663_INT_ST_1, 0); + snd_soc_write(codec, RT5663_HP_LOGIC_1, 0); + snd_soc_update_bits(codec, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK, + RT5663_DIG_25M_CLK_DIS); + snd_soc_write(codec, RT5663_GLB_CLK, reg80); + snd_soc_write(codec, RT5663_RECMIX, reg10); + snd_soc_write(codec, RT5663_DUMMY_2, 0x00a4); + snd_soc_write(codec, RT5663_DUMMY_1, reg2fa); + snd_soc_write(codec, RT5663_HP_CALIB_2, 0x00c8); + snd_soc_write(codec, RT5663_STO1_HPF_ADJ1, 0xb320); + snd_soc_write(codec, RT5663_ADDA_RST, 0xe400); + snd_soc_write(codec, RT5663_CHOP_ADC, 0x2000); + snd_soc_write(codec, RT5663_HP_OUT_EN, 0x0008); + snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, + RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0); + snd_soc_update_bits(codec, RT5663_PWR_DIG_1, + RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | + RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 | + RT5663_PWR_ADC_R1, 0); + snd_soc_update_bits(codec, RT5663_PWR_DIG_2, + RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0); + snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0); + snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0); + snd_soc_write(codec, RT5663_HP_LOGIC_2, 0); + snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_1, reg91); + snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, + RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0); + snd_soc_write(codec, RT5663_STO1_ADC_MIXER, reg26); + snd_soc_write(codec, RT5663_ASRC_2, reg84); + + for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) { + if (value >= rt5663->imp_table[i].imp_min && + value <= rt5663->imp_table[i].imp_max) + break; + } + + snd_soc_update_bits(codec, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK, + rt5663->imp_table[i].vol); + snd_soc_update_bits(codec, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK, + rt5663->imp_table[i].vol); + + if (rt5663->jack_type == SND_JACK_HEADSET) { + snd_soc_write(codec, RT5663_MIC_DECRO_2, + rt5663->imp_table[i].dc_offset_l_manual_mic >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_3, + rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff); + snd_soc_write(codec, RT5663_MIC_DECRO_5, + rt5663->imp_table[i].dc_offset_r_manual_mic >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_6, + rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff); + } else { + snd_soc_write(codec, RT5663_MIC_DECRO_2, + rt5663->imp_table[i].dc_offset_l_manual >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_3, + rt5663->imp_table[i].dc_offset_l_manual & 0xffff); + snd_soc_write(codec, RT5663_MIC_DECRO_5, + rt5663->imp_table[i].dc_offset_r_manual >> 16); + snd_soc_write(codec, RT5663_MIC_DECRO_6, + rt5663->imp_table[i].dc_offset_r_manual & 0xffff); + } + + return 0; +} + static int rt5663_button_detect(struct snd_soc_codec *codec) { int btn_type, val; @@ -1701,6 +1889,8 @@ static void rt5663_jack_detect_work(struct work_struct *work) break; case CODEC_VER_0: report = rt5663_jack_detect(rt5663->codec, 1); + if (rt5663->pdata.impedance_sensing_num) + rt5663_impedance_sensing(rt5663->codec); break; default: dev_err(codec->dev, "Unknown CODEC Version\n"); @@ -1796,10 +1986,6 @@ static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = { }; static const struct snd_kcontrol_new rt5663_specific_controls[] = { - /* Headphone Output Volume */ - SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9, - RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1, - rt5663_hp_vol_tlv), /* Mic Boost Volume*/ SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2, RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv), @@ -1807,6 +1993,13 @@ static const struct snd_kcontrol_new rt5663_specific_controls[] = { SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum), }; +static const struct snd_kcontrol_new rt5663_hpvol_controls[] = { + /* Headphone Output Volume */ + SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9, + RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1, + rt5663_hp_vol_tlv), +}; + static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, struct snd_soc_dapm_widget *sink) { @@ -2889,6 +3082,10 @@ static int rt5663_probe(struct snd_soc_codec *codec) ARRAY_SIZE(rt5663_specific_dapm_routes)); snd_soc_add_codec_controls(codec, rt5663_specific_controls, ARRAY_SIZE(rt5663_specific_controls)); + + if (!rt5663->imp_table) + snd_soc_add_codec_controls(codec, rt5663_hpvol_controls, + ARRAY_SIZE(rt5663_hpvol_controls)); break; } @@ -3177,6 +3374,8 @@ static void rt5663_calibrate(struct rt5663_priv *rt5663) static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev) { + int table_size; + device_property_read_u32(dev, "realtek,dc_offset_l_manual", &rt5663->pdata.dc_offset_l_manual); device_property_read_u32(dev, "realtek,dc_offset_r_manual", @@ -3185,6 +3384,17 @@ static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev) &rt5663->pdata.dc_offset_l_manual_mic); device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic", &rt5663->pdata.dc_offset_r_manual_mic); + device_property_read_u32(dev, "realtek,impedance_sensing_num", + &rt5663->pdata.impedance_sensing_num); + + if (rt5663->pdata.impedance_sensing_num) { + table_size = sizeof(struct impedance_mapping_table) * + rt5663->pdata.impedance_sensing_num; + rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL); + device_property_read_u32_array(dev, + "realtek,impedance_sensing_table", + (u32 *)rt5663->imp_table, table_size); + } return 0; } -- cgit v1.2.3 From d6604145dfccc3dd9e882dd3d6bd2545c9ff64e9 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Mon, 18 Sep 2017 19:14:34 +0800 Subject: ASoC: rt5514: Add devicetree binding support for rt5514-spi Add devicetree binding support for rt5514 spi dsp codec. Signed-off-by: Jeffy Chen Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5514.txt | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt index 929ca6756b02..4f33b0d96afe 100644 --- a/Documentation/devicetree/bindings/sound/rt5514.txt +++ b/Documentation/devicetree/bindings/sound/rt5514.txt @@ -1,22 +1,27 @@ RT5514 audio CODEC -This device supports I2C only. +This device supports both I2C and SPI. Required properties: - compatible : "realtek,rt5514". -- reg : The I2C address of the device. +- reg : the I2C address of the device for I2C, the chip select + number for SPI. Optional properties: - clocks: The phandle of the master clock to the CODEC - clock-names: Should be "mclk" +- interrupt-parent: The phandle for the interrupt controller. +- interrupts: The interrupt number to the cpu. The interrupt specifier format + depends on the interrupt controller. + - realtek,dmic-init-delay-ms - Set the DMIC initial delay (ms) to wait it ready. + Set the DMIC initial delay (ms) to wait it ready for I2C. -Pins on the device (for linking into audio routes) for RT5514: +Pins on the device (for linking into audio routes) for I2C: * DMIC1L * DMIC1R -- cgit v1.2.3 From 32c30f73687a7ea5fe6add62b7bc3b520115d0d9 Mon Sep 17 00:00:00 2001 From: Franklin Cooper Date: Fri, 8 Sep 2017 15:46:36 -0500 Subject: spi: spi-davinci: Update binding for 66AK2Gx pwr dm property Add pm-domains property which is required for 66AK2Gx. Also document 66AK2G unique clocks property usage. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-davinci.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt index f5916c92fe91..1925277bfc1e 100644 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt @@ -24,6 +24,16 @@ Required properties: based on a specific SoC configuration. - interrupts: interrupt number mapped to CPU. - clocks: spi clk phandle + For 66AK2G this property should be set per binding, + Documentation/devicetree/bindings/clock/ti,sci-clk.txt + +SoC-specific Required Properties: + +The following are mandatory properties for Keystone 2 66AK2G SoCs only: + +- power-domains: Should contain a phandle to a PM domain provider node + and an args specifier containing the SPI device id + value. This property is as per the binding, Optional: - cs-gpios: gpio chip selects -- cgit v1.2.3 From 10c1705eced11d6ad710fddcdb57aaa9f85a6f98 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 8 Sep 2017 09:07:15 +0100 Subject: spi: rspi: Add r8a7743/5 to the compatible list Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-rspi.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt index 8f4169f63936..3b02b3a7cfb2 100644 --- a/Documentation/devicetree/bindings/spi/spi-rspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt @@ -5,11 +5,14 @@ Required properties: "renesas,rspi-", "renesas,rspi" as fallback. For Renesas Serial Peripheral Interface on RZ/A1H: "renesas,rspi-", "renesas,rspi-rz" as fallback. - For Quad Serial Peripheral Interface on R-Car Gen2: + For Quad Serial Peripheral Interface on R-Car Gen2 and + RZ/G1 devices: "renesas,qspi-", "renesas,qspi" as fallback. Examples with soctypes are: - "renesas,rspi-sh7757" (SH) - "renesas,rspi-r7s72100" (RZ/A1H) + - "renesas,qspi-r8a7743" (RZ/G1M) + - "renesas,qspi-r8a7745" (RZ/G1E) - "renesas,qspi-r8a7790" (R-Car H2) - "renesas,qspi-r8a7791" (R-Car M2-W) - "renesas,qspi-r8a7792" (R-Car V2H) -- cgit v1.2.3 From c737abc193d16e62e23e2fb585b8b7398ab380d8 Mon Sep 17 00:00:00 2001 From: allen yan Date: Thu, 7 Sep 2017 15:04:53 +0200 Subject: arm64: dts: marvell: Fix A37xx UART0 register size Armada-37xx UART0 registers are 0x200 bytes wide. Right next to them are the UART1 registers that should not be declared in this node. Update the example in DT bindings document accordingly. Signed-off-by: allen yan Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/serial/mvebu-uart.txt | 2 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt index 6087defd9f93..d37fabe17bd1 100644 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt @@ -8,6 +8,6 @@ Required properties: Example: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; + reg = <0x12000 0x200>; interrupts = <43>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 8c0cf7efac65..b554cdaf5e53 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -134,7 +134,7 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; + reg = <0x12000 0x200>; interrupts = ; status = "disabled"; }; -- cgit v1.2.3 From 9fda3b428a74339e358d4b0850427fa1ce1b4714 Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Mon, 4 Sep 2017 16:41:50 +0100 Subject: ASoC: arizona: Add audio device tree bindings In keeping with the style of the rest of this drivers device tree bindings split the audio device tree bindings into their own document. It should be noted this patch makes no change to the binding itself just moves the documentation into a specific file for the audio binding. For easy of merging a separate patch removes the current documentation from the MFD binding documentation. Signed-off-by: Charles Keepax Acked-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/wlf,arizona.txt | 49 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/wlf,arizona.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/wlf,arizona.txt b/Documentation/devicetree/bindings/sound/wlf,arizona.txt new file mode 100644 index 000000000000..4e67224488d8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/wlf,arizona.txt @@ -0,0 +1,49 @@ +Cirrus Logic Arizona class audio SoCs + +These devices are audio SoCs with extensive digital capabilities and a range +of analogue I/O. + +This document lists sound specific bindings, see the primary binding +document: + ../mfd/arizona.txt + +Optional properties: + + - wlf,inmode : A list of INn_MODE register values, where n is the number + of input signals. Valid values are 0 (Differential), 1 (Single-ended) and + 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. + If present, values must be specified less than or equal to the number of + input signals. If values less than the number of input signals, elements + that have not been specified are set to 0 by default. Entries are: + (wm5102, wm5110, wm8280, wm8997) + (wm8998, wm1814) + - wlf,out-mono : A list of boolean values indicating whether each output is + mono or stereo. Position within the list indicates the output affected + (eg. First entry in the list corresponds to output 1). A non-zero value + indicates a mono output. If present, the number of values should be less + than or equal to the number of outputs, if less values are supplied the + additional outputs will be treated as stereo. + + - wlf,dmic-ref : DMIC reference voltage source for each input, can be + selected from either MICVDD or one of the MICBIAS's, defines + (ARIZONA_DMIC_xxxx) are provided in . If + present, the number of values should be less than or equal to the + number of inputs, unspecified inputs will use the chip default. + + - wlf,max-channels-clocked : The maximum number of channels to be clocked on + each AIF, useful for I2S systems with multiple data lines being mastered. + Specify one cell for each AIF to be configured, specify zero for AIFs that + should be handled normally. + If present, number of cells must be less than or equal to the number of + AIFs. If less than the number of AIFs, for cells that have not been + specified the corresponding AIFs will be treated as default setting. + + - wlf,spk-fmt : PDM speaker data format, must contain 2 cells (OUT5 and OUT6). + See the datasheet for values. + The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, + wm8998, wm1814) + + - wlf,spk-mute : PDM speaker mute setting, must contain 2 cells (OUT5 and OUT6). + See the datasheet for values. + The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, + wm8998, wm1814) diff --git a/MAINTAINERS b/MAINTAINERS index 2281af4b41b6..5824962f419f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14575,6 +14575,7 @@ F: Documentation/devicetree/bindings/extcon/extcon-arizona.txt F: Documentation/devicetree/bindings/regulator/arizona-regulator.txt F: Documentation/devicetree/bindings/mfd/arizona.txt F: Documentation/devicetree/bindings/mfd/wm831x.txt +F: Documentation/devicetree/bindings/sound/wlf,arizona.txt F: arch/arm/mach-s3c64xx/mach-crag6410* F: drivers/clk/clk-wm83*.c F: drivers/extcon/extcon-arizona.c -- cgit v1.2.3 From 1d6a332ae8b7d8eacb9fe4c0a09370550f0b3eee Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:39 -0700 Subject: ARM: dts: Add missing properties for omap4 control modules On omap4, we are missing several ti,hwmods properties and IO ranges for system control modules. These are needed by the SoC interconnect code. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. In order to add these, we need to move omap4_pmx_wkup to be a child of omap4_padconf_wkup. On omap4 there are separate modules for control module and control module pads. For control module core, we have this already configured except for the missing ti,hwmods and reg entries. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/arm/omap/ctrl.txt | 2 ++ arch/arm/boot/dts/omap4.dtsi | 39 ++++++++++++++++------ 2 files changed, 31 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index 3a4e5901ce31..ce8dabf8c0f9 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -21,6 +21,8 @@ Required properties: "ti,omap3-scm" "ti,omap4-scm-core" "ti,omap4-scm-padconf-core" + "ti,omap4-scm-wkup" + "ti,omap4-scm-padconf-wkup" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" "ti,dra7-scm-core" diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 47bc41954e2e..16ec0bd29209 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -174,6 +174,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x1000>; + ti,hwmods = "ctrl_module_core"; scm_conf: scm_conf@0 { compatible = "syscon"; @@ -186,9 +187,11 @@ omap4_padconf_core: scm@100000 { compatible = "ti,omap4-scm-padconf-core", "simple-bus"; + reg = <0x100000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x100000 0x1000>; + ti,hwmods = "ctrl_module_pad_core"; omap4_pmx_core: pinmux@40 { compatible = "ti,omap4-padconf", @@ -263,17 +266,33 @@ }; }; - omap4_pmx_wkup: pinmux@1e040 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x1e040 0x0038>; + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + ti,hwmods = "ctrl_module_wkup"; + }; + + omap4_padconf_wkup: padconf@1e000 { + compatible = "ti,omap4-scm-padconf-wkup", + "simple-bus"; + reg = <0x1e000 0x1000>; #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; + #size-cells = <1>; + ranges = <0 0x1e000 0x1000>; + ti,hwmods = "ctrl_module_pad_wkup"; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; }; -- cgit v1.2.3 From 514b2da46fcc10bd5f42446b9fa746ba2c80aaf1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:41 -0700 Subject: ARM: dts: Add missing smartreflex node and binding for omap4 We are missing smartreflex device tree nodes for omap4 with their related "ti,hwmods" properties that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. And since we're missing the device tree binding for smartreflex, let's also add it and document the existing omap3 use too. Note that the related driver also needs to be updated to probe using device tree and get the platform data passed to it using auxdata with arch/arm/mach-omap2/pdata-quirks.c. Cc: Mark Rutland Cc: Nishanth Menon Cc: Rafael J. Wysocki Cc: Tero Kristo Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/power/ti-smartreflex.txt | 47 ++++++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 21 ++++++++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/ti-smartreflex.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt new file mode 100644 index 000000000000..9780957c9115 --- /dev/null +++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt @@ -0,0 +1,47 @@ +Texas Instruments SmartReflex binding + +SmartReflex is used to set and adjust the SoC operating points. + + +Required properties: + +compatible: Shall be one of the following: + "ti,omap3-smartreflex-core" + "ti,omap3-smartreflex-iva" + "ti,omap4-smartreflex-core" + "ti,omap4-smartreflex-mpu" + "ti,omap4-smartreflex-iva" + +reg: Shall contain the device instance IO range + +interrupts: Shall contain the device instance interrupt + + +Optional properties: + +ti,hwmods: Shall contain the TI interconnect module name if needed + by the SoC + + +Example: + + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_mpu"; + }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 24a3f70f1eef..c48b7e8713ca 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -442,6 +442,27 @@ clock-frequency = <48000000>; }; + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_mpu"; + }; + hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; -- cgit v1.2.3 From 0c37c56d63f4924134edd7e3af805291add56fac Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 14 Sep 2017 17:18:30 +0300 Subject: dt: Add vendor prefix 'shimafuji' Add Shimafuji Electric, Inc. to the list of device tree vendor prefixes Signed-off-by: Vladimir Barinov Acked-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index c6ef403e6321..9d46f99cc144 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -297,6 +297,7 @@ sensirion Sensirion AG sff Small Form Factor Committee sgx SGX Sensortech sharp Sharp Corporation +shimafuji Shimafuji Electric, Inc. si-en Si-En Technology Ltd. sigma Sigma Designs, Inc. sii Seiko Instruments, Inc. -- cgit v1.2.3 From 8be8576fcf2d90a8bc679bfb25a4121d0eebe0de Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 13:25:20 -0700 Subject: ARM: dts: Add missing hsi node for omap4 On omap4 we're missing the hsi node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's also update the binding accrodingly while at it. Cc: Mark Rutland Cc: Rob Herring Reviewed-by: Sebastian Reichel Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/hsi/omap-ssi.txt | 13 +++++++-- arch/arm/boot/dts/omap4.dtsi | 34 ++++++++++++++++++++++ 2 files changed, 44 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt index b8eca3c7810d..955e335e7e56 100644 --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt +++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt @@ -1,10 +1,12 @@ OMAP SSI controller bindings -OMAP Synchronous Serial Interface (SSI) controller implements a legacy -variant of MIPI's High Speed Synchronous Serial Interface (HSI). +OMAP3's Synchronous Serial Interface (SSI) controller implements a +legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI), +while the controller found inside OMAP4 is supposed to be fully compliant +with the HSI standard. Required properties: -- compatible: Should include "ti,omap3-ssi". +- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi" - reg-names: Contains the values "sys" and "gdd" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device. Required Port sub-node properties: - compatible: Should be set to the following value ti,omap3-ssi-port (applicable to OMAP34xx devices) + ti,omap4-hsi-port (applicable to OMAP44xx devices) - reg-names: Contains the values "tx" and "rx" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -38,6 +41,10 @@ Required Port sub-node properties: property. If it's missing the port will not be enabled. +Optional properties: +- ti,hwmods: Shall contain TI interconnect module name if needed + by the SoC + Example for Nokia N900: ssi-controller@48058000 { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 69d129b420e0..a3c4d3541e3d 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -624,6 +624,40 @@ dma-names = "tx", "rx"; }; + hsi: hsi@4a058000 { + compatible = "ti,omap4-hsi"; + reg = <0x4a058000 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + ti,hwmods = "hsi"; + + clocks = <&hsi_fck>; + clock-names = "hsi_fck"; + + interrupts = ; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a058000 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + }; + mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; -- cgit v1.2.3 From cd57dc5a2099a43c99fb39cb7c953246149db816 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:52 -0700 Subject: ARM: dts: Add missing hwmod related nodes for am33xx On am33xx we're missing the pmu and emif nodes with their related "ti,hwmods" properties that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's also update the related binding documentation while at it. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/memory-controllers/ti/emif.txt | 6 ++++-- arch/arm/boot/dts/am33xx.dtsi | 10 +++++++++- 2 files changed, 13 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 0db60470ebb6..fd823d6091b2 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it. Required properties: - compatible : Should be of the form "ti,emif-" where - is the IP revision of the specific EMIF instance. - For am437x should be ti,emif-am4372. + is the IP revision of the specific EMIF instance. For newer controllers, + compatible should be one of the following: + "ti,emif-am3352" + "ti,emif-am4372" - phy-type : indicating the DDR phy type. Following are the allowed values diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7d7ca054c557..08653552db71 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -128,9 +128,11 @@ }; }; - pmu { + pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; + reg = <0x4b000000 0x1000000>; + ti,hwmods = "debugss"; }; /* @@ -927,6 +929,12 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; -- cgit v1.2.3 From 4633f7a156bf41003b1527f88ddf843ce0bb7d68 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Fri, 14 Jul 2017 17:11:06 +0300 Subject: thermal: imx: Add nvmem-cells alternate binding for OCOTP access On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Add a binding for accessing the same values through the imx-ocotp nvmem driver using nvmem-cells. This is similar to other thermal drivers. The old binding is preserved for compatibility and because it still works fine on imx6qdl series chips. In theory this problem could be solved by adding a reference to the OCOTP clock instead but it is better to hide such details in a specific nvmem driver. Signed-off-by: Leonard Crestez Acked-by: Rob Herring Signed-off-by: Zhang Rui --- Documentation/devicetree/bindings/thermal/imx-thermal.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt index 3c67bd50aa10..28be51afdb6a 100644 --- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt @@ -7,10 +7,17 @@ Required properties: is higher than panic threshold, system will auto reboot by SRC module. - fsl,tempmon : phandle pointer to system controller that contains TEMPMON control registers, e.g. ANATOP on imx6q. +- nvmem-cells: A phandle to the calibration cells provided by ocotp. +- nvmem-cell-names: Should be "calib", "temp_grade". + +Deprecated properties: - fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON calibration data, e.g. OCOTP on imx6q. The details about calibration data can be found in SoC Reference Manual. +Direct access to OCOTP via fsl,tempmon-data is incorrect on some newer chips +because it does not handle OCOTP clock requirements. + Optional properties: - clocks : thermal sensor's clock source. -- cgit v1.2.3 From 3d345b5f7b2f613b6965fc3fc68de9f439752ffe Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Sep 2017 19:59:04 -0300 Subject: ASoC: tfa9879: Add device tree bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even though the tfa9879 driver can probe via device tree trough the I2C core code, it is preferable to have explicit device tree bindings instead [1], so add this support. [1] https://www.spinics.net/lists/devicetree/msg195176.html Signed-off-by: Fabio Estevam Reviewed-by: Łukasz Majewski Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/tfa9879.txt | 23 ++++++++++++++++++++++ sound/soc/codecs/tfa9879.c | 6 ++++++ 2 files changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/tfa9879.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/tfa9879.txt b/Documentation/devicetree/bindings/sound/tfa9879.txt new file mode 100644 index 000000000000..23ba522d9e2b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tfa9879.txt @@ -0,0 +1,23 @@ +NXP TFA9879 class-D audio amplifier + +Required properties: + +- compatible : "nxp,tfa9879" + +- reg : the I2C address of the device + +Example: + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: tfa9879@6c { + #sound-dai-cells = <0>; + compatible = "nxp,tfa9879"; + reg = <0x6c>; + }; +}; + diff --git a/sound/soc/codecs/tfa9879.c b/sound/soc/codecs/tfa9879.c index 95e0a7abeb7a..f8dd67ca0744 100644 --- a/sound/soc/codecs/tfa9879.c +++ b/sound/soc/codecs/tfa9879.c @@ -312,9 +312,15 @@ static const struct i2c_device_id tfa9879_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, tfa9879_i2c_id); +static const struct of_device_id tfa9879_of_match[] = { + { .compatible = "nxp,tfa9879", }, + { } +}; + static struct i2c_driver tfa9879_i2c_driver = { .driver = { .name = "tfa9879", + .of_match_table = tfa9879_of_match, }, .probe = tfa9879_i2c_probe, .remove = tfa9879_i2c_remove, -- cgit v1.2.3 From f9705438b0f7da5dd04e270a95536b36b3dca54a Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Fri, 18 Aug 2017 16:53:47 +0100 Subject: dt-bindings: misc: achc: Add device tree binding for GE ACHC Add Device Tree binding document for GE Healthcare USB Management Controller (ACHC). Signed-off-by: Martyn Welch Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/misc/ge-achc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/ge-achc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/misc/ge-achc.txt b/Documentation/devicetree/bindings/misc/ge-achc.txt new file mode 100644 index 000000000000..77df94d7a32f --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ge-achc.txt @@ -0,0 +1,26 @@ +* GE Healthcare USB Management Controller + +A device which handles data aquisition from compatible USB based peripherals. +SPI is used for device management. + +Note: This device does not expose the peripherals as USB devices. + +Required properties: + +- compatible : Should be "ge,achc" + +Required SPI properties: + +- reg : Should be address of the device chip select within + the controller. + +- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be + 1MHz for the GE ACHC. + +Example: + +spidev0: spi@0 { + compatible = "ge,achc"; + reg = <0>; + spi-max-frequency = <1000000>; +}; -- cgit v1.2.3 From 8c5b3b328b3c43bc2453c5ffa9cfdaba68c0feba Mon Sep 17 00:00:00 2001 From: Yuan Yao Date: Wed, 30 Aug 2017 18:12:37 +0800 Subject: dt-bindings: spi: Add fsl,ls1012a-dspi compatible string new compatible string: "fsl,ls1012a-dspi". Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index 13b1fcc8469e..dcc7eaada511 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -5,6 +5,7 @@ Required properties: "fsl,ls2085a-dspi" or "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi" + "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt - clocks: from common clock binding: handle to dspi clock. -- cgit v1.2.3 From b07815d4eaf658b683c345d6e643895a20d92f29 Mon Sep 17 00:00:00 2001 From: Yuan Yao Date: Wed, 30 Aug 2017 18:12:38 +0800 Subject: dt-bindings: mtd: add sst25wf040b and en25s64 to sip-nor list The chip sst25wf040b and en25s64 are compatible with SPI NOR flash. Signed-off-by: Yuan Yao Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 9ce35af8507c..4cab5d85cf6f 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -13,6 +13,7 @@ Required properties: at25df321a at25df641 at26df081a + en25s64 mr25h256 mr25h10 mr25h40 @@ -31,6 +32,7 @@ Required properties: s25fl008k s25fl064k sst25vf040b + sst25wf040b m25p40 m25p80 m25p16 -- cgit v1.2.3 From 601516a6f8cf9118a7c65ec38aa53896efc446bb Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Mon, 4 Sep 2017 16:41:52 +0100 Subject: mfd: arizona: Remove audio bindings from MFD binding document Now the audio bindings have their own binding document update the main MFD document to point to that file and remove the audio binding documentation. Signed-off-by: Charles Keepax Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/mfd/arizona.txt | 40 +---------------------- 1 file changed, 1 insertion(+), 39 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index b37bdde5cfda..bdd017686ea5 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -65,45 +65,6 @@ Optional properties: a value that is out of range for a 16 bit register then the chip default will be used. If present exactly five values must be specified. - - wlf,inmode : A list of INn_MODE register values, where n is the number - of input signals. Valid values are 0 (Differential), 1 (Single-ended) and - 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. - If present, values must be specified less than or equal to the number of - input signals. If values less than the number of input signals, elements - that have not been specified are set to 0 by default. Entries are: - (wm5102, wm5110, wm8280, wm8997) - (wm8998, wm1814) - - wlf,out-mono : A list of boolean values indicating whether each output is - mono or stereo. Position within the list indicates the output affected - (eg. First entry in the list corresponds to output 1). A non-zero value - indicates a mono output. If present, the number of values should be less - than or equal to the number of outputs, if less values are supplied the - additional outputs will be treated as stereo. - - - wlf,dmic-ref : DMIC reference voltage source for each input, can be - selected from either MICVDD or one of the MICBIAS's, defines - (ARIZONA_DMIC_xxxx) are provided in . If - present, the number of values should be less than or equal to the - number of inputs, unspecified inputs will use the chip default. - - - wlf,max-channels-clocked : The maximum number of channels to be clocked on - each AIF, useful for I2S systems with multiple data lines being mastered. - Specify one cell for each AIF to be configured, specify zero for AIFs that - should be handled normally. - If present, number of cells must be less than or equal to the number of - AIFs. If less than the number of AIFs, for cells that have not been - specified the corresponding AIFs will be treated as default setting. - - - wlf,spk-fmt : PDM speaker data format, must contain 2 cells (OUT5 and OUT6). - See the datasheet for values. - The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, - wm8998, wm1814) - - - wlf,spk-mute : PDM speaker mute setting, must contain 2 cells (OUT5 and OUT6). - See the datasheet for values. - The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, - wm8998, wm1814) - - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt @@ -112,6 +73,7 @@ Optional properties: Also see child specific device properties: Regulator - ../regulator/arizona-regulator.txt Extcon - ../extcon/extcon-arizona.txt + Sound - ../sound/arizona.txt Example: -- cgit v1.2.3 From 0340afe74d43e9c82bc0f5904d8f5b99d0fc3ab0 Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Mon, 4 Sep 2017 16:41:54 +0100 Subject: ASoC: arizona: Add device tree binding doc for volume limits Signed-off-by: Charles Keepax Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/wlf,arizona.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/wlf,arizona.txt b/Documentation/devicetree/bindings/sound/wlf,arizona.txt index 4e67224488d8..e172c62dc2df 100644 --- a/Documentation/devicetree/bindings/sound/wlf,arizona.txt +++ b/Documentation/devicetree/bindings/sound/wlf,arizona.txt @@ -47,3 +47,7 @@ Optional properties: See the datasheet for values. The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, wm8998, wm1814) + + - wlf,out-volume-limit : The volume limit value that should be applied to each + output channel. See the datasheet for exact values. Channels are specified + in the order OUT1L, OUT1R, OUT2L, OUT2R, etc. -- cgit v1.2.3 From 5418a9004126992aa2bbd07d79e8305659cb0dc9 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Sat, 16 Sep 2017 21:48:47 +0300 Subject: arm: shmobile: Document Kingfisher board DT bindings Add Kingfisher Device tree bindings Documentation, listing it as a supported board. Kingfisher is the H3ULCB/M3ULCB extension board. Signed-off-by: Vladimir Barinov Acked-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index a1f06711a4dd..e9bd3091dcf6 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -78,6 +78,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - Kingfisher (SBEV-RCAR-KF-M03) + compatible = "shimafuji,kingfisher" - Koelsch (RTP0RC7791SEB00010S) compatible = "renesas,koelsch", "renesas,r8a7791" - Kyoto Microcomputer Co. KZM-A9-Dual -- cgit v1.2.3 From e22b36bd75ad57fdf1010ce7d6d92df96311947b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 15 Sep 2017 22:43:24 +0300 Subject: arm64: renesas: document Eagle board bindings Document the Eagle device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the Eagle board. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index e9bd3091dcf6..4fa984ada912 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -59,6 +59,8 @@ Boards: compatible = "renesas,bockw", "renesas,r8a7778" - Draak (RTP0RC77995SEB0010S) compatible = "renesas,draak", "renesas,r8a77995" + - Eagle (RTP0RC77970SEB0010S) + compatible = "renesas,eagle", "renesas,r8a77970" - Genmai (RTK772100BC00000BR) compatible = "renesas,genmai", "renesas,r7s72100" - GR-Peach (X28A-M01-E/F) -- cgit v1.2.3 From e8901f3ab5b5c2ce75abdcd182b07d00fd6746fe Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 22 Sep 2017 14:58:23 +0900 Subject: dt-bindings: nand: denali: reduce the register space in the example This example allocates much more than needed for address regions. As for "denali_reg", as you see in drivers/mtd/nand/denali.h, all registers fit in 0x1000. As for "nand_data", this IP is generally configured to use Indexed Addressing mode, where there are only two registers in the address translation module (CTRL: 0x00, DATA: 0x10). Altera SOCFPGA is also this case. So, 0x20 is enough. Signed-off-by: Masahiro Yamada Acked-by: Rob Herring Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index 504291d2e5c2..0ee8edb60efc 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -29,7 +29,7 @@ nand: nand@ff900000 { #address-cells = <1>; #size-cells = <1>; compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x100000>, <0xffb80000 0x10000>; + reg = <0xff900000 0x20>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 144 4>; }; -- cgit v1.2.3 From 9ebd65cbdfbf59e7ef4b9c0c8fd767ff63f60411 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 6 Sep 2017 17:15:54 +0530 Subject: dt-bindings: sdhci-omap: Add bindings for the sdhci-omap controller Add binding for the TI's sdhci-omap controller. Signed-off-by: Kishon Vijay Abraham I Acked-by: Tony Lindgren Acked-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-omap.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-omap.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt new file mode 100644 index 000000000000..51775a372c06 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt @@ -0,0 +1,16 @@ +* TI OMAP SDHCI Controller + +Refer to mmc.txt for standard MMC bindings. + +Required properties: +- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers +- ti,hwmods: Must be "mmc", is controller instance starting 1 + +Example: + mmc1: mmc@4809c000 { + compatible = "ti,dra7-sdhci"; + reg = <0x4809c000 0x400>; + ti,hwmods = "mmc1"; + bus-width = <4>; + vmmc-supply = <&vmmc>; /* phandle to regulator node */ + }; -- cgit v1.2.3 From 6e480762aa3fb83a038761a54343e197a984821a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 3 Sep 2017 21:53:12 +0200 Subject: dt-bindings: gpu: mali-utgard: Add Rockchip Utgard Malis Some (older or lower power) Rockchip socs use Utgard-based Mali-GPUs. So add the necessary compatibles for them. As the setup is the same for all of them (needing only the additional reset line), they get added in a somewhat condensed form, to not inflate the document unnecessary. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index b4ebd56d03f3..24aacafb2594 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -13,6 +13,10 @@ Required properties: + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali + + rockchip,rk3036-mali + + rockchip,rk3066-mali + + rockchip,rk3188-mali + + rockchip,rk3228-mali + stericsson,db8500-mali - reg: Physical base address and length of the GPU registers @@ -63,6 +67,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - Rockchip variants: + Required properties: + * resets: phandle to the reset line for the GPU + - stericsson,db8500-mali Required properties: * interrupt-names and interrupts: -- cgit v1.2.3 From dc1f65c5bd04918a8975009d694fa244f433d08e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 3 Sep 2017 22:09:49 +0200 Subject: dt-bindings: gpu: mali-utgard: add optional supply regulator Mali GPUs have a separate supplying regulator in a lot of socs, so describe a mali-supply property. The already described operating points will likely also need access to this regulator. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 24aacafb2594..25ebf4140e69 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -44,6 +44,10 @@ Optional properties: Memory region to allocate from, as defined in Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt + - mali-supply: + Phandle to regulator for the Mali device, as defined in + Documentation/devicetree/bindings/regulator/regulator.txt for details. + - operating-points-v2: Operating Points for the GPU, as defined in Documentation/devicetree/bindings/opp/opp.txt -- cgit v1.2.3 From 6a4d02f88fa2b6c21d8ba645e690bdbfe6adcb1f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 15 Sep 2017 11:07:55 +0200 Subject: dt-bindings: gpu: mali-utgard: add optional power-domain reference On some socs Mali Utgard gpus have both soc power-domains and external supplying regulators, so add an optional power-domains property for reference. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 25ebf4140e69..c6814d7cc2b2 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -52,6 +52,10 @@ Optional properties: Operating Points for the GPU, as defined in Documentation/devicetree/bindings/opp/opp.txt + - power-domains: + A power domain consumer specifier as defined in + Documentation/devicetree/bindings/power/power_domain.txt + Vendor-specific bindings ------------------------ -- cgit v1.2.3 From f1f2237ff699bbc1a0265ed10407ae8d4a52008e Mon Sep 17 00:00:00 2001 From: PrasannaKumar Muralidharan Date: Wed, 23 Aug 2017 20:34:43 +0530 Subject: dt/bindings: exynos-rng: Move dt binding documentation to bindings/crypto Samsung exynos PRNG driver is using crypto framework instead of hw_random framework. So move the devicetree binding to crypto folder. Signed-off-by: PrasannaKumar Muralidharan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu --- .../devicetree/bindings/crypto/samsung,exynos-rng4.txt | 17 +++++++++++++++++ .../devicetree/bindings/rng/samsung,exynos-rng4.txt | 17 ----------------- MAINTAINERS | 2 +- 3 files changed, 18 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt delete mode 100644 Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt b/Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt new file mode 100644 index 000000000000..4ca8dd4d7e66 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt @@ -0,0 +1,17 @@ +Exynos Pseudo Random Number Generator + +Required properties: + +- compatible : Should be "samsung,exynos4-rng". +- reg : Specifies base physical address and size of the registers map. +- clocks : Phandle to clock-controller plus clock-specifier pair. +- clock-names : "secss" as a clock name. + +Example: + + rng@10830400 { + compatible = "samsung,exynos4-rng"; + reg = <0x10830400 0x200>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt b/Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt deleted file mode 100644 index 4ca8dd4d7e66..000000000000 --- a/Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt +++ /dev/null @@ -1,17 +0,0 @@ -Exynos Pseudo Random Number Generator - -Required properties: - -- compatible : Should be "samsung,exynos4-rng". -- reg : Specifies base physical address and size of the registers map. -- clocks : Phandle to clock-controller plus clock-specifier pair. -- clock-names : "secss" as a clock name. - -Example: - - rng@10830400 { - compatible = "samsung,exynos4-rng"; - reg = <0x10830400 0x200>; - clocks = <&clock CLK_SSS>; - clock-names = "secss"; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 2281af4b41b6..92df4e80a170 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11743,7 +11743,7 @@ L: linux-crypto@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/crypto/exynos-rng.c -F: Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt +F: Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt SAMSUNG FRAMEBUFFER DRIVER M: Jingoo Han -- cgit v1.2.3 From d21010789ce0efb48b56de02f57ae56cd40b6503 Mon Sep 17 00:00:00 2001 From: Roy Pledge Date: Mon, 18 Sep 2017 16:39:39 -0400 Subject: dt-bindings: soc/fsl: Update reserved memory binding for QBMan Updates the QMan and BMan device tree bindings for reserved memory nodes. This makes the reserved memory allocation compatible with the shared-dma-pool usage. Signed-off-by: Roy Pledge Acked-by: Rob Herring Signed-off-by: Li Yang --- Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +++++----- Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 ++++++++++++++++------ 2 files changed, 26 insertions(+), 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt b/Documentation/devicetree/bindings/soc/fsl/bman.txt index 47ac834414d8..48eed140765b 100644 --- a/Documentation/devicetree/bindings/soc/fsl/bman.txt +++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt @@ -65,8 +65,8 @@ to the respective BMan instance BMan Private Memory Node BMan requires a contiguous range of physical memory used for the backing store -for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as a -node under the /reserved-memory node +for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as +a node under the /reserved-memory node. The BMan FBPR memory node must be named "bman-fbpr" @@ -75,7 +75,9 @@ PROPERTIES - compatible Usage: required Value type: - Definition: Must inclide "fsl,bman-fbpr" + Definition: PPC platforms: Must include "fsl,bman-fbpr" + ARM platforms: Must include "shared-dma-pool" + as well as the "no-map" property The following constraints are relevant to the FBPR private memory: - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to @@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation memory node ranges; bman_fbpr: bman-fbpr { - compatible = "fsl,bman-fbpr"; - alloc-ranges = <0 0 0x10 0>; + compatible = "shared-mem-pool"; size = <0 0x1000000>; alignment = <0 0x1000000>; + no-map; }; }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt b/Documentation/devicetree/bindings/soc/fsl/qman.txt index 556ebb8be75d..ee96afd2af72 100644 --- a/Documentation/devicetree/bindings/soc/fsl/qman.txt +++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt @@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc Value type: Definition: Reference input clock. Its frequency is half of the platform clock +- memory-regions + Usage: Required for ARM + Value type: + Definition: List of phandles referencing the QMan private memory + nodes (described below). The qman-fqd node must be + first followed by qman-pfdr node. Only used on ARM Devices connected to a QMan instance via Direct Connect Portals (DCP) must link to the respective QMan instance @@ -74,7 +80,9 @@ QMan Private Memory Nodes QMan requires two contiguous range of physical memory used for the backing store for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). -This memory is reserved/allocated as a nodes under the /reserved-memory node +This memory is reserved/allocated as a node under the /reserved-memory node. + +For additional details about reserved memory regions see reserved-memory.txt The QMan FQD memory node must be named "qman-fqd" @@ -83,7 +91,9 @@ PROPERTIES - compatible Usage: required Value type: - Definition: Must inclide "fsl,qman-fqd" + Definition: PPC platforms: Must include "fsl,qman-fqd" + ARM platforms: Must include "shared-dma-pool" + as well as the "no-map" property The QMan PFDR memory node must be named "qman-pfdr" @@ -92,7 +102,9 @@ PROPERTIES - compatible Usage: required Value type: - Definition: Must inclide "fsl,qman-pfdr" + Definition: PPC platforms: Must include "fsl,qman-pfdr" + ARM platforms: Must include "shared-dma-pool" + as well as the "no-map" property The following constraints are relevant to the FQD and PFDR private memory: - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to @@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes ranges; qman_fqd: qman-fqd { - compatible = "fsl,qman-fqd"; - alloc-ranges = <0 0 0x10 0>; + compatible = "shared-dma-pool"; size = <0 0x400000>; alignment = <0 0x400000>; + no-map; }; qman_pfdr: qman-pfdr { - compatible = "fsl,qman-pfdr"; - alloc-ranges = <0 0 0x10 0>; + compatible = "shared-dma-pool"; size = <0 0x2000000>; alignment = <0 0x2000000>; + no-map; }; }; -- cgit v1.2.3 From b69116cd96ec641168ced9460675360fa6df84c8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 22 Aug 2017 13:23:20 +0800 Subject: dt-bindings: add compatible string for Allwinner V3s SoC The compatible string for Allwinner V3s SoC used to be missing. Add it to the binding document. Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC") Acked-by: Rob Herring Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index d2c46449b4eb..f35c6ada5a65 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,6 +14,7 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 + allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 nextthing,gr8 -- cgit v1.2.3 From 14e25a03682f7ca0464ac7e3f3f10f02d885fed4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 22 Aug 2017 13:23:22 +0800 Subject: ARM: sunxi: add support for R40 SoC Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- Documentation/arm/sunxi/README | 6 ++++++ Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/sunxi.c | 1 + 3 files changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index de791e18ccef..f8efc21998bf 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -76,6 +76,12 @@ SunXi family + Datasheet http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf + - Allwinner R40 (sun8i) + + Datasheet + https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf + + User Manual + https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf + * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 + Datasheet diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index f35c6ada5a65..e4beec3d9ad3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,6 +14,7 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 + allwinner-sun8i-r40 allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 7ab353fb25f2..5e9602ce1573 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -65,6 +65,7 @@ static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a83t", "allwinner,sun8i-h2-plus", "allwinner,sun8i-h3", + "allwinner,sun8i-r40", "allwinner,sun8i-v3s", NULL, }; -- cgit v1.2.3 From 67f2a06f14a9419bc2da0a8e6b440c6813dccdb0 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Wed, 2 Aug 2017 03:22:33 -0400 Subject: media: dt-bindings: document the CEC GPIO bindings Document the bindings for the cec-gpio module for hardware where the CEC line and optionally the HPD line are connected to GPIO lines. Signed-off-by: Hans Verkuil Reviewed-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/cec-gpio.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/cec-gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/cec-gpio.txt b/Documentation/devicetree/bindings/media/cec-gpio.txt new file mode 100644 index 000000000000..46a0bac8b3b9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/cec-gpio.txt @@ -0,0 +1,32 @@ +* HDMI CEC GPIO driver + +The HDMI CEC GPIO module supports CEC implementations where the CEC line +is hooked up to a pull-up GPIO line and - optionally - the HPD line is +hooked up to another GPIO line. + +Required properties: + - compatible: value must be "cec-gpio". + - cec-gpios: gpio that the CEC line is connected to. The line should be + tagged as open drain. + +If the CEC line is associated with an HDMI receiver/transmitter, then the +following property is also required: + + - hdmi-phandle - phandle to the HDMI controller, see also cec.txt. + +If the CEC line is not associated with an HDMI receiver/transmitter, then +the following property is optional: + + - hpd-gpios: gpio that the HPD line is connected to. + +Example for the Raspberry Pi 3 where the CEC line is connected to +pin 26 aka BCM7 aka CE1 on the GPIO pin header and the HPD line is +connected to pin 11 aka BCM17: + +#include + +cec-gpio { + compatible = "cec-gpio"; + cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From fd060b3cd585542b44335d9169c71ce40b6384ac Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Sat, 9 Sep 2017 20:32:41 +0200 Subject: dt-bindings: iio: adc: mcp320x: Update for mcp3550/1/3 All chips supported by this driver clock data out on the falling edge and latch data in on the rising edge, hence SPI mode (0,0) or (1,1) must be used. Furthermore, none of the chips has an internal reference voltage regulator, so an external supply is always required and needs to be specified in the device tree lest the IIO "scale" in sysfs cannot be calculated. Document these requirements in the device tree binding, add compatible strings for the newly supported mcp3550/1/3 and explain that SPI mode (0,0) should be preferred for these chips. Cc: Mathias Duckeck Signed-off-by: Lukas Wunner Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/mcp320x.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/mcp320x.txt b/Documentation/devicetree/bindings/iio/adc/mcp320x.txt index bcd3ac8e6e0c..7d64753df949 100644 --- a/Documentation/devicetree/bindings/iio/adc/mcp320x.txt +++ b/Documentation/devicetree/bindings/iio/adc/mcp320x.txt @@ -29,15 +29,29 @@ Required properties: "microchip,mcp3204" "microchip,mcp3208" "microchip,mcp3301" + "microchip,mcp3550-50" + "microchip,mcp3550-60" + "microchip,mcp3551" + "microchip,mcp3553" NOTE: The use of the compatibles with no vendor prefix is deprecated and only listed because old DT use them. + - spi-cpha, spi-cpol (boolean): + Either SPI mode (0,0) or (1,1) must be used, so specify + none or both of spi-cpha, spi-cpol. The MCP3550/1/3 + is more efficient in mode (1,1) as only 3 instead of + 4 bytes need to be read from the ADC, but not all SPI + masters support it. + + - vref-supply: Phandle to the external reference voltage supply. + Examples: spi_controller { mcp3x0x@0 { compatible = "mcp3002"; reg = <0>; spi-max-frequency = <1000000>; + vref-supply = <&vref_reg>; }; }; -- cgit v1.2.3 From 4d354feffff16499464d57501c034657499eee97 Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Thu, 21 Sep 2017 09:26:50 +0800 Subject: dt-bindings: adc: mt2712: add binding documention The commit adds mt2712 compatible node in binding document. Signed-off-by: Zhiyong Tao Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt index 64dc4843c180..0df9befdaecc 100644 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt @@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC. Required properties: - compatible: Should be one of: - "mediatek,mt2701-auxadc": For MT2701 family of SoCs + - "mediatek,mt2712-auxadc": For MT2712 family of SoCs - "mediatek,mt7622-auxadc": For MT7622 family of SoCs - "mediatek,mt8173-auxadc": For MT8173 family of SoCs - reg: Address range of the AUXADC unit. -- cgit v1.2.3 From 2e931b06de97d762ef139bffbbe75e1483735734 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 21 Sep 2017 11:44:59 +0200 Subject: ARM: shmobile: remove inconsistent ; from documentation Consistently do not suffix compat string documentation with a ';' Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/shmobile.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 4fa984ada912..020d758fc0c5 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -69,7 +69,7 @@ Boards: compatible = "renesas,gose", "renesas,r8a7793" - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - compatible = "renesas,h3ulcb", "renesas,r8a7795"; + compatible = "renesas,h3ulcb", "renesas,r8a7795" - Henninger compatible = "renesas,henninger", "renesas,r8a7791" - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) @@ -91,7 +91,7 @@ Boards: - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) - compatible = "renesas,m3ulcb", "renesas,r8a7796"; + compatible = "renesas,m3ulcb", "renesas,r8a7796" - Marzen (R0P7779A00010S) compatible = "renesas,marzen", "renesas,r8a7779" - Porter (M2-LCDP) @@ -99,11 +99,11 @@ Boards: - RSKRZA1 (YR0K77210C000BE) compatible = "renesas,rskrza1", "renesas,r7s72100" - Salvator-X (RTP0RC7795SIPB0010S) - compatible = "renesas,salvator-x", "renesas,r8a7795"; + compatible = "renesas,salvator-x", "renesas,r8a7795" - Salvator-X (RTP0RC7796SIPB0011S) - compatible = "renesas,salvator-x", "renesas,r8a7796"; + compatible = "renesas,salvator-x", "renesas,r8a7796" - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7795"; + compatible = "renesas,salvator-xs", "renesas,r8a7795" - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" - SK-RZG1E (YR8A77450S000BE) -- cgit v1.2.3 From 4702f4b23a2fc6196abacf515a959e69176da40e Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 25 Sep 2017 09:54:20 +0100 Subject: spi: sh-msiof: Add r8a774[35] to the compatible list Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index e865855726a2..bdd83959019c 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -1,7 +1,9 @@ Renesas MSIOF spi controller Required properties: -- compatible : "renesas,msiof-r8a7790" (R-Car H2) +- compatible : "renesas,msiof-r8a7743" (RZ/G1M) + "renesas,msiof-r8a7745" (RZ/G1E) + "renesas,msiof-r8a7790" (R-Car H2) "renesas,msiof-r8a7791" (R-Car M2-W) "renesas,msiof-r8a7792" (R-Car V2H) "renesas,msiof-r8a7793" (R-Car M2-N) @@ -10,7 +12,7 @@ Required properties: "renesas,msiof-r8a7796" (R-Car M3-W) "renesas,msiof-sh73a0" (SH-Mobile AG5) "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device) - "renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device) + "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device) "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device) "renesas,sh-msiof" (deprecated) -- cgit v1.2.3 From dedcf233ceb069c2c1d919ec74a913b39b5b4dd5 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 15 Jun 2017 15:19:02 -0700 Subject: dt-bindings: Document MIPS Broadcom STB power management nodes Document the different nodes required for supporting S2/S3/S5 suspend states on MIPS-based Broadcom STB SoCs. Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- .../devicetree/bindings/mips/brcm/soc.txt | 153 +++++++++++++++++++++ 1 file changed, 153 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.txt b/Documentation/devicetree/bindings/mips/brcm/soc.txt index e4e1cd91fb1f..356c29789cf5 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.txt +++ b/Documentation/devicetree/bindings/mips/brcm/soc.txt @@ -11,3 +11,156 @@ Required properties: The experimental -viper variants are for running Linux on the 3384's BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor. + +Power management +---------------- + +For power management (particularly, S2/S3/S5 system suspend), the following SoC +components are needed: + += Always-On control block (AON CTRL) + +This hardware provides control registers for the "always-on" (even in low-power +modes) hardware, such as the Power Management State Machine (PMSM). + +Required properties: +- compatible : should be one of + "brcm,bcm7425-aon-ctrl" + "brcm,bcm7429-aon-ctrl" + "brcm,bcm7435-aon-ctrl" and + "brcm,brcmstb-aon-ctrl" +- reg : the register start and length for the AON CTRL block + +Example: + +syscon@410000 { + compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl"; + reg = <0x410000 0x400>; +}; + += Memory controllers + +A Broadcom STB SoC typically has a number of independent memory controllers, +each of which may have several associated hardware blocks, which are versioned +independently (control registers, DDR PHYs, etc.). One might consider +describing these controllers as a parent "memory controllers" block, which +contains N sub-nodes (one for each controller in the system), each of which is +associated with a number of hardware register resources (e.g., its PHY. + +== MEMC (MEMory Controller) + +Represents a single memory controller instance. + +Required properties: +- compatible : should contain "brcm,brcmstb-memc" and "simple-bus" +- ranges : should contain the child address in the parent address + space, must be 0 here, and the register start and length of + the entire memory controller (including all sub nodes: DDR PHY, + arbiter, etc.) +- #address-cells : must be 1 +- #size-cells : must be 1 + +Example: + + memory-controller@0 { + compatible = "brcm,brcmstb-memc", "simple-bus"; + ranges = <0x0 0x0 0xa000>; + #address-cells = <1>; + #size-cells = <1>; + + memc-arb@1000 { + ... + }; + + memc-ddr@2000 { + ... + }; + + ddr-phy@6000 { + ... + }; + }; + +Should contain subnodes for any of the following relevant hardware resources: + +== DDR PHY control + +Control registers for this memory controller's DDR PHY. + +Required properties: +- compatible : should contain one of these + "brcm,brcmstb-ddr-phy-v64.5" + "brcm,brcmstb-ddr-phy" + +- reg : the DDR PHY register range and length + +Example: + + ddr-phy@6000 { + compatible = "brcm,brcmstb-ddr-phy-v64.5"; + reg = <0x6000 0xc8>; + }; + +== DDR memory controller sequencer + +Control registers for this memory controller's DDR memory sequencer + +Required properties: +- compatible : should contain one of these + "brcm,bcm7425-memc-ddr" + "brcm,bcm7429-memc-ddr" + "brcm,bcm7435-memc-ddr" and + "brcm,brcmstb-memc-ddr" + +- reg : the DDR sequencer register range and length + +Example: + + memc-ddr@2000 { + compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr"; + reg = <0x2000 0x300>; + }; + +== MEMC Arbiter + +The memory controller arbiter is responsible for memory clients allocation +(bandwidth, priorities etc.) and needs to have its contents restored during +deep sleep states (S3). + +Required properties: + +- compatible : should contain one of these + "brcm,brcmstb-memc-arb-v10.0.0.0" + "brcm,brcmstb-memc-arb" + +- reg : the DDR Arbiter register range and length + +Example: + + memc-arb@1000 { + compatible = "brcm,brcmstb-memc-arb-v10.0.0.0"; + reg = <0x1000 0x248>; + }; + +== Timers + +The Broadcom STB chips contain a timer block with several general purpose +timers that can be used. + +Required properties: + +- compatible : should contain one of: + "brcm,bcm7425-timers" + "brcm,bcm7429-timers" + "brcm,bcm7435-timers and + "brcm,brcmstb-timers" +- reg : the timers register range +- interrupts : the interrupt line for this timer block + +Example: + + timers: timer@4067c0 { + compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers"; + reg = <0x4067c0 0x40>; + interrupts = <&periph_intc 19>; + }; -- cgit v1.2.3 From 8caea502367056881e5209ca55a7a01775c9a1cd Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 8 Sep 2017 17:07:44 -0700 Subject: dt-bindings: RISC-V CPU Bindings This patch adds device tree bindings for RISC-V CPUs, patterned after the ARM device tree CPU bindings. Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.txt | 162 +++++++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/cpus.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt new file mode 100644 index 000000000000..adf7b7af5dc3 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -0,0 +1,162 @@ +=================== +RISC-V CPU Bindings +=================== + +The device tree allows to describe the layout of CPUs in a system through +the "cpus" node, which in turn contains a number of subnodes (ie "cpu") +defining properties for every cpu. + +Bindings for CPU nodes follow the Devicetree Specification, available from: + +https://www.devicetree.org/specifications/ + +with updates for 32-bit and 64-bit RISC-V systems provided in this document. + +=========== +Terminology +=========== + +This document uses some terminology common to the RISC-V community that is not +widely used, the definitions of which are listed here: + +* hart: A hardware execution context, which contains all the state mandated by + the RISC-V ISA: a PC and some registers. This terminology is designed to + disambiguate software's view of execution contexts from any particular + microarchitectural implementation strategy. For example, my Intel laptop is + described as having one socket with two cores, each of which has two hyper + threads. Therefore this system has four harts. + +===================================== +cpus and cpu node bindings definition +===================================== + +The RISC-V architecture, in accordance with the Devicetree Specification, +requires the cpus and cpu nodes to be present and contain the properties +described below. + +- cpus node + + Description: Container of cpu nodes + + The node name must be "cpus". + + A cpus node must define the following properties: + + - #address-cells + Usage: required + Value type: + Definition: must be set to 1 + - #size-cells + Usage: required + Value type: + Definition: must be set to 0 + +- cpu node + + Description: Describes a hart context + + PROPERTIES + + - device_type + Usage: required + Value type: + Definition: must be "cpu" + - reg + Usage: required + Value type: + Definition: The hart ID of this CPU node + - compatible: + Usage: required + Value type: + Definition: must contain "riscv", may contain one of + "sifive,rocket0" + - mmu-type: + Usage: optional + Value type: + Definition: Specifies the CPU's MMU type. Possible values are + "riscv,sv32" + "riscv,sv39" + "riscv,sv48" + - riscv,isa: + Usage: required + Value type: + Definition: Contains the RISC-V ISA string of this hart. These + ISA strings are defined by the RISC-V ISA manual. + +Example: SiFive Freedom U540G Development Kit +--------------------------------------------- + +This system contains two harts: a hart marked as disabled that's used for +low-level system tasks and should be ignored by Linux, and a second hart that +Linux is allowed to run on. + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu@0 { + clock-frequency = <1600000000>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L15 &L0>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu@1 { + clock-frequency = <1600000000>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L15 &L0>; + reg = <1>; + riscv,isa = "rv64imafdc"; + status = "okay"; + tlb-split; + L13: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + +Example: Spike ISA Simulator with 1 Hart +---------------------------------------- + +This device tree matches the Spike ISA golden model as run with `spike -p1`. + + cpus { + cpu@0 { + device_type = "cpu"; + reg = <0x00000000>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + clock-frequency = <0x3b9aca00>; + interrupt-controller { + #interrupt-cells = <0x00000001>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + } + } + } -- cgit v1.2.3 From 45b611c896faf29e235d9de6c7a8ceb3393c2b9c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 15 Sep 2017 04:00:02 +0200 Subject: rtc: rv3029: fix vendor string The vendor string for Microcrystal is microcrystal. Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/trivial-devices.txt | 2 +- drivers/rtc/rtc-rv3029c2.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index af284fbd4d23..aae37352c574 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -72,7 +72,6 @@ isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface -mc,rv3029c2 Real Time Clock Module with I2C-Bus mcube,mc3230 mCube 3-axis 8-bit digital accelerometer memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) @@ -141,6 +140,7 @@ microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Mem microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection +microcrystal,rv3029 Real Time Clock Module with I2C-Bus miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer diff --git a/drivers/rtc/rtc-rv3029c2.c b/drivers/rtc/rtc-rv3029c2.c index aa09771de04f..cfe3aece51d1 100644 --- a/drivers/rtc/rtc-rv3029c2.c +++ b/drivers/rtc/rtc-rv3029c2.c @@ -876,6 +876,8 @@ static const struct i2c_device_id rv3029_id[] = { MODULE_DEVICE_TABLE(i2c, rv3029_id); static const struct of_device_id rv3029_of_match[] = { + { .compatible = "microcrystal,rv3029" }, + /* Backward compatibility only, do not use compatibles below: */ { .compatible = "rv3029" }, { .compatible = "rv3029c2" }, { .compatible = "mc,rv3029c2" }, -- cgit v1.2.3 From da6789756d4e7755bc389389770335927fa96ad0 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Fri, 22 Sep 2017 09:31:29 +0200 Subject: dt-bindings: Document the STM32 DMAMUX bindings This patch adds the documentation of device tree bindings for the STM32 DMAMUX. Signed-off-by: M'boumba Cedric Madianga Signed-off-by: Pierre-Yves MORDRET Acked-by: Rob Herring Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt new file mode 100644 index 000000000000..1b893b235507 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt @@ -0,0 +1,84 @@ +STM32 DMA MUX (DMA request router) + +Required properties: +- compatible: "st,stm32h7-dmamux" +- reg: Memory map for accessing module +- #dma-cells: Should be set to <3>. + First parameter is request line number. + Second is DMA channel configuration + Third is Fifo threshold + For more details about the three cells, please see + stm32-dma.txt documentation binding file +- dma-masters: Phandle pointing to the DMA controllers. + Several controllers are allowed. Only "st,stm32-dma" DMA + compatible are supported. + +Optional properties: +- dma-channels : Number of DMA requests supported. +- dma-requests : Number of DMAMUX requests supported. +- resets: Reference to a reset controller asserting the DMA controller +- clocks: Input clock of the DMAMUX instance. + +Example: + +/* DMA controller 1 */ +dma1: dma-controller@40020000 { + compatible = "st,stm32-dma"; + reg = <0x40020000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&timer_clk>; + #dma-cells = <4>; + st,mem2mem; + resets = <&rcc 150>; + dma-channels = <8>; + dma-requests = <8>; +}; + +/* DMA controller 1 */ +dma2: dma@40020400 { + compatible = "st,stm32-dma"; + reg = <0x40020400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&timer_clk>; + #dma-cells = <4>; + st,mem2mem; + resets = <&rcc 150>; + dma-channels = <8>; + dma-requests = <8>; +}; + +/* DMA mux */ +dmamux1: dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x3c>; + #dma-cells = <3>; + dma-requests = <128>; + dma-channels = <16>; + dma-masters = <&dma1 &dma2>; + clocks = <&timer_clk>; +}; + +/* DMA client */ +usart1: serial@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&timer_clk>; + dmas = <&dmamux1 41 0x414 0>, + <&dmamux1 42 0x414 0>; + dma-names = "rx", "tx"; +}; -- cgit v1.2.3 From 6e10d19b145747c9667d40b7cf079b42d33c4c28 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Fri, 22 Sep 2017 09:31:31 +0200 Subject: dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX STM32 DMA controller has to exposed its number of request line to be addressed via STM32 DMAMUX. Signed-off-by: M'boumba Cedric Madianga Signed-off-by: Pierre-Yves MORDRET Acked-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/stm32-dma.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt index 4408af693d0c..77542e1c7bde 100644 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt @@ -13,6 +13,7 @@ Required properties: - #dma-cells : Must be <4>. See DMA client paragraph for more details. Optional properties: +- dma-requests : Number of DMA requests supported. - resets: Reference to a reset controller asserting the DMA controller - st,mem2mem: boolean; if defined, it indicates that the controller supports memory-to-memory transfer @@ -34,12 +35,13 @@ Example: #dma-cells = <4>; st,mem2mem; resets = <&rcc 150>; + dma-requests = <8>; }; * DMA client DMA clients connected to the STM32 DMA controller must use the format -described in the dma.txt file, using a five-cell specifier for each +described in the dma.txt file, using a four-cell specifier for each channel: a phandle to the DMA controller plus the following four integer cells: 1. The channel id -- cgit v1.2.3 From d25d41827fee2b489518eee99ef156b005c0c01e Mon Sep 17 00:00:00 2001 From: Stefan Brüns Date: Thu, 28 Sep 2017 03:49:28 +0200 Subject: arm: allwinner: Correct unit name in devicetree binding example MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unit-names must not start with a leading 0. Signed-off-by: Stefan Brüns Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/dma/sun6i-dma.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt index 98fbe1a5c6dd..b32e3bfdb88a 100644 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt @@ -18,7 +18,7 @@ Required properties: - #dma-cells : Should be 1, a single cell holding a line request number Example: - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <0 50 4>; -- cgit v1.2.3 From 8635d6b3afe68cdde2f646c2a3bbd8149c031e8c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sun, 1 Oct 2017 17:17:26 +0200 Subject: dt-bindings: hsi: add omap4 hsi controller bindings Update omap-ssi binding document to also cover the HSI compliant module from OMAP4. Signed-off-by: Tony Lindgren Acked-by: Rob Herring [dropped the omap.dtsi update and updated patch description accordingly] Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/hsi/omap-ssi.txt | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt index b8eca3c7810d..955e335e7e56 100644 --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt +++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt @@ -1,10 +1,12 @@ OMAP SSI controller bindings -OMAP Synchronous Serial Interface (SSI) controller implements a legacy -variant of MIPI's High Speed Synchronous Serial Interface (HSI). +OMAP3's Synchronous Serial Interface (SSI) controller implements a +legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI), +while the controller found inside OMAP4 is supposed to be fully compliant +with the HSI standard. Required properties: -- compatible: Should include "ti,omap3-ssi". +- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi" - reg-names: Contains the values "sys" and "gdd" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device. Required Port sub-node properties: - compatible: Should be set to the following value ti,omap3-ssi-port (applicable to OMAP34xx devices) + ti,omap4-hsi-port (applicable to OMAP44xx devices) - reg-names: Contains the values "tx" and "rx" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -38,6 +41,10 @@ Required Port sub-node properties: property. If it's missing the port will not be enabled. +Optional properties: +- ti,hwmods: Shall contain TI interconnect module name if needed + by the SoC + Example for Nokia N900: ssi-controller@48058000 { -- cgit v1.2.3 From dbfdd153d4aefec13460c97475737e59af92d8e2 Mon Sep 17 00:00:00 2001 From: Marco Franchi Date: Mon, 2 Oct 2017 10:45:30 -0300 Subject: dt-bindings: fsl-imx-drm: Remove incorrect "@di0" usage Improve the binding example by removing the '@di0' notation, which fixes the following build warning: Warning (unit_address_vs_reg): Node /display@di0 has a unit name, but no reg property Signed-off-by: Marco Franchi Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index f79854783c2c..5bf77f6dd19d 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -129,7 +129,7 @@ Optional properties: example: -display@di0 { +disp0 { compatible = "fsl,imx-parallel-display"; edid = [edid-data]; interface-pix-fmt = "rgb24"; -- cgit v1.2.3 From 7a08c4d514b1ee70e637bb06738b13895a318e8e Mon Sep 17 00:00:00 2001 From: Al Cooper Date: Fri, 22 Sep 2017 15:34:00 -0400 Subject: dt-bindings: Add Broadcom STB USB PHY binding document Add DT bindings document for Broadcom STB USB PHYs Acked-by: Rob Herring Signed-off-by: Al Cooper Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/brcm,brcmstb-usb-phy.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt new file mode 100644 index 000000000000..24a0d06acd1d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt @@ -0,0 +1,43 @@ +Broadcom STB USB PHY + +Required properties: + - compatible: brcm,brcmstb-usb-phy + - reg: two offset and length pairs. + The first pair specifies a manditory set of memory mapped + registers used for general control of the PHY. + The second pair specifies optional registers used by some of + the SoCs that support USB 3.x + - #phy-cells: Shall be 1 as it expects one argument for setting + the type of the PHY. Possible values are: + - PHY_TYPE_USB2 for USB1.1/2.0 PHY + - PHY_TYPE_USB3 for USB3.x PHY + +Optional Properties: +- clocks : clock phandles. +- clock-names: String, clock name. +- brcm,ipp: Boolean, Invert Port Power. + Possible values are: 0 (Don't invert), 1 (Invert) +- brcm,ioc: Boolean, Invert Over Current detection. + Possible values are: 0 (Don't invert), 1 (Invert) +NOTE: one or both of the following two properties must be set +- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. +- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. +- dr_mode: String, PHY Device mode. + Possible values are: "host", "peripheral ", "drd" or "typec-pd" + If this property is not defined, the phy will default to "host" mode. + +Example: + +usbphy_0: usb-phy@f0470200 { + reg = <0xf0470200 0xb8>, + <0xf0471940 0x6c0>; + compatible = "brcm,brcmstb-usb-phy"; + #phy-cells = <1>; + dr_mode = "host" + brcm,ioc = <1>; + brcm,ipp = <1>; + brcm,has-xhci; + brcm,has-eohci; + clocks = <&usb20>, <&usb30>; + clock-names = "sw_usb", "sw_usb3"; +}; -- cgit v1.2.3 From 06e5e0045afd5f3165ba4d11f23e448d8d2ecbd4 Mon Sep 17 00:00:00 2001 From: Jules Maselbas Date: Fri, 15 Sep 2017 18:58:46 +0200 Subject: dt-bindings: max3421: Add bindings documentation Adds bindings documentation for the max3421 driver. Signed-off-by: Jules Maselbas Acked-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/maxim,max3421.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/maxim,max3421.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/maxim,max3421.txt b/Documentation/devicetree/bindings/usb/maxim,max3421.txt new file mode 100644 index 000000000000..7536c3ab3e5a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/maxim,max3421.txt @@ -0,0 +1,24 @@ +Maxim Integrated SPI-based USB 2.0 host controller MAX3421E + +Required properties: + - compatible: "maxim,max3421" + - spi-max-frequency: maximum frequency for this device must not exceed 26 MHz. + - reg: chip select number to which this device is connected. + - maxim,vbus-en-pin: + GPOUTx is the number (1-8) of the GPOUT pin of MAX3421E to drive Vbus. + ACTIVE_LEVEL is 0 or 1. + - interrupt-parent: the phandle of the associated interrupt controller. + - interrupts: the interuption line description for the interrupt controller. + The driver configures MAX3421E for active low level triggered interrupts, + configure your interrupt line accordingly. + +Example: + + usb@0 { + compatible = "maxim,max3421"; + reg = <0>; + maxim,vbus-en-pin = <3 1>; + spi-max-frequency = <26000000>; + interrupt-parent = <&PIC>; + interrupts = <42>; + }; -- cgit v1.2.3 From 0dc262f49232ba306303a3ebc5c01e41b2e6d1af Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 28 Sep 2017 15:51:24 -0700 Subject: Arm: dts: stm32: remove extra compatible string for uart This patch removes the extra compatibility string "st,stm32-usart" to avoid confusion, save some time & space. Signed-off-by: Vikas Manocha Reviewed-by: Patrice Chotard Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/dma/stm32-dma.txt | 2 +- Documentation/devicetree/bindings/serial/st,stm32-usart.txt | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt index 4408af693d0c..6f44df94101c 100644 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt @@ -71,7 +71,7 @@ channel: a phandle to the DMA controller plus the following four integer cells: Example: usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&clk_pclk2>; diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt index 3657f9f9d17a..d150b04a6229 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt +++ b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt @@ -2,14 +2,10 @@ Required properties: - compatible: can be either: - - "st,stm32-usart", - "st,stm32-uart", - - "st,stm32f7-usart", - "st,stm32f7-uart", - - "st,stm32h7-usart" - "st,stm32h7-uart". - depending on whether the device supports synchronous mode - and is compatible with stm32(f4), stm32f7 or stm32h7. + depending is compatible with stm32(f4), stm32f7 or stm32h7. - reg: The address and length of the peripheral registers space - interrupts: - The interrupt line for the USART instance, @@ -33,7 +29,7 @@ usart4: serial@40004c00 { }; usart2: serial@40004400 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38>; clocks = <&clk_pclk1>; @@ -43,7 +39,7 @@ usart2: serial@40004400 { }; usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 0 164>; -- cgit v1.2.3 From 4038e3483c5331592d24f4ea354bb9c72c7f2d64 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 20 Sep 2017 14:29:36 +0200 Subject: dt-bindings: serial: document rs485 bindings for various devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Atmel USART, Freescale UARTs and OMAP UART all support the rs485 binding described in rs485.txt, this commit just makes that explicit. Acked-by: Nicolas Ferre Acked-by: Rob Herring Signed-off-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/atmel-usart.txt | 1 + Documentation/devicetree/bindings/serial/fsl-imx-uart.txt | 1 + Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 1 + Documentation/devicetree/bindings/serial/omap_serial.txt | 1 + 4 files changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt index e6e6142e33ac..7c0d6b2f53e4 100644 --- a/Documentation/devicetree/bindings/serial/atmel-usart.txt +++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt @@ -24,6 +24,7 @@ Optional properties: - dma-names: "rx" for RX channel, "tx" for TX channel. - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO capable USARTs. +- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt compatible description: - at91rm9200: legacy USART support diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt index 574c3a2c77d5..860a9559839a 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt @@ -9,6 +9,7 @@ Optional properties: - fsl,irda-mode : Indicate the uart supports irda mode - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works in DCE mode by default. +- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt Please check Documentation/devicetree/bindings/serial/serial.txt for the complete list of generic properties. diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index a1252a047f78..59567b51cf09 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -16,6 +16,7 @@ Required properties: Optional properties: - dmas: A list of two dma specifiers, one for each entry in dma-names. - dma-names: should contain "tx" and "rx". +- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt Note: Optional properties for DMA support. Write them both or both not. diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index 7a71b5de77d6..43eac675f21f 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -19,6 +19,7 @@ Optional properties: - dmas : DMA specifier, consisting of a phandle to the DMA controller node and a DMA channel number. - dma-names : "rx" for receive channel, "tx" for transmit channel. +- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt Example: -- cgit v1.2.3 From eeb8b4934f2e9dce2e2c9adc28ce8571e53b8aec Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Sun, 17 Sep 2017 12:33:42 +0200 Subject: nvmem: dt: document SNVS LPGPR binding Documentation bindings for the Low Power General Purpose Register available on i.MX6 SoCs in the Secure Non-Volatile Storage. Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt new file mode 100644 index 000000000000..20bc49b49799 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt @@ -0,0 +1,20 @@ +Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D +Secure Non-Volatile Storage. + +This DT node should be represented as a sub-node of a "syscon", +"simple-mfd" node. + +Required properties: +- compatible: should be one of the fallowing variants: + "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S + "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL + +Example: +snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6q-snvs-lpgpr"; + }; +}; -- cgit v1.2.3 From 2a158f888853cb11140532be79883c8faf31c83d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Oct 2017 11:30:57 +0900 Subject: reset: uniphier: add PXs3 reset data Add basic reset data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada Signed-off-by: Philipp Zabel --- .../devicetree/bindings/reset/uniphier-reset.txt | 3 +++ drivers/reset/reset-uniphier.c | 26 ++++++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index 68a6f487c409..93efed629900 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -13,6 +13,7 @@ Required properties: "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC "socionext,uniphier-ld11-reset" - for LD11 SoC "socionext,uniphier-ld20-reset" - for LD20 SoC + "socionext,uniphier-pxs3-reset" - for PXs3 SoC - #reset-cells: should be 1. Example: @@ -44,6 +45,7 @@ Required properties: "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO) "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD) "socionext,uniphier-ld20-sd-reset" - for LD20 SoC + "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC - #reset-cells: should be 1. Example: @@ -74,6 +76,7 @@ Required properties: "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC "socionext,uniphier-ld11-peri-reset" - for LD11 SoC "socionext,uniphier-ld20-peri-reset" - for LD20 SoC + "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC - #reset-cells: should be 1. Example: diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 6e40f7db4243..e8bb023ff15e 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -118,6 +118,20 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESET_END, }; +static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { + UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ + UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ + UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */ + UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */ + UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */ + UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */ + UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ + UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ + UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ + UNIPHIER_RESET_END, +}; + /* Media I/O reset data */ #define UNIPHIER_MIO_RESET_SD(id, ch) \ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) @@ -363,6 +377,10 @@ static const struct of_device_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-reset", .data = uniphier_ld20_sys_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-reset", + .data = uniphier_pxs3_sys_reset_data, + }, /* Media I/O reset, SD reset */ { .compatible = "socionext,uniphier-ld4-mio-reset", @@ -396,6 +414,10 @@ static const struct of_device_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-sd-reset", .data = uniphier_pro5_sd_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-sd-reset", + .data = uniphier_pro5_sd_reset_data, + }, /* Peripheral reset */ { .compatible = "socionext,uniphier-ld4-peri-reset", @@ -425,6 +447,10 @@ static const struct of_device_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-peri-reset", .data = uniphier_pro4_peri_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-peri-reset", + .data = uniphier_pro4_peri_reset_data, + }, /* Analog signal amplifiers reset */ { .compatible = "socionext,uniphier-ld11-adamv-reset", -- cgit v1.2.3 From 4750bc78efdb126ddc40f1b34dbae7ce319344cb Mon Sep 17 00:00:00 2001 From: "Thang Q. Nguyen" Date: Thu, 5 Oct 2017 11:21:37 +0300 Subject: usb: host: xhci support option to disable the xHCI USB2 HW LPM XHCI specification 1.1 does not require xHCI-compliant controllers to always enable hardware USB2 LPM. However, the current xHCI driver always enable it when seeing HLC=1. This patch supports an option for users to control disabling USB2 Hardware LPM via DT/ACPI attribute. This option is needed in case user would like to disable this feature. For example, their xHCI controller has its USB2 HW LPM broken. Signed-off-by: Tung Nguyen Signed-off-by: Thang Q. Nguyen Acked-by: Rob Herring Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + drivers/usb/host/xhci-plat.c | 3 +++ drivers/usb/host/xhci.c | 2 +- drivers/usb/host/xhci.h | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index 2d80b60eeabe..ae6e484a8d7c 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -26,6 +26,7 @@ Required properties: Optional properties: - clocks: reference to a clock + - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - usb3-lpm-capable: determines if platform is USB3 LPM capable - quirk-broken-port-ped: set if the controller has broken port disable mechanism diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index 163bafde709f..d0625faee8f7 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -259,6 +259,9 @@ static int xhci_plat_probe(struct platform_device *pdev) goto disable_clk; } + if (device_property_read_bool(sysdev, "usb2-lpm-disable")) + xhci->quirks |= XHCI_HW_LPM_DISABLE; + if (device_property_read_bool(sysdev, "usb3-lpm-capable")) xhci->quirks |= XHCI_LPM_SUPPORT; diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index b2ff1ff1a02f..3a8e75f6898f 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -4087,7 +4087,7 @@ static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", enable ? "enable" : "disable", port_num + 1); - if (enable) { + if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) { /* Host supports BESL timeout instead of HIRD */ if (udev->usb2_hw_lpm_besl_capable) { /* if device doesn't have a preferred BESL value use a diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 2abaa4d6d39d..dc22392711e3 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1828,6 +1828,7 @@ struct xhci_hcd { #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) #define XHCI_U2_DISABLE_WAKE (1 << 27) #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) +#define XHCI_HW_LPM_DISABLE (1 << 29) unsigned int num_active_eps; unsigned int limit_active_eps; -- cgit v1.2.3 From 69146d05ef96d91577b5e8d804b50d47b6b014f9 Mon Sep 17 00:00:00 2001 From: Dmitry Dunaev Date: Tue, 26 Sep 2017 17:49:37 +0300 Subject: Add Tecon Microprocessor Technologies, LLC vendor prefix Signed-off-by: Dmitry Dunaev Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 9d46f99cc144..5268738c3e7c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -341,6 +341,7 @@ thine THine Electronics, Inc. ti Texas Instruments tianma Tianma Micro-electronics Co., Ltd. tlm Trusted Logic Mobility +tmt Tecon Microprocessor Technologies, LLC. topeet Topeet toradex Toradex AG toshiba Toshiba Corporation -- cgit v1.2.3 From af37bed303e2b8fbdbe62e8c2c60900eb62a7fea Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 8 Sep 2017 14:45:02 +0200 Subject: PCI: v3: Update the device tree bindings The bindings for the V3 Semiconductor PCI bridge are a tad bit outdated and predates the more formal format we have adopted for the bindings. Update them a bit so it is easier to read, and add the Integrator AP- specific compatible so we can detect that we are running on that specific platform. Add a second register bank for the configuration memory area. The device tree specs do specify a memory range for configuration space but it is not applicable to custom accessors like this. Instead follow the pattern from the Versatile PCI adapter and simply add a second register bank for this memory. Signed-off-by: Linus Walleij Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring Cc: Marc Gonzalez --- .../devicetree/bindings/pci/v3-v360epc-pci.txt | 75 ++++++++++++++++++++-- 1 file changed, 68 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt index 30b364e504ba..11063293f761 100644 --- a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt +++ b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt @@ -2,14 +2,75 @@ V3 Semiconductor V360 EPC PCI bridge This bridge is found in the ARM Integrator/AP (Application Platform) -Integrator-specific notes: +Required properties: +- compatible: should be one of: + "v3,v360epc-pci" + "arm,integrator-ap-pci", "v3,v360epc-pci" +- reg: should contain two register areas: + first the base address of the V3 host bridge controller, 64KB + second the configuration area register space, 16MB +- interrupts: should contain a reference to the V3 error interrupt + as routed on the system. +- bus-range: see pci.txt +- ranges: this follows the standard PCI bindings in the IEEE Std + 1275-1994 (see pci.txt) with the following restriction: + - The non-prefetchable and prefetchable memory windows must + each be exactly 256MB (0x10000000) in size. + - The prefetchable memory window must be immediately adjacent + to the non-prefetcable memory window +- dma-ranges: three ranges for the inbound memory region. The ranges must + be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, + 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked + as pre-fetchable. Two ranges are supported by the hardware. -- syscon: should contain a link to the syscon device node (since +Integrator-specific required properties: +- syscon: should contain a link to the syscon device node, since on the Integrator, some registers in the syscon are required to - operate the V3). + operate the V3 host bridge. -V360 EPC specific notes: +Example: -- reg: should contain the base address of the V3 adapter. -- interrupts: should contain a reference to the V3 error interrupt - as routed on the system. +pci: pciv3@62000000 { + compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + clocks = <&pciclk>; + bus-range = <0x00 0xff>; + ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */ + 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ + 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ + 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ + 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ + dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ + 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ + 0x02000000 0 0x80000000 /* Core module alias memory */ + 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; +}; -- cgit v1.2.3 From a38b9267995402b89916017872a6f3ba405bcb96 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Sep 2017 16:03:40 +0200 Subject: dt-bindings: trivial: Add RTCs Add remaining trivial RTC bindings. Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/trivial-devices.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index af284fbd4d23..e3992013133e 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -41,6 +41,7 @@ dallas,ds1338 I2C RTC with 56-Byte NV RAM dallas,ds1340 I2C RTC with Trickle Charger dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output dallas,ds1631 High-Precision Digital Thermometer +dallas,ds1672 Dallas DS1672 Real-time Clock dallas,ds1682 Total-Elapsed-Time Recorder with Alarm dallas,ds1775 Tiny Digital Thermometer and Thermostat dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM @@ -56,6 +57,7 @@ domintech,dmard10 DMARD10: 3-axis Accelerometer epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE +emmicro,em3027 EM Microelectronic EM3027 Real-time Clock fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor @@ -67,6 +69,8 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM +isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM +isil,isl12022 Intersil ISL12022 Real-time Clock isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator @@ -155,6 +159,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset nxp,pcf2127 Real-time clock nxp,pcf2129 Real-time clock +nxp,pcf8523 Real-time Clock nxp,pcf8563 Real-time clock/calendar nxp,pcf85063 Tiny Real-Time Clock oki,ml86v7667 OKI ML86V7667 video decoder -- cgit v1.2.3 From b766f10f7b1b416460c05df57345bba74cd5911d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Sep 2017 16:03:41 +0200 Subject: dt-bindings: rtc: add stericsson,coh901331 bindings Add device tree bindings for the ST-Ericsson COH 901 331 Real Time Clock Signed-off-by: Alexandre Belloni Reviewed-by: Linus Walleij Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- .../devicetree/bindings/rtc/stericsson,coh901331.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt b/Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt new file mode 100644 index 000000000000..3ebeb311335f --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/stericsson,coh901331.txt @@ -0,0 +1,17 @@ +ST-Ericsson COH 901 331 Real Time Clock + +Required properties: +- compatible: must be "stericsson,coh901331" +- reg: address range of rtc register set. +- interrupt-parent: phandle for the interrupt controller. +- interrupts: rtc alarm interrupt. +- clocks: phandle to the rtc clock source + +Example: + rtc: rtc@c0017000 { + compatible = "stericsson,coh901331"; + reg = <0xc0017000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <10>; + clocks = <&rtc_clk>; + }; -- cgit v1.2.3 From 0fc52ca54aa1f6ad8a38efea2f4b072150280008 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Sep 2017 16:03:42 +0200 Subject: dt-bindings: rtc: Add sirf,prima2-sysrtc bindings Add device tree bindings for the SiRFSoC Real Time Clock. Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- .../devicetree/bindings/rtc/sirf,prima2-sysrtc.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt b/Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt new file mode 100644 index 000000000000..58885b55da21 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sirf,prima2-sysrtc.txt @@ -0,0 +1,13 @@ +SiRFSoC Real Time Clock + +Required properties: +- compatible: must be "sirf,prima2-sysrtc" +- reg: address range of rtc register set. +- interrupts: rtc alarm interrupts. + +Example: + rtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; -- cgit v1.2.3 From 13a5595892ca3cf99625085aaee4c2cb2e6dd5a5 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Sep 2017 16:03:43 +0200 Subject: dt-bindings: rtc: DS1307 and compatibles are not trivial Document optional properties for ds1307 and compatible RTCs Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- .../devicetree/bindings/rtc/rtc-ds1307.txt | 36 ++++++++++++++++++++++ .../devicetree/bindings/trivial-devices.txt | 6 ---- 2 files changed, 36 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/rtc-ds1307.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt new file mode 100644 index 000000000000..c010f18a85a0 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt @@ -0,0 +1,36 @@ +Dallas DS1307 and compatible RTC + +Required properties: +- compatible: should be one of: + "dallas,ds1307", + "dallas,ds1308", + "dallas,ds1337", + "dallas,ds1338", + "dallas,ds1339", + "dallas,ds1388", + "dallas,ds1340", + "dallas,ds1341", + "maxim,ds3231", + "st,m41t0", + "st,m41t00", + "microchip,mcp7940x", + "microchip,mcp7941x", + "pericom,pt7c4338", + "epson,rx8025", + "isil,isl12057" +- reg: I2C bus address of the device + +Optional properties: +- interrupt-parent: phandle for the interrupt controller. +- interrupts: rtc alarm interrupt. +- clock-output-names: From common clock binding to override the default output + clock name +- wakeup-source: Enables wake up of host system on alarm + +Example: + rtc1: ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + interrupt-parent = <&gpio4>; + interrupts = <20 0>; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index e3992013133e..4353151367a1 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -36,9 +36,6 @@ atmel,at97sc3204t i2c trusted platform module (TPM) capella,cm32181 CM32181: Ambient Light Sensor capella,cm3232 CM3232: Ambient Light Sensor cirrus,cs42l51 Cirrus Logic CS42L51 audio codec -dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock -dallas,ds1338 I2C RTC with 56-Byte NV RAM -dallas,ds1340 I2C RTC with Trickle Charger dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output dallas,ds1631 High-Precision Digital Thermometer dallas,ds1672 Dallas DS1672 Real-time Clock @@ -55,7 +52,6 @@ dlg,da9063 DA9063: system PMIC for quad-core application processors domintech,dmard09 DMARD09: 3-axis Accelerometer domintech,dmard10 DMARD10: 3-axis Accelerometer epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE emmicro,em3027 EM Microelectronic EM3027 Real-time Clock fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer @@ -179,8 +175,6 @@ sii,s35390a 2-wire CMOS real-time clock silabs,si7020 Relative Humidity and Temperature Sensors skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply st,24c256 i2c serial eeprom (24cxx) -st,m41t0 Serial real-time clock (RTC) -st,m41t00 Serial real-time clock (RTC) st,m41t62 Serial real-time clock (RTC) with alarm st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface -- cgit v1.2.3 From 5015391d9d6e28c85fd98d663703497dd1ec7917 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Sep 2017 16:03:44 +0200 Subject: dt-bindings: rtc: Add bindings for m41t80 and compatibles The ST M41T80 family of RTC are not trivial devices, document them. Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- .../devicetree/bindings/rtc/rtc-m41t80.txt | 31 ++++++++++++++++++++++ .../devicetree/bindings/trivial-devices.txt | 2 -- 2 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/rtc-m41t80.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt new file mode 100644 index 000000000000..717d93860af1 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt @@ -0,0 +1,31 @@ +ST M41T80 family of RTC and compatible + +Required properties: +- compatible: should be one of: + "st,m41t62", + "st,m41t65", + "st,m41t80", + "st,m41t81", + "st,m41t81s", + "st,m41t82", + "st,m41t83", + "st,m41t84", + "st,m41t85", + "st,m41t87", + "microcrystal,rv4162", +- reg: I2C bus address of the device + +Optional properties: +- interrupt-parent: phandle for the interrupt controller. +- interrupts: rtc alarm interrupt. +- clock-output-names: From common clock binding to override the default output + clock name +- wakeup-source: Enables wake up of host system on alarm + +Example: + rtc@68 { + compatible = "st,m41t80"; + reg = <0x68>; + interrupt-parent = <&UIC0>; + interrupts = <0x9 0x8>; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index 4353151367a1..4b169caab0eb 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -175,8 +175,6 @@ sii,s35390a 2-wire CMOS real-time clock silabs,si7020 Relative Humidity and Temperature Sensors skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply st,24c256 i2c serial eeprom (24cxx) -st,m41t62 Serial real-time clock (RTC) with alarm -st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface ti,ads7828 8-Channels, 12-bit ADC ti,ads7830 8-Channels, 8-bit ADC -- cgit v1.2.3 From 1620c624305f3773563996757a87eecf44cecfec Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 27 Sep 2017 16:03:45 +0200 Subject: dt-bindings: rtc: merge ds1339 in ds1307 documentation Now that there is documentation for the ds1307 and compatible RTCs, merge the ds1339 documentation in it. Signed-off-by: Alexandre Belloni Signed-off-by: Rob Herring --- .../devicetree/bindings/rtc/dallas,ds1339.txt | 18 ------------------ Documentation/devicetree/bindings/rtc/rtc-ds1307.txt | 8 ++++++++ 2 files changed, 8 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/dallas,ds1339.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt b/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt deleted file mode 100644 index 916f57601a8f..000000000000 --- a/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Dallas DS1339 I2C Serial Real-Time Clock - -Required properties: -- compatible: Should contain "dallas,ds1339". -- reg: I2C address for chip - -Optional properties: -- trickle-resistor-ohms : Selected resistor for trickle charger - Values usable for ds1339 are 250, 2000, 4000 - Should be given if trickle charger should be enabled -- trickle-diode-disable : Do not use internal trickle charger diode - Should be given if internal trickle charger diode should be disabled -Example: - ds1339: rtc@68 { - compatible = "dallas,ds1339"; - trickle-resistor-ohms = <250>; - reg = <0x68>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt index c010f18a85a0..d28d6e7f6ae8 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt +++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.txt @@ -26,6 +26,13 @@ Optional properties: - clock-output-names: From common clock binding to override the default output clock name - wakeup-source: Enables wake up of host system on alarm +- trickle-resistor-ohms : ds1339, ds1340 and ds 1388 only + Selected resistor for trickle charger + Possible values are 250, 2000, 4000 + Should be given if trickle charger should be enabled +- trickle-diode-disable : ds1339, ds1340 and ds 1388 only + Do not use internal trickle charger diode + Should be given if internal trickle charger diode should be disabled Example: rtc1: ds1339@68 { @@ -33,4 +40,5 @@ Example: reg = <0x68>; interrupt-parent = <&gpio4>; interrupts = <20 0>; + trickle-resistor-ohms = <250>; }; -- cgit v1.2.3 From 28517c02e1dd8fef7a0eab5e9f18013a0e297aba Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 8 Sep 2017 15:57:53 +0200 Subject: dt-bindings: net: document Bluetooth bindings in one place In the same way as Ethernet, gather the Bluetooth related bindings in one file. Introduce the bluetooth-bd-address property which can be used to store the assigned BD address. Signed-off-by: Loic Poulain Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/net/bluetooth.txt | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/bluetooth.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/bluetooth.txt b/Documentation/devicetree/bindings/net/bluetooth.txt new file mode 100644 index 000000000000..94797df751b8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/bluetooth.txt @@ -0,0 +1,5 @@ +The following properties are common to the Bluetooth controllers: + +- local-bd-address: array of 6 bytes, specifies the BD address that was + uniquely assigned to the Bluetooth device, formatted with least significant + byte first (little-endian). -- cgit v1.2.3 From e7868a2f71bd9f81494f0c90a64e4dd454248850 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 8 Sep 2017 15:57:54 +0200 Subject: dt-bindings: soc: qcom: Add local-bd-address property to WCNSS-BT Add optional local-bd-address property which is a 6-byte array storing the assigned BD address. Since having a unique BD address is critical, a per-device property value should be allocated. This property is usually added by the boot loader which has access to the provisioned data. Signed-off-by: Loic Poulain Signed-off-by: Marcel Holtmann --- Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt index 4ea39e9186a7..042a2e4159bd 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt @@ -37,6 +37,11 @@ The following properties are defined to the bluetooth node: Definition: must be: "qcom,wcnss-bt" +- local-bd-address: + Usage: optional + Value type: + Definition: see Documentation/devicetree/bindings/net/bluetooth.txt + == WiFi The following properties are defined to the WiFi node: @@ -91,6 +96,9 @@ smd { bt { compatible = "qcom,wcnss-bt"; + + /* BD address 00:11:22:33:44:55 */ + local-bd-address = [ 55 44 33 22 11 00 ]; }; wlan { -- cgit v1.2.3 From aee2828ccb3444ad1551e8528a868ab49ef447de Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 23 Sep 2017 16:14:01 +0200 Subject: dt-bindings: Amlogic: add documentation for the SoC info register areas There are three register areas which contain information about the SoC version and revision: - the assist registers contain the SoC's "major version" which encodes the SoC generation and part number. this is available on Meson6, Meson8 and Meson8b SoCs. - the bootrom register contains at least the SoCs "misc version". this is avilable on Meson6, Meson8 and Meson8b - the analog top registers contain information about the SoC revision. this is only available on Meson8 and Meson8b Not much else is currently known about these registers. Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic/analog-top.txt | 20 ++++++++++++++++++++ .../devicetree/bindings/arm/amlogic/assist.txt | 17 +++++++++++++++++ .../devicetree/bindings/arm/amlogic/bootrom.txt | 17 +++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/analog-top.txt create mode 100644 Documentation/devicetree/bindings/arm/amlogic/assist.txt create mode 100644 Documentation/devicetree/bindings/arm/amlogic/bootrom.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt new file mode 100644 index 000000000000..101dc21014ec --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/analog-top.txt @@ -0,0 +1,20 @@ +Amlogic Meson8 and Meson8b "analog top" registers: +-------------------------------------------------- + +The analog top registers contain information about the so-called +"metal revision" (which encodes the "minor version") of the SoC. + +Required properties: +- reg: the register range of the analog top registers +- compatible: depending on the SoC this should be one of: + - "amlogic,meson8-analog-top" + - "amlogic,meson8b-analog-top" + along with "syscon" + + +Example: + + analog_top: analog-top@81a8 { + compatible = "amlogic,meson8-analog-top", "syscon"; + reg = <0x81a8 0x14>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/assist.txt b/Documentation/devicetree/bindings/arm/amlogic/assist.txt new file mode 100644 index 000000000000..7656812b67b9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/assist.txt @@ -0,0 +1,17 @@ +Amlogic Meson6/Meson8/Meson8b assist registers: +----------------------------------------------- + +The assist registers contain basic information about the SoC, +for example the encoded SoC part number. + +Required properties: +- reg: the register range of the assist registers +- compatible: should be "amlogic,meson-mx-assist" along with "syscon" + + +Example: + + assist: assist@7c00 { + compatible = "amlogic,meson-mx-assist", "syscon"; + reg = <0x7c00 0x200>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt new file mode 100644 index 000000000000..407e27f230ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/bootrom.txt @@ -0,0 +1,17 @@ +Amlogic Meson6/Meson8/Meson8b bootrom: +-------------------------------------- + +The bootrom register area can be used to access SoC specific +information, such as the "misc version". + +Required properties: +- reg: the register range of the bootrom registers +- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon" + + +Example: + + bootrom: bootrom@d9040000 { + compatible = "amlogic,meson-mx-bootrom", "syscon"; + reg = <0xd9040000 0x10000>; + }; -- cgit v1.2.3 From b330213d98c357859b686b77ad0db9e98fe73763 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 25 Sep 2017 16:53:50 +0200 Subject: Documentation: devicetree: add pxa3xx compatible and syscon property Document the new pxa3xx_nand driver compatible string for A7k/A8k SoCs that need to access system controller registers in order to enable the NAND controller through the use of a phandle pointed to by the 'marvell,system-controller' property. Signed-off-by: Miquel Raynal Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt index d9b655f11048..d4ee4da58463 100644 --- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt +++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt @@ -5,9 +5,13 @@ Required properties: - compatible: Should be set to one of the following: marvell,pxa3xx-nand marvell,armada370-nand + marvell,armada-8k-nand - reg: The register base for the controller - interrupts: The interrupt to map - #address-cells: Set to <1> if the node includes partitions + - marvell,system-controller: Set to retrieve the syscon node that handles + NAND controller related registers (only required + with marvell,armada-8k-nand compatible). Optional properties: -- cgit v1.2.3 From 18d59893eb2e836c920856772ead554eb461ef72 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Thu, 28 Sep 2017 17:36:40 +0200 Subject: dt-bindings: Document the STM32 MDMA bindings This patch adds documentation of device tree bindings for the STM32 MDMA controller. Signed-off-by: M'boumba Cedric Madianga Signed-off-by: Pierre-Yves MORDRET Acked-by: Rob Herring Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/stm32-mdma.txt | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/stm32-mdma.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt new file mode 100644 index 000000000000..d18772d6bc65 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt @@ -0,0 +1,94 @@ +* STMicroelectronics STM32 MDMA controller + +The STM32 MDMA is a general-purpose direct memory access controller capable of +supporting 64 independent DMA channels with 256 HW requests. + +Required properties: +- compatible: Should be "st,stm32h7-mdma" +- reg: Should contain MDMA registers location and length. This should include + all of the per-channel registers. +- interrupts: Should contain the MDMA interrupt. +- clocks: Should contain the input clock of the DMA instance. +- resets: Reference to a reset controller asserting the DMA controller. +- #dma-cells : Must be <5>. See DMA client paragraph for more details. + +Optional properties: +- dma-channels: Number of DMA channels supported by the controller. +- dma-requests: Number of DMA request signals supported by the controller. +- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via + AHB bus. + +Example: + + mdma1: dma@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&timer_clk>; + resets = <&rcc 992>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + st,ahb-addr-masks = <0x20000000>, <0x00000000>; + }; + +* DMA client + +DMA clients connected to the STM32 MDMA controller must use the format +described in the dma.txt file, using a five-cell specifier for each channel: +a phandle to the MDMA controller plus the following five integer cells: + +1. The request line number +2. The priority level + 0x00: Low + 0x01: Medium + 0x10: High + 0x11: Very high +3. A 32bit mask specifying the DMA channel configuration + -bit 0-1: Source increment mode + 0x00: Source address pointer is fixed + 0x10: Source address pointer is incremented after each data transfer + 0x11: Source address pointer is decremented after each data transfer + -bit 2-3: Destination increment mode + 0x00: Destination address pointer is fixed + 0x10: Destination address pointer is incremented after each data + transfer + 0x11: Destination address pointer is decremented after each data + transfer + -bit 8-9: Source increment offset size + 0x00: byte (8bit) + 0x01: half-word (16bit) + 0x10: word (32bit) + 0x11: double-word (64bit) + -bit 10-11: Destination increment offset size + 0x00: byte (8bit) + 0x01: half-word (16bit) + 0x10: word (32bit) + 0x11: double-word (64bit) +-bit 25-18: The number of bytes to be transferred in a single transfer + (min = 1 byte, max = 128 bytes) +-bit 29:28: Trigger Mode + 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) + 0x01: Each MDMA request triggers a block transfer (max 64K bytes) + 0x10: Each MDMA request triggers a repeated block transfer + 0x11: Each MDMA request triggers a linked list transfer +4. A 32bit value specifying the register to be used to acknowledge the request + if no HW ack signal is used by the MDMA client +5. A 32bit mask specifying the value to be written to acknowledge the request + if no HW ack signal is used by the MDMA client + +Example: + + i2c4: i2c@5c002000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c002000 0x400>; + interrupts = <95>, + <96>; + clocks = <&timer_clk>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, + <&mdma1 37 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; -- cgit v1.2.3 From 5543de66e26776c20ecfb9e498c2561d74823ec3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 6 Oct 2017 18:15:17 +0100 Subject: dmaengine: usb-dmac: Add compatible string for r8a7743/5 This patch adds support for r8a7743/5 SoCs. The Renesas RZ/G1[ME] (R8A7743/5) usbdmac engine is identical to the R-Car Gen2 family. No driver change is needed due to the fallback compatible value "renesas,r8a7743-usb-dmac". Adding the SoC-specific compatible values here has two purposes: 1. Document which SoCs have this hardware module, 2. Allow checkpatch to validate compatible values. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index 1be6941ac1e5..f3d1f151ba80 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -3,6 +3,8 @@ Required Properties: -compatible: "renesas,-usb-dmac", "renesas,usb-dmac" as fallback. Examples with soctypes are: + - "renesas,r8a7743-usb-dmac" (RZ/G1M) + - "renesas,r8a7745-usb-dmac" (RZ/G1E) - "renesas,r8a7790-usb-dmac" (R-Car H2) - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - "renesas,r8a7793-usb-dmac" (R-Car M2-N) -- cgit v1.2.3 From c40610198f35e8264f9175dafe74db6288a07eda Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 4 Oct 2017 08:38:23 +0200 Subject: soc: samsung: Remove Exynos4212 related dead code Support for Exynos4212 SoCs has been removed by commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), so there is no need to keep remaining dead code related to this SoC version. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 - drivers/soc/samsung/exynos-pmu.c | 9 --------- drivers/soc/samsung/exynos-pmu.h | 2 -- drivers/soc/samsung/exynos4-pmu.c | 13 ++----------- 4 files changed, 2 insertions(+), 23 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index bf5fc59a6938..87ed95512b63 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt @@ -4,7 +4,6 @@ Properties: - compatible : should contain two values. First value must be one from following list: - "samsung,exynos3250-pmu" - for Exynos3250 SoC, - "samsung,exynos4210-pmu" - for Exynos4210 SoC, - - "samsung,exynos4212-pmu" - for Exynos4212 SoC, - "samsung,exynos4412-pmu" - for Exynos4412 SoC, - "samsung,exynos5250-pmu" - for Exynos5250 SoC, - "samsung,exynos5260-pmu" - for Exynos5260 SoC. diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index bd4a76f27bc2..938f8ccfcb74 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -60,12 +60,6 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) if (pmu_data->powerdown_conf_extra) pmu_data->powerdown_conf_extra(mode); - - if (pmu_data->pmu_config_extra) { - for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) - pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], - pmu_data->pmu_config_extra[i].offset); - } } /* @@ -88,9 +82,6 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos4210-pmu", .data = exynos_pmu_data_arm_ptr(exynos4210_pmu_data), - }, { - .compatible = "samsung,exynos4212-pmu", - .data = exynos_pmu_data_arm_ptr(exynos4212_pmu_data), }, { .compatible = "samsung,exynos4412-pmu", .data = exynos_pmu_data_arm_ptr(exynos4412_pmu_data), diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 40d4229abfb5..86b3f2f8966d 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -23,7 +23,6 @@ struct exynos_pmu_conf { struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; - const struct exynos_pmu_conf *pmu_config_extra; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); @@ -36,7 +35,6 @@ extern void __iomem *pmu_base_addr; /* list of all exported SoC specific data */ extern const struct exynos_pmu_data exynos3250_pmu_data; extern const struct exynos_pmu_data exynos4210_pmu_data; -extern const struct exynos_pmu_data exynos4212_pmu_data; extern const struct exynos_pmu_data exynos4412_pmu_data; extern const struct exynos_pmu_data exynos5250_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; diff --git a/drivers/soc/samsung/exynos4-pmu.c b/drivers/soc/samsung/exynos4-pmu.c index bc4fa73bed11..5dbfe4e31f4c 100644 --- a/drivers/soc/samsung/exynos4-pmu.c +++ b/drivers/soc/samsung/exynos4-pmu.c @@ -90,7 +90,7 @@ static const struct exynos_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -195,10 +195,6 @@ static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, @@ -212,11 +208,6 @@ const struct exynos_pmu_data exynos4210_pmu_data = { .pmu_config = exynos4210_pmu_config, }; -const struct exynos_pmu_data exynos4212_pmu_data = { - .pmu_config = exynos4x12_pmu_config, -}; - const struct exynos_pmu_data exynos4412_pmu_data = { - .pmu_config = exynos4x12_pmu_config, - .pmu_config_extra = exynos4412_pmu_config, + .pmu_config = exynos4412_pmu_config, }; -- cgit v1.2.3 From 4a9cfe47b8ea3f7b8c551a365184f4aec993ee5d Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 4 Oct 2017 16:07:24 -0500 Subject: dt-bindings: pinctrl: Add support for RZ/A1M and RZ/A1L Describe how to specify RZ/A1M and RZ/A1L devices. Signed-off-by: Chris Brandt Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt index 43e21474528a..fd3696eb36bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -12,8 +12,10 @@ Pin controller node ------------------- Required properties: - - compatible - this shall be "renesas,r7s72100-ports". + - compatible: should be: + - "renesas,r7s72100-ports": for RZ/A1H + - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M + - "renesas,r7s72102-ports": for RZ/A1L - reg address base and length of the memory area where the pin controller -- cgit v1.2.3 From b091b9ed1b133455dd46346411dfa7526e889a8f Mon Sep 17 00:00:00 2001 From: "Ismail H. Kose" Date: Fri, 22 Sep 2017 13:12:09 -0700 Subject: iio:dac: Add DT binding documentation for ds4424 Signed-off-by: Ismail H. Kose Signed-off-by: Ismail H. Kose Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/dac/ds4424.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/ds4424.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/dac/ds4424.txt b/Documentation/devicetree/bindings/iio/dac/ds4424.txt new file mode 100644 index 000000000000..eaebbf8dab40 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/ds4424.txt @@ -0,0 +1,20 @@ +Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC Device Driver + +Datasheet publicly available at: +https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf + +Required properties: + - compatible: Should be one of + maxim,ds4422 + maxim,ds4424 + - reg: Should contain the DAC I2C address + +Optional properties: + - vcc-supply: Power supply is optional. If not defined, driver will ignore it. + +Example: + ds4224@10 { + compatible = "maxim,ds4424"; + reg = <0x10>; /* When A0, A1 pins are ground */ + vcc-supply = <&vcc_3v3>; + }; -- cgit v1.2.3 From 7886082dfb6ab8221b1b5509a582256040820c2e Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Wed, 30 Aug 2017 13:50:43 +0200 Subject: dt-bindings: iio: accel: add LIS2DW12 sensor device binding Signed-off-by: Lorenzo Bianconi Acked-by: Rob Herring Reviewed-by: Linus Walleij Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st-sensors.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index 678c035d9ed6..9cfc82d21792 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -46,6 +46,7 @@ Accelerometers: - st,h3lis331dl-accel - st,lng2dm-accel - st,lis3l02dq +- st,lis2dw12 Gyroscopes: - st,l3g4200d-gyro -- cgit v1.2.3 From 19f3f22aade704f9ce82a55c853381e672629a1d Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 6 Oct 2017 17:39:19 +0100 Subject: dt-bindings: PCI: designware: Add binding for Designware PCIe in ECAM mode Describe the binding for firmware-configured instances of the Synopsys DesignWare PCIe controller in RC mode, that are almost but not quite ECAM compliant. Signed-off-by: Ard Biesheuvel Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring --- .../bindings/pci/designware-pcie-ecam.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt new file mode 100644 index 000000000000..515b2f9542e5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt @@ -0,0 +1,42 @@ +* Synopsys DesignWare PCIe root complex in ECAM shift mode + +In some cases, firmware may already have configured the Synopsys DesignWare +PCIe controller in RC mode with static ATU window mappings that cover all +config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. +In this case, there is no need for the OS to perform any low level setup +of clocks, PHYs or device registers, nor is there any reason for the driver +to reconfigure ATU windows for config and/or IO space accesses at runtime. + +In cases where the IP was synthesized with a minimum ATU window size of +64 KB, it cannot be supported by the generic ECAM driver, because it +requires special config space accessors that filter accesses to device #1 +and beyond on the first bus. + +Required properties: +- compatible: "marvell,armada8k-pcie-ecam" or + "socionext,synquacer-pcie-ecam" or + "snps,dw-pcie-ecam" (must be preceded by a more specific match) + +Please refer to the binding document of "pci-host-ecam-generic" in the +file host-generic-pci.txt for a description of the remaining required +and optional properties. + +Example: + + pcie1: pcie@7f000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x7f000000 0x0 0xf00000>; + bus-range = <0x0 0xe>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, + <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; + msi-map = <0x0 &its 0x0 0x10000>; + dma-coherent; + }; -- cgit v1.2.3 From 3888ffd0c76110e8f45523e3ede842699a2c6614 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sun, 17 Sep 2017 18:17:12 +0200 Subject: dt-bindings: iio: accel: add LIS3DHH device bindings Signed-off-by: Lorenzo Bianconi Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st-sensors.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt index 9cfc82d21792..6f626f73417e 100644 --- a/Documentation/devicetree/bindings/iio/st-sensors.txt +++ b/Documentation/devicetree/bindings/iio/st-sensors.txt @@ -47,6 +47,7 @@ Accelerometers: - st,lng2dm-accel - st,lis3l02dq - st,lis2dw12 +- st,lis3dhh Gyroscopes: - st,l3g4200d-gyro -- cgit v1.2.3 From b6891523fe9915dfa868773db638832454316788 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 10 Oct 2017 14:14:40 -0700 Subject: dt-bindings: bus: Minimal TI sysc interconnect target module binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the recently introduced omap clkctrl module binding, we can start moving omap hwmod data to device tree and drivers from arch/arm/mach-omap2. To start doing this, let's introduce a device tree binding for TI sysc interconnect target module hardware. The sysc manages module clocks, idlemodes and interconnect level resets. Each interconnect target module can have one or more child devices connected to it. TI sysc interconnect target module hardware is independent of the interconnect. It is used at least with TI L3 interconnect (Arteris NoC) and TI L4 interconnect (Sonics s3220). The sysc is mostly used for interaction between module and PRCM. It participates in the OCP Disconnect Protocol but other than that is mostly indepenent of the interconnect. As all the features may not be supported for a given sysc module, we need to use device tree configuration for the revision of the interconnect target module. Note that the interconnect target module control registers are always sprinked at varying locations in the unused address space of the first child device IP block. To avoid device tree reg conflicts, the sysc device provides ranges for it's children. For a non-intrusive transition from static hwmod data to using device tree defined TI interconnect target module binding, we can keep things working with static hwmod data if device tree property "ti,hwmods" is specified for the the interconnect target module. Note that additional properties for sysc capabilities will be added later on. For now, we can already use this binding for interconnect target modules that do not have any child device drivers available. This allows us to idle the unused interconnect target modules during init without the need for legacy hwmod platform data for doing it. Cc: Benoît Cousson Cc: Dave Gerlach Cc: Laurent Pinchart Cc: Liam Girdwood Cc: Mark Brown Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Nishanth Menon Cc: Matthijs van Duin Cc: Paul Walmsley Cc: Peter Ujfalusi Cc: Sakari Ailus Cc: Suman Anna Cc: Tero Kristo Cc: Tomi Valkeinen Reviewed-by: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/bus/ti-sysc.txt | 93 +++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt new file mode 100644 index 000000000000..fb1790e39398 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -0,0 +1,93 @@ +Texas Instruments sysc interconnect target module wrapper binding + +Texas Instruments SoCs can have a generic interconnect target module +hardware for devices connected to various interconnects such as L3 +interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc +is mostly used for interaction between module and PRCM. It participates +in the OCP Disconnect Protocol but other than that is mostly independent +of the interconnect. + +Each interconnect target module can have one or more devices connected to +it. There is a set of control registers for managing interconnect target +module clocks, idle modes and interconnect level resets for the module. + +These control registers are sprinkled into the unused register address +space of the first child device IP block managed by the interconnect +target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. + +Required standard properties: + +- compatible shall be one of the following generic types: + + "ti,sysc-omap2" + "ti,sysc-omap4" + "ti,sysc-omap4-simple" + + or one of the following derivative types for hardware + needing special workarounds: + + "ti,sysc-omap3430-sr" + "ti,sysc-omap3630-sr" + "ti,sysc-omap4-sr" + "ti,sysc-omap3-sham" + "ti,sysc-omap-aes" + "ti,sysc-mcasp" + "ti,sysc-usb-host-fs" + +- reg shall have register areas implemented for the interconnect + target module in question such as revision, sysc and syss + +- reg-names shall contain the register names implemented for the + interconnect target module in question such as + "rev, "sysc", and "syss" + +- ranges shall contain the interconnect target module IO range + available for one or more child device IP blocks managed + by the interconnect target module, the ranges may include + multiple ranges such as device L4 range for control and + parent L3 range for DMA access + +Optional properties: + +- clocks clock specifier for each name in the clock-names as + specified in the binding documentation for ti-clkctrl, + typically available for all interconnect targets on TI SoCs + based on omap4 except if it's read-only register in hwauto + mode as for example omap4 L4_CFG_CLKCTRL + +- clock-names should contain at least "fck", and optionally also "ick" + depending on the SoC and the interconnect target module + +- ti,hwmods optional TI interconnect module name to use legacy + hwmod platform data + + +Example: Single instance of MUSB controller on omap4 using interconnect ranges +using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): + + target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ + compatible = "ti,sysc-omap2"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + + usb_otg_hs: otg@0 { + compatible = "ti,omap4-musb"; + reg = <0x0 0x7ff>; + interrupts = , + ; + usb-phy = <&usb2_phy>; + ... + }; + }; + +Note that other SoCs, such as am335x can have multipe child devices. On am335x +there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA +instance as children of a single interconnet target module. -- cgit v1.2.3 From a157789b78f4e95f5d66f8b564356e396716f67e Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Thu, 5 Oct 2017 09:50:02 +0200 Subject: dt-bindings: pinctrl: Move mcp23s08 from gpio The mcp23s08 driver was moved from gpio to pinctrl. This moves it's devicetree binding doc as well. So driver and binding doc are in sync again. Signed-off-by: Lars Poeschel Reviewed-by: Sebastian Reichel Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-mcp23s08.txt | 83 ---------------------- .../bindings/pinctrl/pinctrl-mcp23s08.txt | 83 ++++++++++++++++++++++ 2 files changed, 83 insertions(+), 83 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt deleted file mode 100644 index c934106b10aa..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt +++ /dev/null @@ -1,83 +0,0 @@ -Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for -8-/16-bit I/O expander with serial interface (I2C/SPI) - -Required properties: -- compatible : Should be - - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version - - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version - - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or - - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip - - - "microchip,mcp23s08" for 8 GPIO SPI version - - "microchip,mcp23s17" for 16 GPIO SPI version - - "microchip,mcp23s18" for 16 GPIO SPI version - - "microchip,mcp23008" for 8 GPIO I2C version or - - "microchip,mcp23017" for 16 GPIO I2C version of the chip - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- #gpio-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. Flags are currently unused. -- gpio-controller : Marks the device node as a GPIO controller. -- reg : For an address on its bus. I2C uses this a the I2C address of the chip. - SPI uses this to specify the chipselect line which the chip is - connected to. The driver and the SPI variant of the chip support - multiple chips on the same chipselect. Have a look at - microchip,spi-present-mask below. - -Required device specific properties (only for SPI chips): -- mcp,spi-present-mask (DEPRECATED) -- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI - chips - as the name suggests. Multiple SPI chips can share the same - SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a - chip connected with the corresponding spi address set. For example if - you have a chip with address 3 connected, you have to set bit3 to 1, - which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not - possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at - least one bit to 1 for SPI chips. - NOTE: Do not use the old mcp prefix any more. It is deprecated and will be - removed. -- spi-max-frequency = The maximum frequency this chip is able to handle - -Optional properties: -- #interrupt-cells : Should be two. - - first cell is the pin number - - second cell is used to specify flags. -- interrupt-controller: Marks the device node as a interrupt controller. - -Optional device specific properties: -- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices - with two interrupt outputs (these are the devices ending with 17 and - those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and - IO 8-15 are bank 2. These chips have two different interrupt outputs: - One for bank 1 and another for bank 2. If irq-mirror is set, both - interrupts are generated regardless of the bank that an input change - occurred on. If it is not set, the interrupt are only generated for the - bank they belong to. - On devices with only one interrupt output this property is useless. -- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This - configures the IRQ output polarity as active high. - -Example I2C (with interrupt): -gpiom1: gpio@20 { - compatible = "microchip,mcp23017"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells=<2>; - microchip,irq-mirror; -}; - -Example SPI: -gpiom1: gpio@0 { - compatible = "microchip,mcp23s17"; - gpio-controller; - #gpio-cells = <2>; - spi-present-mask = <0x01>; - reg = <0>; - spi-max-frequency = <1000000>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt new file mode 100644 index 000000000000..c934106b10aa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -0,0 +1,83 @@ +Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for +8-/16-bit I/O expander with serial interface (I2C/SPI) + +Required properties: +- compatible : Should be + - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version + - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version + - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or + - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip + + - "microchip,mcp23s08" for 8 GPIO SPI version + - "microchip,mcp23s17" for 16 GPIO SPI version + - "microchip,mcp23s18" for 16 GPIO SPI version + - "microchip,mcp23008" for 8 GPIO I2C version or + - "microchip,mcp23017" for 16 GPIO I2C version of the chip + NOTE: Do not use the old mcp prefix any more. It is deprecated and will be + removed. +- #gpio-cells : Should be two. + - first cell is the pin number + - second cell is used to specify flags. Flags are currently unused. +- gpio-controller : Marks the device node as a GPIO controller. +- reg : For an address on its bus. I2C uses this a the I2C address of the chip. + SPI uses this to specify the chipselect line which the chip is + connected to. The driver and the SPI variant of the chip support + multiple chips on the same chipselect. Have a look at + microchip,spi-present-mask below. + +Required device specific properties (only for SPI chips): +- mcp,spi-present-mask (DEPRECATED) +- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI + chips - as the name suggests. Multiple SPI chips can share the same + SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a + chip connected with the corresponding spi address set. For example if + you have a chip with address 3 connected, you have to set bit3 to 1, + which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not + possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at + least one bit to 1 for SPI chips. + NOTE: Do not use the old mcp prefix any more. It is deprecated and will be + removed. +- spi-max-frequency = The maximum frequency this chip is able to handle + +Optional properties: +- #interrupt-cells : Should be two. + - first cell is the pin number + - second cell is used to specify flags. +- interrupt-controller: Marks the device node as a interrupt controller. + +Optional device specific properties: +- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices + with two interrupt outputs (these are the devices ending with 17 and + those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and + IO 8-15 are bank 2. These chips have two different interrupt outputs: + One for bank 1 and another for bank 2. If irq-mirror is set, both + interrupts are generated regardless of the bank that an input change + occurred on. If it is not set, the interrupt are only generated for the + bank they belong to. + On devices with only one interrupt output this property is useless. +- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This + configures the IRQ output polarity as active high. + +Example I2C (with interrupt): +gpiom1: gpio@20 { + compatible = "microchip,mcp23017"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells=<2>; + microchip,irq-mirror; +}; + +Example SPI: +gpiom1: gpio@0 { + compatible = "microchip,mcp23s17"; + gpio-controller; + #gpio-cells = <2>; + spi-present-mask = <0x01>; + reg = <0>; + spi-max-frequency = <1000000>; +}; -- cgit v1.2.3 From e8527b6eb6ffdccc45b58646312cfe42365b74b0 Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Mon, 9 Oct 2017 14:03:00 +0200 Subject: dt-bindings: pinctrl: mcp23s08 update binding doc The mcp23s08 driver moved to pinctrl recently. It accepts the bias-pull-up pinctrl property since then. This updates the binding doc to reflect that. Thanks to Sebastian Reichel for the working example. Signed-off-by: Lars Poeschel Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-mcp23s08.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt index c934106b10aa..b7a0e868ec13 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -81,3 +81,61 @@ gpiom1: gpio@0 { reg = <0>; spi-max-frequency = <1000000>; }; + +Pull-up configuration +===================== + +If pins are used as output, they can also be configured with pull-ups. This is +done with pinctrl. + +Please refer file +for details of the common pinctrl bindings used by client devices, +including the meaning of the phrase "pin configuration node". + +Optional Pinmux properties: +-------------------------- +Following properties are required if default setting of pins are required +at boot. +- pinctrl-names: A pinctrl state named per . +- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per + . + +The pin configurations are defined as child of the pinctrl states node. Each +sub-node have following properties: + +Required properties: +------------------ +- pins: List of pins. Valid values of pins properties are: + gpio0 ... gpio7 for the devices with 8 GPIO pins and + gpio0 ... gpio15 for the devices with 16 GPIO pins. + +Optional properties: +------------------- +The following optional property is defined in the pinmux DT binding document +. Absence of this property will leave the configuration +in its default state. + bias-pull-up + +Example with pinctrl to pull-up output pins: +gpio21: gpio@21 { + compatible = "microchip,mcp23017"; + gpio-controller; + #gpio-cells = <0x2>; + reg = <0x21>; + interrupt-parent = <&socgpio>; + interrupts = <0x17 0x8>; + interrupt-names = "mcp23017@21 irq"; + interrupt-controller; + #interrupt-cells = <0x2>; + microchip,irq-mirror; + pinctrl-names = "default"; + pinctrl-0 = <&i2cgpio0irq &gpio21pullups>; + + gpio21pullups: pinmux { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + bias-pull-up; + }; +}; -- cgit v1.2.3 From b889372c843b2a2c4aa776c85bca31636fd38d90 Mon Sep 17 00:00:00 2001 From: Phil Reid Date: Fri, 6 Oct 2017 13:08:06 +0800 Subject: dt-bindings: pinctrl: add mcp23018 to mcp23s08 documentation This adds the compatible string for the mcp23018, which is the i2c variant of the mcp23s18. Signed-off-by: Phil Reid Reviewed-by: Sebastian Reichel Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt index b7a0e868ec13..9c451c20dda4 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -13,6 +13,7 @@ Required properties: - "microchip,mcp23s18" for 16 GPIO SPI version - "microchip,mcp23008" for 8 GPIO I2C version or - "microchip,mcp23017" for 16 GPIO I2C version of the chip + - "microchip,mcp23018" for 16 GPIO I2C version NOTE: Do not use the old mcp prefix any more. It is deprecated and will be removed. - #gpio-cells : Should be two. -- cgit v1.2.3 From 9044070dc6949d853976b01edc80eaca9d09cea1 Mon Sep 17 00:00:00 2001 From: Kevin Wangtao Date: Tue, 10 Oct 2017 20:02:48 +0200 Subject: dt-bindings: Document the hi3660 thermal sensor binding This adds documentation of device tree bindings for the thermal sensor controller of hi3660 SoC. Signed-off-by: Kevin Wangtao Signed-off-by: Daniel Lezcano Acked-by: Rob Herring Signed-off-by: Wei Xu --- Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt index d48fc5280d5a..cef716a236f1 100644 --- a/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/hisilicon-thermal.txt @@ -13,6 +13,7 @@ Example : +for Hi6220: tsensor: tsensor@0,f7030700 { compatible = "hisilicon,tsensor"; reg = <0x0 0xf7030700 0x0 0x1000>; @@ -21,3 +22,11 @@ Example : clock-names = "thermal_clk"; #thermal-sensor-cells = <1>; } + +for Hi3660: + tsensor: tsensor@fff30000 { + compatible = "hisilicon,hi3660-tsensor"; + reg = <0x0 0xfff30000 0x0 0x1000>; + interrupts = ; + #thermal-sensor-cells = <1>; + }; -- cgit v1.2.3 From 5ce8c7a0e6945fdd48ed99cfcfcc25568c1e5960 Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Fri, 6 Oct 2017 08:23:37 -0400 Subject: media: dt: bindings: Add binding for tango HW IR decoder Add DT binding for the HW IR decoder embedded in SMP86xx/SMP87xx. Signed-off-by: Marc Gonzalez Acked-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/tango-ir.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/tango-ir.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/tango-ir.txt b/Documentation/devicetree/bindings/media/tango-ir.txt new file mode 100644 index 000000000000..a9f00c2bf897 --- /dev/null +++ b/Documentation/devicetree/bindings/media/tango-ir.txt @@ -0,0 +1,21 @@ +Sigma Designs Tango IR NEC/RC-5/RC-6 decoder (SMP86xx and SMP87xx) + +Required properties: + +- compatible: "sigma,smp8642-ir" +- reg: address/size of NEC+RC5 area, address/size of RC6 area +- interrupts: spec for IR IRQ +- clocks: spec for IR clock (typically the crystal oscillator) + +Optional properties: + +- linux,rc-map-name: see Documentation/devicetree/bindings/media/rc.txt + +Example: + + ir@10518 { + compatible = "sigma,smp8642-ir"; + reg = <0x10518 0x18>, <0x105e0 0x1c>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + }; -- cgit v1.2.3 From 68ace22edb932836d59a5834df85f519c5ce4e4d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 19 Sep 2017 17:26:54 +0800 Subject: irqchip/ls-scfg-msi: Add LS1012a MSI support The ls1012a implements only 1 MSI controller, and it is the same as ls1043a. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring Acked-by: Minghuan Lian Acked-by: Thomas Gleixner --- .../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 + drivers/irqchip/irq-ls-scfg-msi.c | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt index 49ccabbfa6f3..a4ff93d6b7f3 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt @@ -8,6 +8,7 @@ Required properties: "fsl,ls1043a-msi" "fsl,ls1046a-msi" "fsl,ls1043a-v1.1-msi" + "fsl,ls1012a-msi" - msi-controller: indicates that this is a PCIe MSI controller node - reg: physical base address of the controller and length of memory mapped. - interrupts: an interrupt to the parent interrupt controller. diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c index 119f4ef0d421..57e3d900f19e 100644 --- a/drivers/irqchip/irq-ls-scfg-msi.c +++ b/drivers/irqchip/irq-ls-scfg-msi.c @@ -316,6 +316,7 @@ static const struct of_device_id ls_scfg_msi_id[] = { { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg}, { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg}, + { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg }, { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg }, { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg }, { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg }, -- cgit v1.2.3 From 1548a21458bf7c5fc541c0785aa886602b27d5f5 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 11 Oct 2017 13:02:25 +0200 Subject: ARM: dts: qcom: Add initial DTS file for Fairphone 2 phone This DTS has support for the Fairphone 2 (codenamed FP2). This first version of the DTS supports just the serial console via the MSM UART pins. Signed-off-by: Luca Weiss Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 22 ++++++++++++++++++++++ 3 files changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ea1fd4232ab..f6d148f5c5f0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ everspin Everspin Technologies, Inc. exar Exar Corporation excito Excito ezchip EZchip Semiconductor +fairphone Fairphone B.V. faraday Faraday Technology Corporation fcs Fairchild Semiconductor firefly Firefly diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4da1b19178ec..f5cc9bef0f2d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -700,6 +700,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ + qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts new file mode 100644 index 000000000000..79a5aa8b856a --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -0,0 +1,22 @@ +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" + +/ { + model = "Fairphone 2"; + compatible = "fairphone,fp2", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; +}; -- cgit v1.2.3 From b8b74dda3908660f49a5d5cec28725e3950e00d5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 3 Oct 2017 17:24:43 +0200 Subject: ARM64: dts: meson-gxm: Add support for Khadas VIM2 The Khadas VIM2 is a Single Board Computer, respin of the origin Khadas VIM board, using an Amlogic S912 SoC and more server oriented. It provides the same external connectors and header pinout, plus a SPI NOR Flash, a reprogrammable STM8S003 MCU, FPC Connector, Cooling FAN header and Pogo Pads Arrays. Cc: Gouwa Acked-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Neil Armstrong Tested-by: Jerome Brunet Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 399 +++++++++++++++++++++ 3 files changed, 401 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 4e4bc0bae597..a44599739746 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -71,6 +71,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) + - "khadas,vim2" (Meson gxm s912) - "kingnovel,r-box-pro" (Meson gxm S912) - "nexbox,a1" (Meson gxm s912) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 7a9f48c27b1f..70246e3ecd5c 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts new file mode 100644 index 000000000000..32c138ec0e58 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -0,0 +1,399 @@ +/* + * Copyright (c) 2017 Martin Blumenstingl . + * Copyright (c) 2017 BayLibre, SAS + * Author: Neil Armstrong + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include +#include + +#include "meson-gxm.dtsi" + +/ { + compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; + model = "Khadas VIM2"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Function"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + gpio_fan: gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH + &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; + /* Dummy RPM values since fan is optional */ + gpio-fan,speed-map = <0 0 + 1 1 + 2 2 + 3 3>; + cooling-min-level = <0>; + cooling-max-level = <3>; + #cooling-cells = <2>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + power { + label = "vim:red:power"; + pwms = <&pwm_AO_ab 1 7812500 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&scpi_sensors 0>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + cpu_alert1: cpu-alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map3 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cooling-min-level = <0>; + cooling-max-level = <6>; + #cooling-cells = <2>; +}; + +&cpu4 { + cooling-min-level = <0>; + cooling-max-level = <4>; + #cooling-cells = <2>; +}; + +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + /* Select external PHY by default */ + phy-handle = <&external_phy>; + + amlogic,tx-delay-ns = <2>; + + /* External PHY reset is shared with internal PHY Led signals */ + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + /* External PHY is in RGMII */ + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + /* has to be enabled manually when a battery is connected: */ + status = "disabled"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; + linux,rc-map-name = "rc-geekbox"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* + * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe + * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled + */ +&spifc { + status = "disabled"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + w25q32: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q16", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; + +/* This one is connected to the Bluetooth module */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>; + pinctrl-names = "default"; +}; + +/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_pins>; + pinctrl-names = "default"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; -- cgit v1.2.3 From abe8bbd308c5f2864c1bc066a0e60ec59a0ae450 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 3 Oct 2017 17:29:45 +0200 Subject: dt-bindings: arm: amlogic: Add Tronsmart Vega S96 binding Cc: support@tronsmart.com Acked-by: Jerome Brunet Signed-off-by: Oleg Ivanov Signed-off-by: Neil Armstrong Acked-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index a44599739746..da379880abb6 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -74,6 +74,7 @@ Board compatible values (alphabetically, grouped by SoC): - "khadas,vim2" (Meson gxm s912) - "kingnovel,r-box-pro" (Meson gxm S912) - "nexbox,a1" (Meson gxm s912) + - "tronsmart,vega-s96" (Meson gxm s912) Amlogic Meson Firmware registers Interface ------------------------------------------ -- cgit v1.2.3 From 8c1b7dc9ba2294c6dbd1870a3d2e534bfda3047a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 14 Aug 2017 15:46:18 -0700 Subject: firmware: qcom: scm: Expose download-mode control In order to aid post-mortem debugging the Qualcomm platforms provide a "memory download mode", where the boot loader will provide an interface for custom tools to "download" the content of RAM to a host machine. The mode is triggered by writing a magic value somewhere in RAM, that is read in the boot code path after a warm-restart. Two mechanism for setting this magic value are supported in modern platforms; a direct SCM call to enable the mode or through a secure io write of a magic value. In order for a normal reboot not to trigger "download mode" the magic must be cleared during a clean reboot. Download mode has to be enabled by including qcom_scm.download_mode=1 on the command line. Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../devicetree/bindings/firmware/qcom,scm.txt | 2 + drivers/firmware/Kconfig | 11 ++++ drivers/firmware/qcom_scm-32.c | 6 ++ drivers/firmware/qcom_scm-64.c | 13 ++++ drivers/firmware/qcom_scm.c | 75 ++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 2 + 6 files changed, 109 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 20f26fbce875..7b40054be0d8 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -18,6 +18,8 @@ Required properties: * Core, iface, and bus clocks required for "qcom,scm" - clock-names: Must contain "core" for the core clock, "iface" for the interface clock and "bus" for the bus clock per the requirements of the compatible. +- qcom,dload-mode: phandle to the TCSR hardware block and offset of the + download mode control register (optional) Example for MSM8916: diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 6e4ed5a9c6fd..fa87a055905e 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -215,6 +215,17 @@ config QCOM_SCM_64 def_bool y depends on QCOM_SCM && ARM64 +config QCOM_SCM_DOWNLOAD_MODE_DEFAULT + bool "Qualcomm download mode enabled by default" + depends on QCOM_SCM + help + A device with "download mode" enabled will upon an unexpected + warm-restart enter a special debug mode that allows the user to + "download" memory content over USB for offline postmortem analysis. + The feature can be enabled/disabled on the kernel command line. + + Say Y here to enable "download mode" by default. + config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on TI_MESSAGE_MANAGER diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 11fdb1584823..68b2033bc30e 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -561,6 +561,12 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : le32_to_cpu(out); } +int __qcom_scm_set_dload_mode(struct device *dev, bool enable) +{ + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE, + enable ? QCOM_SCM_SET_DLOAD_MODE : 0, 0); +} + int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) { struct { diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index bf50fb59852e..3fea6f563ca9 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -440,6 +440,19 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, return ret; } +int __qcom_scm_set_dload_mode(struct device *dev, bool enable) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + + desc.args[0] = QCOM_SCM_SET_DLOAD_MODE; + desc.args[1] = enable ? QCOM_SCM_SET_DLOAD_MODE : 0; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE, + &desc, &res); +} + int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val) { diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index e18d63935648..9064e559a01f 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -19,15 +19,20 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include "qcom_scm.h" +static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); +module_param(download_mode, bool, 0); + #define SCM_HAS_CORE_CLK BIT(0) #define SCM_HAS_IFACE_CLK BIT(1) #define SCM_HAS_BUS_CLK BIT(2) @@ -38,6 +43,8 @@ struct qcom_scm { struct clk *iface_clk; struct clk *bus_clk; struct reset_controller_dev reset; + + u64 dload_mode_addr; }; static struct qcom_scm *__scm; @@ -345,6 +352,54 @@ int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) } EXPORT_SYMBOL(qcom_scm_io_writel); +static void qcom_scm_set_download_mode(bool enable) +{ + bool avail; + int ret = 0; + + avail = __qcom_scm_is_call_available(__scm->dev, + QCOM_SCM_SVC_BOOT, + QCOM_SCM_SET_DLOAD_MODE); + if (avail) { + ret = __qcom_scm_set_dload_mode(__scm->dev, enable); + } else if (__scm->dload_mode_addr) { + ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr, + enable ? QCOM_SCM_SET_DLOAD_MODE : 0); + } else { + dev_err(__scm->dev, + "No available mechanism for setting download mode\n"); + } + + if (ret) + dev_err(__scm->dev, "failed to set download mode: %d\n", ret); +} + +static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) +{ + struct device_node *tcsr; + struct device_node *np = dev->of_node; + struct resource res; + u32 offset; + int ret; + + tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); + if (!tcsr) + return 0; + + ret = of_address_to_resource(tcsr, 0, &res); + of_node_put(tcsr); + if (ret) + return ret; + + ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); + if (ret < 0) + return ret; + + *addr = res.start + offset; + + return 0; +} + /** * qcom_scm_is_available() - Checks if SCM is available */ @@ -370,6 +425,10 @@ static int qcom_scm_probe(struct platform_device *pdev) if (!scm) return -ENOMEM; + ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); + if (ret < 0) + return ret; + clks = (unsigned long)of_device_get_match_data(&pdev->dev); if (clks & SCM_HAS_CORE_CLK) { scm->core_clk = devm_clk_get(&pdev->dev, "core"); @@ -418,9 +477,24 @@ static int qcom_scm_probe(struct platform_device *pdev) __qcom_scm_init(); + /* + * If requested enable "download mode", from this point on warmboot + * will cause the the boot stages to enter download mode, unless + * disabled below by a clean shutdown/reboot. + */ + if (download_mode) + qcom_scm_set_download_mode(true); + return 0; } +static void qcom_scm_shutdown(struct platform_device *pdev) +{ + /* Clean shutdown, disable download mode to allow normal restart */ + if (download_mode) + qcom_scm_set_download_mode(false); +} + static const struct of_device_id qcom_scm_dt_match[] = { { .compatible = "qcom,scm-apq8064", /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ @@ -448,6 +522,7 @@ static struct platform_driver qcom_scm_driver = { .of_match_table = qcom_scm_dt_match, }, .probe = qcom_scm_probe, + .shutdown = qcom_scm_shutdown, }; static int __init qcom_scm_init(void) diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index a60e4b9b1394..83f171c23943 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -14,9 +14,11 @@ #define QCOM_SCM_SVC_BOOT 0x1 #define QCOM_SCM_BOOT_ADDR 0x1 +#define QCOM_SCM_SET_DLOAD_MODE 0x10 #define QCOM_SCM_BOOT_ADDR_MC 0x11 #define QCOM_SCM_SET_REMOTE_STATE 0xa extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id); +extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable); #define QCOM_SCM_FLAG_HLOS 0x01 #define QCOM_SCM_FLAG_COLDBOOT_MC 0x02 -- cgit v1.2.3 From a335b122ba277c879d224b41e52fcfdf334266b0 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 19 Sep 2017 17:26:56 +0800 Subject: PCI: layerscape: Add support for ls1012a Add support for ls1012a. Signed-off-by: Hou Zhiqiang Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring Acked-by: Minghuan Lian Acked-by: Thomas Gleixner --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + drivers/pci/dwc/pci-layerscape.c | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index c0484da0f20d..66df1e81e0b8 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -18,6 +18,7 @@ Required properties: "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" + "fsl,ls1012a-pcie" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 87fa486bee2c..3b01e309a55e 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -253,6 +253,7 @@ static struct ls_pcie_drvdata ls2088_drvdata = { }; static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, -- cgit v1.2.3 From bc811c697b13dcb5abac9a410527859aca095a9c Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 28 Sep 2017 16:14:54 -0700 Subject: dt-bindings: Add documentation for Broadcom Hurricane 2 SoCs Add binding documentation for the Broadcom Hurricane 2 SoCs used in switching control planes. Acked-by: Jon Mason Signed-off-by: Florian Fainelli Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt new file mode 100644 index 000000000000..a124c7fc4dcd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,hr2.txt @@ -0,0 +1,14 @@ +Broadcom Hurricane 2 device tree bindings +--------------------------------------- + +Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs +are based on Broadcom's iProc SoC architecture and feature a single core Cortex +A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND +flash and a PCIe attached integrated switching engine. + +Boards with Hurricane SoCs shall have the following properties: + +Required root node property: + +BCM53342 +compatible = "brcm,bcm53342", "brcm,hr2"; -- cgit v1.2.3 From c6d2efd12744fc4c9c620eab9a92b0c4e9f5e4bd Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 28 Sep 2017 16:14:56 -0700 Subject: dt-bindings: Document Broadcom Hurricane 2 clocks Add a Device Tree binding document for the Broadcom Hurricane 2 SoC which is an iProc based system. Acked-by: Jon Mason Signed-off-by: Florian Fainelli Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- .../devicetree/bindings/clock/brcm,iproc-clocks.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index f2c5f0e4a363..f8e4a93466cb 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -137,6 +137,20 @@ These clock IDs are defined in: ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 +Hurricane 2 +------ +PLL and leaf clock compatible strings for Hurricane 2 are: + "brcm,hr2-armpll" + +The following table defines the set of PLL/clock for Hurricane 2: + + Clock Source Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + Northstar and Northstar Plus ------ PLL and leaf clock compatible strings for Northstar and Northstar Plus are: -- cgit v1.2.3 From e6ac8fc0823f9227a6ce65481adcbdbf529acfb9 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 28 Sep 2017 16:15:00 -0700 Subject: dt-bindings: Add Ubiquiti Networks vendor prefix Use the stock ticker: UBNT as the vendor prefix for Ubiquiti Networks. Acked-by: Jon Mason Signed-off-by: Florian Fainelli Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ea1fd4232ab..91b6b5b36d4c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -351,6 +351,7 @@ truly Truly Semiconductors Limited tsd Theobroma Systems Design und Consulting GmbH tyan Tyan Computer Corporation ucrobotics uCRobotics +ubnt Ubiquiti Networks udoo Udoo uniwest United Western Technologies Corp (UniWest) upisemi uPI Semiconductor Corp. -- cgit v1.2.3 From cfc95173ba8e18e41d9a69d2747d0f2738a2a551 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 23 Aug 2017 15:39:56 +0930 Subject: dt-bindings: aspeed-scu: Add clock and reset properties Signed-off-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt index 4fc5b83726d6..ce8cf0ec6279 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt @@ -9,10 +9,16 @@ Required properties: "aspeed,g5-scu", "syscon", "simple-mfd" - reg: contains the offset and length of the SCU memory region +- #clock-cells: should be set to <1> - the system controller is also a + clock provider +- #reset-cells: should be set to <1> - the system controller is also a + reset line provider Example: syscon: syscon@1e6e2000 { compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; }; -- cgit v1.2.3 From 4589515af30005a404bd34e4b7933f98e68849f4 Mon Sep 17 00:00:00 2001 From: Maciej Purski Date: Tue, 5 Sep 2017 15:50:27 +0200 Subject: mfd: max77693: Add muic of_compatible in mfd_cell This patch adds muic of_compatible in order to use the muic device driver in device tree. Signed-off-by: Maciej Purski Reviewed-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/max77693.txt | 6 ++++++ drivers/mfd/max77693.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/max77693.txt b/Documentation/devicetree/bindings/mfd/max77693.txt index 6a1ae3a2b77f..e6754974a745 100644 --- a/Documentation/devicetree/bindings/mfd/max77693.txt +++ b/Documentation/devicetree/bindings/mfd/max77693.txt @@ -127,6 +127,12 @@ Required properties for the LED child node: Optional properties for the LED child node: - label : see Documentation/devicetree/bindings/leds/common.txt +Optional nodes: +- max77693-muic : + Node used only by extcon consumers. + Required properties: + - compatible : "maxim,max77693-muic" + Example: #include diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c index 662ae0d9e334..1c05ea0cba61 100644 --- a/drivers/mfd/max77693.c +++ b/drivers/mfd/max77693.c @@ -48,7 +48,10 @@ static const struct mfd_cell max77693_devs[] = { .name = "max77693-charger", .of_compatible = "maxim,max77693-charger", }, - { .name = "max77693-muic", }, + { + .name = "max77693-muic", + .of_compatible = "maxim,max77693-muic", + }, { .name = "max77693-haptic", .of_compatible = "maxim,max77693-haptic", -- cgit v1.2.3 From 58ab243ef5ad1aee7600eb4bd8d9ce5a63401c5e Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Wed, 6 Sep 2017 17:27:41 -0700 Subject: syscon: dt-bindings: Add binding doc for Broadcom iProc CDRU Add binding document for Broadcom iProc's Chip Device Resource Unit (CDRU). Multiple iProc based chips have this CDRU block that contains miscellaneous registers for chip or device configurations. Start with Stingray specific compatible string for the initial binding Signed-off-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/brcm,iproc-cdru.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt b/Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt new file mode 100644 index 000000000000..82f82e069563 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/brcm,iproc-cdru.txt @@ -0,0 +1,16 @@ +Broadcom iProc Chip Device Resource Unit (CDRU) + +Various Broadcom iProc SoCs have a set of registers that provide various +chip specific device and resource configurations. This node allows access to +these CDRU registers via syscon. + +Required properties: +- compatible: should contain: + "brcm,sr-cdru", "syscon" for Stingray +- reg: base address and range of the CDRU registers + +Example: + cdru: syscon@6641d000 { + compatible = "brcm,sr-cdru", "syscon"; + reg = <0 0x6641d000 0 0x400>; + }; -- cgit v1.2.3 From 88decb026d90c386b2a15adbe6fb094f6a86d144 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Wed, 6 Sep 2017 17:27:42 -0700 Subject: syscon: dt-bindings: Add binding document for iProc MHB block Add binding document for Broadcom iProc's Multi-Host Bridge (MHB) block Signed-off-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/brcm,iproc-mhb.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt b/Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt new file mode 100644 index 000000000000..4421e9771b8a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/brcm,iproc-mhb.txt @@ -0,0 +1,18 @@ +Broadcom iProc Multi Host Bridge (MHB) + +Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls +the connection and configuration of 1) internal PCIe serdes; 2) PCIe endpoint +interface; 3) access to the Nitro (network processing) engine + +This node allows access to these MHB registers via syscon. + +Required properties: +- compatible: should contain: + "brcm,sr-mhb", "syscon" for Stingray +- reg: base address and range of the MHB registers + +Example: + mhb: syscon@60401000 { + compatible = "brcm,sr-mhb", "syscon"; + reg = <0 0x60401000 0 0x38c>; + }; -- cgit v1.2.3 From d67ac3ae3a3ce464b4fec854c4c85407a99e8e2c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Oct 2017 14:33:08 +0200 Subject: dt-bindings: iommu: ipmmu-vmsa: Use generic node name Use the preferred generic node name in the example. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt index 3ed027cfca95..857df929a654 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt @@ -53,7 +53,7 @@ Example: R8A7791 IPMMU-MX and VSP1-D0 bus master #iommu-cells = <1>; }; - vsp1@fe928000 { + vsp@fe928000 { ... iommus = <&ipmmu_mx 13>; ... -- cgit v1.2.3 From de18e4bea0784e8df67c908c6157acc05ecba0cf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 9 Oct 2017 20:18:33 +0200 Subject: devicetree: Add vendor-prefix for DH electronics GmbH Add vendor prefix for DH electronics GmbH, https://www.dh-electronics.com . The company is a SoM and evaluation board manufacturer. Signed-off-by: Marek Vasut Cc: Rob Herring Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 5268738c3e7c..15c6b33f0b21 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -83,6 +83,7 @@ davicom DAVICOM Semiconductor, Inc. delta Delta Electronics, Inc. denx Denx Software Engineering devantech Devantech, Ltd. +dh DH electronics GmbH digi Digi International Inc. digilent Diglent, Inc. dioo Dioo Microcircuit Co., Ltd -- cgit v1.2.3 From 6d39a6cc38899d3f77b5f8bb03afcdc407e11933 Mon Sep 17 00:00:00 2001 From: Peter Meerwald-Stadler Date: Wed, 11 Oct 2017 11:09:07 +0200 Subject: dt-bindings: iio: health: Fix max30100 I2C chip address in example Should be in hex, not decimal or even octal Signed-off-by: Peter Meerwald-Stadler Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/health/max30100.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/health/max30100.txt b/Documentation/devicetree/bindings/iio/health/max30100.txt index 295a9edfa4fd..8d8176459d09 100644 --- a/Documentation/devicetree/bindings/iio/health/max30100.txt +++ b/Documentation/devicetree/bindings/iio/health/max30100.txt @@ -20,9 +20,9 @@ Optional properties: Example: -max30100@057 { +max30100@57 { compatible = "maxim,max30100"; - reg = <57>; + reg = <0x57>; maxim,led-current-microamp = <24000 50000>; interrupt-parent = <&gpio1>; interrupts = <16 2>; -- cgit v1.2.3 From 446b3217a96c456ab8796605fbb3ce379b03a504 Mon Sep 17 00:00:00 2001 From: Peter Meerwald-Stadler Date: Wed, 11 Oct 2017 11:09:08 +0200 Subject: dt-bindings: iio: health: Use binding name for max30102 in example Signed-off-by: Peter Meerwald-Stadler Acked-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/health/max30102.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/health/max30102.txt b/Documentation/devicetree/bindings/iio/health/max30102.txt index c695e7cbeefb..8629c18b0e78 100644 --- a/Documentation/devicetree/bindings/iio/health/max30102.txt +++ b/Documentation/devicetree/bindings/iio/health/max30102.txt @@ -20,7 +20,7 @@ Optional properties: Example: -max30100@57 { +max30102@57 { compatible = "maxim,max30102"; reg = <0x57>; maxim,red-led-current-microamp = <7000>; -- cgit v1.2.3 From 3991e054832e52119b238b397e5e510d7fee5bb4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 Oct 2017 14:26:28 +0200 Subject: dt-bindings: samsung: Document binding for new Odroid HC1 board Document the binding for new Hardkernel Odroid HC1 board. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 3c551894f621..5e95e3e81140 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -57,6 +57,7 @@ Required root node properties: - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel Odroid XU3 Lite board. - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4. + - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1. * Insignal - "insignal,arndale" - for Exynos5250-based Insignal Arndale board. -- cgit v1.2.3 From 70dfb1205224ed62acd46b31ebfa299685b0098a Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sat, 12 Aug 2017 00:04:51 +0200 Subject: dt-bindings: Add vendor prefix for ProBox2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PROBOX2 is a TV box brand by Hong Kong based online reseller W2COMP Company Limited. Cc: support@probox2.com Acked-by: Rob Herring Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1ea1fd4232ab..d17d01a160de 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -263,6 +263,7 @@ plathome Plat'Home Co., Ltd. plda PLDA poslab Poslab Technology Co., Ltd. powervr PowerVR (deprecated, use img) +probox2 PROBOX2 (by W2COMP Co., Ltd.) pulsedlight PulsedLight, Inc qca Qualcomm Atheros, Inc. qcom Qualcomm Technologies, Inc -- cgit v1.2.3 From f80ec175ba721fd6d56f407af64a6712d5bdfa1b Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sat, 12 Aug 2017 00:22:30 +0200 Subject: dt-bindings: arm: realtek: Add ProBox2 AVA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document a compatible string for the PROBOX2 AVA TV Box. Cc: support@probox2.com Acked-by: Rob Herring Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/arm/realtek.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/realtek.txt b/Documentation/devicetree/bindings/arm/realtek.txt index 13d755787b4f..297c15eb81e2 100644 --- a/Documentation/devicetree/bindings/arm/realtek.txt +++ b/Documentation/devicetree/bindings/arm/realtek.txt @@ -12,6 +12,7 @@ Required root node properties: Root node property compatible must contain, depending on board: + - ProBox2 AVA: "probox2,ava" - Zidoo X9S: "zidoo,x9s" -- cgit v1.2.3 From d93cc0e7888a7c650a9155ad70e2236d15785c1e Mon Sep 17 00:00:00 2001 From: Stefan Brüns Date: Thu, 28 Sep 2017 03:49:23 +0200 Subject: arm64: allwinner: a64: Add devicetree binding for DMA controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The A64 is register compatible with the H3, but has a different number of dma channels and request ports. Attach additional properties to the node to allow future reuse of the compatible for controllers with different number of channels/requests. If dma-requests is not specified, the register layout defined maximum of 32 is used. Signed-off-by: Stefan Brüns Acked-by: Rob Herring Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/sun6i-dma.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt index 98fbe1a5c6dd..9700b1d00fed 100644 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt @@ -27,6 +27,32 @@ Example: #dma-cells = <1>; }; +------------------------------------------------------------------------------ +For A64 DMA controller: + +Required properties: +- compatible: "allwinner,sun50i-a64-dma" +- dma-channels: Number of DMA channels supported by the controller. + Refer to Documentation/devicetree/bindings/dma/dma.txt +- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells + +Optional properties: +- dma-requests: Number of DMA request signals supported by the controller. + Refer to Documentation/devicetree/bindings/dma/dma.txt + +Example: + dma: dma-controller@1c02000 { + compatible = "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <8>; + dma-requests = <27>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; +------------------------------------------------------------------------------ + Clients: DMA clients connected to the A31 DMA controller must use the format -- cgit v1.2.3 From 8ca8ac1024841781f544427b7ca5684e4c5637a9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 11 Oct 2017 11:25:12 +0200 Subject: clk: samsung: Add dt bindings for Exynos4412 ISP clock controller Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Because those registers are also located in a different memory region than the main clock controller, support for them can be provided by a separate clock controller. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Sylwester Nawrocki --- .../devicetree/bindings/clock/exynos4-clock.txt | 43 ++++++++++++++++++++++ include/dt-bindings/clock/exynos4.h | 35 ++++++++++++++++++ 2 files changed, 78 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19ed3b2..bc61c952cb0b 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; + +Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP) +subsystem. Registers for those clocks are located in the ISP power domain. +Because those registers are also located in a different memory region than +the main clock controller, a separate clock controller has to be defined for +handling them. + +Required Properties: + +- compatible: should be "samsung,exynos4412-isp-clock". + +- reg: physical base address of the ISP clock controller and length of memory + mapped region. + +- #clock-cells: should be 1. + +- clocks: list of the clock controller input clock identifiers, + from common clock bindings, should point to CLK_ACLK200 and + CLK_ACLK400_MCUISP clocks from the main clock controller. + +- clock-names: list of the clock controller input clock names, + as described in clock-bindings.txt, should be "aclk200" and + "aclk400_mcuisp". + +- power-domains: a phandle to ISP power domain node as described by + generic PM domain bindings. + +Example 3: The clock controllers bindings for Exynos4412 SoCs. + + clock: clock-controller@10030000 { + compatible = "samsung,exynos4412-clock"; + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index c40111f36d5e..e9f9d400c322 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -272,4 +272,39 @@ /* must be greater than maximal clock id */ #define CLK_NR_CLKS 461 +/* Exynos4x12 ISP clocks */ +#define CLK_ISP_FIMC_ISP 1 +#define CLK_ISP_FIMC_DRC 2 +#define CLK_ISP_FIMC_FD 3 +#define CLK_ISP_FIMC_LITE0 4 +#define CLK_ISP_FIMC_LITE1 5 +#define CLK_ISP_MCUISP 6 +#define CLK_ISP_GICISP 7 +#define CLK_ISP_SMMU_ISP 8 +#define CLK_ISP_SMMU_DRC 9 +#define CLK_ISP_SMMU_FD 10 +#define CLK_ISP_SMMU_LITE0 11 +#define CLK_ISP_SMMU_LITE1 12 +#define CLK_ISP_PPMUISPMX 13 +#define CLK_ISP_PPMUISPX 14 +#define CLK_ISP_MCUCTL_ISP 15 +#define CLK_ISP_MPWM_ISP 16 +#define CLK_ISP_I2C0_ISP 17 +#define CLK_ISP_I2C1_ISP 18 +#define CLK_ISP_MTCADC_ISP 19 +#define CLK_ISP_PWM_ISP 20 +#define CLK_ISP_WDT_ISP 21 +#define CLK_ISP_UART_ISP 22 +#define CLK_ISP_ASYNCAXIM 23 +#define CLK_ISP_SMMU_ISPCX 24 +#define CLK_ISP_SPI0_ISP 25 +#define CLK_ISP_SPI1_ISP 26 + +#define CLK_ISP_DIV_ISP0 27 +#define CLK_ISP_DIV_ISP1 28 +#define CLK_ISP_DIV_MCUISP0 29 +#define CLK_ISP_DIV_MCUISP1 30 + +#define CLK_NR_ISP_CLKS 31 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ -- cgit v1.2.3 From 162d58c26d65e1486d18436eb151148a7f9886e5 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 16 Oct 2017 13:45:58 +0200 Subject: ARM: dts: stm32: change pinctrl bindings definition Initially each pin was declared in "include/dt-bindings/stm32-pinfunc.h" and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX). Since this approach was approved, the number of supported MCU has increased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new file in "include/dt-bindings" each time a new STM32 SOC arrives I propose a new approach which consist to use a macro to define pin muxing in device tree. All STM32 will use the common macro to define pinmux. Furthermore, it will make STM32 maintenance and integration of new SOC easier . Signed-off-by: Alexandre TORGUE Reviewed-by: Vikas MANOCHA Reviewed-by: Benjamin Gaignard Acked-by: Linus Walleij Acked-by: Rob Herring --- .../bindings/pinctrl/st,stm32-pinctrl.txt | 22 +- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 176 +-- arch/arm/boot/dts/stm32f746.dtsi | 16 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 10 +- include/dt-bindings/pinctrl/stm32-pinfunc.h | 30 + include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1239 --------------- include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 1324 ---------------- include/dt-bindings/pinctrl/stm32h7-pinfunc.h | 1612 -------------------- 8 files changed, 151 insertions(+), 4278 deletions(-) create mode 100644 include/dt-bindings/pinctrl/stm32-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/stm32h7-pinfunc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 33e3d3c47552..58c2a4c229db 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -143,6 +143,24 @@ Required properties: * 16 : Alternate Function 15 * 17 : Analog + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + - include/dt-bindings/pinctrl/stm32-pinfunc.h + + Some examples of using macro: + /* GPIO A9 set as alernate function 2 */ + ... { + pinmux = ; + }; + /* GPIO A9 set as GPIO */ + ... { + pinmux = ; + }; + /* GPIO A9 set as analog */ + ... { + pinmux = ; + }; + Optional properties: - GENERIC_PINCONFIG: is the generic pinconfig options to use. Available options are: @@ -165,13 +183,13 @@ pin-controller { ... usart1_pins_a: usart1@0 { pins1 { - pinmux = ; + pinmux = ; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; bias-disable; }; }; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 7f3560c0211d..ae94d86c53c4 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include +#include #include / { @@ -165,35 +165,35 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = ; + pinmux = ; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART1_RX */ bias-disable; }; }; usart3_pins_a: usart3@0 { pins1 { - pinmux = ; + pinmux = ; /* USART3_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART3_RX */ bias-disable; }; }; usbotg_fs_pins_a: usbotg_fs@0 { pins { - pinmux = , - , - ; + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -202,9 +202,9 @@ usbotg_fs_pins_b: usbotg_fs@1 { pins { - pinmux = , - , - ; + pinmux = , /* OTG_HS_ID */ + , /* OTG_HS_DM */ + ; /* OTG_HS_DP */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -213,18 +213,18 @@ usbotg_hs_pins_a: usbotg_hs@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - ; + pinmux = , /* OTG_HS_ULPI_NXT*/ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ bias-disable; drive-push-pull; slew-rate = <2>; @@ -233,49 +233,49 @@ ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - ; + pinmux = , /* ETH_MII_TXD0_ETH_RMII_TXD0 */ + , /* ETH_MII_TXD1_ETH_RMII_TXD1 */ + , /* ETH_MII_TXD2 */ + , /* ETH_MII_TXD3 */ + , /* ETH_MII_TX_CLK */ + , /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ + , /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ + , /* ETH_MII_RXD0_ETH_RMII_RXD0 */ + , /* ETH_MII_RXD1_ETH_RMII_RXD1 */ + , /* ETH_MII_RXD2 */ + ; /* ETH_MII_RXD3 */ slew-rate = <2>; }; }; adc3_in8_pin: adc@200 { pins { - pinmux = ; + pinmux = ; }; }; pwm1_pins: pwm@1 { pins { - pinmux = , - , - ; + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH1N */ + ; /* TIM1_BKIN */ }; }; pwm3_pins: pwm@3 { pins { - pinmux = , - ; + pinmux = , /* TIM3_CH1 */ + ; /* TIM3_CH2 */ }; }; i2c1_pins: i2c1@0 { pins { - pinmux = , - ; + pinmux = , /* I2C1_SDA */ + ; /* I2C1_SCL */ bias-disable; drive-open-drain; slew-rate = <3>; @@ -284,55 +284,55 @@ ltdc_pins: ltdc@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + pinmux = , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_CLK */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6*/ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3*/ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + , /* LCD_B7 */ + ; /* LCD_DE */ slew-rate = <2>; }; }; dcmi_pins: dcmi@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + pinmux = , /* DCMI_HSYNC */ + , /* DCMI_VSYNC */ + , /* DCMI_PIXCLK */ + , /* DCMI_D0 */ + , /* DCMI_D1 */ + , /* DCMI_D2 */ + , /* DCMI_D3 */ + , /*DCMI_D4 */ + , /* DCMI_D5 */ + , /* DCMI_D6 */ + , /* DCMI_D7 */ + , /* DCMI_D8 */ + , /* DCMI_D9 */ + , /* DCMI_D10 */ + ; /* DCMI_D11 */ bias-disable; drive-push-pull; slew-rate = <3>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 73bf8c1529a1..faaeca803943 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -42,7 +42,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include +#include #include #include @@ -619,7 +619,7 @@ cec_pins_a: cec@0 { pins { - pinmux = ; + pinmux = ; /* HDMI CEC */ slew-rate = <0>; drive-open-drain; bias-disable; @@ -628,34 +628,34 @@ usart1_pins_a: usart1@0 { pins1 { - pinmux = ; + pinmux = ; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART1_RX */ bias-disable; }; }; usart1_pins_b: usart1@1 { pins1 { - pinmux = ; + pinmux = ; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART1_RX */ bias-disable; }; }; i2c1_pins_b: i2c1@0 { pins { - pinmux = , - ; + pinmux = , /* I2C1 SDA */ + ; /* I2C1 SCL */ bias-disable; drive-open-drain; slew-rate = <0>; diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index d438818155b2..65c1cd043987 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include +#include / { soc { @@ -141,26 +141,26 @@ usart1_pins: usart1@0 { pins1 { - pinmux = ; + pinmux = ; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART1_RX */ bias-disable; }; }; usart2_pins: usart2@0 { pins1 { - pinmux = ; + pinmux = ; /* USART2_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART2_RX */ bias-disable; }; }; diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h new file mode 100644 index 000000000000..b8dfe31821e6 --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -0,0 +1,30 @@ +#ifndef _DT_BINDINGS_STM32_PINFUNC_H +#define _DT_BINDINGS_STM32_PINFUNC_H + +/* define PIN modes */ +#define GPIO 0x0 +#define AF0 0x1 +#define AF1 0x2 +#define AF2 0x3 +#define AF3 0x4 +#define AF4 0x5 +#define AF5 0x6 +#define AF6 0x7 +#define AF7 0x8 +#define AF8 0x9 +#define AF9 0xa +#define AF10 0xb +#define AF11 0xc +#define AF12 0xd +#define AF13 0xe +#define AF14 0xf +#define AF15 0x10 +#define ANALOG 0x11 + +/* define Pins number*/ +#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) + +#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) + +#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ + diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h deleted file mode 100644 index 26f18798d949..000000000000 --- a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h +++ /dev/null @@ -1,1239 +0,0 @@ -#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H -#define _DT_BINDINGS_STM32F429_PINFUNC_H - -#define STM32F429_PA0_FUNC_GPIO 0x0 -#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F429_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F429_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F429_PA0_FUNC_USART2_CTS 0x8 -#define STM32F429_PA0_FUNC_UART4_TX 0x9 -#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F429_PA0_FUNC_EVENTOUT 0x10 -#define STM32F429_PA0_FUNC_ANALOG 0x11 - -#define STM32F429_PA1_FUNC_GPIO 0x100 -#define STM32F429_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F429_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F429_PA1_FUNC_USART2_RTS 0x108 -#define STM32F429_PA1_FUNC_UART4_RX 0x109 -#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F429_PA1_FUNC_EVENTOUT 0x110 -#define STM32F429_PA1_FUNC_ANALOG 0x111 - -#define STM32F429_PA2_FUNC_GPIO 0x200 -#define STM32F429_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F429_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F429_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F429_PA2_FUNC_USART2_TX 0x208 -#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F429_PA2_FUNC_EVENTOUT 0x210 -#define STM32F429_PA2_FUNC_ANALOG 0x211 - -#define STM32F429_PA3_FUNC_GPIO 0x300 -#define STM32F429_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F429_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F429_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F429_PA3_FUNC_USART2_RX 0x308 -#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F429_PA3_FUNC_LCD_B5 0x30f -#define STM32F429_PA3_FUNC_EVENTOUT 0x310 -#define STM32F429_PA3_FUNC_ANALOG 0x311 - -#define STM32F429_PA4_FUNC_GPIO 0x400 -#define STM32F429_PA4_FUNC_SPI1_NSS 0x406 -#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F429_PA4_FUNC_USART2_CK 0x408 -#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F429_PA4_FUNC_EVENTOUT 0x410 -#define STM32F429_PA4_FUNC_ANALOG 0x411 - -#define STM32F429_PA5_FUNC_GPIO 0x500 -#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F429_PA5_FUNC_SPI1_SCK 0x506 -#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F429_PA5_FUNC_EVENTOUT 0x510 -#define STM32F429_PA5_FUNC_ANALOG 0x511 - -#define STM32F429_PA6_FUNC_GPIO 0x600 -#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F429_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F429_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F429_PA6_FUNC_LCD_G2 0x60f -#define STM32F429_PA6_FUNC_EVENTOUT 0x610 -#define STM32F429_PA6_FUNC_ANALOG 0x611 - -#define STM32F429_PA7_FUNC_GPIO 0x700 -#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F429_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706 -#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F429_PA7_FUNC_EVENTOUT 0x710 -#define STM32F429_PA7_FUNC_ANALOG 0x711 - -#define STM32F429_PA8_FUNC_GPIO 0x800 -#define STM32F429_PA8_FUNC_MCO1 0x801 -#define STM32F429_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F429_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F429_PA8_FUNC_USART1_CK 0x808 -#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F429_PA8_FUNC_LCD_R6 0x80f -#define STM32F429_PA8_FUNC_EVENTOUT 0x810 -#define STM32F429_PA8_FUNC_ANALOG 0x811 - -#define STM32F429_PA9_FUNC_GPIO 0x900 -#define STM32F429_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F429_PA9_FUNC_USART1_TX 0x908 -#define STM32F429_PA9_FUNC_DCMI_D0 0x90e -#define STM32F429_PA9_FUNC_EVENTOUT 0x910 -#define STM32F429_PA9_FUNC_ANALOG 0x911 - -#define STM32F429_PA10_FUNC_GPIO 0xa00 -#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F429_PA10_FUNC_USART1_RX 0xa08 -#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F429_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F429_PA10_FUNC_ANALOG 0xa11 - -#define STM32F429_PA11_FUNC_GPIO 0xb00 -#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F429_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F429_PA11_FUNC_LCD_R4 0xb0f -#define STM32F429_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F429_PA11_FUNC_ANALOG 0xb11 - -#define STM32F429_PA12_FUNC_GPIO 0xc00 -#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F429_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F429_PA12_FUNC_LCD_R5 0xc0f -#define STM32F429_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F429_PA12_FUNC_ANALOG 0xc11 - -#define STM32F429_PA13_FUNC_GPIO 0xd00 -#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F429_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F429_PA13_FUNC_ANALOG 0xd11 - -#define STM32F429_PA14_FUNC_GPIO 0xe00 -#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F429_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F429_PA14_FUNC_ANALOG 0xe11 - -#define STM32F429_PA15_FUNC_GPIO 0xf00 -#define STM32F429_PA15_FUNC_JTDI 0xf01 -#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06 -#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F429_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F429_PA15_FUNC_ANALOG 0xf11 - - - -#define STM32F429_PB0_FUNC_GPIO 0x1000 -#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F429_PB0_FUNC_LCD_R3 0x100a -#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F429_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F429_PB0_FUNC_ANALOG 0x1011 - -#define STM32F429_PB1_FUNC_GPIO 0x1100 -#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F429_PB1_FUNC_LCD_R6 0x110a -#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F429_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F429_PB1_FUNC_ANALOG 0x1111 - -#define STM32F429_PB2_FUNC_GPIO 0x1200 -#define STM32F429_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F429_PB2_FUNC_ANALOG 0x1211 - -#define STM32F429_PB3_FUNC_GPIO 0x1300 -#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306 -#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F429_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F429_PB3_FUNC_ANALOG 0x1311 - -#define STM32F429_PB4_FUNC_GPIO 0x1400 -#define STM32F429_PB4_FUNC_NJTRST 0x1401 -#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408 -#define STM32F429_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F429_PB4_FUNC_ANALOG 0x1411 - -#define STM32F429_PB5_FUNC_GPIO 0x1500 -#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506 -#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F429_PB5_FUNC_CAN2_RX 0x150a -#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F429_PB5_FUNC_DCMI_D10 0x150e -#define STM32F429_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F429_PB5_FUNC_ANALOG 0x1511 - -#define STM32F429_PB6_FUNC_GPIO 0x1600 -#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F429_PB6_FUNC_USART1_TX 0x1608 -#define STM32F429_PB6_FUNC_CAN2_TX 0x160a -#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F429_PB6_FUNC_DCMI_D5 0x160e -#define STM32F429_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F429_PB6_FUNC_ANALOG 0x1611 - -#define STM32F429_PB7_FUNC_GPIO 0x1700 -#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F429_PB7_FUNC_USART1_RX 0x1708 -#define STM32F429_PB7_FUNC_FMC_NL 0x170d -#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F429_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F429_PB7_FUNC_ANALOG 0x1711 - -#define STM32F429_PB8_FUNC_GPIO 0x1800 -#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F429_PB8_FUNC_CAN1_RX 0x180a -#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F429_PB8_FUNC_SDIO_D4 0x180d -#define STM32F429_PB8_FUNC_DCMI_D6 0x180e -#define STM32F429_PB8_FUNC_LCD_B6 0x180f -#define STM32F429_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F429_PB8_FUNC_ANALOG 0x1811 - -#define STM32F429_PB9_FUNC_GPIO 0x1900 -#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F429_PB9_FUNC_CAN1_TX 0x190a -#define STM32F429_PB9_FUNC_SDIO_D5 0x190d -#define STM32F429_PB9_FUNC_DCMI_D7 0x190e -#define STM32F429_PB9_FUNC_LCD_B7 0x190f -#define STM32F429_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F429_PB9_FUNC_ANALOG 0x1911 - -#define STM32F429_PB10_FUNC_GPIO 0x1a00 -#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F429_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F429_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F429_PB11_FUNC_GPIO 0x1b00 -#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F429_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F429_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F429_PB12_FUNC_GPIO 0x1c00 -#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F429_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F429_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F429_PB13_FUNC_GPIO 0x1d00 -#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F429_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F429_PB14_FUNC_GPIO 0x1e00 -#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07 -#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F429_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F429_PB15_FUNC_GPIO 0x1f00 -#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F429_PB15_FUNC_ANALOG 0x1f11 - - - -#define STM32F429_PC0_FUNC_GPIO 0x2000 -#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F429_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F429_PC0_FUNC_ANALOG 0x2011 - -#define STM32F429_PC1_FUNC_GPIO 0x2100 -#define STM32F429_PC1_FUNC_ETH_MDC 0x210c -#define STM32F429_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F429_PC1_FUNC_ANALOG 0x2111 - -#define STM32F429_PC2_FUNC_GPIO 0x2200 -#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207 -#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F429_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F429_PC2_FUNC_ANALOG 0x2211 - -#define STM32F429_PC3_FUNC_GPIO 0x2300 -#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F429_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F429_PC3_FUNC_ANALOG 0x2311 - -#define STM32F429_PC4_FUNC_GPIO 0x2400 -#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F429_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F429_PC4_FUNC_ANALOG 0x2411 - -#define STM32F429_PC5_FUNC_GPIO 0x2500 -#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F429_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F429_PC5_FUNC_ANALOG 0x2511 - -#define STM32F429_PC6_FUNC_GPIO 0x2600 -#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F429_PC6_FUNC_USART6_TX 0x2609 -#define STM32F429_PC6_FUNC_SDIO_D6 0x260d -#define STM32F429_PC6_FUNC_DCMI_D0 0x260e -#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F429_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F429_PC6_FUNC_ANALOG 0x2611 - -#define STM32F429_PC7_FUNC_GPIO 0x2700 -#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F429_PC7_FUNC_USART6_RX 0x2709 -#define STM32F429_PC7_FUNC_SDIO_D7 0x270d -#define STM32F429_PC7_FUNC_DCMI_D1 0x270e -#define STM32F429_PC7_FUNC_LCD_G6 0x270f -#define STM32F429_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F429_PC7_FUNC_ANALOG 0x2711 - -#define STM32F429_PC8_FUNC_GPIO 0x2800 -#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F429_PC8_FUNC_USART6_CK 0x2809 -#define STM32F429_PC8_FUNC_SDIO_D0 0x280d -#define STM32F429_PC8_FUNC_DCMI_D2 0x280e -#define STM32F429_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F429_PC8_FUNC_ANALOG 0x2811 - -#define STM32F429_PC9_FUNC_GPIO 0x2900 -#define STM32F429_PC9_FUNC_MCO2 0x2901 -#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F429_PC9_FUNC_SDIO_D1 0x290d -#define STM32F429_PC9_FUNC_DCMI_D3 0x290e -#define STM32F429_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F429_PC9_FUNC_ANALOG 0x2911 - -#define STM32F429_PC10_FUNC_GPIO 0x2a00 -#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F429_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F429_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d -#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F429_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F429_PC11_FUNC_GPIO 0x2b00 -#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06 -#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F429_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F429_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d -#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F429_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F429_PC12_FUNC_GPIO 0x2c00 -#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F429_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F429_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d -#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F429_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F429_PC13_FUNC_GPIO 0x2d00 -#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F429_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F429_PC14_FUNC_GPIO 0x2e00 -#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F429_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F429_PC15_FUNC_GPIO 0x2f00 -#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F429_PC15_FUNC_ANALOG 0x2f11 - - - -#define STM32F429_PD0_FUNC_GPIO 0x3000 -#define STM32F429_PD0_FUNC_CAN1_RX 0x300a -#define STM32F429_PD0_FUNC_FMC_D2 0x300d -#define STM32F429_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F429_PD0_FUNC_ANALOG 0x3011 - -#define STM32F429_PD1_FUNC_GPIO 0x3100 -#define STM32F429_PD1_FUNC_CAN1_TX 0x310a -#define STM32F429_PD1_FUNC_FMC_D3 0x310d -#define STM32F429_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F429_PD1_FUNC_ANALOG 0x3111 - -#define STM32F429_PD2_FUNC_GPIO 0x3200 -#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F429_PD2_FUNC_UART5_RX 0x3209 -#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d -#define STM32F429_PD2_FUNC_DCMI_D11 0x320e -#define STM32F429_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F429_PD2_FUNC_ANALOG 0x3211 - -#define STM32F429_PD3_FUNC_GPIO 0x3300 -#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F429_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F429_PD3_FUNC_FMC_CLK 0x330d -#define STM32F429_PD3_FUNC_DCMI_D5 0x330e -#define STM32F429_PD3_FUNC_LCD_G7 0x330f -#define STM32F429_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F429_PD3_FUNC_ANALOG 0x3311 - -#define STM32F429_PD4_FUNC_GPIO 0x3400 -#define STM32F429_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F429_PD4_FUNC_FMC_NOE 0x340d -#define STM32F429_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F429_PD4_FUNC_ANALOG 0x3411 - -#define STM32F429_PD5_FUNC_GPIO 0x3500 -#define STM32F429_PD5_FUNC_USART2_TX 0x3508 -#define STM32F429_PD5_FUNC_FMC_NWE 0x350d -#define STM32F429_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F429_PD5_FUNC_ANALOG 0x3511 - -#define STM32F429_PD6_FUNC_GPIO 0x3600 -#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F429_PD6_FUNC_USART2_RX 0x3608 -#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F429_PD6_FUNC_DCMI_D10 0x360e -#define STM32F429_PD6_FUNC_LCD_B2 0x360f -#define STM32F429_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F429_PD6_FUNC_ANALOG 0x3611 - -#define STM32F429_PD7_FUNC_GPIO 0x3700 -#define STM32F429_PD7_FUNC_USART2_CK 0x3708 -#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d -#define STM32F429_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F429_PD7_FUNC_ANALOG 0x3711 - -#define STM32F429_PD8_FUNC_GPIO 0x3800 -#define STM32F429_PD8_FUNC_USART3_TX 0x3808 -#define STM32F429_PD8_FUNC_FMC_D13 0x380d -#define STM32F429_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F429_PD8_FUNC_ANALOG 0x3811 - -#define STM32F429_PD9_FUNC_GPIO 0x3900 -#define STM32F429_PD9_FUNC_USART3_RX 0x3908 -#define STM32F429_PD9_FUNC_FMC_D14 0x390d -#define STM32F429_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F429_PD9_FUNC_ANALOG 0x3911 - -#define STM32F429_PD10_FUNC_GPIO 0x3a00 -#define STM32F429_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F429_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F429_PD11_FUNC_GPIO 0x3b00 -#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d -#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F429_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F429_PD12_FUNC_GPIO 0x3c00 -#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d -#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F429_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F429_PD13_FUNC_GPIO 0x3d00 -#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F429_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F429_PD14_FUNC_GPIO 0x3e00 -#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F429_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F429_PD15_FUNC_GPIO 0x3f00 -#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F429_PD15_FUNC_ANALOG 0x3f11 - - - -#define STM32F429_PE0_FUNC_GPIO 0x4000 -#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F429_PE0_FUNC_UART8_RX 0x4009 -#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F429_PE0_FUNC_DCMI_D2 0x400e -#define STM32F429_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F429_PE0_FUNC_ANALOG 0x4011 - -#define STM32F429_PE1_FUNC_GPIO 0x4100 -#define STM32F429_PE1_FUNC_UART8_TX 0x4109 -#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F429_PE1_FUNC_DCMI_D3 0x410e -#define STM32F429_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F429_PE1_FUNC_ANALOG 0x4111 - -#define STM32F429_PE2_FUNC_GPIO 0x4200 -#define STM32F429_PE2_FUNC_TRACECLK 0x4201 -#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F429_PE2_FUNC_FMC_A23 0x420d -#define STM32F429_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F429_PE2_FUNC_ANALOG 0x4211 - -#define STM32F429_PE3_FUNC_GPIO 0x4300 -#define STM32F429_PE3_FUNC_TRACED0 0x4301 -#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F429_PE3_FUNC_FMC_A19 0x430d -#define STM32F429_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F429_PE3_FUNC_ANALOG 0x4311 - -#define STM32F429_PE4_FUNC_GPIO 0x4400 -#define STM32F429_PE4_FUNC_TRACED1 0x4401 -#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F429_PE4_FUNC_FMC_A20 0x440d -#define STM32F429_PE4_FUNC_DCMI_D4 0x440e -#define STM32F429_PE4_FUNC_LCD_B0 0x440f -#define STM32F429_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F429_PE4_FUNC_ANALOG 0x4411 - -#define STM32F429_PE5_FUNC_GPIO 0x4500 -#define STM32F429_PE5_FUNC_TRACED2 0x4501 -#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F429_PE5_FUNC_FMC_A21 0x450d -#define STM32F429_PE5_FUNC_DCMI_D6 0x450e -#define STM32F429_PE5_FUNC_LCD_G0 0x450f -#define STM32F429_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F429_PE5_FUNC_ANALOG 0x4511 - -#define STM32F429_PE6_FUNC_GPIO 0x4600 -#define STM32F429_PE6_FUNC_TRACED3 0x4601 -#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F429_PE6_FUNC_FMC_A22 0x460d -#define STM32F429_PE6_FUNC_DCMI_D7 0x460e -#define STM32F429_PE6_FUNC_LCD_G1 0x460f -#define STM32F429_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F429_PE6_FUNC_ANALOG 0x4611 - -#define STM32F429_PE7_FUNC_GPIO 0x4700 -#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F429_PE7_FUNC_UART7_RX 0x4709 -#define STM32F429_PE7_FUNC_FMC_D4 0x470d -#define STM32F429_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F429_PE7_FUNC_ANALOG 0x4711 - -#define STM32F429_PE8_FUNC_GPIO 0x4800 -#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F429_PE8_FUNC_UART7_TX 0x4809 -#define STM32F429_PE8_FUNC_FMC_D5 0x480d -#define STM32F429_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F429_PE8_FUNC_ANALOG 0x4811 - -#define STM32F429_PE9_FUNC_GPIO 0x4900 -#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F429_PE9_FUNC_FMC_D6 0x490d -#define STM32F429_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F429_PE9_FUNC_ANALOG 0x4911 - -#define STM32F429_PE10_FUNC_GPIO 0x4a00 -#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F429_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F429_PE11_FUNC_GPIO 0x4b00 -#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F429_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F429_PE12_FUNC_GPIO 0x4c00 -#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F429_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F429_PE13_FUNC_GPIO 0x4d00 -#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F429_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F429_PE14_FUNC_GPIO 0x4e00 -#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F429_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F429_PE15_FUNC_GPIO 0x4f00 -#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F429_PE15_FUNC_ANALOG 0x4f11 - - - -#define STM32F429_PF0_FUNC_GPIO 0x5000 -#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F429_PF0_FUNC_FMC_A0 0x500d -#define STM32F429_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F429_PF0_FUNC_ANALOG 0x5011 - -#define STM32F429_PF1_FUNC_GPIO 0x5100 -#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F429_PF1_FUNC_FMC_A1 0x510d -#define STM32F429_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F429_PF1_FUNC_ANALOG 0x5111 - -#define STM32F429_PF2_FUNC_GPIO 0x5200 -#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F429_PF2_FUNC_FMC_A2 0x520d -#define STM32F429_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F429_PF2_FUNC_ANALOG 0x5211 - -#define STM32F429_PF3_FUNC_GPIO 0x5300 -#define STM32F429_PF3_FUNC_FMC_A3 0x530d -#define STM32F429_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F429_PF3_FUNC_ANALOG 0x5311 - -#define STM32F429_PF4_FUNC_GPIO 0x5400 -#define STM32F429_PF4_FUNC_FMC_A4 0x540d -#define STM32F429_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F429_PF4_FUNC_ANALOG 0x5411 - -#define STM32F429_PF5_FUNC_GPIO 0x5500 -#define STM32F429_PF5_FUNC_FMC_A5 0x550d -#define STM32F429_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F429_PF5_FUNC_ANALOG 0x5511 - -#define STM32F429_PF6_FUNC_GPIO 0x5600 -#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F429_PF6_FUNC_UART7_RX 0x5609 -#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d -#define STM32F429_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F429_PF6_FUNC_ANALOG 0x5611 - -#define STM32F429_PF7_FUNC_GPIO 0x5700 -#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F429_PF7_FUNC_UART7_TX 0x5709 -#define STM32F429_PF7_FUNC_FMC_NREG 0x570d -#define STM32F429_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F429_PF7_FUNC_ANALOG 0x5711 - -#define STM32F429_PF8_FUNC_GPIO 0x5800 -#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d -#define STM32F429_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F429_PF8_FUNC_ANALOG 0x5811 - -#define STM32F429_PF9_FUNC_GPIO 0x5900 -#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F429_PF9_FUNC_FMC_CD 0x590d -#define STM32F429_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F429_PF9_FUNC_ANALOG 0x5911 - -#define STM32F429_PF10_FUNC_GPIO 0x5a00 -#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d -#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F429_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F429_PF11_FUNC_GPIO 0x5b00 -#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F429_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F429_PF12_FUNC_GPIO 0x5c00 -#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F429_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F429_PF13_FUNC_GPIO 0x5d00 -#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F429_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F429_PF14_FUNC_GPIO 0x5e00 -#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F429_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F429_PF15_FUNC_GPIO 0x5f00 -#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F429_PF15_FUNC_ANALOG 0x5f11 - - - -#define STM32F429_PG0_FUNC_GPIO 0x6000 -#define STM32F429_PG0_FUNC_FMC_A10 0x600d -#define STM32F429_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F429_PG0_FUNC_ANALOG 0x6011 - -#define STM32F429_PG1_FUNC_GPIO 0x6100 -#define STM32F429_PG1_FUNC_FMC_A11 0x610d -#define STM32F429_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F429_PG1_FUNC_ANALOG 0x6111 - -#define STM32F429_PG2_FUNC_GPIO 0x6200 -#define STM32F429_PG2_FUNC_FMC_A12 0x620d -#define STM32F429_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F429_PG2_FUNC_ANALOG 0x6211 - -#define STM32F429_PG3_FUNC_GPIO 0x6300 -#define STM32F429_PG3_FUNC_FMC_A13 0x630d -#define STM32F429_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F429_PG3_FUNC_ANALOG 0x6311 - -#define STM32F429_PG4_FUNC_GPIO 0x6400 -#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F429_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F429_PG4_FUNC_ANALOG 0x6411 - -#define STM32F429_PG5_FUNC_GPIO 0x6500 -#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F429_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F429_PG5_FUNC_ANALOG 0x6511 - -#define STM32F429_PG6_FUNC_GPIO 0x6600 -#define STM32F429_PG6_FUNC_FMC_INT2 0x660d -#define STM32F429_PG6_FUNC_DCMI_D12 0x660e -#define STM32F429_PG6_FUNC_LCD_R7 0x660f -#define STM32F429_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F429_PG6_FUNC_ANALOG 0x6611 - -#define STM32F429_PG7_FUNC_GPIO 0x6700 -#define STM32F429_PG7_FUNC_USART6_CK 0x6709 -#define STM32F429_PG7_FUNC_FMC_INT3 0x670d -#define STM32F429_PG7_FUNC_DCMI_D13 0x670e -#define STM32F429_PG7_FUNC_LCD_CLK 0x670f -#define STM32F429_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F429_PG7_FUNC_ANALOG 0x6711 - -#define STM32F429_PG8_FUNC_GPIO 0x6800 -#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F429_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F429_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F429_PG8_FUNC_ANALOG 0x6811 - -#define STM32F429_PG9_FUNC_GPIO 0x6900 -#define STM32F429_PG9_FUNC_USART6_RX 0x6909 -#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d -#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F429_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F429_PG9_FUNC_ANALOG 0x6911 - -#define STM32F429_PG10_FUNC_GPIO 0x6a00 -#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d -#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F429_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F429_PG11_FUNC_GPIO 0x6b00 -#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d -#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F429_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F429_PG12_FUNC_GPIO 0x6c00 -#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F429_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F429_PG13_FUNC_GPIO 0x6d00 -#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F429_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F429_PG14_FUNC_GPIO 0x6e00 -#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F429_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F429_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F429_PG15_FUNC_GPIO 0x6f00 -#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F429_PG15_FUNC_ANALOG 0x6f11 - - - -#define STM32F429_PH0_FUNC_GPIO 0x7000 -#define STM32F429_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F429_PH0_FUNC_ANALOG 0x7011 - -#define STM32F429_PH1_FUNC_GPIO 0x7100 -#define STM32F429_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F429_PH1_FUNC_ANALOG 0x7111 - -#define STM32F429_PH2_FUNC_GPIO 0x7200 -#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F429_PH2_FUNC_LCD_R0 0x720f -#define STM32F429_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F429_PH2_FUNC_ANALOG 0x7211 - -#define STM32F429_PH3_FUNC_GPIO 0x7300 -#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F429_PH3_FUNC_LCD_R1 0x730f -#define STM32F429_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F429_PH3_FUNC_ANALOG 0x7311 - -#define STM32F429_PH4_FUNC_GPIO 0x7400 -#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F429_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F429_PH4_FUNC_ANALOG 0x7411 - -#define STM32F429_PH5_FUNC_GPIO 0x7500 -#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F429_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F429_PH5_FUNC_ANALOG 0x7511 - -#define STM32F429_PH6_FUNC_GPIO 0x7600 -#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F429_PH6_FUNC_DCMI_D8 0x760e -#define STM32F429_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F429_PH6_FUNC_ANALOG 0x7611 - -#define STM32F429_PH7_FUNC_GPIO 0x7700 -#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F429_PH7_FUNC_DCMI_D9 0x770e -#define STM32F429_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F429_PH7_FUNC_ANALOG 0x7711 - -#define STM32F429_PH8_FUNC_GPIO 0x7800 -#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F429_PH8_FUNC_FMC_D16 0x780d -#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F429_PH8_FUNC_LCD_R2 0x780f -#define STM32F429_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F429_PH8_FUNC_ANALOG 0x7811 - -#define STM32F429_PH9_FUNC_GPIO 0x7900 -#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F429_PH9_FUNC_FMC_D17 0x790d -#define STM32F429_PH9_FUNC_DCMI_D0 0x790e -#define STM32F429_PH9_FUNC_LCD_R3 0x790f -#define STM32F429_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F429_PH9_FUNC_ANALOG 0x7911 - -#define STM32F429_PH10_FUNC_GPIO 0x7a00 -#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F429_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F429_PH11_FUNC_GPIO 0x7b00 -#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F429_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F429_PH12_FUNC_GPIO 0x7c00 -#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F429_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F429_PH13_FUNC_GPIO 0x7d00 -#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F429_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F429_PH14_FUNC_GPIO 0x7e00 -#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F429_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F429_PH15_FUNC_GPIO 0x7f00 -#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F429_PH15_FUNC_ANALOG 0x7f11 - - - -#define STM32F429_PI0_FUNC_GPIO 0x8000 -#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F429_PI0_FUNC_FMC_D24 0x800d -#define STM32F429_PI0_FUNC_DCMI_D13 0x800e -#define STM32F429_PI0_FUNC_LCD_G5 0x800f -#define STM32F429_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F429_PI0_FUNC_ANALOG 0x8011 - -#define STM32F429_PI1_FUNC_GPIO 0x8100 -#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F429_PI1_FUNC_FMC_D25 0x810d -#define STM32F429_PI1_FUNC_DCMI_D8 0x810e -#define STM32F429_PI1_FUNC_LCD_G6 0x810f -#define STM32F429_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F429_PI1_FUNC_ANALOG 0x8111 - -#define STM32F429_PI2_FUNC_GPIO 0x8200 -#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207 -#define STM32F429_PI2_FUNC_FMC_D26 0x820d -#define STM32F429_PI2_FUNC_DCMI_D9 0x820e -#define STM32F429_PI2_FUNC_LCD_G7 0x820f -#define STM32F429_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F429_PI2_FUNC_ANALOG 0x8211 - -#define STM32F429_PI3_FUNC_GPIO 0x8300 -#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F429_PI3_FUNC_FMC_D27 0x830d -#define STM32F429_PI3_FUNC_DCMI_D10 0x830e -#define STM32F429_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F429_PI3_FUNC_ANALOG 0x8311 - -#define STM32F429_PI4_FUNC_GPIO 0x8400 -#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F429_PI4_FUNC_DCMI_D5 0x840e -#define STM32F429_PI4_FUNC_LCD_B4 0x840f -#define STM32F429_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F429_PI4_FUNC_ANALOG 0x8411 - -#define STM32F429_PI5_FUNC_GPIO 0x8500 -#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F429_PI5_FUNC_LCD_B5 0x850f -#define STM32F429_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F429_PI5_FUNC_ANALOG 0x8511 - -#define STM32F429_PI6_FUNC_GPIO 0x8600 -#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F429_PI6_FUNC_FMC_D28 0x860d -#define STM32F429_PI6_FUNC_DCMI_D6 0x860e -#define STM32F429_PI6_FUNC_LCD_B6 0x860f -#define STM32F429_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F429_PI6_FUNC_ANALOG 0x8611 - -#define STM32F429_PI7_FUNC_GPIO 0x8700 -#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F429_PI7_FUNC_FMC_D29 0x870d -#define STM32F429_PI7_FUNC_DCMI_D7 0x870e -#define STM32F429_PI7_FUNC_LCD_B7 0x870f -#define STM32F429_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F429_PI7_FUNC_ANALOG 0x8711 - -#define STM32F429_PI8_FUNC_GPIO 0x8800 -#define STM32F429_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F429_PI8_FUNC_ANALOG 0x8811 - -#define STM32F429_PI9_FUNC_GPIO 0x8900 -#define STM32F429_PI9_FUNC_CAN1_RX 0x890a -#define STM32F429_PI9_FUNC_FMC_D30 0x890d -#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F429_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F429_PI9_FUNC_ANALOG 0x8911 - -#define STM32F429_PI10_FUNC_GPIO 0x8a00 -#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F429_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F429_PI11_FUNC_GPIO 0x8b00 -#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F429_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F429_PI12_FUNC_GPIO 0x8c00 -#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F429_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F429_PI13_FUNC_GPIO 0x8d00 -#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F429_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F429_PI14_FUNC_GPIO 0x8e00 -#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F429_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F429_PI15_FUNC_GPIO 0x8f00 -#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F429_PI15_FUNC_ANALOG 0x8f11 - - - -#define STM32F429_PJ0_FUNC_GPIO 0x9000 -#define STM32F429_PJ0_FUNC_LCD_R1 0x900f -#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F429_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F429_PJ1_FUNC_GPIO 0x9100 -#define STM32F429_PJ1_FUNC_LCD_R2 0x910f -#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F429_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F429_PJ2_FUNC_GPIO 0x9200 -#define STM32F429_PJ2_FUNC_LCD_R3 0x920f -#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F429_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F429_PJ3_FUNC_GPIO 0x9300 -#define STM32F429_PJ3_FUNC_LCD_R4 0x930f -#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F429_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F429_PJ4_FUNC_GPIO 0x9400 -#define STM32F429_PJ4_FUNC_LCD_R5 0x940f -#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F429_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F429_PJ5_FUNC_GPIO 0x9500 -#define STM32F429_PJ5_FUNC_LCD_R6 0x950f -#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F429_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F429_PJ6_FUNC_GPIO 0x9600 -#define STM32F429_PJ6_FUNC_LCD_R7 0x960f -#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F429_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F429_PJ7_FUNC_GPIO 0x9700 -#define STM32F429_PJ7_FUNC_LCD_G0 0x970f -#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F429_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F429_PJ8_FUNC_GPIO 0x9800 -#define STM32F429_PJ8_FUNC_LCD_G1 0x980f -#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F429_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F429_PJ9_FUNC_GPIO 0x9900 -#define STM32F429_PJ9_FUNC_LCD_G2 0x990f -#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F429_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F429_PJ10_FUNC_GPIO 0x9a00 -#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F429_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F429_PJ11_FUNC_GPIO 0x9b00 -#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F429_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F429_PJ12_FUNC_GPIO 0x9c00 -#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F429_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F429_PJ13_FUNC_GPIO 0x9d00 -#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F429_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F429_PJ14_FUNC_GPIO 0x9e00 -#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F429_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F429_PJ15_FUNC_GPIO 0x9f00 -#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F429_PJ15_FUNC_ANALOG 0x9f11 - - - -#define STM32F429_PK0_FUNC_GPIO 0xa000 -#define STM32F429_PK0_FUNC_LCD_G5 0xa00f -#define STM32F429_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F429_PK0_FUNC_ANALOG 0xa011 - -#define STM32F429_PK1_FUNC_GPIO 0xa100 -#define STM32F429_PK1_FUNC_LCD_G6 0xa10f -#define STM32F429_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F429_PK1_FUNC_ANALOG 0xa111 - -#define STM32F429_PK2_FUNC_GPIO 0xa200 -#define STM32F429_PK2_FUNC_LCD_G7 0xa20f -#define STM32F429_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F429_PK2_FUNC_ANALOG 0xa211 - -#define STM32F429_PK3_FUNC_GPIO 0xa300 -#define STM32F429_PK3_FUNC_LCD_B4 0xa30f -#define STM32F429_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F429_PK3_FUNC_ANALOG 0xa311 - -#define STM32F429_PK4_FUNC_GPIO 0xa400 -#define STM32F429_PK4_FUNC_LCD_B5 0xa40f -#define STM32F429_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F429_PK4_FUNC_ANALOG 0xa411 - -#define STM32F429_PK5_FUNC_GPIO 0xa500 -#define STM32F429_PK5_FUNC_LCD_B6 0xa50f -#define STM32F429_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F429_PK5_FUNC_ANALOG 0xa511 - -#define STM32F429_PK6_FUNC_GPIO 0xa600 -#define STM32F429_PK6_FUNC_LCD_B7 0xa60f -#define STM32F429_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F429_PK6_FUNC_ANALOG 0xa611 - -#define STM32F429_PK7_FUNC_GPIO 0xa700 -#define STM32F429_PK7_FUNC_LCD_DE 0xa70f -#define STM32F429_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F429_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h deleted file mode 100644 index 6348c6a830e9..000000000000 --- a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h +++ /dev/null @@ -1,1324 +0,0 @@ -#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H -#define _DT_BINDINGS_STM32F746_PINFUNC_H - -#define STM32F746_PA0_FUNC_GPIO 0x0 -#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32F746_PA0_FUNC_TIM5_CH1 0x3 -#define STM32F746_PA0_FUNC_TIM8_ETR 0x4 -#define STM32F746_PA0_FUNC_USART2_CTS 0x8 -#define STM32F746_PA0_FUNC_UART4_TX 0x9 -#define STM32F746_PA0_FUNC_SAI2_SD_B 0xb -#define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32F746_PA0_FUNC_EVENTOUT 0x10 -#define STM32F746_PA0_FUNC_ANALOG 0x11 - -#define STM32F746_PA1_FUNC_GPIO 0x100 -#define STM32F746_PA1_FUNC_TIM2_CH2 0x102 -#define STM32F746_PA1_FUNC_TIM5_CH2 0x103 -#define STM32F746_PA1_FUNC_USART2_RTS 0x108 -#define STM32F746_PA1_FUNC_UART4_RX 0x109 -#define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a -#define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b -#define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32F746_PA1_FUNC_LCD_R2 0x10f -#define STM32F746_PA1_FUNC_EVENTOUT 0x110 -#define STM32F746_PA1_FUNC_ANALOG 0x111 - -#define STM32F746_PA2_FUNC_GPIO 0x200 -#define STM32F746_PA2_FUNC_TIM2_CH3 0x202 -#define STM32F746_PA2_FUNC_TIM5_CH3 0x203 -#define STM32F746_PA2_FUNC_TIM9_CH1 0x204 -#define STM32F746_PA2_FUNC_USART2_TX 0x208 -#define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209 -#define STM32F746_PA2_FUNC_ETH_MDIO 0x20c -#define STM32F746_PA2_FUNC_LCD_R1 0x20f -#define STM32F746_PA2_FUNC_EVENTOUT 0x210 -#define STM32F746_PA2_FUNC_ANALOG 0x211 - -#define STM32F746_PA3_FUNC_GPIO 0x300 -#define STM32F746_PA3_FUNC_TIM2_CH4 0x302 -#define STM32F746_PA3_FUNC_TIM5_CH4 0x303 -#define STM32F746_PA3_FUNC_TIM9_CH2 0x304 -#define STM32F746_PA3_FUNC_USART2_RX 0x308 -#define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32F746_PA3_FUNC_LCD_B5 0x30f -#define STM32F746_PA3_FUNC_EVENTOUT 0x310 -#define STM32F746_PA3_FUNC_ANALOG 0x311 - -#define STM32F746_PA4_FUNC_GPIO 0x400 -#define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 -#define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32F746_PA4_FUNC_USART2_CK 0x408 -#define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32F746_PA4_FUNC_EVENTOUT 0x410 -#define STM32F746_PA4_FUNC_ANALOG 0x411 - -#define STM32F746_PA5_FUNC_GPIO 0x500 -#define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32F746_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 -#define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32F746_PA5_FUNC_LCD_R4 0x50f -#define STM32F746_PA5_FUNC_EVENTOUT 0x510 -#define STM32F746_PA5_FUNC_ANALOG 0x511 - -#define STM32F746_PA6_FUNC_GPIO 0x600 -#define STM32F746_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32F746_PA6_FUNC_TIM3_CH1 0x603 -#define STM32F746_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32F746_PA6_FUNC_SPI1_MISO 0x606 -#define STM32F746_PA6_FUNC_TIM13_CH1 0x60a -#define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32F746_PA6_FUNC_LCD_G2 0x60f -#define STM32F746_PA6_FUNC_EVENTOUT 0x610 -#define STM32F746_PA6_FUNC_ANALOG 0x611 - -#define STM32F746_PA7_FUNC_GPIO 0x700 -#define STM32F746_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32F746_PA7_FUNC_TIM3_CH2 0x703 -#define STM32F746_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706 -#define STM32F746_PA7_FUNC_TIM14_CH1 0x70a -#define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d -#define STM32F746_PA7_FUNC_EVENTOUT 0x710 -#define STM32F746_PA7_FUNC_ANALOG 0x711 - -#define STM32F746_PA8_FUNC_GPIO 0x800 -#define STM32F746_PA8_FUNC_MCO1 0x801 -#define STM32F746_PA8_FUNC_TIM1_CH1 0x802 -#define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804 -#define STM32F746_PA8_FUNC_I2C3_SCL 0x805 -#define STM32F746_PA8_FUNC_USART1_CK 0x808 -#define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32F746_PA8_FUNC_LCD_R6 0x80f -#define STM32F746_PA8_FUNC_EVENTOUT 0x810 -#define STM32F746_PA8_FUNC_ANALOG 0x811 - -#define STM32F746_PA9_FUNC_GPIO 0x900 -#define STM32F746_PA9_FUNC_TIM1_CH2 0x902 -#define STM32F746_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 -#define STM32F746_PA9_FUNC_USART1_TX 0x908 -#define STM32F746_PA9_FUNC_DCMI_D0 0x90e -#define STM32F746_PA9_FUNC_EVENTOUT 0x910 -#define STM32F746_PA9_FUNC_ANALOG 0x911 - -#define STM32F746_PA10_FUNC_GPIO 0xa00 -#define STM32F746_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32F746_PA10_FUNC_USART1_RX 0xa08 -#define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32F746_PA10_FUNC_DCMI_D1 0xa0e -#define STM32F746_PA10_FUNC_EVENTOUT 0xa10 -#define STM32F746_PA10_FUNC_ANALOG 0xa11 - -#define STM32F746_PA11_FUNC_GPIO 0xb00 -#define STM32F746_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32F746_PA11_FUNC_USART1_CTS 0xb08 -#define STM32F746_PA11_FUNC_CAN1_RX 0xb0a -#define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32F746_PA11_FUNC_LCD_R4 0xb0f -#define STM32F746_PA11_FUNC_EVENTOUT 0xb10 -#define STM32F746_PA11_FUNC_ANALOG 0xb11 - -#define STM32F746_PA12_FUNC_GPIO 0xc00 -#define STM32F746_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32F746_PA12_FUNC_USART1_RTS 0xc08 -#define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09 -#define STM32F746_PA12_FUNC_CAN1_TX 0xc0a -#define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32F746_PA12_FUNC_LCD_R5 0xc0f -#define STM32F746_PA12_FUNC_EVENTOUT 0xc10 -#define STM32F746_PA12_FUNC_ANALOG 0xc11 - -#define STM32F746_PA13_FUNC_GPIO 0xd00 -#define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32F746_PA13_FUNC_EVENTOUT 0xd10 -#define STM32F746_PA13_FUNC_ANALOG 0xd11 - -#define STM32F746_PA14_FUNC_GPIO 0xe00 -#define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32F746_PA14_FUNC_EVENTOUT 0xe10 -#define STM32F746_PA14_FUNC_ANALOG 0xe11 - -#define STM32F746_PA15_FUNC_GPIO 0xf00 -#define STM32F746_PA15_FUNC_JTDI 0xf01 -#define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32F746_PA15_FUNC_HDMI_CEC 0xf05 -#define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 -#define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32F746_PA15_FUNC_UART4_RTS 0xf09 -#define STM32F746_PA15_FUNC_EVENTOUT 0xf10 -#define STM32F746_PA15_FUNC_ANALOG 0xf11 - - -#define STM32F746_PB0_FUNC_GPIO 0x1000 -#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32F746_PB0_FUNC_UART4_CTS 0x1009 -#define STM32F746_PB0_FUNC_LCD_R3 0x100a -#define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32F746_PB0_FUNC_EVENTOUT 0x1010 -#define STM32F746_PB0_FUNC_ANALOG 0x1011 - -#define STM32F746_PB1_FUNC_GPIO 0x1100 -#define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32F746_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32F746_PB1_FUNC_LCD_R6 0x110a -#define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32F746_PB1_FUNC_EVENTOUT 0x1110 -#define STM32F746_PB1_FUNC_ANALOG 0x1111 - -#define STM32F746_PB2_FUNC_GPIO 0x1200 -#define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207 -#define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208 -#define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a -#define STM32F746_PB2_FUNC_EVENTOUT 0x1210 -#define STM32F746_PB2_FUNC_ANALOG 0x1211 - -#define STM32F746_PB3_FUNC_GPIO 0x1300 -#define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 -#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32F746_PB3_FUNC_EVENTOUT 0x1310 -#define STM32F746_PB3_FUNC_ANALOG 0x1311 - -#define STM32F746_PB4_FUNC_GPIO 0x1400 -#define STM32F746_PB4_FUNC_NJTRST 0x1401 -#define STM32F746_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406 -#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407 -#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 -#define STM32F746_PB4_FUNC_EVENTOUT 0x1410 -#define STM32F746_PB4_FUNC_ANALOG 0x1411 - -#define STM32F746_PB5_FUNC_GPIO 0x1500 -#define STM32F746_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506 -#define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 -#define STM32F746_PB5_FUNC_CAN2_RX 0x150a -#define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32F746_PB5_FUNC_DCMI_D10 0x150e -#define STM32F746_PB5_FUNC_EVENTOUT 0x1510 -#define STM32F746_PB5_FUNC_ANALOG 0x1511 - -#define STM32F746_PB6_FUNC_GPIO 0x1600 -#define STM32F746_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32F746_PB6_FUNC_HDMI_CEC 0x1604 -#define STM32F746_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32F746_PB6_FUNC_USART1_TX 0x1608 -#define STM32F746_PB6_FUNC_CAN2_TX 0x160a -#define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b -#define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32F746_PB6_FUNC_DCMI_D5 0x160e -#define STM32F746_PB6_FUNC_EVENTOUT 0x1610 -#define STM32F746_PB6_FUNC_ANALOG 0x1611 - -#define STM32F746_PB7_FUNC_GPIO 0x1700 -#define STM32F746_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32F746_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32F746_PB7_FUNC_USART1_RX 0x1708 -#define STM32F746_PB7_FUNC_FMC_NL 0x170d -#define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32F746_PB7_FUNC_EVENTOUT 0x1710 -#define STM32F746_PB7_FUNC_ANALOG 0x1711 - -#define STM32F746_PB8_FUNC_GPIO 0x1800 -#define STM32F746_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32F746_PB8_FUNC_TIM10_CH1 0x1804 -#define STM32F746_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32F746_PB8_FUNC_CAN1_RX 0x180a -#define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d -#define STM32F746_PB8_FUNC_DCMI_D6 0x180e -#define STM32F746_PB8_FUNC_LCD_B6 0x180f -#define STM32F746_PB8_FUNC_EVENTOUT 0x1810 -#define STM32F746_PB8_FUNC_ANALOG 0x1811 - -#define STM32F746_PB9_FUNC_GPIO 0x1900 -#define STM32F746_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32F746_PB9_FUNC_TIM11_CH1 0x1904 -#define STM32F746_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32F746_PB9_FUNC_CAN1_TX 0x190a -#define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d -#define STM32F746_PB9_FUNC_DCMI_D7 0x190e -#define STM32F746_PB9_FUNC_LCD_B7 0x190f -#define STM32F746_PB9_FUNC_EVENTOUT 0x1910 -#define STM32F746_PB9_FUNC_ANALOG 0x1911 - -#define STM32F746_PB10_FUNC_GPIO 0x1a00 -#define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32F746_PB10_FUNC_USART3_TX 0x1a08 -#define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32F746_PB10_FUNC_LCD_G4 0x1a0f -#define STM32F746_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32F746_PB10_FUNC_ANALOG 0x1a11 - -#define STM32F746_PB11_FUNC_GPIO 0x1b00 -#define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32F746_PB11_FUNC_USART3_RX 0x1b08 -#define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32F746_PB11_FUNC_LCD_G5 0x1b0f -#define STM32F746_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32F746_PB11_FUNC_ANALOG 0x1b11 - -#define STM32F746_PB12_FUNC_GPIO 0x1c00 -#define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32F746_PB12_FUNC_USART3_CK 0x1c08 -#define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32F746_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32F746_PB12_FUNC_ANALOG 0x1c11 - -#define STM32F746_PB13_FUNC_GPIO 0x1d00 -#define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32F746_PB13_FUNC_USART3_CTS 0x1d08 -#define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32F746_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32F746_PB13_FUNC_ANALOG 0x1d11 - -#define STM32F746_PB14_FUNC_GPIO 0x1e00 -#define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06 -#define STM32F746_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a -#define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32F746_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32F746_PB14_FUNC_ANALOG 0x1e11 - -#define STM32F746_PB15_FUNC_GPIO 0x1f00 -#define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 -#define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a -#define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32F746_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32F746_PB15_FUNC_ANALOG 0x1f11 - - -#define STM32F746_PC0_FUNC_GPIO 0x2000 -#define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009 -#define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32F746_PC0_FUNC_LCD_R5 0x200f -#define STM32F746_PC0_FUNC_EVENTOUT 0x2010 -#define STM32F746_PC0_FUNC_ANALOG 0x2011 - -#define STM32F746_PC1_FUNC_GPIO 0x2100 -#define STM32F746_PC1_FUNC_TRACED0 0x2101 -#define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106 -#define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107 -#define STM32F746_PC1_FUNC_ETH_MDC 0x210c -#define STM32F746_PC1_FUNC_EVENTOUT 0x2110 -#define STM32F746_PC1_FUNC_ANALOG 0x2111 - -#define STM32F746_PC2_FUNC_GPIO 0x2200 -#define STM32F746_PC2_FUNC_SPI2_MISO 0x2206 -#define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32F746_PC2_FUNC_EVENTOUT 0x2210 -#define STM32F746_PC2_FUNC_ANALOG 0x2211 - -#define STM32F746_PC3_FUNC_GPIO 0x2300 -#define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 -#define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32F746_PC3_FUNC_EVENTOUT 0x2310 -#define STM32F746_PC3_FUNC_ANALOG 0x2311 - -#define STM32F746_PC4_FUNC_GPIO 0x2400 -#define STM32F746_PC4_FUNC_I2S1_MCK 0x2406 -#define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409 -#define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d -#define STM32F746_PC4_FUNC_EVENTOUT 0x2410 -#define STM32F746_PC4_FUNC_ANALOG 0x2411 - -#define STM32F746_PC5_FUNC_GPIO 0x2500 -#define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509 -#define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d -#define STM32F746_PC5_FUNC_EVENTOUT 0x2510 -#define STM32F746_PC5_FUNC_ANALOG 0x2511 - -#define STM32F746_PC6_FUNC_GPIO 0x2600 -#define STM32F746_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32F746_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32F746_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32F746_PC6_FUNC_USART6_TX 0x2609 -#define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d -#define STM32F746_PC6_FUNC_DCMI_D0 0x260e -#define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32F746_PC6_FUNC_EVENTOUT 0x2610 -#define STM32F746_PC6_FUNC_ANALOG 0x2611 - -#define STM32F746_PC7_FUNC_GPIO 0x2700 -#define STM32F746_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32F746_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32F746_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32F746_PC7_FUNC_USART6_RX 0x2709 -#define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d -#define STM32F746_PC7_FUNC_DCMI_D1 0x270e -#define STM32F746_PC7_FUNC_LCD_G6 0x270f -#define STM32F746_PC7_FUNC_EVENTOUT 0x2710 -#define STM32F746_PC7_FUNC_ANALOG 0x2711 - -#define STM32F746_PC8_FUNC_GPIO 0x2800 -#define STM32F746_PC8_FUNC_TRACED1 0x2801 -#define STM32F746_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32F746_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32F746_PC8_FUNC_UART5_RTS 0x2808 -#define STM32F746_PC8_FUNC_USART6_CK 0x2809 -#define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d -#define STM32F746_PC8_FUNC_DCMI_D2 0x280e -#define STM32F746_PC8_FUNC_EVENTOUT 0x2810 -#define STM32F746_PC8_FUNC_ANALOG 0x2811 - -#define STM32F746_PC9_FUNC_GPIO 0x2900 -#define STM32F746_PC9_FUNC_MCO2 0x2901 -#define STM32F746_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32F746_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32F746_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32F746_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32F746_PC9_FUNC_UART5_CTS 0x2908 -#define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a -#define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d -#define STM32F746_PC9_FUNC_DCMI_D3 0x290e -#define STM32F746_PC9_FUNC_EVENTOUT 0x2910 -#define STM32F746_PC9_FUNC_ANALOG 0x2911 - -#define STM32F746_PC10_FUNC_GPIO 0x2a00 -#define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32F746_PC10_FUNC_USART3_TX 0x2a08 -#define STM32F746_PC10_FUNC_UART4_TX 0x2a09 -#define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a -#define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d -#define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32F746_PC10_FUNC_LCD_R2 0x2a0f -#define STM32F746_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32F746_PC10_FUNC_ANALOG 0x2a11 - -#define STM32F746_PC11_FUNC_GPIO 0x2b00 -#define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07 -#define STM32F746_PC11_FUNC_USART3_RX 0x2b08 -#define STM32F746_PC11_FUNC_UART4_RX 0x2b09 -#define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a -#define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d -#define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32F746_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32F746_PC11_FUNC_ANALOG 0x2b11 - -#define STM32F746_PC12_FUNC_GPIO 0x2c00 -#define STM32F746_PC12_FUNC_TRACED3 0x2c01 -#define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 -#define STM32F746_PC12_FUNC_USART3_CK 0x2c08 -#define STM32F746_PC12_FUNC_UART5_TX 0x2c09 -#define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d -#define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32F746_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32F746_PC12_FUNC_ANALOG 0x2c11 - -#define STM32F746_PC13_FUNC_GPIO 0x2d00 -#define STM32F746_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32F746_PC13_FUNC_ANALOG 0x2d11 - -#define STM32F746_PC14_FUNC_GPIO 0x2e00 -#define STM32F746_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32F746_PC14_FUNC_ANALOG 0x2e11 - -#define STM32F746_PC15_FUNC_GPIO 0x2f00 -#define STM32F746_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32F746_PC15_FUNC_ANALOG 0x2f11 - - -#define STM32F746_PD0_FUNC_GPIO 0x3000 -#define STM32F746_PD0_FUNC_CAN1_RX 0x300a -#define STM32F746_PD0_FUNC_FMC_D2 0x300d -#define STM32F746_PD0_FUNC_EVENTOUT 0x3010 -#define STM32F746_PD0_FUNC_ANALOG 0x3011 - -#define STM32F746_PD1_FUNC_GPIO 0x3100 -#define STM32F746_PD1_FUNC_CAN1_TX 0x310a -#define STM32F746_PD1_FUNC_FMC_D3 0x310d -#define STM32F746_PD1_FUNC_EVENTOUT 0x3110 -#define STM32F746_PD1_FUNC_ANALOG 0x3111 - -#define STM32F746_PD2_FUNC_GPIO 0x3200 -#define STM32F746_PD2_FUNC_TRACED2 0x3201 -#define STM32F746_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32F746_PD2_FUNC_UART5_RX 0x3209 -#define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d -#define STM32F746_PD2_FUNC_DCMI_D11 0x320e -#define STM32F746_PD2_FUNC_EVENTOUT 0x3210 -#define STM32F746_PD2_FUNC_ANALOG 0x3211 - -#define STM32F746_PD3_FUNC_GPIO 0x3300 -#define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32F746_PD3_FUNC_USART2_CTS 0x3308 -#define STM32F746_PD3_FUNC_FMC_CLK 0x330d -#define STM32F746_PD3_FUNC_DCMI_D5 0x330e -#define STM32F746_PD3_FUNC_LCD_G7 0x330f -#define STM32F746_PD3_FUNC_EVENTOUT 0x3310 -#define STM32F746_PD3_FUNC_ANALOG 0x3311 - -#define STM32F746_PD4_FUNC_GPIO 0x3400 -#define STM32F746_PD4_FUNC_USART2_RTS 0x3408 -#define STM32F746_PD4_FUNC_FMC_NOE 0x340d -#define STM32F746_PD4_FUNC_EVENTOUT 0x3410 -#define STM32F746_PD4_FUNC_ANALOG 0x3411 - -#define STM32F746_PD5_FUNC_GPIO 0x3500 -#define STM32F746_PD5_FUNC_USART2_TX 0x3508 -#define STM32F746_PD5_FUNC_FMC_NWE 0x350d -#define STM32F746_PD5_FUNC_EVENTOUT 0x3510 -#define STM32F746_PD5_FUNC_ANALOG 0x3511 - -#define STM32F746_PD6_FUNC_GPIO 0x3600 -#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 -#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32F746_PD6_FUNC_USART2_RX 0x3608 -#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32F746_PD6_FUNC_DCMI_D10 0x360e -#define STM32F746_PD6_FUNC_LCD_B2 0x360f -#define STM32F746_PD6_FUNC_EVENTOUT 0x3610 -#define STM32F746_PD6_FUNC_ANALOG 0x3611 - -#define STM32F746_PD7_FUNC_GPIO 0x3700 -#define STM32F746_PD7_FUNC_USART2_CK 0x3708 -#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709 -#define STM32F746_PD7_FUNC_FMC_NE1 0x370d -#define STM32F746_PD7_FUNC_EVENTOUT 0x3710 -#define STM32F746_PD7_FUNC_ANALOG 0x3711 - -#define STM32F746_PD8_FUNC_GPIO 0x3800 -#define STM32F746_PD8_FUNC_USART3_TX 0x3808 -#define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809 -#define STM32F746_PD8_FUNC_FMC_D13 0x380d -#define STM32F746_PD8_FUNC_EVENTOUT 0x3810 -#define STM32F746_PD8_FUNC_ANALOG 0x3811 - -#define STM32F746_PD9_FUNC_GPIO 0x3900 -#define STM32F746_PD9_FUNC_USART3_RX 0x3908 -#define STM32F746_PD9_FUNC_FMC_D14 0x390d -#define STM32F746_PD9_FUNC_EVENTOUT 0x3910 -#define STM32F746_PD9_FUNC_ANALOG 0x3911 - -#define STM32F746_PD10_FUNC_GPIO 0x3a00 -#define STM32F746_PD10_FUNC_USART3_CK 0x3a08 -#define STM32F746_PD10_FUNC_FMC_D15 0x3a0d -#define STM32F746_PD10_FUNC_LCD_B3 0x3a0f -#define STM32F746_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32F746_PD10_FUNC_ANALOG 0x3a11 - -#define STM32F746_PD11_FUNC_GPIO 0x3b00 -#define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05 -#define STM32F746_PD11_FUNC_USART3_CTS 0x3b08 -#define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a -#define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b -#define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d -#define STM32F746_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32F746_PD11_FUNC_ANALOG 0x3b11 - -#define STM32F746_PD12_FUNC_GPIO 0x3c00 -#define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04 -#define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05 -#define STM32F746_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a -#define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b -#define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d -#define STM32F746_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32F746_PD12_FUNC_ANALOG 0x3c11 - -#define STM32F746_PD13_FUNC_GPIO 0x3d00 -#define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04 -#define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05 -#define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a -#define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b -#define STM32F746_PD13_FUNC_FMC_A18 0x3d0d -#define STM32F746_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32F746_PD13_FUNC_ANALOG 0x3d11 - -#define STM32F746_PD14_FUNC_GPIO 0x3e00 -#define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32F746_PD14_FUNC_UART8_CTS 0x3e09 -#define STM32F746_PD14_FUNC_FMC_D0 0x3e0d -#define STM32F746_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32F746_PD14_FUNC_ANALOG 0x3e11 - -#define STM32F746_PD15_FUNC_GPIO 0x3f00 -#define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32F746_PD15_FUNC_UART8_RTS 0x3f09 -#define STM32F746_PD15_FUNC_FMC_D1 0x3f0d -#define STM32F746_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32F746_PD15_FUNC_ANALOG 0x3f11 - - -#define STM32F746_PE0_FUNC_GPIO 0x4000 -#define STM32F746_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004 -#define STM32F746_PE0_FUNC_UART8_RX 0x4009 -#define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b -#define STM32F746_PE0_FUNC_FMC_NBL0 0x400d -#define STM32F746_PE0_FUNC_DCMI_D2 0x400e -#define STM32F746_PE0_FUNC_EVENTOUT 0x4010 -#define STM32F746_PE0_FUNC_ANALOG 0x4011 - -#define STM32F746_PE1_FUNC_GPIO 0x4100 -#define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104 -#define STM32F746_PE1_FUNC_UART8_TX 0x4109 -#define STM32F746_PE1_FUNC_FMC_NBL1 0x410d -#define STM32F746_PE1_FUNC_DCMI_D3 0x410e -#define STM32F746_PE1_FUNC_EVENTOUT 0x4110 -#define STM32F746_PE1_FUNC_ANALOG 0x4111 - -#define STM32F746_PE2_FUNC_GPIO 0x4200 -#define STM32F746_PE2_FUNC_TRACECLK 0x4201 -#define STM32F746_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a -#define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32F746_PE2_FUNC_FMC_A23 0x420d -#define STM32F746_PE2_FUNC_EVENTOUT 0x4210 -#define STM32F746_PE2_FUNC_ANALOG 0x4211 - -#define STM32F746_PE3_FUNC_GPIO 0x4300 -#define STM32F746_PE3_FUNC_TRACED0 0x4301 -#define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32F746_PE3_FUNC_FMC_A19 0x430d -#define STM32F746_PE3_FUNC_EVENTOUT 0x4310 -#define STM32F746_PE3_FUNC_ANALOG 0x4311 - -#define STM32F746_PE4_FUNC_GPIO 0x4400 -#define STM32F746_PE4_FUNC_TRACED1 0x4401 -#define STM32F746_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32F746_PE4_FUNC_FMC_A20 0x440d -#define STM32F746_PE4_FUNC_DCMI_D4 0x440e -#define STM32F746_PE4_FUNC_LCD_B0 0x440f -#define STM32F746_PE4_FUNC_EVENTOUT 0x4410 -#define STM32F746_PE4_FUNC_ANALOG 0x4411 - -#define STM32F746_PE5_FUNC_GPIO 0x4500 -#define STM32F746_PE5_FUNC_TRACED2 0x4501 -#define STM32F746_PE5_FUNC_TIM9_CH1 0x4504 -#define STM32F746_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32F746_PE5_FUNC_FMC_A21 0x450d -#define STM32F746_PE5_FUNC_DCMI_D6 0x450e -#define STM32F746_PE5_FUNC_LCD_G0 0x450f -#define STM32F746_PE5_FUNC_EVENTOUT 0x4510 -#define STM32F746_PE5_FUNC_ANALOG 0x4511 - -#define STM32F746_PE6_FUNC_GPIO 0x4600 -#define STM32F746_PE6_FUNC_TRACED3 0x4601 -#define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602 -#define STM32F746_PE6_FUNC_TIM9_CH2 0x4604 -#define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b -#define STM32F746_PE6_FUNC_FMC_A22 0x460d -#define STM32F746_PE6_FUNC_DCMI_D7 0x460e -#define STM32F746_PE6_FUNC_LCD_G1 0x460f -#define STM32F746_PE6_FUNC_EVENTOUT 0x4610 -#define STM32F746_PE6_FUNC_ANALOG 0x4611 - -#define STM32F746_PE7_FUNC_GPIO 0x4700 -#define STM32F746_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32F746_PE7_FUNC_UART7_RX 0x4709 -#define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b -#define STM32F746_PE7_FUNC_FMC_D4 0x470d -#define STM32F746_PE7_FUNC_EVENTOUT 0x4710 -#define STM32F746_PE7_FUNC_ANALOG 0x4711 - -#define STM32F746_PE8_FUNC_GPIO 0x4800 -#define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32F746_PE8_FUNC_UART7_TX 0x4809 -#define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b -#define STM32F746_PE8_FUNC_FMC_D5 0x480d -#define STM32F746_PE8_FUNC_EVENTOUT 0x4810 -#define STM32F746_PE8_FUNC_ANALOG 0x4811 - -#define STM32F746_PE9_FUNC_GPIO 0x4900 -#define STM32F746_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32F746_PE9_FUNC_UART7_RTS 0x4909 -#define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b -#define STM32F746_PE9_FUNC_FMC_D6 0x490d -#define STM32F746_PE9_FUNC_EVENTOUT 0x4910 -#define STM32F746_PE9_FUNC_ANALOG 0x4911 - -#define STM32F746_PE10_FUNC_GPIO 0x4a00 -#define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32F746_PE10_FUNC_UART7_CTS 0x4a09 -#define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b -#define STM32F746_PE10_FUNC_FMC_D7 0x4a0d -#define STM32F746_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32F746_PE10_FUNC_ANALOG 0x4a11 - -#define STM32F746_PE11_FUNC_GPIO 0x4b00 -#define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b -#define STM32F746_PE11_FUNC_FMC_D8 0x4b0d -#define STM32F746_PE11_FUNC_LCD_G3 0x4b0f -#define STM32F746_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32F746_PE11_FUNC_ANALOG 0x4b11 - -#define STM32F746_PE12_FUNC_GPIO 0x4c00 -#define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b -#define STM32F746_PE12_FUNC_FMC_D9 0x4c0d -#define STM32F746_PE12_FUNC_LCD_B4 0x4c0f -#define STM32F746_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32F746_PE12_FUNC_ANALOG 0x4c11 - -#define STM32F746_PE13_FUNC_GPIO 0x4d00 -#define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b -#define STM32F746_PE13_FUNC_FMC_D10 0x4d0d -#define STM32F746_PE13_FUNC_LCD_DE 0x4d0f -#define STM32F746_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32F746_PE13_FUNC_ANALOG 0x4d11 - -#define STM32F746_PE14_FUNC_GPIO 0x4e00 -#define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b -#define STM32F746_PE14_FUNC_FMC_D11 0x4e0d -#define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32F746_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32F746_PE14_FUNC_ANALOG 0x4e11 - -#define STM32F746_PE15_FUNC_GPIO 0x4f00 -#define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32F746_PE15_FUNC_FMC_D12 0x4f0d -#define STM32F746_PE15_FUNC_LCD_R7 0x4f0f -#define STM32F746_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32F746_PE15_FUNC_ANALOG 0x4f11 - - -#define STM32F746_PF0_FUNC_GPIO 0x5000 -#define STM32F746_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32F746_PF0_FUNC_FMC_A0 0x500d -#define STM32F746_PF0_FUNC_EVENTOUT 0x5010 -#define STM32F746_PF0_FUNC_ANALOG 0x5011 - -#define STM32F746_PF1_FUNC_GPIO 0x5100 -#define STM32F746_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32F746_PF1_FUNC_FMC_A1 0x510d -#define STM32F746_PF1_FUNC_EVENTOUT 0x5110 -#define STM32F746_PF1_FUNC_ANALOG 0x5111 - -#define STM32F746_PF2_FUNC_GPIO 0x5200 -#define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32F746_PF2_FUNC_FMC_A2 0x520d -#define STM32F746_PF2_FUNC_EVENTOUT 0x5210 -#define STM32F746_PF2_FUNC_ANALOG 0x5211 - -#define STM32F746_PF3_FUNC_GPIO 0x5300 -#define STM32F746_PF3_FUNC_FMC_A3 0x530d -#define STM32F746_PF3_FUNC_EVENTOUT 0x5310 -#define STM32F746_PF3_FUNC_ANALOG 0x5311 - -#define STM32F746_PF4_FUNC_GPIO 0x5400 -#define STM32F746_PF4_FUNC_FMC_A4 0x540d -#define STM32F746_PF4_FUNC_EVENTOUT 0x5410 -#define STM32F746_PF4_FUNC_ANALOG 0x5411 - -#define STM32F746_PF5_FUNC_GPIO 0x5500 -#define STM32F746_PF5_FUNC_FMC_A5 0x550d -#define STM32F746_PF5_FUNC_EVENTOUT 0x5510 -#define STM32F746_PF5_FUNC_ANALOG 0x5511 - -#define STM32F746_PF6_FUNC_GPIO 0x5600 -#define STM32F746_PF6_FUNC_TIM10_CH1 0x5604 -#define STM32F746_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32F746_PF6_FUNC_UART7_RX 0x5609 -#define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a -#define STM32F746_PF6_FUNC_EVENTOUT 0x5610 -#define STM32F746_PF6_FUNC_ANALOG 0x5611 - -#define STM32F746_PF7_FUNC_GPIO 0x5700 -#define STM32F746_PF7_FUNC_TIM11_CH1 0x5704 -#define STM32F746_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32F746_PF7_FUNC_UART7_TX 0x5709 -#define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a -#define STM32F746_PF7_FUNC_EVENTOUT 0x5710 -#define STM32F746_PF7_FUNC_ANALOG 0x5711 - -#define STM32F746_PF8_FUNC_GPIO 0x5800 -#define STM32F746_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32F746_PF8_FUNC_UART7_RTS 0x5809 -#define STM32F746_PF8_FUNC_TIM13_CH1 0x580a -#define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b -#define STM32F746_PF8_FUNC_EVENTOUT 0x5810 -#define STM32F746_PF8_FUNC_ANALOG 0x5811 - -#define STM32F746_PF9_FUNC_GPIO 0x5900 -#define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32F746_PF9_FUNC_UART7_CTS 0x5909 -#define STM32F746_PF9_FUNC_TIM14_CH1 0x590a -#define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b -#define STM32F746_PF9_FUNC_EVENTOUT 0x5910 -#define STM32F746_PF9_FUNC_ANALOG 0x5911 - -#define STM32F746_PF10_FUNC_GPIO 0x5a00 -#define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32F746_PF10_FUNC_LCD_DE 0x5a0f -#define STM32F746_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32F746_PF10_FUNC_ANALOG 0x5a11 - -#define STM32F746_PF11_FUNC_GPIO 0x5b00 -#define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b -#define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32F746_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32F746_PF11_FUNC_ANALOG 0x5b11 - -#define STM32F746_PF12_FUNC_GPIO 0x5c00 -#define STM32F746_PF12_FUNC_FMC_A6 0x5c0d -#define STM32F746_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32F746_PF12_FUNC_ANALOG 0x5c11 - -#define STM32F746_PF13_FUNC_GPIO 0x5d00 -#define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05 -#define STM32F746_PF13_FUNC_FMC_A7 0x5d0d -#define STM32F746_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32F746_PF13_FUNC_ANALOG 0x5d11 - -#define STM32F746_PF14_FUNC_GPIO 0x5e00 -#define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05 -#define STM32F746_PF14_FUNC_FMC_A8 0x5e0d -#define STM32F746_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32F746_PF14_FUNC_ANALOG 0x5e11 - -#define STM32F746_PF15_FUNC_GPIO 0x5f00 -#define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05 -#define STM32F746_PF15_FUNC_FMC_A9 0x5f0d -#define STM32F746_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32F746_PF15_FUNC_ANALOG 0x5f11 - - -#define STM32F746_PG0_FUNC_GPIO 0x6000 -#define STM32F746_PG0_FUNC_FMC_A10 0x600d -#define STM32F746_PG0_FUNC_EVENTOUT 0x6010 -#define STM32F746_PG0_FUNC_ANALOG 0x6011 - -#define STM32F746_PG1_FUNC_GPIO 0x6100 -#define STM32F746_PG1_FUNC_FMC_A11 0x610d -#define STM32F746_PG1_FUNC_EVENTOUT 0x6110 -#define STM32F746_PG1_FUNC_ANALOG 0x6111 - -#define STM32F746_PG2_FUNC_GPIO 0x6200 -#define STM32F746_PG2_FUNC_FMC_A12 0x620d -#define STM32F746_PG2_FUNC_EVENTOUT 0x6210 -#define STM32F746_PG2_FUNC_ANALOG 0x6211 - -#define STM32F746_PG3_FUNC_GPIO 0x6300 -#define STM32F746_PG3_FUNC_FMC_A13 0x630d -#define STM32F746_PG3_FUNC_EVENTOUT 0x6310 -#define STM32F746_PG3_FUNC_ANALOG 0x6311 - -#define STM32F746_PG4_FUNC_GPIO 0x6400 -#define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32F746_PG4_FUNC_EVENTOUT 0x6410 -#define STM32F746_PG4_FUNC_ANALOG 0x6411 - -#define STM32F746_PG5_FUNC_GPIO 0x6500 -#define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32F746_PG5_FUNC_EVENTOUT 0x6510 -#define STM32F746_PG5_FUNC_ANALOG 0x6511 - -#define STM32F746_PG6_FUNC_GPIO 0x6600 -#define STM32F746_PG6_FUNC_DCMI_D12 0x660e -#define STM32F746_PG6_FUNC_LCD_R7 0x660f -#define STM32F746_PG6_FUNC_EVENTOUT 0x6610 -#define STM32F746_PG6_FUNC_ANALOG 0x6611 - -#define STM32F746_PG7_FUNC_GPIO 0x6700 -#define STM32F746_PG7_FUNC_USART6_CK 0x6709 -#define STM32F746_PG7_FUNC_FMC_INT 0x670d -#define STM32F746_PG7_FUNC_DCMI_D13 0x670e -#define STM32F746_PG7_FUNC_LCD_CLK 0x670f -#define STM32F746_PG7_FUNC_EVENTOUT 0x6710 -#define STM32F746_PG7_FUNC_ANALOG 0x6711 - -#define STM32F746_PG8_FUNC_GPIO 0x6800 -#define STM32F746_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808 -#define STM32F746_PG8_FUNC_USART6_RTS 0x6809 -#define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32F746_PG8_FUNC_EVENTOUT 0x6810 -#define STM32F746_PG8_FUNC_ANALOG 0x6811 - -#define STM32F746_PG9_FUNC_GPIO 0x6900 -#define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908 -#define STM32F746_PG9_FUNC_USART6_RX 0x6909 -#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a -#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b -#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d -#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32F746_PG9_FUNC_EVENTOUT 0x6910 -#define STM32F746_PG9_FUNC_ANALOG 0x6911 - -#define STM32F746_PG10_FUNC_GPIO 0x6a00 -#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a -#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b -#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d -#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f -#define STM32F746_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32F746_PG10_FUNC_ANALOG 0x6a11 - -#define STM32F746_PG11_FUNC_GPIO 0x6b00 -#define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08 -#define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32F746_PG11_FUNC_LCD_B3 0x6b0f -#define STM32F746_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32F746_PG11_FUNC_ANALOG 0x6b11 - -#define STM32F746_PG12_FUNC_GPIO 0x6c00 -#define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04 -#define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08 -#define STM32F746_PG12_FUNC_USART6_RTS 0x6c09 -#define STM32F746_PG12_FUNC_LCD_B4 0x6c0a -#define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32F746_PG12_FUNC_LCD_B1 0x6c0f -#define STM32F746_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32F746_PG12_FUNC_ANALOG 0x6c11 - -#define STM32F746_PG13_FUNC_GPIO 0x6d00 -#define STM32F746_PG13_FUNC_TRACED0 0x6d01 -#define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04 -#define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32F746_PG13_FUNC_USART6_CTS 0x6d09 -#define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32F746_PG13_FUNC_FMC_A24 0x6d0d -#define STM32F746_PG13_FUNC_LCD_R0 0x6d0f -#define STM32F746_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32F746_PG13_FUNC_ANALOG 0x6d11 - -#define STM32F746_PG14_FUNC_GPIO 0x6e00 -#define STM32F746_PG14_FUNC_TRACED1 0x6e01 -#define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04 -#define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32F746_PG14_FUNC_USART6_TX 0x6e09 -#define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a -#define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32F746_PG14_FUNC_FMC_A25 0x6e0d -#define STM32F746_PG14_FUNC_LCD_B0 0x6e0f -#define STM32F746_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32F746_PG14_FUNC_ANALOG 0x6e11 - -#define STM32F746_PG15_FUNC_GPIO 0x6f00 -#define STM32F746_PG15_FUNC_USART6_CTS 0x6f09 -#define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32F746_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32F746_PG15_FUNC_ANALOG 0x6f11 - - -#define STM32F746_PH0_FUNC_GPIO 0x7000 -#define STM32F746_PH0_FUNC_EVENTOUT 0x7010 -#define STM32F746_PH0_FUNC_ANALOG 0x7011 - -#define STM32F746_PH1_FUNC_GPIO 0x7100 -#define STM32F746_PH1_FUNC_EVENTOUT 0x7110 -#define STM32F746_PH1_FUNC_ANALOG 0x7111 - -#define STM32F746_PH2_FUNC_GPIO 0x7200 -#define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204 -#define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a -#define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b -#define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32F746_PH2_FUNC_LCD_R0 0x720f -#define STM32F746_PH2_FUNC_EVENTOUT 0x7210 -#define STM32F746_PH2_FUNC_ANALOG 0x7211 - -#define STM32F746_PH3_FUNC_GPIO 0x7300 -#define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a -#define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b -#define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32F746_PH3_FUNC_LCD_R1 0x730f -#define STM32F746_PH3_FUNC_EVENTOUT 0x7310 -#define STM32F746_PH3_FUNC_ANALOG 0x7311 - -#define STM32F746_PH4_FUNC_GPIO 0x7400 -#define STM32F746_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32F746_PH4_FUNC_EVENTOUT 0x7410 -#define STM32F746_PH4_FUNC_ANALOG 0x7411 - -#define STM32F746_PH5_FUNC_GPIO 0x7500 -#define STM32F746_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32F746_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32F746_PH5_FUNC_EVENTOUT 0x7510 -#define STM32F746_PH5_FUNC_ANALOG 0x7511 - -#define STM32F746_PH6_FUNC_GPIO 0x7600 -#define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32F746_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32F746_PH6_FUNC_TIM12_CH1 0x760a -#define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32F746_PH6_FUNC_DCMI_D8 0x760e -#define STM32F746_PH6_FUNC_EVENTOUT 0x7610 -#define STM32F746_PH6_FUNC_ANALOG 0x7611 - -#define STM32F746_PH7_FUNC_GPIO 0x7700 -#define STM32F746_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32F746_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32F746_PH7_FUNC_DCMI_D9 0x770e -#define STM32F746_PH7_FUNC_EVENTOUT 0x7710 -#define STM32F746_PH7_FUNC_ANALOG 0x7711 - -#define STM32F746_PH8_FUNC_GPIO 0x7800 -#define STM32F746_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32F746_PH8_FUNC_FMC_D16 0x780d -#define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32F746_PH8_FUNC_LCD_R2 0x780f -#define STM32F746_PH8_FUNC_EVENTOUT 0x7810 -#define STM32F746_PH8_FUNC_ANALOG 0x7811 - -#define STM32F746_PH9_FUNC_GPIO 0x7900 -#define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32F746_PH9_FUNC_TIM12_CH2 0x790a -#define STM32F746_PH9_FUNC_FMC_D17 0x790d -#define STM32F746_PH9_FUNC_DCMI_D0 0x790e -#define STM32F746_PH9_FUNC_LCD_R3 0x790f -#define STM32F746_PH9_FUNC_EVENTOUT 0x7910 -#define STM32F746_PH9_FUNC_ANALOG 0x7911 - -#define STM32F746_PH10_FUNC_GPIO 0x7a00 -#define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05 -#define STM32F746_PH10_FUNC_FMC_D18 0x7a0d -#define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32F746_PH10_FUNC_LCD_R4 0x7a0f -#define STM32F746_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32F746_PH10_FUNC_ANALOG 0x7a11 - -#define STM32F746_PH11_FUNC_GPIO 0x7b00 -#define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05 -#define STM32F746_PH11_FUNC_FMC_D19 0x7b0d -#define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32F746_PH11_FUNC_LCD_R5 0x7b0f -#define STM32F746_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32F746_PH11_FUNC_ANALOG 0x7b11 - -#define STM32F746_PH12_FUNC_GPIO 0x7c00 -#define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05 -#define STM32F746_PH12_FUNC_FMC_D20 0x7c0d -#define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32F746_PH12_FUNC_LCD_R6 0x7c0f -#define STM32F746_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32F746_PH12_FUNC_ANALOG 0x7c11 - -#define STM32F746_PH13_FUNC_GPIO 0x7d00 -#define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32F746_PH13_FUNC_FMC_D21 0x7d0d -#define STM32F746_PH13_FUNC_LCD_G2 0x7d0f -#define STM32F746_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32F746_PH13_FUNC_ANALOG 0x7d11 - -#define STM32F746_PH14_FUNC_GPIO 0x7e00 -#define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32F746_PH14_FUNC_FMC_D22 0x7e0d -#define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32F746_PH14_FUNC_LCD_G3 0x7e0f -#define STM32F746_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32F746_PH14_FUNC_ANALOG 0x7e11 - -#define STM32F746_PH15_FUNC_GPIO 0x7f00 -#define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32F746_PH15_FUNC_FMC_D23 0x7f0d -#define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32F746_PH15_FUNC_LCD_G4 0x7f0f -#define STM32F746_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32F746_PH15_FUNC_ANALOG 0x7f11 - - -#define STM32F746_PI0_FUNC_GPIO 0x8000 -#define STM32F746_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32F746_PI0_FUNC_FMC_D24 0x800d -#define STM32F746_PI0_FUNC_DCMI_D13 0x800e -#define STM32F746_PI0_FUNC_LCD_G5 0x800f -#define STM32F746_PI0_FUNC_EVENTOUT 0x8010 -#define STM32F746_PI0_FUNC_ANALOG 0x8011 - -#define STM32F746_PI1_FUNC_GPIO 0x8100 -#define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104 -#define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32F746_PI1_FUNC_FMC_D25 0x810d -#define STM32F746_PI1_FUNC_DCMI_D8 0x810e -#define STM32F746_PI1_FUNC_LCD_G6 0x810f -#define STM32F746_PI1_FUNC_EVENTOUT 0x8110 -#define STM32F746_PI1_FUNC_ANALOG 0x8111 - -#define STM32F746_PI2_FUNC_GPIO 0x8200 -#define STM32F746_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32F746_PI2_FUNC_SPI2_MISO 0x8206 -#define STM32F746_PI2_FUNC_FMC_D26 0x820d -#define STM32F746_PI2_FUNC_DCMI_D9 0x820e -#define STM32F746_PI2_FUNC_LCD_G7 0x820f -#define STM32F746_PI2_FUNC_EVENTOUT 0x8210 -#define STM32F746_PI2_FUNC_ANALOG 0x8211 - -#define STM32F746_PI3_FUNC_GPIO 0x8300 -#define STM32F746_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 -#define STM32F746_PI3_FUNC_FMC_D27 0x830d -#define STM32F746_PI3_FUNC_DCMI_D10 0x830e -#define STM32F746_PI3_FUNC_EVENTOUT 0x8310 -#define STM32F746_PI3_FUNC_ANALOG 0x8311 - -#define STM32F746_PI4_FUNC_GPIO 0x8400 -#define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b -#define STM32F746_PI4_FUNC_FMC_NBL2 0x840d -#define STM32F746_PI4_FUNC_DCMI_D5 0x840e -#define STM32F746_PI4_FUNC_LCD_B4 0x840f -#define STM32F746_PI4_FUNC_EVENTOUT 0x8410 -#define STM32F746_PI4_FUNC_ANALOG 0x8411 - -#define STM32F746_PI5_FUNC_GPIO 0x8500 -#define STM32F746_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b -#define STM32F746_PI5_FUNC_FMC_NBL3 0x850d -#define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32F746_PI5_FUNC_LCD_B5 0x850f -#define STM32F746_PI5_FUNC_EVENTOUT 0x8510 -#define STM32F746_PI5_FUNC_ANALOG 0x8511 - -#define STM32F746_PI6_FUNC_GPIO 0x8600 -#define STM32F746_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b -#define STM32F746_PI6_FUNC_FMC_D28 0x860d -#define STM32F746_PI6_FUNC_DCMI_D6 0x860e -#define STM32F746_PI6_FUNC_LCD_B6 0x860f -#define STM32F746_PI6_FUNC_EVENTOUT 0x8610 -#define STM32F746_PI6_FUNC_ANALOG 0x8611 - -#define STM32F746_PI7_FUNC_GPIO 0x8700 -#define STM32F746_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b -#define STM32F746_PI7_FUNC_FMC_D29 0x870d -#define STM32F746_PI7_FUNC_DCMI_D7 0x870e -#define STM32F746_PI7_FUNC_LCD_B7 0x870f -#define STM32F746_PI7_FUNC_EVENTOUT 0x8710 -#define STM32F746_PI7_FUNC_ANALOG 0x8711 - -#define STM32F746_PI8_FUNC_GPIO 0x8800 -#define STM32F746_PI8_FUNC_EVENTOUT 0x8810 -#define STM32F746_PI8_FUNC_ANALOG 0x8811 - -#define STM32F746_PI9_FUNC_GPIO 0x8900 -#define STM32F746_PI9_FUNC_CAN1_RX 0x890a -#define STM32F746_PI9_FUNC_FMC_D30 0x890d -#define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32F746_PI9_FUNC_EVENTOUT 0x8910 -#define STM32F746_PI9_FUNC_ANALOG 0x8911 - -#define STM32F746_PI10_FUNC_GPIO 0x8a00 -#define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32F746_PI10_FUNC_FMC_D31 0x8a0d -#define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32F746_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32F746_PI10_FUNC_ANALOG 0x8a11 - -#define STM32F746_PI11_FUNC_GPIO 0x8b00 -#define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32F746_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32F746_PI11_FUNC_ANALOG 0x8b11 - -#define STM32F746_PI12_FUNC_GPIO 0x8c00 -#define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32F746_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32F746_PI12_FUNC_ANALOG 0x8c11 - -#define STM32F746_PI13_FUNC_GPIO 0x8d00 -#define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32F746_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32F746_PI13_FUNC_ANALOG 0x8d11 - -#define STM32F746_PI14_FUNC_GPIO 0x8e00 -#define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32F746_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32F746_PI14_FUNC_ANALOG 0x8e11 - -#define STM32F746_PI15_FUNC_GPIO 0x8f00 -#define STM32F746_PI15_FUNC_LCD_R0 0x8f0f -#define STM32F746_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32F746_PI15_FUNC_ANALOG 0x8f11 - - -#define STM32F746_PJ0_FUNC_GPIO 0x9000 -#define STM32F746_PJ0_FUNC_LCD_R1 0x900f -#define STM32F746_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32F746_PJ0_FUNC_ANALOG 0x9011 - -#define STM32F746_PJ1_FUNC_GPIO 0x9100 -#define STM32F746_PJ1_FUNC_LCD_R2 0x910f -#define STM32F746_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32F746_PJ1_FUNC_ANALOG 0x9111 - -#define STM32F746_PJ2_FUNC_GPIO 0x9200 -#define STM32F746_PJ2_FUNC_LCD_R3 0x920f -#define STM32F746_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32F746_PJ2_FUNC_ANALOG 0x9211 - -#define STM32F746_PJ3_FUNC_GPIO 0x9300 -#define STM32F746_PJ3_FUNC_LCD_R4 0x930f -#define STM32F746_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32F746_PJ3_FUNC_ANALOG 0x9311 - -#define STM32F746_PJ4_FUNC_GPIO 0x9400 -#define STM32F746_PJ4_FUNC_LCD_R5 0x940f -#define STM32F746_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32F746_PJ4_FUNC_ANALOG 0x9411 - -#define STM32F746_PJ5_FUNC_GPIO 0x9500 -#define STM32F746_PJ5_FUNC_LCD_R6 0x950f -#define STM32F746_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32F746_PJ5_FUNC_ANALOG 0x9511 - -#define STM32F746_PJ6_FUNC_GPIO 0x9600 -#define STM32F746_PJ6_FUNC_LCD_R7 0x960f -#define STM32F746_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32F746_PJ6_FUNC_ANALOG 0x9611 - -#define STM32F746_PJ7_FUNC_GPIO 0x9700 -#define STM32F746_PJ7_FUNC_LCD_G0 0x970f -#define STM32F746_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32F746_PJ7_FUNC_ANALOG 0x9711 - -#define STM32F746_PJ8_FUNC_GPIO 0x9800 -#define STM32F746_PJ8_FUNC_LCD_G1 0x980f -#define STM32F746_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32F746_PJ8_FUNC_ANALOG 0x9811 - -#define STM32F746_PJ9_FUNC_GPIO 0x9900 -#define STM32F746_PJ9_FUNC_LCD_G2 0x990f -#define STM32F746_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32F746_PJ9_FUNC_ANALOG 0x9911 - -#define STM32F746_PJ10_FUNC_GPIO 0x9a00 -#define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32F746_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32F746_PJ11_FUNC_GPIO 0x9b00 -#define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32F746_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32F746_PJ12_FUNC_GPIO 0x9c00 -#define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32F746_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32F746_PJ13_FUNC_GPIO 0x9d00 -#define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32F746_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32F746_PJ14_FUNC_GPIO 0x9e00 -#define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32F746_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32F746_PJ15_FUNC_GPIO 0x9f00 -#define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32F746_PJ15_FUNC_ANALOG 0x9f11 - - -#define STM32F746_PK0_FUNC_GPIO 0xa000 -#define STM32F746_PK0_FUNC_LCD_G5 0xa00f -#define STM32F746_PK0_FUNC_EVENTOUT 0xa010 -#define STM32F746_PK0_FUNC_ANALOG 0xa011 - -#define STM32F746_PK1_FUNC_GPIO 0xa100 -#define STM32F746_PK1_FUNC_LCD_G6 0xa10f -#define STM32F746_PK1_FUNC_EVENTOUT 0xa110 -#define STM32F746_PK1_FUNC_ANALOG 0xa111 - -#define STM32F746_PK2_FUNC_GPIO 0xa200 -#define STM32F746_PK2_FUNC_LCD_G7 0xa20f -#define STM32F746_PK2_FUNC_EVENTOUT 0xa210 -#define STM32F746_PK2_FUNC_ANALOG 0xa211 - -#define STM32F746_PK3_FUNC_GPIO 0xa300 -#define STM32F746_PK3_FUNC_LCD_B4 0xa30f -#define STM32F746_PK3_FUNC_EVENTOUT 0xa310 -#define STM32F746_PK3_FUNC_ANALOG 0xa311 - -#define STM32F746_PK4_FUNC_GPIO 0xa400 -#define STM32F746_PK4_FUNC_LCD_B5 0xa40f -#define STM32F746_PK4_FUNC_EVENTOUT 0xa410 -#define STM32F746_PK4_FUNC_ANALOG 0xa411 - -#define STM32F746_PK5_FUNC_GPIO 0xa500 -#define STM32F746_PK5_FUNC_LCD_B6 0xa50f -#define STM32F746_PK5_FUNC_EVENTOUT 0xa510 -#define STM32F746_PK5_FUNC_ANALOG 0xa511 - -#define STM32F746_PK6_FUNC_GPIO 0xa600 -#define STM32F746_PK6_FUNC_LCD_B7 0xa60f -#define STM32F746_PK6_FUNC_EVENTOUT 0xa610 -#define STM32F746_PK6_FUNC_ANALOG 0xa611 - -#define STM32F746_PK7_FUNC_GPIO 0xa700 -#define STM32F746_PK7_FUNC_LCD_DE 0xa70f -#define STM32F746_PK7_FUNC_EVENTOUT 0xa710 -#define STM32F746_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h deleted file mode 100644 index cb673b5e8e1e..000000000000 --- a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h +++ /dev/null @@ -1,1612 +0,0 @@ -#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H -#define _DT_BINDINGS_STM32H7_PINFUNC_H - -#define STM32H7_PA0_FUNC_GPIO 0x0 -#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 -#define STM32H7_PA0_FUNC_TIM5_CH1 0x3 -#define STM32H7_PA0_FUNC_TIM8_ETR 0x4 -#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5 -#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8 -#define STM32H7_PA0_FUNC_UART4_TX 0x9 -#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa -#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb -#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc -#define STM32H7_PA0_FUNC_EVENTOUT 0x10 -#define STM32H7_PA0_FUNC_ANALOG 0x11 - -#define STM32H7_PA1_FUNC_GPIO 0x100 -#define STM32H7_PA1_FUNC_TIM2_CH2 0x102 -#define STM32H7_PA1_FUNC_TIM5_CH2 0x103 -#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104 -#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105 -#define STM32H7_PA1_FUNC_USART2_RTS 0x108 -#define STM32H7_PA1_FUNC_UART4_RX 0x109 -#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a -#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b -#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c -#define STM32H7_PA1_FUNC_LCD_R2 0x10f -#define STM32H7_PA1_FUNC_EVENTOUT 0x110 -#define STM32H7_PA1_FUNC_ANALOG 0x111 - -#define STM32H7_PA2_FUNC_GPIO 0x200 -#define STM32H7_PA2_FUNC_TIM2_CH3 0x202 -#define STM32H7_PA2_FUNC_TIM5_CH3 0x203 -#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204 -#define STM32H7_PA2_FUNC_TIM15_CH1 0x205 -#define STM32H7_PA2_FUNC_USART2_TX 0x208 -#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209 -#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c -#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d -#define STM32H7_PA2_FUNC_LCD_R1 0x20f -#define STM32H7_PA2_FUNC_EVENTOUT 0x210 -#define STM32H7_PA2_FUNC_ANALOG 0x211 - -#define STM32H7_PA3_FUNC_GPIO 0x300 -#define STM32H7_PA3_FUNC_TIM2_CH4 0x302 -#define STM32H7_PA3_FUNC_TIM5_CH4 0x303 -#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304 -#define STM32H7_PA3_FUNC_TIM15_CH2 0x305 -#define STM32H7_PA3_FUNC_USART2_RX 0x308 -#define STM32H7_PA3_FUNC_LCD_B2 0x30a -#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b -#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c -#define STM32H7_PA3_FUNC_LCD_B5 0x30f -#define STM32H7_PA3_FUNC_EVENTOUT 0x310 -#define STM32H7_PA3_FUNC_ANALOG 0x311 - -#define STM32H7_PA4_FUNC_GPIO 0x400 -#define STM32H7_PA4_FUNC_TIM5_ETR 0x403 -#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 -#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 -#define STM32H7_PA4_FUNC_USART2_CK 0x408 -#define STM32H7_PA4_FUNC_SPI6_NSS 0x409 -#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d -#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e -#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f -#define STM32H7_PA4_FUNC_EVENTOUT 0x410 -#define STM32H7_PA4_FUNC_ANALOG 0x411 - -#define STM32H7_PA5_FUNC_GPIO 0x500 -#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 -#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504 -#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 -#define STM32H7_PA5_FUNC_SPI6_SCK 0x509 -#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b -#define STM32H7_PA5_FUNC_LCD_R4 0x50f -#define STM32H7_PA5_FUNC_EVENTOUT 0x510 -#define STM32H7_PA5_FUNC_ANALOG 0x511 - -#define STM32H7_PA6_FUNC_GPIO 0x600 -#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602 -#define STM32H7_PA6_FUNC_TIM3_CH1 0x603 -#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604 -#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606 -#define STM32H7_PA6_FUNC_SPI6_MISO 0x609 -#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a -#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b -#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c -#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d -#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e -#define STM32H7_PA6_FUNC_LCD_G2 0x60f -#define STM32H7_PA6_FUNC_EVENTOUT 0x610 -#define STM32H7_PA6_FUNC_ANALOG 0x611 - -#define STM32H7_PA7_FUNC_GPIO 0x700 -#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702 -#define STM32H7_PA7_FUNC_TIM3_CH2 0x703 -#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704 -#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706 -#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709 -#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a -#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c -#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d -#define STM32H7_PA7_FUNC_EVENTOUT 0x710 -#define STM32H7_PA7_FUNC_ANALOG 0x711 - -#define STM32H7_PA8_FUNC_GPIO 0x800 -#define STM32H7_PA8_FUNC_MCO1 0x801 -#define STM32H7_PA8_FUNC_TIM1_CH1 0x802 -#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803 -#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804 -#define STM32H7_PA8_FUNC_I2C3_SCL 0x805 -#define STM32H7_PA8_FUNC_USART1_CK 0x808 -#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b -#define STM32H7_PA8_FUNC_UART7_RX 0x80c -#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d -#define STM32H7_PA8_FUNC_LCD_B3 0x80e -#define STM32H7_PA8_FUNC_LCD_R6 0x80f -#define STM32H7_PA8_FUNC_EVENTOUT 0x810 -#define STM32H7_PA8_FUNC_ANALOG 0x811 - -#define STM32H7_PA9_FUNC_GPIO 0x900 -#define STM32H7_PA9_FUNC_TIM1_CH2 0x902 -#define STM32H7_PA9_FUNC_HRTIM_CHC1 0x903 -#define STM32H7_PA9_FUNC_LPUART1_TX 0x904 -#define STM32H7_PA9_FUNC_I2C3_SMBA 0x905 -#define STM32H7_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 -#define STM32H7_PA9_FUNC_USART1_TX 0x908 -#define STM32H7_PA9_FUNC_CAN1_RXFD 0x90a -#define STM32H7_PA9_FUNC_ETH_TX_ER 0x90c -#define STM32H7_PA9_FUNC_DCMI_D0 0x90e -#define STM32H7_PA9_FUNC_LCD_R5 0x90f -#define STM32H7_PA9_FUNC_EVENTOUT 0x910 -#define STM32H7_PA9_FUNC_ANALOG 0x911 - -#define STM32H7_PA10_FUNC_GPIO 0xa00 -#define STM32H7_PA10_FUNC_TIM1_CH3 0xa02 -#define STM32H7_PA10_FUNC_HRTIM_CHC2 0xa03 -#define STM32H7_PA10_FUNC_LPUART1_RX 0xa04 -#define STM32H7_PA10_FUNC_USART1_RX 0xa08 -#define STM32H7_PA10_FUNC_CAN1_TXFD 0xa0a -#define STM32H7_PA10_FUNC_OTG_FS_ID 0xa0b -#define STM32H7_PA10_FUNC_MDIOS_MDIO 0xa0c -#define STM32H7_PA10_FUNC_LCD_B4 0xa0d -#define STM32H7_PA10_FUNC_DCMI_D1 0xa0e -#define STM32H7_PA10_FUNC_LCD_B1 0xa0f -#define STM32H7_PA10_FUNC_EVENTOUT 0xa10 -#define STM32H7_PA10_FUNC_ANALOG 0xa11 - -#define STM32H7_PA11_FUNC_GPIO 0xb00 -#define STM32H7_PA11_FUNC_TIM1_CH4 0xb02 -#define STM32H7_PA11_FUNC_HRTIM_CHD1 0xb03 -#define STM32H7_PA11_FUNC_LPUART1_CTS 0xb04 -#define STM32H7_PA11_FUNC_SPI2_NSS_I2S2_WS 0xb06 -#define STM32H7_PA11_FUNC_UART4_RX 0xb07 -#define STM32H7_PA11_FUNC_USART1_CTS_NSS 0xb08 -#define STM32H7_PA11_FUNC_CAN1_RX 0xb0a -#define STM32H7_PA11_FUNC_OTG_FS_DM 0xb0b -#define STM32H7_PA11_FUNC_LCD_R4 0xb0f -#define STM32H7_PA11_FUNC_EVENTOUT 0xb10 -#define STM32H7_PA11_FUNC_ANALOG 0xb11 - -#define STM32H7_PA12_FUNC_GPIO 0xc00 -#define STM32H7_PA12_FUNC_TIM1_ETR 0xc02 -#define STM32H7_PA12_FUNC_HRTIM_CHD2 0xc03 -#define STM32H7_PA12_FUNC_LPUART1_RTS 0xc04 -#define STM32H7_PA12_FUNC_SPI2_SCK_I2S2_CK 0xc06 -#define STM32H7_PA12_FUNC_UART4_TX 0xc07 -#define STM32H7_PA12_FUNC_USART1_RTS 0xc08 -#define STM32H7_PA12_FUNC_SAI2_FS_B 0xc09 -#define STM32H7_PA12_FUNC_CAN1_TX 0xc0a -#define STM32H7_PA12_FUNC_OTG_FS_DP 0xc0b -#define STM32H7_PA12_FUNC_LCD_R5 0xc0f -#define STM32H7_PA12_FUNC_EVENTOUT 0xc10 -#define STM32H7_PA12_FUNC_ANALOG 0xc11 - -#define STM32H7_PA13_FUNC_GPIO 0xd00 -#define STM32H7_PA13_FUNC_JTMS_SWDIO 0xd01 -#define STM32H7_PA13_FUNC_EVENTOUT 0xd10 -#define STM32H7_PA13_FUNC_ANALOG 0xd11 - -#define STM32H7_PA14_FUNC_GPIO 0xe00 -#define STM32H7_PA14_FUNC_JTCK_SWCLK 0xe01 -#define STM32H7_PA14_FUNC_EVENTOUT 0xe10 -#define STM32H7_PA14_FUNC_ANALOG 0xe11 - -#define STM32H7_PA15_FUNC_GPIO 0xf00 -#define STM32H7_PA15_FUNC_JTDI 0xf01 -#define STM32H7_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 -#define STM32H7_PA15_FUNC_HRTIM_FLT1 0xf03 -#define STM32H7_PA15_FUNC_HDMI_CEC 0xf05 -#define STM32H7_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 -#define STM32H7_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 -#define STM32H7_PA15_FUNC_SPI6_NSS 0xf08 -#define STM32H7_PA15_FUNC_UART4_RTS 0xf09 -#define STM32H7_PA15_FUNC_UART7_TX 0xf0c -#define STM32H7_PA15_FUNC_DSI_TE 0xf0e -#define STM32H7_PA15_FUNC_EVENTOUT 0xf10 -#define STM32H7_PA15_FUNC_ANALOG 0xf11 - -#define STM32H7_PB0_FUNC_GPIO 0x1000 -#define STM32H7_PB0_FUNC_TIM1_CH2N 0x1002 -#define STM32H7_PB0_FUNC_TIM3_CH3 0x1003 -#define STM32H7_PB0_FUNC_TIM8_CH2N 0x1004 -#define STM32H7_PB0_FUNC_DFSDM_CKOUT 0x1007 -#define STM32H7_PB0_FUNC_UART4_CTS 0x1009 -#define STM32H7_PB0_FUNC_LCD_R3 0x100a -#define STM32H7_PB0_FUNC_OTG_HS_ULPI_D1 0x100b -#define STM32H7_PB0_FUNC_ETH_MII_RXD2 0x100c -#define STM32H7_PB0_FUNC_LCD_G1 0x100f -#define STM32H7_PB0_FUNC_EVENTOUT 0x1010 -#define STM32H7_PB0_FUNC_ANALOG 0x1011 - -#define STM32H7_PB1_FUNC_GPIO 0x1100 -#define STM32H7_PB1_FUNC_TIM1_CH3N 0x1102 -#define STM32H7_PB1_FUNC_TIM3_CH4 0x1103 -#define STM32H7_PB1_FUNC_TIM8_CH3N 0x1104 -#define STM32H7_PB1_FUNC_DFSDM_DATIN1 0x1107 -#define STM32H7_PB1_FUNC_LCD_R6 0x110a -#define STM32H7_PB1_FUNC_OTG_HS_ULPI_D2 0x110b -#define STM32H7_PB1_FUNC_ETH_MII_RXD3 0x110c -#define STM32H7_PB1_FUNC_LCD_G0 0x110f -#define STM32H7_PB1_FUNC_EVENTOUT 0x1110 -#define STM32H7_PB1_FUNC_ANALOG 0x1111 - -#define STM32H7_PB2_FUNC_GPIO 0x1200 -#define STM32H7_PB2_FUNC_SAI1_D1 0x1203 -#define STM32H7_PB2_FUNC_DFSDM_CKIN1 0x1205 -#define STM32H7_PB2_FUNC_SAI1_SD_A 0x1207 -#define STM32H7_PB2_FUNC_SPI3_MOSI_I2S3_SDO 0x1208 -#define STM32H7_PB2_FUNC_SAI4_SD_A 0x1209 -#define STM32H7_PB2_FUNC_QUADSPI_CLK 0x120a -#define STM32H7_PB2_FUNC_SAI4_D1 0x120b -#define STM32H7_PB2_FUNC_ETH_TX_ER 0x120c -#define STM32H7_PB2_FUNC_EVENTOUT 0x1210 -#define STM32H7_PB2_FUNC_ANALOG 0x1211 - -#define STM32H7_PB3_FUNC_GPIO 0x1300 -#define STM32H7_PB3_FUNC_JTDO_TRACESWO 0x1301 -#define STM32H7_PB3_FUNC_TIM2_CH2 0x1302 -#define STM32H7_PB3_FUNC_HRTIM_FLT4 0x1303 -#define STM32H7_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 -#define STM32H7_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 -#define STM32H7_PB3_FUNC_SPI6_SCK 0x1309 -#define STM32H7_PB3_FUNC_SDMMC2_D2 0x130a -#define STM32H7_PB3_FUNC_UART7_RX 0x130c -#define STM32H7_PB3_FUNC_EVENTOUT 0x1310 -#define STM32H7_PB3_FUNC_ANALOG 0x1311 - -#define STM32H7_PB4_FUNC_GPIO 0x1400 -#define STM32H7_PB4_FUNC_NJTRST 0x1401 -#define STM32H7_PB4_FUNC_TIM16_BKIN 0x1402 -#define STM32H7_PB4_FUNC_TIM3_CH1 0x1403 -#define STM32H7_PB4_FUNC_HRTIM_EEV6 0x1404 -#define STM32H7_PB4_FUNC_SPI1_MISO_I2S1_SDI 0x1406 -#define STM32H7_PB4_FUNC_SPI3_MISO_I2S3_SDI 0x1407 -#define STM32H7_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 -#define STM32H7_PB4_FUNC_SPI6_MISO 0x1409 -#define STM32H7_PB4_FUNC_SDMMC2_D3 0x140a -#define STM32H7_PB4_FUNC_UART7_TX 0x140c -#define STM32H7_PB4_FUNC_EVENTOUT 0x1410 -#define STM32H7_PB4_FUNC_ANALOG 0x1411 - -#define STM32H7_PB5_FUNC_GPIO 0x1500 -#define STM32H7_PB5_FUNC_TIM17_BKIN 0x1502 -#define STM32H7_PB5_FUNC_TIM3_CH2 0x1503 -#define STM32H7_PB5_FUNC_HRTIM_EEV7 0x1504 -#define STM32H7_PB5_FUNC_I2C1_SMBA 0x1505 -#define STM32H7_PB5_FUNC_SPI1_MOSI_I2S1_SDO 0x1506 -#define STM32H7_PB5_FUNC_I2C4_SMBA 0x1507 -#define STM32H7_PB5_FUNC_SPI3_MOSI_I2S3_SDO 0x1508 -#define STM32H7_PB5_FUNC_SPI6_MOSI 0x1509 -#define STM32H7_PB5_FUNC_CAN2_RX 0x150a -#define STM32H7_PB5_FUNC_OTG_HS_ULPI_D7 0x150b -#define STM32H7_PB5_FUNC_ETH_PPS_OUT 0x150c -#define STM32H7_PB5_FUNC_FMC_SDCKE1 0x150d -#define STM32H7_PB5_FUNC_DCMI_D10 0x150e -#define STM32H7_PB5_FUNC_UART5_RX 0x150f -#define STM32H7_PB5_FUNC_EVENTOUT 0x1510 -#define STM32H7_PB5_FUNC_ANALOG 0x1511 - -#define STM32H7_PB6_FUNC_GPIO 0x1600 -#define STM32H7_PB6_FUNC_TIM16_CH1N 0x1602 -#define STM32H7_PB6_FUNC_TIM4_CH1 0x1603 -#define STM32H7_PB6_FUNC_HRTIM_EEV8 0x1604 -#define STM32H7_PB6_FUNC_I2C1_SCL 0x1605 -#define STM32H7_PB6_FUNC_HDMI_CEC 0x1606 -#define STM32H7_PB6_FUNC_I2C4_SCL 0x1607 -#define STM32H7_PB6_FUNC_USART1_TX 0x1608 -#define STM32H7_PB6_FUNC_LPUART1_TX 0x1609 -#define STM32H7_PB6_FUNC_CAN2_TX 0x160a -#define STM32H7_PB6_FUNC_QUADSPI_BK1_NCS 0x160b -#define STM32H7_PB6_FUNC_DFSDM_DATIN5 0x160c -#define STM32H7_PB6_FUNC_FMC_SDNE1 0x160d -#define STM32H7_PB6_FUNC_DCMI_D5 0x160e -#define STM32H7_PB6_FUNC_UART5_TX 0x160f -#define STM32H7_PB6_FUNC_EVENTOUT 0x1610 -#define STM32H7_PB6_FUNC_ANALOG 0x1611 - -#define STM32H7_PB7_FUNC_GPIO 0x1700 -#define STM32H7_PB7_FUNC_TIM17_CH1N 0x1702 -#define STM32H7_PB7_FUNC_TIM4_CH2 0x1703 -#define STM32H7_PB7_FUNC_HRTIM_EEV9 0x1704 -#define STM32H7_PB7_FUNC_I2C1_SDA 0x1705 -#define STM32H7_PB7_FUNC_I2C4_SDA 0x1707 -#define STM32H7_PB7_FUNC_USART1_RX 0x1708 -#define STM32H7_PB7_FUNC_LPUART1_RX 0x1709 -#define STM32H7_PB7_FUNC_CAN2_TXFD 0x170a -#define STM32H7_PB7_FUNC_DFSDM_CKIN5 0x170c -#define STM32H7_PB7_FUNC_FMC_NL 0x170d -#define STM32H7_PB7_FUNC_DCMI_VSYNC 0x170e -#define STM32H7_PB7_FUNC_EVENTOUT 0x1710 -#define STM32H7_PB7_FUNC_ANALOG 0x1711 - -#define STM32H7_PB8_FUNC_GPIO 0x1800 -#define STM32H7_PB8_FUNC_TIM16_CH1 0x1802 -#define STM32H7_PB8_FUNC_TIM4_CH3 0x1803 -#define STM32H7_PB8_FUNC_DFSDM_CKIN7 0x1804 -#define STM32H7_PB8_FUNC_I2C1_SCL 0x1805 -#define STM32H7_PB8_FUNC_I2C4_SCL 0x1807 -#define STM32H7_PB8_FUNC_SDMMC1_CKIN 0x1808 -#define STM32H7_PB8_FUNC_UART4_RX 0x1809 -#define STM32H7_PB8_FUNC_CAN1_RX 0x180a -#define STM32H7_PB8_FUNC_SDMMC2_D4 0x180b -#define STM32H7_PB8_FUNC_ETH_MII_TXD3 0x180c -#define STM32H7_PB8_FUNC_SDMMC1_D4 0x180d -#define STM32H7_PB8_FUNC_DCMI_D6 0x180e -#define STM32H7_PB8_FUNC_LCD_B6 0x180f -#define STM32H7_PB8_FUNC_EVENTOUT 0x1810 -#define STM32H7_PB8_FUNC_ANALOG 0x1811 - -#define STM32H7_PB9_FUNC_GPIO 0x1900 -#define STM32H7_PB9_FUNC_TIM17_CH1 0x1902 -#define STM32H7_PB9_FUNC_TIM4_CH4 0x1903 -#define STM32H7_PB9_FUNC_DFSDM_DATIN7 0x1904 -#define STM32H7_PB9_FUNC_I2C1_SDA 0x1905 -#define STM32H7_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 -#define STM32H7_PB9_FUNC_I2C4_SDA 0x1907 -#define STM32H7_PB9_FUNC_SDMMC1_CDIR 0x1908 -#define STM32H7_PB9_FUNC_UART4_TX 0x1909 -#define STM32H7_PB9_FUNC_CAN1_TX 0x190a -#define STM32H7_PB9_FUNC_SDMMC2_D5 0x190b -#define STM32H7_PB9_FUNC_I2C4_SMBA 0x190c -#define STM32H7_PB9_FUNC_SDMMC1_D5 0x190d -#define STM32H7_PB9_FUNC_DCMI_D7 0x190e -#define STM32H7_PB9_FUNC_LCD_B7 0x190f -#define STM32H7_PB9_FUNC_EVENTOUT 0x1910 -#define STM32H7_PB9_FUNC_ANALOG 0x1911 - -#define STM32H7_PB10_FUNC_GPIO 0x1a00 -#define STM32H7_PB10_FUNC_TIM2_CH3 0x1a02 -#define STM32H7_PB10_FUNC_HRTIM_SCOUT 0x1a03 -#define STM32H7_PB10_FUNC_LPTIM2_IN1 0x1a04 -#define STM32H7_PB10_FUNC_I2C2_SCL 0x1a05 -#define STM32H7_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 -#define STM32H7_PB10_FUNC_DFSDM_DATIN7 0x1a07 -#define STM32H7_PB10_FUNC_USART3_TX 0x1a08 -#define STM32H7_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a -#define STM32H7_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b -#define STM32H7_PB10_FUNC_ETH_MII_RX_ER 0x1a0c -#define STM32H7_PB10_FUNC_LCD_G4 0x1a0f -#define STM32H7_PB10_FUNC_EVENTOUT 0x1a10 -#define STM32H7_PB10_FUNC_ANALOG 0x1a11 - -#define STM32H7_PB11_FUNC_GPIO 0x1b00 -#define STM32H7_PB11_FUNC_TIM2_CH4 0x1b02 -#define STM32H7_PB11_FUNC_HRTIM_SCIN 0x1b03 -#define STM32H7_PB11_FUNC_LPTIM2_ETR 0x1b04 -#define STM32H7_PB11_FUNC_I2C2_SDA 0x1b05 -#define STM32H7_PB11_FUNC_DFSDM_CKIN7 0x1b07 -#define STM32H7_PB11_FUNC_USART3_RX 0x1b08 -#define STM32H7_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b -#define STM32H7_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c -#define STM32H7_PB11_FUNC_DSI_TE 0x1b0e -#define STM32H7_PB11_FUNC_LCD_G5 0x1b0f -#define STM32H7_PB11_FUNC_EVENTOUT 0x1b10 -#define STM32H7_PB11_FUNC_ANALOG 0x1b11 - -#define STM32H7_PB12_FUNC_GPIO 0x1c00 -#define STM32H7_PB12_FUNC_TIM1_BKIN 0x1c02 -#define STM32H7_PB12_FUNC_I2C2_SMBA 0x1c05 -#define STM32H7_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 -#define STM32H7_PB12_FUNC_DFSDM_DATIN1 0x1c07 -#define STM32H7_PB12_FUNC_USART3_CK 0x1c08 -#define STM32H7_PB12_FUNC_CAN2_RX 0x1c0a -#define STM32H7_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b -#define STM32H7_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c -#define STM32H7_PB12_FUNC_OTG_HS_ID 0x1c0d -#define STM32H7_PB12_FUNC_TIM1_BKIN_COMP12 0x1c0e -#define STM32H7_PB12_FUNC_UART5_RX 0x1c0f -#define STM32H7_PB12_FUNC_EVENTOUT 0x1c10 -#define STM32H7_PB12_FUNC_ANALOG 0x1c11 - -#define STM32H7_PB13_FUNC_GPIO 0x1d00 -#define STM32H7_PB13_FUNC_TIM1_CH1N 0x1d02 -#define STM32H7_PB13_FUNC_LPTIM2_OUT 0x1d04 -#define STM32H7_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 -#define STM32H7_PB13_FUNC_DFSDM_CKIN1 0x1d07 -#define STM32H7_PB13_FUNC_USART3_CTS_NSS 0x1d08 -#define STM32H7_PB13_FUNC_CAN2_TX 0x1d0a -#define STM32H7_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b -#define STM32H7_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c -#define STM32H7_PB13_FUNC_UART5_TX 0x1d0f -#define STM32H7_PB13_FUNC_EVENTOUT 0x1d10 -#define STM32H7_PB13_FUNC_ANALOG 0x1d11 - -#define STM32H7_PB14_FUNC_GPIO 0x1e00 -#define STM32H7_PB14_FUNC_TIM1_CH2N 0x1e02 -#define STM32H7_PB14_FUNC_TIM8_CH2N 0x1e04 -#define STM32H7_PB14_FUNC_USART1_TX 0x1e05 -#define STM32H7_PB14_FUNC_SPI2_MISO_I2S2_SDI 0x1e06 -#define STM32H7_PB14_FUNC_DFSDM_DATIN2 0x1e07 -#define STM32H7_PB14_FUNC_USART3_RTS 0x1e08 -#define STM32H7_PB14_FUNC_UART4_RTS 0x1e09 -#define STM32H7_PB14_FUNC_SDMMC2_D0 0x1e0a -#define STM32H7_PB14_FUNC_OTG_HS_DM 0x1e0d -#define STM32H7_PB14_FUNC_EVENTOUT 0x1e10 -#define STM32H7_PB14_FUNC_ANALOG 0x1e11 - -#define STM32H7_PB15_FUNC_GPIO 0x1f00 -#define STM32H7_PB15_FUNC_RTC_REFIN 0x1f01 -#define STM32H7_PB15_FUNC_TIM1_CH3N 0x1f02 -#define STM32H7_PB15_FUNC_TIM8_CH3N 0x1f04 -#define STM32H7_PB15_FUNC_USART1_RX 0x1f05 -#define STM32H7_PB15_FUNC_SPI2_MOSI_I2S2_SDO 0x1f06 -#define STM32H7_PB15_FUNC_DFSDM_CKIN2 0x1f07 -#define STM32H7_PB15_FUNC_UART4_CTS 0x1f09 -#define STM32H7_PB15_FUNC_SDMMC2_D1 0x1f0a -#define STM32H7_PB15_FUNC_OTG_HS_DP 0x1f0d -#define STM32H7_PB15_FUNC_EVENTOUT 0x1f10 -#define STM32H7_PB15_FUNC_ANALOG 0x1f11 - -#define STM32H7_PC0_FUNC_GPIO 0x2000 -#define STM32H7_PC0_FUNC_DFSDM_CKIN0 0x2004 -#define STM32H7_PC0_FUNC_DFSDM_DATIN4 0x2007 -#define STM32H7_PC0_FUNC_SAI2_FS_B 0x2009 -#define STM32H7_PC0_FUNC_OTG_HS_ULPI_STP 0x200b -#define STM32H7_PC0_FUNC_FMC_SDNWE 0x200d -#define STM32H7_PC0_FUNC_LCD_R5 0x200f -#define STM32H7_PC0_FUNC_EVENTOUT 0x2010 -#define STM32H7_PC0_FUNC_ANALOG 0x2011 - -#define STM32H7_PC1_FUNC_GPIO 0x2100 -#define STM32H7_PC1_FUNC_TRACED0 0x2101 -#define STM32H7_PC1_FUNC_SAI1_D1 0x2103 -#define STM32H7_PC1_FUNC_DFSDM_DATIN0 0x2104 -#define STM32H7_PC1_FUNC_DFSDM_CKIN4 0x2105 -#define STM32H7_PC1_FUNC_SPI2_MOSI_I2S2_SDO 0x2106 -#define STM32H7_PC1_FUNC_SAI1_SD_A 0x2107 -#define STM32H7_PC1_FUNC_SAI4_SD_A 0x2109 -#define STM32H7_PC1_FUNC_SDMMC2_CK 0x210a -#define STM32H7_PC1_FUNC_SAI4_D1 0x210b -#define STM32H7_PC1_FUNC_ETH_MDC 0x210c -#define STM32H7_PC1_FUNC_MDIOS_MDC 0x210d -#define STM32H7_PC1_FUNC_EVENTOUT 0x2110 -#define STM32H7_PC1_FUNC_ANALOG 0x2111 - -#define STM32H7_PC2_FUNC_GPIO 0x2200 -#define STM32H7_PC2_FUNC_DFSDM_CKIN1 0x2204 -#define STM32H7_PC2_FUNC_SPI2_MISO_I2S2_SDI 0x2206 -#define STM32H7_PC2_FUNC_DFSDM_CKOUT 0x2207 -#define STM32H7_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b -#define STM32H7_PC2_FUNC_ETH_MII_TXD2 0x220c -#define STM32H7_PC2_FUNC_FMC_SDNE0 0x220d -#define STM32H7_PC2_FUNC_EVENTOUT 0x2210 -#define STM32H7_PC2_FUNC_ANALOG 0x2211 - -#define STM32H7_PC3_FUNC_GPIO 0x2300 -#define STM32H7_PC3_FUNC_DFSDM_DATIN1 0x2304 -#define STM32H7_PC3_FUNC_SPI2_MOSI_I2S2_SDO 0x2306 -#define STM32H7_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b -#define STM32H7_PC3_FUNC_ETH_MII_TX_CLK 0x230c -#define STM32H7_PC3_FUNC_FMC_SDCKE0 0x230d -#define STM32H7_PC3_FUNC_EVENTOUT 0x2310 -#define STM32H7_PC3_FUNC_ANALOG 0x2311 - -#define STM32H7_PC4_FUNC_GPIO 0x2400 -#define STM32H7_PC4_FUNC_DFSDM_CKIN2 0x2404 -#define STM32H7_PC4_FUNC_I2S1_MCK 0x2406 -#define STM32H7_PC4_FUNC_SPDIFRX_IN2 0x240a -#define STM32H7_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c -#define STM32H7_PC4_FUNC_FMC_SDNE0 0x240d -#define STM32H7_PC4_FUNC_EVENTOUT 0x2410 -#define STM32H7_PC4_FUNC_ANALOG 0x2411 - -#define STM32H7_PC5_FUNC_GPIO 0x2500 -#define STM32H7_PC5_FUNC_SAI1_D3 0x2503 -#define STM32H7_PC5_FUNC_DFSDM_DATIN2 0x2504 -#define STM32H7_PC5_FUNC_SPDIFRX_IN3 0x250a -#define STM32H7_PC5_FUNC_SAI4_D3 0x250b -#define STM32H7_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c -#define STM32H7_PC5_FUNC_FMC_SDCKE0 0x250d -#define STM32H7_PC5_FUNC_COMP_1_OUT 0x250e -#define STM32H7_PC5_FUNC_EVENTOUT 0x2510 -#define STM32H7_PC5_FUNC_ANALOG 0x2511 - -#define STM32H7_PC6_FUNC_GPIO 0x2600 -#define STM32H7_PC6_FUNC_HRTIM_CHA1 0x2602 -#define STM32H7_PC6_FUNC_TIM3_CH1 0x2603 -#define STM32H7_PC6_FUNC_TIM8_CH1 0x2604 -#define STM32H7_PC6_FUNC_DFSDM_CKIN3 0x2605 -#define STM32H7_PC6_FUNC_I2S2_MCK 0x2606 -#define STM32H7_PC6_FUNC_USART6_TX 0x2608 -#define STM32H7_PC6_FUNC_SDMMC1_D0DIR 0x2609 -#define STM32H7_PC6_FUNC_FMC_NWAIT 0x260a -#define STM32H7_PC6_FUNC_SDMMC2_D6 0x260b -#define STM32H7_PC6_FUNC_SDMMC1_D6 0x260d -#define STM32H7_PC6_FUNC_DCMI_D0 0x260e -#define STM32H7_PC6_FUNC_LCD_HSYNC 0x260f -#define STM32H7_PC6_FUNC_EVENTOUT 0x2610 -#define STM32H7_PC6_FUNC_ANALOG 0x2611 - -#define STM32H7_PC7_FUNC_GPIO 0x2700 -#define STM32H7_PC7_FUNC_TRGIO 0x2701 -#define STM32H7_PC7_FUNC_HRTIM_CHA2 0x2702 -#define STM32H7_PC7_FUNC_TIM3_CH2 0x2703 -#define STM32H7_PC7_FUNC_TIM8_CH2 0x2704 -#define STM32H7_PC7_FUNC_DFSDM_DATIN3 0x2705 -#define STM32H7_PC7_FUNC_I2S3_MCK 0x2707 -#define STM32H7_PC7_FUNC_USART6_RX 0x2708 -#define STM32H7_PC7_FUNC_SDMMC1_D123DIR 0x2709 -#define STM32H7_PC7_FUNC_FMC_NE1 0x270a -#define STM32H7_PC7_FUNC_SDMMC2_D7 0x270b -#define STM32H7_PC7_FUNC_SWPMI_TX 0x270c -#define STM32H7_PC7_FUNC_SDMMC1_D7 0x270d -#define STM32H7_PC7_FUNC_DCMI_D1 0x270e -#define STM32H7_PC7_FUNC_LCD_G6 0x270f -#define STM32H7_PC7_FUNC_EVENTOUT 0x2710 -#define STM32H7_PC7_FUNC_ANALOG 0x2711 - -#define STM32H7_PC8_FUNC_GPIO 0x2800 -#define STM32H7_PC8_FUNC_TRACED1 0x2801 -#define STM32H7_PC8_FUNC_HRTIM_CHB1 0x2802 -#define STM32H7_PC8_FUNC_TIM3_CH3 0x2803 -#define STM32H7_PC8_FUNC_TIM8_CH3 0x2804 -#define STM32H7_PC8_FUNC_USART6_CK 0x2808 -#define STM32H7_PC8_FUNC_UART5_RTS 0x2809 -#define STM32H7_PC8_FUNC_FMC_NE2_FMC_NCE 0x280a -#define STM32H7_PC8_FUNC_SWPMI_RX 0x280c -#define STM32H7_PC8_FUNC_SDMMC1_D0 0x280d -#define STM32H7_PC8_FUNC_DCMI_D2 0x280e -#define STM32H7_PC8_FUNC_EVENTOUT 0x2810 -#define STM32H7_PC8_FUNC_ANALOG 0x2811 - -#define STM32H7_PC9_FUNC_GPIO 0x2900 -#define STM32H7_PC9_FUNC_MCO2 0x2901 -#define STM32H7_PC9_FUNC_TIM3_CH4 0x2903 -#define STM32H7_PC9_FUNC_TIM8_CH4 0x2904 -#define STM32H7_PC9_FUNC_I2C3_SDA 0x2905 -#define STM32H7_PC9_FUNC_I2S_CKIN 0x2906 -#define STM32H7_PC9_FUNC_UART5_CTS 0x2909 -#define STM32H7_PC9_FUNC_QUADSPI_BK1_IO0 0x290a -#define STM32H7_PC9_FUNC_LCD_G3 0x290b -#define STM32H7_PC9_FUNC_SWPMI_SUSPEND 0x290c -#define STM32H7_PC9_FUNC_SDMMC1_D1 0x290d -#define STM32H7_PC9_FUNC_DCMI_D3 0x290e -#define STM32H7_PC9_FUNC_LCD_B2 0x290f -#define STM32H7_PC9_FUNC_EVENTOUT 0x2910 -#define STM32H7_PC9_FUNC_ANALOG 0x2911 - -#define STM32H7_PC10_FUNC_GPIO 0x2a00 -#define STM32H7_PC10_FUNC_HRTIM_EEV1 0x2a03 -#define STM32H7_PC10_FUNC_DFSDM_CKIN5 0x2a04 -#define STM32H7_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 -#define STM32H7_PC10_FUNC_USART3_TX 0x2a08 -#define STM32H7_PC10_FUNC_UART4_TX 0x2a09 -#define STM32H7_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a -#define STM32H7_PC10_FUNC_SDMMC1_D2 0x2a0d -#define STM32H7_PC10_FUNC_DCMI_D8 0x2a0e -#define STM32H7_PC10_FUNC_LCD_R2 0x2a0f -#define STM32H7_PC10_FUNC_EVENTOUT 0x2a10 -#define STM32H7_PC10_FUNC_ANALOG 0x2a11 - -#define STM32H7_PC11_FUNC_GPIO 0x2b00 -#define STM32H7_PC11_FUNC_HRTIM_FLT2 0x2b03 -#define STM32H7_PC11_FUNC_DFSDM_DATIN5 0x2b04 -#define STM32H7_PC11_FUNC_SPI3_MISO_I2S3_SDI 0x2b07 -#define STM32H7_PC11_FUNC_USART3_RX 0x2b08 -#define STM32H7_PC11_FUNC_UART4_RX 0x2b09 -#define STM32H7_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a -#define STM32H7_PC11_FUNC_SDMMC1_D3 0x2b0d -#define STM32H7_PC11_FUNC_DCMI_D4 0x2b0e -#define STM32H7_PC11_FUNC_EVENTOUT 0x2b10 -#define STM32H7_PC11_FUNC_ANALOG 0x2b11 - -#define STM32H7_PC12_FUNC_GPIO 0x2c00 -#define STM32H7_PC12_FUNC_TRACED3 0x2c01 -#define STM32H7_PC12_FUNC_HRTIM_EEV2 0x2c03 -#define STM32H7_PC12_FUNC_SPI3_MOSI_I2S3_SDO 0x2c07 -#define STM32H7_PC12_FUNC_USART3_CK 0x2c08 -#define STM32H7_PC12_FUNC_UART5_TX 0x2c09 -#define STM32H7_PC12_FUNC_SDMMC1_CK 0x2c0d -#define STM32H7_PC12_FUNC_DCMI_D9 0x2c0e -#define STM32H7_PC12_FUNC_EVENTOUT 0x2c10 -#define STM32H7_PC12_FUNC_ANALOG 0x2c11 - -#define STM32H7_PC13_FUNC_GPIO 0x2d00 -#define STM32H7_PC13_FUNC_EVENTOUT 0x2d10 -#define STM32H7_PC13_FUNC_ANALOG 0x2d11 - -#define STM32H7_PC14_FUNC_GPIO 0x2e00 -#define STM32H7_PC14_FUNC_EVENTOUT 0x2e10 -#define STM32H7_PC14_FUNC_ANALOG 0x2e11 - -#define STM32H7_PC15_FUNC_GPIO 0x2f00 -#define STM32H7_PC15_FUNC_EVENTOUT 0x2f10 -#define STM32H7_PC15_FUNC_ANALOG 0x2f11 - -#define STM32H7_PD0_FUNC_GPIO 0x3000 -#define STM32H7_PD0_FUNC_DFSDM_CKIN6 0x3004 -#define STM32H7_PD0_FUNC_SAI3_SCK_A 0x3007 -#define STM32H7_PD0_FUNC_UART4_RX 0x3009 -#define STM32H7_PD0_FUNC_CAN1_RX 0x300a -#define STM32H7_PD0_FUNC_FMC_D2_FMC_DA2 0x300d -#define STM32H7_PD0_FUNC_EVENTOUT 0x3010 -#define STM32H7_PD0_FUNC_ANALOG 0x3011 - -#define STM32H7_PD1_FUNC_GPIO 0x3100 -#define STM32H7_PD1_FUNC_DFSDM_DATIN6 0x3104 -#define STM32H7_PD1_FUNC_SAI3_SD_A 0x3107 -#define STM32H7_PD1_FUNC_UART4_TX 0x3109 -#define STM32H7_PD1_FUNC_CAN1_TX 0x310a -#define STM32H7_PD1_FUNC_FMC_D3_FMC_DA3 0x310d -#define STM32H7_PD1_FUNC_EVENTOUT 0x3110 -#define STM32H7_PD1_FUNC_ANALOG 0x3111 - -#define STM32H7_PD2_FUNC_GPIO 0x3200 -#define STM32H7_PD2_FUNC_TRACED2 0x3201 -#define STM32H7_PD2_FUNC_TIM3_ETR 0x3203 -#define STM32H7_PD2_FUNC_UART5_RX 0x3209 -#define STM32H7_PD2_FUNC_SDMMC1_CMD 0x320d -#define STM32H7_PD2_FUNC_DCMI_D11 0x320e -#define STM32H7_PD2_FUNC_EVENTOUT 0x3210 -#define STM32H7_PD2_FUNC_ANALOG 0x3211 - -#define STM32H7_PD3_FUNC_GPIO 0x3300 -#define STM32H7_PD3_FUNC_DFSDM_CKOUT 0x3304 -#define STM32H7_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 -#define STM32H7_PD3_FUNC_USART2_CTS_NSS 0x3308 -#define STM32H7_PD3_FUNC_FMC_CLK 0x330d -#define STM32H7_PD3_FUNC_DCMI_D5 0x330e -#define STM32H7_PD3_FUNC_LCD_G7 0x330f -#define STM32H7_PD3_FUNC_EVENTOUT 0x3310 -#define STM32H7_PD3_FUNC_ANALOG 0x3311 - -#define STM32H7_PD4_FUNC_GPIO 0x3400 -#define STM32H7_PD4_FUNC_HRTIM_FLT3 0x3403 -#define STM32H7_PD4_FUNC_SAI3_FS_A 0x3407 -#define STM32H7_PD4_FUNC_USART2_RTS 0x3408 -#define STM32H7_PD4_FUNC_CAN1_RXFD 0x340a -#define STM32H7_PD4_FUNC_FMC_NOE 0x340d -#define STM32H7_PD4_FUNC_EVENTOUT 0x3410 -#define STM32H7_PD4_FUNC_ANALOG 0x3411 - -#define STM32H7_PD5_FUNC_GPIO 0x3500 -#define STM32H7_PD5_FUNC_HRTIM_EEV3 0x3503 -#define STM32H7_PD5_FUNC_USART2_TX 0x3508 -#define STM32H7_PD5_FUNC_CAN1_TXFD 0x350a -#define STM32H7_PD5_FUNC_FMC_NWE 0x350d -#define STM32H7_PD5_FUNC_EVENTOUT 0x3510 -#define STM32H7_PD5_FUNC_ANALOG 0x3511 - -#define STM32H7_PD6_FUNC_GPIO 0x3600 -#define STM32H7_PD6_FUNC_SAI1_D1 0x3603 -#define STM32H7_PD6_FUNC_DFSDM_CKIN4 0x3604 -#define STM32H7_PD6_FUNC_DFSDM_DATIN1 0x3605 -#define STM32H7_PD6_FUNC_SPI3_MOSI_I2S3_SDO 0x3606 -#define STM32H7_PD6_FUNC_SAI1_SD_A 0x3607 -#define STM32H7_PD6_FUNC_USART2_RX 0x3608 -#define STM32H7_PD6_FUNC_SAI4_SD_A 0x3609 -#define STM32H7_PD6_FUNC_CAN2_RXFD 0x360a -#define STM32H7_PD6_FUNC_SAI4_D1 0x360b -#define STM32H7_PD6_FUNC_SDMMC2_CK 0x360c -#define STM32H7_PD6_FUNC_FMC_NWAIT 0x360d -#define STM32H7_PD6_FUNC_DCMI_D10 0x360e -#define STM32H7_PD6_FUNC_LCD_B2 0x360f -#define STM32H7_PD6_FUNC_EVENTOUT 0x3610 -#define STM32H7_PD6_FUNC_ANALOG 0x3611 - -#define STM32H7_PD7_FUNC_GPIO 0x3700 -#define STM32H7_PD7_FUNC_DFSDM_DATIN4 0x3704 -#define STM32H7_PD7_FUNC_SPI1_MOSI_I2S1_SDO 0x3706 -#define STM32H7_PD7_FUNC_DFSDM_CKIN1 0x3707 -#define STM32H7_PD7_FUNC_USART2_CK 0x3708 -#define STM32H7_PD7_FUNC_SPDIFRX_IN0 0x370a -#define STM32H7_PD7_FUNC_SDMMC2_CMD 0x370c -#define STM32H7_PD7_FUNC_FMC_NE1 0x370d -#define STM32H7_PD7_FUNC_EVENTOUT 0x3710 -#define STM32H7_PD7_FUNC_ANALOG 0x3711 - -#define STM32H7_PD8_FUNC_GPIO 0x3800 -#define STM32H7_PD8_FUNC_DFSDM_CKIN3 0x3804 -#define STM32H7_PD8_FUNC_SAI3_SCK_B 0x3807 -#define STM32H7_PD8_FUNC_USART3_TX 0x3808 -#define STM32H7_PD8_FUNC_SPDIFRX_IN1 0x380a -#define STM32H7_PD8_FUNC_FMC_D13_FMC_DA13 0x380d -#define STM32H7_PD8_FUNC_EVENTOUT 0x3810 -#define STM32H7_PD8_FUNC_ANALOG 0x3811 - -#define STM32H7_PD9_FUNC_GPIO 0x3900 -#define STM32H7_PD9_FUNC_DFSDM_DATIN3 0x3904 -#define STM32H7_PD9_FUNC_SAI3_SD_B 0x3907 -#define STM32H7_PD9_FUNC_USART3_RX 0x3908 -#define STM32H7_PD9_FUNC_CAN2_RXFD 0x390a -#define STM32H7_PD9_FUNC_FMC_D14_FMC_DA14 0x390d -#define STM32H7_PD9_FUNC_EVENTOUT 0x3910 -#define STM32H7_PD9_FUNC_ANALOG 0x3911 - -#define STM32H7_PD10_FUNC_GPIO 0x3a00 -#define STM32H7_PD10_FUNC_DFSDM_CKOUT 0x3a04 -#define STM32H7_PD10_FUNC_SAI3_FS_B 0x3a07 -#define STM32H7_PD10_FUNC_USART3_CK 0x3a08 -#define STM32H7_PD10_FUNC_CAN2_TXFD 0x3a0a -#define STM32H7_PD10_FUNC_FMC_D15_FMC_DA15 0x3a0d -#define STM32H7_PD10_FUNC_LCD_B3 0x3a0f -#define STM32H7_PD10_FUNC_EVENTOUT 0x3a10 -#define STM32H7_PD10_FUNC_ANALOG 0x3a11 - -#define STM32H7_PD11_FUNC_GPIO 0x3b00 -#define STM32H7_PD11_FUNC_LPTIM2_IN2 0x3b04 -#define STM32H7_PD11_FUNC_I2C4_SMBA 0x3b05 -#define STM32H7_PD11_FUNC_USART3_CTS_NSS 0x3b08 -#define STM32H7_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a -#define STM32H7_PD11_FUNC_SAI2_SD_A 0x3b0b -#define STM32H7_PD11_FUNC_FMC_A16 0x3b0d -#define STM32H7_PD11_FUNC_EVENTOUT 0x3b10 -#define STM32H7_PD11_FUNC_ANALOG 0x3b11 - -#define STM32H7_PD12_FUNC_GPIO 0x3c00 -#define STM32H7_PD12_FUNC_LPTIM1_IN1 0x3c02 -#define STM32H7_PD12_FUNC_TIM4_CH1 0x3c03 -#define STM32H7_PD12_FUNC_LPTIM2_IN1 0x3c04 -#define STM32H7_PD12_FUNC_I2C4_SCL 0x3c05 -#define STM32H7_PD12_FUNC_USART3_RTS 0x3c08 -#define STM32H7_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a -#define STM32H7_PD12_FUNC_SAI2_FS_A 0x3c0b -#define STM32H7_PD12_FUNC_FMC_A17 0x3c0d -#define STM32H7_PD12_FUNC_EVENTOUT 0x3c10 -#define STM32H7_PD12_FUNC_ANALOG 0x3c11 - -#define STM32H7_PD13_FUNC_GPIO 0x3d00 -#define STM32H7_PD13_FUNC_LPTIM1_OUT 0x3d02 -#define STM32H7_PD13_FUNC_TIM4_CH2 0x3d03 -#define STM32H7_PD13_FUNC_I2C4_SDA 0x3d05 -#define STM32H7_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a -#define STM32H7_PD13_FUNC_SAI2_SCK_A 0x3d0b -#define STM32H7_PD13_FUNC_FMC_A18 0x3d0d -#define STM32H7_PD13_FUNC_EVENTOUT 0x3d10 -#define STM32H7_PD13_FUNC_ANALOG 0x3d11 - -#define STM32H7_PD14_FUNC_GPIO 0x3e00 -#define STM32H7_PD14_FUNC_TIM4_CH3 0x3e03 -#define STM32H7_PD14_FUNC_SAI3_MCLK_B 0x3e07 -#define STM32H7_PD14_FUNC_UART8_CTS 0x3e09 -#define STM32H7_PD14_FUNC_FMC_D0_FMC_DA0 0x3e0d -#define STM32H7_PD14_FUNC_EVENTOUT 0x3e10 -#define STM32H7_PD14_FUNC_ANALOG 0x3e11 - -#define STM32H7_PD15_FUNC_GPIO 0x3f00 -#define STM32H7_PD15_FUNC_TIM4_CH4 0x3f03 -#define STM32H7_PD15_FUNC_SAI3_MCLK_A 0x3f07 -#define STM32H7_PD15_FUNC_UART8_RTS 0x3f09 -#define STM32H7_PD15_FUNC_FMC_D1_FMC_DA1 0x3f0d -#define STM32H7_PD15_FUNC_EVENTOUT 0x3f10 -#define STM32H7_PD15_FUNC_ANALOG 0x3f11 - -#define STM32H7_PE0_FUNC_GPIO 0x4000 -#define STM32H7_PE0_FUNC_LPTIM1_ETR 0x4002 -#define STM32H7_PE0_FUNC_TIM4_ETR 0x4003 -#define STM32H7_PE0_FUNC_HRTIM_SCIN 0x4004 -#define STM32H7_PE0_FUNC_LPTIM2_ETR 0x4005 -#define STM32H7_PE0_FUNC_UART8_RX 0x4009 -#define STM32H7_PE0_FUNC_CAN1_RXFD 0x400a -#define STM32H7_PE0_FUNC_SAI2_MCK_A 0x400b -#define STM32H7_PE0_FUNC_FMC_NBL0 0x400d -#define STM32H7_PE0_FUNC_DCMI_D2 0x400e -#define STM32H7_PE0_FUNC_EVENTOUT 0x4010 -#define STM32H7_PE0_FUNC_ANALOG 0x4011 - -#define STM32H7_PE1_FUNC_GPIO 0x4100 -#define STM32H7_PE1_FUNC_LPTIM1_IN2 0x4102 -#define STM32H7_PE1_FUNC_HRTIM_SCOUT 0x4104 -#define STM32H7_PE1_FUNC_UART8_TX 0x4109 -#define STM32H7_PE1_FUNC_CAN1_TXFD 0x410a -#define STM32H7_PE1_FUNC_FMC_NBL1 0x410d -#define STM32H7_PE1_FUNC_DCMI_D3 0x410e -#define STM32H7_PE1_FUNC_EVENTOUT 0x4110 -#define STM32H7_PE1_FUNC_ANALOG 0x4111 - -#define STM32H7_PE2_FUNC_GPIO 0x4200 -#define STM32H7_PE2_FUNC_TRACECLK 0x4201 -#define STM32H7_PE2_FUNC_SAI1_CK1 0x4203 -#define STM32H7_PE2_FUNC_SPI4_SCK 0x4206 -#define STM32H7_PE2_FUNC_SAI1_MCLK_A 0x4207 -#define STM32H7_PE2_FUNC_SAI4_MCLK_A 0x4209 -#define STM32H7_PE2_FUNC_QUADSPI_BK1_IO2 0x420a -#define STM32H7_PE2_FUNC_SAI4_CK1 0x420b -#define STM32H7_PE2_FUNC_ETH_MII_TXD3 0x420c -#define STM32H7_PE2_FUNC_FMC_A23 0x420d -#define STM32H7_PE2_FUNC_EVENTOUT 0x4210 -#define STM32H7_PE2_FUNC_ANALOG 0x4211 - -#define STM32H7_PE3_FUNC_GPIO 0x4300 -#define STM32H7_PE3_FUNC_TRACED0 0x4301 -#define STM32H7_PE3_FUNC_TIM15_BKIN 0x4305 -#define STM32H7_PE3_FUNC_SAI1_SD_B 0x4307 -#define STM32H7_PE3_FUNC_SAI4_SD_B 0x4309 -#define STM32H7_PE3_FUNC_FMC_A19 0x430d -#define STM32H7_PE3_FUNC_EVENTOUT 0x4310 -#define STM32H7_PE3_FUNC_ANALOG 0x4311 - -#define STM32H7_PE4_FUNC_GPIO 0x4400 -#define STM32H7_PE4_FUNC_TRACED1 0x4401 -#define STM32H7_PE4_FUNC_SAI1_D2 0x4403 -#define STM32H7_PE4_FUNC_DFSDM_DATIN3 0x4404 -#define STM32H7_PE4_FUNC_TIM15_CH1N 0x4405 -#define STM32H7_PE4_FUNC_SPI4_NSS 0x4406 -#define STM32H7_PE4_FUNC_SAI1_FS_A 0x4407 -#define STM32H7_PE4_FUNC_SAI4_FS_A 0x4409 -#define STM32H7_PE4_FUNC_SAI4_D2 0x440b -#define STM32H7_PE4_FUNC_FMC_A20 0x440d -#define STM32H7_PE4_FUNC_DCMI_D4 0x440e -#define STM32H7_PE4_FUNC_LCD_B0 0x440f -#define STM32H7_PE4_FUNC_EVENTOUT 0x4410 -#define STM32H7_PE4_FUNC_ANALOG 0x4411 - -#define STM32H7_PE5_FUNC_GPIO 0x4500 -#define STM32H7_PE5_FUNC_TRACED2 0x4501 -#define STM32H7_PE5_FUNC_SAI1_CK2 0x4503 -#define STM32H7_PE5_FUNC_DFSDM_CKIN3 0x4504 -#define STM32H7_PE5_FUNC_TIM15_CH1 0x4505 -#define STM32H7_PE5_FUNC_SPI4_MISO 0x4506 -#define STM32H7_PE5_FUNC_SAI1_SCK_A 0x4507 -#define STM32H7_PE5_FUNC_SAI4_SCK_A 0x4509 -#define STM32H7_PE5_FUNC_SAI4_CK2 0x450b -#define STM32H7_PE5_FUNC_FMC_A21 0x450d -#define STM32H7_PE5_FUNC_DCMI_D6 0x450e -#define STM32H7_PE5_FUNC_LCD_G0 0x450f -#define STM32H7_PE5_FUNC_EVENTOUT 0x4510 -#define STM32H7_PE5_FUNC_ANALOG 0x4511 - -#define STM32H7_PE6_FUNC_GPIO 0x4600 -#define STM32H7_PE6_FUNC_TRACED3 0x4601 -#define STM32H7_PE6_FUNC_TIM1_BKIN2 0x4602 -#define STM32H7_PE6_FUNC_SAI1_D1 0x4603 -#define STM32H7_PE6_FUNC_TIM15_CH2 0x4605 -#define STM32H7_PE6_FUNC_SPI4_MOSI 0x4606 -#define STM32H7_PE6_FUNC_SAI1_SD_A 0x4607 -#define STM32H7_PE6_FUNC_SAI4_SD_A 0x4609 -#define STM32H7_PE6_FUNC_SAI4_D1 0x460a -#define STM32H7_PE6_FUNC_SAI2_MCK_B 0x460b -#define STM32H7_PE6_FUNC_TIM1_BKIN2_COMP12 0x460c -#define STM32H7_PE6_FUNC_FMC_A22 0x460d -#define STM32H7_PE6_FUNC_DCMI_D7 0x460e -#define STM32H7_PE6_FUNC_LCD_G1 0x460f -#define STM32H7_PE6_FUNC_EVENTOUT 0x4610 -#define STM32H7_PE6_FUNC_ANALOG 0x4611 - -#define STM32H7_PE7_FUNC_GPIO 0x4700 -#define STM32H7_PE7_FUNC_TIM1_ETR 0x4702 -#define STM32H7_PE7_FUNC_DFSDM_DATIN2 0x4704 -#define STM32H7_PE7_FUNC_UART7_RX 0x4708 -#define STM32H7_PE7_FUNC_QUADSPI_BK2_IO0 0x470b -#define STM32H7_PE7_FUNC_FMC_D4_FMC_DA4 0x470d -#define STM32H7_PE7_FUNC_EVENTOUT 0x4710 -#define STM32H7_PE7_FUNC_ANALOG 0x4711 - -#define STM32H7_PE8_FUNC_GPIO 0x4800 -#define STM32H7_PE8_FUNC_TIM1_CH1N 0x4802 -#define STM32H7_PE8_FUNC_DFSDM_CKIN2 0x4804 -#define STM32H7_PE8_FUNC_UART7_TX 0x4808 -#define STM32H7_PE8_FUNC_QUADSPI_BK2_IO1 0x480b -#define STM32H7_PE8_FUNC_FMC_D5_FMC_DA5 0x480d -#define STM32H7_PE8_FUNC_COMP_2_OUT 0x480e -#define STM32H7_PE8_FUNC_EVENTOUT 0x4810 -#define STM32H7_PE8_FUNC_ANALOG 0x4811 - -#define STM32H7_PE9_FUNC_GPIO 0x4900 -#define STM32H7_PE9_FUNC_TIM1_CH1 0x4902 -#define STM32H7_PE9_FUNC_DFSDM_CKOUT 0x4904 -#define STM32H7_PE9_FUNC_UART7_RTS 0x4908 -#define STM32H7_PE9_FUNC_QUADSPI_BK2_IO2 0x490b -#define STM32H7_PE9_FUNC_FMC_D6_FMC_DA6 0x490d -#define STM32H7_PE9_FUNC_EVENTOUT 0x4910 -#define STM32H7_PE9_FUNC_ANALOG 0x4911 - -#define STM32H7_PE10_FUNC_GPIO 0x4a00 -#define STM32H7_PE10_FUNC_TIM1_CH2N 0x4a02 -#define STM32H7_PE10_FUNC_DFSDM_DATIN4 0x4a04 -#define STM32H7_PE10_FUNC_UART7_CTS 0x4a08 -#define STM32H7_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b -#define STM32H7_PE10_FUNC_FMC_D7_FMC_DA7 0x4a0d -#define STM32H7_PE10_FUNC_EVENTOUT 0x4a10 -#define STM32H7_PE10_FUNC_ANALOG 0x4a11 - -#define STM32H7_PE11_FUNC_GPIO 0x4b00 -#define STM32H7_PE11_FUNC_TIM1_CH2 0x4b02 -#define STM32H7_PE11_FUNC_DFSDM_CKIN4 0x4b04 -#define STM32H7_PE11_FUNC_SPI4_NSS 0x4b06 -#define STM32H7_PE11_FUNC_SAI2_SD_B 0x4b0b -#define STM32H7_PE11_FUNC_FMC_D8_FMC_DA8 0x4b0d -#define STM32H7_PE11_FUNC_LCD_G3 0x4b0f -#define STM32H7_PE11_FUNC_EVENTOUT 0x4b10 -#define STM32H7_PE11_FUNC_ANALOG 0x4b11 - -#define STM32H7_PE12_FUNC_GPIO 0x4c00 -#define STM32H7_PE12_FUNC_TIM1_CH3N 0x4c02 -#define STM32H7_PE12_FUNC_DFSDM_DATIN5 0x4c04 -#define STM32H7_PE12_FUNC_SPI4_SCK 0x4c06 -#define STM32H7_PE12_FUNC_SAI2_SCK_B 0x4c0b -#define STM32H7_PE12_FUNC_FMC_D9_FMC_DA9 0x4c0d -#define STM32H7_PE12_FUNC_COMP_1_OUT 0x4c0e -#define STM32H7_PE12_FUNC_LCD_B4 0x4c0f -#define STM32H7_PE12_FUNC_EVENTOUT 0x4c10 -#define STM32H7_PE12_FUNC_ANALOG 0x4c11 - -#define STM32H7_PE13_FUNC_GPIO 0x4d00 -#define STM32H7_PE13_FUNC_TIM1_CH3 0x4d02 -#define STM32H7_PE13_FUNC_DFSDM_CKIN5 0x4d04 -#define STM32H7_PE13_FUNC_SPI4_MISO 0x4d06 -#define STM32H7_PE13_FUNC_SAI2_FS_B 0x4d0b -#define STM32H7_PE13_FUNC_FMC_D10_FMC_DA10 0x4d0d -#define STM32H7_PE13_FUNC_COMP_2_OUT 0x4d0e -#define STM32H7_PE13_FUNC_LCD_DE 0x4d0f -#define STM32H7_PE13_FUNC_EVENTOUT 0x4d10 -#define STM32H7_PE13_FUNC_ANALOG 0x4d11 - -#define STM32H7_PE14_FUNC_GPIO 0x4e00 -#define STM32H7_PE14_FUNC_TIM1_CH4 0x4e02 -#define STM32H7_PE14_FUNC_SPI4_MOSI 0x4e06 -#define STM32H7_PE14_FUNC_SAI2_MCK_B 0x4e0b -#define STM32H7_PE14_FUNC_FMC_D11_FMC_DA11 0x4e0d -#define STM32H7_PE14_FUNC_LCD_CLK 0x4e0f -#define STM32H7_PE14_FUNC_EVENTOUT 0x4e10 -#define STM32H7_PE14_FUNC_ANALOG 0x4e11 - -#define STM32H7_PE15_FUNC_GPIO 0x4f00 -#define STM32H7_PE15_FUNC_TIM1_BKIN 0x4f02 -#define STM32H7_PE15_FUNC_HDMI__TIM1_BKIN 0x4f06 -#define STM32H7_PE15_FUNC_FMC_D12_FMC_DA12 0x4f0d -#define STM32H7_PE15_FUNC_TIM1_BKIN_COMP12 0x4f0e -#define STM32H7_PE15_FUNC_LCD_R7 0x4f0f -#define STM32H7_PE15_FUNC_EVENTOUT 0x4f10 -#define STM32H7_PE15_FUNC_ANALOG 0x4f11 - -#define STM32H7_PF0_FUNC_GPIO 0x5000 -#define STM32H7_PF0_FUNC_I2C2_SDA 0x5005 -#define STM32H7_PF0_FUNC_FMC_A0 0x500d -#define STM32H7_PF0_FUNC_EVENTOUT 0x5010 -#define STM32H7_PF0_FUNC_ANALOG 0x5011 - -#define STM32H7_PF1_FUNC_GPIO 0x5100 -#define STM32H7_PF1_FUNC_I2C2_SCL 0x5105 -#define STM32H7_PF1_FUNC_FMC_A1 0x510d -#define STM32H7_PF1_FUNC_EVENTOUT 0x5110 -#define STM32H7_PF1_FUNC_ANALOG 0x5111 - -#define STM32H7_PF2_FUNC_GPIO 0x5200 -#define STM32H7_PF2_FUNC_I2C2_SMBA 0x5205 -#define STM32H7_PF2_FUNC_FMC_A2 0x520d -#define STM32H7_PF2_FUNC_EVENTOUT 0x5210 -#define STM32H7_PF2_FUNC_ANALOG 0x5211 - -#define STM32H7_PF3_FUNC_GPIO 0x5300 -#define STM32H7_PF3_FUNC_FMC_A3 0x530d -#define STM32H7_PF3_FUNC_EVENTOUT 0x5310 -#define STM32H7_PF3_FUNC_ANALOG 0x5311 - -#define STM32H7_PF4_FUNC_GPIO 0x5400 -#define STM32H7_PF4_FUNC_FMC_A4 0x540d -#define STM32H7_PF4_FUNC_EVENTOUT 0x5410 -#define STM32H7_PF4_FUNC_ANALOG 0x5411 - -#define STM32H7_PF5_FUNC_GPIO 0x5500 -#define STM32H7_PF5_FUNC_FMC_A5 0x550d -#define STM32H7_PF5_FUNC_EVENTOUT 0x5510 -#define STM32H7_PF5_FUNC_ANALOG 0x5511 - -#define STM32H7_PF6_FUNC_GPIO 0x5600 -#define STM32H7_PF6_FUNC_TIM16_CH1 0x5602 -#define STM32H7_PF6_FUNC_SPI5_NSS 0x5606 -#define STM32H7_PF6_FUNC_SAI1_SD_B 0x5607 -#define STM32H7_PF6_FUNC_UART7_RX 0x5608 -#define STM32H7_PF6_FUNC_SAI4_SD_B 0x5609 -#define STM32H7_PF6_FUNC_QUADSPI_BK1_IO3 0x560a -#define STM32H7_PF6_FUNC_EVENTOUT 0x5610 -#define STM32H7_PF6_FUNC_ANALOG 0x5611 - -#define STM32H7_PF7_FUNC_GPIO 0x5700 -#define STM32H7_PF7_FUNC_TIM17_CH1 0x5702 -#define STM32H7_PF7_FUNC_SPI5_SCK 0x5706 -#define STM32H7_PF7_FUNC_SAI1_MCLK_B 0x5707 -#define STM32H7_PF7_FUNC_UART7_TX 0x5708 -#define STM32H7_PF7_FUNC_SAI4_MCLK_B 0x5709 -#define STM32H7_PF7_FUNC_QUADSPI_BK1_IO2 0x570a -#define STM32H7_PF7_FUNC_EVENTOUT 0x5710 -#define STM32H7_PF7_FUNC_ANALOG 0x5711 - -#define STM32H7_PF8_FUNC_GPIO 0x5800 -#define STM32H7_PF8_FUNC_TIM16_CH1N 0x5802 -#define STM32H7_PF8_FUNC_SPI5_MISO 0x5806 -#define STM32H7_PF8_FUNC_SAI1_SCK_B 0x5807 -#define STM32H7_PF8_FUNC_UART7_RTS 0x5808 -#define STM32H7_PF8_FUNC_SAI4_SCK_B 0x5809 -#define STM32H7_PF8_FUNC_TIM13_CH1 0x580a -#define STM32H7_PF8_FUNC_QUADSPI_BK1_IO0 0x580b -#define STM32H7_PF8_FUNC_EVENTOUT 0x5810 -#define STM32H7_PF8_FUNC_ANALOG 0x5811 - -#define STM32H7_PF9_FUNC_GPIO 0x5900 -#define STM32H7_PF9_FUNC_TIM17_CH1N 0x5902 -#define STM32H7_PF9_FUNC_SPI5_MOSI 0x5906 -#define STM32H7_PF9_FUNC_SAI1_FS_B 0x5907 -#define STM32H7_PF9_FUNC_UART7_CTS 0x5908 -#define STM32H7_PF9_FUNC_SAI4_FS_B 0x5909 -#define STM32H7_PF9_FUNC_TIM14_CH1 0x590a -#define STM32H7_PF9_FUNC_QUADSPI_BK1_IO1 0x590b -#define STM32H7_PF9_FUNC_EVENTOUT 0x5910 -#define STM32H7_PF9_FUNC_ANALOG 0x5911 - -#define STM32H7_PF10_FUNC_GPIO 0x5a00 -#define STM32H7_PF10_FUNC_TIM16_BKIN 0x5a02 -#define STM32H7_PF10_FUNC_SAI1_D3 0x5a03 -#define STM32H7_PF10_FUNC_QUADSPI_CLK 0x5a0a -#define STM32H7_PF10_FUNC_SAI4_D3 0x5a0b -#define STM32H7_PF10_FUNC_DCMI_D11 0x5a0e -#define STM32H7_PF10_FUNC_LCD_DE 0x5a0f -#define STM32H7_PF10_FUNC_EVENTOUT 0x5a10 -#define STM32H7_PF10_FUNC_ANALOG 0x5a11 - -#define STM32H7_PF11_FUNC_GPIO 0x5b00 -#define STM32H7_PF11_FUNC_SPI5_MOSI 0x5b06 -#define STM32H7_PF11_FUNC_SAI2_SD_B 0x5b0b -#define STM32H7_PF11_FUNC_FMC_SDNRAS 0x5b0d -#define STM32H7_PF11_FUNC_DCMI_D12 0x5b0e -#define STM32H7_PF11_FUNC_EVENTOUT 0x5b10 -#define STM32H7_PF11_FUNC_ANALOG 0x5b11 - -#define STM32H7_PF12_FUNC_GPIO 0x5c00 -#define STM32H7_PF12_FUNC_FMC_A6 0x5c0d -#define STM32H7_PF12_FUNC_EVENTOUT 0x5c10 -#define STM32H7_PF12_FUNC_ANALOG 0x5c11 - -#define STM32H7_PF13_FUNC_GPIO 0x5d00 -#define STM32H7_PF13_FUNC_DFSDM_DATIN6 0x5d04 -#define STM32H7_PF13_FUNC_I2C4_SMBA 0x5d05 -#define STM32H7_PF13_FUNC_FMC_A7 0x5d0d -#define STM32H7_PF13_FUNC_EVENTOUT 0x5d10 -#define STM32H7_PF13_FUNC_ANALOG 0x5d11 - -#define STM32H7_PF14_FUNC_GPIO 0x5e00 -#define STM32H7_PF14_FUNC_DFSDM_CKIN6 0x5e04 -#define STM32H7_PF14_FUNC_I2C4_SCL 0x5e05 -#define STM32H7_PF14_FUNC_FMC_A8 0x5e0d -#define STM32H7_PF14_FUNC_EVENTOUT 0x5e10 -#define STM32H7_PF14_FUNC_ANALOG 0x5e11 - -#define STM32H7_PF15_FUNC_GPIO 0x5f00 -#define STM32H7_PF15_FUNC_I2C4_SDA 0x5f05 -#define STM32H7_PF15_FUNC_FMC_A9 0x5f0d -#define STM32H7_PF15_FUNC_EVENTOUT 0x5f10 -#define STM32H7_PF15_FUNC_ANALOG 0x5f11 - -#define STM32H7_PG0_FUNC_GPIO 0x6000 -#define STM32H7_PG0_FUNC_FMC_A10 0x600d -#define STM32H7_PG0_FUNC_EVENTOUT 0x6010 -#define STM32H7_PG0_FUNC_ANALOG 0x6011 - -#define STM32H7_PG1_FUNC_GPIO 0x6100 -#define STM32H7_PG1_FUNC_FMC_A11 0x610d -#define STM32H7_PG1_FUNC_EVENTOUT 0x6110 -#define STM32H7_PG1_FUNC_ANALOG 0x6111 - -#define STM32H7_PG2_FUNC_GPIO 0x6200 -#define STM32H7_PG2_FUNC_TIM8_BKIN 0x6204 -#define STM32H7_PG2_FUNC_TIM8_BKIN_COMP12 0x620c -#define STM32H7_PG2_FUNC_FMC_A12 0x620d -#define STM32H7_PG2_FUNC_EVENTOUT 0x6210 -#define STM32H7_PG2_FUNC_ANALOG 0x6211 - -#define STM32H7_PG3_FUNC_GPIO 0x6300 -#define STM32H7_PG3_FUNC_TIM8_BKIN2 0x6304 -#define STM32H7_PG3_FUNC_TIM8_BKIN2_COMP12 0x630c -#define STM32H7_PG3_FUNC_FMC_A13 0x630d -#define STM32H7_PG3_FUNC_EVENTOUT 0x6310 -#define STM32H7_PG3_FUNC_ANALOG 0x6311 - -#define STM32H7_PG4_FUNC_GPIO 0x6400 -#define STM32H7_PG4_FUNC_TIM1_BKIN2 0x6402 -#define STM32H7_PG4_FUNC_TIM1_BKIN2_COMP12 0x640c -#define STM32H7_PG4_FUNC_FMC_A14_FMC_BA0 0x640d -#define STM32H7_PG4_FUNC_EVENTOUT 0x6410 -#define STM32H7_PG4_FUNC_ANALOG 0x6411 - -#define STM32H7_PG5_FUNC_GPIO 0x6500 -#define STM32H7_PG5_FUNC_TIM1_ETR 0x6502 -#define STM32H7_PG5_FUNC_FMC_A15_FMC_BA1 0x650d -#define STM32H7_PG5_FUNC_EVENTOUT 0x6510 -#define STM32H7_PG5_FUNC_ANALOG 0x6511 - -#define STM32H7_PG6_FUNC_GPIO 0x6600 -#define STM32H7_PG6_FUNC_TIM17_BKIN 0x6602 -#define STM32H7_PG6_FUNC_HRTIM_CHE1 0x6603 -#define STM32H7_PG6_FUNC_QUADSPI_BK1_NCS 0x660b -#define STM32H7_PG6_FUNC_FMC_NE3 0x660d -#define STM32H7_PG6_FUNC_DCMI_D12 0x660e -#define STM32H7_PG6_FUNC_LCD_R7 0x660f -#define STM32H7_PG6_FUNC_EVENTOUT 0x6610 -#define STM32H7_PG6_FUNC_ANALOG 0x6611 - -#define STM32H7_PG7_FUNC_GPIO 0x6700 -#define STM32H7_PG7_FUNC_HRTIM_CHE2 0x6703 -#define STM32H7_PG7_FUNC_SAI1_MCLK_A 0x6707 -#define STM32H7_PG7_FUNC_USART6_CK 0x6708 -#define STM32H7_PG7_FUNC_FMC_INT 0x670d -#define STM32H7_PG7_FUNC_DCMI_D13 0x670e -#define STM32H7_PG7_FUNC_LCD_CLK 0x670f -#define STM32H7_PG7_FUNC_EVENTOUT 0x6710 -#define STM32H7_PG7_FUNC_ANALOG 0x6711 - -#define STM32H7_PG8_FUNC_GPIO 0x6800 -#define STM32H7_PG8_FUNC_TIM8_ETR 0x6804 -#define STM32H7_PG8_FUNC_SPI6_NSS 0x6806 -#define STM32H7_PG8_FUNC_USART6_RTS 0x6808 -#define STM32H7_PG8_FUNC_SPDIFRX_IN2 0x6809 -#define STM32H7_PG8_FUNC_ETH_PPS_OUT 0x680c -#define STM32H7_PG8_FUNC_FMC_SDCLK 0x680d -#define STM32H7_PG8_FUNC_LCD_G7 0x680f -#define STM32H7_PG8_FUNC_EVENTOUT 0x6810 -#define STM32H7_PG8_FUNC_ANALOG 0x6811 - -#define STM32H7_PG9_FUNC_GPIO 0x6900 -#define STM32H7_PG9_FUNC_SPI1_MISO_I2S1_SDI 0x6906 -#define STM32H7_PG9_FUNC_USART6_RX 0x6908 -#define STM32H7_PG9_FUNC_SPDIFRX_IN3 0x6909 -#define STM32H7_PG9_FUNC_QUADSPI_BK2_IO2 0x690a -#define STM32H7_PG9_FUNC_SAI2_FS_B 0x690b -#define STM32H7_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d -#define STM32H7_PG9_FUNC_DCMI_VSYNC 0x690e -#define STM32H7_PG9_FUNC_EVENTOUT 0x6910 -#define STM32H7_PG9_FUNC_ANALOG 0x6911 - -#define STM32H7_PG10_FUNC_GPIO 0x6a00 -#define STM32H7_PG10_FUNC_HRTIM_FLT5 0x6a03 -#define STM32H7_PG10_FUNC_SPI1_NSS_I2S1_WS 0x6a06 -#define STM32H7_PG10_FUNC_LCD_G3 0x6a0a -#define STM32H7_PG10_FUNC_SAI2_SD_B 0x6a0b -#define STM32H7_PG10_FUNC_FMC_NE3 0x6a0d -#define STM32H7_PG10_FUNC_DCMI_D2 0x6a0e -#define STM32H7_PG10_FUNC_LCD_B2 0x6a0f -#define STM32H7_PG10_FUNC_EVENTOUT 0x6a10 -#define STM32H7_PG10_FUNC_ANALOG 0x6a11 - -#define STM32H7_PG11_FUNC_GPIO 0x6b00 -#define STM32H7_PG11_FUNC_HRTIM_EEV4 0x6b03 -#define STM32H7_PG11_FUNC_SPI1_SCK_I2S1_CK 0x6b06 -#define STM32H7_PG11_FUNC_SPDIFRX_IN0 0x6b09 -#define STM32H7_PG11_FUNC_SDMMC2_D2 0x6b0b -#define STM32H7_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c -#define STM32H7_PG11_FUNC_DCMI_D3 0x6b0e -#define STM32H7_PG11_FUNC_LCD_B3 0x6b0f -#define STM32H7_PG11_FUNC_EVENTOUT 0x6b10 -#define STM32H7_PG11_FUNC_ANALOG 0x6b11 - -#define STM32H7_PG12_FUNC_GPIO 0x6c00 -#define STM32H7_PG12_FUNC_LPTIM1_IN1 0x6c02 -#define STM32H7_PG12_FUNC_HRTIM_EEV5 0x6c03 -#define STM32H7_PG12_FUNC_SPI6_MISO 0x6c06 -#define STM32H7_PG12_FUNC_USART6_RTS 0x6c08 -#define STM32H7_PG12_FUNC_SPDIFRX_IN1 0x6c09 -#define STM32H7_PG12_FUNC_LCD_B4 0x6c0a -#define STM32H7_PG12_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6c0c -#define STM32H7_PG12_FUNC_FMC_NE4 0x6c0d -#define STM32H7_PG12_FUNC_LCD_B1 0x6c0f -#define STM32H7_PG12_FUNC_EVENTOUT 0x6c10 -#define STM32H7_PG12_FUNC_ANALOG 0x6c11 - -#define STM32H7_PG13_FUNC_GPIO 0x6d00 -#define STM32H7_PG13_FUNC_TRACED0 0x6d01 -#define STM32H7_PG13_FUNC_LPTIM1_OUT 0x6d02 -#define STM32H7_PG13_FUNC_HRTIM_EEV10 0x6d03 -#define STM32H7_PG13_FUNC_SPI6_SCK 0x6d06 -#define STM32H7_PG13_FUNC_USART6_CTS_NSS 0x6d08 -#define STM32H7_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c -#define STM32H7_PG13_FUNC_FMC_A24 0x6d0d -#define STM32H7_PG13_FUNC_LCD_R0 0x6d0f -#define STM32H7_PG13_FUNC_EVENTOUT 0x6d10 -#define STM32H7_PG13_FUNC_ANALOG 0x6d11 - -#define STM32H7_PG14_FUNC_GPIO 0x6e00 -#define STM32H7_PG14_FUNC_TRACED1 0x6e01 -#define STM32H7_PG14_FUNC_LPTIM1_ETR 0x6e02 -#define STM32H7_PG14_FUNC_SPI6_MOSI 0x6e06 -#define STM32H7_PG14_FUNC_USART6_TX 0x6e08 -#define STM32H7_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a -#define STM32H7_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c -#define STM32H7_PG14_FUNC_FMC_A25 0x6e0d -#define STM32H7_PG14_FUNC_LCD_B0 0x6e0f -#define STM32H7_PG14_FUNC_EVENTOUT 0x6e10 -#define STM32H7_PG14_FUNC_ANALOG 0x6e11 - -#define STM32H7_PG15_FUNC_GPIO 0x6f00 -#define STM32H7_PG15_FUNC_USART6_CTS_NSS 0x6f08 -#define STM32H7_PG15_FUNC_FMC_SDNCAS 0x6f0d -#define STM32H7_PG15_FUNC_DCMI_D13 0x6f0e -#define STM32H7_PG15_FUNC_EVENTOUT 0x6f10 -#define STM32H7_PG15_FUNC_ANALOG 0x6f11 - -#define STM32H7_PH0_FUNC_GPIO 0x7000 -#define STM32H7_PH0_FUNC_EVENTOUT 0x7010 -#define STM32H7_PH0_FUNC_ANALOG 0x7011 - -#define STM32H7_PH1_FUNC_GPIO 0x7100 -#define STM32H7_PH1_FUNC_EVENTOUT 0x7110 -#define STM32H7_PH1_FUNC_ANALOG 0x7111 - -#define STM32H7_PH2_FUNC_GPIO 0x7200 -#define STM32H7_PH2_FUNC_LPTIM1_IN2 0x7202 -#define STM32H7_PH2_FUNC_QUADSPI_BK2_IO0 0x720a -#define STM32H7_PH2_FUNC_SAI2_SCK_B 0x720b -#define STM32H7_PH2_FUNC_ETH_MII_CRS 0x720c -#define STM32H7_PH2_FUNC_FMC_SDCKE0 0x720d -#define STM32H7_PH2_FUNC_LCD_R0 0x720f -#define STM32H7_PH2_FUNC_EVENTOUT 0x7210 -#define STM32H7_PH2_FUNC_ANALOG 0x7211 - -#define STM32H7_PH3_FUNC_GPIO 0x7300 -#define STM32H7_PH3_FUNC_QUADSPI_BK2_IO1 0x730a -#define STM32H7_PH3_FUNC_SAI2_MCK_B 0x730b -#define STM32H7_PH3_FUNC_ETH_MII_COL 0x730c -#define STM32H7_PH3_FUNC_FMC_SDNE0 0x730d -#define STM32H7_PH3_FUNC_LCD_R1 0x730f -#define STM32H7_PH3_FUNC_EVENTOUT 0x7310 -#define STM32H7_PH3_FUNC_ANALOG 0x7311 - -#define STM32H7_PH4_FUNC_GPIO 0x7400 -#define STM32H7_PH4_FUNC_I2C2_SCL 0x7405 -#define STM32H7_PH4_FUNC_LCD_G5 0x740a -#define STM32H7_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b -#define STM32H7_PH4_FUNC_LCD_G4 0x740f -#define STM32H7_PH4_FUNC_EVENTOUT 0x7410 -#define STM32H7_PH4_FUNC_ANALOG 0x7411 - -#define STM32H7_PH5_FUNC_GPIO 0x7500 -#define STM32H7_PH5_FUNC_I2C2_SDA 0x7505 -#define STM32H7_PH5_FUNC_SPI5_NSS 0x7506 -#define STM32H7_PH5_FUNC_FMC_SDNWE 0x750d -#define STM32H7_PH5_FUNC_EVENTOUT 0x7510 -#define STM32H7_PH5_FUNC_ANALOG 0x7511 - -#define STM32H7_PH6_FUNC_GPIO 0x7600 -#define STM32H7_PH6_FUNC_I2C2_SMBA 0x7605 -#define STM32H7_PH6_FUNC_SPI5_SCK 0x7606 -#define STM32H7_PH6_FUNC_ETH_MII_RXD2 0x760c -#define STM32H7_PH6_FUNC_FMC_SDNE1 0x760d -#define STM32H7_PH6_FUNC_DCMI_D8 0x760e -#define STM32H7_PH6_FUNC_EVENTOUT 0x7610 -#define STM32H7_PH6_FUNC_ANALOG 0x7611 - -#define STM32H7_PH7_FUNC_GPIO 0x7700 -#define STM32H7_PH7_FUNC_I2C3_SCL 0x7705 -#define STM32H7_PH7_FUNC_SPI5_MISO 0x7706 -#define STM32H7_PH7_FUNC_ETH_MII_RXD3 0x770c -#define STM32H7_PH7_FUNC_FMC_SDCKE1 0x770d -#define STM32H7_PH7_FUNC_DCMI_D9 0x770e -#define STM32H7_PH7_FUNC_EVENTOUT 0x7710 -#define STM32H7_PH7_FUNC_ANALOG 0x7711 - -#define STM32H7_PH8_FUNC_GPIO 0x7800 -#define STM32H7_PH8_FUNC_TIM5_ETR 0x7803 -#define STM32H7_PH8_FUNC_I2C3_SDA 0x7805 -#define STM32H7_PH8_FUNC_FMC_D16 0x780d -#define STM32H7_PH8_FUNC_DCMI_HSYNC 0x780e -#define STM32H7_PH8_FUNC_LCD_R2 0x780f -#define STM32H7_PH8_FUNC_EVENTOUT 0x7810 -#define STM32H7_PH8_FUNC_ANALOG 0x7811 - -#define STM32H7_PH9_FUNC_GPIO 0x7900 -#define STM32H7_PH9_FUNC_I2C3_SMBA 0x7905 -#define STM32H7_PH9_FUNC_FMC_D17 0x790d -#define STM32H7_PH9_FUNC_DCMI_D0 0x790e -#define STM32H7_PH9_FUNC_LCD_R3 0x790f -#define STM32H7_PH9_FUNC_EVENTOUT 0x7910 -#define STM32H7_PH9_FUNC_ANALOG 0x7911 - -#define STM32H7_PH10_FUNC_GPIO 0x7a00 -#define STM32H7_PH10_FUNC_TIM5_CH1 0x7a03 -#define STM32H7_PH10_FUNC_I2C4_SMBA 0x7a05 -#define STM32H7_PH10_FUNC_FMC_D18 0x7a0d -#define STM32H7_PH10_FUNC_DCMI_D1 0x7a0e -#define STM32H7_PH10_FUNC_LCD_R4 0x7a0f -#define STM32H7_PH10_FUNC_EVENTOUT 0x7a10 -#define STM32H7_PH10_FUNC_ANALOG 0x7a11 - -#define STM32H7_PH11_FUNC_GPIO 0x7b00 -#define STM32H7_PH11_FUNC_TIM5_CH2 0x7b03 -#define STM32H7_PH11_FUNC_I2C4_SCL 0x7b05 -#define STM32H7_PH11_FUNC_FMC_D19 0x7b0d -#define STM32H7_PH11_FUNC_DCMI_D2 0x7b0e -#define STM32H7_PH11_FUNC_LCD_R5 0x7b0f -#define STM32H7_PH11_FUNC_EVENTOUT 0x7b10 -#define STM32H7_PH11_FUNC_ANALOG 0x7b11 - -#define STM32H7_PH12_FUNC_GPIO 0x7c00 -#define STM32H7_PH12_FUNC_TIM5_CH3 0x7c03 -#define STM32H7_PH12_FUNC_I2C4_SDA 0x7c05 -#define STM32H7_PH12_FUNC_FMC_D20 0x7c0d -#define STM32H7_PH12_FUNC_DCMI_D3 0x7c0e -#define STM32H7_PH12_FUNC_LCD_R6 0x7c0f -#define STM32H7_PH12_FUNC_EVENTOUT 0x7c10 -#define STM32H7_PH12_FUNC_ANALOG 0x7c11 - -#define STM32H7_PH13_FUNC_GPIO 0x7d00 -#define STM32H7_PH13_FUNC_TIM8_CH1N 0x7d04 -#define STM32H7_PH13_FUNC_UART4_TX 0x7d09 -#define STM32H7_PH13_FUNC_CAN1_TX 0x7d0a -#define STM32H7_PH13_FUNC_FMC_D21 0x7d0d -#define STM32H7_PH13_FUNC_LCD_G2 0x7d0f -#define STM32H7_PH13_FUNC_EVENTOUT 0x7d10 -#define STM32H7_PH13_FUNC_ANALOG 0x7d11 - -#define STM32H7_PH14_FUNC_GPIO 0x7e00 -#define STM32H7_PH14_FUNC_TIM8_CH2N 0x7e04 -#define STM32H7_PH14_FUNC_UART4_RX 0x7e09 -#define STM32H7_PH14_FUNC_CAN1_RX 0x7e0a -#define STM32H7_PH14_FUNC_FMC_D22 0x7e0d -#define STM32H7_PH14_FUNC_DCMI_D4 0x7e0e -#define STM32H7_PH14_FUNC_LCD_G3 0x7e0f -#define STM32H7_PH14_FUNC_EVENTOUT 0x7e10 -#define STM32H7_PH14_FUNC_ANALOG 0x7e11 - -#define STM32H7_PH15_FUNC_GPIO 0x7f00 -#define STM32H7_PH15_FUNC_TIM8_CH3N 0x7f04 -#define STM32H7_PH15_FUNC_CAN1_TXFD 0x7f0a -#define STM32H7_PH15_FUNC_FMC_D23 0x7f0d -#define STM32H7_PH15_FUNC_DCMI_D11 0x7f0e -#define STM32H7_PH15_FUNC_LCD_G4 0x7f0f -#define STM32H7_PH15_FUNC_EVENTOUT 0x7f10 -#define STM32H7_PH15_FUNC_ANALOG 0x7f11 - -#define STM32H7_PI0_FUNC_GPIO 0x8000 -#define STM32H7_PI0_FUNC_TIM5_CH4 0x8003 -#define STM32H7_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 -#define STM32H7_PI0_FUNC_CAN1_RXFD 0x800a -#define STM32H7_PI0_FUNC_FMC_D24 0x800d -#define STM32H7_PI0_FUNC_DCMI_D13 0x800e -#define STM32H7_PI0_FUNC_LCD_G5 0x800f -#define STM32H7_PI0_FUNC_EVENTOUT 0x8010 -#define STM32H7_PI0_FUNC_ANALOG 0x8011 - -#define STM32H7_PI1_FUNC_GPIO 0x8100 -#define STM32H7_PI1_FUNC_TIM8_BKIN2 0x8104 -#define STM32H7_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 -#define STM32H7_PI1_FUNC_TIM8_BKIN2_COMP12 0x810c -#define STM32H7_PI1_FUNC_FMC_D25 0x810d -#define STM32H7_PI1_FUNC_DCMI_D8 0x810e -#define STM32H7_PI1_FUNC_LCD_G6 0x810f -#define STM32H7_PI1_FUNC_EVENTOUT 0x8110 -#define STM32H7_PI1_FUNC_ANALOG 0x8111 - -#define STM32H7_PI2_FUNC_GPIO 0x8200 -#define STM32H7_PI2_FUNC_TIM8_CH4 0x8204 -#define STM32H7_PI2_FUNC_SPI2_MISO_I2S2_SDI 0x8206 -#define STM32H7_PI2_FUNC_FMC_D26 0x820d -#define STM32H7_PI2_FUNC_DCMI_D9 0x820e -#define STM32H7_PI2_FUNC_LCD_G7 0x820f -#define STM32H7_PI2_FUNC_EVENTOUT 0x8210 -#define STM32H7_PI2_FUNC_ANALOG 0x8211 - -#define STM32H7_PI3_FUNC_GPIO 0x8300 -#define STM32H7_PI3_FUNC_TIM8_ETR 0x8304 -#define STM32H7_PI3_FUNC_SPI2_MOSI_I2S2_SDO 0x8306 -#define STM32H7_PI3_FUNC_FMC_D27 0x830d -#define STM32H7_PI3_FUNC_DCMI_D10 0x830e -#define STM32H7_PI3_FUNC_EVENTOUT 0x8310 -#define STM32H7_PI3_FUNC_ANALOG 0x8311 - -#define STM32H7_PI4_FUNC_GPIO 0x8400 -#define STM32H7_PI4_FUNC_TIM8_BKIN 0x8404 -#define STM32H7_PI4_FUNC_SAI2_MCK_A 0x840b -#define STM32H7_PI4_FUNC_TIM8_BKIN_COMP12 0x840c -#define STM32H7_PI4_FUNC_FMC_NBL2 0x840d -#define STM32H7_PI4_FUNC_DCMI_D5 0x840e -#define STM32H7_PI4_FUNC_LCD_B4 0x840f -#define STM32H7_PI4_FUNC_EVENTOUT 0x8410 -#define STM32H7_PI4_FUNC_ANALOG 0x8411 - -#define STM32H7_PI5_FUNC_GPIO 0x8500 -#define STM32H7_PI5_FUNC_TIM8_CH1 0x8504 -#define STM32H7_PI5_FUNC_SAI2_SCK_A 0x850b -#define STM32H7_PI5_FUNC_FMC_NBL3 0x850d -#define STM32H7_PI5_FUNC_DCMI_VSYNC 0x850e -#define STM32H7_PI5_FUNC_LCD_B5 0x850f -#define STM32H7_PI5_FUNC_EVENTOUT 0x8510 -#define STM32H7_PI5_FUNC_ANALOG 0x8511 - -#define STM32H7_PI6_FUNC_GPIO 0x8600 -#define STM32H7_PI6_FUNC_TIM8_CH2 0x8604 -#define STM32H7_PI6_FUNC_SAI2_SD_A 0x860b -#define STM32H7_PI6_FUNC_FMC_D28 0x860d -#define STM32H7_PI6_FUNC_DCMI_D6 0x860e -#define STM32H7_PI6_FUNC_LCD_B6 0x860f -#define STM32H7_PI6_FUNC_EVENTOUT 0x8610 -#define STM32H7_PI6_FUNC_ANALOG 0x8611 - -#define STM32H7_PI7_FUNC_GPIO 0x8700 -#define STM32H7_PI7_FUNC_TIM8_CH3 0x8704 -#define STM32H7_PI7_FUNC_SAI2_FS_A 0x870b -#define STM32H7_PI7_FUNC_FMC_D29 0x870d -#define STM32H7_PI7_FUNC_DCMI_D7 0x870e -#define STM32H7_PI7_FUNC_LCD_B7 0x870f -#define STM32H7_PI7_FUNC_EVENTOUT 0x8710 -#define STM32H7_PI7_FUNC_ANALOG 0x8711 - -#define STM32H7_PI8_FUNC_GPIO 0x8800 -#define STM32H7_PI8_FUNC_EVENTOUT 0x8810 -#define STM32H7_PI8_FUNC_ANALOG 0x8811 - -#define STM32H7_PI9_FUNC_GPIO 0x8900 -#define STM32H7_PI9_FUNC_UART4_RX 0x8909 -#define STM32H7_PI9_FUNC_CAN1_RX 0x890a -#define STM32H7_PI9_FUNC_FMC_D30 0x890d -#define STM32H7_PI9_FUNC_LCD_VSYNC 0x890f -#define STM32H7_PI9_FUNC_EVENTOUT 0x8910 -#define STM32H7_PI9_FUNC_ANALOG 0x8911 - -#define STM32H7_PI10_FUNC_GPIO 0x8a00 -#define STM32H7_PI10_FUNC_CAN1_RXFD 0x8a0a -#define STM32H7_PI10_FUNC_ETH_MII_RX_ER 0x8a0c -#define STM32H7_PI10_FUNC_FMC_D31 0x8a0d -#define STM32H7_PI10_FUNC_LCD_HSYNC 0x8a0f -#define STM32H7_PI10_FUNC_EVENTOUT 0x8a10 -#define STM32H7_PI10_FUNC_ANALOG 0x8a11 - -#define STM32H7_PI11_FUNC_GPIO 0x8b00 -#define STM32H7_PI11_FUNC_LCD_G6 0x8b0a -#define STM32H7_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b -#define STM32H7_PI11_FUNC_EVENTOUT 0x8b10 -#define STM32H7_PI11_FUNC_ANALOG 0x8b11 - -#define STM32H7_PI12_FUNC_GPIO 0x8c00 -#define STM32H7_PI12_FUNC_ETH_TX_ER 0x8c0c -#define STM32H7_PI12_FUNC_LCD_HSYNC 0x8c0f -#define STM32H7_PI12_FUNC_EVENTOUT 0x8c10 -#define STM32H7_PI12_FUNC_ANALOG 0x8c11 - -#define STM32H7_PI13_FUNC_GPIO 0x8d00 -#define STM32H7_PI13_FUNC_LCD_VSYNC 0x8d0f -#define STM32H7_PI13_FUNC_EVENTOUT 0x8d10 -#define STM32H7_PI13_FUNC_ANALOG 0x8d11 - -#define STM32H7_PI14_FUNC_GPIO 0x8e00 -#define STM32H7_PI14_FUNC_LCD_CLK 0x8e0f -#define STM32H7_PI14_FUNC_EVENTOUT 0x8e10 -#define STM32H7_PI14_FUNC_ANALOG 0x8e11 - -#define STM32H7_PI15_FUNC_GPIO 0x8f00 -#define STM32H7_PI15_FUNC_LCD_G2 0x8f0a -#define STM32H7_PI15_FUNC_LCD_R0 0x8f0f -#define STM32H7_PI15_FUNC_EVENTOUT 0x8f10 -#define STM32H7_PI15_FUNC_ANALOG 0x8f11 - -#define STM32H7_PJ0_FUNC_GPIO 0x9000 -#define STM32H7_PJ0_FUNC_LCD_R7 0x900a -#define STM32H7_PJ0_FUNC_LCD_R1 0x900f -#define STM32H7_PJ0_FUNC_EVENTOUT 0x9010 -#define STM32H7_PJ0_FUNC_ANALOG 0x9011 - -#define STM32H7_PJ1_FUNC_GPIO 0x9100 -#define STM32H7_PJ1_FUNC_LCD_R2 0x910f -#define STM32H7_PJ1_FUNC_EVENTOUT 0x9110 -#define STM32H7_PJ1_FUNC_ANALOG 0x9111 - -#define STM32H7_PJ2_FUNC_GPIO 0x9200 -#define STM32H7_PJ2_FUNC_DSI_TE 0x920e -#define STM32H7_PJ2_FUNC_LCD_R3 0x920f -#define STM32H7_PJ2_FUNC_EVENTOUT 0x9210 -#define STM32H7_PJ2_FUNC_ANALOG 0x9211 - -#define STM32H7_PJ3_FUNC_GPIO 0x9300 -#define STM32H7_PJ3_FUNC_LCD_R4 0x930f -#define STM32H7_PJ3_FUNC_EVENTOUT 0x9310 -#define STM32H7_PJ3_FUNC_ANALOG 0x9311 - -#define STM32H7_PJ4_FUNC_GPIO 0x9400 -#define STM32H7_PJ4_FUNC_LCD_R5 0x940f -#define STM32H7_PJ4_FUNC_EVENTOUT 0x9410 -#define STM32H7_PJ4_FUNC_ANALOG 0x9411 - -#define STM32H7_PJ5_FUNC_GPIO 0x9500 -#define STM32H7_PJ5_FUNC_LCD_R6 0x950f -#define STM32H7_PJ5_FUNC_EVENTOUT 0x9510 -#define STM32H7_PJ5_FUNC_ANALOG 0x9511 - -#define STM32H7_PJ6_FUNC_GPIO 0x9600 -#define STM32H7_PJ6_FUNC_TIM8_CH2 0x9604 -#define STM32H7_PJ6_FUNC_LCD_R7 0x960f -#define STM32H7_PJ6_FUNC_EVENTOUT 0x9610 -#define STM32H7_PJ6_FUNC_ANALOG 0x9611 - -#define STM32H7_PJ7_FUNC_GPIO 0x9700 -#define STM32H7_PJ7_FUNC_TRGIN 0x9701 -#define STM32H7_PJ7_FUNC_TIM8_CH2N 0x9704 -#define STM32H7_PJ7_FUNC_LCD_G0 0x970f -#define STM32H7_PJ7_FUNC_EVENTOUT 0x9710 -#define STM32H7_PJ7_FUNC_ANALOG 0x9711 - -#define STM32H7_PJ8_FUNC_GPIO 0x9800 -#define STM32H7_PJ8_FUNC_TIM1_CH3N 0x9802 -#define STM32H7_PJ8_FUNC_TIM8_CH1 0x9804 -#define STM32H7_PJ8_FUNC_UART8_TX 0x9809 -#define STM32H7_PJ8_FUNC_LCD_G1 0x980f -#define STM32H7_PJ8_FUNC_EVENTOUT 0x9810 -#define STM32H7_PJ8_FUNC_ANALOG 0x9811 - -#define STM32H7_PJ9_FUNC_GPIO 0x9900 -#define STM32H7_PJ9_FUNC_TIM1_CH3 0x9902 -#define STM32H7_PJ9_FUNC_TIM8_CH1N 0x9904 -#define STM32H7_PJ9_FUNC_UART8_RX 0x9909 -#define STM32H7_PJ9_FUNC_LCD_G2 0x990f -#define STM32H7_PJ9_FUNC_EVENTOUT 0x9910 -#define STM32H7_PJ9_FUNC_ANALOG 0x9911 - -#define STM32H7_PJ10_FUNC_GPIO 0x9a00 -#define STM32H7_PJ10_FUNC_TIM1_CH2N 0x9a02 -#define STM32H7_PJ10_FUNC_TIM8_CH2 0x9a04 -#define STM32H7_PJ10_FUNC_SPI5_MOSI 0x9a06 -#define STM32H7_PJ10_FUNC_LCD_G3 0x9a0f -#define STM32H7_PJ10_FUNC_EVENTOUT 0x9a10 -#define STM32H7_PJ10_FUNC_ANALOG 0x9a11 - -#define STM32H7_PJ11_FUNC_GPIO 0x9b00 -#define STM32H7_PJ11_FUNC_TIM1_CH2 0x9b02 -#define STM32H7_PJ11_FUNC_TIM8_CH2N 0x9b04 -#define STM32H7_PJ11_FUNC_SPI5_MISO 0x9b06 -#define STM32H7_PJ11_FUNC_LCD_G4 0x9b0f -#define STM32H7_PJ11_FUNC_EVENTOUT 0x9b10 -#define STM32H7_PJ11_FUNC_ANALOG 0x9b11 - -#define STM32H7_PJ12_FUNC_GPIO 0x9c00 -#define STM32H7_PJ12_FUNC_TRGOUT 0x9c01 -#define STM32H7_PJ12_FUNC_LCD_G3 0x9c0a -#define STM32H7_PJ12_FUNC_LCD_B0 0x9c0f -#define STM32H7_PJ12_FUNC_EVENTOUT 0x9c10 -#define STM32H7_PJ12_FUNC_ANALOG 0x9c11 - -#define STM32H7_PJ13_FUNC_GPIO 0x9d00 -#define STM32H7_PJ13_FUNC_LCD_B4 0x9d0a -#define STM32H7_PJ13_FUNC_LCD_B1 0x9d0f -#define STM32H7_PJ13_FUNC_EVENTOUT 0x9d10 -#define STM32H7_PJ13_FUNC_ANALOG 0x9d11 - -#define STM32H7_PJ14_FUNC_GPIO 0x9e00 -#define STM32H7_PJ14_FUNC_LCD_B2 0x9e0f -#define STM32H7_PJ14_FUNC_EVENTOUT 0x9e10 -#define STM32H7_PJ14_FUNC_ANALOG 0x9e11 - -#define STM32H7_PJ15_FUNC_GPIO 0x9f00 -#define STM32H7_PJ15_FUNC_LCD_B3 0x9f0f -#define STM32H7_PJ15_FUNC_EVENTOUT 0x9f10 -#define STM32H7_PJ15_FUNC_ANALOG 0x9f11 - -#define STM32H7_PK0_FUNC_GPIO 0xa000 -#define STM32H7_PK0_FUNC_TIM1_CH1N 0xa002 -#define STM32H7_PK0_FUNC_TIM8_CH3 0xa004 -#define STM32H7_PK0_FUNC_SPI5_SCK 0xa006 -#define STM32H7_PK0_FUNC_LCD_G5 0xa00f -#define STM32H7_PK0_FUNC_EVENTOUT 0xa010 -#define STM32H7_PK0_FUNC_ANALOG 0xa011 - -#define STM32H7_PK1_FUNC_GPIO 0xa100 -#define STM32H7_PK1_FUNC_TIM1_CH1 0xa102 -#define STM32H7_PK1_FUNC_TIM8_CH3N 0xa104 -#define STM32H7_PK1_FUNC_SPI5_NSS 0xa106 -#define STM32H7_PK1_FUNC_LCD_G6 0xa10f -#define STM32H7_PK1_FUNC_EVENTOUT 0xa110 -#define STM32H7_PK1_FUNC_ANALOG 0xa111 - -#define STM32H7_PK2_FUNC_GPIO 0xa200 -#define STM32H7_PK2_FUNC_TIM1_BKIN 0xa202 -#define STM32H7_PK2_FUNC_TIM8_BKIN 0xa204 -#define STM32H7_PK2_FUNC_TIM8_BKIN_COMP12 0xa20b -#define STM32H7_PK2_FUNC_TIM1_BKIN_COMP12 0xa20c -#define STM32H7_PK2_FUNC_LCD_G7 0xa20f -#define STM32H7_PK2_FUNC_EVENTOUT 0xa210 -#define STM32H7_PK2_FUNC_ANALOG 0xa211 - -#define STM32H7_PK3_FUNC_GPIO 0xa300 -#define STM32H7_PK3_FUNC_LCD_B4 0xa30f -#define STM32H7_PK3_FUNC_EVENTOUT 0xa310 -#define STM32H7_PK3_FUNC_ANALOG 0xa311 - -#define STM32H7_PK4_FUNC_GPIO 0xa400 -#define STM32H7_PK4_FUNC_LCD_B5 0xa40f -#define STM32H7_PK4_FUNC_EVENTOUT 0xa410 -#define STM32H7_PK4_FUNC_ANALOG 0xa411 - -#define STM32H7_PK5_FUNC_GPIO 0xa500 -#define STM32H7_PK5_FUNC_LCD_B6 0xa50f -#define STM32H7_PK5_FUNC_EVENTOUT 0xa510 -#define STM32H7_PK5_FUNC_ANALOG 0xa511 - -#define STM32H7_PK6_FUNC_GPIO 0xa600 -#define STM32H7_PK6_FUNC_LCD_B7 0xa60f -#define STM32H7_PK6_FUNC_EVENTOUT 0xa610 -#define STM32H7_PK6_FUNC_ANALOG 0xa611 - -#define STM32H7_PK7_FUNC_GPIO 0xa700 -#define STM32H7_PK7_FUNC_LCD_DE 0xa70f -#define STM32H7_PK7_FUNC_EVENTOUT 0xa710 -#define STM32H7_PK7_FUNC_ANALOG 0xa711 - -#endif /* _DT_BINDINGS_STM32H7_PINFUNC_H */ -- cgit v1.2.3 From fbe8749897710deffae4c77c1cdc34b31e2fc773 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 13 Oct 2017 11:01:46 +0200 Subject: pinctrl: dt-bindings: Fix A37xx uart2 group name Fix a typo in A37xx pin controllers documentation about uart2 pin group. Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt index f64060908d5a..c7c088d2dd50 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt @@ -97,8 +97,8 @@ group spi_quad - pins 15-16 - functions spi, gpio -group uart_2 - - pins 9-10 +group uart2 + - pins 9-10 and 18-19 - functions uart, gpio Available groups and functions for the South bridge: -- cgit v1.2.3 From 7ef3b44ceafb5456b7e43e2bd96e22bb696806c9 Mon Sep 17 00:00:00 2001 From: Jacob Chen Date: Wed, 11 Oct 2017 00:29:34 -0700 Subject: [media] dt-bindings: Document the Rockchip RGA bindings Add DT bindings documentation for Rockchip RGA Signed-off-by: Jacob Chen Signed-off-by: Yakir Yang Acked-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/rockchip-rga.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-rga.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.txt b/Documentation/devicetree/bindings/media/rockchip-rga.txt new file mode 100644 index 000000000000..fd5276abfad6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-rga.txt @@ -0,0 +1,33 @@ +device-tree bindings for rockchip 2D raster graphic acceleration controller (RGA) + +RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D +graphics operations, such as point/line drawing, image scaling, rotation, +BitBLT, alpha blending and image blur/sharpness. + +Required properties: +- compatible: value should be one of the following + "rockchip,rk3288-rga"; + "rockchip,rk3399-rga"; + +- interrupts: RGA interrupt specifier. + +- clocks: phandle to RGA sclk/hclk/aclk clocks + +- clock-names: should be "aclk", "hclk" and "sclk" + +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: should be "core", "axi" and "ahb" + +Example: +SoC-specific DT entry: + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0xff680000 0x10000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core, "axi", "ahb"; + }; -- cgit v1.2.3 From defc3a47c53d54e933ecb923c064c36be4cf70e6 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 13 Sep 2017 04:41:52 -0700 Subject: media: exynos-gsc: Add compatible for Exynos 5250 and 5420 SoC version Exynos 5250 and 5420 have different hardware rotation limits. Since we have to distinguish between these two, we add different compatible: samsung,exynos5250-gsc and samsung,exynos5420-gsc. Signed-off-by: Hoegeun Kwon Signed-off-by: Sylwester Nawrocki Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/exynos5-gsc.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt index 26ca25b6d264..0d4fdaedc6f1 100644 --- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt +++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt @@ -3,8 +3,11 @@ G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs. Required properties: -- compatible: should be "samsung,exynos5-gsc" (for Exynos 5250, 5420 and - 5422 SoCs) or "samsung,exynos5433-gsc" (Exynos 5433) +- compatible: should be one of + "samsung,exynos5250-gsc" + "samsung,exynos5420-gsc" + "samsung,exynos5433-gsc" + "samsung,exynos5-gsc" (deprecated) - reg: should contain G-Scaler physical address location and length. - interrupts: should contain G-Scaler interrupt number @@ -15,7 +18,7 @@ Optional properties: Example: gsc_0: gsc@0x13e00000 { - compatible = "samsung,exynos5-gsc"; + compatible = "samsung,exynos5250-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; }; -- cgit v1.2.3 From a197c7fccc0d8958ff73e323dcb1985c19d8166f Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 18 Sep 2017 01:15:53 -0700 Subject: media: dt: bindings: media: Document practices for DT bindings, ports, endpoints Port and endpoint numbering has been omitted in DT binding documentation for a large number of devices. Also common properties the device uses have been missed in binding documentation. Make it explicit that these things need to be documented. Signed-off-by: Sakari Ailus Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/video-interfaces.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index 852041a7480c..bc8f18fb6730 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -55,6 +55,15 @@ divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width and data-shift properties can be used to assign physical data lines to each endpoint node (logical bus). +Documenting bindings for devices +-------------------------------- + +All required and optional bindings the device supports shall be explicitly +documented in device DT binding documentation. This also includes port and +endpoint nodes for the device, including unit-addresses and reg properties where +relevant. + +Please also see Documentation/devicetree/bindings/graph.txt . Required properties ------------------- -- cgit v1.2.3 From 7571358dd22dc91dea560f0dde62ce23c033b6b6 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 18 Sep 2017 01:20:59 -0700 Subject: media: dt: bindings: media: Document data lane numbering without lane reordering Most devices do not support lane reordering and in many cases the documentation of the data-lanes property is incomplete for such devices. Document that in case the lane reordering isn't supported, monotonically incremented values from 0 or 1 shall be used. Signed-off-by: Sakari Ailus Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/video-interfaces.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index bc8f18fb6730..bd6474920510 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -108,7 +108,10 @@ Optional endpoint properties determines the logical lane number, while the value of an entry indicates physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. - This property is valid for serial busses only (e.g. MIPI CSI-2). + If the hardware does not support lane reordering, monotonically + incremented values shall be used from 0 or 1 onwards, depending on + whether or not there is also a clock lane. This property is valid for + serial busses only (e.g. MIPI CSI-2). - clock-lanes: an array of physical clock lane indexes. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", -- cgit v1.2.3 From 18a3dde9db78076755275423b754846a2da000ad Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 3 Oct 2017 10:49:20 +0530 Subject: mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Update binding documentation to add a new compatible for TI 66AK2G SoC, to handle TI SoC specific quirks in the driver. Signed-off-by: Vignesh R Acked-by: Rob Herring Acked-by: Marek Vasut Signed-off-by: Cyrille Pitchen --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index f248056da24c..7dbe3bd9ac56 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -1,7 +1,9 @@ * Cadence Quad SPI controller Required properties: -- compatible : Should be "cdns,qspi-nor". +- compatible : should be one of the following: + Generic default - "cdns,qspi-nor". + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the -- cgit v1.2.3 From 00df263560673cefe3341275990324730d4791d5 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 3 Oct 2017 10:49:22 +0530 Subject: mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Cadence QSPI IP has a adapted loop-back circuit which can be enabled by setting BYPASS field to 0 in READCAPTURE register. It enables use of QSPI return clock to latch the data rather than the internal QSPI reference clock. For high speed operations, adapted loop-back circuit using QSPI return clock helps to increase data valid window. Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit for boards which do have QSPI return clock provided. Update binding documentation for the same. Signed-off-by: Vignesh R Acked-by: Rob Herring Acked-by: Marek Vasut Signed-off-by: Cyrille Pitchen --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index 7dbe3bd9ac56..bb2075df9b38 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -16,6 +16,9 @@ Required properties: Optional properties: - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. +- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch + the read data rather than the QSPI clock. Make sure that QSPI return + clock is populated on the board before using this property. Optional subnodes: Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -- cgit v1.2.3 From 2ceec8be7d5c7c6b8f4e907c9d46ee3764c19016 Mon Sep 17 00:00:00 2001 From: Tom McLeod Date: Wed, 11 Oct 2017 11:57:50 -0700 Subject: dt-bindings: Add vendor prefix for Opal Kelly Inc Opal Kelly is a manufacturer of FPGA Integration Modules. Signed-off-by: Tom McLeod Cc: Rob Herring Cc: Mark Rutland Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 15c6b33f0b21..01500f2a399b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -247,6 +247,7 @@ olimex OLIMEX Ltd. onion Onion Corporation onnn ON Semiconductor Corp. ontat On Tat Industrial Company +opalkelly Opal Kelly Incorporated opencores OpenCores.org option Option NV ORCL Oracle Corporation -- cgit v1.2.3 From f2f5afd3845c88e96e863ae31f6a7587906af0e6 Mon Sep 17 00:00:00 2001 From: Divagar Mohandass Date: Tue, 10 Oct 2017 11:30:35 +0530 Subject: dt-bindings: add eeprom "size" property This adds eeprom "size" as optional property for i2c eeproms. The "size" property allows explicitly specifying the size of the EEPROM chip in bytes. Acked-by: Rob Herring Reviewed-by: Sakari Ailus Signed-off-by: Divagar Mohandass Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/eeprom/eeprom.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/eeprom.txt b/Documentation/devicetree/bindings/eeprom/eeprom.txt index afc04589eadf..27f2bc15298a 100644 --- a/Documentation/devicetree/bindings/eeprom/eeprom.txt +++ b/Documentation/devicetree/bindings/eeprom/eeprom.txt @@ -36,6 +36,8 @@ Optional properties: - read-only: this parameterless property disables writes to the eeprom + - size: total eeprom size in bytes + Example: eeprom@52 { -- cgit v1.2.3 From 15e9833e22cc6e2f882639662b90eef02ef7583e Mon Sep 17 00:00:00 2001 From: Franklin S Cooper Jr Date: Mon, 11 Sep 2017 15:11:45 -0500 Subject: dt-bindings: i2c: i2c-davinci: Update binding for 66AK2Gx pwr dm property Add pm-domains property which is required for 66AK2Gx. Also document 66AK2G unique clocks property usage. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring Acked-by: Sekhar Nori Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-davinci.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt index 5b123e0e4cc2..64e6e656c345 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt @@ -6,6 +6,18 @@ davinci/keystone i2c interface contains. Required properties: - compatible: "ti,davinci-i2c" or "ti,keystone-i2c"; - reg : Offset and length of the register set for the device +- clocks: I2C functional clock phandle. + For 66AK2G this property should be set per binding, + Documentation/devicetree/bindings/clock/ti,sci-clk.txt + +SoC-specific Required Properties: + +The following are mandatory properties for Keystone 2 66AK2G SoCs only: + +- power-domains: Should contain a phandle to a PM domain provider node + and an args specifier containing the I2C device id + value. This property is as per the binding, + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt Recommended properties : - interrupts : standard interrupt property. -- cgit v1.2.3 From db6b78073ac135bb68cae77bb873371d0fe0efa6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 13 Oct 2017 15:23:55 +0300 Subject: i2c: rcar: document R8A77970 bindings R-Car V3M (R8A77970) SoC also has the R-Car gen3 compatible I2C controller, so document the SoC specific bindings. Signed-off-by: Sergei Shtylyov Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index cad39aee9f73..a777477e4547 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -13,6 +13,7 @@ Required properties: "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC. "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. + "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible device. -- cgit v1.2.3 From 0290c4ca2536a35e55c53cfb9058465b1f987b17 Mon Sep 17 00:00:00 2001 From: Frank Rowand Date: Tue, 17 Oct 2017 16:36:23 -0700 Subject: of: overlay: rename identifiers to more reflect what they do This patch is aimed primarily at drivers/of/overlay.c, but those changes also have a small impact in a few other files. overlay.c is difficult to read and maintain. Improve readability: - Rename functions, types and variables to better reflect what they do and to be consistent with names in other places, such as the device tree overlay FDT (flattened device tree), and make the algorithms more clear - Use the same names consistently throughout the file - Update comments for name changes - Fix incorrect comments This patch is intended to not introduce any functional change. Signed-off-by: Frank Rowand Signed-off-by: Rob Herring --- Documentation/devicetree/overlay-notes.txt | 12 +- drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c | 5 +- drivers/of/dynamic.c | 2 +- drivers/of/overlay.c | 530 ++++++++++++++------------- drivers/of/unittest.c | 20 +- include/linux/of.h | 12 +- 6 files changed, 310 insertions(+), 271 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt index eb7f2685fda1..c4aa0adf13ec 100644 --- a/Documentation/devicetree/overlay-notes.txt +++ b/Documentation/devicetree/overlay-notes.txt @@ -87,15 +87,15 @@ Overlay in-kernel API The API is quite easy to use. -1. Call of_overlay_create() to create and apply an overlay. The return value -is a cookie identifying this overlay. +1. Call of_overlay_apply() to create and apply an overlay changeset. The return +value is an error or a cookie identifying this overlay. -2. Call of_overlay_destroy() to remove and cleanup the overlay previously -created via the call to of_overlay_create(). Removal of an overlay that -is stacked by another will not be permitted. +2. Call of_overlay_remove() to remove and cleanup the overlay changeset +previously created via the call to of_overlay_apply(). Removal of an overlay +changeset that is stacked by another will not be permitted. Finally, if you need to remove all overlays in one-go, just call -of_overlay_destroy_all() which will remove every single one in the correct +of_overlay_remove_all() which will remove every single one in the correct order. Overlay DTS Format diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c index 623a9140493c..5f5b7ba35f1d 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c @@ -247,9 +247,10 @@ static void __init tilcdc_convert_slave_node(void) tilcdc_node_disable(slave); - ret = of_overlay_create(overlay); + ret = of_overlay_apply(overlay); if (ret) - pr_err("%s: Creating overlay failed: %d\n", __func__, ret); + pr_err("%s: Applying overlay changeset failed: %d\n", + __func__, ret); else pr_info("%s: ti,tilcdc,slave node successfully converted\n", __func__); diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c index 39e8cf731764..4bc96af4d8e2 100644 --- a/drivers/of/dynamic.c +++ b/drivers/of/dynamic.c @@ -758,7 +758,7 @@ int of_changeset_revert(struct of_changeset *ocs) EXPORT_SYMBOL_GPL(of_changeset_revert); /** - * of_changeset_action - Perform a changeset action + * of_changeset_action - Add an action to the tail of the changeset list * * @ocs: changeset pointer * @action: action to perform diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c index d3f4a5974a11..69610637af88 100644 --- a/drivers/of/overlay.c +++ b/drivers/of/overlay.c @@ -25,67 +25,63 @@ #include "of_private.h" /** - * struct of_overlay_info - Holds a single overlay info + * struct fragment - info about fragment nodes in overlay expanded device tree * @target: target of the overlay operation - * @overlay: pointer to the overlay contents node - * - * Holds a single overlay state, including all the overlay logs & - * records. + * @overlay: pointer to the __overlay__ node */ -struct of_overlay_info { +struct fragment { struct device_node *target; struct device_node *overlay; bool is_symbols_node; }; /** - * struct of_overlay - Holds a complete overlay transaction - * @node: List on which we are located - * @count: Count of ovinfo structures - * @ovinfo_tab: Overlay info table (count sized) - * @cset: Changeset to be used - * - * Holds a complete overlay transaction + * struct overlay_changeset + * @ovcs_list: list on which we are located + * @count: count of @fragments structures + * @fragments: info about fragment nodes in overlay expanded device tree + * @cset: changeset to apply fragments to live device tree */ -struct of_overlay { +struct overlay_changeset { int id; - struct list_head node; + struct list_head ovcs_list; int count; - struct of_overlay_info *ovinfo_tab; + struct fragment *fragments; struct of_changeset cset; }; -static int of_overlay_apply_one(struct of_overlay *ov, - struct device_node *target, const struct device_node *overlay, +static int build_changeset_next_level(struct overlay_changeset *ovcs, + struct device_node *target_node, + const struct device_node *overlay_node, bool is_symbols_node); -static BLOCKING_NOTIFIER_HEAD(of_overlay_chain); +static BLOCKING_NOTIFIER_HEAD(overlay_notify_chain); int of_overlay_notifier_register(struct notifier_block *nb) { - return blocking_notifier_chain_register(&of_overlay_chain, nb); + return blocking_notifier_chain_register(&overlay_notify_chain, nb); } EXPORT_SYMBOL_GPL(of_overlay_notifier_register); int of_overlay_notifier_unregister(struct notifier_block *nb) { - return blocking_notifier_chain_unregister(&of_overlay_chain, nb); + return blocking_notifier_chain_unregister(&overlay_notify_chain, nb); } EXPORT_SYMBOL_GPL(of_overlay_notifier_unregister); -static int of_overlay_notify(struct of_overlay *ov, - enum of_overlay_notify_action action) +static int overlay_notify(struct overlay_changeset *ovcs, + enum of_overlay_notify_action action) { struct of_overlay_notify_data nd; int i, ret; - for (i = 0; i < ov->count; i++) { - struct of_overlay_info *ovinfo = &ov->ovinfo_tab[i]; + for (i = 0; i < ovcs->count; i++) { + struct fragment *fragment = &ovcs->fragments[i]; - nd.target = ovinfo->target; - nd.overlay = ovinfo->overlay; + nd.target = fragment->target; + nd.overlay = fragment->overlay; - ret = blocking_notifier_call_chain(&of_overlay_chain, + ret = blocking_notifier_call_chain(&overlay_notify_chain, action, &nd); if (ret) return notifier_to_errno(ret); @@ -94,10 +90,10 @@ static int of_overlay_notify(struct of_overlay *ov, return 0; } -static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov, - const struct property *prop) +static struct property *dup_and_fixup_symbol_prop( + struct overlay_changeset *ovcs, const struct property *prop) { - struct of_overlay_info *ovinfo; + struct fragment *fragment; struct property *new; const char *overlay_name; char *label_path; @@ -116,18 +112,18 @@ static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov, if (!new) return NULL; - for (k = 0; k < ov->count; k++) { - ovinfo = &ov->ovinfo_tab[k]; - overlay_name = ovinfo->overlay->full_name; + for (k = 0; k < ovcs->count; k++) { + fragment = &ovcs->fragments[k]; + overlay_name = fragment->overlay->full_name; overlay_name_len = strlen(overlay_name); if (!strncasecmp(symbol_path, overlay_name, overlay_name_len)) break; } - if (k >= ov->count) + if (k >= ovcs->count) goto err_free; - target_path = ovinfo->target->full_name; + target_path = fragment->target->full_name; target_path_len = strlen(target_path); label_path = symbol_path + overlay_name_len; @@ -156,82 +152,119 @@ static struct property *dup_and_fixup_symbol_prop(struct of_overlay *ov, } -/* +/** + * add_changeset_property() - add @overlay_prop to overlay changeset + * @ovcs: overlay changeset + * @target_node: where to place @overlay_prop in live tree + * @overlay_prop: property to add or update, from overlay tree + * is_symbols_node: 1 if @target_node is "/__symbols__" + * + * If @overlay_prop does not already exist in @target_node, add changeset entry + * to add @overlay_prop in @target_node, else add changeset entry to update + * value of @overlay_prop. + * * Some special properties are not updated (no error returned). + * * Update of property in symbols node is not allowed. + * + * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if + * invalid @overlay. */ -static int of_overlay_apply_single_property(struct of_overlay *ov, - struct device_node *target, struct property *prop, +static int add_changeset_property(struct overlay_changeset *ovcs, + struct device_node *target_node, + struct property *overlay_prop, bool is_symbols_node) { - struct property *propn = NULL, *tprop; + struct property *new_prop = NULL, *prop; int ret = 0; - tprop = of_find_property(target, prop->name, NULL); + prop = of_find_property(target_node, overlay_prop->name, NULL); - if (!of_prop_cmp(prop->name, "name") || - !of_prop_cmp(prop->name, "phandle") || - !of_prop_cmp(prop->name, "linux,phandle")) + if (!of_prop_cmp(overlay_prop->name, "name") || + !of_prop_cmp(overlay_prop->name, "phandle") || + !of_prop_cmp(overlay_prop->name, "linux,phandle")) return 0; if (is_symbols_node) { - if (tprop) + if (prop) return -EINVAL; - propn = dup_and_fixup_symbol_prop(ov, prop); + new_prop = dup_and_fixup_symbol_prop(ovcs, overlay_prop); } else { - propn = __of_prop_dup(prop, GFP_KERNEL); + new_prop = __of_prop_dup(overlay_prop, GFP_KERNEL); } - if (!propn) + if (!new_prop) return -ENOMEM; - if (!tprop) - ret = of_changeset_add_property(&ov->cset, target, propn); + if (!prop) + ret = of_changeset_add_property(&ovcs->cset, target_node, + new_prop); else - ret = of_changeset_update_property(&ov->cset, target, propn); + ret = of_changeset_update_property(&ovcs->cset, target_node, + new_prop); if (ret) { - kfree(propn->name); - kfree(propn->value); - kfree(propn); + kfree(new_prop->name); + kfree(new_prop->value); + kfree(new_prop); } return ret; } -static int of_overlay_apply_single_device_node(struct of_overlay *ov, - struct device_node *target, struct device_node *child) +/** + * add_changeset_node() - add @node (and children) to overlay changeset + * @ovcs: overlay changeset + * @target_node: where to place @node in live tree + * @node: node from within overlay device tree fragment + * + * If @node does not already exist in @target_node, add changeset entry + * to add @node in @target_node. + * + * If @node already exists in @target_node, and the existing node has + * a phandle, the overlay node is not allowed to have a phandle. + * + * If @node has child nodes, add the children recursively via + * build_changeset_next_level(). + * + * NOTE: Multiple mods of created nodes not supported. + * + * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if + * invalid @overlay. + */ +static int add_changeset_node(struct overlay_changeset *ovcs, + struct device_node *target_node, struct device_node *node) { - const char *cname; + const char *node_kbasename; struct device_node *tchild; int ret = 0; - cname = kbasename(child->full_name); - if (!cname) + node_kbasename = kbasename(node->full_name); + if (!node_kbasename) return -ENOMEM; - for_each_child_of_node(target, tchild) - if (!of_node_cmp(cname, kbasename(tchild->full_name))) + for_each_child_of_node(target_node, tchild) + if (!of_node_cmp(node_kbasename, kbasename(tchild->full_name))) break; if (tchild) { - if (child->phandle) + if (node->phandle) return -EINVAL; - /* apply overlay recursively */ - ret = of_overlay_apply_one(ov, tchild, child, 0); + ret = build_changeset_next_level(ovcs, tchild, node, 0); of_node_put(tchild); } else { - tchild = __of_node_dup(child, "%pOF/%s", target, cname); + tchild = __of_node_dup(node, "%pOF/%s", + target_node, node_kbasename); if (!tchild) return -ENOMEM; - tchild->parent = target; + tchild->parent = target_node; - ret = of_changeset_attach_node(&ov->cset, tchild); + ret = of_changeset_attach_node(&ovcs->cset, tchild); if (ret) return ret; - ret = of_overlay_apply_one(ov, tchild, child, 0); + ret = build_changeset_next_level(ovcs, tchild, node, 0); if (ret) return ret; } @@ -239,29 +272,37 @@ static int of_overlay_apply_single_device_node(struct of_overlay *ov, return ret; } -/* - * Apply a single overlay node recursively. +/** + * build_changeset_next_level() - add level of overlay changeset + * @ovcs: overlay changeset + * @target_node: where to place @overlay_node in live tree + * @overlay_node: node from within an overlay device tree fragment + * @is_symbols_node: @overlay_node is node "/__symbols__" * - * Note that the in case of an error the target node is left - * in a inconsistent state. Error recovery should be performed - * by using the changeset. + * Add the properties (if any) and nodes (if any) from @overlay_node to the + * @ovcs->cset changeset. If an added node has child nodes, they will + * be added recursively. * * Do not allow symbols node to have any children. + * + * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if + * invalid @overlay_node. */ -static int of_overlay_apply_one(struct of_overlay *ov, - struct device_node *target, const struct device_node *overlay, +static int build_changeset_next_level(struct overlay_changeset *ovcs, + struct device_node *target_node, + const struct device_node *overlay_node, bool is_symbols_node) { struct device_node *child; struct property *prop; int ret; - for_each_property_of_node(overlay, prop) { - ret = of_overlay_apply_single_property(ov, target, prop, - is_symbols_node); + for_each_property_of_node(overlay_node, prop) { + ret = add_changeset_property(ovcs, target_node, prop, + is_symbols_node); if (ret) { pr_err("Failed to apply prop @%pOF/%s\n", - target, prop->name); + target_node, prop->name); return ret; } } @@ -269,11 +310,11 @@ static int of_overlay_apply_one(struct of_overlay *ov, if (is_symbols_node) return 0; - for_each_child_of_node(overlay, child) { - ret = of_overlay_apply_single_device_node(ov, target, child); + for_each_child_of_node(overlay_node, child) { + ret = add_changeset_node(ovcs, target_node, child); if (ret) { - pr_err("Failed to apply single node @%pOF/%s\n", - target, child->name); + pr_err("Failed to apply node @%pOF/%s\n", + target_node, child->name); of_node_put(child); return ret; } @@ -283,26 +324,30 @@ static int of_overlay_apply_one(struct of_overlay *ov, } /** - * of_overlay_apply() - Apply @count overlays pointed at by @ovinfo_tab - * @ov: Overlay to apply + * build_changeset() - populate overlay changeset in @ovcs from @ovcs->fragments + * @ovcs: Overlay changeset * - * Applies the overlays given, while handling all error conditions - * appropriately. Either the operation succeeds, or if it fails the - * live tree is reverted to the state before the attempt. - * Returns 0, or an error if the overlay attempt failed. + * Create changeset @ovcs->cset to contain the nodes and properties of the + * overlay device tree fragments in @ovcs->fragments[]. If an error occurs, + * any portions of the changeset that were successfully created will remain + * in @ovcs->cset. + * + * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if + * invalid overlay in @ovcs->fragments[]. */ -static int of_overlay_apply(struct of_overlay *ov) +static int build_changeset(struct overlay_changeset *ovcs) { - int i, err; + int i, ret; - for (i = 0; i < ov->count; i++) { - struct of_overlay_info *ovinfo = &ov->ovinfo_tab[i]; + for (i = 0; i < ovcs->count; i++) { + struct fragment *fragment = &ovcs->fragments[i]; - err = of_overlay_apply_one(ov, ovinfo->target, ovinfo->overlay, - ovinfo->is_symbols_node); - if (err) { - pr_err("apply failed '%pOF'\n", ovinfo->target); - return err; + ret = build_changeset_next_level(ovcs, fragment->target, + fragment->overlay, + fragment->is_symbols_node); + if (ret) { + pr_err("apply failed '%pOF'\n", fragment->target); + return ret; } } @@ -350,45 +395,46 @@ static struct device_node *find_target_node(struct device_node *info_node) * * Returns 0 on success, or a negative error value. */ -static int of_fill_overlay_info(struct of_overlay *ov, - struct device_node *info_node, struct of_overlay_info *ovinfo) +static int of_fill_overlay_info(struct overlay_changeset *ovcset, + struct device_node *info_node, struct fragment *fragment) { - ovinfo->overlay = of_get_child_by_name(info_node, "__overlay__"); - if (!ovinfo->overlay) + fragment->overlay = of_get_child_by_name(info_node, "__overlay__"); + if (!fragment->overlay) goto err_fail; - ovinfo->target = find_target_node(info_node); - if (!ovinfo->target) + fragment->target = find_target_node(info_node); + if (!fragment->target) goto err_fail; return 0; err_fail: - of_node_put(ovinfo->target); - of_node_put(ovinfo->overlay); + of_node_put(fragment->target); + of_node_put(fragment->overlay); - memset(ovinfo, 0, sizeof(*ovinfo)); + memset(fragment, 0, sizeof(*fragment)); return -EINVAL; } /** - * of_build_overlay_info() - Build an overlay info array - * @ov Overlay to build - * @tree: Device node containing all the overlays + * init_overlay_changeset() - initialize overlay changeset from overlay tree + * @ovcs Overlay changeset to build + * @tree: Contains all the overlay fragments and overlay fixup nodes * - * Helper function that given a tree containing overlay information, - * allocates and builds an overlay info array containing it, ready - * for use using of_overlay_apply. + * Initialize @ovcs. Populate @ovcs->fragments with node information from + * the top level of @tree. The relevant top level nodes are the fragment + * nodes and the __symbols__ node. Any other top level node will be ignored. * - * Returns 0 on success with the @cntp @ovinfop pointers valid, - * while on error a negative error value is returned. + * Returns 0 on success, -ENOMEM if memory allocation failure, -EINVAL if error + * detected in @tree, or -ENODEV if no valid nodes found. */ -static int of_build_overlay_info(struct of_overlay *ov, +static int init_overlay_changeset(struct overlay_changeset *ovcs, struct device_node *tree) { struct device_node *node; - struct of_overlay_info *ovinfo; - int cnt, err; + struct fragment *fragment; + struct fragment *fragments; + int cnt, ret; cnt = 0; for_each_child_of_node(tree, node) @@ -397,24 +443,25 @@ static int of_build_overlay_info(struct of_overlay *ov, if (of_get_child_by_name(tree, "__symbols__")) cnt++; - ovinfo = kcalloc(cnt, sizeof(*ovinfo), GFP_KERNEL); - if (!ovinfo) + fragments = kcalloc(cnt, sizeof(*fragments), GFP_KERNEL); + if (!fragments) return -ENOMEM; cnt = 0; for_each_child_of_node(tree, node) { - err = of_fill_overlay_info(ov, node, &ovinfo[cnt]); - if (!err) + ret = of_fill_overlay_info(ovcs, node, &fragments[cnt]); + if (!ret) cnt++; } node = of_get_child_by_name(tree, "__symbols__"); if (node) { - ovinfo[cnt].overlay = node; - ovinfo[cnt].target = of_find_node_by_path("/__symbols__"); - ovinfo[cnt].is_symbols_node = 1; + fragment = &fragments[cnt]; + fragment->overlay = node; + fragment->target = of_find_node_by_path("/__symbols__"); + fragment->is_symbols_node = 1; - if (!ovinfo[cnt].target) { + if (!fragment->target) { pr_err("no symbols in root of device tree.\n"); return -EINVAL; } @@ -423,137 +470,127 @@ static int of_build_overlay_info(struct of_overlay *ov, } if (!cnt) { - kfree(ovinfo); + kfree(fragments); return -ENODEV; } - ov->count = cnt; - ov->ovinfo_tab = ovinfo; + ovcs->count = cnt; + ovcs->fragments = fragments; return 0; } /** - * of_free_overlay_info() - Free an overlay info array - * @ov Overlay to free the overlay info from - * @ovinfo_tab: Array of overlay_info's to free + * free_overlay_fragments() - Free a fragments array + * @ovcs Overlay to free the overlay info from * - * Releases the memory of a previously allocated ovinfo array - * by of_build_overlay_info. - * Returns 0, or an error if the arguments are bogus. + * Frees the memory of an ovcs->fragments[] array. */ -static int of_free_overlay_info(struct of_overlay *ov) +static void free_overlay_fragments(struct overlay_changeset *ovcs) { - struct of_overlay_info *ovinfo; int i; /* do it in reverse */ - for (i = ov->count - 1; i >= 0; i--) { - ovinfo = &ov->ovinfo_tab[i]; - - of_node_put(ovinfo->target); - of_node_put(ovinfo->overlay); + for (i = ovcs->count - 1; i >= 0; i--) { + of_node_put(ovcs->fragments[i].target); + of_node_put(ovcs->fragments[i].overlay); } - kfree(ov->ovinfo_tab); - return 0; + kfree(ovcs->fragments); } -static LIST_HEAD(ov_list); -static DEFINE_IDR(ov_idr); +static LIST_HEAD(ovcs_list); +static DEFINE_IDR(ovcs_idr); /** - * of_overlay_create() - Create and apply an overlay - * @tree: Device node containing all the overlays + * of_overlay_apply() - Create and apply an overlay changeset + * @tree: Expanded overlay device tree * - * Creates and applies an overlay while also keeping track - * of the overlay in a list. This list can be used to prevent - * illegal overlay removals. + * Creates and applies an overlay changeset. If successful, the overlay + * changeset is added to the overlay changeset list. * - * Returns the id of the created overlay, or a negative error number + * Returns the id of the created overlay changeset, or a negative error number */ -int of_overlay_create(struct device_node *tree) +int of_overlay_apply(struct device_node *tree) { - struct of_overlay *ov; - int err, id; + struct overlay_changeset *ovcs; + int id, ret; - ov = kzalloc(sizeof(*ov), GFP_KERNEL); - if (!ov) + ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL); + if (!ovcs) return -ENOMEM; - ov->id = -1; + ovcs->id = -1; - INIT_LIST_HEAD(&ov->node); + INIT_LIST_HEAD(&ovcs->ovcs_list); - of_changeset_init(&ov->cset); + of_changeset_init(&ovcs->cset); mutex_lock(&of_mutex); - id = idr_alloc(&ov_idr, ov, 0, 0, GFP_KERNEL); + id = idr_alloc(&ovcs_idr, ovcs, 0, 0, GFP_KERNEL); if (id < 0) { - err = id; + ret = id; goto err_destroy_trans; } - ov->id = id; + ovcs->id = id; - err = of_build_overlay_info(ov, tree); - if (err) { - pr_err("of_build_overlay_info() failed for tree@%pOF\n", + ret = init_overlay_changeset(ovcs, tree); + if (ret) { + pr_err("init_overlay_changeset() failed for tree@%pOF\n", tree); goto err_free_idr; } - err = of_overlay_notify(ov, OF_OVERLAY_PRE_APPLY); - if (err < 0) { - pr_err("%s: Pre-apply notifier failed (err=%d)\n", - __func__, err); - goto err_free_idr; + ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY); + if (ret < 0) { + pr_err("%s: Pre-apply notifier failed (ret=%d)\n", + __func__, ret); + goto err_free_overlay_fragments; } - err = of_overlay_apply(ov); - if (err) - goto err_abort_trans; - - err = __of_changeset_apply(&ov->cset); - if (err) - goto err_revert_overlay; + ret = build_changeset(ovcs); + if (ret) + goto err_free_overlay_fragments; + ret = __of_changeset_apply(&ovcs->cset); + if (ret) + goto err_free_overlay_fragments; - list_add_tail(&ov->node, &ov_list); + list_add_tail(&ovcs->ovcs_list, &ovcs_list); - of_overlay_notify(ov, OF_OVERLAY_POST_APPLY); + overlay_notify(ovcs, OF_OVERLAY_POST_APPLY); mutex_unlock(&of_mutex); return id; -err_revert_overlay: -err_abort_trans: - of_free_overlay_info(ov); +err_free_overlay_fragments: + free_overlay_fragments(ovcs); err_free_idr: - idr_remove(&ov_idr, ov->id); + idr_remove(&ovcs_idr, ovcs->id); err_destroy_trans: - of_changeset_destroy(&ov->cset); - kfree(ov); + of_changeset_destroy(&ovcs->cset); + kfree(ovcs); mutex_unlock(&of_mutex); - return err; + return ret; } -EXPORT_SYMBOL_GPL(of_overlay_create); +EXPORT_SYMBOL_GPL(of_overlay_apply); /* - * check whether the given node, lies under the given tree - * return 1 if under tree, else 0 + * Find @np in @tree. + * + * Returns 1 if @np is @tree or is contained in @tree, else 0 */ -static int overlay_subtree_check(struct device_node *tree, - struct device_node *dn) +static int find_node(struct device_node *tree, struct device_node *np) { struct device_node *child; - if (tree == dn) + if (tree == np) return 1; for_each_child_of_node(tree, child) { - if (overlay_subtree_check(child, dn)) { + if (find_node(child, np)) { of_node_put(child); return 1; } @@ -563,30 +600,32 @@ static int overlay_subtree_check(struct device_node *tree, } /* - * check whether this overlay is the topmost - * return 1 if topmost, else 0 + * Is @remove_ce_np a child of or the same as any + * node in an overlay changeset more topmost than @remove_ovcs? + * + * Returns 1 if found, else 0 */ -static int overlay_is_topmost(struct of_overlay *ov, struct device_node *dn) +static int node_in_later_cs(struct overlay_changeset *remove_ovcs, + struct device_node *remove_ce_np) { - struct of_overlay *ovt; + struct overlay_changeset *ovcs; struct of_changeset_entry *ce; - list_for_each_entry_reverse(ovt, &ov_list, node) { - /* if we hit ourselves, we're done */ - if (ovt == ov) + list_for_each_entry_reverse(ovcs, &ovcs_list, ovcs_list) { + if (ovcs == remove_ovcs) break; - /* check against each subtree affected by this overlay */ - list_for_each_entry(ce, &ovt->cset.entries, node) { - if (overlay_subtree_check(ce->np, dn)) { + list_for_each_entry(ce, &ovcs->cset.entries, node) { + if (find_node(ce->np, remove_ce_np)) { pr_err("%s: #%d clashes #%d @%pOF\n", - __func__, ov->id, ovt->id, dn); - return 0; + __func__, remove_ovcs->id, ovcs->id, + remove_ce_np); + return 1; } } } - return 1; + return 0; } /* @@ -599,13 +638,13 @@ static int overlay_is_topmost(struct of_overlay *ov, struct device_node *dn) * the one closest to the tail. If another overlay has affected this * device node and is closest to the tail, then removal is not permited. */ -static int overlay_removal_is_ok(struct of_overlay *ov) +static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs) { - struct of_changeset_entry *ce; + struct of_changeset_entry *remove_ce; - list_for_each_entry(ce, &ov->cset.entries, node) { - if (!overlay_is_topmost(ov, ce->np)) { - pr_err("overlay #%d is not topmost\n", ov->id); + list_for_each_entry(remove_ce, &remove_ovcs->cset.entries, node) { + if (node_in_later_cs(remove_ovcs, remove_ce->np)) { + pr_err("overlay #%d is not topmost\n", remove_ovcs->id); return 0; } } @@ -614,74 +653,73 @@ static int overlay_removal_is_ok(struct of_overlay *ov) } /** - * of_overlay_destroy() - Removes an overlay - * @id: Overlay id number returned by a previous call to of_overlay_create + * of_overlay_remove() - Revert and free an overlay changeset + * @ovcs_id: Overlay changeset id number * - * Removes an overlay if it is permissible. + * Removes an overlay if it is permissible. ovcs_id was previously returned + * by of_overlay_apply(). * * Returns 0 on success, or a negative error number */ -int of_overlay_destroy(int id) +int of_overlay_remove(int ovcs_id) { - struct of_overlay *ov; - int err; + struct overlay_changeset *ovcs; + int ret = 0; mutex_lock(&of_mutex); - ov = idr_find(&ov_idr, id); - if (!ov) { - err = -ENODEV; - pr_err("destroy: Could not find overlay #%d\n", id); + ovcs = idr_find(&ovcs_idr, ovcs_id); + if (!ovcs) { + ret = -ENODEV; + pr_err("remove: Could not find overlay #%d\n", ovcs_id); goto out; } - if (!overlay_removal_is_ok(ov)) { - err = -EBUSY; + if (!overlay_removal_is_ok(ovcs)) { + ret = -EBUSY; goto out; } - of_overlay_notify(ov, OF_OVERLAY_PRE_REMOVE); - list_del(&ov->node); - __of_changeset_revert(&ov->cset); - of_overlay_notify(ov, OF_OVERLAY_POST_REMOVE); - of_free_overlay_info(ov); - idr_remove(&ov_idr, id); - of_changeset_destroy(&ov->cset); - kfree(ov); - - err = 0; + overlay_notify(ovcs, OF_OVERLAY_PRE_REMOVE); + list_del(&ovcs->ovcs_list); + __of_changeset_revert(&ovcs->cset); + overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE); + free_overlay_fragments(ovcs); + idr_remove(&ovcs_idr, ovcs_id); + of_changeset_destroy(&ovcs->cset); + kfree(ovcs); out: mutex_unlock(&of_mutex); - return err; + return ret; } -EXPORT_SYMBOL_GPL(of_overlay_destroy); +EXPORT_SYMBOL_GPL(of_overlay_remove); /** - * of_overlay_destroy_all() - Removes all overlays from the system + * of_overlay_remove_all() - Reverts and frees all overlay changesets * * Removes all overlays from the system in the correct order. * * Returns 0 on success, or a negative error number */ -int of_overlay_destroy_all(void) +int of_overlay_remove_all(void) { - struct of_overlay *ov, *ovn; + struct overlay_changeset *ovcs, *ovcs_n; mutex_lock(&of_mutex); /* the tail of list is guaranteed to be safe to remove */ - list_for_each_entry_safe_reverse(ov, ovn, &ov_list, node) { - list_del(&ov->node); - __of_changeset_revert(&ov->cset); - of_free_overlay_info(ov); - idr_remove(&ov_idr, ov->id); - kfree(ov); + list_for_each_entry_safe_reverse(ovcs, ovcs_n, &ovcs_list, ovcs_list) { + list_del(&ovcs->ovcs_list); + __of_changeset_revert(&ovcs->cset); + free_overlay_fragments(ovcs); + idr_remove(&ovcs_idr, ovcs->id); + kfree(ovcs); } mutex_unlock(&of_mutex); return 0; } -EXPORT_SYMBOL_GPL(of_overlay_destroy_all); +EXPORT_SYMBOL_GPL(of_overlay_remove_all); diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index add02cfbfb88..bbdaf5606820 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -1230,7 +1230,7 @@ static void of_unittest_destroy_tracked_overlays(void) if (!(overlay_id_bits[BIT_WORD(id)] & BIT_MASK(id))) continue; - ret = of_overlay_destroy(id + overlay_first_id); + ret = of_overlay_remove(id + overlay_first_id); if (ret == -ENODEV) { pr_warn("%s: no overlay to destroy for #%d\n", __func__, id + overlay_first_id); @@ -1262,7 +1262,7 @@ static int of_unittest_apply_overlay(int overlay_nr, int unittest_nr, goto out; } - ret = of_overlay_create(np); + ret = of_overlay_apply(np); if (ret < 0) { unittest(0, "could not create overlay from \"%s\"\n", overlay_path(overlay_nr)); @@ -1347,7 +1347,7 @@ static int of_unittest_apply_revert_overlay_check(int overlay_nr, return -EINVAL; } - ret = of_overlay_destroy(ov_id); + ret = of_overlay_remove(ov_id); if (ret != 0) { unittest(0, "overlay @\"%s\" failed to be destroyed @\"%s\"\n", overlay_path(overlay_nr), @@ -1476,7 +1476,7 @@ static void of_unittest_overlay_6(void) return; } - ret = of_overlay_create(np); + ret = of_overlay_apply(np); if (ret < 0) { unittest(0, "could not create overlay from \"%s\"\n", overlay_path(overlay_nr + i)); @@ -1500,7 +1500,7 @@ static void of_unittest_overlay_6(void) } for (i = 1; i >= 0; i--) { - ret = of_overlay_destroy(ov_id[i]); + ret = of_overlay_remove(ov_id[i]); if (ret != 0) { unittest(0, "overlay @\"%s\" failed destroy @\"%s\"\n", overlay_path(overlay_nr + i), @@ -1546,7 +1546,7 @@ static void of_unittest_overlay_8(void) return; } - ret = of_overlay_create(np); + ret = of_overlay_apply(np); if (ret < 0) { unittest(0, "could not create overlay from \"%s\"\n", overlay_path(overlay_nr + i)); @@ -1557,7 +1557,7 @@ static void of_unittest_overlay_8(void) } /* now try to remove first overlay (it should fail) */ - ret = of_overlay_destroy(ov_id[0]); + ret = of_overlay_remove(ov_id[0]); if (ret == 0) { unittest(0, "overlay @\"%s\" was destroyed @\"%s\"\n", overlay_path(overlay_nr + 0), @@ -1568,7 +1568,7 @@ static void of_unittest_overlay_8(void) /* removing them in order should work */ for (i = 1; i >= 0; i--) { - ret = of_overlay_destroy(ov_id[i]); + ret = of_overlay_remove(ov_id[i]); if (ret != 0) { unittest(0, "overlay @\"%s\" not destroyed @\"%s\"\n", overlay_path(overlay_nr + i), @@ -2149,9 +2149,9 @@ static int __init overlay_data_add(int onum) goto out_free_np_overlay; } - ret = of_overlay_create(info->np_overlay); + ret = of_overlay_apply(info->np_overlay); if (ret < 0) { - pr_err("of_overlay_create() (ret=%d), %d\n", ret, onum); + pr_err("of_overlay_apply() (ret=%d), %d\n", ret, onum); goto out_free_np_overlay; } else { info->overlay_id = ret; diff --git a/include/linux/of.h b/include/linux/of.h index 7b0f17be7830..7569e9cc45de 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1312,26 +1312,26 @@ struct of_overlay_notify_data { #ifdef CONFIG_OF_OVERLAY /* ID based overlays; the API for external users */ -int of_overlay_create(struct device_node *tree); -int of_overlay_destroy(int id); -int of_overlay_destroy_all(void); +int of_overlay_apply(struct device_node *tree); +int of_overlay_remove(int id); +int of_overlay_remove_all(void); int of_overlay_notifier_register(struct notifier_block *nb); int of_overlay_notifier_unregister(struct notifier_block *nb); #else -static inline int of_overlay_create(struct device_node *tree) +static inline int of_overlay_apply(struct device_node *tree) { return -ENOTSUPP; } -static inline int of_overlay_destroy(int id) +static inline int of_overlay_remove(int id) { return -ENOTSUPP; } -static inline int of_overlay_destroy_all(void) +static inline int of_overlay_remove_all(void) { return -ENOTSUPP; } -- cgit v1.2.3 From 4b8b77a4ec807a5f14e02e84b1bb7a2fd43768c0 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 22 Sep 2016 11:48:19 +0100 Subject: dt-bindings: Document devicetree binding for ARM SPE This patch documents the devicetree binding in use for ARM SPE. Cc: Rob Herring Acked-by: Mark Rutland Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/arm/spe-pmu.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/spe-pmu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt new file mode 100644 index 000000000000..93372f2a7df9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -0,0 +1,20 @@ +* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU) + +ARMv8.2 introduces the optional Statistical Profiling Extension for collecting +performance sample data using an in-memory trace buffer. + +** SPE Required properties: + +- compatible : should be one of: + "arm,statistical-profiling-extension-v1" + +- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where + SPE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + +** Example: + +spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; +}; -- cgit v1.2.3 From 904fb8e452b4a95490357841291fa523ad1d6442 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Wed, 27 Sep 2017 17:28:34 +0530 Subject: dt-bindings: pci: tegra: Document Tegra186 PCIe DT Tegra186 PCIe controller DT properties has couple of differences wrt Tegra210 PCIe, rest of the DT properties are same. Tested-by: Mikko Perttunen Signed-off-by: Manikanta Maddireddy Signed-off-by: Bjorn Helgaas Reviewed-by: Mikko Perttunen Acked-by: Thierry Reding --- .../bindings/pci/nvidia,tegra20-pcie.txt | 134 ++++++++++++++++++++- 1 file changed, 130 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 982a74ea6df9..33d2e2139333 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -1,10 +1,15 @@ NVIDIA Tegra PCIe controller Required properties: -- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30, - "nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie". - Otherwise, must contain "nvidia,-pcie", plus one of the above, where - is tegra132 or tegra210. +- compatible: Must be: + - "nvidia,tegra20-pcie": for Tegra20 + - "nvidia,tegra30-pcie": for Tegra30 + - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 + - "nvidia,tegra210-pcie": for Tegra210 + - "nvidia,tegra186-pcie": for Tegra186 +- power-domains: To ungate power partition by BPMP powergate driver. Must + contain BPMP phandle and PCIe power partition ID. This is required only + for Tegra186. - device_type: Must be "pci" - reg: A list of physical base address and length for each set of controller registers. Must contain an entry for each entry in the reg-names property. @@ -124,6 +129,16 @@ Power supplies for Tegra210: - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must supply 1.8 V. +Power supplies for Tegra186: +- Required: + - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must + supply 1.8 V. + - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. + Must supply 1.8 V. + - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must + supply 1.8 V. + Root ports are defined as subnodes of the PCIe controller node. Required properties: @@ -546,3 +561,114 @@ Board DTS: status = "okay"; }; }; + +Tegra186: +--------- + +SoC DTSI: + + pcie@10003000 { + compatible = "nvidia,tegra186-pcie"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; + device_type = "pci"; + reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ + 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + + clocks = <&bpmp TEGRA186_CLK_AFI>, + <&bpmp TEGRA186_CLK_PCIE>, + <&bpmp TEGRA186_CLK_PLLE>; + clock-names = "afi", "pex", "pll_e"; + + resets = <&bpmp TEGRA186_RESET_AFI>, + <&bpmp TEGRA186_RESET_PCIE>, + <&bpmp TEGRA186_RESET_PCIEXCLK>; + reset-names = "afi", "pex", "pcie_x"; + + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + +Board DTS: + + pcie@10003000 { + status = "okay"; + + dvdd-pex-supply = <&vdd_pex>; + hvdd-pex-pll-supply = <&vdd_1v8>; + hvdd-pex-supply = <&vdd_1v8>; + vddio-pexctl-aud-supply = <&vdd_1v8>; + + pci@1,0 { + nvidia,num-lanes = <4>; + status = "okay"; + }; + + pci@2,0 { + nvidia,num-lanes = <0>; + status = "disabled"; + }; + + pci@3,0 { + nvidia,num-lanes = <1>; + status = "disabled"; + }; + }; -- cgit v1.2.3 From 0f38672c629b79fa2b929d2c391bc063a08279eb Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 3 Oct 2017 20:09:14 +0900 Subject: usb: renesas_usbhs: add support for R-Car D3 This patch adds support for R-Car D3. This SoC needs to release the PLL reset by the UGCTRL register. So, since this is not the same as other R-Car Gen3 SoCs, this patch adds a new type as "USBHS_TYPE_RCAR_GEN3_WITH_PLL". Acked-by: Rob Herring Signed-off-by: Yoshihiro Shimoda Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/renesas_usbhs.txt | 1 + drivers/usb/renesas_usbhs/common.c | 10 ++++- drivers/usb/renesas_usbhs/rcar3.c | 48 ++++++++++++++++++++++ drivers/usb/renesas_usbhs/rcar3.h | 1 + include/linux/usb/renesas_usbhs.h | 5 ++- 5 files changed, 62 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index 9e18e000339e..e79f6e43061a 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -10,6 +10,7 @@ Required properties: - "renesas,usbhs-r8a7794" for r8a7794 (R-Car E2) compatible device - "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device - "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device + - "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device - "renesas,rcar-gen2-usbhs" for R-Car Gen2 compatible device - "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c index 2a860e496b4f..3e92a784c5c3 100644 --- a/drivers/usb/renesas_usbhs/common.c +++ b/drivers/usb/renesas_usbhs/common.c @@ -485,6 +485,10 @@ static const struct of_device_id usbhs_of_match[] = { .compatible = "renesas,usbhs-r8a7796", .data = (void *)USBHS_TYPE_RCAR_GEN3, }, + { + .compatible = "renesas,usbhs-r8a77995", + .data = (void *)USBHS_TYPE_RCAR_GEN3_WITH_PLL, + }, { .compatible = "renesas,rcar-gen2-usbhs", .data = (void *)USBHS_TYPE_RCAR_GEN2, @@ -519,7 +523,8 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev) dparam->enable_gpio = gpio; if (dparam->type == USBHS_TYPE_RCAR_GEN2 || - dparam->type == USBHS_TYPE_RCAR_GEN3) { + dparam->type == USBHS_TYPE_RCAR_GEN3 || + dparam->type == USBHS_TYPE_RCAR_GEN3_WITH_PLL) { dparam->has_usb_dmac = 1; dparam->pipe_configs = usbhsc_new_pipe; dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe); @@ -584,6 +589,9 @@ static int usbhs_probe(struct platform_device *pdev) case USBHS_TYPE_RCAR_GEN3: priv->pfunc = usbhs_rcar3_ops; break; + case USBHS_TYPE_RCAR_GEN3_WITH_PLL: + priv->pfunc = usbhs_rcar3_with_pll_ops; + break; default: if (!info->platform_callback.get_id) { dev_err(&pdev->dev, "no platform callbacks"); diff --git a/drivers/usb/renesas_usbhs/rcar3.c b/drivers/usb/renesas_usbhs/rcar3.c index 02b67abfc2a1..f436e9d51127 100644 --- a/drivers/usb/renesas_usbhs/rcar3.c +++ b/drivers/usb/renesas_usbhs/rcar3.c @@ -15,24 +15,39 @@ #include "rcar3.h" #define LPSTS 0x102 +#define UGCTRL 0x180 /* 32-bit register */ #define UGCTRL2 0x184 /* 32-bit register */ +#define UGSTS 0x188 /* 32-bit register */ /* Low Power Status register (LPSTS) */ #define LPSTS_SUSPM 0x4000 +/* R-Car D3 only: USB General control register (UGCTRL) */ +#define UGCTRL_PLLRESET 0x00000001 +#define UGCTRL_CONNECT 0x00000004 + /* * USB General control register 2 (UGCTRL2) * Remarks: bit[31:11] and bit[9:6] should be 0 */ #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */ +#define UGCTRL2_USB0SEL_HSUSB 0x00000020 #define UGCTRL2_USB0SEL_OTG 0x00000030 #define UGCTRL2_VBUSSEL 0x00000400 +/* R-Car D3 only: USB General status register (UGSTS) */ +#define UGSTS_LOCK 0x00000100 + static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data) { iowrite32(data, priv->base + reg); } +static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg) +{ + return ioread32(priv->base + reg); +} + static int usbhs_rcar3_power_ctrl(struct platform_device *pdev, void __iomem *base, int enable) { @@ -52,6 +67,34 @@ static int usbhs_rcar3_power_ctrl(struct platform_device *pdev, return 0; } +/* R-Car D3 needs to release UGCTRL.PLLRESET */ +static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev, + void __iomem *base, int enable) +{ + struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev); + u32 val; + int timeout = 1000; + + if (enable) { + usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */ + usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | + UGCTRL2_USB0SEL_HSUSB); + + usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM); + do { + val = usbhs_read32(priv, UGSTS); + udelay(1); + } while (!(val & UGSTS_LOCK) && timeout--); + usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT); + } else { + usbhs_write32(priv, UGCTRL, 0); + usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0); + usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET); + } + + return 0; +} + static int usbhs_rcar3_get_id(struct platform_device *pdev) { return USBHS_GADGET; @@ -61,3 +104,8 @@ const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = { .power_ctrl = usbhs_rcar3_power_ctrl, .get_id = usbhs_rcar3_get_id, }; + +const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = { + .power_ctrl = usbhs_rcar3_power_and_pll_ctrl, + .get_id = usbhs_rcar3_get_id, +}; diff --git a/drivers/usb/renesas_usbhs/rcar3.h b/drivers/usb/renesas_usbhs/rcar3.h index 5f850b23ff18..7fe98175f94f 100644 --- a/drivers/usb/renesas_usbhs/rcar3.h +++ b/drivers/usb/renesas_usbhs/rcar3.h @@ -1,3 +1,4 @@ #include "common.h" extern const struct renesas_usbhs_platform_callback usbhs_rcar3_ops; +extern const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops; diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h index 00a47d058d83..d2f41e4dd7a8 100644 --- a/include/linux/usb/renesas_usbhs.h +++ b/include/linux/usb/renesas_usbhs.h @@ -183,8 +183,9 @@ struct renesas_usbhs_driver_param { #define USBHS_USB_DMAC_XFER_SIZE 32 /* hardcode the xfer size */ }; -#define USBHS_TYPE_RCAR_GEN2 1 -#define USBHS_TYPE_RCAR_GEN3 2 +#define USBHS_TYPE_RCAR_GEN2 1 +#define USBHS_TYPE_RCAR_GEN3 2 +#define USBHS_TYPE_RCAR_GEN3_WITH_PLL 3 /* * option: -- cgit v1.2.3 From 279d4bc6406022461713cd6a3e5411336d2ff26b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 29 Sep 2017 20:45:01 +0900 Subject: usb: gadget: udc: renesas_usb3: add support for generic phy This patch adds support for generic phy as an optional. If you want to use a generic phy (e.g. phy-rcar-gen3-usb3 driver) on this driver, you have to do "insmod phy-rcar-gen3-usb3.ko" first for now. Acked-by: Rob Herring Signed-off-by: Yoshihiro Shimoda Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/renesas_usb3.txt | 4 ++++ drivers/usb/gadget/udc/renesas_usb3.c | 26 ++++++++++++++++++++-- 2 files changed, 28 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas_usb3.txt b/Documentation/devicetree/bindings/usb/renesas_usb3.txt index e28025883b79..87a45e2f9b7f 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usb3.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usb3.txt @@ -15,6 +15,10 @@ Required properties: - interrupts: Interrupt specifier for the USB3.0 Peripheral - clocks: clock phandle and specifier pair +Optional properties: + - phys: phandle + phy specifier pair + - phy-names: must be "usb" + Example of R-Car H3 ES1.x: usb3_peri0: usb@ee020000 { compatible = "renesas,r8a7795-usb3-peri", diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c index 75afc4c4bbd8..0cbf909182a2 100644 --- a/drivers/usb/gadget/udc/renesas_usb3.c +++ b/drivers/usb/gadget/udc/renesas_usb3.c @@ -1,7 +1,7 @@ /* * Renesas USB3.0 Peripheral driver (USB gadget) * - * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015-2017 Renesas Electronics Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -334,6 +335,7 @@ struct renesas_usb3 { struct usb_gadget_driver *driver; struct extcon_dev *extcon; struct work_struct extcon_work; + struct phy *phy; struct renesas_usb3_ep *usb3_ep; int num_usb3_eps; @@ -2239,6 +2241,9 @@ static int renesas_usb3_start(struct usb_gadget *gadget, /* hook up the driver */ usb3->driver = driver; + if (usb3->phy) + phy_init(usb3->phy); + pm_runtime_get_sync(usb3_to_dev(usb3)); renesas_usb3_init_controller(usb3); @@ -2255,6 +2260,9 @@ static int renesas_usb3_stop(struct usb_gadget *gadget) usb3->driver = NULL; renesas_usb3_stop_controller(usb3); + if (usb3->phy) + phy_exit(usb3->phy); + pm_runtime_put(usb3_to_dev(usb3)); return 0; @@ -2403,6 +2411,8 @@ static int renesas_usb3_remove(struct platform_device *pdev) renesas_usb3_dma_free_prd(usb3, &pdev->dev); __renesas_usb3_ep_free_request(usb3->ep0_req); + if (usb3->phy) + phy_put(usb3->phy); pm_runtime_disable(usb3_to_dev(usb3)); return 0; @@ -2634,11 +2644,19 @@ static int renesas_usb3_probe(struct platform_device *pdev) if (ret < 0) goto err_dev_create; + /* + * This is an optional. So, if this driver cannot get a phy, + * this driver will not handle a phy anymore. + */ + usb3->phy = devm_phy_get(&pdev->dev, "usb"); + if (IS_ERR(usb3->phy)) + usb3->phy = NULL; + usb3->workaround_for_vbus = priv->workaround_for_vbus; renesas_usb3_debugfs_init(usb3, &pdev->dev); - dev_info(&pdev->dev, "probed\n"); + dev_info(&pdev->dev, "probed%s\n", usb3->phy ? " with phy" : ""); pm_runtime_enable(usb3_to_dev(usb3)); return 0; @@ -2665,6 +2683,8 @@ static int renesas_usb3_suspend(struct device *dev) return 0; renesas_usb3_stop_controller(usb3); + if (usb3->phy) + phy_exit(usb3->phy); pm_runtime_put(dev); return 0; @@ -2678,6 +2698,8 @@ static int renesas_usb3_resume(struct device *dev) if (!usb3->driver) return 0; + if (usb3->phy) + phy_init(usb3->phy); pm_runtime_get_sync(dev); renesas_usb3_init_controller(usb3); -- cgit v1.2.3 From 000777dadc7e22d3656bc9f30dde2ba40d069a2f Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Thu, 17 Aug 2017 11:33:00 +0200 Subject: dt-bindings: usb: Document the STM32F7xx DWC2 USB OTG HS core binding This patch adds binding documentation for DWC2 controller in HS mode found on STMicroelectronics STM32F7xx SoC. Signed-off-by: Amelie Delaunay Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index fcf199b64d3d..e64d903bcbe8 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -19,6 +19,8 @@ Required properties: configured in FS mode; - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs configured in HS mode; + - "st,stm32f7xx-hsotg": The DWC2 USB HS controller instance in STM32F7xx SoCs + configured in HS mode; - reg : Should contain 1 register range (address and length) - interrupts : Should contain 1 interrupt - clocks: clock provider specifier -- cgit v1.2.3 From 85a299d52766a60d3a1ce0dc168646656060fc89 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 13 Oct 2017 17:10:47 +0800 Subject: dt-bindings: usb: mtu3: add a optional property to disable u3ports Add a new optional property to disable u3ports Signed-off-by: Chunfeng Yun Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt index 49f54767cd21..7c611d14a0a0 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt @@ -44,6 +44,8 @@ Optional properties: - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup control register, it depends on "mediatek,enable-wakeup". + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, + bit1 for u3port1, ... etc; Sub-nodes: The xhci should be added as subnode to mtu3 as shown in the following example -- cgit v1.2.3 From fc3a41aa696ca588cde95ae348bce999bf08f234 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 13 Oct 2017 17:10:48 +0800 Subject: dt-bindings: usb: mtu3: remove dummy clocks and add optional ones Remove dummy clocks for usb wakeup and add optional ones for mcu_bus and dma_bus bus. Signed-off-by: Chunfeng Yun Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt index 7c611d14a0a0..49c982bb5bfc 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt @@ -14,9 +14,9 @@ Required properties: - vusb33-supply : regulator of USB avdd3.3v - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller; - "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are - depends on "mediatek,enable-wakeup" + - clock-names : must contain "sys_ck" for clock of controller, + the following clocks are optional: + "ref_ck", "mcu_ck" and "dam_ck"; - phys : a list of phandle + phy specifier pairs - dr_mode : should be one of "host", "peripheral" or "otg", refer to usb/generic.txt @@ -65,9 +65,7 @@ ssusb: usb@11271000 { clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, <&pericfg CLK_PERI_USB0>, <&pericfg CLK_PERI_USB1>; - clock-names = "sys_ck", "ref_ck", - "wakeup_deb_p0", - "wakeup_deb_p1"; + clock-names = "sys_ck", "ref_ck"; vusb33-supply = <&mt6397_vusb_reg>; vbus-supply = <&usb_p0_vbus>; extcon = <&extcon_usb>; -- cgit v1.2.3 From 32428aa22d08a1be660b571a0f71880e5a9dd926 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 13 Oct 2017 17:10:49 +0800 Subject: dt-bindings: usb: mtu3: remove optional pinctrls Remove optional pinctrls due to using FORCE/RG_IDDIG to implement manual switch function. Signed-off-by: Chunfeng Yun Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt index 49c982bb5bfc..b2271d8e6b50 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt @@ -30,9 +30,10 @@ Optional properties: when supports dual-role mode. - vbus-supply : reference to the VBUS regulator, needed when supports dual-role mode. - - pinctl-names : a pinctrl state named "default" must be defined, - "id_float" and "id_ground" are optinal which depends on - "mediatek,enable-manual-drd" + - pinctrl-names : a pinctrl state named "default" is optional, and need be + defined if auto drd switch is enabled, that means the property dr_mode + is set as "otg", and meanwhile the property "mediatek,enable-manual-drd" + is not set. - pinctrl-0 : pin control group See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -- cgit v1.2.3 From e0d63c4083852e07655dfcda1320504c304218be Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 6 Oct 2017 17:49:34 +0100 Subject: usb: renesas_usbhs: Add compatible string for r8a7743/5 This patch adds support for r8a7743/5 SoCs. The Renesas RZ/G1[ME] (R8A7743/5) usbhs is identical to the R-Car Gen2 family. No driver change is needed due to the fallback compatible value "renesas,rcar-gen2-usbhs". Adding the SoC-specific compatible values here has two purposes: 1. Document which SoCs have this hardware module, 2. Allow checkpatch to validate compatible values. Acked-by: Rob Herring Acked-by: Simon Horman Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt index e79f6e43061a..47394ab788e3 100644 --- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt @@ -3,6 +3,8 @@ Renesas Electronics USBHS driver Required properties: - compatible: Must contain one or more of the following: + - "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device + - "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device - "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device - "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device - "renesas,usbhs-r8a7792" for r8a7792 (R-Car V2H) compatible device @@ -11,7 +13,7 @@ Required properties: - "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device - "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device - "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device - - "renesas,rcar-gen2-usbhs" for R-Car Gen2 compatible device + - "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices - "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device When compatible with the generic version, nodes must list the -- cgit v1.2.3 From bea173e5acd73d536dd234b34328cd52c1cadaab Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 6 Oct 2017 13:51:32 +0200 Subject: dt-bindings: irqchip: renesas-irqc: Document R-Car M3-W, V3M, D3 support Document support for the Interrupt Controller for Externel Devices (INTC-EX) in the Renesas M3-W (r8a7796), V3M (r8a77970), and D3 (r8a77995) SoCs. No driver update is needed. Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/renesas,irqc.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt index e3f052d8c11a..33c9a10fdc91 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt @@ -13,6 +13,9 @@ Required properties: - "renesas,irqc-r8a7793" (R-Car M2-N) - "renesas,irqc-r8a7794" (R-Car E2) - "renesas,intc-ex-r8a7795" (R-Car H3) + - "renesas,intc-ex-r8a7796" (R-Car M3-W) + - "renesas,intc-ex-r8a77970" (R-Car V3M) + - "renesas,intc-ex-r8a77995" (R-Car D3) - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in interrupts.txt in this directory - clocks: Must contain a reference to the functional clock. -- cgit v1.2.3 From c0ca7262088ebab67452a39f27979d3faa4762f0 Mon Sep 17 00:00:00 2001 From: Doug Berger Date: Mon, 18 Sep 2017 18:00:00 -0700 Subject: irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller Add the initialization of the generic irq chip for the BCM7271 L2 interrupt controller. This controller only supports level interrupts and uses the "brcm,bcm7271-l2-intc" compatibility string. Acked-by: Rob Herring Reviewed-by: Florian Fainelli Signed-off-by: Doug Berger Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/brcm,l2-intc.txt | 3 +- drivers/irqchip/irq-brcmstb-l2.c | 86 ++++++++++++++++------ 2 files changed, 66 insertions(+), 23 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt index 448273a30a11..36df06c5c567 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt @@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller Required properties: -- compatible: should be "brcm,l2-intc" +- compatible: should be "brcm,l2-intc" for latched interrupt controllers + should be "brcm,bcm7271-l2-intc" for level interrupt controllers - reg: specifies the base physical address and size of the registers - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index 8d54cd7a090d..691d20eb0bec 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -31,13 +31,34 @@ #include #include -/* Register offsets in the L2 interrupt controller */ -#define CPU_STATUS 0x00 -#define CPU_SET 0x04 -#define CPU_CLEAR 0x08 -#define CPU_MASK_STATUS 0x0c -#define CPU_MASK_SET 0x10 -#define CPU_MASK_CLEAR 0x14 +struct brcmstb_intc_init_params { + irq_flow_handler_t handler; + int cpu_status; + int cpu_clear; + int cpu_mask_status; + int cpu_mask_set; + int cpu_mask_clear; +}; + +/* Register offsets in the L2 latched interrupt controller */ +static const struct brcmstb_intc_init_params l2_edge_intc_init = { + .handler = handle_edge_irq, + .cpu_status = 0x00, + .cpu_clear = 0x08, + .cpu_mask_status = 0x0c, + .cpu_mask_set = 0x10, + .cpu_mask_clear = 0x14 +}; + +/* Register offsets in the L2 level interrupt controller */ +static const struct brcmstb_intc_init_params l2_lvl_intc_init = { + .handler = handle_level_irq, + .cpu_status = 0x00, + .cpu_clear = -1, /* Register not present */ + .cpu_mask_status = 0x04, + .cpu_mask_set = 0x08, + .cpu_mask_clear = 0x0C +}; /* L2 intc private data structure */ struct brcmstb_l2_intc_data { @@ -128,7 +149,7 @@ static void brcmstb_l2_intc_resume(struct irq_data *d) struct brcmstb_l2_intc_data *b = gc->private; irq_gc_lock(gc); - if (ct->chip.irq_ack != irq_gc_noop) { + if (ct->chip.irq_ack) { /* Clear unmasked non-wakeup interrupts */ irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, ct->regs.ack); @@ -141,7 +162,9 @@ static void brcmstb_l2_intc_resume(struct irq_data *d) } static int __init brcmstb_l2_intc_of_init(struct device_node *np, - struct device_node *parent) + struct device_node *parent, + const struct brcmstb_intc_init_params + *init_params) { unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct brcmstb_l2_intc_data *data; @@ -163,12 +186,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, } /* Disable all interrupts by default */ - writel(0xffffffff, base + CPU_MASK_SET); + writel(0xffffffff, base + init_params->cpu_mask_set); /* Wakeup interrupts may be retained from S5 (cold boot) */ data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); - if (!data->can_wake) - writel(0xffffffff, base + CPU_CLEAR); + if (!data->can_wake && (init_params->cpu_clear >= 0)) + writel(0xffffffff, base + init_params->cpu_clear); parent_irq = irq_of_parse_and_map(np, 0); if (!parent_irq) { @@ -193,7 +216,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, /* Allocate a single Generic IRQ chip for this node */ ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, - np->full_name, handle_edge_irq, clr, 0, flags); + np->full_name, init_params->handler, clr, 0, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; @@ -206,21 +229,26 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, data->gc = irq_get_domain_generic_chip(data->domain, 0); data->gc->reg_base = base; data->gc->private = data; - data->status_offset = CPU_STATUS; - data->mask_offset = CPU_MASK_STATUS; + data->status_offset = init_params->cpu_status; + data->mask_offset = init_params->cpu_mask_status; ct = data->gc->chip_types; - ct->chip.irq_ack = irq_gc_ack_set_bit; - ct->regs.ack = CPU_CLEAR; + if (init_params->cpu_clear >= 0) { + ct->regs.ack = init_params->cpu_clear; + ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack; + } else { + /* No Ack - but still slightly more efficient to define this */ + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + } ct->chip.irq_mask = irq_gc_mask_disable_reg; - ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack; - ct->regs.disable = CPU_MASK_SET; - ct->regs.mask = CPU_MASK_STATUS; + ct->regs.disable = init_params->cpu_mask_set; + ct->regs.mask = init_params->cpu_mask_status; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; - ct->regs.enable = CPU_MASK_CLEAR; + ct->regs.enable = init_params->cpu_mask_clear; ct->chip.irq_suspend = brcmstb_l2_intc_suspend; ct->chip.irq_resume = brcmstb_l2_intc_resume; @@ -247,4 +275,18 @@ out_free: kfree(data); return ret; } -IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init); + +int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, + struct device_node *parent) +{ + return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); +} +IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init); + +int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, + struct device_node *parent) +{ + return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); +} +IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc", + brcmstb_l2_lvl_intc_of_init); -- cgit v1.2.3 From 1000cec2f02263e081e7ad559da5e03329aab58a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 14 Oct 2017 07:13:12 +0800 Subject: dt-bindings: arm: amlogic: Add Meson AXG binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce new bindings for the Meson AXG SoC which now have different memory layout. Signed-off-by: Yixun Lan Reviewed-by: Andreas Färber Reviewed-by: Neil Armstrong Reviewed-by: Kevin Hilman Acked-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index da379880abb6..f747f47922c5 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -41,6 +41,10 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: Required root node property: compatible: "amlogic,s912", "amlogic,meson-gxm"; +Boards with the Amlogic Meson AXG A113D SoC shall have the following properties: + Required root node property: + compatible: "amlogic,a113d", "amlogic,meson-axg"; + Board compatible values (alphabetically, grouped by SoC): - "geniatech,atv1200" (Meson6) @@ -76,6 +80,8 @@ Board compatible values (alphabetically, grouped by SoC): - "nexbox,a1" (Meson gxm s912) - "tronsmart,vega-s96" (Meson gxm s912) + - "amlogic,s400" (Meson axg a113d) + Amlogic Meson Firmware registers Interface ------------------------------------------ -- cgit v1.2.3 From 558b01654d92332d3b7b17bf773cdce8ce16ef46 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 17 Oct 2017 17:55:56 +0100 Subject: irqchip/gic-v3: Add workaround for Synquacer pre-ITS The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. Acked-by: Rob Herring Signed-off-by: Ard Biesheuvel Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/arm,gic-v3.txt | 4 ++ arch/arm64/Kconfig | 8 +++ drivers/irqchip/irq-gic-v3-its.c | 72 +++++++++++++++++++++- 3 files changed, 82 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..c3e6092f3add 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional: +- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated + address and size of the pre-ITS window. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..c4361dff2b74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 4d432804c2bc..54ea4e26c7a9 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -83,6 +83,8 @@ struct its_baser { u32 psz; }; +struct its_device; + /* * The ITS structure - contains most of the infrastructure, with the * top-level MSI domain, the command queue, the collections, and the @@ -97,11 +99,15 @@ struct its_node { struct its_cmd_block *cmd_write; struct its_baser tables[GITS_BASER_NR_REGS]; struct its_collection *collections; + struct fwnode_handle *fwnode_handle; + u64 (*get_msi_base)(struct its_device *its_dev); struct list_head its_device_list; u64 flags; u32 ite_size; u32 device_ids; int numa_node; + unsigned int msi_domain_flags; + u32 pre_its_base; /* for Socionext Synquacer */ bool is_v4; }; @@ -1095,6 +1101,13 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return IRQ_SET_MASK_OK_DONE; } +static u64 its_irq_get_msi_base(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + return its->phys_base + GITS_TRANSLATER; +} + static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); @@ -1102,7 +1115,7 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) u64 addr; its = its_dev->its; - addr = its->phys_base + GITS_TRANSLATER; + addr = its->get_msi_base(its_dev); msg->address_lo = lower_32_bits(addr); msg->address_hi = upper_32_bits(addr); @@ -2760,6 +2773,45 @@ static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) return true; } +static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + + /* + * The Socionext Synquacer SoC has a so-called 'pre-ITS', + * which maps 32-bit writes targeted at a separate window of + * size '4 << device_id_bits' onto writes to GITS_TRANSLATER + * with device ID taken from bits [device_id_bits + 1:2] of + * the window offset. + */ + return its->pre_its_base + (its_dev->device_id << 2); +} + +static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) +{ + struct its_node *its = data; + u32 pre_its_window[2]; + u32 ids; + + if (!fwnode_property_read_u32_array(its->fwnode_handle, + "socionext,synquacer-pre-its", + pre_its_window, + ARRAY_SIZE(pre_its_window))) { + + its->pre_its_base = pre_its_window[0]; + its->get_msi_base = its_irq_get_msi_base_pre_its; + + ids = ilog2(pre_its_window[1]) - 2; + if (its->device_ids > ids) + its->device_ids = ids; + + /* the pre-ITS breaks isolation, so disable MSI remapping */ + its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; + return true; + } + return false; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -2784,6 +2836,19 @@ static const struct gic_quirk its_quirks[] = { .mask = 0xffffffff, .init = its_enable_quirk_qdf2400_e0065, }, +#endif +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + { + /* + * The Socionext Synquacer SoC incorporates ARM's own GIC-500 + * implementation, but with a 'pre-ITS' added that requires + * special handling in software. + */ + .desc = "ITS: Socionext Synquacer pre-ITS", + .iidr = 0x0001143b, + .mask = 0xffffffff, + .init = its_enable_quirk_socionext_synquacer, + }, #endif { } @@ -2813,7 +2878,7 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) inner_domain->parent = its_parent; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); - inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + inner_domain->flags |= its->msi_domain_flags; info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; @@ -2967,6 +3032,9 @@ static int __init its_probe_one(struct resource *res, goto out_free_its; } its->cmd_write = its->cmd_base; + its->fwnode_handle = handle; + its->get_msi_base = its_irq_get_msi_base; + its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; its_enable_quirks(its); -- cgit v1.2.3 From df48d3b5ef276998e399846db12c241e6f9d318c Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 18 Sep 2017 15:46:09 +0200 Subject: dt-bindings: interrupt-controller: Add DT binding for meson GPIO interrupt controller This commit adds the device tree bindings description for Amlogic's GPIO interrupt controller available on the meson8b, gxbb and gxl SoC families Cc: Heiner Kallweit Acked-by: Rob Herring Signed-off-by: Jerome Brunet Signed-off-by: Marc Zyngier --- .../amlogic,meson-gpio-intc.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt new file mode 100644 index 000000000000..633e21ce4b17 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -0,0 +1,35 @@ +Amlogic meson GPIO interrupt controller + +Meson SoCs contains an interrupt controller which is able to watch the SoC +pads and generate an interrupt on edge or level. The controller is essentially +a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. It does not expose all 256 mux inputs because the +documentation shows that the upper part is not mapped to any pad. The actual +number of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : must have "amlogic,meson8-gpio-intc” and either + “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or + “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or + “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912) +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC. +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. +- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These + are the hwirqs used on the parent interrupt controller. + +Example: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + meson,channel-interrupts = <64 65 66 67 68 69 70 71>; +}; -- cgit v1.2.3 From 3e09b155d58e44e33a699650128f8c6c833cb320 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Mon, 24 Jul 2017 19:29:15 +0300 Subject: dt-bindings: Add bindings for nvidia,tegra186-bpmp-thermal In Tegra186, the BPMP (Boot and Power Management Processor) implements an interface that is used to read system temperatures, including CPU cluster and GPU temperatures. This binding describes the thermal sensor that is exposed by BPMP. Signed-off-by: Mikko Perttunen Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../thermal/nvidia,tegra186-bpmp-thermal.txt | 32 ++++++++++++++++++++++ .../dt-bindings/thermal/tegra186-bpmp-thermal.h | 14 ++++++++++ 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt create mode 100644 include/dt-bindings/thermal/tegra186-bpmp-thermal.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt new file mode 100644 index 000000000000..276387dd6815 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra186 BPMP thermal sensor + +In Tegra186, the BPMP (Boot and Power Management Processor) implements an +interface that is used to read system temperatures, including CPU cluster +and GPU temperatures. This binding describes the thermal sensor that is +exposed by BPMP. + +The BPMP thermal node must be located directly inside the main BPMP node. See +../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. + +This node represents a thermal sensor. See thermal.txt for details of the +core thermal binding. + +Required properties: +- compatible: + Array of strings. + One of: + - "nvidia,tegra186-bpmp-thermal". +- #thermal-sensor-cells: Cell for sensor index. + Single-cell integer. + Must be <1>. + +Example: + +bpmp { + ... + + bpmp_thermal: thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; +}; diff --git a/include/dt-bindings/thermal/tegra186-bpmp-thermal.h b/include/dt-bindings/thermal/tegra186-bpmp-thermal.h new file mode 100644 index 000000000000..a96b8fa31aab --- /dev/null +++ b/include/dt-bindings/thermal/tegra186-bpmp-thermal.h @@ -0,0 +1,14 @@ +/* + * This header provides constants for binding nvidia,tegra186-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA186_BPMP_THERMAL_H + +#define TEGRA186_BPMP_THERMAL_ZONE_CPU 2 +#define TEGRA186_BPMP_THERMAL_ZONE_GPU 3 +#define TEGRA186_BPMP_THERMAL_ZONE_AUX 4 +#define TEGRA186_BPMP_THERMAL_ZONE_PLLX 5 +#define TEGRA186_BPMP_THERMAL_ZONE_AO 6 + +#endif -- cgit v1.2.3 From f76a2d9d7f9524c54dfd9c7b49ed26e488c4cf6c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 11 Oct 2017 22:51:59 +0300 Subject: gpio-rcar: document R8A77970 bindings Renesas R-Car V3M (R8A77970) SoC also has the R-Car gen3 compatible GPIO controllers, so document the SoC specific bindings. Signed-off-by: Sergei Shtylyov Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 51c86f69995e..41137a1cc099 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -14,6 +14,7 @@ Required Properties: - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller. + - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller. - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller. - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller. - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller. -- cgit v1.2.3 From 07901a94f9f9b11cc3a4537e33229cb7e7df5d2a Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Wed, 11 Oct 2017 11:34:44 -0500 Subject: gpio: gpio-dwapb: add optional reset Some platforms require reset to be released to allow register access. Signed-off-by: Alan Tull Reviewed-by: Philipp Zabel [Added DT bindings oneliner for standard reset binding] Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt | 1 + drivers/gpio/gpio-dwapb.c | 9 +++++++++ 2 files changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt index 4d6c8cdc8586..4a75da7051bd 100644 --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt @@ -29,6 +29,7 @@ controller. - interrupts : The interrupt to the parent controller raised when GPIOs generate the interrupts. - snps,nr-gpios : The number of pins in the port, a single cell. +- resets : Reset line for the controller. Example: diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c index 5cdb7bc3ad99..d782ad195c89 100644 --- a/drivers/gpio/gpio-dwapb.c +++ b/drivers/gpio/gpio-dwapb.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -98,6 +99,7 @@ struct dwapb_gpio { unsigned int nr_ports; struct irq_domain *domain; unsigned int flags; + struct reset_control *rst; }; static inline u32 gpio_reg_v2_convert(unsigned int offset) @@ -629,6 +631,12 @@ static int dwapb_gpio_probe(struct platform_device *pdev) gpio->dev = &pdev->dev; gpio->nr_ports = pdata->nports; + gpio->rst = devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(gpio->rst)) + return PTR_ERR(gpio->rst); + + reset_control_deassert(gpio->rst); + gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, sizeof(*gpio->ports), GFP_KERNEL); if (!gpio->ports) @@ -680,6 +688,7 @@ static int dwapb_gpio_remove(struct platform_device *pdev) dwapb_gpio_unregister(gpio); dwapb_irq_teardown(gpio); + reset_control_assert(gpio->rst); return 0; } -- cgit v1.2.3 From 1f63fab955dbcb8f6db56d67a4c63fc0746e4fe1 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Thu, 12 Oct 2017 12:40:10 +0200 Subject: dt-bindings: Document common property for daisy-chained devices Many serially-attached GPIO and IIO devices are daisy-chainable. Examples for GPIO devices are Maxim MAX3191x and TI SN65HVS88x: https://datasheets.maximintegrated.com/en/ds/MAX31913.pdf http://www.ti.com/lit/ds/symlink/sn65hvs880.pdf Examples for IIO devices are TI DAC128S085 and TI DAC161S055: http://www.ti.com/lit/ds/symlink/dac128s085.pdf http://www.ti.com/lit/ds/symlink/dac161s055.pdf We already have drivers for daisy-chainable devices in the tree but their devicetree bindings are somewhat inconsistent and ill-named: The gpio-74x164.c driver uses "registers-number" to convey the number of devices in the daisy-chain. (Sans vendor prefix, multiple vendors sell compatible versions of this chip.) The gpio-pisosr.c driver takes a different approach and calculates the number of devices in the daisy-chain by dividing the common "ngpios" property (Documentation/devicetree/bindings/gpio/gpio.txt) by 8 (which assumes that each chip has 8 inputs). Let's standardize on a common "#daisy-chained-devices" property. That name was chosen because it's the term most frequently used in datasheets. (A less frequently used synonym is "cascaded devices".) Signed-off-by: Lukas Wunner Acked-by: Jonathan Cameron Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/common-properties.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/common-properties.txt b/Documentation/devicetree/bindings/common-properties.txt index 697714f8d75c..a3448bfa1c82 100644 --- a/Documentation/devicetree/bindings/common-properties.txt +++ b/Documentation/devicetree/bindings/common-properties.txt @@ -1,4 +1,8 @@ Common properties +================= + +Endianness +---------- The Devicetree Specification does not define any properties related to hardware byteswapping, but endianness issues show up frequently in porting Linux to @@ -58,3 +62,25 @@ dev: dev@40031000 { ... little-endian; }; + +Daisy-chained devices +--------------------- + +Many serially-attached GPIO and IIO devices are daisy-chainable. To the +host controller, a daisy-chain appears as a single device, but the number +of inputs and outputs it provides is the sum of inputs and outputs provided +by all of its devices. The driver needs to know how many devices the +daisy-chain comprises to determine the amount of data exchanged, how many +inputs and outputs to register and so on. + +Optional properties: + - #daisy-chained-devices: Number of devices in the daisy-chain (default is 1). + +Example: +gpio@0 { + compatible = "name"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + #daisy-chained-devices = <3>; +}; -- cgit v1.2.3 From c019c18da10dae244308f584707804d0c148fe0b Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Thu, 12 Oct 2017 12:40:10 +0200 Subject: dt-bindings: gpio: max3191x: Document new driver Add device tree bindings for Maxim MAX3191x industrial serializer. Cc: Mathias Duckeck Signed-off-by: Lukas Wunner Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-max3191x.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-max3191x.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-max3191x.txt b/Documentation/devicetree/bindings/gpio/gpio-max3191x.txt new file mode 100644 index 000000000000..b3a6444b8f45 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-max3191x.txt @@ -0,0 +1,59 @@ +GPIO driver for Maxim MAX3191x industrial serializer + +Required properties: + - compatible: Must be one of: + "maxim,max31910" + "maxim,max31911" + "maxim,max31912" + "maxim,max31913" + "maxim,max31953" + "maxim,max31963" + - reg: Chip select number. + - gpio-controller: Marks the device node as a GPIO controller. + - #gpio-cells: Should be two. For consumer use see gpio.txt. + +Optional properties: + - #daisy-chained-devices: + Number of chips in the daisy-chain (default is 1). + - maxim,modesel-gpios: GPIO pins to configure modesel of each chip. + The number of GPIOs must equal "#daisy-chained-devices" + (if each chip is driven by a separate pin) or 1 + (if all chips are wired to the same pin). + - maxim,fault-gpios: GPIO pins to read fault of each chip. + The number of GPIOs must equal "#daisy-chained-devices" + or 1. + - maxim,db0-gpios: GPIO pins to configure debounce of each chip. + The number of GPIOs must equal "#daisy-chained-devices" + or 1. + - maxim,db1-gpios: GPIO pins to configure debounce of each chip. + The number of GPIOs must equal "maxim,db0-gpios". + - maxim,modesel-8bit: Boolean whether the modesel pin of the chips is + pulled high (8-bit mode). Use this if the modesel pin + is hardwired and consequently "maxim,modesel-gpios" + cannot be specified. By default if neither this nor + "maxim,modesel-gpios" is given, the driver assumes + that modesel is pulled low (16-bit mode). + - maxim,ignore-undervoltage: + Boolean whether to ignore undervoltage alarms signaled + by the "maxim,fault-gpios" or by the status byte + (in 16-bit mode). Use this if the chips are powered + through 5VOUT instead of VCC24V, in which case they + will constantly signal undervoltage. + +For other required and optional properties of SPI slave nodes please refer to +../spi/spi-bus.txt. + +Example: + gpio@0 { + compatible = "maxim,max31913"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + + maxim,modesel-gpios = <&gpio2 23>; + maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + maxim,db0-gpios = <&gpio2 25>; + maxim,db1-gpios = <&gpio2 26>; + + spi-max-frequency = <25000000>; + }; -- cgit v1.2.3 From e20824e944c3bf4352fcd8d9f446c41b53901e7b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 18 Sep 2017 15:46:41 +0200 Subject: dt-bindings: timer: renesas, cmt: Fix SoC-specific compatible values While the new family-specific compatible values introduced by commit 6f54cc1adcc8957f ("devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings") use the recommended order ",-", the new SoC-specific compatible values still use the old and deprecated order ",-". Switch the SoC-specific compatible values to the recommended order while there are no upstream users of these compatible values yet. Fixes: 7f03a0ecfdc786c1 ("devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings") Fixes: 63d9e8ca0dd4bfa4 ("devicetree: bindings: Deprecate property, update example") Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 6ca6b9e582a0..d740989eb569 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -20,16 +20,16 @@ Required Properties: (CMT1 on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-48-* entries. - - "renesas,cmt0-r8a73a4" for the 32-bit CMT0 device included in r8a73a4. - - "renesas,cmt1-r8a73a4" for the 48-bit CMT1 device included in r8a73a4. - - "renesas,cmt0-r8a7790" for the 32-bit CMT0 device included in r8a7790. - - "renesas,cmt1-r8a7790" for the 48-bit CMT1 device included in r8a7790. - - "renesas,cmt0-r8a7791" for the 32-bit CMT0 device included in r8a7791. - - "renesas,cmt1-r8a7791" for the 48-bit CMT1 device included in r8a7791. - - "renesas,cmt0-r8a7793" for the 32-bit CMT0 device included in r8a7793. - - "renesas,cmt1-r8a7793" for the 48-bit CMT1 device included in r8a7793. - - "renesas,cmt0-r8a7794" for the 32-bit CMT0 device included in r8a7794. - - "renesas,cmt1-r8a7794" for the 48-bit CMT1 device included in r8a7794. + - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4. + - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4. + - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. + - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. + - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. + - "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791. + - "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793. + - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793. + - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. + - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2. - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2. @@ -46,7 +46,7 @@ Required Properties: Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes cmt0: timer@ffca0000 { - compatible = "renesas,cmt0-r8a7790", "renesas,rcar-gen2-cmt0"; + compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, <0 142 IRQ_TYPE_LEVEL_HIGH>; @@ -55,7 +55,7 @@ Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes }; cmt1: timer@e6130000 { - compatible = "renesas,cmt1-r8a7790", "renesas,rcar-gen2-cmt1"; + compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, <0 121 IRQ_TYPE_LEVEL_HIGH>, -- cgit v1.2.3 From 055f624e1eb9cae28211a7e1e140111d29228e13 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 19 Oct 2017 16:21:05 -0700 Subject: Input: gpio_mouse - add DT bindings This adds DT bindings for simple mice attached to GPIO lines. As the properties are very general and pertains to all mice I can think of, we use very generic names for the 4-7 GPIO lines, "up", "down" etc. Acked-by: Hans-Christian Noren Egtvedt Signed-off-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/gpio-mouse.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/gpio-mouse.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/gpio-mouse.txt b/Documentation/devicetree/bindings/input/gpio-mouse.txt new file mode 100644 index 000000000000..519510a11af9 --- /dev/null +++ b/Documentation/devicetree/bindings/input/gpio-mouse.txt @@ -0,0 +1,32 @@ +Device-Tree bindings for GPIO attached mice + +This simply uses standard GPIO handles to define a simple mouse connected +to 5-7 GPIO lines. + +Required properties: + - compatible: must be "gpio-mouse" + - scan-interval-ms: The scanning interval in milliseconds + - up-gpios: GPIO line phandle to the line indicating "up" + - down-gpios: GPIO line phandle to the line indicating "down" + - left-gpios: GPIO line phandle to the line indicating "left" + - right-gpios: GPIO line phandle to the line indicating "right" + +Optional properties: + - button-left-gpios: GPIO line handle to the left mouse button + - button-middle-gpios: GPIO line handle to the middle mouse button + - button-right-gpios: GPIO line handle to the right mouse button +Example: + +#include + +gpio-mouse { + compatible = "gpio-mouse"; + scan-interval-ms = <50>; + up-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + down-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + left-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + right-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + button-left-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + button-middle-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + button-right-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From 87d9fa647020fb65985ec08826f6c77b9b4084af Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 18 Oct 2017 09:21:26 +0200 Subject: dt-bindings: net: sh_eth: add R-Car Gen[12] fallback compatibility strings Add fallback compatibility strings for R-Car Gen 1 and 2. In the case of Renesas R-Car hardware we know that there are generations of SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship between IP blocks might be. For example, I believe that r8a7790 is older than r8a7791 but that doesn't imply that the latter is a descendant of the former or vice versa. We can, however, by examining the documentation and behaviour of the hardware at run-time observe that the current driver implementation appears to be compatible with the IP blocks on SoCs within a given generation. For the above reasons and convenience when enabling new SoCs a per-generation fallback compatibility string scheme is being adopted for drivers for Renesas SoCs. Note that R-Car Gen2 and RZ/G1 have many compatible IP blocks. The approach that has been consistently taken for other IP blocks is to name common code, compatibility strings and so on after R-Car Gen2. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Reviewed-by: Sergei Shtylyov Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/sh_eth.txt | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/sh_eth.txt b/Documentation/devicetree/bindings/net/sh_eth.txt index 0115c85a2425..5172799a7f1a 100644 --- a/Documentation/devicetree/bindings/net/sh_eth.txt +++ b/Documentation/devicetree/bindings/net/sh_eth.txt @@ -4,7 +4,8 @@ This file provides information on what the device node for the SH EtherMAC interface contains. Required properties: -- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC. +- compatible: Must contain one or more of the following: + "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC. "renesas,ether-r8a7743" if the device is a part of R8A7743 SoC. "renesas,ether-r8a7745" if the device is a part of R8A7745 SoC. "renesas,ether-r8a7778" if the device is a part of R8A7778 SoC. @@ -14,6 +15,14 @@ Required properties: "renesas,ether-r8a7793" if the device is a part of R8A7793 SoC. "renesas,ether-r8a7794" if the device is a part of R8A7794 SoC. "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC. + "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device. + "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1 + device. + + When compatible with the generic version, nodes must list + the SoC-specific version corresponding to the platform + first followed by the generic version. + - reg: offset and length of (1) the E-DMAC/feLic register block (required), (2) the TSU register block (optional). - interrupts: interrupt specifier for the sole interrupt. @@ -36,7 +45,8 @@ Optional properties: Example (Lager board): ethernet@ee700000 { - compatible = "renesas,ether-r8a7790"; + compatible = "renesas,ether-r8a7790", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupt-parent = <&gic>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From d454cecc637b90996ab15b2e61a6cc51b7e1463c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 10:54:22 +0200 Subject: clk: renesas: rz: clk-rz is meant for RZ/A1 The RZ family of Renesas SoCs has several different subfamilies (RZ/A, RZ/G, RZ/N, and RZ/T). Clarify that the renesas,rz-cpg-clocks DT bindings and clk-rz driver apply to RZ/A1 only. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt | 4 ++-- drivers/clk/renesas/clk-rz.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt index bb5d942075fb..8ff3e2774ed8 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt @@ -1,6 +1,6 @@ -* Renesas RZ Clock Pulse Generator (CPG) +* Renesas RZ/A1 Clock Pulse Generator (CPG) -The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable +The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable CPU and GPU clocks, and several fixed ratio dividers. The CPG also provides a Clock Domain for SoC devices, in combination with the CPG Module Stop (MSTP) Clocks. diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index 5adb934326d1..127c58135c8f 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -1,5 +1,5 @@ /* - * rz Core CPG Clocks + * RZ/A1 Core CPG Clocks * * Copyright (C) 2013 Ideas On Board SPRL * Copyright (C) 2014 Wolfram Sang, Sang Engineering -- cgit v1.2.3 From c77d3b8d0ce856836c682617eeaac2ac00164c53 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 18 Oct 2017 16:28:42 +0800 Subject: dt-bindings: arm: mediatek: add MT7622 string to the PMIC wrapper doc Signed-off-by: Chenglin Xu Signed-off-by: Sean Wang Acked-by: Rob Herring Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index 107700d00df4..bf80e3f96f8c 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -19,6 +19,7 @@ IP Pairing Required properties in pwrap device node. - compatible: "mediatek,mt2701-pwrap" for MT2701/7623 SoCs + "mediatek,mt7622-pwrap" for MT7622 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs - interrupts: IRQ for pwrap in SOC @@ -36,9 +37,12 @@ Required properties in pwrap device node. - clocks: Must contain an entry for each entry in clock-names. Optional properities: -- pmic: Mediatek PMIC MFD is the child device of pwrap +- pmic: Using either MediaTek PMIC MFD as the child device of pwrap See the following for child node definitions: Documentation/devicetree/bindings/mfd/mt6397.txt + or the regulator-only device as the child device of pwrap, such as MT6380. + See the following definitions for such kinds of devices. + Documentation/devicetree/bindings/regulator/mt6380-regulator.txt Example: pwrap: pwrap@1000f000 { -- cgit v1.2.3 From 7a15cf2af480440bacf2fc0010f1fa1a1f3980d6 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Mon, 9 Oct 2017 15:26:38 +0200 Subject: nvmem: rockchip: add support for RK3368 This adds the necessary function for handling support on RK3368 SoCs Signed-off-by: Romain Perier Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt | 1 + drivers/nvmem/rockchip-efuse.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt index 1ff02afdc55a..60bec4782806 100644 --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt @@ -6,6 +6,7 @@ Required properties: - "rockchip,rk3188-efuse" - for RK3188 SoCs. - "rockchip,rk3228-efuse" - for RK3228 SoCs. - "rockchip,rk3288-efuse" - for RK3288 SoCs. + - "rockchip,rk3368-efuse" - for RK3368 SoCs. - "rockchip,rk3399-efuse" - for RK3399 SoCs. - reg: Should contain the registers location and exact eFuse size - clocks: Should be the clock id of eFuse diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c index 63e3eb55f3ac..eb4c530c2564 100644 --- a/drivers/nvmem/rockchip-efuse.c +++ b/drivers/nvmem/rockchip-efuse.c @@ -177,6 +177,10 @@ static const struct of_device_id rockchip_efuse_match[] = { .compatible = "rockchip,rk3288-efuse", .data = (void *)&rockchip_rk3288_efuse_read, }, + { + .compatible = "rockchip,rk3368-efuse", + .data = (void *)&rockchip_rk3288_efuse_read, + }, { .compatible = "rockchip,rk3399-efuse", .data = (void *)&rockchip_rk3399_efuse_read, -- cgit v1.2.3 From 41e043498978ad3c8d5a70613f41195faf09663f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 9 Oct 2017 15:26:39 +0200 Subject: dt-bindings: nvmem: Describe the Amlogic Meson6/Meson8/Meson8b efuse Amlogic Meson6, Meson8 and Meson8b SoCs have an efuse which contains calibration data from the factory (for the internal temperature sensor and some CVBS connector settings). Some manufacturers also store the MAC address or serial number in the efuse. This documents the devicetree bindings for the efuse on these SoCs. Signed-off-by: Martin Blumenstingl Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../bindings/nvmem/amlogic-meson-mx-efuse.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt new file mode 100644 index 000000000000..a3c63954a1a4 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/amlogic-meson-mx-efuse.txt @@ -0,0 +1,22 @@ +Amlogic Meson6/Meson8/Meson8b efuse + +Required Properties: +- compatible: depending on the SoC this should be one of: + - "amlogic,meson6-efuse" + - "amlogic,meson8-efuse" + - "amlogic,meson8b-efuse" +- reg: base address and size of the efuse registers +- clocks: a reference to the efuse core gate clock +- clock-names: must be "core" + +All properties and sub-nodes as well as the consumer bindings +defined in nvmem.txt in this directory are also supported. + + +Example: + efuse: nvmem@0 { + compatible = "amlogic,meson8-efuse"; + reg = <0x0 0x2000>; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "core"; + }; -- cgit v1.2.3 From 9593ad32b8be82f3abd6002336a93c405361b9fd Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 9 Oct 2017 15:26:40 +0200 Subject: nvmem: meson-efuse: indicate that this driver is only for Meson GX SoCs The current Amlogic Meson eFuse driver only supports the 64-bit SoCs (GXBB and newer). Older SoCs cannot be supported by the same driver because they do not use the meson secure monitor firmware to access the hardware. Signed-off-by: Martin Blumenstingl Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt | 2 +- drivers/nvmem/Kconfig | 4 ++-- drivers/nvmem/meson-efuse.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt index fafd85bd67a6..e3298e18de26 100644 --- a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt @@ -1,4 +1,4 @@ -= Amlogic eFuse device tree bindings = += Amlogic Meson GX eFuse device tree bindings = Required properties: - compatible: should be "amlogic,meson-gxbb-efuse" diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index ea3044c5d6ee..2a07cf169b52 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -135,11 +135,11 @@ config NVMEM_VF610_OCOTP be called nvmem-vf610-ocotp. config MESON_EFUSE - tristate "Amlogic eFuse Support" + tristate "Amlogic Meson GX eFuse Support" depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM help This is a driver to retrieve specific values from the eFuse found on - the Amlogic Meson SoCs. + the Amlogic Meson GX SoCs. This driver can also be built as a module. If so, the module will be called nvmem_meson_efuse. diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c index 70bfc9839bb2..1ea3cd24a508 100644 --- a/drivers/nvmem/meson-efuse.c +++ b/drivers/nvmem/meson-efuse.c @@ -1,5 +1,5 @@ /* - * Amlogic eFuse Driver + * Amlogic Meson GX eFuse Driver * * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione @@ -89,5 +89,5 @@ static struct platform_driver meson_efuse_driver = { module_platform_driver(meson_efuse_driver); MODULE_AUTHOR("Carlo Caione "); -MODULE_DESCRIPTION("Amlogic Meson NVMEM driver"); +MODULE_DESCRIPTION("Amlogic Meson GX NVMEM driver"); MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From f6755643d62e14c55c2f864a7995fd8001ae3f51 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 11 Oct 2017 15:50:13 +0200 Subject: dt-bindings: PCI: rcar: Correct example to match reality Correct the USB subnodes in the example, as in f7d569c1e6a6 ("ARM: dts: r8a779x: Fix PCI bus dtc warnings"). 1. Drop the bogus 'device_type = "pci"' properties, 2. Correct the unit addresses. Update other bits in the example to match real use: 1. Rename the USB subnodes from "pci" to "usb", 2. Update the "phys" property. Signed-off-by: Geert Uytterhoeven Signed-off-by: Bjorn Helgaas Acked-by: Sergei Shtylyov Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt index 3d038638612b..9fe7e12a7bf3 100644 --- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt +++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt @@ -60,17 +60,15 @@ Example SoC configuration: 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; - pci@0,1 { + usb@1,0 { reg = <0x800 0 0 0 0>; - device_type = "pci"; - phys = <&usbphy 0 0>; + phys = <&usb0 0>; phy-names = "usb"; }; - pci@0,2 { + usb@2,0 { reg = <0x1000 0 0 0 0>; - device_type = "pci"; - phys = <&usbphy 0 0>; + phys = <&usb0 0>; phy-names = "usb"; }; }; -- cgit v1.2.3 From 14f0e5f8d97e632695d92f41f2e91d10d8005d47 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Thu, 19 Oct 2017 15:03:17 +0200 Subject: ASoC: stm32: Add synchronization to SAI bindings Add synchronization configuration to STM32 SAI bindings. This patch also adds peripheral clock which is required to access synchronization register. Signed-off-by: Olivier Moysan Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/st,stm32-sai.txt | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt index f1c5ae59e7c9..1f9cd7095337 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt @@ -10,13 +10,21 @@ Required properties: - reg: Base address and size of SAI common register set. - clocks: Must contain phandle and clock specifier pairs for each entry in clock-names. - - clock-names: Must contain "x8k" and "x11k" + - clock-names: Must contain "pclk" "x8k" and "x11k" + "pclk": Clock which feeds the peripheral bus interface. + Mandatory for "st,stm32h7-sai" compatible. + Not used for "st,stm32f4-sai" compatible. "x8k": SAI parent clock for sampling rates multiple of 8kHz. "x11k": SAI parent clock for sampling rates multiple of 11.025kHz. - interrupts: cpu DAI interrupt line shared by SAI sub-blocks Optional properties: - resets: Reference to a reset controller asserting the SAI + - st,sync: specify synchronization mode. + By default SAI sub-block is in asynchronous mode. + This property sets SAI sub-block as slave of another SAI sub-block. + Must contain the phandle and index of the sai sub-block providing + the synchronization. SAI subnodes: Two subnodes corresponding to SAI sub-block instances A et B can be defined. @@ -52,8 +60,8 @@ sai1: sai1@40015800 { #size-cells = <1>; ranges = <0 0x40015800 0x400>; reg = <0x40015800 0x4>; - clocks = <&rcc PLL1_Q>, <&rcc PLL2_P>; - clock-names = "x8k", "x11k"; + clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>; + clock-names = "pclk", "x8k", "x11k"; interrupts = <87>; sai1a: audio-controller@40015804 { -- cgit v1.2.3 From 05c006145054a86430ed4fdd4f8c1b4139a44bee Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 17 Oct 2017 06:57:19 +0000 Subject: ASoC: audio-graph-scu-card: add missing Capture routing on Example Both cases have 1 Capture path. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt index 8b8afe9fcb31..a10daf54aa0c 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt +++ b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt @@ -43,7 +43,8 @@ Example 1. Sampling Rate Conversion label = "sound-card"; prefix = "codec"; routing = "codec Playback", "DAI0 Playback", - "codec Playback", "DAI1 Playback"; + "codec Playback", "DAI1 Playback", + "DAI0 Capture", "codec Capture"; convert-rate = <48000>; dais = <&cpu_port>; @@ -79,7 +80,8 @@ Example 2. 2 CPU 1 Codec (Mixing) label = "sound-card"; prefix = "codec"; routing = "codec Playback", "DAI0 Playback", - "codec Playback", "DAI1 Playback"; + "codec Playback", "DAI1 Playback", + "DAI0 Capture", "codec Capture"; convert-rate = <48000>; dais = <&cpu_port0 -- cgit v1.2.3 From 86d5b2c20d8ec255ef7646533b81dabc935e0eff Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 17 Oct 2017 06:57:49 +0000 Subject: ASoC: audio-graph-scu-card: remove unnecessary route patch from Example 1 Example 1 is for "Sampling Rate Conversion", sample has only 1 CPU, 1 Codec. Thus, "codec Playback", "DAI1 Playback" route is unnecessary. Signed-off-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt index a10daf54aa0c..441dd6f29df1 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt +++ b/Documentation/devicetree/bindings/sound/audio-graph-scu-card.txt @@ -43,7 +43,6 @@ Example 1. Sampling Rate Conversion label = "sound-card"; prefix = "codec"; routing = "codec Playback", "DAI0 Playback", - "codec Playback", "DAI1 Playback", "DAI0 Capture", "codec Capture"; convert-rate = <48000>; -- cgit v1.2.3 From 930cc2d27847a4235bb3dc1e3817504dcf230dcb Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Tue, 17 Oct 2017 12:42:00 +0200 Subject: dt-bindings: iio: dac: ti-dac082s085: Document new driver Add device tree bindings for Texas Instruments 8/10/12-bit 2/4-channel DAC driver. Cc: Mathias Duckeck Acked-by: Rob Herring Signed-off-by: Lukas Wunner Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/dac/ti-dac082s085.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt b/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt new file mode 100644 index 000000000000..9cb0e10df704 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt @@ -0,0 +1,34 @@ +Texas Instruments 8/10/12-bit 2/4-channel DAC driver + +Required properties: + - compatible: Must be one of: + "ti,dac082s085" + "ti,dac102s085" + "ti,dac122s085" + "ti,dac084s085" + "ti,dac104s085" + "ti,dac124s085" + - reg: Chip select number. + - spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify + either spi-cpha or spi-cpol (but not both). + - vref-supply: Phandle to the external reference voltage supply. + +For other required and optional properties of SPI slave nodes please refer to +../../spi/spi-bus.txt. + +Example: + vref_2v5_reg: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + dac@0 { + compatible = "ti,dac082s085"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-cpol; + vref-supply = <&vref_2v5_reg>; + }; -- cgit v1.2.3 From 2501ec14048d24d98651d2204cdf9cb33a127199 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 10 Oct 2017 22:08:55 -0700 Subject: dt-binding: soc: qcom: Add binding for rmtfs memory This adds the binding for describing shared memory used to exchange file system blocks between the RMTFS client and service. A client for this is generally found in the modem firmware and is used for accessing persistent storage for things such as radio calibration. Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../bindings/reserved-memory/qcom,rmtfs-mem.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt new file mode 100644 index 000000000000..8562ba1dce69 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt @@ -0,0 +1,51 @@ +Qualcomm Remote File System Memory binding + +This binding describes the Qualcomm remote filesystem memory, which serves the +purpose of describing the shared memory region used for remote processors to +access block device data using the Remote Filesystem protocol. + +- compatible: + Usage: required + Value type: + Definition: must be: + "qcom,rmtfs-mem" + +- reg: + Usage: required for static allocation + Value type: + Definition: must specify base address and size of the memory region, + as described in reserved-memory.txt + +- size: + Usage: required for dynamic allocation + Value type: + Definition: must specify a size of the memory region, as described in + reserved-memory.txt + +- qcom,client-id: + Usage: required + Value type: + Definition: identifier of the client to use this region for buffers. + +- qcom,vmid: + Usage: optional + Value type: + Definition: vmid of the remote processor, to set up memory protection. + += EXAMPLE +The following example shows the remote filesystem memory setup for APQ8016, +with the rmtfs region for the Hexagon DSP (id #1) located at 0x86700000. + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rmtfs@86700000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x86700000 0x0 0xe0000>; + no-map; + + qcom,client-id = <1>; + }; + }; -- cgit v1.2.3 From f7da4e6d29539bad2c29dd8ccb4ac628fe19f82b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 11:22:23 +0100 Subject: phy: rcar-gen2: Add r8a7743/5 support Add USB PHY support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) USB PHY is identical to the R-Car Gen2 family. Signed-off-by: Biju Das Acked-by: Simon Horman Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt index 91da947ae9b6..eeb9e1874ea6 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt @@ -4,10 +4,13 @@ This file provides information on what the device node for the R-Car generation 2 USB PHY contains. Required properties: -- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. +- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. + "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. + "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. - "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 compatible device. + "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or + RZ/G1 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first -- cgit v1.2.3 From 6100ef093ba7b99efbb8b6c62b6af3c72fc82ddb Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 12 Oct 2017 15:34:48 +0900 Subject: phy: rcar-gen3-usb2: add binding for r8a77995 This patch adds binding for r8a77995 (R-Car D3). Since r8a77995 doesn't have dedicated pins (ID, VBUS), this will match against the generic fallback on R-Car D3. For now, this driver doesn't support usb role swap for r8a77995. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Simon Horman Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index ace9cce2704a..99b651b33110 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -8,6 +8,8 @@ Required properties: SoC. "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796 SoC. + "renesas,usb2-phy-r8a77995" if the device is a part of an + R8A77995 SoC. "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device. When compatible with the generic version, nodes must list the -- cgit v1.2.3 From a7ac6570f67061576c51c5204a51f034af54adec Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 11 Oct 2017 17:53:10 -0700 Subject: dt-bindings: phy: Add RX equalizer properties for Broadcom SATA PHY Define two new properties: brcm,rx-aeq-mode which allows configuring the SATA PHY RX equalizers and when "manual" is used, brcm,rx-aeq can be used to set the exact value. Signed-off-by: Florian Fainelli Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index 97977cd29a98..0aced97d8092 100644 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -27,7 +27,16 @@ Sub-nodes optional properties: This property is not applicable for "brcm,iproc-ns2-sata-phy", "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy". -Example: +- brcm,rxaeq-mode: string that indicates the desired RX equalizer + mode, possible values are: + "off" (equivalent to not specifying the property) + "auto" + "manual" (brcm,rxaeq-value is used in that case) + +- brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX + equalizer value that should be used. Allowed range is 0..63. + +Example sata-phy@f0458100 { compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>; -- cgit v1.2.3 From 1c59d045058750904926d5883ce8acdedbc52df3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 12 Oct 2017 20:36:15 +0900 Subject: dt-bindings: gpio: uniphier: add UniPhier GPIO binding This GPIO controller is used on UniPhier SoC family. The vendor specific property "socionext,interrupt-ranges" is for specifying interrupt mapping to the parent interrupt controller because the mapping is not contiguous. It works like "ranges", but transforms "interrupts" instead of "reg". Signed-off-by: Masahiro Yamada Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-uniphier.txt | 52 ++++++++++++++++++++++ MAINTAINERS | 1 + include/dt-bindings/gpio/uniphier-gpio.h | 18 ++++++++ 3 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-uniphier.txt create mode 100644 include/dt-bindings/gpio/uniphier-gpio.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt new file mode 100644 index 000000000000..fed9158dd913 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt @@ -0,0 +1,52 @@ +UniPhier GPIO controller + +Required properties: +- compatible: Should be "socionext,uniphier-gpio". +- reg: Specifies offset and length of the register set for the device. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be 2. The first cell is the pin number and the second + cell is used to specify optional parameters. +- interrupt-parent: Specifies the parent interrupt controller. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be 2. The first cell defines the interrupt number. + The second cell bits[3:0] is used to specify trigger type as follows: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. +- ngpios: Specifies the number of GPIO lines. +- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt) +- socionext,interrupt-ranges: Specifies an interrupt number mapping between + this GPIO controller and its interrupt parent, in the form of arbitrary + number of triplets. + +Optional properties: +- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt) + +Example: + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; + }; + +Consumer Example: + + sdhci0_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; + }; + +Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document. +Unfortunately, only the one's place is octal in the port numbering. (That is, +PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper +macro to calculate 29 * 8 + 4. diff --git a/MAINTAINERS b/MAINTAINERS index 00c8be748ed2..193b86116cd1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2017,6 +2017,7 @@ M: Masahiro Yamada L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git S: Maintained +F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt F: arch/arm/boot/dts/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h new file mode 100644 index 000000000000..9f0ad174f61c --- /dev/null +++ b/include/dt-bindings/gpio/uniphier-gpio.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + */ + +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H +#define _DT_BINDINGS_GPIO_UNIPHIER_H + +#define UNIPHIER_GPIO_LINES_PER_BANK 8 + +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) + +#define UNIPHIER_GPIO_PORT(bank, line) \ + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) + +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) + +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ -- cgit v1.2.3 From 2fbf8050dde85ed14a944035e1d7ca7eb8240eec Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 13 Oct 2017 16:26:40 +0800 Subject: dt-bindings: usb: mtk-xhci: add a optional property to disable u3ports Add a new optional property to disable u3ports Signed-off-by: Chunfeng Yun Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt index 5611a2e4ddf0..2d9b459bd890 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt @@ -38,6 +38,8 @@ Optional properties: mode; - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup control register, it depends on "mediatek,wakeup-src". + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, + bit1 for u3port1, ... etc; - vbus-supply : reference to the VBUS regulator; - usb3-lpm-capable : supports USB3.0 LPM - pinctrl-names : a pinctrl state named "default" must be defined -- cgit v1.2.3 From e7eef2ced8e7b2b4a06fd66e7d03df1f90fa67c9 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Fri, 13 Oct 2017 16:26:41 +0800 Subject: dt-bindings: usb: mtk-xhci: remove dummy clocks and add optional ones Remove dummy clocks for usb wakeup and add optional ones for MCU_BUS_CK and DMA_BUS_CK. Signed-off-by: Chunfeng Yun Acked-by: Rob Herring Reviewed-by: Matthias Brugger Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/mediatek,mtk-xhci.txt | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt index 2d9b459bd890..30595964876a 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt @@ -26,10 +26,11 @@ Required properties: - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : must contain - "sys_ck": for clock of xHCI MAC - "ref_ck": for reference clock of xHCI MAC - "wakeup_deb_p0": for USB wakeup debounce clock of port0 - "wakeup_deb_p1": for USB wakeup debounce clock of port1 + "sys_ck": controller clock used by normal mode, + the following ones are optional: + "ref_ck": reference clock used by low power mode etc, + "mcu_ck": mcu_bus clock for register access, + "dma_ck": dma_bus clock for data transfer by DMA - phys : a list of phandle + phy specifier pairs @@ -57,9 +58,7 @@ usb30: usb@11270000 { clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, <&pericfg CLK_PERI_USB0>, <&pericfg CLK_PERI_USB1>; - clock-names = "sys_ck", "ref_ck", - "wakeup_deb_p0", - "wakeup_deb_p1"; + clock-names = "sys_ck", "ref_ck"; phys = <&phy_port0 PHY_TYPE_USB3>, <&phy_port1 PHY_TYPE_USB2>; vusb33-supply = <&mt6397_vusb_reg>; @@ -91,9 +90,8 @@ Required properties: - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - - clock-names : must be - "sys_ck": for clock of xHCI MAC - "ref_ck": for reference clock of xHCI MAC + - clock-names : must contain "sys_ck", and the following ones are optional: + "ref_ck", "mcu_ck" and "dma_ck" Optional properties: - vbus-supply : reference to the VBUS regulator; -- cgit v1.2.3 From 9053f4b9855c91f8905114c2108d5397be83bcf3 Mon Sep 17 00:00:00 2001 From: Anurag Kumar Vulisha Date: Mon, 21 Aug 2017 13:17:16 +0200 Subject: devicetree: bindings: Add sata port phy config parameters in ahci-ceva This patch adds device tree bindings for sata port phy parameters in the ahci-ceva.txt file. Signed-off-by: Anurag Kumar Vulisha Signed-off-by: Michal Simek Acked-by: Rob Herring Signed-off-by: Tejun Heo --- .../devicetree/bindings/ata/ahci-ceva.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt index 7ca8b976c13a..7561cc4de371 100644 --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt @@ -5,6 +5,36 @@ Required properties: - compatible: Compatibility string. Must be 'ceva,ahci-1v84'. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. + - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0. + - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1. + The fields for the above parameter must be as shown below: + ceva,pN-cominit-params = /bits/ 8 ; + CINMP : COMINIT Negate Minimum Period. + CIBGN : COMINIT Burst Gap Nominal. + CIBGMX: COMINIT Burst Gap Maximum. + CIBGMN: COMINIT Burst Gap Minimum. + - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0. + - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1. + The fields for the above parameter must be as shown below: + ceva,pN-comwake-params = /bits/ 8 ; + CWBGMN: COMWAKE Burst Gap Minimum. + CWBGMX: COMWAKE Burst Gap Maximum. + CWBGN: COMWAKE Burst Gap Nominal. + CWNMP: COMWAKE Negate Minimum Period. + - ceva,p0-burst-params: Burst timing value for COM parameter for port 0. + - ceva,p1-burst-params: Burst timing value for COM parameter for port 1. + The fields for the above parameter must be as shown below: + ceva,pN-burst-params = /bits/ 8 ; + BMX: COM Burst Maximum. + BNM: COM Burst Nominal. + SFD: Signal Failure Detection value. + PTST: Partial to Slumber timer value. + - ceva,p0-retry-params: Retry interval timing value for port 0. + - ceva,p1-retry-params: Retry interval timing value for port 1. + The fields for the above parameter must be as shown below: + ceva,pN-retry-params = /bits/ 16 ; + RIT: Retry Interval Timer. + RCT: Rate Change Timer. Optional properties: - ceva,broken-gen2: limit to gen1 speed instead of gen2. @@ -16,5 +46,14 @@ Examples: interrupt-parent = <&gic>; interrupts = <0 133 4>; clocks = <&clkc SATA_CLK_ID>; + ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; + ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; + ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; + + ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; + ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; + ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; ceva,broken-gen2; }; -- cgit v1.2.3 From ea09ec8c444c61446fb71952c6c50c8f7e8a8731 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Tue, 24 Oct 2017 13:47:49 +0800 Subject: dt-bindings: dmaengine: Add Spreadtrum SC9860 DMA controller This patch adds the binding documentation for Spreadtrum SC9860 DMA controller device. Signed-off-by: Baolin Wang Acked-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/sprd-dma.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sprd-dma.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/sprd-dma.txt b/Documentation/devicetree/bindings/dma/sprd-dma.txt new file mode 100644 index 000000000000..7a10fea2e51b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/sprd-dma.txt @@ -0,0 +1,41 @@ +* Spreadtrum DMA controller + +This binding follows the generic DMA bindings defined in dma.txt. + +Required properties: +- compatible: Should be "sprd,sc9860-dma". +- reg: Should contain DMA registers location and length. +- interrupts: Should contain one interrupt shared by all channel. +- #dma-cells: must be <1>. Used to represent the number of integer + cells in the dmas property of client device. +- #dma-channels : Number of DMA channels supported. Should be 32. +- clock-names: Should contain the clock of the DMA controller. +- clocks: Should contain a clock specifier for each entry in clock-names. + +Example: + +Controller: +apdma: dma-controller@20100000 { + compatible = "sprd,sc9860-dma"; + reg = <0x20100000 0x4000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <32>; + clock-names = "enable"; + clocks = <&clk_ap_ahb_gates 5>; +}; + + +Client: +DMA clients connected to the Spreadtrum DMA controller must use the format +described in the dma.txt file, using a two-cell specifier for each channel. +The two cells in order are: +1. A phandle pointing to the DMA controller. +2. The channel id. + +spi0: spi@70a00000{ + ... + dma-names = "rx_chn", "tx_chn"; + dmas = <&apdma 11>, <&apdma 12>; + ... +}; -- cgit v1.2.3 From 25309004c0e761986c9dc23526a03928a85188c0 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Tue, 24 Oct 2017 11:06:41 -0700 Subject: Input: goodix - support gt1151 touchpanel Support was added based on Goodix GitHub repo [1]. There are two major differences between gt1151 and currently supported devices (gt9x): * CONFIG_DATA register has 0x8050 address instead of 0x8047, * config data checksum has 16-bit width instead of 8-bit. Also update goodix_i2c_test() function, so it reads ID register (which has the same address for all devices) instead of CONFIG_DATA (because its address is known only after reading ID of the device). [1] https://github.com/goodix/gt1x_driver_generic Signed-off-by: Marcin Niestroj Acked-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/goodix.txt | 3 +- drivers/input/touchscreen/goodix.c | 125 ++++++++++++++++----- 2 files changed, 100 insertions(+), 28 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt b/Documentation/devicetree/bindings/input/touchscreen/goodix.txt index c98757a69110..0c369d8ebcab 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.txt @@ -2,7 +2,8 @@ Device tree bindings for Goodix GT9xx series touchscreen controller Required properties: - - compatible : Should be "goodix,gt911" + - compatible : Should be "goodix,gt1151" + or "goodix,gt911" or "goodix,gt9110" or "goodix,gt912" or "goodix,gt927" diff --git a/drivers/input/touchscreen/goodix.c b/drivers/input/touchscreen/goodix.c index b3bbad7d2282..69d0b8cbc71f 100644 --- a/drivers/input/touchscreen/goodix.c +++ b/drivers/input/touchscreen/goodix.c @@ -31,9 +31,18 @@ #include #include +struct goodix_ts_data; + +struct goodix_chip_data { + u16 config_addr; + int config_len; + int (*check_config)(struct goodix_ts_data *, const struct firmware *); +}; + struct goodix_ts_data { struct i2c_client *client; struct input_dev *input_dev; + const struct goodix_chip_data *chip; int abs_x_max; int abs_y_max; bool swapped_x_y; @@ -41,7 +50,6 @@ struct goodix_ts_data { bool inverted_y; unsigned int max_touch_num; unsigned int int_trigger_type; - int cfg_len; struct gpio_desc *gpiod_int; struct gpio_desc *gpiod_rst; u16 id; @@ -69,7 +77,8 @@ struct goodix_ts_data { #define GOODIX_CMD_SCREEN_OFF 0x05 #define GOODIX_READ_COOR_ADDR 0x814E -#define GOODIX_REG_CONFIG_DATA 0x8047 +#define GOODIX_GT1X_REG_CONFIG_DATA 0x8050 +#define GOODIX_GT9X_REG_CONFIG_DATA 0x8047 #define GOODIX_REG_ID 0x8140 #define GOODIX_BUFFER_STATUS_READY BIT(7) @@ -79,6 +88,35 @@ struct goodix_ts_data { #define MAX_CONTACTS_LOC 5 #define TRIGGER_LOC 6 +static int goodix_check_cfg_8(struct goodix_ts_data *ts, + const struct firmware *cfg); +static int goodix_check_cfg_16(struct goodix_ts_data *ts, + const struct firmware *cfg); + +static const struct goodix_chip_data gt1x_chip_data = { + .config_addr = GOODIX_GT1X_REG_CONFIG_DATA, + .config_len = GOODIX_CONFIG_MAX_LENGTH, + .check_config = goodix_check_cfg_16, +}; + +static const struct goodix_chip_data gt911_chip_data = { + .config_addr = GOODIX_GT9X_REG_CONFIG_DATA, + .config_len = GOODIX_CONFIG_911_LENGTH, + .check_config = goodix_check_cfg_8, +}; + +static const struct goodix_chip_data gt967_chip_data = { + .config_addr = GOODIX_GT9X_REG_CONFIG_DATA, + .config_len = GOODIX_CONFIG_967_LENGTH, + .check_config = goodix_check_cfg_8, +}; + +static const struct goodix_chip_data gt9x_chip_data = { + .config_addr = GOODIX_GT9X_REG_CONFIG_DATA, + .config_len = GOODIX_CONFIG_MAX_LENGTH, + .check_config = goodix_check_cfg_8, +}; + static const unsigned long goodix_irq_flags[] = { IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING, @@ -177,22 +215,25 @@ static int goodix_i2c_write_u8(struct i2c_client *client, u16 reg, u8 value) return goodix_i2c_write(client, reg, &value, sizeof(value)); } -static int goodix_get_cfg_len(u16 id) +static const struct goodix_chip_data *goodix_get_chip_data(u16 id) { switch (id) { + case 1151: + return >1x_chip_data; + case 911: case 9271: case 9110: case 927: case 928: - return GOODIX_CONFIG_911_LENGTH; + return >911_chip_data; case 912: case 967: - return GOODIX_CONFIG_967_LENGTH; + return >967_chip_data; default: - return GOODIX_CONFIG_MAX_LENGTH; + return >9x_chip_data; } } @@ -332,25 +373,12 @@ static int goodix_request_irq(struct goodix_ts_data *ts) ts->irq_flags, ts->client->name, ts); } -/** - * goodix_check_cfg - Checks if config fw is valid - * - * @ts: goodix_ts_data pointer - * @cfg: firmware config data - */ -static int goodix_check_cfg(struct goodix_ts_data *ts, - const struct firmware *cfg) +static int goodix_check_cfg_8(struct goodix_ts_data *ts, + const struct firmware *cfg) { - int i, raw_cfg_len; + int i, raw_cfg_len = cfg->size - 2; u8 check_sum = 0; - if (cfg->size > GOODIX_CONFIG_MAX_LENGTH) { - dev_err(&ts->client->dev, - "The length of the config fw is not correct"); - return -EINVAL; - } - - raw_cfg_len = cfg->size - 2; for (i = 0; i < raw_cfg_len; i++) check_sum += cfg->data[i]; check_sum = (~check_sum) + 1; @@ -369,6 +397,48 @@ static int goodix_check_cfg(struct goodix_ts_data *ts, return 0; } +static int goodix_check_cfg_16(struct goodix_ts_data *ts, + const struct firmware *cfg) +{ + int i, raw_cfg_len = cfg->size - 3; + u16 check_sum = 0; + + for (i = 0; i < raw_cfg_len; i += 2) + check_sum += get_unaligned_be16(&cfg->data[i]); + check_sum = (~check_sum) + 1; + if (check_sum != get_unaligned_be16(&cfg->data[raw_cfg_len])) { + dev_err(&ts->client->dev, + "The checksum of the config fw is not correct"); + return -EINVAL; + } + + if (cfg->data[raw_cfg_len + 2] != 1) { + dev_err(&ts->client->dev, + "Config fw must have Config_Fresh register set"); + return -EINVAL; + } + + return 0; +} + +/** + * goodix_check_cfg - Checks if config fw is valid + * + * @ts: goodix_ts_data pointer + * @cfg: firmware config data + */ +static int goodix_check_cfg(struct goodix_ts_data *ts, + const struct firmware *cfg) +{ + if (cfg->size > GOODIX_CONFIG_MAX_LENGTH) { + dev_err(&ts->client->dev, + "The length of the config fw is not correct"); + return -EINVAL; + } + + return ts->chip->check_config(ts, cfg); +} + /** * goodix_send_cfg - Write fw config to device * @@ -384,7 +454,7 @@ static int goodix_send_cfg(struct goodix_ts_data *ts, if (error) return error; - error = goodix_i2c_write(ts->client, GOODIX_REG_CONFIG_DATA, cfg->data, + error = goodix_i2c_write(ts->client, ts->chip->config_addr, cfg->data, cfg->size); if (error) { dev_err(&ts->client->dev, "Failed to write config data: %d", @@ -511,8 +581,8 @@ static void goodix_read_config(struct goodix_ts_data *ts) u8 config[GOODIX_CONFIG_MAX_LENGTH]; int error; - error = goodix_i2c_read(ts->client, GOODIX_REG_CONFIG_DATA, - config, ts->cfg_len); + error = goodix_i2c_read(ts->client, ts->chip->config_addr, + config, ts->chip->config_len); if (error) { dev_warn(&ts->client->dev, "Error reading config (%d), using defaults\n", @@ -592,7 +662,7 @@ static int goodix_i2c_test(struct i2c_client *client) u8 test; while (retry++ < 2) { - error = goodix_i2c_read(client, GOODIX_REG_CONFIG_DATA, + error = goodix_i2c_read(client, GOODIX_REG_ID, &test, 1); if (!error) return 0; @@ -762,7 +832,7 @@ static int goodix_ts_probe(struct i2c_client *client, return error; } - ts->cfg_len = goodix_get_cfg_len(ts->id); + ts->chip = goodix_get_chip_data(ts->id); if (ts->gpiod_int && ts->gpiod_rst) { /* update device config */ @@ -891,6 +961,7 @@ MODULE_DEVICE_TABLE(acpi, goodix_acpi_match); #ifdef CONFIG_OF static const struct of_device_id goodix_of_match[] = { + { .compatible = "goodix,gt1151" }, { .compatible = "goodix,gt911" }, { .compatible = "goodix,gt9110" }, { .compatible = "goodix,gt912" }, -- cgit v1.2.3 From bbd11bddb398c4278c06892bd6498da34c47a00a Mon Sep 17 00:00:00 2001 From: Jianguo Sun Date: Mon, 23 Oct 2017 19:17:50 +0800 Subject: PCI: hisi: Add HiSilicon STB SoC PCIe controller driver Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: Jianguo Sun Signed-off-by: Shawn Guo Signed-off-by: Bjorn Helgaas --- .../bindings/pci/hisilicon-histb-pcie.txt | 68 +++ MAINTAINERS | 8 + drivers/pci/dwc/Kconfig | 10 + drivers/pci/dwc/Makefile | 1 + drivers/pci/dwc/pcie-histb.c | 470 +++++++++++++++++++++ 5 files changed, 557 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt create mode 100644 drivers/pci/dwc/pcie-histb.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt new file mode 100644 index 000000000000..c84bc027930b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -0,0 +1,68 @@ +HiSilicon STB PCIe host bridge DT description + +The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. +It shares common functions with the DesignWare PCIe core driver and inherits +common properties defined in +Documentation/devicetree/bindings/pci/designware-pcie.txt. + +Additional properties are described here: + +Required properties +- compatible: Should be one of the following strings: + "hisilicon,hi3798cv200-pcie" +- reg: Should contain sysctl, rc_dbi, config registers location and length. +- reg-names: Must include the following entries: + "control": control registers of PCIe controller; + "rc-dbi": configuration space of PCIe controller; + "config": configuration transaction space of PCIe controller. +- bus-range: PCI bus numbers covered. +- interrupts: MSI interrupt. +- interrupt-names: Must include "msi" entries. +- clocks: List of phandle and clock specifier pairs as listed in clock-names + property. +- clock-name: Must include the following entries: + "aux": auxiliary gate clock; + "pipe": pipe gate clock; + "sys": sys gate clock; + "bus": bus gate clock. +- resets: List of phandle and reset specifier pairs as listed in reset-names + property. +- reset-names: Must include the following entries: + "soft": soft reset; + "sys": sys reset; + "bus": bus reset. + +Optional properties: +- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal. +- phys: List of phandle and phy mode specifier, should be 0. +- phy-names: Must be "phy". + +Example: + pcie@f9860000 { + compatible = "hisilicon,hi3798cv200-pcie"; + reg = <0xf9860000 0x1000>, + <0xf0000000 0x2000>, + <0xf2000000 0x01000000>; + reg-names = "control", "rc-dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0 15>; + num-lanes = <1>; + ranges=<0x81000000 0 0 0xf4000000 0 0x00010000 + 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg PCIE_AUX_CLK>, + <&crg PCIE_PIPE_CLK>, + <&crg PCIE_SYS_CLK>, + <&crg PCIE_BUS_CLK>; + clock-names = "aux", "pipe", "sys", "bus"; + resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; + reset-names = "soft", "sys", "bus"; + phys = <&combphy1 PHY_TYPE_PCIE>; + phy-names = "phy"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 65b0c88d5ee0..2a3501cfd201 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10480,6 +10480,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/pcie-kirin.txt F: drivers/pci/dwc/pcie-kirin.c +PCIE DRIVER FOR HISILICON STB +M: Jianguo Sun +M: Shawn Guo +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +F: drivers/pci/dwc/pcie-histb.c + PCIE DRIVER FOR MEDIATEK M: Ryder Lee L: linux-pci@vger.kernel.org diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index 22ec82fcdea2..113e09440f85 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -169,4 +169,14 @@ config PCIE_KIRIN Say Y here if you want PCIe controller support on HiSilicon Kirin series SoCs. +config PCIE_HISI_STB + bool "HiSilicon STB SoCs PCIe controllers" + depends on ARCH_HISI + depends on PCI + depends on PCI_MSI_IRQ_DOMAIN + select PCIEPORTBUS + select PCIE_DW_HOST + help + Say Y here if you want PCIe controller support on HiSilicon STB SoCs + endmenu diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile index c61be9738cce..54f56f6e9236 100644 --- a/drivers/pci/dwc/Makefile +++ b/drivers/pci/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o +obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/dwc/pcie-histb.c b/drivers/pci/dwc/pcie-histb.c new file mode 100644 index 000000000000..33b01b734d7d --- /dev/null +++ b/drivers/pci/dwc/pcie-histb.c @@ -0,0 +1,470 @@ +/* + * PCIe host controller driver for HiSilicon STB SoCs + * + * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com + * + * Authors: Ruqiang Ju + * Jianguo Sun + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_histb_pcie(x) dev_get_drvdata((x)->dev) + +#define PCIE_SYS_CTRL0 0x0000 +#define PCIE_SYS_CTRL1 0x0004 +#define PCIE_SYS_CTRL7 0x001C +#define PCIE_SYS_CTRL13 0x0034 +#define PCIE_SYS_CTRL15 0x003C +#define PCIE_SYS_CTRL16 0x0040 +#define PCIE_SYS_CTRL17 0x0044 + +#define PCIE_SYS_STAT0 0x0100 +#define PCIE_SYS_STAT4 0x0110 + +#define PCIE_RDLH_LINK_UP BIT(5) +#define PCIE_XMLH_LINK_UP BIT(15) +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define PCIE_APP_LTSSM_ENABLE BIT(11) + +#define PCIE_DEVICE_TYPE_MASK GENMASK(31, 28) +#define PCIE_WM_EP 0 +#define PCIE_WM_LEGACY BIT(1) +#define PCIE_WM_RC BIT(30) + +#define PCIE_LTSSM_STATE_MASK GENMASK(5, 0) +#define PCIE_LTSSM_STATE_ACTIVE 0x11 + +struct histb_pcie { + struct dw_pcie *pci; + struct clk *aux_clk; + struct clk *pipe_clk; + struct clk *sys_clk; + struct clk *bus_clk; + struct phy *phy; + struct reset_control *soft_reset; + struct reset_control *sys_reset; + struct reset_control *bus_reset; + void __iomem *ctrl; + int reset_gpio; +}; + +static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg) +{ + return readl(histb_pcie->ctrl + reg); +} + +static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val) +{ + writel(val, histb_pcie->ctrl + reg); +} + +static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct histb_pcie *hipcie = to_histb_pcie(pci); + u32 val; + + val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); + if (enable) + val |= PCIE_ELBI_SLV_DBI_ENABLE; + else + val &= ~PCIE_ELBI_SLV_DBI_ENABLE; + histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val); +} + +static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct histb_pcie *hipcie = to_histb_pcie(pci); + u32 val; + + val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL1); + if (enable) + val |= PCIE_ELBI_SLV_DBI_ENABLE; + else + val &= ~PCIE_ELBI_SLV_DBI_ENABLE; + histb_pcie_writel(hipcie, PCIE_SYS_CTRL1, val); +} + +static u32 histb_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + u32 val; + + histb_pcie_dbi_r_mode(&pci->pp, true); + dw_pcie_read(base + reg, size, &val); + histb_pcie_dbi_r_mode(&pci->pp, false); + + return val; +} + +static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + histb_pcie_dbi_w_mode(&pci->pp, true); + dw_pcie_write(base + reg, size, val); + histb_pcie_dbi_w_mode(&pci->pp, false); +} + +static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where, + int size, u32 *val) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + histb_pcie_dbi_r_mode(pp, true); + ret = dw_pcie_read(pci->dbi_base + where, size, val); + histb_pcie_dbi_r_mode(pp, false); + + return ret; +} + +static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where, + int size, u32 val) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + histb_pcie_dbi_w_mode(pp, true); + ret = dw_pcie_write(pci->dbi_base + where, size, val); + histb_pcie_dbi_w_mode(pp, false); + + return ret; +} + +static int histb_pcie_link_up(struct dw_pcie *pci) +{ + struct histb_pcie *hipcie = to_histb_pcie(pci); + u32 regval; + u32 status; + + regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0); + status = histb_pcie_readl(hipcie, PCIE_SYS_STAT4); + status &= PCIE_LTSSM_STATE_MASK; + if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) && + (status == PCIE_LTSSM_STATE_ACTIVE)) + return 1; + + return 0; +} + +static int histb_pcie_establish_link(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct histb_pcie *hipcie = to_histb_pcie(pci); + u32 regval; + + if (dw_pcie_link_up(pci)) { + dev_info(pci->dev, "Link already up\n"); + return 0; + } + + /* PCIe RC work mode */ + regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); + regval &= ~PCIE_DEVICE_TYPE_MASK; + regval |= PCIE_WM_RC; + histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval); + + /* setup root complex */ + dw_pcie_setup_rc(pp); + + /* assert LTSSM enable */ + regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7); + regval |= PCIE_APP_LTSSM_ENABLE; + histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval); + + return dw_pcie_wait_for_link(pci); +} + +static int histb_pcie_host_init(struct pcie_port *pp) +{ + histb_pcie_establish_link(pp); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + dw_pcie_msi_init(pp); + + return 0; +} + +static struct dw_pcie_host_ops histb_pcie_host_ops = { + .rd_own_conf = histb_pcie_rd_own_conf, + .wr_own_conf = histb_pcie_wr_own_conf, + .host_init = histb_pcie_host_init, +}; + +static irqreturn_t histb_pcie_msi_irq_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + + return dw_handle_msi_irq(pp); +} + +static void histb_pcie_host_disable(struct histb_pcie *hipcie) +{ + reset_control_assert(hipcie->soft_reset); + reset_control_assert(hipcie->sys_reset); + reset_control_assert(hipcie->bus_reset); + + clk_disable_unprepare(hipcie->aux_clk); + clk_disable_unprepare(hipcie->pipe_clk); + clk_disable_unprepare(hipcie->sys_clk); + clk_disable_unprepare(hipcie->bus_clk); + + if (gpio_is_valid(hipcie->reset_gpio)) + gpio_set_value_cansleep(hipcie->reset_gpio, 0); +} + +static int histb_pcie_host_enable(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct histb_pcie *hipcie = to_histb_pcie(pci); + struct device *dev = pci->dev; + int ret; + + /* power on PCIe device if have */ + if (gpio_is_valid(hipcie->reset_gpio)) + gpio_set_value_cansleep(hipcie->reset_gpio, 1); + + ret = clk_prepare_enable(hipcie->bus_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable bus clk\n"); + goto err_bus_clk; + } + + ret = clk_prepare_enable(hipcie->sys_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable sys clk\n"); + goto err_sys_clk; + } + + ret = clk_prepare_enable(hipcie->pipe_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable pipe clk\n"); + goto err_pipe_clk; + } + + ret = clk_prepare_enable(hipcie->aux_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable aux clk\n"); + goto err_aux_clk; + } + + reset_control_assert(hipcie->soft_reset); + reset_control_deassert(hipcie->soft_reset); + + reset_control_assert(hipcie->sys_reset); + reset_control_deassert(hipcie->sys_reset); + + reset_control_assert(hipcie->bus_reset); + reset_control_deassert(hipcie->bus_reset); + + return 0; + +err_aux_clk: + clk_disable_unprepare(hipcie->aux_clk); +err_pipe_clk: + clk_disable_unprepare(hipcie->pipe_clk); +err_sys_clk: + clk_disable_unprepare(hipcie->sys_clk); +err_bus_clk: + clk_disable_unprepare(hipcie->bus_clk); + + return ret; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .read_dbi = histb_pcie_read_dbi, + .write_dbi = histb_pcie_write_dbi, + .link_up = histb_pcie_link_up, +}; + +static int histb_pcie_probe(struct platform_device *pdev) +{ + struct histb_pcie *hipcie; + struct dw_pcie *pci; + struct pcie_port *pp; + struct resource *res; + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + enum of_gpio_flags of_flags; + unsigned long flag = GPIOF_DIR_OUT; + int ret; + + hipcie = devm_kzalloc(dev, sizeof(*hipcie), GFP_KERNEL); + if (!hipcie) + return -ENOMEM; + + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + hipcie->pci = pci; + pp = &pci->pp; + pci->dev = dev; + pci->ops = &dw_pcie_ops; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); + hipcie->ctrl = devm_ioremap_resource(dev, res); + if (IS_ERR(hipcie->ctrl)) { + dev_err(dev, "cannot get control reg base\n"); + return PTR_ERR(hipcie->ctrl); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc-dbi"); + pci->dbi_base = devm_ioremap_resource(dev, res); + if (IS_ERR(pci->dbi_base)) { + dev_err(dev, "cannot get rc-dbi base\n"); + return PTR_ERR(pci->dbi_base); + } + + hipcie->reset_gpio = of_get_named_gpio_flags(np, + "reset-gpios", 0, &of_flags); + if (of_flags & OF_GPIO_ACTIVE_LOW) + flag |= GPIOF_ACTIVE_LOW; + if (gpio_is_valid(hipcie->reset_gpio)) { + ret = devm_gpio_request_one(dev, hipcie->reset_gpio, + flag, "PCIe device power control"); + if (ret) { + dev_err(dev, "unable to request gpio\n"); + return ret; + } + } + + hipcie->aux_clk = devm_clk_get(dev, "aux"); + if (IS_ERR(hipcie->aux_clk)) { + dev_err(dev, "Failed to get PCIe aux clk\n"); + return PTR_ERR(hipcie->aux_clk); + } + + hipcie->pipe_clk = devm_clk_get(dev, "pipe"); + if (IS_ERR(hipcie->pipe_clk)) { + dev_err(dev, "Failed to get PCIe pipe clk\n"); + return PTR_ERR(hipcie->pipe_clk); + } + + hipcie->sys_clk = devm_clk_get(dev, "sys"); + if (IS_ERR(hipcie->sys_clk)) { + dev_err(dev, "Failed to get PCIEe sys clk\n"); + return PTR_ERR(hipcie->sys_clk); + } + + hipcie->bus_clk = devm_clk_get(dev, "bus"); + if (IS_ERR(hipcie->bus_clk)) { + dev_err(dev, "Failed to get PCIe bus clk\n"); + return PTR_ERR(hipcie->bus_clk); + } + + hipcie->soft_reset = devm_reset_control_get(dev, "soft"); + if (IS_ERR(hipcie->soft_reset)) { + dev_err(dev, "couldn't get soft reset\n"); + return PTR_ERR(hipcie->soft_reset); + } + + hipcie->sys_reset = devm_reset_control_get(dev, "sys"); + if (IS_ERR(hipcie->sys_reset)) { + dev_err(dev, "couldn't get sys reset\n"); + return PTR_ERR(hipcie->sys_reset); + } + + hipcie->bus_reset = devm_reset_control_get(dev, "bus"); + if (IS_ERR(hipcie->bus_reset)) { + dev_err(dev, "couldn't get bus reset\n"); + return PTR_ERR(hipcie->bus_reset); + } + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + pp->msi_irq = platform_get_irq_byname(pdev, "msi"); + if (pp->msi_irq < 0) { + dev_err(dev, "Failed to get MSI IRQ\n"); + return pp->msi_irq; + } + + ret = devm_request_irq(dev, pp->msi_irq, + histb_pcie_msi_irq_handler, + IRQF_SHARED, "histb-pcie-msi", pp); + if (ret) { + dev_err(dev, "cannot request MSI IRQ\n"); + return ret; + } + } + + hipcie->phy = devm_phy_get(dev, "phy"); + if (IS_ERR(hipcie->phy)) { + dev_info(dev, "no pcie-phy found\n"); + hipcie->phy = NULL; + /* fall through here! + * if no pcie-phy found, phy init + * should be done under boot! + */ + } else { + phy_init(hipcie->phy); + } + + pp->root_bus_nr = -1; + pp->ops = &histb_pcie_host_ops; + + platform_set_drvdata(pdev, hipcie); + + ret = histb_pcie_host_enable(pp); + if (ret) { + dev_err(dev, "failed to enable host\n"); + return ret; + } + + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "failed to initialize host\n"); + return ret; + } + + return 0; +} + +static int histb_pcie_remove(struct platform_device *pdev) +{ + struct histb_pcie *hipcie = platform_get_drvdata(pdev); + + histb_pcie_host_disable(hipcie); + + if (hipcie->phy) + phy_exit(hipcie->phy); + + return 0; +} + +static const struct of_device_id histb_pcie_of_match[] = { + { .compatible = "hisilicon,hi3798cv200-pcie", }, + {}, +}; +MODULE_DEVICE_TABLE(of, histb_pcie_of_match); + +static struct platform_driver histb_pcie_platform_driver = { + .probe = histb_pcie_probe, + .remove = histb_pcie_remove, + .driver = { + .name = "histb-pcie", + .of_match_table = histb_pcie_of_match, + }, +}; +module_platform_driver(histb_pcie_platform_driver); + +MODULE_DESCRIPTION("HiSilicon STB PCIe host controller driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 3c535c94a0ba94e9852de3aae7b6c62413eb2af7 Mon Sep 17 00:00:00 2001 From: Guochun Mao Date: Thu, 21 Sep 2017 20:45:05 +0800 Subject: dt-bindings: mtd: add new compatible strings and improve description Add "mediatak,mt2712-nor" and "mediatek,mt7622-nor" for nor flash node's compatible strings. Explicate the fallback compatible. Acked-by: Rob Herring Signed-off-by: Guochun Mao Signed-off-by: Cyrille Pitchen --- Documentation/devicetree/bindings/mtd/mtk-quadspi.txt | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt index 840f9405dcf0..56d3668e2c50 100644 --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt @@ -1,13 +1,16 @@ * Serial NOR flash controller for MTK MT81xx (and similar) Required properties: -- compatible: The possible values are: - "mediatek,mt2701-nor" - "mediatek,mt7623-nor" +- compatible: For mt8173, compatible should be "mediatek,mt8173-nor", + and it's the fallback compatible for other Soc. + For every other SoC, should contain both the SoC-specific compatible + string and "mediatek,mt8173-nor". + The possible values are: + "mediatek,mt2701-nor", "mediatek,mt8173-nor" + "mediatek,mt2712-nor", "mediatek,mt8173-nor" + "mediatek,mt7622-nor", "mediatek,mt8173-nor" + "mediatek,mt7623-nor", "mediatek,mt8173-nor" "mediatek,mt8173-nor" - For mt8173, compatible should be "mediatek,mt8173-nor". - For every other SoC, should contain both the SoC-specific compatible string - and "mediatek,mt8173-nor". - reg: physical base address and length of the controller's register - clocks: the phandle of the clocks needed by the nor controller - clock-names: the names of the clocks -- cgit v1.2.3 From 1901142ba8d5bf9f21b86d33770be8309071c25d Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Mon, 23 Oct 2017 15:16:44 +0800 Subject: dt-bindings: rtc: mediatek: add bindings for MediaTek SoC based RTC Add device-tree binding for MediaTek SoC based RTC Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/rtc-mt7622.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mt7622.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt new file mode 100644 index 000000000000..09fe8f51476f --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt @@ -0,0 +1,21 @@ +Device-Tree bindings for MediaTek SoC based RTC + +Required properties: +- compatible : Should be + "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC +- reg : Specifies base physical address and size of the registers; +- interrupts : Should contain the interrupt for RTC alarm; +- clocks : Specifies list of clock specifiers, corresponding to + entries in clock-names property; +- clock-names : Should contain "rtc" entries + +Example: + +rtc: rtc@10212800 { + compatible = "mediatek,mt7622-rtc", + "mediatek,soc-rtc"; + reg = <0 0x10212800 0 0x200>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RTC>; + clock-names = "rtc"; +}; -- cgit v1.2.3 From 7e577a17f2eefeef32f1106ebf91e7cd143ba654 Mon Sep 17 00:00:00 2001 From: Ahmet Inan Date: Sat, 14 Oct 2017 10:10:53 -0700 Subject: Input: add I2C attached EETI EXC3000 multi touch driver The 3000 series have a new protocol which allows to report up to 5 points in a single 66 byte frame. One must always read in 66 byte frames. To support up to 10 points, two consecutive frames need to be read: The first frame says how many points until sync. The second frame must say zero points or both frames must be discarded. To be able to work with the higher 400KHz I2C bus rate, one must successfully send a special package prior _each_ read or the controller will refuse to cooperate. This is a minimal implementation based on egalax_i2c.c (which can be found on the internet) and egalax_ts.c but without the vendor interface and no power management support. Signed-off-by: Ahmet Inan Acked-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/exc3000.txt | 27 +++ drivers/input/touchscreen/Kconfig | 10 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/exc3000.c | 223 +++++++++++++++++++++ 4 files changed, 261 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/exc3000.txt create mode 100644 drivers/input/touchscreen/exc3000.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt b/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt new file mode 100644 index 000000000000..1dcff4a43eaa --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt @@ -0,0 +1,27 @@ +* EETI EXC3000 Multiple Touch Controller + +Required properties: +- compatible: must be "eeti,exc3000" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller +- interrupts: touch controller interrupt +- touchscreen-size-x: See touchscreen.txt +- touchscreen-size-y: See touchscreen.txt + +Optional properties: +- touchscreen-inverted-x: See touchscreen.txt +- touchscreen-inverted-y: See touchscreen.txt +- touchscreen-swapped-x-y: See touchscreen.txt + +Example: + + touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + }; diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 16cadc149bbc..26a66bc7b2df 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -316,6 +316,16 @@ config TOUCHSCREEN_EGALAX_SERIAL To compile this driver as a module, choose M here: the module will be called egalax_ts_serial. +config TOUCHSCREEN_EXC3000 + tristate "EETI EXC3000 multi-touch panel support" + depends on I2C + help + Say Y here to enable support for I2C connected EETI + EXC3000 multi-touch panels. + + To compile this driver as a module, choose M here: the + module will be called exc3000. + config TOUCHSCREEN_FUJITSU tristate "Fujitsu serial touchscreen" select SERIO diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 6badce87037b..a129df6b2300 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_TOUCHSCREEN_ELAN) += elants_i2c.o obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o obj-$(CONFIG_TOUCHSCREEN_EGALAX_SERIAL) += egalax_ts_serial.o +obj-$(CONFIG_TOUCHSCREEN_EXC3000) += exc3000.o obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o diff --git a/drivers/input/touchscreen/exc3000.c b/drivers/input/touchscreen/exc3000.c new file mode 100644 index 000000000000..37437a53cd1a --- /dev/null +++ b/drivers/input/touchscreen/exc3000.c @@ -0,0 +1,223 @@ +/* + * Driver for I2C connected EETI EXC3000 multiple touch controller + * + * Copyright (C) 2017 Ahmet Inan + * + * minimal implementation based on egalax_ts.c and egalax_i2c.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EXC3000_NUM_SLOTS 10 +#define EXC3000_SLOTS_PER_FRAME 5 +#define EXC3000_LEN_FRAME 66 +#define EXC3000_LEN_POINT 10 +#define EXC3000_MT_EVENT 6 +#define EXC3000_TIMEOUT_MS 100 + +struct exc3000_data { + struct i2c_client *client; + struct input_dev *input; + struct touchscreen_properties prop; + struct timer_list timer; + u8 buf[2 * EXC3000_LEN_FRAME]; +}; + +static void exc3000_report_slots(struct input_dev *input, + struct touchscreen_properties *prop, + const u8 *buf, int num) +{ + for (; num--; buf += EXC3000_LEN_POINT) { + if (buf[0] & BIT(0)) { + input_mt_slot(input, buf[1]); + input_mt_report_slot_state(input, MT_TOOL_FINGER, true); + touchscreen_report_pos(input, prop, + get_unaligned_le16(buf + 2), + get_unaligned_le16(buf + 4), + true); + } + } +} + +static void exc3000_timer(struct timer_list *t) +{ + struct exc3000_data *data = from_timer(data, t, timer); + + input_mt_sync_frame(data->input); + input_sync(data->input); +} + +static int exc3000_read_frame(struct i2c_client *client, u8 *buf) +{ + int ret; + + ret = i2c_master_send(client, "'", 2); + if (ret < 0) + return ret; + + if (ret != 2) + return -EIO; + + ret = i2c_master_recv(client, buf, EXC3000_LEN_FRAME); + if (ret < 0) + return ret; + + if (ret != EXC3000_LEN_FRAME) + return -EIO; + + if (get_unaligned_le16(buf) != EXC3000_LEN_FRAME || + buf[2] != EXC3000_MT_EVENT) + return -EINVAL; + + return 0; +} + +static int exc3000_read_data(struct i2c_client *client, + u8 *buf, int *n_slots) +{ + int error; + + error = exc3000_read_frame(client, buf); + if (error) + return error; + + *n_slots = buf[3]; + if (!*n_slots || *n_slots > EXC3000_NUM_SLOTS) + return -EINVAL; + + if (*n_slots > EXC3000_SLOTS_PER_FRAME) { + /* Read 2nd frame to get the rest of the contacts. */ + error = exc3000_read_frame(client, buf + EXC3000_LEN_FRAME); + if (error) + return error; + + /* 2nd chunk must have number of contacts set to 0. */ + if (buf[EXC3000_LEN_FRAME + 3] != 0) + return -EINVAL; + } + + return 0; +} + +static irqreturn_t exc3000_interrupt(int irq, void *dev_id) +{ + struct exc3000_data *data = dev_id; + struct input_dev *input = data->input; + u8 *buf = data->buf; + int slots, total_slots; + int error; + + error = exc3000_read_data(data->client, buf, &total_slots); + if (error) { + /* Schedule a timer to release "stuck" contacts */ + mod_timer(&data->timer, + jiffies + msecs_to_jiffies(EXC3000_TIMEOUT_MS)); + goto out; + } + + /* + * We read full state successfully, no contacts will be "stuck". + */ + del_timer_sync(&data->timer); + + while (total_slots > 0) { + slots = min(total_slots, EXC3000_SLOTS_PER_FRAME); + exc3000_report_slots(input, &data->prop, buf + 4, slots); + total_slots -= slots; + buf += EXC3000_LEN_FRAME; + } + + input_mt_sync_frame(input); + input_sync(input); + +out: + return IRQ_HANDLED; +} + +static int exc3000_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct exc3000_data *data; + struct input_dev *input; + int error; + + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + timer_setup(&data->timer, exc3000_timer, 0); + + input = devm_input_allocate_device(&client->dev); + if (!input) + return -ENOMEM; + + data->input = input; + + input->name = "EETI EXC3000 Touch Screen"; + input->id.bustype = BUS_I2C; + + input_set_abs_params(input, ABS_MT_POSITION_X, 0, 4095, 0, 0); + input_set_abs_params(input, ABS_MT_POSITION_Y, 0, 4095, 0, 0); + touchscreen_parse_properties(input, true, &data->prop); + + error = input_mt_init_slots(input, EXC3000_NUM_SLOTS, + INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED); + if (error) + return error; + + error = input_register_device(input); + if (error) + return error; + + error = devm_request_threaded_irq(&client->dev, client->irq, + NULL, exc3000_interrupt, IRQF_ONESHOT, + client->name, data); + if (error) + return error; + + return 0; +} + +static const struct i2c_device_id exc3000_id[] = { + { "exc3000", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, exc3000_id); + +#ifdef CONFIG_OF +static const struct of_device_id exc3000_of_match[] = { + { .compatible = "eeti,exc3000" }, + { } +}; +MODULE_DEVICE_TABLE(of, exc3000_of_match); +#endif + +static struct i2c_driver exc3000_driver = { + .driver = { + .name = "exc3000", + .of_match_table = of_match_ptr(exc3000_of_match), + }, + .id_table = exc3000_id, + .probe = exc3000_probe, +}; + +module_i2c_driver(exc3000_driver); + +MODULE_AUTHOR("Ahmet Inan "); +MODULE_DESCRIPTION("I2C connected EETI EXC3000 multiple touch controller driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 50be28a654ff04b282dfcb06ad5d0b20556242cb Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 1 Oct 2017 15:45:52 +0200 Subject: dt-bindings: Add vendor prefix for MeLE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MeLE is a Chinese manufacturer of TV boxes and Mini PCs. Cc: meleservice@mele.cn Acked-by: Rob Herring Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index d17d01a160de..3618b23fa067 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -197,6 +197,7 @@ mcube mCube meas Measurement Specialties mediatek MediaTek Inc. megachips MegaChips +mele Shenzhen MeLE Digital Technology Ltd. melexis Melexis N.V. melfas MELFAS Inc. mellanox Mellanox Technologies -- cgit v1.2.3 From d109cbf1842fbfca57ab33323ca63be48a8efa53 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 16 Oct 2017 04:45:54 +0200 Subject: dt-bindings: arm: realtek: Document MeLE V9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define a compatible string for MeLE V9 Media Player. Cc: meleservice@mele.cn Acked-by: Rob Herring Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/arm/realtek.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/realtek.txt b/Documentation/devicetree/bindings/arm/realtek.txt index 297c15eb81e2..95839e19ae92 100644 --- a/Documentation/devicetree/bindings/arm/realtek.txt +++ b/Documentation/devicetree/bindings/arm/realtek.txt @@ -12,6 +12,7 @@ Required root node properties: Root node property compatible must contain, depending on board: + - MeLE V9: "mele,v9" - ProBox2 AVA: "probox2,ava" - Zidoo X9S: "zidoo,x9s" -- cgit v1.2.3 From 3fa30ae9ff4a29e677b4800036f755517a27dd9e Mon Sep 17 00:00:00 2001 From: Marco Franchi Date: Wed, 25 Oct 2017 15:24:50 -0200 Subject: ASoC: sgtl5000: Remove leading zero from '@0a' notation Improve the binding example by removing the leading 0 from '@0a' notation, which fixes the following build warning: Warning (unit_address_format): Node /sgtl5000@0a unit name should not have leading 0s Signed-off-by: Marco Franchi Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/sgtl5000.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt index 7a73a9d62015..060cb4a3b47e 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt @@ -37,7 +37,7 @@ VDDIO 1.8V 2.5V 3.3V Example: -codec: sgtl5000@0a { +codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks 150>; -- cgit v1.2.3 From 26284ca918e4e271bae4e96129fc3791b9bf0983 Mon Sep 17 00:00:00 2001 From: Marco Franchi Date: Wed, 25 Oct 2017 16:57:13 -0200 Subject: ASoC: pfuze100: Remove leading zero from '@08' notation Improve the binding example by removing the leading 0 from '@08' notation, which fixes the following build warnings: Warning (unit_address_format): Node /pfuze100@08 unit name should not have leading 0s Warning (unit_address_format): Node /pfuze200@08 unit name should not have leading 0s Warning (unit_address_format): Node /pfuze3000@08 unit name should not have leading 0s Signed-off-by: Marco Franchi Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/pfuze100.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt index 444c47831a40..c6dd3f5e485b 100644 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt @@ -21,7 +21,7 @@ Each regulator is defined using the standard binding for regulators. Example 1: PFUZE100 - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -122,7 +122,7 @@ Example 1: PFUZE100 Example 2: PFUZE200 - pmic: pfuze200@08 { + pmic: pfuze200@8 { compatible = "fsl,pfuze200"; reg = <0x08>; @@ -216,7 +216,7 @@ Example 2: PFUZE200 Example 3: PFUZE3000 - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; -- cgit v1.2.3 From b2b60bcc7d0940f02858b1721499df9674f685e5 Mon Sep 17 00:00:00 2001 From: Leon Luo Date: Thu, 5 Oct 2017 02:06:20 +0200 Subject: media: imx274: device tree binding file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding file for imx274 CMOS sensor V4l2 driver Signed-off-by: Leon Luo Acked-by: Sören Brinkmann Acked-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/imx274.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/imx274.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/imx274.txt b/Documentation/devicetree/bindings/media/i2c/imx274.txt new file mode 100644 index 000000000000..80f2e89568e1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/imx274.txt @@ -0,0 +1,33 @@ +* Sony 1/2.5-Inch 8.51Mp CMOS Digital Image Sensor + +The Sony imx274 is a 1/2.5-inch CMOS active pixel digital image sensor with +an active array size of 3864H x 2202V. It is programmable through I2C +interface. The I2C address is fixed to 0x1a as per sensor data sheet. +Image data is sent through MIPI CSI-2, which is configured as 4 lanes +at 1440 Mbps. + + +Required Properties: +- compatible: value should be "sony,imx274" for imx274 sensor +- reg: I2C bus address of the device + +Optional Properties: +- reset-gpios: Sensor reset GPIO + +The imx274 device node should contain one 'port' child node with +an 'endpoint' subnode. For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + sensor@1a { + compatible = "sony,imx274"; + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio_sensor 0 0>; + port { + sensor_out: endpoint { + remote-endpoint = <&csiss_in>; + }; + }; + }; -- cgit v1.2.3 From d524b8fc75f1ad8132b6661b48a8cbfba37ecc2b Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sat, 15 Jul 2017 10:51:24 +0200 Subject: media: dt-bindings: document the tegra CEC bindings This documents the binding for the Tegra CEC module. Signed-off-by: Hans Verkuil Acked-by: Rob Herring Acked-by: Thierry Reding Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/tegra-cec.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/tegra-cec.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/tegra-cec.txt b/Documentation/devicetree/bindings/media/tegra-cec.txt new file mode 100644 index 000000000000..c503f06f3b84 --- /dev/null +++ b/Documentation/devicetree/bindings/media/tegra-cec.txt @@ -0,0 +1,27 @@ +* Tegra HDMI CEC hardware + +The HDMI CEC module is present in Tegra SoCs and its purpose is to +handle communication between HDMI connected devices over the CEC bus. + +Required properties: + - compatible : value should be one of the following: + "nvidia,tegra114-cec" + "nvidia,tegra124-cec" + "nvidia,tegra210-cec" + - reg : Physical base address of the IP registers and length of memory + mapped region. + - interrupts : HDMI CEC interrupt number to the CPU. + - clocks : from common clock binding: handle to HDMI CEC clock. + - clock-names : from common clock binding: must contain "cec", + corresponding to the entry in the clocks property. + - hdmi-phandle : phandle to the HDMI controller, see also cec.txt. + +Example: + +cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; +}; -- cgit v1.2.3 From fcc046801b934ad27ba80e20e3e0f4c97957af58 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 21 Sep 2017 14:52:29 +0200 Subject: dt-bindings: i2c: i2c-mux: spelling s/required is/required if/ Fix both instances. Signed-off-by: Geert Uytterhoeven Signed-off-by: Peter Rosin --- Documentation/devicetree/bindings/i2c/i2c-mux.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt index 212e6779dc5c..b38f58a1c878 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux.txt @@ -6,10 +6,10 @@ multiplexer/switch will have one child node for each child bus. Optional properties: - #address-cells = <1>; - This property is required is the i2c-mux child node does not exist. + This property is required if the i2c-mux child node does not exist. - #size-cells = <0>; - This property is required is the i2c-mux child node does not exist. + This property is required if the i2c-mux child node does not exist. - i2c-mux For i2c multiplexers/switches that have child nodes that are a mixture -- cgit v1.2.3 From 69d17246ab255dda8e71c8d65396b4aa6121b7ad Mon Sep 17 00:00:00 2001 From: Phil Reid Date: Thu, 24 Aug 2017 17:31:03 +0800 Subject: i2c: i2c-smbus: add of_i2c_setup_smbus_alert This commit adds of_i2c_setup_smbus_alert which allows the smbalert driver to be attached to an i2c adapter via the device tree. Signed-off-by: Phil Reid Acked-by: Rob Herring Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c.txt | 4 ++-- drivers/i2c/i2c-core-smbus.c | 22 ++++++++++++++++++++++ drivers/i2c/i2c-smbus.c | 10 +++++++++- include/linux/i2c-smbus.h | 9 +++++++++ 4 files changed, 42 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt index cee9d5055fa2..11263982470e 100644 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c.txt @@ -59,8 +59,8 @@ wants to support one of the below features, it should adapt the bindings below. interrupts used by the device. - interrupt-names - "irq" and "wakeup" names are recognized by I2C core, other names are - left to individual drivers. + "irq", "wakeup" and "smbus_alert" names are recognized by I2C core, + other names are left to individual drivers. - host-notify device uses SMBus host notify protocol instead of interrupt line. diff --git a/drivers/i2c/i2c-core-smbus.c b/drivers/i2c/i2c-core-smbus.c index 7f3ec02f085a..4bb9927afd01 100644 --- a/drivers/i2c/i2c-core-smbus.c +++ b/drivers/i2c/i2c-core-smbus.c @@ -625,3 +625,25 @@ struct i2c_client *i2c_setup_smbus_alert(struct i2c_adapter *adapter, return i2c_new_device(adapter, &ara_board_info); } EXPORT_SYMBOL_GPL(i2c_setup_smbus_alert); + +#if IS_ENABLED(CONFIG_I2C_SMBUS) && IS_ENABLED(CONFIG_OF) +int of_i2c_setup_smbus_alert(struct i2c_adapter *adapter) +{ + struct i2c_client *client; + int irq; + + irq = of_property_match_string(adapter->dev.of_node, "interrupt-names", + "smbus_alert"); + if (irq == -EINVAL || irq == -ENODATA) + return 0; + else if (irq < 0) + return irq; + + client = i2c_setup_smbus_alert(adapter, NULL); + if (!client) + return -ENODEV; + + return 0; +} +EXPORT_SYMBOL_GPL(of_i2c_setup_smbus_alert); +#endif diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c index d0bb0358b578..5a1dd7f13bac 100644 --- a/drivers/i2c/i2c-smbus.c +++ b/drivers/i2c/i2c-smbus.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -139,7 +140,14 @@ static int smbalert_probe(struct i2c_client *ara, if (!alert) return -ENOMEM; - irq = setup->irq; + if (setup) { + irq = setup->irq; + } else { + irq = of_irq_get_byname(adapter->dev.of_node, "smbus_alert"); + if (irq <= 0) + return irq; + } + INIT_WORK(&alert->alert, smbalert_work); alert->ara = ara; diff --git a/include/linux/i2c-smbus.h b/include/linux/i2c-smbus.h index 19efbd14e812..fb0e040b1abb 100644 --- a/include/linux/i2c-smbus.h +++ b/include/linux/i2c-smbus.h @@ -49,4 +49,13 @@ struct i2c_client *i2c_setup_smbus_alert(struct i2c_adapter *adapter, struct i2c_smbus_alert_setup *setup); int i2c_handle_smbus_alert(struct i2c_client *ara); +#if IS_ENABLED(CONFIG_I2C_SMBUS) && IS_ENABLED(CONFIG_OF) +int of_i2c_setup_smbus_alert(struct i2c_adapter *adap); +#else +static inline int of_i2c_setup_smbus_alert(struct i2c_adapter *adap) +{ + return 0; +} +#endif + #endif /* _LINUX_I2C_SMBUS_H */ -- cgit v1.2.3 From 26b61a652f6d52ec9c14f6be7c5a854a4fe831ae Mon Sep 17 00:00:00 2001 From: Karl-Heinz Schneider Date: Thu, 24 Aug 2017 17:31:07 +0800 Subject: Documentation: Add sbs-manager device tree node documentation This patch adds device tree documentation for the sbs-manager Signed-off-by: Karl-Heinz Schneider Signed-off-by: Phil Reid Acked-by: Rob Herring Reviewed-by: Sebastian Reichel Signed-off-by: Wolfram Sang --- .../bindings/power/supply/sbs,sbs-manager.txt | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt b/Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt new file mode 100644 index 000000000000..4b2195571a49 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.txt @@ -0,0 +1,66 @@ +Binding for sbs-manager + +Required properties: +- compatible: ",", "sbs,sbs-charger" as fallback. The part + number compatible string might be used in order to take care of vendor + specific registers. +- reg: integer, i2c address of the device. Should be <0xa>. +Optional properties: +- gpio-controller: Marks the port as GPIO controller. + See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. +- #gpio-cells: Should be <2>. The first cell is the pin number, the second cell + is used to specify optional parameters: + See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. + +From OS view the device is basically an i2c-mux used to communicate with up to +four smart battery devices at address 0xb. The driver actually implements this +behaviour. So standard i2c-mux nodes can be used to register up to four slave +batteries. Channels will be numerated starting from 1 to 4. + +Example: + +batman@a { + compatible = "lltc,ltc1760", "sbs,sbs-manager"; + reg = <0x0a>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + battery@b { + compatible = "ti,bq2060", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&batman 1 1>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + battery@b { + compatible = "ti,bq2060", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&batman 2 1>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + battery@b { + compatible = "ti,bq2060", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&batman 3 1>; + }; + }; +}; -- cgit v1.2.3 From 8fca9e95243128961357577ba394ec1d4bd8c92c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sat, 28 Oct 2017 18:40:17 +0200 Subject: dt-bindings: power: add amlogic meson power domain bindings Acked-by: Rob Herring Signed-off-by: Neil Armstrong [khilman: minor whitespace fixups] Signed-off-by: Kevin Hilman --- .../bindings/power/amlogic,meson-gx-pwrc.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt new file mode 100644 index 000000000000..1cd050b4054c --- /dev/null +++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt @@ -0,0 +1,61 @@ +Amlogic Meson Power Controller +============================== + +The Amlogic Meson SoCs embeds an internal Power domain controller. + +VPU Power Domain +---------------- + +The Video Processing Unit power domain is controlled by this power controller, +but the domain requires some external resources to meet the correct power +sequences. +The bindings must respect the power domain bindings as described in the file +power_domain.txt + +Device Tree Bindings: +--------------------- + +Required properties: +- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs +- #power-domain-cells: should be 0 +- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node +- resets: phandles to the reset lines needed for this power demain sequence + as described in ../reset/reset.txt +- clocks: from common clock binding: handle to VPU and VAPB clocks +- clock-names: from common clock binding: must contain "vpu", "vapb" + corresponding to entry in the clocks property. + +Parent node should have the following properties : +- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" +- reg: base address and size of the AO system control register space. + +Example: +------- + +ao_sysctrl: sys-ctrl@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + reg = <0x0 0x0 0x0 0x100>; + + pwrc_vpu: power-controller-vpu { + compatible = "amlogic,meson-gx-pwrc-vpu"; + #power-domain-cells = <0>; + amlogic,hhi-sysctrl = <&sysctrl>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_BT656>, + <&reset RESET_DVIN_RESET>, + <&reset RESET_RDMA>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC>, + <&reset RESET_VDI6>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + }; +}; + + -- cgit v1.2.3 From 9c52aaf756ecaec195517e17875b136eb4d176bf Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sun, 17 Sep 2017 18:45:18 +0200 Subject: dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation With this patch we add documentation for: * power-management-unit: the PMU is used to bring up the cores during SMP operations * sram: among other things the sram is used to store the first code executed by the core when it is powered up * cpu-enable-method: the CPU enable method used by Amlogic Meson8 and Meson8b SoCs Signed-off-by: Carlo Caione [also add Meson8 to the documentation] Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic/pmu.txt | 18 ++++++++++++ .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 ++++++++++++++++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 2 ++ 3 files changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file mode 100644 index 000000000000..72f8d08198b6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt @@ -0,0 +1,18 @@ +Amlogic Meson8 and Meson8b power-management-unit: +------------------------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : depending on the SoC this should be one of: + "amlogic,meson8-pmu" + "amlogic,meson8b-pmu" +- reg : physical base address and the size of the registers window + +Example: + + pmu@c81000e4 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xc81000e0 0x18>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt new file mode 100644 index 000000000000..3473ddaadfac --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt @@ -0,0 +1,32 @@ +Amlogic Meson8 and Meson8b SRAM for smp bringup: +------------------------------------------------ + +Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. +Once the core gets powered up it executes the code that is residing at a +specific location. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Required sub-node properties: +- compatible : depending on the SoC this should be one of: + "amlogic,meson8-smp-sram" + "amlogic,meson8b-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram: sram@d9000000 { + compatible = "mmio-sram"; + reg = <0xd9000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd9000000 0x20000>; + + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index b92f12bd5244..a0009b72e9be 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -197,6 +197,8 @@ described below. "actions,s500-smp" "allwinner,sun6i-a31" "allwinner,sun8i-a23" + "amlogic,meson8-smp" + "amlogic,meson8b-smp" "arm,realview-smp" "brcm,bcm11351-cpu-method" "brcm,bcm23550" -- cgit v1.2.3 From 282e45dc64d1832c9b51d2c6f6eb0a634c924fa7 Mon Sep 17 00:00:00 2001 From: Philipp Puschmann Date: Thu, 19 Oct 2017 10:12:47 +0200 Subject: mtd: spi-nor: Add support for mr25h128 Add Everspin mr25h128 16KB MRAM to the list of supported chips. Signed-off-by: Philipp Puschmann Signed-off-by: Cyrille Pitchen --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 1 + drivers/mtd/devices/m25p80.c | 1 + drivers/mtd/spi-nor/spi-nor.c | 1 + 3 files changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt index 9ce35af8507c..956bb046e599 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt @@ -13,6 +13,7 @@ Required properties: at25df321a at25df641 at26df081a + mr25h128 mr25h256 mr25h10 mr25h40 diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 00eea6fd379c..dbe6a1de2bb8 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -359,6 +359,7 @@ static const struct spi_device_id m25p_ids[] = { {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, /* Everspin MRAMs (non-JEDEC) */ + { "mr25h128" }, /* 128 Kib, 40 MHz */ { "mr25h256" }, /* 256 Kib, 40 MHz */ { "mr25h10" }, /* 1 Mib, 40 MHz */ { "mr25h40" }, /* 4 Mib, 40 MHz */ diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 31d308ab51cd..bc266f70a15b 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -968,6 +968,7 @@ static const struct flash_info spi_nor_ids[] = { { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) }, /* Everspin */ + { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, -- cgit v1.2.3 From 0ec54a2e8ee22b13e9a89dfd76e66e5b75ca9885 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Mon, 11 Sep 2017 14:16:48 -0500 Subject: dt-bindings: hwmon: add compatible for max1619 Add new device tree bindings document for max1619 device including a new compatible string. Signed-off-by: Alan Tull Cc: Jean Delvare Cc: Guenter Roeck Cc: Rob Herring Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/max1619.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/max1619.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/max1619.txt b/Documentation/devicetree/bindings/hwmon/max1619.txt new file mode 100644 index 000000000000..c70dbbe1e56f --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/max1619.txt @@ -0,0 +1,12 @@ +Bindings for MAX1619 Temperature Sensor + +Required properties: +- compatible : "maxim,max1619" +- reg : I2C address, one of 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, or + 0x4d, 0x4e + +Example: + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; -- cgit v1.2.3 From 24fae2b5b61da0cec6b94059552ae97ccc498ccc Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Tue, 3 Oct 2017 18:08:28 +0000 Subject: Documentation: devicetree: add max6621 device Add device record for Maxim MAX6621 temperature sensor device. Signed-off-by: Vadim Pasternak Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/trivial-devices.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index af284fbd4d23..8bcac6ee73da 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -71,6 +71,7 @@ isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs +maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface mc,rv3029c2 Real Time Clock Module with I2C-Bus mcube,mc3230 mCube 3-axis 8-bit digital accelerometer -- cgit v1.2.3 From 9dfe310ed5f0802cba5ec29f2b5f5f92ba8ad9e9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 26 Sep 2017 01:09:03 +0200 Subject: hwmon: (gpio-fan) Move DT bindings to the right place This moves the GPIO fan bindings to the hwmon bindings. The GPIO fan is a hwmon class hardware, not related to GPIO other than being a consumer of GPIOs. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- .../devicetree/bindings/gpio/gpio-fan.txt | 40 ---------------------- .../devicetree/bindings/hwmon/gpio-fan.txt | 40 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-fan.txt create mode 100644 Documentation/devicetree/bindings/hwmon/gpio-fan.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt deleted file mode 100644 index 439a7430fc68..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-fan.txt +++ /dev/null @@ -1,40 +0,0 @@ -Bindings for fan connected to GPIO lines - -Required properties: -- compatible : "gpio-fan" - -Optional properties: -- gpios: Specifies the pins that map to bits in the control value, - ordered MSB-->LSB. -- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the - control value that should be set to achieve them. This array - must have the RPM values in ascending order. -- alarm-gpios: This pin going active indicates something is wrong with - the fan, and a udev event will be fired. -- cooling-cells: If used as a cooling device, must be <2> - Also see: Documentation/devicetree/bindings/thermal/thermal.txt - min and max states are derived from the speed-map of the fan. - -Note: At least one the "gpios" or "alarm-gpios" properties must be set. - -Examples: - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio1 14 1 - &gpio1 13 1>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - alarm-gpios = <&gpio1 15 1>; - }; - gpio_fan_cool: gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio2 14 1 - &gpio2 13 1>; - gpio-fan,speed-map = <0 0>, - <3000 1>, - <6000 2>; - alarm-gpios = <&gpio2 15 1>; - #cooling-cells = <2>; /* min followed by max */ - }; diff --git a/Documentation/devicetree/bindings/hwmon/gpio-fan.txt b/Documentation/devicetree/bindings/hwmon/gpio-fan.txt new file mode 100644 index 000000000000..439a7430fc68 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/gpio-fan.txt @@ -0,0 +1,40 @@ +Bindings for fan connected to GPIO lines + +Required properties: +- compatible : "gpio-fan" + +Optional properties: +- gpios: Specifies the pins that map to bits in the control value, + ordered MSB-->LSB. +- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the + control value that should be set to achieve them. This array + must have the RPM values in ascending order. +- alarm-gpios: This pin going active indicates something is wrong with + the fan, and a udev event will be fired. +- cooling-cells: If used as a cooling device, must be <2> + Also see: Documentation/devicetree/bindings/thermal/thermal.txt + min and max states are derived from the speed-map of the fan. + +Note: At least one the "gpios" or "alarm-gpios" properties must be set. + +Examples: + + gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio1 14 1 + &gpio1 13 1>; + gpio-fan,speed-map = <0 0 + 3000 1 + 6000 2>; + alarm-gpios = <&gpio1 15 1>; + }; + gpio_fan_cool: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio2 14 1 + &gpio2 13 1>; + gpio-fan,speed-map = <0 0>, + <3000 1>, + <6000 2>; + alarm-gpios = <&gpio2 15 1>; + #cooling-cells = <2>; /* min followed by max */ + }; -- cgit v1.2.3 From 7d29f509d2cfd807b2fccc643ac1f7066b9b1949 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 24 Aug 2017 09:21:12 +0200 Subject: dt-bindings: i2c: i2c-gpio: Add support for named gpios The current i2c-gpio DT bindings use a single unnamed "gpios" property to refer to the SDA and SCL signal lines by index. This is error-prone for the casual DT writer and reviewer, as one has to look up the order in the DT bindings. Fix this by amending the DT bindings to use two separate named gpios properties, and deprecate the old unnamed variant. Take this opportunity to clearly deprecate the "i2c-gpio,sda-open-drain" and "i2c-gpio,scl-open-drain" flags as well. The commit describes in detail what these flags actually mean, and why they should not be used in new device trees. Cc: devicetree@vger.kernel.org Signed-off-by: Geert Uytterhoeven [Augmented to what I and Rob would like] Tested-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/i2c/i2c-gpio.txt | 32 ++++++++++++++++------ 1 file changed, 23 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt index 4f8ec947c6bd..38a05562d1d2 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt @@ -2,25 +2,39 @@ Device-Tree bindings for i2c gpio driver Required properties: - compatible = "i2c-gpio"; - - gpios: sda and scl gpio - + - sda-gpios: gpio used for the sda signal, this should be flagged as + active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) + from since the signal is by definition + open drain. + - scl-gpios: gpio used for the scl signal, this should be flagged as + active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) + from since the signal is by definition + open drain. Optional properties: - - i2c-gpio,sda-open-drain: sda as open drain - - i2c-gpio,scl-open-drain: scl as open drain - i2c-gpio,scl-output-only: scl as output only - i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform) - i2c-gpio,timeout-ms: timeout to get data +Deprecated properties, do not use in new device tree sources: + - gpios: sda and scl gpio, alternative for {sda,scl}-gpios + - i2c-gpio,sda-open-drain: this means that something outside of our + control has put the GPIO line used for SDA into open drain mode, and + that something is not the GPIO chip. It is essentially an + inconsistency flag. + - i2c-gpio,scl-open-drain: this means that something outside of our + control has put the GPIO line used for SCL into open drain mode, and + that something is not the GPIO chip. It is essentially an + inconsistency flag. + Example nodes: +#include + i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 23 0 /* sda */ - &pioA 24 0 /* scl */ - >; - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; + sda-gpios = <&pioA 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&pioA 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 4946b3af5e8e96f0f0ceec53701541f1faae714d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 15 Sep 2017 16:35:24 -0700 Subject: mmc: sdhci-msm: Enable delay circuit calibration clocks The delay circuit used to support HS400 is calibrated based on two additional clocks. When these clocks are not available and FF_CLK_SW_RST_DIS is not set in CORE_HC_MODE, reset might fail. But on some platforms this doesn't work properly and below dump can be seen in the kernel log. mmc0: Reset 0x1 never completed. mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00001102 mmc0: sdhci: Blk size: 0x00004000 | Blk cnt: 0x00000000 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 mmc0: sdhci: Present: 0x01f80000 | Host ctl: 0x00000000 mmc0: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000002 mmc0: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 mmc0: sdhci: Int enab: 0x00000000 | Sig enab: 0x00000000 mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 mmc0: sdhci: Caps: 0x742dc8b2 | Caps_1: 0x00008007 mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc0: sdhci: Host ctl2: 0x00000000 mmc0: sdhci: ============================================ Add support for the additional calibration clocks to allow these platforms to be configured appropriately. Cc: Venkat Gopalakrishnan Cc: Ritesh Harjani Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Tested-by: Jeremy McNicoll Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 ++ drivers/mmc/host/sdhci-msm.c | 12 +++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 0576264eab5e..bfdcdc4ccdff 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -18,6 +18,8 @@ Required properties: "core" - SDC MMC clock (MCLK) (required) "bus" - SDCC bus voter clock (optional) "xo" - TCXO clock (optional) + "cal" - reference clock for RCLK delay calibration (optional) + "sleep" - sleep clock for RCLK delay calibration (optional) Example: diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 526e19eced2f..33919d2b35d1 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -129,7 +129,7 @@ struct sdhci_msm_host { int pwr_irq; /* power irq */ struct clk *bus_clk; /* SDHC bus voter clock */ struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ - struct clk_bulk_data bulk_clks[2]; /* core, iface clocks */ + struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */ unsigned long clk_rate; struct mmc_host *mmc; bool use_14lpp_dll_reset; @@ -1184,6 +1184,16 @@ static int sdhci_msm_probe(struct platform_device *pdev) if (ret) dev_warn(&pdev->dev, "core clock boost failed\n"); + clk = devm_clk_get(&pdev->dev, "cal"); + if (IS_ERR(clk)) + clk = NULL; + msm_host->bulk_clks[2].clk = clk; + + clk = devm_clk_get(&pdev->dev, "sleep"); + if (IS_ERR(clk)) + clk = NULL; + msm_host->bulk_clks[3].clk = clk; + ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), msm_host->bulk_clks); if (ret) -- cgit v1.2.3 From 17f5e716703b3281293790e83ad3d6a0bd8b9681 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Tue, 3 Oct 2017 13:24:16 +0200 Subject: dt-bindings: mmc: Document the Amlogic Meson8 and Meson8b SDIO bindings This documents the devicetree bindings for the SDIO/MMC host found in Amlogic Meson8 and Meson8b SoCs. It supports the SD specification v2.0 and the eMMC specification v4.41. It has an internal "mux" which allows connecting up to three MMC devices to it. The maximum supported bus-width is 4-bits. Amlogic's GPL kernel sources call it "SDIO" to differentiate it from the other MMC controller in (at least the Meson8 and Meson8b) the SoCs (they call the other one "SDHC", which supports a bus-width of up to 8-bits). Signed-off-by: Carlo Caione Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Ulf Hansson --- .../bindings/mmc/amlogic,meson-mx-sdio.txt | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt new file mode 100644 index 000000000000..8765c605e6bc --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt @@ -0,0 +1,54 @@ +* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller + +The highspeed MMC host controller on Amlogic SoCs provides an interface +for MMC, SD, SDIO and SDHC types of memory cards. + +Supported maximum speeds are the ones of the eMMC standard 4.41 as well +as the speed of SD standard 2.0. + +The hardware provides an internal "mux" which allows up to three slots +to be controlled. Only one slot can be accessed at a time. + +Required properties: + - compatible : must be one of + - "amlogic,meson8-sdio" + - "amlogic,meson8b-sdio" + along with the generic "amlogic,meson-mx-sdio" + - reg : mmc controller base registers + - interrupts : mmc controller interrupt + - #address-cells : must be 1 + - size-cells : must be 0 + - clocks : phandle to clock providers + - clock-names : must contain "core" and "clkin" + +Required child nodes: +A node for each slot provided by the MMC controller is required. +NOTE: due to a driver limitation currently only one slot (= child node) + is supported! + +Required properties on each child node (= slot): + - compatible : must be "mmc-slot" (see mmc.txt within this directory) + - reg : the slot (or "port") ID + +Optional properties on each child node (= slot): + - bus-width : must be 1 or 4 (8-bit bus is not supported) + - for cd and all other additional generic mmc parameters + please refer to mmc.txt within this directory + +Examples: + mmc@c1108c20 { + compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; + reg = <0xc1108c20 0x20>; + interrupts = <0 28 1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; + clock-names = "core", "clkin"; + + slot@1 { + compatible = "mmc-slot"; + reg = <1>; + + bus-width = <4>; + }; + }; -- cgit v1.2.3 From f7834cbd907abb5d4d84f85dba5a7321e5a37b83 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 15 Oct 2017 14:46:13 +0200 Subject: dt-bindings: mmc: describe new eMMC binding for fixed driver type Some boards may have to use a certain driver type (or drive strength) to achieve stable eMMC communication. Describe a binding to set this up via DT. Signed-off-by: Wolfram Sang Acked-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index b32ade645ad9..94a90b49a692 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -53,6 +53,9 @@ Optional properties: - no-sdio: controller is limited to send sdio cmd during initialization - no-sd: controller is limited to send sd cmd during initialization - no-mmc: controller is limited to send mmc cmd during initialization +- fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type. + The value is the driver type as specified in the eMMC specification + (table 206 in spec version 5.1). *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line polarity properties, we have to fix the meaning of the "normal" and "inverted" -- cgit v1.2.3 From 95e91ade6900547a74ac8e3ce35213aacfbdd0d3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 18 Oct 2017 09:00:21 +0200 Subject: dt-bindings: mmc: renesas_sdhi: provide example in bindings documentation Provide an example of the usage of the DT bindings for TMIO in their documentation. The example given is for the r8a7790 (R-Car H2). Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index 54ef642f23a0..b63392d9cc47 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -43,3 +43,61 @@ Optional properties: - pinctrl-names: should be "default", "state_uhs" - pinctrl-0: should contain default/high speed pin ctrl - pinctrl-1: should contain uhs mode pin ctrl + +Example: R8A7790 (R-Car H2) SDHI controller nodes + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee120000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7790"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; -- cgit v1.2.3 From 54839d012d5f98cde2fa102fdcd22e1da661d138 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 18 Oct 2017 09:00:22 +0200 Subject: dt-bindings: mmc: renesas_sdhi: add R-Car Gen[123] fallback compatibility strings Add fallback compatibility strings for R-Car Gen 1, 2 and 3. In the case of Renesas R-Car hardware we know that there are generations of SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship between IP blocks might be. For example, I believe that r8a7790 is older than r8a7791 but that doesn't imply that the latter is a descendant of the former or vice versa. We can, however, by examining the documentation and behaviour of the hardware at run-time observe that the current driver implementation appears to be compatible with the IP blocks on SoCs within a given generation. For the above reasons and convenience when enabling new SoCs a per-generation fallback compatibility string scheme is being adopted for drivers for Renesas SoCs. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index b63392d9cc47..3c6762430fd9 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -10,7 +10,7 @@ described in mmc.txt, can be used. Additionally the following tmio_mmc-specific optional bindings can be used. Required properties: -- compatible: "renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit +- compatible: should contain one or more of the following: "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC @@ -26,6 +26,16 @@ Required properties: "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC + "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller + "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller + "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 or RZ/G1 + SDHI controller + "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 SDHI controller + + + When compatible with the generic version, nodes must list + the SoC-specific version corresponding to the platform + first followed by the generic version. - clocks: Most controllers only have 1 clock source per channel. However, on some variations of this controller, the internal card detection @@ -47,7 +57,7 @@ Optional properties: Example: R8A7790 (R-Car H2) SDHI controller nodes sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = ; clocks = <&cpg CPG_MOD 314>; @@ -61,7 +71,7 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes }; sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee120000 0 0x328>; interrupts = ; clocks = <&cpg CPG_MOD 313>; @@ -75,7 +85,7 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes }; sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 312>; @@ -89,7 +99,7 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes }; sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790"; + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 311>; -- cgit v1.2.3 From d91ca84edeb04fad89faf0f723029b692f6b13b4 Mon Sep 17 00:00:00 2001 From: Chaotian Jing Date: Mon, 16 Oct 2017 09:46:28 +0800 Subject: mmc: dt-bindings: Add reg/source_cg/latch-ck for Mediatek MMC bindings Change the comptiable for support of multi-platform Make compatible explicit, as MMC host of mt8173 has difference with mt8135(mt8173 supports hs400 and hs400_tune),so that need separate mt8173/mt8135 compatible name. Add description for reg Add description for source_cg Add description for mediatek,latch-ck Note that source_cg and mediatek,latch-ck are optional for some projects, eg, MT2701 do not have source_cg, and MT2712 do not need mediatek,latch-ck Signed-off-by: Chaotian Jing Acked-by: Rob Herring Tested-by: Sean Wang Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 4182ea36ca5b..72d2a734ab85 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -7,10 +7,18 @@ This file documents differences between the core properties in mmc.txt and the properties used by the msdc driver. Required properties: -- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc" +- compatible: value should be either of the following. + "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135 + "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 + "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 + "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 +- reg: physical base address of the controller and length - interrupts: Should contain MSDC interrupt number -- clocks: MSDC source clock, HCLK -- clock-names: "source", "hclk" +- clocks: Should contain phandle for the clock feeding the MMC controller +- clock-names: Should contain the following: + "source" - source clock (required) + "hclk" - HCLK which used for host (required) + "source_cg" - independent source clock gate (required for MT2712) - pinctrl-names: should be "default", "state_uhs" - pinctrl-0: should contain default/high speed pin ctrl - pinctrl-1: should contain uhs mode pin ctrl @@ -30,6 +38,10 @@ Optional properties: - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection If present,HS400 command responses are sampled on rising edges. If not present,HS400 command responses are sampled on falling edges. +- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc + error caused by stop clock(fifo full) + Valid range = [0:0x7]. if not present, default value is 0. + applied to compatible "mediatek,mt2701-mmc". Examples: mmc0: mmc@11230000 { -- cgit v1.2.3 From 9f058fa2efb10cd75884c4ee6c357bab07715f02 Mon Sep 17 00:00:00 2001 From: Avaneesh Kumar Dwivedi Date: Tue, 24 Oct 2017 21:22:27 +0530 Subject: remoteproc: qcom: Add support for mss remoteproc on msm8996 This patch add support for mss boot on msm8996. Major changes include initializing mss rproc for msm8996, making appropriate change for executing mss reset sequence etc. Tested-and-acked-by: Bjorn Andersson Signed-off-by: Avaneesh Kumar Dwivedi Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 + drivers/remoteproc/qcom_q6v5_pil.c | 164 ++++++++++++++++++--- 2 files changed, 141 insertions(+), 24 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 7ff3f7903f26..00d3d58a102f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -10,6 +10,7 @@ on the Qualcomm Hexagon core. "qcom,q6v5-pil", "qcom,msm8916-mss-pil", "qcom,msm8974-mss-pil" + "qcom,msm8996-mss-pil" - reg: Usage: required diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c index 728179ba7db2..5460f61ee21c 100644 --- a/drivers/remoteproc/qcom_q6v5_pil.c +++ b/drivers/remoteproc/qcom_q6v5_pil.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "remoteproc_internal.h" #include "qcom_common.h" @@ -64,6 +65,8 @@ #define QDSP6SS_RESET_REG 0x014 #define QDSP6SS_GFMUX_CTL_REG 0x020 #define QDSP6SS_PWR_CTL_REG 0x030 +#define QDSP6SS_MEM_PWR_CTL 0x0B0 +#define QDSP6SS_STRAP_ACC 0x110 /* AXI Halt Register Offsets */ #define AXI_HALTREQ_REG 0x0 @@ -92,6 +95,15 @@ #define QDSS_BHS_ON BIT(21) #define QDSS_LDO_BYP BIT(22) +/* QDSP6v56 parameters */ +#define QDSP6v56_LDO_BYP BIT(25) +#define QDSP6v56_BHS_ON BIT(24) +#define QDSP6v56_CLAMP_WL BIT(21) +#define QDSP6v56_CLAMP_QMC_MEM BIT(22) +#define HALT_CHECK_MAX_LOOPS 200 +#define QDSP6SS_XO_CBCR 0x0038 +#define QDSP6SS_ACC_OVERRIDE_VAL 0x20 + struct reg_info { struct regulator *reg; int uV; @@ -110,6 +122,7 @@ struct rproc_hexagon_res { struct qcom_mss_reg_res *active_supply; char **proxy_clk_names; char **active_clk_names; + int version; bool need_mem_protection; }; @@ -158,7 +171,13 @@ struct q6v5 { bool need_mem_protection; int mpss_perm; int mba_perm; + int version; +}; +enum { + MSS_MSM8916, + MSS_MSM8974, + MSS_MSM8996, }; static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, @@ -387,33 +406,98 @@ static int q6v5proc_reset(struct q6v5 *qproc) { u32 val; int ret; + int i; - /* Assert resets, stop core */ - val = readl(qproc->reg_base + QDSP6SS_RESET_REG); - val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE); - writel(val, qproc->reg_base + QDSP6SS_RESET_REG); - /* Enable power block headswitch, and wait for it to stabilize */ - val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= QDSS_BHS_ON | QDSS_LDO_BYP; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - udelay(1); - - /* - * Turn on memories. L2 banks should be done individually - * to minimize inrush current. - */ - val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | - Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= Q6SS_L2DATA_SLP_NRET_N_2; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= Q6SS_L2DATA_SLP_NRET_N_1; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val |= Q6SS_L2DATA_SLP_NRET_N_0; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + if (qproc->version == MSS_MSM8996) { + /* Override the ACC value if required */ + writel(QDSP6SS_ACC_OVERRIDE_VAL, + qproc->reg_base + QDSP6SS_STRAP_ACC); + /* Assert resets, stop core */ + val = readl(qproc->reg_base + QDSP6SS_RESET_REG); + val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; + writel(val, qproc->reg_base + QDSP6SS_RESET_REG); + + /* BHS require xo cbcr to be enabled */ + val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); + val |= 0x1; + writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); + + /* Read CLKOFF bit to go low indicating CLK is enabled */ + ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, + val, !(val & BIT(31)), 1, + HALT_CHECK_MAX_LOOPS); + if (ret) { + dev_err(qproc->dev, + "xo cbcr enabling timed out (rc:%d)\n", ret); + return ret; + } + /* Enable power block headswitch and wait for it to stabilize */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= QDSP6v56_BHS_ON; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + udelay(1); + + /* Put LDO in bypass mode */ + val |= QDSP6v56_LDO_BYP; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Deassert QDSP6 compiler memory clamp */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val &= ~QDSP6v56_CLAMP_QMC_MEM; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Deassert memory peripheral sleep and L2 memory standby */ + val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Turn on L1, L2, ETB and JU memories 1 at a time */ + val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); + for (i = 19; i >= 0; i--) { + val |= BIT(i); + writel(val, qproc->reg_base + + QDSP6SS_MEM_PWR_CTL); + /* + * Read back value to ensure the write is done then + * wait for 1us for both memory peripheral and data + * array to turn on. + */ + val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); + udelay(1); + } + /* Remove word line clamp */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val &= ~QDSP6v56_CLAMP_WL; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + } else { + /* Assert resets, stop core */ + val = readl(qproc->reg_base + QDSP6SS_RESET_REG); + val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; + writel(val, qproc->reg_base + QDSP6SS_RESET_REG); + + /* Enable power block headswitch and wait for it to stabilize */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= QDSS_BHS_ON | QDSS_LDO_BYP; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + udelay(1); + /* + * Turn on memories. L2 banks should be done individually + * to minimize inrush current. + */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | + Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= Q6SS_L2DATA_SLP_NRET_N_2; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= Q6SS_L2DATA_SLP_NRET_N_1; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= Q6SS_L2DATA_SLP_NRET_N_0; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + } /* Remove IO clamp */ val &= ~Q6SS_CLAMP_IO; writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); @@ -803,6 +887,16 @@ static int q6v5_stop(struct rproc *rproc) q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); + if (qproc->version == MSS_MSM8996) { + /* + * To avoid high MX current during LPASS/MSS restart. + */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | + QDSP6v56_CLAMP_QMC_MEM; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + } + ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, qproc->mpss_phys, qproc->mpss_size); @@ -1106,6 +1200,7 @@ static int q6v5_probe(struct platform_device *pdev) if (ret) goto free_rproc; + qproc->version = desc->version; qproc->need_mem_protection = desc->need_mem_protection; ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt); if (ret < 0) @@ -1158,6 +1253,24 @@ static int q6v5_remove(struct platform_device *pdev) return 0; } +static const struct rproc_hexagon_res msm8996_mss = { + .hexagon_mba_image = "mba.mbn", + .proxy_clk_names = (char*[]){ + "xo", + "pnoc", + NULL + }, + .active_clk_names = (char*[]){ + "iface", + "bus", + "mem", + "gpll0_mss_clk", + NULL + }, + .need_mem_protection = true, + .version = MSS_MSM8996, +}; + static const struct rproc_hexagon_res msm8916_mss = { .hexagon_mba_image = "mba.mbn", .proxy_supply = (struct qcom_mss_reg_res[]) { @@ -1186,6 +1299,7 @@ static const struct rproc_hexagon_res msm8916_mss = { NULL }, .need_mem_protection = false, + .version = MSS_MSM8916, }; static const struct rproc_hexagon_res msm8974_mss = { @@ -1224,12 +1338,14 @@ static const struct rproc_hexagon_res msm8974_mss = { NULL }, .need_mem_protection = false, + .version = MSS_MSM8974, }; static const struct of_device_id q6v5_of_match[] = { { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, + { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, { }, }; MODULE_DEVICE_TABLE(of, q6v5_of_match); -- cgit v1.2.3 From eace566c3406cac3131d44198f05b7b55f79651f Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Thu, 26 Oct 2017 15:28:54 -0700 Subject: dt-bindings: soc: qcom: Support GLINK intents Virtual GLINK channels may know what throughput to expect from a remoteproc. An intent advertises to the remoteproc this channel is ready to receive data. Allow a channel to define the size and amount of intents to be prequeued. Acked-by: Rob Herring Signed-off-by: Chris Lew Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt index b277eca861f7..9663cab52246 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,glink.txt @@ -39,6 +39,14 @@ of these nodes are defined by the individual bindings for the specific function Definition: a list of channels tied to this function, used for matching the function to a set of virtual channels +- qcom,intents: + Usage: optional + Value type: + Definition: a list of size,amount pairs describing what intents should + be preallocated for this virtual channel. This can be used + to tweak the default intents available for the channel to + meet expectations of the remote. + = EXAMPLE The following example represents the GLINK RPM node on a MSM8996 device, with the function for the "rpm_request" channel defined, which is used for @@ -69,6 +77,8 @@ regualtors and root clocks. compatible = "qcom,rpm-msm8996"; qcom,glink-channels = "rpm_requests"; + qcom,intents = <0x400 5 + 0x800 1>; ... }; }; -- cgit v1.2.3 From 707ce9eac5fc3b68f98c887dddea3911a8fc4f9f Mon Sep 17 00:00:00 2001 From: James Ban Date: Mon, 30 Oct 2017 11:32:38 +0900 Subject: regulator: da9211: update for supporting da9223/4/5 This is update for supporting additional devices da9223/4/5. Only device strings is added because only package type is different. Signed-off-by: James Ban Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/da9211.txt | 82 ++++++++++++++++++++-- drivers/regulator/Kconfig | 2 +- drivers/regulator/da9211-regulator.c | 14 ++-- drivers/regulator/da9211-regulator.h | 2 +- include/linux/regulator/da9211.h | 5 +- 5 files changed, 91 insertions(+), 14 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/da9211.txt b/Documentation/devicetree/bindings/regulator/da9211.txt index 0f2a6f8fcafd..27717e816e71 100644 --- a/Documentation/devicetree/bindings/regulator/da9211.txt +++ b/Documentation/devicetree/bindings/regulator/da9211.txt @@ -1,8 +1,9 @@ -* Dialog Semiconductor DA9211/DA9212/DA9213/DA9214/DA9215 Voltage Regulator +* Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 + Voltage Regulator Required properties: -- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" - or "dlg,da9214" or "dlg,da9215" +- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" or "dlg,da9223" + or "dlg,da9214" or "dlg,da9224" or "dlg,da9215" or "dlg,da9225" - reg: I2C slave address, usually 0x68. - interrupts: the interrupt outputs of the controller - regulators: A node that houses a sub-node for each regulator within the @@ -16,7 +17,6 @@ Optional properties: - Any optional property defined in regulator.txt Example 1) DA9211 - pmic: da9211@68 { compatible = "dlg,da9211"; reg = <0x68>; @@ -35,7 +35,6 @@ Example 1) DA9211 }; Example 2) DA9212 - pmic: da9212@68 { compatible = "dlg,da9212"; reg = <0x68>; @@ -79,7 +78,25 @@ Example 3) DA9213 }; }; -Example 4) DA9214 +Example 4) DA9223 + pmic: da9223@68 { + compatible = "dlg,da9223"; + reg = <0x68>; + interrupts = <3 27>; + + regulators { + BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <6000000>; + enable-gpios = <&gpio 27 0>; + }; + }; + }; + +Example 5) DA9214 pmic: da9214@68 { compatible = "dlg,da9214"; reg = <0x68>; @@ -105,7 +122,33 @@ Example 4) DA9214 }; }; -Example 5) DA9215 +Example 6) DA9224 + pmic: da9224@68 { + compatible = "dlg,da9224"; + reg = <0x68>; + interrupts = <3 27>; + + regulators { + BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <6000000>; + enable-gpios = <&gpio 27 0>; + }; + BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <6000000>; + enable-gpios = <&gpio 17 0>; + }; + }; + }; + +Example 7) DA9215 pmic: da9215@68 { compatible = "dlg,da9215"; reg = <0x68>; @@ -131,3 +174,28 @@ Example 5) DA9215 }; }; +Example 8) DA9225 + pmic: da9225@68 { + compatible = "dlg,da9225"; + reg = <0x68>; + interrupts = <3 27>; + + regulators { + BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <4000000>; + regulator-max-microamp = <7000000>; + enable-gpios = <&gpio 27 0>; + }; + BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <4000000>; + regulator-max-microamp = <7000000>; + enable-gpios = <&gpio 17 0>; + }; + }; + }; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 0fd6195601ba..96cd55f9e3c5 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -244,7 +244,7 @@ config REGULATOR_DA9210 interface. config REGULATOR_DA9211 - tristate "Dialog Semiconductor DA9211/DA9212/DA9213/DA9214/DA9215 regulator" + tristate "Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 regulator" depends on I2C select REGMAP_I2C help diff --git a/drivers/regulator/da9211-regulator.c b/drivers/regulator/da9211-regulator.c index aa47280efd32..9b8f47617724 100644 --- a/drivers/regulator/da9211-regulator.c +++ b/drivers/regulator/da9211-regulator.c @@ -1,6 +1,6 @@ /* * da9211-regulator.c - Regulator device driver for DA9211/DA9212 - * /DA9213/DA9214/DA9215 + * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 * Copyright (C) 2015 Dialog Semiconductor Ltd. * * This library is free software; you can redistribute it and/or @@ -496,8 +496,11 @@ static const struct i2c_device_id da9211_i2c_id[] = { {"da9211", DA9211}, {"da9212", DA9212}, {"da9213", DA9213}, + {"da9223", DA9223}, {"da9214", DA9214}, + {"da9224", DA9224}, {"da9215", DA9215}, + {"da9225", DA9225}, {}, }; MODULE_DEVICE_TABLE(i2c, da9211_i2c_id); @@ -507,8 +510,11 @@ static const struct of_device_id da9211_dt_ids[] = { { .compatible = "dlg,da9211", .data = &da9211_i2c_id[0] }, { .compatible = "dlg,da9212", .data = &da9211_i2c_id[1] }, { .compatible = "dlg,da9213", .data = &da9211_i2c_id[2] }, - { .compatible = "dlg,da9214", .data = &da9211_i2c_id[3] }, - { .compatible = "dlg,da9215", .data = &da9211_i2c_id[4] }, + { .compatible = "dlg,da9223", .data = &da9211_i2c_id[3] }, + { .compatible = "dlg,da9214", .data = &da9211_i2c_id[4] }, + { .compatible = "dlg,da9224", .data = &da9211_i2c_id[5] }, + { .compatible = "dlg,da9215", .data = &da9211_i2c_id[6] }, + { .compatible = "dlg,da9225", .data = &da9211_i2c_id[7] }, {}, }; MODULE_DEVICE_TABLE(of, da9211_dt_ids); @@ -526,5 +532,5 @@ static struct i2c_driver da9211_regulator_driver = { module_i2c_driver(da9211_regulator_driver); MODULE_AUTHOR("James Ban "); -MODULE_DESCRIPTION("DA9211/DA9212/DA9213/DA9214/DA9215 regulator driver"); +MODULE_DESCRIPTION("DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 regulator driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/da9211-regulator.h b/drivers/regulator/da9211-regulator.h index b841bbf330cc..2cb32aab4f82 100644 --- a/drivers/regulator/da9211-regulator.h +++ b/drivers/regulator/da9211-regulator.h @@ -1,6 +1,6 @@ /* * da9211-regulator.h - Regulator definitions for DA9211/DA9212 - * /DA9213/DA9214/DA9215 + * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 * Copyright (C) 2015 Dialog Semiconductor Ltd. * * This program is free software; you can redistribute it and/or diff --git a/include/linux/regulator/da9211.h b/include/linux/regulator/da9211.h index 80cb40b7c88d..f2fd2d3bf58f 100644 --- a/include/linux/regulator/da9211.h +++ b/include/linux/regulator/da9211.h @@ -1,6 +1,6 @@ /* * da9211.h - Regulator device driver for DA9211/DA9212 - * /DA9213/DA9214/DA9215 + * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 * Copyright (C) 2015 Dialog Semiconductor Ltd. * * This program is free software; you can redistribute it and/or @@ -25,8 +25,11 @@ enum da9211_chip_id { DA9211, DA9212, DA9213, + DA9223, DA9214, + DA9224, DA9215, + DA9225, }; struct da9211_pdata { -- cgit v1.2.3 From 2bf209b8e28a5cf0a843d16005cfc7a432db888b Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 31 Oct 2017 09:19:08 +0100 Subject: dt-bindings: net: Restore sun8i dwmac binding The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe Acked-by: Rob Herring Acked-by: Florian Fainelli Signed-off-by: Maxime Ripard --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; -- cgit v1.2.3 From 26baf6dd63ddd2808561926cae6ecf16f56de38c Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 3 Mar 2017 13:14:02 -0500 Subject: media: dt: bindings: Add a binding for flash LED devices associated to a sensor Camera flash drivers (and LEDs) are separate from the sensor devices in DT. In order to make an association between the two, provide the association information to the software. Signed-off-by: Sakari Ailus Cc: devicetree@vger.kernel.org Acked-by: Hans Verkuil Acked-by: Pavel Machek Acked-by: Rob Herring Reviewed-by: Sebastian Reichel Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/video-interfaces.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index bd6474920510..dc66e3224692 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -76,6 +76,14 @@ are required in a relevant parent node: identifier, should be 1. - #size-cells : should be zero. + +Optional properties +------------------- + +- flash-leds: An array of phandles, each referring to a flash LED, a sub-node + of the LED driver device node. + + Optional endpoint properties ---------------------------- -- cgit v1.2.3 From 95293f79d53995142ed1f66be70216a6cbfc36f4 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Fri, 3 Mar 2017 17:07:51 -0500 Subject: media: dt: bindings: Add lens-focus binding for image sensors The lens-focus property contains a phandle to the lens voice coil driver that is associated to the sensor; typically both are contained in the same camera module. Signed-off-by: Sakari Ailus Cc: devicetree@vger.kernel.org Acked-by: Pavel Machek Reviewed-by: Sebastian Reichel Acked-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/video-interfaces.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index dc66e3224692..3994b0143dd1 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -83,6 +83,8 @@ Optional properties - flash-leds: An array of phandles, each referring to a flash LED, a sub-node of the LED driver device node. +- lens-focus: A phandle to the node of the focus lens controller. + Optional endpoint properties ---------------------------- -- cgit v1.2.3 From e4219f9f9c98ae28874c2b7390a561a2a77e6f64 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sun, 3 Sep 2017 15:41:53 -0400 Subject: media: dt: bindings: smiapp: Document lens-focus and flash-leds properties Document optional lens-focus and flash-leds properties for the smiapp driver. Signed-off-by: Sakari Ailus Acked-by: Hans Verkuil Acked-by: Pavel Machek Acked-by: Rob Herring Reviewed-by: Sebastian Reichel Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/nokia,smia.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt index 855e1faf73e2..33f10a94c381 100644 --- a/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +++ b/Documentation/devicetree/bindings/media/i2c/nokia,smia.txt @@ -27,6 +27,8 @@ Optional properties - nokia,nvm-size: The size of the NVM, in bytes. If the size is not given, the NVM contents will not be read. - reset-gpios: XSHUTDOWN GPIO +- flash-leds: See ../video-interfaces.txt +- lens-focus: See ../video-interfaces.txt Endpoint node mandatory properties -- cgit v1.2.3 From 1027d759c9517a255f663d4365d98d78d8680b20 Mon Sep 17 00:00:00 2001 From: Rocky Hao Date: Thu, 24 Aug 2017 18:27:51 +0800 Subject: dt-bindings: rockchip-thermal: Support the RV1108 SoC compatible Add a new compatible for thermal founding on RV1108 SoCs. Acked-by: Rob Herring Signed-off-by: Rocky Hao Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt index e3a6234fb1ac..43d744e5305e 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt @@ -2,6 +2,7 @@ Required properties: - compatible : should be "rockchip,-tsadc" + "rockchip,rv1108-tsadc": found on RV1108 SoCs "rockchip,rk3228-tsadc": found on RK3228 SoCs "rockchip,rk3288-tsadc": found on RK3288 SoCs "rockchip,rk3328-tsadc": found on RK3328 SoCs -- cgit v1.2.3 From b590c51c9b956f465acc73a2864d3a1444c76c3b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 26 Sep 2017 14:27:58 -0700 Subject: Documentation: devicetree: add binding for Broadcom STB AVS TMON Add binding for Broadcom STB thermal. Signed-off-by: Brian Norris Acked-by: Rob Herring Signed-off-by: Markus Mayer Signed-off-by: Eduardo Valentin --- .../devicetree/bindings/thermal/brcm,avs-tmon.txt | 20 ++++++++++++++++++++ MAINTAINERS | 8 ++++++++ 2 files changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt new file mode 100644 index 000000000000..9d43553a8d39 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt @@ -0,0 +1,20 @@ +* Broadcom STB thermal management + +Thermal management core, provided by the AVS TMON hardware block. + +Required properties: +- compatible: must be "brcm,avs-tmon" and/or "brcm,avs-tmon-bcm7445" +- reg: address range for the AVS TMON registers +- interrupts: temperature monitor interrupt, for high/low threshold triggers +- interrupt-names: should be "tmon" +- interrupt-parent: the parent interrupt controller + +Example: + + thermal@f04d1500 { + compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon"; + reg = <0xf04d1500 0x28>; + interrupts = <0x6>; + interrupt-names = "tmon"; + interrupt-parent = <&avs_host_l2_intc>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2281af4b41b6..46c592bc402f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2955,6 +2955,14 @@ S: Maintained F: Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt F: drivers/cpufreq/brcmstb* +BROADCOM STB AVS TMON DRIVER +M: Markus Mayer +M: bcm-kernel-feedback-list@broadcom.com +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt +F: drivers/thermal/broadcom/brcmstb* + BROADCOM STB NAND FLASH DRIVER M: Brian Norris M: Kamal Dasu -- cgit v1.2.3 From 9f17ceaa01133e9a67fd796617446e9499570e3d Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 1 Nov 2017 10:32:07 +0800 Subject: dt-bindings: mfd: Add Spreadtrum SC27xx PMIC documentation This patch adds the binding documentation for Spreadtrum SC27xx series PMIC device. Signed-off-by: Baolin Wang Acked-by: Rob Herring Acked-by: Lee Jones Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/sprd,sc27xx-pmic.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt b/Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt new file mode 100644 index 000000000000..21b9a897fca5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/sprd,sc27xx-pmic.txt @@ -0,0 +1,40 @@ +Spreadtrum SC27xx Power Management Integrated Circuit (PMIC) + +The Spreadtrum SC27xx series PMICs contain SC2720, SC2721, SC2723, SC2730 +and SC2731. The Spreadtrum PMIC belonging to SC27xx series integrates all +mobile handset power management, audio codec, battery management and user +interface support function in a single chip. It has 6 major functional +blocks: +- DCDCs to support CPU, memory. +- LDOs to support both internal and external requirement. +- Battery management system, such as charger, fuel gauge. +- Audio codec. +- User interface function, such as indicator, flash LED and so on. +- IC level interface, such as power on/off control, RTC and typec and so on. + +Required properties: +- compatible: Should be one of the following: + "sprd,sc2720" + "sprd,sc2721" + "sprd,sc2723" + "sprd,sc2730" + "sprd,sc2731" +- reg: The address of the device chip select, should be 0. +- spi-max-frequency: Typically set to 26000000. +- interrupts: The interrupt line the device is connected to. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: The number of cells to describe an PMIC IRQ, must be 2. +- #address-cells: Child device offset number of cells, must be 1. +- #size-cells: Child device size number of cells, must be 0. + +Example: +pmic@0 { + compatible = "sprd,sc2731"; + reg = <0>; + spi-max-frequency = <26000000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; +}; -- cgit v1.2.3 From 9b796ffcd16dfaf820ecc6a9dc287e6d758a556e Mon Sep 17 00:00:00 2001 From: Jules Maselbas Date: Tue, 31 Oct 2017 11:32:57 +0100 Subject: dt-bindings: usb: max3421: Interrupt-parent is optional Documentation modification, now interrupt-parent is an optional property. Also fix few typos. Signed-off-by: Jules Maselbas Reported-by: Sergei Shtylyov Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/maxim,max3421.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/maxim,max3421.txt b/Documentation/devicetree/bindings/usb/maxim,max3421.txt index 7536c3ab3e5a..8cdbe0c85188 100644 --- a/Documentation/devicetree/bindings/usb/maxim,max3421.txt +++ b/Documentation/devicetree/bindings/usb/maxim,max3421.txt @@ -1,17 +1,19 @@ Maxim Integrated SPI-based USB 2.0 host controller MAX3421E Required properties: - - compatible: "maxim,max3421" + - compatible: Should be "maxim,max3421" - spi-max-frequency: maximum frequency for this device must not exceed 26 MHz. - reg: chip select number to which this device is connected. - maxim,vbus-en-pin: GPOUTx is the number (1-8) of the GPOUT pin of MAX3421E to drive Vbus. ACTIVE_LEVEL is 0 or 1. - - interrupt-parent: the phandle of the associated interrupt controller. - - interrupts: the interuption line description for the interrupt controller. + - interrupts: the interrupt line description for the interrupt controller. The driver configures MAX3421E for active low level triggered interrupts, configure your interrupt line accordingly. +Optional property: + - interrupt-parent: the phandle to the associated interrupt controller. + Example: usb@0 { -- cgit v1.2.3 From a8a5267756c32308681a1c9a42bd8079a76ff4a4 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Sun, 22 Oct 2017 23:38:03 +0300 Subject: usb: usb251xb: Update usb251xb bindings Since hub usb2517 is going to be supported by the usb251xb driver, the bindings need to be properly updated. Particularly: - add "microchip,usb2517" and "microchip,usb2517i" compatible strings. - add "boolean" description to all the properties, which really accept a boolean value including a new one "led-{usb,speed}-mode". - move reset-gpios property to the optional section. It isn't defined as required in the code and shouldn't be required at all, since hardware may handle reset pins by itself. - add new led-{usb,speed}-mode mode property. USB2517 device supports two LED modes: USB mode and speed (default) indication mode. The last one can be switched on by this property. - add {bp,sp}-max-{total,removable}-current-microamp property measured in microamp. It hasn't been defined as property before. Since the limitation specified by these parameters is hardware specific it needs to be defined in dts. Signed-off-by: Serge Semin Acked-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/usb251xb.txt | 46 +++++++++++++++------- 1 file changed, 32 insertions(+), 14 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb251xb.txt b/Documentation/devicetree/bindings/usb/usb251xb.txt index 3957d4edaa74..168ff819e827 100644 --- a/Documentation/devicetree/bindings/usb/usb251xb.txt +++ b/Documentation/devicetree/bindings/usb/usb251xb.txt @@ -1,16 +1,17 @@ Microchip USB 2.0 Hi-Speed Hub Controller -The device node for the configuration of a Microchip USB251xB/xBi USB 2.0 +The device node for the configuration of a Microchip USB251x/xBi USB 2.0 Hi-Speed Controller. Required properties : - compatible : Should be "microchip,usb251xb" or one of the specific types: "microchip,usb2512b", "microchip,usb2512bi", "microchip,usb2513b", - "microchip,usb2513bi", "microchip,usb2514b", "microchip,usb2514bi" - - reset-gpios : Should specify the gpio for hub reset + "microchip,usb2513bi", "microchip,usb2514b", "microchip,usb2514bi", + "microchip,usb2517", "microchip,usb2517i" - reg : I2C address on the selected bus (default is <0x2C>) Optional properties : + - reset-gpios : Should specify the gpio for hub reset - skip-config : Skip Hub configuration, but only send the USB-Attach command - vendor-id : Set USB Vendor ID of the hub (16 bit, default is 0x0424) - product-id : Set USB Product ID of the hub (16 bit, default depends on type) @@ -19,29 +20,47 @@ Optional properties : - manufacturer : Set USB Manufacturer string (max 31 characters long) - product : Set USB Product string (max 31 characters long) - serial : Set USB Serial string (max 31 characters long) - - {bus,self}-powered : selects between self- and bus-powered operation (default - is self-powered) - - disable-hi-speed : disable USB Hi-Speed support + - {bus,self}-powered : selects between self- and bus-powered operation + (boolean, default is self-powered) + - disable-hi-speed : disable USB Hi-Speed support (boolean) - {multi,single}-tt : selects between multi- and single-transaction-translator - (default is multi-tt) - - disable-eop : disable End of Packet generation in full-speed mode + (boolean, default is multi-tt) + - disable-eop : disable End of Packet generation in full-speed mode (boolean) - {ganged,individual}-sensing : select over-current sense type in self-powered - mode (default is individual) + mode (boolean, default is individual) - {ganged,individual}-port-switching : select port power switching mode - (default is individual) + (boolean, default is individual) - dynamic-power-switching : enable auto-switching from self- to bus-powered - operation if the local power source is removed or unavailable + operation if the local power source is removed or unavailable (boolean) - oc-delay-us : Delay time (in microseconds) for filtering the over-current sense inputs. Valid values are 100, 4000, 8000 (default) and 16000. If an invalid value is given, the default is used instead. - - compound-device : indicate the hub is part of a compound device - - port-mapping-mode : enable port mapping mode + - compound-device : indicate the hub is part of a compound device (boolean) + - port-mapping-mode : enable port mapping mode (boolean) + - led-{usb,speed}-mode : led usb/speed indication mode selection + (boolean, default is speed mode) - string-support : enable string descriptor support (required for manufacturer, product and serial string configuration) - non-removable-ports : Should specify the ports which have a non-removable device connected. - sp-disabled-ports : Specifies the ports which will be self-power disabled - bp-disabled-ports : Specifies the ports which will be bus-power disabled + - sp-max-total-current-microamp: Specifies max current consumed by the hub + from VBUS when operating in self-powered hub. It includes the hub + silicon along with all associated circuitry including a permanently + attached peripheral (range: 0 - 100000 uA, default 1000 uA) + - bp-max-total-current-microamp: Specifies max current consumed by the hub + from VBUS when operating in self-powered hub. It includes the hub + silicon along with all associated circuitry including a permanently + attached peripheral (range: 0 - 510000 uA, default 100000 uA) + - sp-max-removable-current-microamp: Specifies max current consumed by the hub + from VBUS when operating in self-powered hub. It includes the hub + silicon along with all associated circuitry excluding a permanently + attached peripheral (range: 0 - 100000 uA, default 1000 uA) + - bp-max-removable-current-microamp: Specifies max current consumed by the hub + from VBUS when operating in self-powered hub. It includes the hub + silicon along with all associated circuitry excluding a permanently + attached peripheral (range: 0 - 510000 uA, default 100000 uA) - power-on-time-ms : Specifies the time it takes from the time the host initiates the power-on sequence to a port until the port has adequate power. The value is given in ms in a 0 - 510 range (default is 100ms). @@ -56,7 +75,6 @@ Examples: usb2514b@2c { compatible = "microchip,usb2514b"; reg = <0x2c>; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; vendor-id = /bits/ 16 <0x0000>; product-id = /bits/ 16 <0x0000>; string-support; -- cgit v1.2.3 From efb5b43a5410fefa0516691af8e73f255260f598 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 29 Oct 2017 14:25:48 +0100 Subject: dt-bindings: add vendor prefix for Next Thing Co. Next Thing Co. is the company behind the C.H.I.P. and C.H.I.P. Pro miniature single board computers. The "nextthing" vendor-prefix is already used for these two board as well as their own "GR8" SoC. Cc: Alexander Kaplan Signed-off-by: Martin Blumenstingl Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 01500f2a399b..b2c1b8d80367 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -230,6 +230,7 @@ netlogic Broadcom Corporation (formerly NetLogic Microsystems) netron-dy Netron DY netxeon Shenzhen Netxeon Technology CO., LTD nexbox Nexbox +nextthing Next Thing Co. newhaven Newhaven Display International ni National Instruments nintendo Nintendo -- cgit v1.2.3 From 5e70ca8753c8d9749d206a4fdb14f22a6ba1d893 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 13 Oct 2017 13:26:35 +0200 Subject: clk: qcom: Elaborate on "active" clocks in the RPM clock bindings The concept of "active" clocks is just explained in a bried comment in the device driver, let's explain it a bit more in the device tree bindings so everyone understands this. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Signed-off-by: Linus Walleij Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,rpmcc.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index a7235e9e1c97..32c6e9ce64c3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,14 @@ Required properties : - #clock-cells : shall contain 1 +The clock enumerators are defined in +and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock +is an "active" clock, which means that the consumer only care that the +clock is available when the apps CPU subsystem is active, i.e. not +suspended or in deep idle. If it is important that the clock keeps running +during system suspend, you need to specify the non-active clock, the one +not containing *_A_* in the enumerator name. + Example: smd { compatible = "qcom,smd"; -- cgit v1.2.3 From 856e6bb91e198c4fb0ca2f4f3ee0e7f660b3e0ca Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 13 Oct 2017 13:59:16 +0200 Subject: clk: qcom: Update DT bindings for the MSM8660/APQ8060 RPMCC These compatible strings need to be added to extend support for the RPM CC to cover MSM8660/APQ8060. We also need to add enumberators to the include file for a few clocks that were missing. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Signed-off-by: Linus Walleij Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,rpmcc.txt | 2 ++ include/dt-bindings/clock/qcom,rpmcc.h | 3 +++ 2 files changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 32c6e9ce64c3..833a89f06ae0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -10,6 +10,8 @@ Required properties : - compatible : shall contain only one of the following. The generic compatible "qcom,rpmcc" should be also included. + "qcom,rpmcc-msm8660", "qcom,rpmcc" + "qcom,rpmcc-apq8060", "qcom,rpmcc" "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 96b63c00249e..29dad206a74b 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -37,6 +37,9 @@ #define RPM_SYS_FABRIC_A_CLK 19 #define RPM_SFPB_CLK 20 #define RPM_SFPB_A_CLK 21 +#define RPM_SMI_CLK 22 +#define RPM_SMI_A_CLK 23 +#define RPM_PLL4_CLK 24 /* SMD RPM clocks */ #define RPM_SMD_XO_CLK_SRC 0 -- cgit v1.2.3 From 7066fdd0d7427f1ba455d186e75213c442c9663b Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 10 Oct 2017 14:27:13 +0530 Subject: clk: qcom: clk-smd-rpm: add msm8996 rpmclks Add all RPM controlled clocks on msm8996 platform [srini: Fixed various issues with offsets and made names specific to msm8996] Signed-off-by: Srinivas Kandagatla Signed-off-by: Rajendra Nayak Acked-by: Rob Herring Acked-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + drivers/clk/qcom/clk-smd-rpm.c | 82 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 14 ++++ include/linux/soc/qcom/smd-rpm.h | 4 ++ 4 files changed, 101 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 833a89f06ae0..4491d1c104aa 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -15,6 +15,7 @@ Required properties : "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" + "qcom,rpmcc-msm8996", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index cc03d5508627..c26d9007bfc4 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -530,9 +530,91 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { .clks = msm8974_clks, .num_clks = ARRAY_SIZE(msm8974_clks), }; + +/* msm8996 */ +DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, + QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, + QCOM_SMD_RPM_AGGR_CLK, 1, 1000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, + QCOM_SMD_RPM_AGGR_CLK, 2, 1000); +DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk, + QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5); + +static struct clk_smd_rpm *msm8996_clks[] = { + [RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk, + [RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk, + [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, + [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, + [RPM_SMD_IPA_CLK] = &msm8996_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &msm8996_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk, + [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk, + [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk, + [RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &msm8996_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &msm8996_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &msm8996_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &msm8996_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a, + [RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk, + [RPM_SMD_DIV_CLK1] = &msm8996_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a, + [RPM_SMD_DIV_CLK2] = &msm8996_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a, + [RPM_SMD_DIV_CLK3] = &msm8996_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a, + [RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin, +}; + +static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { + .clks = msm8996_clks, + .num_clks = ARRAY_SIZE(msm8996_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, + { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 29dad206a74b..b8337a5fa347 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -104,5 +104,19 @@ #define RPM_SMD_CXO_A1_A_PIN 59 #define RPM_SMD_CXO_A2_PIN 60 #define RPM_SMD_CXO_A2_A_PIN 61 +#define RPM_SMD_AGGR1_NOC_CLK 62 +#define RPM_SMD_AGGR1_NOC_A_CLK 63 +#define RPM_SMD_AGGR2_NOC_CLK 64 +#define RPM_SMD_AGGR2_NOC_A_CLK 65 +#define RPM_SMD_MMAXI_CLK 66 +#define RPM_SMD_MMAXI_A_CLK 67 +#define RPM_SMD_IPA_CLK 68 +#define RPM_SMD_IPA_A_CLK 69 +#define RPM_SMD_CE1_CLK 70 +#define RPM_SMD_CE1_A_CLK 71 +#define RPM_SMD_DIV_CLK3 72 +#define RPM_SMD_DIV_A_CLK3 73 +#define RPM_SMD_LN_BB_CLK 74 +#define RPM_SMD_LN_BB_A_CLK 75 #endif diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 2a53dcaeeeed..ebdabd669d93 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -26,6 +26,10 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_SMPB 0x62706d73 #define QCOM_SMD_RPM_SPDM 0x63707362 #define QCOM_SMD_RPM_VSA 0x00617376 +#define QCOM_SMD_RPM_MMAXI_CLK 0x69786d6d +#define QCOM_SMD_RPM_IPA_CLK 0x617069 +#define QCOM_SMD_RPM_CE_CLK 0x6563 +#define QCOM_SMD_RPM_AGGR_CLK 0x72676761 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, -- cgit v1.2.3 From eb522df40e41915210856f1d654e0c31650cb526 Mon Sep 17 00:00:00 2001 From: "weiyi.lu@mediatek.com" Date: Mon, 23 Oct 2017 12:10:32 +0800 Subject: dt-bindings: ARM: Mediatek: Document bindings for MT2712 This patch adds the binding documentation for apmixedsys, bdpsys, imgsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, pericfg, topckgen, vdecsys and vencsys for Mediatek MT2712. Acked-by: Rob Herring Signed-off-by: Weiyi Lu Signed-off-by: Stephen Boyd --- .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,bdpsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,jpgdecsys.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,mcucfg.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 + .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + .../bindings/arm/mediatek/mediatek,vdecsys.txt | 1 + .../bindings/arm/mediatek/mediatek,vencsys.txt | 1 + 12 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index cd977db7630c..19fc116346d6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-apmixedsys" + - "mediatek,mt2712-apmixedsys", "syscon" - "mediatek,mt6797-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt index 4137196dd686..4010e37c53a0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt2701-bdpsys", "syscon" + - "mediatek,mt2712-bdpsys", "syscon" - #clock-cells: Must be 1 The bdpsys controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index 047b11ae5f45..868bd51a98be 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-imgsys", "syscon" + - "mediatek,mt2712-imgsys", "syscon" - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 58d58e2006b8..a3430cd96d0f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt2712-infracfg", "syscon" - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt new file mode 100644 index 000000000000..2df799cd06a7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt @@ -0,0 +1,22 @@ +Mediatek jpgdecsys controller +============================ + +The Mediatek jpgdecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt2712-jpgdecsys", "syscon" +- #clock-cells: Must be 1 + +The jpgdecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +jpgdecsys: syscon@19000000 { + compatible = "mediatek,mt2712-jpgdecsys", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt new file mode 100644 index 000000000000..b8fb03f3613e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt @@ -0,0 +1,22 @@ +Mediatek mcucfg controller +============================ + +The Mediatek mcucfg controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2712-mcucfg", "syscon" +- #clock-cells: Must be 1 + +The mcucfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +mcucfg: syscon@10220000 { + compatible = "mediatek,mt2712-mcucfg", "syscon"; + reg = <0 0x10220000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt new file mode 100644 index 000000000000..859e67b416d5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -0,0 +1,22 @@ +Mediatek mfgcfg controller +============================ + +The Mediatek mfgcfg controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt2712-mfgcfg", "syscon" +- #clock-cells: Must be 1 + +The mfgcfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +mfgcfg: syscon@13000000 { + compatible = "mediatek,mt2712-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index 70529e0b58e9..4eb8bbe15c01 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-mmsys", "syscon" + - "mediatek,mt2712-mmsys", "syscon" - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index e494366782aa..d9f092eb3550 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-pericfg", "syscon" + - "mediatek,mt2712-pericfg", "syscon" - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index ec93ecbb9f3c..2024fc909d69 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-topckgen" + - "mediatek,mt2712-topckgen", "syscon" - "mediatek,mt6797-topckgen" - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt index d150104f928a..ea40d05089f8 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-vdecsys", "syscon" + - "mediatek,mt2712-vdecsys", "syscon" - "mediatek,mt6797-vdecsys", "syscon" - "mediatek,mt8173-vdecsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt index 8a93be643647..851545357e94 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt @@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system. Required Properties: - compatible: Should be one of: + - "mediatek,mt2712-vencsys", "syscon" - "mediatek,mt6797-vencsys", "syscon" - "mediatek,mt8173-vencsys", "syscon" - #clock-cells: Must be 1 -- cgit v1.2.3 From 079573e373d3714acd53aad02a3c52355fb177ab Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 31 Oct 2017 09:19:09 +0100 Subject: dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe Acked-by: Florian Fainelli Acked-by: Rob Herring Reviewed-by: Andrew Lunn Signed-off-by: Maxime Ripard --- .../devicetree/bindings/net/dwmac-sun8i.txt | 147 +++++++++++++++++++-- 1 file changed, 135 insertions(+), 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..3d6d5fa0c4d5 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,42 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the emac node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "allwinner,sun8i-h3-mdio-mux" + - mdio-parent-bus: a phandle to EMAC mdio + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Additional information regarding generic multiplexer properties can be found +at Documentation/devicetree/bindings/net/mdio-mux.txt + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +91,117 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; }; -- cgit v1.2.3 From 808ecf4ad087f80c2eee99af67549f05d5315694 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Thu, 5 Oct 2017 11:50:22 +0800 Subject: dt-bindings: clock: mediatek: document clk bindings for MediaTek MT7622 SoC This patch adds the binding documentation for apmixedsys, ethsys, hifsys, infracfg, pericfg, topckgen and audsys for MT7622. Signed-off-by: Chen Zhong Signed-off-by: Sean Wang Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,ethsys.txt | 1 + .../bindings/arm/mediatek/mediatek,hifsys.txt | 1 + .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,pciesys.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 + .../bindings/arm/mediatek/mediatek,sgmiisys.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,ssusbsys.txt | 22 ++++++++++++++++++++++ .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + 10 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 19fc116346d6..b404d592ce58 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2701-apmixedsys" - "mediatek,mt2712-apmixedsys", "syscon" - "mediatek,mt6797-apmixedsys" + - "mediatek,mt7622-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt new file mode 100644 index 000000000000..9b8f578d5e19 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -0,0 +1,22 @@ +MediaTek AUDSYS controller +============================ + +The MediaTek AUDSYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt7622-audsys", "syscon" +- #clock-cells: Must be 1 + +The AUDSYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +audsys: audsys@11220000 { + compatible = "mediatek,mt7622-audsys", "syscon"; + reg = <0 0x11220000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 768f3a5bc055..7aa3fa167668 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7622-ethsys", "syscon" - #clock-cells: Must be 1 The ethsys controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt index beed7b594cea..f5629d64cef2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt2701-hifsys", "syscon" + - "mediatek,mt7622-hifsys", "syscon" - #clock-cells: Must be 1 The hifsys controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index a3430cd96d0f..566f153f9f83 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt2712-infracfg", "syscon" - "mediatek,mt6797-infracfg", "syscon" + - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt new file mode 100644 index 000000000000..d5d5f1227665 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt @@ -0,0 +1,22 @@ +MediaTek PCIESYS controller +============================ + +The MediaTek PCIESYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt7622-pciesys", "syscon" +- #clock-cells: Must be 1 + +The PCIESYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +pciesys: pciesys@1a100800 { + compatible = "mediatek,mt7622-pciesys", "syscon"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index d9f092eb3550..fb58ca8c2770 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -9,6 +9,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-pericfg", "syscon" - "mediatek,mt2712-pericfg", "syscon" + - "mediatek,mt7622-pericfg", "syscon" - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt new file mode 100644 index 000000000000..d113b8e741f3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -0,0 +1,22 @@ +MediaTek SGMIISYS controller +============================ + +The MediaTek SGMIISYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt7622-sgmiisys", "syscon" +- #clock-cells: Must be 1 + +The SGMIISYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +sgmiisys: sgmiisys@1b128000 { + compatible = "mediatek,mt7622-sgmiisys", "syscon"; + reg = <0 0x1b128000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt new file mode 100644 index 000000000000..00760019da00 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt @@ -0,0 +1,22 @@ +MediaTek SSUSBSYS controller +============================ + +The MediaTek SSUSBSYS controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt7622-ssusbsys", "syscon" +- #clock-cells: Must be 1 + +The SSUSBSYS controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 2024fc909d69..24014a7e2332 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2701-topckgen" - "mediatek,mt2712-topckgen", "syscon" - "mediatek,mt6797-topckgen" + - "mediatek,mt7622-topckgen" - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" - #clock-cells: Must be 1 -- cgit v1.2.3 From ca5cd8c9400c7eeeda84e34fa773c6c245e65c82 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 2 Nov 2017 14:54:00 +0530 Subject: regulator: qcom_spmi: Add support for pmi8994 Document the regulators available on pmi8994 and add support for this PMIC to the SPMI PMIC regulator driver. Signed-off-by: Rajendra Nayak Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/qcom,spmi-regulator.txt | 13 +++++++++++++ drivers/regulator/qcom_spmi-regulator.c | 9 +++++++++ 2 files changed, 22 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt index 0fa3b0fac129..57d2c65899df 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt @@ -8,6 +8,7 @@ Qualcomm SPMI Regulators "qcom,pm8916-regulators" "qcom,pm8941-regulators" "qcom,pm8994-regulators" + "qcom,pmi8994-regulators" - interrupts: Usage: optional @@ -100,6 +101,15 @@ Qualcomm SPMI Regulators Definition: Reference to regulator supplying the input pin, as described in the data sheet. +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_l1-supply: + Usage: optional (pmi8994 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each @@ -122,6 +132,9 @@ pm8994: l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 +pmi8994: + s1, s2, s3, l1 + The content of each sub-node is defined by the standard binding for regulators - see regulator.txt - with additional custom properties described below: diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index 16c5f84e06a7..9f8eb5dd2a4e 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -1619,11 +1619,20 @@ static const struct spmi_regulator_data pm8994_regulators[] = { { } }; +static const struct spmi_regulator_data pmi8994_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "l1", 0x4000, "vdd_l1", }, + { } +}; + static const struct of_device_id qcom_spmi_regulator_match[] = { { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, + { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, { } }; MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); -- cgit v1.2.3 From 4e4cb1b183d6e9df57f4e54c8b1a5231995da820 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 30 Oct 2017 00:05:21 +0100 Subject: irqchip/meson-gpio: add support for Meson8 SoCs Meson8 uses the same GPIO interrupt controller IP block as the other Meson SoCs. A total of 134 pins can be spied on, which is the sum of: - 22 pins on bank GPIOX - 17 pins on bank GPIOY - 30 pins on bank GPIODV - 10 pins on bank GPIOH - 15 pins on bank GPIOZ - 7 pins on bank CARD - 19 pins on bank BOOT - 14 pins in the AO domain Acked-by: Kevin Hilman Acked-by: Rob Herring Signed-off-by: Martin Blumenstingl Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + drivers/irqchip/irq-meson-gpio.c | 5 +++++ 2 files changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 633e21ce4b17..a83f9a5734ca 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -10,6 +10,7 @@ number of interrupt exposed depends on the SoC. Required properties: - compatible : must have "amlogic,meson8-gpio-intc” and either + “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index c7cc7e37a23c..a59bdbc0b9bb 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -47,6 +47,10 @@ struct meson_gpio_irq_params { unsigned int nr_hwirq; }; +static const struct meson_gpio_irq_params meson8_params = { + .nr_hwirq = 134, +}; + static const struct meson_gpio_irq_params meson8b_params = { .nr_hwirq = 119, }; @@ -60,6 +64,7 @@ static const struct meson_gpio_irq_params gxl_params = { }; static const struct of_device_id meson_irq_gpio_matches[] = { + { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params }, { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params }, -- cgit v1.2.3 From ddc92bec6d7d7e8a07794a8dbeade19476891b53 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sat, 21 Oct 2017 22:39:35 +0900 Subject: dt-bindings: openrisc: Add OpenRISC platform SoC Add devicetree binding documentation for the OpenRISC platform opencores,or1ksim. This is the main OpenRISC reference platform supporting multiple FPGA SoC's. This format is based on some of the mips binding docs as we have similar requirements. Also, update maintainers so openrisc related binding changes are visible to the openrisc team. Acked-by: Rob Herring Suggested-by: Pavel Machek Signed-off-by: Stafford Horne --- .../bindings/openrisc/opencores/or1ksim.txt | 39 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt new file mode 100644 index 000000000000..4950c794ecbb --- /dev/null +++ b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt @@ -0,0 +1,39 @@ +OpenRISC Generic SoC +==================== + +Boards and FPGA SoC's which support the OpenRISC standard platform. The +platform essentially follows the conventions of the OpenRISC architecture +specification, however some aspects, such as the boot protocol have been defined +by the Linux port. + +Required properties +------------------- + - compatible: Must include "opencores,or1ksim" + +CPU nodes: +---------- +A "cpus" node is required. Required properties: + - #address-cells: Must be 1. + - #size-cells: Must be 0. +A CPU sub-node is also required for at least CPU 0. Since the topology may +be probed via CPS, it is not necessary to specify secondary CPUs. Required +properties: + - compatible: Must be "opencores,or1200-rtlsvn481". + - reg: CPU number. + - clock-frequency: The CPU clock frequency in Hz. +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + +Boot protocol +------------- +The bootloader may pass the following arguments to the kernel: + - r3: address of a flattened device-tree blob or 0x0. diff --git a/MAINTAINERS b/MAINTAINERS index 4e2b720ca661..bcb7e2525f54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10031,6 +10031,7 @@ T: git git://github.com/openrisc/linux.git L: openrisc@lists.librecores.org W: http://openrisc.io S: Maintained +F: Documentation/devicetree/bindings/openrisc/ F: Documentation/openrisc/ F: arch/openrisc/ F: drivers/irqchip/irq-or1k-* -- cgit v1.2.3 From fab8be88ac0478b0157859f74fad5088c292356b Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Thu, 7 Sep 2017 22:55:18 +0900 Subject: dt-bindings: add openrisc to vendor prefixes list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add OpenRISC.io to vendor prefixes. This is reserved for softcores developed by the OpenRISC community. The OpenRISC community has separated from OpenCores.org requiring a new prefix. Reviewed-by: Andreas Färber Acked-by: Rob Herring Signed-off-by: Stafford Horne --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1afd298eddd7..b1eeca851d6f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -246,6 +246,7 @@ onion Onion Corporation onnn ON Semiconductor Corp. ontat On Tat Industrial Company opencores OpenCores.org +openrisc OpenRISC.io option Option NV ORCL Oracle Corporation ortustech Ortus Technology Co., Ltd. -- cgit v1.2.3 From 9b54470afd836278a7e6f0f08194e2e2dca4b6eb Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Mon, 30 Oct 2017 21:38:35 +0900 Subject: irqchip: add initial support for ompic IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multi-core support section of the OpenRISC 1.2 architecture specification: https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC. Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation. Reviewed-by: Marc Zyngier Acked-by: Rob Herring Signed-off-by: Stefan Kristiansson [shorne@gmail.com: converted ops to bitmask, wrote commit message] Signed-off-by: Stafford Horne --- .../interrupt-controller/openrisc,ompic.txt | 22 +++ MAINTAINERS | 1 + arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 202 +++++++++++++++++++++ 6 files changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file mode 100644 index 000000000000..caec07cc7149 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt @@ -0,0 +1,22 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : This should be set to 0 as this will not be an irq + parent. +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: interrupt-controller@98000000 { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + #interrupt-cells = <0>; + interrupts = <1>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index bcb7e2525f54..bb129d5f0d3a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10034,6 +10034,7 @@ S: Maintained F: Documentation/devicetree/bindings/openrisc/ F: Documentation/openrisc/ F: arch/openrisc/ +F: drivers/irqchip/irq-ompic.c F: drivers/irqchip/irq-or1k-* OPENVSWITCH diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index b49acda5e8f4..34eb4e90f56c 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool y diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 9d8a1dd2e2c2..a2ca82f6c2dd 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -151,6 +151,9 @@ config CLPS711X_IRQCHIP select SPARSE_IRQ default y +config OMPIC + bool + config OR1K_PIC bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 845abc107ad5..771f8e7f46f8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o +obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c new file mode 100644 index 000000000000..cf6d0c455518 --- /dev/null +++ b/drivers/irqchip/irq-ompic.c @@ -0,0 +1,202 @@ +/* + * Open Multi-Processor Interrupt Controller driver + * + * Copyright (C) 2014 Stefan Kristiansson + * Copyright (C) 2017 Stafford Horne + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + * + * The ompic device handles IPI communication between cores in multi-core + * OpenRISC systems. + * + * Registers + * + * For each CPU the ompic has 2 registers. The control register for sending + * and acking IPIs and the status register for receiving IPIs. The register + * layouts are as follows: + * + * Control register + * +---------+---------+----------+---------+ + * | 31 | 30 | 29 .. 16 | 15 .. 0 | + * ----------+---------+----------+---------- + * | IRQ ACK | IRQ GEN | DST CORE | DATA | + * +---------+---------+----------+---------+ + * + * Status register + * +----------+-------------+----------+---------+ + * | 31 | 30 | 29 .. 16 | 15 .. 0 | + * -----------+-------------+----------+---------+ + * | Reserved | IRQ Pending | SRC CORE | DATA | + * +----------+-------------+----------+---------+ + * + * Architecture + * + * - The ompic generates a level interrupt to the CPU PIC when a message is + * ready. Messages are delivered via the memory bus. + * - The ompic does not have any interrupt input lines. + * - The ompic is wired to the same irq line on each core. + * - Devices are wired to the same irq line on each core. + * + * +---------+ +---------+ + * | CPU | | CPU | + * | Core 0 |<==\ (memory access) /==>| Core 1 | + * | [ PIC ]| | | | [ PIC ]| + * +----^-^--+ | | +----^-^--+ + * | | v v | | + * <====|=|=================================|=|==> (memory bus) + * | | ^ ^ | | + * (ipi | +------|---------+--------|-------|-+ (device irq) + * irq | | | | | + * core0)| +------|---------|--------|-------+ (ipi irq core1) + * | | | | | + * +----o-o-+ | +--------+ | + * | ompic |<===/ | Device |<===/ + * | IPI | +--------+ + * +--------+* + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define OMPIC_CPUBYTES 8 +#define OMPIC_CTRL(cpu) (0x0 + (cpu * OMPIC_CPUBYTES)) +#define OMPIC_STAT(cpu) (0x4 + (cpu * OMPIC_CPUBYTES)) + +#define OMPIC_CTRL_IRQ_ACK (1 << 31) +#define OMPIC_CTRL_IRQ_GEN (1 << 30) +#define OMPIC_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16) + +#define OMPIC_STAT_IRQ_PENDING (1 << 30) + +#define OMPIC_DATA(x) ((x) & 0xffff) + +DEFINE_PER_CPU(unsigned long, ops); + +static void __iomem *ompic_base; + +static inline u32 ompic_readreg(void __iomem *base, loff_t offset) +{ + return ioread32be(base + offset); +} + +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data) +{ + iowrite32be(data, base + offset); +} + +static void ompic_raise_softirq(const struct cpumask *mask, + unsigned int ipi_msg) +{ + unsigned int dst_cpu; + unsigned int src_cpu = smp_processor_id(); + + for_each_cpu(dst_cpu, mask) { + set_bit(ipi_msg, &per_cpu(ops, dst_cpu)); + + /* + * On OpenRISC the atomic set_bit() call implies a memory + * barrier. Otherwise we would need: smp_wmb(); paired + * with the read in ompic_ipi_handler. + */ + + ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu), + OMPIC_CTRL_IRQ_GEN | + OMPIC_CTRL_DST(dst_cpu) | + OMPIC_DATA(1)); + } +} + +static irqreturn_t ompic_ipi_handler(int irq, void *dev_id) +{ + unsigned int cpu = smp_processor_id(); + unsigned long *pending_ops = &per_cpu(ops, cpu); + unsigned long ops; + + ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK); + while ((ops = xchg(pending_ops, 0)) != 0) { + + /* + * On OpenRISC the atomic xchg() call implies a memory + * barrier. Otherwise we may need an smp_rmb(); paired + * with the write in ompic_raise_softirq. + */ + + do { + unsigned long ipi_msg; + + ipi_msg = __ffs(ops); + ops &= ~(1UL << ipi_msg); + + handle_IPI(ipi_msg); + } while (ops); + } + + return IRQ_HANDLED; +} + +static int __init ompic_of_init(struct device_node *node, + struct device_node *parent) +{ + struct resource res; + int irq; + int ret; + + /* Validate the DT */ + if (ompic_base) { + pr_err("ompic: duplicate ompic's are not supported"); + return -EEXIST; + } + + if (of_address_to_resource(node, 0, &res)) { + pr_err("ompic: reg property requires an address and size"); + return -EINVAL; + } + + if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) { + pr_err("ompic: reg size, currently %d must be at least %d", + resource_size(&res), + (num_possible_cpus() * OMPIC_CPUBYTES)); + return -EINVAL; + } + + /* Setup the device */ + ompic_base = ioremap(res.start, resource_size(&res)); + if (IS_ERR(ompic_base)) { + pr_err("ompic: unable to map registers"); + return PTR_ERR(ompic_base); + } + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) { + pr_err("ompic: unable to parse device irq"); + ret = -EINVAL; + goto out_unmap; + } + + ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU, + "ompic_ipi", NULL); + if (ret) + goto out_irq_disp; + + set_smp_cross_call(ompic_raise_softirq); + + return 0; + +out_irq_disp: + irq_dispose_mapping(irq); +out_unmap: + iounmap(ompic_base); + ompic_base = NULL; + return ret; +} +IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init); -- cgit v1.2.3 From fa687604fa750f934dbbebb7a5b6cda570e88cb8 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 11 Sep 2017 00:31:52 +0200 Subject: dt-bindings: arm: actions: Add CubieBoard6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define a compatible string for Cubietech CubieBoard6. Cc: support@cubietech.com Acked-by: Rob Herring Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/arm/actions.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt index 3bc7ea575564..ced764a8549e 100644 --- a/Documentation/devicetree/bindings/arm/actions.txt +++ b/Documentation/devicetree/bindings/arm/actions.txt @@ -21,6 +21,7 @@ Boards: Root node property compatible must contain, depending on board: + - Cubietech CubieBoard6: "cubietech,cubieboard6" - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar" -- cgit v1.2.3 From edd20e95bca4a5434f264d8ab40d729761479825 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 1 Nov 2017 10:53:30 +1030 Subject: i2c: aspeed: Deassert reset in probe In order to use i2c from a cold boot, the i2c peripheral must be taken out of reset. We request a shared reset controller each time a bus driver is loaded, as the reset is shared between the 14 i2c buses. On remove the reset is asserted, which only touches the hardware once the last i2c bus is removed. The reset is required as the I2C buses will not work without releasing the reset. Previously the driver only worked with out of tree hacks that released this reset before the driver was loaded. Update the device tree bindings to reflect this. Signed-off-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-aspeed.txt | 7 +++++-- drivers/i2c/busses/i2c-aspeed.c | 12 ++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt index bd6480b19535..e7106bfc1f13 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt @@ -7,7 +7,9 @@ Required Properties: - compatible : should be "aspeed,ast2400-i2c-bus" or "aspeed,ast2500-i2c-bus" - clocks : root clock of bus, should reference the APB - clock + clock in the second cell +- resets : phandle to reset controller with the reset number in + the second cell - interrupts : interrupt number - interrupt-parent : interrupt controller for bus, should reference a aspeed,ast2400-i2c-ic or aspeed,ast2500-i2c-ic @@ -40,7 +42,8 @@ i2c { #interrupt-cells = <1>; reg = <0x40 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <0>; interrupt-parent = <&i2c_ic>; diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 284f8670dbeb..7d4aeb4465b3 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -27,6 +27,7 @@ #include #include #include +#include #include /* I2C Register */ @@ -132,6 +133,7 @@ struct aspeed_i2c_bus { struct i2c_adapter adap; struct device *dev; void __iomem *base; + struct reset_control *rst; /* Synchronizes I/O mem access to base. */ spinlock_t lock; struct completion cmd_complete; @@ -847,6 +849,14 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev) /* We just need the clock rate, we don't actually use the clk object. */ devm_clk_put(&pdev->dev, parent_clk); + bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL); + if (IS_ERR(bus->rst)) { + dev_err(&pdev->dev, + "missing or invalid reset controller device tree entry"); + return PTR_ERR(bus->rst); + } + reset_control_deassert(bus->rst); + ret = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &bus->bus_frequency); if (ret < 0) { @@ -917,6 +927,8 @@ static int aspeed_i2c_remove_bus(struct platform_device *pdev) spin_unlock_irqrestore(&bus->lock, flags); + reset_control_assert(bus->rst); + i2c_del_adapter(&bus->adap); return 0; -- cgit v1.2.3 From ded0eb83449e8fcba22fd2736826336e101ffbcb Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Fri, 3 Nov 2017 15:53:01 +1100 Subject: dt-bindings: pmbus: Add Maxim MAX31785 documentation Signed-off-by: Andrew Jeffery Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- .../devicetree/bindings/hwmon/max31785.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/max31785.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/max31785.txt b/Documentation/devicetree/bindings/hwmon/max31785.txt new file mode 100644 index 000000000000..106e08c56aaa --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/max31785.txt @@ -0,0 +1,22 @@ +Bindings for the Maxim MAX31785 Intelligent Fan Controller +========================================================== + +Reference: + +https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf + +The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan +management with temperature and remote voltage sensing. Various fan control +features are provided, including PWM frequency control, temperature hysteresis, +dual tachometer measurements, and fan health monitoring. + +Required properties: +- compatible : One of "maxim,max31785" or "maxim,max31785a" +- reg : I2C address, one of 0x52, 0x53, 0x54, 0x55. + +Example: + + fans@52 { + compatible = "maxim,max31785"; + reg = <0x52>; + }; -- cgit v1.2.3 From 0ea04c7322b0dbbc4e7a862451855b10ef9922d3 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 6 Nov 2017 18:34:36 +0000 Subject: dt-bindings: Add description of Socionext EXIU interrupt controller Add a description of the External Interrupt Unit (EXIU) interrupt controller as found on the Socionext SynQuacer SoC. Acked-by: Rob Herring Signed-off-by: Ard Biesheuvel Signed-off-by: Marc Zyngier --- .../socionext,synquacer-exiu.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt new file mode 100644 index 000000000000..8b2faefe29ca --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt @@ -0,0 +1,32 @@ +Socionext SynQuacer External Interrupt Unit (EXIU) + +The Socionext Synquacer SoC has an external interrupt unit (EXIU) +that forwards a block of 32 configurable input lines to 32 adjacent +level-high type GICv3 SPIs. + +Required properties: + +- compatible : Should be "socionext,synquacer-exiu". +- reg : Specifies base physical address and size of the + control registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 3. +- interrupt-parent : phandle of the GIC these interrupts are routed to. +- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent + ones the EXIU forwards its interrups to. + +Notes: + +- Only SPIs can use the EXIU as an interrupt parent. + +Example: + + exiu: interrupt-controller@510c0000 { + compatible = "socionext,synquacer-exiu"; + reg = <0x0 0x510c0000 0x0 0x20>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + socionext,spi-base = <112>; + }; -- cgit v1.2.3 From ce0b7e39c5a0c65bdce6fc36bba2991ea8f915b7 Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Mon, 6 Nov 2017 18:03:33 +0100 Subject: dt-bindings/interrupt-controllers: Add compatible string for stm32h7 This patch updates stm32-exti documentation with stm32h7-exti compatible string. Acked-by: Rob Herring Signed-off-by: Ludovic Barre Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt index 6e7703d4ff5b..edf03f09244b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt @@ -2,7 +2,9 @@ STM32 External Interrupt Controller Required properties: -- compatible: Should be "st,stm32-exti" +- compatible: Should be: + "st,stm32-exti" + "st,stm32h7-exti" - reg: Specifies base physical address and size of the registers - interrupt-controller: Indentifies the node as an interrupt controller - #interrupt-cells: Specifies the number of cells to encode an interrupt -- cgit v1.2.3 From 167e5b6f98d27901c7a00b566938ce1973af4395 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 6 Nov 2017 15:29:22 +0000 Subject: dt-bindings: sdhci-fujitsu: document cmd-dat-delay property Document a new boolean property of the sdhci-fujitsu binding that indicates whether the CMD_DAT_DELAY bit needs to be set in the F_SDH30_ESD_CONTROL register. Acked-by: Rob Herring Signed-off-by: Ard Biesheuvel Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt b/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt index de2c53cff4f1..3ee9263adf73 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt @@ -15,6 +15,8 @@ Required properties: Optional properties: - vqmmc-supply: phandle to the regulator device tree node, mentioned as the VCCQ/VDD_IO supply in the eMMC/SD specs. +- fujitsu,cmd-dat-delay-select: boolean property indicating that this host + requires the CMD_DAT_DELAY control to be enabled. Example: -- cgit v1.2.3 From ec473a9c40416ef1802088e9f9d44d40c16aac6a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdelin Date: Thu, 2 Nov 2017 14:17:12 -0400 Subject: dt-bindings: bus: Add documentation for the Technologic Systems NBUS Add binding documentation for the Technologic Systems NBUS that is used to interface with peripherals in the FPGA of the TS-4600 SoM. Signed-off-by: Sebastien Bourdelin Acked-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/bus/ts-nbus.txt | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/ts-nbus.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/ts-nbus.txt b/Documentation/devicetree/bindings/bus/ts-nbus.txt new file mode 100644 index 000000000000..2a10d065b9fa --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ts-nbus.txt @@ -0,0 +1,50 @@ +Technologic Systems NBUS + +The NBUS is a bus used to interface with peripherals in the Technologic +Systems FPGA on the TS-4600 SoM. + +Required properties : + - compatible : "technologic,ts-nbus" + - #address-cells : must be 1 + - #size-cells : must be 0 + - pwms : The PWM bound to the FPGA + - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA + - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA + - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA + - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA + - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA + - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA + +Child nodes: + +The NBUS node can contain zero or more child nodes representing peripherals +on the bus. + +Example: + + nbus { + compatible = "technologic,ts-nbus"; + pinctrl-0 = <&nbus_pins>; + #address-cells = <1>; + #size-cells = <0>; + pwms = <&pwm 2 83>; + ts,data-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH + &gpio0 1 GPIO_ACTIVE_HIGH + &gpio0 2 GPIO_ACTIVE_HIGH + &gpio0 3 GPIO_ACTIVE_HIGH + &gpio0 4 GPIO_ACTIVE_HIGH + &gpio0 5 GPIO_ACTIVE_HIGH + &gpio0 6 GPIO_ACTIVE_HIGH + &gpio0 7 GPIO_ACTIVE_HIGH>; + ts,csn-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + ts,txrx-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + ts,strobe-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + ts,ale-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + ts,rdy-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + + watchdog@2a { + compatible = "..."; + + /* ... */ + }; + }; -- cgit v1.2.3 From fa1e6a8aec47d5623f8361907f57e44f112a8f4f Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Wed, 20 Sep 2017 13:14:04 +0200 Subject: tty/bcm63xx_uart: allow naming clock in device tree Codify using a named clock for the refclk of the uart. This makes it easier if we might need to add a gating clock (like present on the BCM6345). Signed-off-by: Jonas Gorski Acked-by: Rob Herring Acked-by: Greg Kroah-Hartman Reviewed-by: Florian Fainelli Cc: Mark Rutland Cc: Kevin Cernekee Cc: Russell King Cc: linux-mips@linux-mips.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: bcm-kernel-feedback-list@broadcom.com Patchwork: https://patchwork.linux-mips.org/patch/17328/ Signed-off-by: Ralf Baechle Signed-off-by: James Hogan --- Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt | 6 ++++++ drivers/tty/serial/bcm63xx_uart.c | 6 ++++-- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt index 5c52e5eef16d..8b2b0460259a 100644 --- a/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt +++ b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt @@ -11,6 +11,11 @@ Required properties: - clocks: Clock driving the hardware; used to figure out the baud rate divisor. + +Optional properties: + +- clock-names: Should be "refclk". + Example: uart0: serial@14e00520 { @@ -19,6 +24,7 @@ Example: interrupt-parent = <&periph_intc>; interrupts = <2>; clocks = <&periph_clk>; + clock-names = "refclk"; }; clocks { diff --git a/drivers/tty/serial/bcm63xx_uart.c b/drivers/tty/serial/bcm63xx_uart.c index afcc0418831b..0385bd361f4f 100644 --- a/drivers/tty/serial/bcm63xx_uart.c +++ b/drivers/tty/serial/bcm63xx_uart.c @@ -846,8 +846,10 @@ static int bcm_uart_probe(struct platform_device *pdev) if (!res_irq) return -ENODEV; - clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) : - clk_get(&pdev->dev, "refclk"); + clk = clk_get(&pdev->dev, "refclk"); + if (IS_ERR(clk) && pdev->dev.of_node) + clk = of_clk_get(pdev->dev.of_node, 0); + if (IS_ERR(clk)) return -ENODEV; -- cgit v1.2.3 From 4ad1ceec05e49175d0f967cc87628101e79176f6 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Fri, 3 Nov 2017 10:29:59 -0700 Subject: net: fec: Let fec_ptp have its own interrupt routine This is better for code locality and should slightly speed up normal interrupts. This also allows PPS clock output to start working for i.mx7. This is because i.mx7 was already using the limit of 3 interrupts, and needed another. Signed-off-by: Troy Kisky Acked-by: Fugang Duan Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/fsl-fec.txt | 13 ++++ drivers/net/ethernet/freescale/fec.h | 3 +- drivers/net/ethernet/freescale/fec_main.c | 31 ++++++--- drivers/net/ethernet/freescale/fec_ptp.c | 82 +++++++++++++---------- 4 files changed, 84 insertions(+), 45 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 6f55bdd52f8a..f0dc94409107 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -34,6 +34,19 @@ Optional properties: - fsl,err006687-workaround-present: If present indicates that the system has the hardware workaround for ERR006687 applied and does not need a software workaround. + -interrupt-names: names of the interrupts listed in interrupts property in + the same order. The defaults if not specified are + __Number of interrupts__ __Default__ + 1 "int0" + 2 "int0", "pps" + 3 "int0", "int1", "int2" + 4 "int0", "int1", "int2", "pps" + The order may be changed as long as they correspond to the interrupts + property. Currently, only i.mx7 uses "int1" and "int2". They correspond to + tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. + For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse + per second interrupt associated with 1588 precision time protocol(PTP). + Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index 44720f83af27..5385074b3b7d 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -583,12 +583,11 @@ struct fec_enet_private { u64 ethtool_stats[0]; }; -void fec_ptp_init(struct platform_device *pdev); +void fec_ptp_init(struct platform_device *pdev, int irq_idx); void fec_ptp_stop(struct platform_device *pdev); void fec_ptp_start_cyclecounter(struct net_device *ndev); int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); -uint fec_ptp_check_pps_event(struct fec_enet_private *fep); /****************************************************************************/ #endif /* FEC_H */ diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 3dc2d771a222..610573855213 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1602,10 +1602,6 @@ fec_enet_interrupt(int irq, void *dev_id) ret = IRQ_HANDLED; complete(&fep->mdio_done); } - - if (fep->ptp_clock) - if (fec_ptp_check_pps_event(fep)) - ret = IRQ_HANDLED; return ret; } @@ -3312,6 +3308,19 @@ fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) } +static int fec_enet_get_irq_cnt(struct platform_device *pdev) +{ + int irq_cnt = platform_irq_count(pdev); + + if (irq_cnt > FEC_IRQ_NUM) + irq_cnt = FEC_IRQ_NUM; /* last for pps */ + else if (irq_cnt == 2) + irq_cnt = 1; /* last for pps */ + else if (irq_cnt <= 0) + irq_cnt = 1; /* At least 1 irq is needed */ + return irq_cnt; +} + static int fec_probe(struct platform_device *pdev) { @@ -3325,6 +3334,8 @@ fec_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node, *phy_node; int num_tx_qs; int num_rx_qs; + char irq_name[8]; + int irq_cnt; fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); @@ -3465,18 +3476,20 @@ fec_probe(struct platform_device *pdev) if (ret) goto failed_reset; + irq_cnt = fec_enet_get_irq_cnt(pdev); if (fep->bufdesc_ex) - fec_ptp_init(pdev); + fec_ptp_init(pdev, irq_cnt); ret = fec_enet_init(ndev); if (ret) goto failed_init; - for (i = 0; i < FEC_IRQ_NUM; i++) { - irq = platform_get_irq(pdev, i); + for (i = 0; i < irq_cnt; i++) { + sprintf(irq_name, "int%d", i); + irq = platform_get_irq_byname(pdev, irq_name); + if (irq < 0) + irq = platform_get_irq(pdev, i); if (irq < 0) { - if (i) - break; ret = irq; goto failed_irq; } diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/ethernet/freescale/fec_ptp.c index 6ebad3fac81d..f81439796ac7 100644 --- a/drivers/net/ethernet/freescale/fec_ptp.c +++ b/drivers/net/ethernet/freescale/fec_ptp.c @@ -549,6 +549,37 @@ static void fec_time_keep(struct work_struct *work) schedule_delayed_work(&fep->time_keep, HZ); } +/* This function checks the pps event and reloads the timer compare counter. */ +static irqreturn_t fec_pps_interrupt(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct fec_enet_private *fep = netdev_priv(ndev); + u32 val; + u8 channel = fep->pps_channel; + struct ptp_clock_event event; + + val = readl(fep->hwp + FEC_TCSR(channel)); + if (val & FEC_T_TF_MASK) { + /* Write the next next compare(not the next according the spec) + * value to the register + */ + writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); + do { + writel(val, fep->hwp + FEC_TCSR(channel)); + } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); + + /* Update the counter; */ + fep->next_counter = (fep->next_counter + fep->reload_period) & + fep->cc.mask; + + event.type = PTP_CLOCK_PPS; + ptp_clock_event(fep->ptp_clock, &event); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + /** * fec_ptp_init * @ndev: The FEC network adapter @@ -558,10 +589,12 @@ static void fec_time_keep(struct work_struct *work) * cyclecounter init routine and exits. */ -void fec_ptp_init(struct platform_device *pdev) +void fec_ptp_init(struct platform_device *pdev, int irq_idx) { struct net_device *ndev = platform_get_drvdata(pdev); struct fec_enet_private *fep = netdev_priv(ndev); + int irq; + int ret; fep->ptp_caps.owner = THIS_MODULE; snprintf(fep->ptp_caps.name, 16, "fec ptp"); @@ -587,6 +620,20 @@ void fec_ptp_init(struct platform_device *pdev) INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep); + irq = platform_get_irq_byname(pdev, "pps"); + if (irq < 0) + irq = platform_get_irq(pdev, irq_idx); + /* Failure to get an irq is not fatal, + * only the PTP_CLOCK_PPS clock events should stop + */ + if (irq >= 0) { + ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt, + 0, pdev->name, ndev); + if (ret < 0) + dev_warn(&pdev->dev, "request for pps irq failed(%d)\n", + ret); + } + fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev); if (IS_ERR(fep->ptp_clock)) { fep->ptp_clock = NULL; @@ -605,36 +652,3 @@ void fec_ptp_stop(struct platform_device *pdev) if (fep->ptp_clock) ptp_clock_unregister(fep->ptp_clock); } - -/** - * fec_ptp_check_pps_event - * @fep: the fec_enet_private structure handle - * - * This function check the pps event and reload the timer compare counter. - */ -uint fec_ptp_check_pps_event(struct fec_enet_private *fep) -{ - u32 val; - u8 channel = fep->pps_channel; - struct ptp_clock_event event; - - val = readl(fep->hwp + FEC_TCSR(channel)); - if (val & FEC_T_TF_MASK) { - /* Write the next next compare(not the next according the spec) - * value to the register - */ - writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); - do { - writel(val, fep->hwp + FEC_TCSR(channel)); - } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); - - /* Update the counter; */ - fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; - - event.type = PTP_CLOCK_PPS; - ptp_clock_event(fep->ptp_clock, &event); - return 1; - } - - return 0; -} -- cgit v1.2.3 From 68d50fa494f6265288b60151a6460b33290593c2 Mon Sep 17 00:00:00 2001 From: Egil Hjelmeland Date: Mon, 6 Nov 2017 12:42:02 +0100 Subject: net: dsa: lan9303: Fix syntax errors in device tree examples Signed-off-by: Egil Hjelmeland Reviewed-by: Vivien Didelot Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/lan9303.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/lan9303.txt b/Documentation/devicetree/bindings/net/dsa/lan9303.txt index 4448d063ddf6..464d6bf87605 100644 --- a/Documentation/devicetree/bindings/net/dsa/lan9303.txt +++ b/Documentation/devicetree/bindings/net/dsa/lan9303.txt @@ -52,7 +52,7 @@ I2C managed mode: port@1 { /* external port 1 */ reg = <1>; - label = "lan1; + label = "lan1"; }; port@2 { /* external port 2 */ @@ -89,7 +89,7 @@ MDIO managed mode: port@1 { /* external port 1 */ reg = <1>; - label = "lan1; + label = "lan1"; }; port@2 { /* external port 2 */ -- cgit v1.2.3 From a9687aa2764dd2669602bd19dc636cbeef5293d5 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 1 Nov 2017 08:01:20 -0700 Subject: rtc: add support for NXP PCF85363 real-time clock Note that alarms are not currently implemented. 64 bytes of nvmem is supported and exposed in sysfs (# is the instance number, starting with 0): /sys/bus/nvmem/devices/pcf85363-#/nvmem Signed-off-by: Eric Nelson Reviewed-by: Fabio Estevam Tested-by: Alexandre Belloni Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/pcf85363.txt | 17 ++ drivers/rtc/Kconfig | 13 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-pcf85363.c | 220 +++++++++++++++++++++ 4 files changed, 251 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/pcf85363.txt create mode 100644 drivers/rtc/rtc-pcf85363.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt new file mode 100644 index 000000000000..76fdabc59742 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt @@ -0,0 +1,17 @@ +NXP PCF85363 Real Time Clock +============================ + +Required properties: +- compatible: Should contain "nxp,pcf85363". +- reg: I2C address for chip. + +Optional properties: +- interrupts: IRQ line for the RTC (not implemented). + +Example: + +pcf85363: pcf85363@51 { + compatible = "nxp,pcf85363"; + reg = <0x51>; +}; + diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 616fe53c788e..47663e03f9a8 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -433,6 +433,19 @@ config RTC_DRV_PCF85063 This driver can also be built as a module. If so, the module will be called rtc-pcf85063. +config RTC_DRV_PCF85363 + tristate "NXP PCF85363" + depends on I2C + select REGMAP_I2C + help + If you say yes here you get support for the PCF85363 RTC chip. + + This driver can also be built as a module. If so, the module + will be called rtc-pcf85363. + + The nvmem interface will be named pcf85363-#, where # is the + zero-based instance number. + config RTC_DRV_PCF8563 tristate "Philips PCF8563/Epson RTC8564" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 5ec891a81f4f..0b5acd6b5cc3 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -114,6 +114,7 @@ obj-$(CONFIG_RTC_DRV_PCF2123) += rtc-pcf2123.o obj-$(CONFIG_RTC_DRV_PCF2127) += rtc-pcf2127.o obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o obj-$(CONFIG_RTC_DRV_PCF85063) += rtc-pcf85063.o +obj-$(CONFIG_RTC_DRV_PCF85363) += rtc-pcf85363.o obj-$(CONFIG_RTC_DRV_PCF8523) += rtc-pcf8523.o obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c new file mode 100644 index 000000000000..ea04e9f0930b --- /dev/null +++ b/drivers/rtc/rtc-pcf85363.c @@ -0,0 +1,220 @@ +/* + * drivers/rtc/rtc-pcf85363.c + * + * Driver for NXP PCF85363 real-time clock. + * + * Copyright (C) 2017 Eric Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Based loosely on rtc-8583 by Russell King, Wolfram Sang and Juergen Beisert + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Date/Time registers + */ +#define DT_100THS 0x00 +#define DT_SECS 0x01 +#define DT_MINUTES 0x02 +#define DT_HOURS 0x03 +#define DT_DAYS 0x04 +#define DT_WEEKDAYS 0x05 +#define DT_MONTHS 0x06 +#define DT_YEARS 0x07 + +/* + * Alarm registers + */ +#define DT_SECOND_ALM1 0x08 +#define DT_MINUTE_ALM1 0x09 +#define DT_HOUR_ALM1 0x0a +#define DT_DAY_ALM1 0x0b +#define DT_MONTH_ALM1 0x0c +#define DT_MINUTE_ALM2 0x0d +#define DT_HOUR_ALM2 0x0e +#define DT_WEEKDAY_ALM2 0x0f +#define DT_ALARM_EN 0x10 + +/* + * Time stamp registers + */ +#define DT_TIMESTAMP1 0x11 +#define DT_TIMESTAMP2 0x17 +#define DT_TIMESTAMP3 0x1d +#define DT_TS_MODE 0x23 + +/* + * control registers + */ +#define CTRL_OFFSET 0x24 +#define CTRL_OSCILLATOR 0x25 +#define CTRL_BATTERY 0x26 +#define CTRL_PIN_IO 0x27 +#define CTRL_FUNCTION 0x28 +#define CTRL_INTA_EN 0x29 +#define CTRL_INTB_EN 0x2a +#define CTRL_FLAGS 0x2b +#define CTRL_RAMBYTE 0x2c +#define CTRL_WDOG 0x2d +#define CTRL_STOP_EN 0x2e +#define CTRL_RESETS 0x2f +#define CTRL_RAM 0x40 + +#define NVRAM_SIZE 0x40 + +static struct i2c_driver pcf85363_driver; + +struct pcf85363 { + struct device *dev; + struct rtc_device *rtc; + struct nvmem_config nvmem_cfg; + struct regmap *regmap; +}; + +static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct pcf85363 *pcf85363 = dev_get_drvdata(dev); + unsigned char buf[DT_YEARS + 1]; + int ret, len = sizeof(buf); + + /* read the RTC date and time registers all at once */ + ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len); + if (ret) { + dev_err(dev, "%s: error %d\n", __func__, ret); + return ret; + } + + tm->tm_year = bcd2bin(buf[DT_YEARS]); + /* adjust for 1900 base of rtc_time */ + tm->tm_year += 100; + + tm->tm_wday = buf[DT_WEEKDAYS] & 7; + buf[DT_SECS] &= 0x7F; + tm->tm_sec = bcd2bin(buf[DT_SECS]); + buf[DT_MINUTES] &= 0x7F; + tm->tm_min = bcd2bin(buf[DT_MINUTES]); + tm->tm_hour = bcd2bin(buf[DT_HOURS]); + tm->tm_mday = bcd2bin(buf[DT_DAYS]); + tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1; + + return 0; +} + +static int pcf85363_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct pcf85363 *pcf85363 = dev_get_drvdata(dev); + unsigned char buf[DT_YEARS + 1]; + int len = sizeof(buf); + + buf[DT_100THS] = 0; + buf[DT_SECS] = bin2bcd(tm->tm_sec); + buf[DT_MINUTES] = bin2bcd(tm->tm_min); + buf[DT_HOURS] = bin2bcd(tm->tm_hour); + buf[DT_DAYS] = bin2bcd(tm->tm_mday); + buf[DT_WEEKDAYS] = tm->tm_wday; + buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1); + buf[DT_YEARS] = bin2bcd(tm->tm_year % 100); + + return regmap_bulk_write(pcf85363->regmap, DT_100THS, + buf, len); +} + +static const struct rtc_class_ops rtc_ops = { + .read_time = pcf85363_rtc_read_time, + .set_time = pcf85363_rtc_set_time, +}; + +static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val, + size_t bytes) +{ + struct pcf85363 *pcf85363 = priv; + + return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset, + val, bytes); +} + +static int pcf85363_nvram_write(void *priv, unsigned int offset, void *val, + size_t bytes) +{ + struct pcf85363 *pcf85363 = priv; + + return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset, + val, bytes); +} + +static const struct regmap_config regmap_config = { + .reg_bits = 8, + .val_bits = 8, +}; + +static int pcf85363_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pcf85363 *pcf85363; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return -ENODEV; + + pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363), + GFP_KERNEL); + if (!pcf85363) + return -ENOMEM; + + pcf85363->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(pcf85363->regmap)) { + dev_err(&client->dev, "regmap allocation failed\n"); + return PTR_ERR(pcf85363->regmap); + } + + pcf85363->dev = &client->dev; + i2c_set_clientdata(client, pcf85363); + + pcf85363->rtc = devm_rtc_allocate_device(pcf85363->dev); + if (IS_ERR(pcf85363->rtc)) + return PTR_ERR(pcf85363->rtc); + + pcf85363->nvmem_cfg.name = "pcf85363-"; + pcf85363->nvmem_cfg.word_size = 1; + pcf85363->nvmem_cfg.stride = 1; + pcf85363->nvmem_cfg.size = NVRAM_SIZE; + pcf85363->nvmem_cfg.reg_read = pcf85363_nvram_read; + pcf85363->nvmem_cfg.reg_write = pcf85363_nvram_write; + pcf85363->nvmem_cfg.priv = pcf85363; + pcf85363->rtc->nvmem_config = &pcf85363->nvmem_cfg; + pcf85363->rtc->ops = &rtc_ops; + + return rtc_register_device(pcf85363->rtc); +} + +static const struct of_device_id dev_ids[] = { + { .compatible = "nxp,pcf85363" }, + {} +}; +MODULE_DEVICE_TABLE(of, dev_ids); + +static struct i2c_driver pcf85363_driver = { + .driver = { + .name = "pcf85363", + .of_match_table = of_match_ptr(dev_ids), + }, + .probe = pcf85363_probe, +}; + +module_i2c_driver(pcf85363_driver); + +MODULE_AUTHOR("Eric Nelson"); +MODULE_DESCRIPTION("pcf85363 I2C RTC driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From e0e1e39de490a2d9b8a173363ccf2415ddada871 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Oct 2017 15:37:17 +0200 Subject: pinctrl: Add skew-delay pin config and bindings Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring Acked-by: Hans Ulli Kroll Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 4 ++++ drivers/pinctrl/pinconf-generic.c | 2 ++ include/linux/pinctrl/pinconf-generic.h | 5 +++++ 3 files changed, 11 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index 4483cc31e531..ad9bbbba36e9 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -271,6 +271,10 @@ output-high - set the pin to output mode with high level sleep-hardware-state - indicate this is sleep related state which will be programmed into the registers for the sleep state. slew-rate - set the slew rate +skew-delay - this affects the expected clock skew on input pins + and the delay before latching a value to an output + pin. Typically indicates how many double-inverters are + used to delay the signal. For example: diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 8eaa25c3384f..b4f7f8a458ea 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -49,6 +49,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), + PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -181,6 +182,7 @@ static const struct pinconf_generic_params dt_params[] = { { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, }; /** diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 5d8bc7f21c2a..ec6dadcc1fde 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -90,6 +90,10 @@ * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to * this parameter (on a custom format) tells the driver which alternative * slew rate to use. + * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs) + * or latch delay (on outputs) this parameter (in a custom format) + * specifies the clock skew or latch delay. It typically controls how + * many double inverters are put in front of the line. * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if * you need to pass in custom configurations to the pin controller, use * PIN_CONFIG_END+1 as the base offset. @@ -117,6 +121,7 @@ enum pin_config_param { PIN_CONFIG_POWER_SOURCE, PIN_CONFIG_SLEEP_HARDWARE_STATE, PIN_CONFIG_SLEW_RATE, + PIN_CONFIG_SKEW_DELAY, PIN_CONFIG_END = 0x7F, PIN_CONFIG_MAX = 0xFF, }; -- cgit v1.2.3 From 60ad481f74a6d5ffb38e2c2ea325324e82081e7e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 28 Oct 2017 15:37:19 +0200 Subject: pinctrl: gemini: Implement clock skew/delay config This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: Hans Ulli Kroll Signed-off-by: Linus Walleij --- .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 10 +- drivers/pinctrl/pinctrl-gemini.c | 178 ++++++++++++++++++++- 2 files changed, 182 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt index 61466c58faae..d857b67fab72 100644 --- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt @@ -9,8 +9,14 @@ The pin controller node must be a subnode of the system controller node. Required properties: - compatible: "cortina,gemini-pinctrl" -Subnodes of the pin controller contain pin control multiplexing set-up. -Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes. +Subnodes of the pin controller contain pin control multiplexing set-up +and pin configuration of individual pins. + +Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes +and generic pin config nodes. + +Supported configurations: +- skew-delay is supported on the Ethernet pins Example: diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 18fb5ff8a442..bd6133f06759 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -24,6 +24,19 @@ #define DRIVER_NAME "pinctrl-gemini" /** + * struct gemini_pin_conf - information about configuring a pin + * @pin: the pin number + * @reg: config register + * @mask: the bits affecting the configuration of the pin + */ +struct gemini_pin_conf { + unsigned int pin; + u32 reg; + u32 mask; +}; + +/** + * struct gemini_pmx - state holder for the gemini pin controller * @dev: a pointer back to containing device * @virtbase: the offset to the controller in virtual memory * @map: regmap to access registers @@ -31,6 +44,8 @@ * @is_3516: whether the SoC/package is the 3516 variant * @flash_pin: whether the flash pin (extended pins for parallel * flash) is set + * @confs: pin config information + * @nconfs: number of pin config information items */ struct gemini_pmx { struct device *dev; @@ -39,6 +54,8 @@ struct gemini_pmx { bool is_3512; bool is_3516; bool flash_pin; + const struct gemini_pin_conf *confs; + unsigned int nconfs; }; /** @@ -59,6 +76,13 @@ struct gemini_pin_group { u32 value; }; +/* Some straight-forward control registers */ +#define GLOBAL_WORD_ID 0x00 +#define GLOBAL_STATUS 0x04 +#define GLOBAL_STATUS_FLPIN BIT(20) +#define GLOBAL_GMAC_CTRL_SKEW 0x1c +#define GLOBAL_GMAC0_DATA_SKEW 0x20 +#define GLOBAL_GMAC1_DATA_SKEW 0x24 /* * Global Miscellaneous Control Register * This register controls all Gemini pad/pin multiplexing @@ -71,9 +95,6 @@ struct gemini_pin_group { * DISABLED again. So you select a flash configuration once, and then * you are stuck with it. */ -#define GLOBAL_WORD_ID 0x00 -#define GLOBAL_STATUS 0x04 -#define GLOBAL_STATUS_FLPIN BIT(20) #define GLOBAL_MISC_CTRL 0x30 #define TVC_CLK_PAD_ENABLE BIT(20) #define PCI_CLK_PAD_ENABLE BIT(17) @@ -1925,7 +1946,7 @@ static const struct pinctrl_ops gemini_pctrl_ops = { .get_group_name = gemini_get_group_name, .get_group_pins = gemini_get_group_pins, .pin_dbg_show = gemini_pin_dbg_show, - .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinconf_generic_dt_free_map, }; @@ -2203,10 +2224,155 @@ static const struct pinmux_ops gemini_pmx_ops = { .set_mux = gemini_pmx_set_mux, }; +#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ + .pin = _n, \ + .reg = _r, \ + .mask = GENMASK(_hb, _lb) \ +} + +static const struct gemini_pin_conf gemini_confs_3512[] = { + GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ + GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ + GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ + GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ + GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ + GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ + GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ + GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ + GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ + GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ + GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ + GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ + GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ + GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ + GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ + GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ + GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ + GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ + GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ + GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ + GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ + GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ + GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ + GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ +}; + +static const struct gemini_pin_conf gemini_confs_3516[] = { + GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ + GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ + GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ + GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ + GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ + GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ + GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ + GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ + GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ + GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ + GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ + GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ + GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ + GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ + GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ + GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ + GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ + GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ + GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ + GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ + GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ + GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ + GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ + GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ +}; + +static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, + unsigned int pin) +{ + const struct gemini_pin_conf *retconf; + int i; + + for (i = 0; i < pmx->nconfs; i++) { + retconf = &gemini_confs_3516[i]; + if (retconf->pin == pin) + return retconf; + } + return NULL; +} + +static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct gemini_pin_conf *conf; + u32 val; + + switch (param) { + case PIN_CONFIG_SKEW_DELAY: + conf = gemini_get_pin_conf(pmx, pin); + if (!conf) + return -ENOTSUPP; + regmap_read(pmx->map, conf->reg, &val); + val &= conf->mask; + val >>= (ffs(conf->mask) - 1); + *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct gemini_pin_conf *conf; + enum pin_config_param param; + u32 arg; + int ret = 0; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_SKEW_DELAY: + if (arg > 0xf) + return -EINVAL; + conf = gemini_get_pin_conf(pmx, pin); + if (!conf) { + dev_err(pmx->dev, + "invalid pin for skew delay %d\n", pin); + return -ENOTSUPP; + } + arg <<= (ffs(conf->mask) - 1); + dev_dbg(pmx->dev, + "set pin %d to skew delay mask %08x, val %08x\n", + pin, conf->mask, arg); + regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); + break; + default: + dev_err(pmx->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + } + + return ret; +} + +static const struct pinconf_ops gemini_pinconf_ops = { + .pin_config_get = gemini_pinconf_get, + .pin_config_set = gemini_pinconf_set, + .is_generic = true, +}; + static struct pinctrl_desc gemini_pmx_desc = { .name = DRIVER_NAME, .pctlops = &gemini_pctrl_ops, .pmxops = &gemini_pmx_ops, + .confops = &gemini_pinconf_ops, .owner = THIS_MODULE, }; @@ -2249,11 +2415,15 @@ static int gemini_pmx_probe(struct platform_device *pdev) val &= 0xffff; if (val == 0x3512) { pmx->is_3512 = true; + pmx->confs = gemini_confs_3512; + pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); gemini_pmx_desc.pins = gemini_3512_pins; gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); dev_info(dev, "detected 3512 chip variant\n"); } else if (val == 0x3516) { pmx->is_3516 = true; + pmx->confs = gemini_confs_3516; + pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); gemini_pmx_desc.pins = gemini_3516_pins; gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); dev_info(dev, "detected 3516 chip variant\n"); -- cgit v1.2.3 From 8d6cfb14088e340acd56264f52a60c8f8f735854 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 2 Nov 2017 14:59:42 +0530 Subject: pinctrl: qcom: spmi-gpio: Add pmi8994 gpio support Update the binding and driver for pmi8994-gpios Signed-off-by: Rajendra Nayak Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 2 ++ drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 2 files changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 5b12c57e7f02..5c25fcb29fb5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -15,6 +15,7 @@ PMIC's from Qualcomm. "qcom,pm8921-gpio" "qcom,pm8941-gpio" "qcom,pm8994-gpio" + "qcom,pmi8994-gpio" "qcom,pma8084-gpio" "qcom,pmi8994-gpio" @@ -85,6 +86,7 @@ to specify in a pin configuration subnode: gpio1-gpio44 for pm8921 gpio1-gpio36 for pm8941 gpio1-gpio22 for pm8994 + gpio1-gpio10 for pmi8994 gpio1-gpio22 for pma8084 gpio1-gpio10 for pmi8994 diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index a0edaa85f22b..3e66e0d10010 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1037,6 +1037,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,spmi-gpio" }, /* Generic */ { }, -- cgit v1.2.3 From 2a96c818f484bcc16f42a09b030a470f2b44df04 Mon Sep 17 00:00:00 2001 From: Keiji Hayashibara Date: Tue, 24 Oct 2017 10:54:25 +0100 Subject: dt-bindings: nvmem: add description for UniPhier eFuse Add uniphier-efuse dt-bindings documentation. Signed-off-by: Keiji Hayashibara Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/uniphier-efuse.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt b/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt new file mode 100644 index 000000000000..eccf490d5a6d --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/uniphier-efuse.txt @@ -0,0 +1,49 @@ += UniPhier eFuse device tree bindings = + +This UniPhier eFuse must be under soc-glue. + +Required properties: +- compatible: should be "socionext,uniphier-efuse" +- reg: should contain the register location and length + += Data cells = +Are child nodes of efuse, bindings of which as described in +bindings/nvmem/nvmem.txt + +Example: + + soc-glue@5f900000 { + compatible = "socionext,uniphier-ld20-soc-glue-debug", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f900000 0x2000>; + + efuse@100 { + compatible = "socionext,uniphier-efuse"; + reg = <0x100 0x28>; + }; + + efuse@200 { + compatible = "socionext,uniphier-efuse"; + reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + usb_mon: usb-mon@54 { + reg = <0x54 0xc>; + }; + }; + }; + += Data consumers = +Are device nodes which consume nvmem data cells. + +Example: + + usb { + ... + nvmem-cells = <&usb_mon>; + nvmem-cell-names = "usb_mon"; + } -- cgit v1.2.3 From b7fe57b802c4f12da20920229acb9fff92300ad4 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 24 Oct 2017 10:54:34 +0100 Subject: nvmem: sunxi-sid: add support for A64/H5's SID controller Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but without the silicon bug that makes the initial value at 0x200 wrong, so the value at 0x200 can be directly read. Add support for this kind of SID controller. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 1 + drivers/nvmem/sunxi_sid.c | 6 ++++++ 2 files changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt index ef06d061913c..6ea0836939ee 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt @@ -5,6 +5,7 @@ Required properties: "allwinner,sun4i-a10-sid" "allwinner,sun7i-a20-sid" "allwinner,sun8i-h3-sid" + "allwinner,sun50i-a64-sid" - reg: Should contain registers location and length diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index 1c3b5cf89212..99bd54d85fcb 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -198,10 +198,16 @@ static const struct sunxi_sid_cfg sun8i_h3_cfg = { .need_register_readout = true, }; +static const struct sunxi_sid_cfg sun50i_a64_cfg = { + .value_offset = 0x200, + .size = 0x100, +}; + static const struct of_device_id sunxi_sid_of_match[] = { { .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg }, { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg }, + { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg }, {/* sentinel */}, }; MODULE_DEVICE_TABLE(of, sunxi_sid_of_match); -- cgit v1.2.3 From 8adc430603d67e76a0f8491df21654f691acda62 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Wed, 8 Nov 2017 15:24:59 -0600 Subject: ASoC: cs42l56: Fix reset GPIO name in example DT binding The binding states the reset GPIO property shall be named "cirrus,gpio-nreset" and this is what the driver looks for, but the example uses "gpio-reset". Fix this here. Fixes: 3bb40619aca8 ("ASoC: cs42l56: bindings: sound: Add bindings for CS42L56 CODEC") Signed-off-by: Andrew F. Davis Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/cs42l56.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/cs42l56.txt b/Documentation/devicetree/bindings/sound/cs42l56.txt index 4feb0eb27ea4..4ba520a28ae8 100644 --- a/Documentation/devicetree/bindings/sound/cs42l56.txt +++ b/Documentation/devicetree/bindings/sound/cs42l56.txt @@ -55,7 +55,7 @@ Example: codec: codec@4b { compatible = "cirrus,cs42l56"; reg = <0x4b>; - gpio-reset = <&gpio 10 0>; + cirrus,gpio-nreset = <&gpio 10 0>; cirrus,chgfreq-divisor = <0x05>; cirrus.ain1_ref_cfg; cirrus,micbias-lvl = <5>; -- cgit v1.2.3 From b2596d70351370530d3fce16f3b6e6f1cd4dbdf0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Sep 2017 12:51:51 -0300 Subject: dt-bindings: mfd: mc13xxx: Remove obsolete property The 'fsl,spi-num-chipselects' property is obsolete according to Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt, so remove it from the example. Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/mc13xxx.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt index 39ba4146769d..ac235fe385fc 100644 --- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt +++ b/Documentation/devicetree/bindings/mfd/mc13xxx.txt @@ -113,7 +113,6 @@ MC13892 regulators: Examples: ecspi@70010000 { /* ECSPI1 */ - fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */ <&gpio4 25 0>; /* GPIO4_25 */ -- cgit v1.2.3 From 924d4db29f1237f9fe90a7439d2ee81837d282bd Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 9 Nov 2017 11:39:20 +0100 Subject: gpio: rcar: Add r8a77995 (R-Car D3) support This patch adds binding for r8a77995 (R-Car D3). This SoC can use "renesas,rcar-gen3-gpio" fallback compatibility. So, this patch doesn't modify the gpio-rcar driver. Signed-off-by: Yoshihiro Shimoda Acked-by: Simon Horman Acked-by: Rob Herring Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 41137a1cc099..a7ac460ad657 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -15,6 +15,7 @@ Required Properties: - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller. - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller. + - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller. - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller. - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller. - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller. -- cgit v1.2.3 From bad12f43d0b164aad2a32b48bdc09d0d9680a213 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Thu, 9 Nov 2017 18:09:30 +0100 Subject: Documentation: Add device tree binding for Goldfish FB driver Add documentation for DT binding of Goldfish FB driver. The compatible string used by OS for binding the driver is "google,goldfish-fb". Signed-off-by: Miodrag Dinic Signed-off-by: Goran Ferenc Signed-off-by: Aleksandar Markovic Acked-by: Rob Herring Cc: David Airlie Cc: Douglas Leung Cc: James Hogan Cc: Mark Rutland Cc: Paul Burton Cc: Petar Jovanovic Cc: Raghu Gandham Signed-off-by: Bartlomiej Zolnierkiewicz --- .../devicetree/bindings/display/google,goldfish-fb.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/google,goldfish-fb.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/google,goldfish-fb.txt b/Documentation/devicetree/bindings/display/google,goldfish-fb.txt new file mode 100644 index 000000000000..751fa9f51e5d --- /dev/null +++ b/Documentation/devicetree/bindings/display/google,goldfish-fb.txt @@ -0,0 +1,17 @@ +Android Goldfish framebuffer + +Android Goldfish framebuffer device used by Android emulator. + +Required properties: + +- compatible : should contain "google,goldfish-fb" +- reg : +- interrupts : + +Example: + + display-controller@1f008000 { + compatible = "google,goldfish-fb"; + interrupts = <0x10>; + reg = <0x1f008000 0x100>; + }; -- cgit v1.2.3 From 48c926cd3414c7e628909f6f831394184816da87 Mon Sep 17 00:00:00 2001 From: Marco Franchi Date: Wed, 8 Nov 2017 14:27:48 -0200 Subject: dt-bindings: Remove leading zeros from bindings notation Improve the binding example by removing all the leading zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"` Some unnecessary changes were manually fixed. Signed-off-by: Marco Franchi Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/samsung/pmu.txt | 2 +- .../devicetree/bindings/arm/samsung/samsung-boards.txt | 2 +- Documentation/devicetree/bindings/arm/sp810.txt | 2 +- .../devicetree/bindings/arm/vexpress-sysreg.txt | 2 +- Documentation/devicetree/bindings/ata/ahci-platform.txt | 2 +- Documentation/devicetree/bindings/ata/imx-sata.txt | 2 +- Documentation/devicetree/bindings/bus/imx-weim.txt | 2 +- Documentation/devicetree/bindings/bus/sunxi-rsb.txt | 2 +- .../devicetree/bindings/clock/arm-syscon-icst.txt | 2 +- .../devicetree/bindings/clock/clk-exynos-audss.txt | 2 +- .../devicetree/bindings/clock/clk-s5pv210-audss.txt | 2 +- .../devicetree/bindings/clock/dove-divider-clock.txt | 2 +- Documentation/devicetree/bindings/clock/imx1-clock.txt | 4 ++-- Documentation/devicetree/bindings/clock/imx6q-clock.txt | 4 ++-- .../devicetree/bindings/clock/maxim,max77686.txt | 4 ++-- Documentation/devicetree/bindings/clock/st/st,clkgen.txt | 2 +- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 4 ++-- Documentation/devicetree/bindings/clock/sunxi.txt | 16 ++++++++-------- Documentation/devicetree/bindings/clock/ti,cdce706.txt | 2 +- Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 2 +- .../devicetree/bindings/display/etnaviv/etnaviv-drm.txt | 2 +- Documentation/devicetree/bindings/display/imx/hdmi.txt | 4 ++-- .../devicetree/bindings/display/simple-framebuffer.txt | 2 +- .../devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 ++-- Documentation/devicetree/bindings/dma/sun4i-dma.txt | 4 ++-- Documentation/devicetree/bindings/dma/sun6i-dma.txt | 2 +- Documentation/devicetree/bindings/dma/ti-edma.txt | 6 +++--- Documentation/devicetree/bindings/dma/zxdma.txt | 2 +- .../bindings/firmware/nvidia,tegra186-bpmp.txt | 2 +- .../devicetree/bindings/gpio/gpio-dsp-keystone.txt | 2 +- .../devicetree/bindings/gpio/gpio-tz1090-pdc.txt | 2 +- Documentation/devicetree/bindings/gpio/gpio-tz1090.txt | 2 +- Documentation/devicetree/bindings/i2c/i2c-axxia.txt | 2 +- Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt | 2 +- .../devicetree/bindings/iio/magnetometer/ak8974.txt | 2 +- .../devicetree/bindings/iio/magnetometer/ak8975.txt | 2 +- .../devicetree/bindings/input/sun4i-lradc-keys.txt | 2 +- .../devicetree/bindings/input/touchscreen/egalax-ts.txt | 2 +- .../devicetree/bindings/input/touchscreen/imx6ul_tsc.txt | 2 +- .../interrupt-controller/allwinner,sunxi-nmi.txt | 2 +- .../bindings/interrupt-controller/ti,keystone-irq.txt | 2 +- Documentation/devicetree/bindings/iommu/qcom,iommu.txt | 2 +- .../devicetree/bindings/leds/register-bit-led.txt | 16 ++++++++-------- .../devicetree/bindings/mailbox/ti,message-manager.txt | 2 +- Documentation/devicetree/bindings/marvell.txt | 4 ++-- Documentation/devicetree/bindings/media/i2c/tc358743.txt | 2 +- Documentation/devicetree/bindings/media/img-ir-rev1.txt | 2 +- Documentation/devicetree/bindings/media/stih-cec.txt | 2 +- .../devicetree/bindings/media/stih407-c8sectpfe.txt | 2 +- Documentation/devicetree/bindings/media/sunxi-ir.txt | 2 +- Documentation/devicetree/bindings/mfd/max77686.txt | 2 +- Documentation/devicetree/bindings/mfd/max77802.txt | 2 +- Documentation/devicetree/bindings/mfd/mfd.txt | 2 +- Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt | 4 ++-- Documentation/devicetree/bindings/mfd/sun6i-prcm.txt | 2 +- Documentation/devicetree/bindings/mfd/syscon.txt | 2 +- Documentation/devicetree/bindings/mmc/mmc.txt | 2 +- Documentation/devicetree/bindings/mmc/sdhci-st.txt | 4 ++-- Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 4 ++-- Documentation/devicetree/bindings/mtd/sunxi-nand.txt | 2 +- .../devicetree/bindings/net/allwinner,sun4i-emac.txt | 2 +- .../devicetree/bindings/net/allwinner,sun4i-mdio.txt | 4 ++-- .../devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt | 2 +- Documentation/devicetree/bindings/net/brcm,bcmgenet.txt | 2 +- Documentation/devicetree/bindings/net/can/m_can.txt | 2 +- Documentation/devicetree/bindings/net/can/sun4i_can.txt | 4 ++-- .../bindings/net/wireless/brcm,bcm43xx-fmac.txt | 2 +- .../devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 4 ++-- Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt | 2 +- Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 2 +- Documentation/devicetree/bindings/nvmem/nvmem.txt | 2 +- Documentation/devicetree/bindings/nvmem/qfprom.txt | 2 +- .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 12 ++++++------ .../devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt | 2 +- Documentation/devicetree/bindings/phy/mxs-usb-phy.txt | 2 +- Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt | 2 +- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +- .../devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | 4 ++-- .../bindings/pinctrl/img,tz1090-pdc-pinctrl.txt | 4 ++-- .../devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt | 4 ++-- .../bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt | 2 +- .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 2 +- Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt | 2 +- .../devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt | 2 +- Documentation/devicetree/bindings/power/fsl,imx-gpc.txt | 4 ++-- .../bindings/power/reset/imx-snvs-poweroff.txt | 2 +- .../devicetree/bindings/power/reset/keystone-reset.txt | 4 ++-- .../devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 2 +- Documentation/devicetree/bindings/pwm/pwm-sun4i.txt | 2 +- Documentation/devicetree/bindings/regulator/max77686.txt | 2 +- Documentation/devicetree/bindings/regulator/max77802.txt | 2 +- .../bindings/reset/allwinner,sunxi-clock-reset.txt | 2 +- Documentation/devicetree/bindings/reset/fsl,imx-src.txt | 6 +++--- .../devicetree/bindings/reset/ti-syscon-reset.txt | 2 +- Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | 2 +- Documentation/devicetree/bindings/rtc/sunxi-rtc.txt | 2 +- .../devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt | 2 +- .../devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt | 2 +- .../devicetree/bindings/soc/ti/sci-pm-domain.txt | 2 +- .../devicetree/bindings/sound/cdns,xtfpga-i2s.txt | 2 +- Documentation/devicetree/bindings/sound/fsl,asrc.txt | 2 +- Documentation/devicetree/bindings/sound/fsl,esai.txt | 2 +- Documentation/devicetree/bindings/sound/fsl,spdif.txt | 2 +- Documentation/devicetree/bindings/sound/imx-audmux.txt | 2 +- Documentation/devicetree/bindings/sound/samsung-i2s.txt | 2 +- Documentation/devicetree/bindings/sound/sun4i-codec.txt | 4 ++-- Documentation/devicetree/bindings/sound/sun4i-i2s.txt | 2 +- .../devicetree/bindings/sound/sun8i-a33-codec.txt | 2 +- .../devicetree/bindings/sound/sun8i-codec-analog.txt | 2 +- .../devicetree/bindings/sound/sunxi,sun4i-spdif.txt | 2 +- Documentation/devicetree/bindings/sound/zte,zx-spdif.txt | 2 +- Documentation/devicetree/bindings/spi/spi-sun4i.txt | 2 +- Documentation/devicetree/bindings/spi/spi-sun6i.txt | 4 ++-- Documentation/devicetree/bindings/sram/samsung-sram.txt | 2 +- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4 ++-- .../bindings/timer/allwinner,sun5i-a13-hstimer.txt | 2 +- .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt | 2 +- Documentation/devicetree/bindings/usb/am33xx-usb.txt | 2 +- Documentation/devicetree/bindings/usb/atmel-usb.txt | 4 ++-- Documentation/devicetree/bindings/usb/ohci-da8xx.txt | 2 +- Documentation/devicetree/bindings/usb/usb-ehci.txt | 2 +- Documentation/devicetree/bindings/usb/usb-ohci.txt | 2 +- Documentation/devicetree/bindings/usb/usb3503.txt | 2 +- Documentation/devicetree/bindings/usb/usbmisc-imx.txt | 2 +- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 +- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 2 +- 126 files changed, 172 insertions(+), 172 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index bf5fc59a6938..088584a98cf4 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt @@ -62,7 +62,7 @@ pmu_system_controller: system-controller@10040000 { Example of clock consumer : -usb3503: usb3503@08 { +usb3503: usb3503@8 { /* ... */ clock-names = "refclk"; clocks = <&pmu_system_controller 0>; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 3c551894f621..fa674818e7e8 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -71,7 +71,7 @@ Optional nodes: - compatible: only "samsung,secure-firmware" is currently supported - reg: address of non-secure SYSRAM used for communication with firmware - firmware@0203F000 { + firmware@203F000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; }; diff --git a/Documentation/devicetree/bindings/arm/sp810.txt b/Documentation/devicetree/bindings/arm/sp810.txt index 6808fb5dee40..1b2ab1ff5587 100644 --- a/Documentation/devicetree/bindings/arm/sp810.txt +++ b/Documentation/devicetree/bindings/arm/sp810.txt @@ -33,7 +33,7 @@ Required properties: property with the highest frequency Example: - v2m_sysctl: sysctl@020000 { + v2m_sysctl: sysctl@20000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt index 00318d083c9e..50095802fb4a 100644 --- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt +++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt @@ -37,7 +37,7 @@ Example: compatible = "arm,vexpress-sysreg"; reg = <0x10000000 0x1000>; - v2m_led_gpios: sys_led@08 { + v2m_led_gpios: sys_led@8 { compatible = "arm,vexpress-sysreg,sys_led"; gpio-controller; #gpio-cells = <2>; diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index fedc213b5f1a..c760ecb81381 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -56,7 +56,7 @@ Examples: interrupts = <115>; }; - ahci: sata@01c18000 { + ahci: sata@1c18000 { compatible = "allwinner,sun4i-a10-ahci"; reg = <0x01c18000 0x1000>; interrupts = <56>; diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt index fa511db18408..a3d14719e478 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.txt +++ b/Documentation/devicetree/bindings/ata/imx-sata.txt @@ -25,7 +25,7 @@ Optional properties: Examples: -sata@02200000 { +sata@2200000 { compatible = "fsl,imx6q-ahci"; reg = <0x02200000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 6630d842c7a3..683eaf3aed79 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -61,7 +61,7 @@ Timing property for child nodes. It is mandatory, not optional. Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: - weim: weim@021b8000 { + weim: weim@21b8000 { compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; clocks = <&clks 196>; diff --git a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt b/Documentation/devicetree/bindings/bus/sunxi-rsb.txt index 3dd28343b6ce..eb3ed628c6f1 100644 --- a/Documentation/devicetree/bindings/bus/sunxi-rsb.txt +++ b/Documentation/devicetree/bindings/bus/sunxi-rsb.txt @@ -28,7 +28,7 @@ which can normally be found in the datasheet. Example: - rsb@01f03400 { + rsb@1f03400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x01f03400 0x400>; interrupts = <0 39 4>; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt index 27468119fd94..4cd81742038f 100644 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt @@ -59,7 +59,7 @@ syscon: syscon@10000000 { compatible = "syscon"; reg = <0x10000000 0x1000>; - oscclk0: osc0@0c { + oscclk0: osc0@c { compatible = "arm,syscon-icst307"; #clock-cells = <0>; lock-offset = <0x20>; diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 0c3d6015868d..2cba012f5af0 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -80,7 +80,7 @@ Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. -i2s0: i2s@03830000 { +i2s0: i2s@3830000 { compatible = "samsung,i2s-v5"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 diff --git a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt b/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt index 4fc869b69d4a..f6272dcd96f4 100644 --- a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt @@ -43,7 +43,7 @@ Example: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. - i2s0: i2s@03830000 { + i2s0: i2s@3830000 { /* ... */ clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt index e3eb0f657c5e..217871f483c0 100644 --- a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt +++ b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt @@ -21,7 +21,7 @@ Required properties: a size of 8. - #clock-cells : from common clock binding; shall be set to 1 -divider_clk: core-clock@0064 { +divider_clk: core-clock@64 { compatible = "marvell,dove-divider-clock"; reg = <0x0064 0x8>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.txt b/Documentation/devicetree/bindings/clock/imx1-clock.txt index b7adf4e3ea98..9823baf7acb6 100644 --- a/Documentation/devicetree/bindings/clock/imx1-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx1-clock.txt @@ -10,13 +10,13 @@ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h for the full list of i.MX1 clock IDs. Examples: - clks: ccm@0021b000 { + clks: ccm@21b000 { #clock-cells = <1>; compatible = "fsl,imx1-ccm"; reg = <0x0021b000 0x1000>; }; - pwm: pwm@00208000 { + pwm: pwm@208000 { #pwm-cells = <2>; compatible = "fsl,imx1-pwm"; reg = <0x00208000 0x1000>; diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index aa0a4d423ef5..a45ca67a9d5f 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -14,14 +14,14 @@ Examples: #include -clks: ccm@020c4000 { +clks: ccm@20c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 0x04 0 88 0x04>; #clock-cells = <1>; }; -uart1: serial@02020000 { +uart1: serial@2020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt index 8398a3a5e106..3472b461ca93 100644 --- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt +++ b/Documentation/devicetree/bindings/clock/maxim,max77686.txt @@ -46,7 +46,7 @@ Example: /* ... */ Node of the MFD chip - max77686: max77686@09 { + max77686: max77686@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; interrupts = <26 0>; @@ -71,7 +71,7 @@ Example: /* ... */ Node of the MFD chip - max77802: max77802@09 { + max77802: max77802@9 { compatible = "maxim,max77802"; interrupt-parent = <&wakeup_eint>; interrupts = <26 0>; diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt index c35390f60545..7364953d0d0b 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt @@ -42,7 +42,7 @@ Required properties: Example: - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 7eda08eb8a1e..4ca21c3a6fc9 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -36,7 +36,7 @@ For the PRCM CCUs on A83T/H3/A64, two more clocks are needed: - "iosc": the SoC's internal frequency oscillator Example for generic CCU: -ccu: clock@01c20000 { +ccu: clock@1c20000 { compatible = "allwinner,sun8i-h3-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; @@ -46,7 +46,7 @@ ccu: clock@01c20000 { }; Example for PRCM CCU: -r_ccu: clock@01f01400 { +r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>; diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 8f7619d8c8d8..1a042e20b115 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -137,7 +137,7 @@ the address block, which is related to the overall mmc block. For example: -osc24M: clk@01c20050 { +osc24M: clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; @@ -145,7 +145,7 @@ osc24M: clk@01c20050 { clock-output-names = "osc24M"; }; -pll1: clk@01c20000 { +pll1: clk@1c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; @@ -153,7 +153,7 @@ pll1: clk@01c20000 { clock-output-names = "pll1"; }; -pll5: clk@01c20020 { +pll5: clk@1c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll5-clk"; reg = <0x01c20020 0x4>; @@ -161,7 +161,7 @@ pll5: clk@01c20020 { clock-output-names = "pll5_ddr", "pll5_other"; }; -pll6: clk@01c20028 { +pll6: clk@1c20028 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-pll6-clk"; reg = <0x01c20028 0x4>; @@ -169,7 +169,7 @@ pll6: clk@01c20028 { clock-output-names = "pll6", "pll6x2"; }; -cpu: cpu@01c20054 { +cpu: cpu@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; @@ -177,7 +177,7 @@ cpu: cpu@01c20054 { clock-output-names = "cpu"; }; -mmc0_clk: clk@01c20088 { +mmc0_clk: clk@1c20088 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20088 0x4>; @@ -199,7 +199,7 @@ gmac_int_tx_clk: clk@3 { clock-output-names = "gmac_int_tx"; }; -gmac_clk: clk@01c20164 { +gmac_clk: clk@1c20164 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-gmac-clk"; reg = <0x01c20164 0x4>; @@ -211,7 +211,7 @@ gmac_clk: clk@01c20164 { clock-output-names = "gmac"; }; -mmc_config_clk: clk@01c13000 { +mmc_config_clk: clk@1c13000 { compatible = "allwinner,sun9i-a80-mmc-config-clk"; reg = <0x01c13000 0x10>; clocks = <&ahb0_gates 8>; diff --git a/Documentation/devicetree/bindings/clock/ti,cdce706.txt b/Documentation/devicetree/bindings/clock/ti,cdce706.txt index 616836e7e1e2..959d96632f5d 100644 --- a/Documentation/devicetree/bindings/clock/ti,cdce706.txt +++ b/Documentation/devicetree/bindings/clock/ti,cdce706.txt @@ -25,7 +25,7 @@ Example: }; }; ... - i2c0: i2c-master@0d090000 { + i2c0: i2c-master@d090000 { ... cdce706: clock-synth@69 { compatible = "ti,cdce706"; diff --git a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt index 5d38e9b7033f..f2dc3d9bca92 100644 --- a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt +++ b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt @@ -14,7 +14,7 @@ Optional properties: - reset-names : must contain "ahb" Example: - crypto: crypto-engine@01c15000 { + crypto: crypto-engine@1c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = ; diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt index ed5e0a7894ad..05176f1ae108 100644 --- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt +++ b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt @@ -42,7 +42,7 @@ Optional properties: example: -gpu_3d: gpu@00130000 { +gpu_3d: gpu@130000 { compatible = "vivante,gc"; reg = <0x00130000 0x4000>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt index 66a8f86e5d12..6d021e71c9cf 100644 --- a/Documentation/devicetree/bindings/display/imx/hdmi.txt +++ b/Documentation/devicetree/bindings/display/imx/hdmi.txt @@ -32,11 +32,11 @@ Optional properties Example: - gpr: iomuxc-gpr@020e0000 { + gpr: iomuxc-gpr@20e0000 { /* ... */ }; - hdmi: hdmi@0120000 { + hdmi: hdmi@120000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-hdmi"; diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer.txt b/Documentation/devicetree/bindings/display/simple-framebuffer.txt index 8c9e9f515c87..5a9ce511be88 100644 --- a/Documentation/devicetree/bindings/display/simple-framebuffer.txt +++ b/Documentation/devicetree/bindings/display/simple-framebuffer.txt @@ -78,7 +78,7 @@ chosen { stdout-path = "display0"; }; -soc@01c00000 { +soc@1c00000 { lcdc0: lcdc@1c0c000 { compatible = "allwinner,sun4i-a10-lcdc"; ... diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 92441086caba..b7faa6f6a326 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -266,7 +266,7 @@ connector { }; }; -hdmi: hdmi@01c16000 { +hdmi: hdmi@1c16000 { compatible = "allwinner,sun5i-a10s-hdmi"; reg = <0x01c16000 0x1000>; interrupts = <58>; @@ -305,7 +305,7 @@ hdmi: hdmi@01c16000 { }; }; -tve0: tv-encoder@01c0a000 { +tve0: tv-encoder@1c0a000 { compatible = "allwinner,sun4i-a10-tv-encoder"; reg = <0x01c0a000 0x1000>; clocks = <&ahb_gates 34>; diff --git a/Documentation/devicetree/bindings/dma/sun4i-dma.txt b/Documentation/devicetree/bindings/dma/sun4i-dma.txt index 3b484380c56a..8ad556aca70b 100644 --- a/Documentation/devicetree/bindings/dma/sun4i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun4i-dma.txt @@ -12,7 +12,7 @@ Required properties: second cell holding the request line number. Example: - dma: dma-controller@01c02000 { + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; interrupts = <27>; @@ -32,7 +32,7 @@ The three cells in order are: 3. The port ID as specified in the datasheet Example: - spi2: spi@01c17000 { + spi2: spi@1c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; interrupts = <0 12 4>; diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt index 98fbe1a5c6dd..717851407fac 100644 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt @@ -38,7 +38,7 @@ The two cells in order are: 2. The port ID as specified in the datasheet Example: -spi2: spi@01c6a000 { +spi2: spi@1c6a000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; interrupts = <0 67 4>; diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 41f0c1a07c56..66026dcf53e1 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -142,7 +142,7 @@ mcasp0: mcasp@48038000 { }; 2. -edma1: edma@02728000 { +edma1: edma@2728000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02728000 0x8000>; reg-names = "edma3_cc"; @@ -165,13 +165,13 @@ edma1: edma@02728000 { power-domains = <&k2g_pds 0x4f>; }; -edma1_tptc0: tptc@027b0000 { +edma1_tptc0: tptc@27b0000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b0000 0x400>; power-domains = <&k2g_pds 0x4f>; }; -edma1_tptc1: tptc@027b8000 { +edma1_tptc1: tptc@27b8000 { compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc"; reg = <0x027b8000 0x400>; power-domains = <&k2g_pds 0x4f>; diff --git a/Documentation/devicetree/bindings/dma/zxdma.txt b/Documentation/devicetree/bindings/dma/zxdma.txt index 3207ceb04d0b..abec59f35fde 100644 --- a/Documentation/devicetree/bindings/dma/zxdma.txt +++ b/Documentation/devicetree/bindings/dma/zxdma.txt @@ -26,7 +26,7 @@ Controller: Client: Use specific request line passing from dmax For example, spdif0 tx channel request line is 4 - spdif0: spdif0@0b004000 { + spdif0: spdif0@b004000 { #sound-dai-cells = <0>; compatible = "zte,zx296702-spdif"; reg = <0x0b004000 0x1000>; diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt index e821e16ad65b..0c10802c8327 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -66,7 +66,7 @@ See ".../sram/sram.txt" for the bindings. Example: -hsp_top0: hsp@03c00000 { +hsp_top0: hsp@3c00000 { ... #mbox-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt index 6c7e6c7302f5..0423699d74c7 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt @@ -25,7 +25,7 @@ Please refer to gpio.txt in this directory for details of the common GPIO bindings used by client devices. Example: - dspgpio0: keystone_dsp_gpio@02620240 { + dspgpio0: keystone_dsp_gpio@2620240 { compatible = "ti,keystone-dsp-gpio"; ti,syscon-dev = <&devctrl 0x240>; gpio-controller; diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt index 1fd98ffa8cb7..528f5ef5a893 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt @@ -30,7 +30,7 @@ Optional properties: Example: - pdc_gpios: gpio-controller@02006500 { + pdc_gpios: gpio-controller@2006500 { gpio-controller; #gpio-cells = <2>; diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt index 174cdf309170..b05a90e0ab29 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt @@ -59,7 +59,7 @@ Required properties: Example: - gpios: gpio-controller@02005800 { + gpios: gpio-controller@2005800 { #address-cells = <1>; #size-cells = <0>; compatible = "img,tz1090-gpio"; diff --git a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt b/Documentation/devicetree/bindings/i2c/i2c-axxia.txt index 2296d782b4c2..7d53a2b79553 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-axxia.txt @@ -17,7 +17,7 @@ Optional properties : Example : -i2c@02010084000 { +i2c@2010084000 { compatible = "lsi,api2c"; device_type = "i2c"; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt b/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt index 6b765485af7d..49df0053347a 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi-p2wi.txt @@ -24,7 +24,7 @@ Slave device properties: Example: - p2wi@01f03400 { + p2wi@1f03400 { compatible = "allwinner,sun6i-a31-p2wi"; reg = <0x01f03400 0x400>; interrupts = <0 39 4>; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt index 77d5aba1bd8c..baecc4a85197 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt +++ b/Documentation/devicetree/bindings/iio/magnetometer/ak8974.txt @@ -19,7 +19,7 @@ Optional properties: Example: -ak8974@0f { +ak8974@f { compatible = "asahi-kasei,ak8974"; reg = <0x0f>; avdd-supply = <&foo_reg>; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt index e1e7dd3259f6..aa67ceb0d4e0 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt +++ b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt @@ -13,7 +13,7 @@ Optional properties: Example: -ak8975@0c { +ak8975@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; gpios = <&gpj0 7 0>; diff --git a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt index 4357e498ef04..1458c3179a63 100644 --- a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt +++ b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt @@ -19,7 +19,7 @@ Example: #include - lradc: lradc@01c22800 { + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x100>; interrupts = <31>; diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt index 49fa14ed155c..298e3442f143 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt @@ -10,7 +10,7 @@ Required properties: Example: - egalax_ts@04 { + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; diff --git a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt index e67e58b61706..164915004424 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt @@ -21,7 +21,7 @@ Optional properties: each read. Valid values are 1, 4, 8, 16 and 32. Example: - tsc: tsc@02040000 { + tsc: tsc@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = , diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt index 4ae553eb333d..4903fb72d883 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt @@ -20,7 +20,7 @@ Required properties: Example: -sc-nmi-intc@01c00030 { +sc-nmi-intc@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; #interrupt-cells = <2>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt index d9bb106bdd16..5f94d7739d8d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt @@ -20,7 +20,7 @@ Please refer to interrupts.txt in this directory for details of the common Interrupt Controllers bindings used by client devices. Example: - kirq0: keystone_irq0@026202a0 { + kirq0: keystone_irq0@26202a0 { compatible = "ti,keystone-irq"; ti,syscon-dev = <&devctrl 0x2a0>; interrupts = ; diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index b2641ceb2b40..059139abce35 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -115,7 +115,7 @@ to non-secure vs secure interrupt line. iommus = <&apps_iommu 4>; }; - gpu@01c00000 { + gpu@1c00000 { ... iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; }; diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.txt b/Documentation/devicetree/bindings/leds/register-bit-led.txt index 59b56365f648..cf1ea403ba7a 100644 --- a/Documentation/devicetree/bindings/leds/register-bit-led.txt +++ b/Documentation/devicetree/bindings/leds/register-bit-led.txt @@ -32,7 +32,7 @@ syscon: syscon@10000000 { compatible = "arm,realview-pb1176-syscon", "syscon"; reg = <0x10000000 0x1000>; - led@08.0 { + led@8.0 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x01>; @@ -40,7 +40,7 @@ syscon: syscon@10000000 { linux,default-trigger = "heartbeat"; default-state = "on"; }; - led@08.1 { + led@8.1 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x02>; @@ -48,7 +48,7 @@ syscon: syscon@10000000 { linux,default-trigger = "mmc0"; default-state = "off"; }; - led@08.2 { + led@8.2 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x04>; @@ -56,35 +56,35 @@ syscon: syscon@10000000 { linux,default-trigger = "cpu0"; default-state = "off"; }; - led@08.3 { + led@8.3 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x08>; label = "versatile:3"; default-state = "off"; }; - led@08.4 { + led@8.4 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x10>; label = "versatile:4"; default-state = "off"; }; - led@08.5 { + led@8.5 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x20>; label = "versatile:5"; default-state = "off"; }; - led@08.6 { + led@8.6 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x40>; label = "versatile:6"; default-state = "off"; }; - led@08.7 { + led@8.7 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x80>; diff --git a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt b/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt index b449d025049f..c3b55b3ede8a 100644 --- a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt +++ b/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt @@ -29,7 +29,7 @@ Required properties: Example(K2G): ------------ - msgmgr: msgmgr@02a00000 { + msgmgr: msgmgr@2a00000 { compatible = "ti,k2g-message-manager"; #mbox-cells = <2>; reg-names = "queue_proxy_region", "queue_state_debug_region"; diff --git a/Documentation/devicetree/bindings/marvell.txt b/Documentation/devicetree/bindings/marvell.txt index ea2b16ced49b..7f722316458a 100644 --- a/Documentation/devicetree/bindings/marvell.txt +++ b/Documentation/devicetree/bindings/marvell.txt @@ -446,7 +446,7 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd. that services interrupts for this device. Example Discovery CPU Error node: - cpu-error@0070 { + cpu-error@70 { compatible = "marvell,mv64360-cpu-error"; reg = <0x70 0x10 0x128 0x28>; interrupts = <3>; @@ -466,7 +466,7 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd. that services interrupts for this device. Example Discovery SRAM Controller node: - sram-ctrl@0380 { + sram-ctrl@380 { compatible = "marvell,mv64360-sram-ctrl"; reg = <0x380 0x80>; interrupts = <13>; diff --git a/Documentation/devicetree/bindings/media/i2c/tc358743.txt b/Documentation/devicetree/bindings/media/i2c/tc358743.txt index 5218921629ed..49f8bcc2ea4d 100644 --- a/Documentation/devicetree/bindings/media/i2c/tc358743.txt +++ b/Documentation/devicetree/bindings/media/i2c/tc358743.txt @@ -27,7 +27,7 @@ Documentation/devicetree/bindings/media/video-interfaces.txt. Example: - tc358743@0f { + tc358743@f { compatible = "toshiba,tc358743"; reg = <0x0f>; clocks = <&hdmi_osc>; diff --git a/Documentation/devicetree/bindings/media/img-ir-rev1.txt b/Documentation/devicetree/bindings/media/img-ir-rev1.txt index 5434ce61b925..ed9ec52b77e0 100644 --- a/Documentation/devicetree/bindings/media/img-ir-rev1.txt +++ b/Documentation/devicetree/bindings/media/img-ir-rev1.txt @@ -25,7 +25,7 @@ Optional properties: Example: - ir@02006200 { + ir@2006200 { compatible = "img,ir-rev1"; reg = <0x02006200 0x100>; interrupts = <29 4>; diff --git a/Documentation/devicetree/bindings/media/stih-cec.txt b/Documentation/devicetree/bindings/media/stih-cec.txt index 8be2a040c6c6..ece0832fdeaf 100644 --- a/Documentation/devicetree/bindings/media/stih-cec.txt +++ b/Documentation/devicetree/bindings/media/stih-cec.txt @@ -13,7 +13,7 @@ Required properties: Example for STIH407: -sti-cec@094a087c { +sti-cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; clocks = <&clk_sysin>; diff --git a/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt b/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt index 6af3fc210ecc..c7888d6f6408 100644 --- a/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt +++ b/Documentation/devicetree/bindings/media/stih407-c8sectpfe.txt @@ -50,7 +50,7 @@ Example: /* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */ - c8sectpfe@08a20000 { + c8sectpfe@8a20000 { compatible = "st,stih407-c8sectpfe"; reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>; reg-names = "stfe", "stfe-ram"; diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt index 302a0b183cb8..91648c569b1e 100644 --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt @@ -14,7 +14,7 @@ Optional properties: Example: -ir0: ir@01c21800 { +ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt index 741e76688cf2..0f2587fa42cb 100644 --- a/Documentation/devicetree/bindings/mfd/max77686.txt +++ b/Documentation/devicetree/bindings/mfd/max77686.txt @@ -19,7 +19,7 @@ Required properties: Example: - max77686: pmic@09 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; interrupts = <26 0>; diff --git a/Documentation/devicetree/bindings/mfd/max77802.txt b/Documentation/devicetree/bindings/mfd/max77802.txt index 51fc1a60caa5..f2f3fe75901c 100644 --- a/Documentation/devicetree/bindings/mfd/max77802.txt +++ b/Documentation/devicetree/bindings/mfd/max77802.txt @@ -18,7 +18,7 @@ Required properties: Example: - max77802: pmic@09 { + max77802: pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&intc>; interrupts = <26 IRQ_TYPE_NONE>; diff --git a/Documentation/devicetree/bindings/mfd/mfd.txt b/Documentation/devicetree/bindings/mfd/mfd.txt index bcb6abb9d413..336c0495c8a3 100644 --- a/Documentation/devicetree/bindings/mfd/mfd.txt +++ b/Documentation/devicetree/bindings/mfd/mfd.txt @@ -41,7 +41,7 @@ foo@1000 { compatible = "syscon", "simple-mfd"; reg = <0x01000 0x1000>; - led@08.0 { + led@8.0 { compatible = "register-bit-led"; offset = <0x08>; mask = <0x01>; diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt index badff3611a98..86dd8191b04c 100644 --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt @@ -10,7 +10,7 @@ Required properties: - #io-channel-cells: shall be 0, Example: - ths: ths@01c25000 { + ths: ths@1c25000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; #thermal-sensor-cells = <0>; @@ -47,7 +47,7 @@ Optional properties: Example: - rtp: rtp@01c25000 { + rtp: rtp@1c25000 { compatible = "allwinner,sun4i-a10-ts"; reg = <0x01c25000 0x100>; interrupts = <29>; diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt index 03c5a551da55..dd2c06540485 100644 --- a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt +++ b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt @@ -15,7 +15,7 @@ The prcm node may contain several subdevices definitions: Example: - prcm: prcm@01f01400 { + prcm: prcm@1f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt index 408f768686f1..8b92d4576c42 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ b/Documentation/devicetree/bindings/mfd/syscon.txt @@ -18,7 +18,7 @@ Optional property: performed on the device. Examples: -gpr: iomuxc-gpr@020e0000 { +gpr: iomuxc-gpr@20e0000 { compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e0000 0x38>; }; diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index b32ade645ad9..5934157cf2cd 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -143,7 +143,7 @@ sdhci@ab000000 { Example with sdio function subnode: -mmc3: mmc@01c12000 { +mmc3: mmc@1c12000 { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt index e35645598315..6b3d40ca395e 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-st.txt @@ -74,7 +74,7 @@ mmc0: sdhci@fe81e000 { /* Example SD stih407 family configuration */ -mmc1: sdhci@09080000 { +mmc1: sdhci@9080000 { compatible = "st,sdhci-stih407", "st,sdhci"; reg = <0x09080000 0x7ff>; reg-names = "mmc"; @@ -90,7 +90,7 @@ mmc1: sdhci@09080000 { /* Example eMMC stih407 family configuration */ -mmc0: sdhci@09060000 { +mmc0: sdhci@9060000 { compatible = "st,sdhci-stih407", "st,sdhci"; reg = <0x09060000 0x7ff>, <0x9061008 0x20>; reg-names = "mmc", "top-mmc-delay"; diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt index 63b57e2a10fb..132e0007d7d6 100644 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt @@ -29,7 +29,7 @@ Optional properties: Examples: - Within .dtsi: - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>; @@ -39,7 +39,7 @@ Examples: }; - Within dts: - mmc0: mmc@01c0f000 { + mmc0: mmc@1c0f000 { pinctrl-names = "default", "default"; pinctrl-0 = <&mmc0_pins_a>; pinctrl-1 = <&mmc0_cd_pin_reference_design>; diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt index a37c67bcb43b..5e13a5cdff03 100644 --- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt @@ -31,7 +31,7 @@ see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. Examples: -nfc: nand@01c03000 { +nfc: nand@1c03000 { compatible = "allwinner,sun4i-a10-nand"; reg = <0x01c03000 0x1000>; interrupts = <0 37 1>; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt index 10640b17c866..e98118aef5f6 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt +++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt @@ -10,7 +10,7 @@ Required properties: Example: -emac: ethernet@01c0b000 { +emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt index 4ec56413779d..ab5b8613b0ef 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt +++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt @@ -9,7 +9,7 @@ Optional properties: - phy-supply: phandle to a regulator if the PHY needs one Example at the SoC level: -mdio@01c0b080 { +mdio@1c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x01c0b080 0x14>; #address-cells = <1>; @@ -18,7 +18,7 @@ mdio@01c0b080 { And at the board level: -mdio@01c0b080 { +mdio@1c0b080 { phy-supply = <®_emac_3v3>; phy0: ethernet-phy@0 { diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt index ea4d752389a2..8b3f953656e3 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt +++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt @@ -15,7 +15,7 @@ Optional properties: Examples: - gmac: ethernet@01c50000 { + gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; reg = <0x01c50000 0x10000>, <0x01c20164 0x4>; diff --git a/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt b/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt index 26c77d985faf..3956af1d30f3 100644 --- a/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt +++ b/Documentation/devicetree/bindings/net/brcm,bcmgenet.txt @@ -109,7 +109,7 @@ ethernet@f0ba0000 { reg = <0xf0ba0000 0xfc4c>; interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>; - mdio@0e14 { + mdio@e14 { compatible = "brcm,genet-mdio-v4"; #address-cells = <0x1>; #size-cells = <0x0>; diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt index 78138333ff7a..63e90421d029 100644 --- a/Documentation/devicetree/bindings/net/can/m_can.txt +++ b/Documentation/devicetree/bindings/net/can/m_can.txt @@ -45,7 +45,7 @@ Required properties: Example: SoC dtsi: -m_can1: can@020e8000 { +m_can1: can@20e8000 { compatible = "bosch,m_can"; reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; reg-names = "m_can", "message_ram"; diff --git a/Documentation/devicetree/bindings/net/can/sun4i_can.txt b/Documentation/devicetree/bindings/net/can/sun4i_can.txt index 84ed1909df76..f69845e6feaf 100644 --- a/Documentation/devicetree/bindings/net/can/sun4i_can.txt +++ b/Documentation/devicetree/bindings/net/can/sun4i_can.txt @@ -19,7 +19,7 @@ SoC common .dtsi file: allwinner,pull = <0>; }; ... - can0: can@01c2bc00 { + can0: can@1c2bc00 { compatible = "allwinner,sun4i-a10-can"; reg = <0x01c2bc00 0x400>; interrupts = <0 26 4>; @@ -29,7 +29,7 @@ SoC common .dtsi file: Board specific .dts file: - can0: can@01c2bc00 { + can0: can@1c2bc00 { pinctrl-names = "default"; pinctrl-0 = <&can0_pins_a>; status = "okay"; diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt index b2bd4704f859..86602f264dce 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt @@ -20,7 +20,7 @@ Optional properties: Example: -mmc3: mmc@01c12000 { +mmc3: mmc@1c12000 { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt index ef06d061913c..081c49c0dac0 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt @@ -13,13 +13,13 @@ Are child nodes of qfprom, bindings of which as described in bindings/nvmem/nvmem.txt Example for sun4i: - sid@01c23800 { + sid@1c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10> }; Example for sun7i: - sid@01c23800 { + sid@1c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200> }; diff --git a/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt b/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt index 6462e12d8de6..0415265c215a 100644 --- a/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/brcm,ocotp.txt @@ -10,7 +10,7 @@ Required Properties: Example: -otp: otp@0301c800 { +otp: otp@301c800 { compatible = "brcm,ocotp"; reg = <0x0301c800 0x2c>; brcm,ocotp-size = <2048>; diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index 70d791b03ea1..f162c72b4e36 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -19,7 +19,7 @@ Optional properties: Example: - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6QDL_CLK_IIM>; diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.txt b/Documentation/devicetree/bindings/nvmem/nvmem.txt index b52bc11e9597..fd06c09b822b 100644 --- a/Documentation/devicetree/bindings/nvmem/nvmem.txt +++ b/Documentation/devicetree/bindings/nvmem/nvmem.txt @@ -33,7 +33,7 @@ bits: Is pair of bit location and number of bits, which specifies offset For example: /* Provider */ - qfprom: qfprom@00700000 { + qfprom: qfprom@700000 { ... /* Data cells */ diff --git a/Documentation/devicetree/bindings/nvmem/qfprom.txt b/Documentation/devicetree/bindings/nvmem/qfprom.txt index 4ad68b7f5c18..26fe878d5c86 100644 --- a/Documentation/devicetree/bindings/nvmem/qfprom.txt +++ b/Documentation/devicetree/bindings/nvmem/qfprom.txt @@ -12,7 +12,7 @@ bindings/nvmem/nvmem.txt Example: - qfprom: qfprom@00700000 { + qfprom: qfprom@700000 { compatible = "qcom,qfprom"; reg = <0x00700000 0x8000>; ... diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 982a74ea6df9..1b4d2803dad1 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -255,7 +255,7 @@ Tegra30: SoC DTSI: - pcie-controller@00003000 { + pcie-controller@3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; reg = <0x00003000 0x00000800 /* PADS registers */ @@ -334,7 +334,7 @@ SoC DTSI: Board DTS: - pcie-controller@00003000 { + pcie-controller@3000 { status = "okay"; avdd-pexa-supply = <&ldo1_reg>; @@ -360,7 +360,7 @@ Tegra124: SoC DTSI: - pcie-controller@01003000 { + pcie-controller@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ @@ -425,7 +425,7 @@ SoC DTSI: Board DTS: - pcie-controller@01003000 { + pcie-controller@1003000 { status = "okay"; avddio-pex-supply = <&vdd_1v05_run>; @@ -456,7 +456,7 @@ Tegra210: SoC DTSI: - pcie-controller@01003000 { + pcie-controller@1003000 { compatible = "nvidia,tegra210-pcie"; device_type = "pci"; reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ @@ -521,7 +521,7 @@ SoC DTSI: Board DTS: - pcie-controller@01003000 { + pcie-controller@1003000 { status = "okay"; avdd-pll-uerefe-supply = <&avdd_1v05_pll>; diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt index 761c4bc24a9b..10efff28b52b 100644 --- a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt @@ -15,7 +15,7 @@ Required properties For the child node: - #phy-cells: must be 0 Example: - pcie_phy: phy@0301d0a0 { + pcie_phy: phy@301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index 1d25b04cd05e..6ac98b3b5f57 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -23,7 +23,7 @@ Optional properties: the 17.78mA TX reference current. Default: 100 Example: -usbphy1: usbphy@020c9000 { +usbphy1: usbphy@20c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; diff --git a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt index f9853156e311..64f7109aea1f 100644 --- a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt @@ -25,7 +25,7 @@ It is recommended to list all clocks and resets available. The driver will only use those matching the phy_type. Example: - usbphy1: phy@00a01800 { + usbphy1: phy@a01800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a01800 0x4>; clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 6f2ec9af0de2..09789fdfa749 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -89,7 +89,7 @@ Optional subnode-properties: Examples: -pio: pinctrl@01c20800 { +pio: pinctrl@1c20800 { compatible = "allwinner,sun5i-a13-pinctrl"; reg = <0x01c20800 0x400>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt index 42d74f8a1bcc..a1050b5982ec 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt @@ -58,14 +58,14 @@ Some requirements for using fsl,imx-pinctrl binding: configurations by referring to the phandle of that pin configuration node. Examples: -usdhc@0219c000 { /* uSDHC4 */ +usdhc@219c000 { /* uSDHC4 */ non-removable; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4_1>; }; -iomuxc@020e0000 { +iomuxc@20e0000 { compatible = "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt index 51b943cc9770..cf9ccdff4455 100644 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt @@ -89,7 +89,7 @@ Valid values for pin and group names are: Example: - pinctrl_pdc: pinctrl@02006500 { + pinctrl_pdc: pinctrl@2006500 { #gpio-range-cells = <3>; compatible = "img,tz1090-pdc-pinctrl"; reg = <0x02006500 0x100>; @@ -121,7 +121,7 @@ Example board file extracts: }; }; - ir: ir@02006200 { + ir: ir@2006200 { pinctrl-names = "default"; pinctrl-0 = <&irmod_default>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt index 509faa87ad0e..2dfd9a3fc1e4 100644 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt @@ -197,7 +197,7 @@ Valid values for pin and group names are: Example: - pinctrl: pinctrl@02005800 { + pinctrl: pinctrl@2005800 { #gpio-range-cells = <3>; compatible = "img,tz1090-pinctrl"; reg = <0x02005800 0xe4>; @@ -221,7 +221,7 @@ Example board file extract: }; }; - uart@02004b00 { + uart@2004b00 { pinctrl-names = "default"; pinctrl-0 = <&uart0_default>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt index 4048f43a9d29..02e971c39d81 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt @@ -97,7 +97,7 @@ SoC file extract: Board file extract: ------------------- - pcie-controller@01003000 { + pcie-controller@1003000 { ... phys = <&padctl 0>; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 37d744750579..231fa1db7c5e 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -86,7 +86,7 @@ Examples: reg = <0 0x1020C020 0 0x1000>; }; - pinctrl@01c20800 { + pinctrl@1c20800 { compatible = "mediatek,mt8135-pinctrl"; reg = <0 0x1000B000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt index 013c675b5b64..48b9be48af18 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt @@ -89,7 +89,7 @@ Example: interrupt-names = "irqmux"; ranges = <0 0x09610000 0x6000>; - pio0: gpio@09610000 { + pio0: gpio@9610000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt index e312a71b2f94..aaf01e929eea 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt @@ -175,7 +175,7 @@ to specify in a pin configuration subnode: Example: - tlmm: pinctrl@01010000 { + tlmm: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; interrupts = <0 208 0>; diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt index 6c1498958d48..e371b262d709 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt @@ -40,7 +40,7 @@ Optional properties: Example: - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, @@ -80,7 +80,7 @@ that is a phandle pointing to the power domain the device belongs to. Example of a device that is part of the PU power domain: - vpu: vpu@02040000 { + vpu: vpu@2040000 { reg = <0x02040000 0x3c000>; /* ... */ power-domains = <&pd_pu>; diff --git a/Documentation/devicetree/bindings/power/reset/imx-snvs-poweroff.txt b/Documentation/devicetree/bindings/power/reset/imx-snvs-poweroff.txt index dc7c9bad63ea..1b81fcd9fb72 100644 --- a/Documentation/devicetree/bindings/power/reset/imx-snvs-poweroff.txt +++ b/Documentation/devicetree/bindings/power/reset/imx-snvs-poweroff.txt @@ -10,7 +10,7 @@ Required Properties: -reg: Specifies the physical address of the SNVS_LPCR register Example: - snvs@020cc000 { + snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt index c82f12e2d85c..c5c03789ed1e 100644 --- a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt @@ -37,12 +37,12 @@ Example 1: Setup keystone reset so that in case software reset or WDT0 is triggered it issues hard reset for SoC. -pllctrl: pll-controller@02310000 { +pllctrl: pll-controller@2310000 { compatible = "ti,keystone-pllctrl", "syscon"; reg = <0x02310000 0x200>; }; -devctrl: device-state-control@02620000 { +devctrl: device-state-control@2620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt index 0f766333b6eb..37f91fa57654 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/mcu-mpc8349emitx.txt @@ -8,7 +8,7 @@ Required properties: Example: -mcu@0a { +mcu@a { #gpio-cells = <2>; compatible = "fsl,mc9s08qg8-mpc8349emitx", "fsl,mcu-mpc8349emitx"; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt index c5171660eaf9..51ff54c8b8ef 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt @@ -14,7 +14,7 @@ Required properties: Example: - pwm: pwm@01c20e00 { + pwm: pwm@1c20e00 { compatible = "allwinner,sun7i-a20-pwm"; reg = <0x01c20e00 0xc>; clocks = <&osc24M>; diff --git a/Documentation/devicetree/bindings/regulator/max77686.txt b/Documentation/devicetree/bindings/regulator/max77686.txt index 0dded64d89d3..e9f7578ca09a 100644 --- a/Documentation/devicetree/bindings/regulator/max77686.txt +++ b/Documentation/devicetree/bindings/regulator/max77686.txt @@ -40,7 +40,7 @@ to get matched with their hardware counterparts as follow: Example: - max77686: pmic@09 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; interrupts = <26 IRQ_TYPE_NONE>; diff --git a/Documentation/devicetree/bindings/regulator/max77802.txt b/Documentation/devicetree/bindings/regulator/max77802.txt index 879e98d3b9aa..b82943d83677 100644 --- a/Documentation/devicetree/bindings/regulator/max77802.txt +++ b/Documentation/devicetree/bindings/regulator/max77802.txt @@ -71,7 +71,7 @@ has not been disabled for that state using "regulator-off-in-suspend". Example: - max77802@09 { + max77802@9 { compatible = "maxim,max77802"; interrupt-parent = <&wakeup_eint>; interrupts = <26 0>; diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt index c8f775714887..4ca66c96fe97 100644 --- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt +++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt @@ -14,7 +14,7 @@ Required properties: example: -ahb1_rst: reset@01c202c0 { +ahb1_rst: reset@1c202c0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-ahb1-reset"; reg = <0x01c202c0 0xc>; diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt index 13301777e11c..6ed79e60248a 100644 --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt @@ -14,7 +14,7 @@ Required properties: example: -src: src@020d8000 { +src: src@20d8000 { compatible = "fsl,imx6q-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 0x04 0 96 0x04>; @@ -33,10 +33,10 @@ reset.txt example: - ipu1: ipu@02400000 { + ipu1: ipu@2400000 { resets = <&src 2>; }; - ipu2: ipu@02800000 { + ipu2: ipu@2800000 { resets = <&src 4>; }; diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt index c516d24959f2..86945502ccb5 100644 --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt @@ -67,7 +67,7 @@ using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 / { soc { - psc: power-sleep-controller@02350000 { + psc: power-sleep-controller@2350000 { compatible = "syscon", "simple-mfd"; reg = <0x02350000 0x1000>; diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt index d5e26d313f62..12c083c1140a 100644 --- a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt @@ -17,7 +17,7 @@ Required properties for new device trees Example: -rtc: rtc@01f00000 { +rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <0 40 4>, <0 41 4>; diff --git a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt index 6983aad376c3..4a8d79c1cf08 100644 --- a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt @@ -10,7 +10,7 @@ Required properties: Example: -rtc: rtc@01c20d00 { +rtc: rtc@1c20d00 { compatible = "allwinner,sun4i-a10-rtc"; reg = <0x01c20d00 0x20>; interrupts = <24>; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 60984260207b..09b1b05fa677 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt @@ -18,7 +18,7 @@ par_io@1400 { #size-cells = <0>; device_type = "par_io"; num-ports = <7>; - ucc_pin@01 { + ucc_pin@1 { ...... }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt index ec6ee2e864a2..5bde8b98a8c9 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt @@ -26,7 +26,7 @@ Required properties: interrupts. Example: - ucc_pin@01 { + ucc_pin@1 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0 3 1 0 1 0 /* TxD0 */ diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt index 66e6265fb0aa..f7b00a7c0f68 100644 --- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt +++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt @@ -51,7 +51,7 @@ of valid identifiers for k2g. Example (K2G): -------------------- - uart0: serial@02530c00 { + uart0: serial@2530c00 { compatible = "ns16550a"; ... power-domains = <&k2g_pds 0x002c>; diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt index befd125d18bb..860fc0da39c0 100644 --- a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt +++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt @@ -9,7 +9,7 @@ Required properties: Examples: - i2s0: xtfpga-i2s@0d080000 { + i2s0: xtfpga-i2s@d080000 { #sound-dai-cells = <0>; compatible = "cdns,xtfpga-i2s"; reg = <0x0d080000 0x40>; diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index 65979b205893..f5a14115b459 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -41,7 +41,7 @@ Required properties: Example: -asrc: asrc@02034000 { +asrc: asrc@2034000 { compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index 21c401e2ccda..cacd18bb9ba6 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt @@ -48,7 +48,7 @@ Required properties: Example: -esai: esai@02024000 { +esai: esai@2024000 { compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = <0 51 0x04>; diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index 0f97e54c3d43..38cfa7573441 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -39,7 +39,7 @@ Required properties: Example: -spdif: spdif@02004000 { +spdif: spdif@2004000 { compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 0x04>; diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt index b30a737e209e..2db4dcbee1b9 100644 --- a/Documentation/devicetree/bindings/sound/imx-audmux.txt +++ b/Documentation/devicetree/bindings/sound/imx-audmux.txt @@ -22,7 +22,7 @@ Required properties of optional child nodes: Example: -audmux@021d8000 { +audmux@21d8000 { compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; }; diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index 09e0e18591ae..bf100cd0d0f7 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt @@ -63,7 +63,7 @@ Optional SoC Specific Properties: Example: -i2s0: i2s@03830000 { +i2s0: i2s@3830000 { compatible = "samsung,s5pv210-i2s"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt index 2d4e10deb6f4..66579bbd3294 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt @@ -62,7 +62,7 @@ Required properties for the following compatibles: block in the PRCM. Example: -codec: codec@01c22c00 { +codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun7i-a20-codec"; reg = <0x01c22c00 0x40>; @@ -73,7 +73,7 @@ codec: codec@01c22c00 { dma-names = "rx", "tx"; }; -codec: codec@01c22c00 { +codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun6i-a31-codec"; reg = <0x01c22c00 0x98>; diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt index fc5da6080759..05d7135a8d2f 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt @@ -28,7 +28,7 @@ Required properties for the following compatibles: Example: -i2s0: i2s@01c22400 { +i2s0: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun4i-a10-i2s"; reg = <0x01c22400 0x400>; diff --git a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt index 399b1b4bae22..2ca3d138528e 100644 --- a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt +++ b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt @@ -48,7 +48,7 @@ are similar to A33 using simple-card: sound-dai = <&codec>; }; - soc@01c00000 { + soc@1c00000 { [...] audio-codec@1c22e00 { diff --git a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt index 1b6e7c4e50ab..07356758bd91 100644 --- a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt +++ b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt @@ -10,7 +10,7 @@ Required properties if not a sub-node of the PRCM node: - reg: must contain the registers location and length Example: -prcm: prcm@01f01400 { +prcm: prcm@1f01400 { codec_analog: codec-analog { compatible = "allwinner,sun8i-a23-codec-analog"; }; diff --git a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt index 70ee177901d3..0c64a209c2e9 100644 --- a/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt +++ b/Documentation/devicetree/bindings/sound/sunxi,sun4i-spdif.txt @@ -31,7 +31,7 @@ Required properties: Example: -spdif: spdif@01c21000 { +spdif: spdif@1c21000 { compatible = "allwinner,sun4i-a10-spdif"; reg = <0x01c21000 0x40>; interrupts = <13>; diff --git a/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt b/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt index b5a5ca4502f9..09231d7586b2 100644 --- a/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt +++ b/Documentation/devicetree/bindings/sound/zte,zx-spdif.txt @@ -16,7 +16,7 @@ please check: * dma/dma.txt Example: - spdif0: spdif0@0b004000 { + spdif0: spdif0@b004000 { compatible = "zte,zx296702-spdif"; reg = <0x0b004000 0x1000>; clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; diff --git a/Documentation/devicetree/bindings/spi/spi-sun4i.txt b/Documentation/devicetree/bindings/spi/spi-sun4i.txt index 484bbff5337e..c75d604a8290 100644 --- a/Documentation/devicetree/bindings/spi/spi-sun4i.txt +++ b/Documentation/devicetree/bindings/spi/spi-sun4i.txt @@ -12,7 +12,7 @@ Required properties: Example: -spi1: spi@01c06000 { +spi1: spi@1c06000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c06000 0x1000>; interrupts = <11>; diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt index ab1811354cce..435a8e0731ac 100644 --- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt +++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt @@ -19,7 +19,7 @@ Optional properties: Example: -spi1: spi@01c69000 { +spi1: spi@1c69000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; interrupts = <0 66 4>; @@ -28,7 +28,7 @@ spi1: spi@01c69000 { resets = <&ahb1_rst 21>; }; -spi0: spi@01c68000 { +spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; interrupts = ; diff --git a/Documentation/devicetree/bindings/sram/samsung-sram.txt b/Documentation/devicetree/bindings/sram/samsung-sram.txt index 6bc474b2b885..61a9bbed303d 100644 --- a/Documentation/devicetree/bindings/sram/samsung-sram.txt +++ b/Documentation/devicetree/bindings/sram/samsung-sram.txt @@ -19,7 +19,7 @@ found in Documentation/devicetree/bindings/sram/sram.txt Example: - sysram@02020000 { + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index 6bb92a1df753..d087f04a4d7f 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -47,7 +47,7 @@ This valid values for this argument are: Example ------- -sram-controller@01c00000 { +sram-controller@1c00000 { compatible = "allwinner,sun4i-a10-sram-controller"; reg = <0x01c00000 0x30>; #address-cells = <1>; @@ -68,7 +68,7 @@ sram-controller@01c00000 { }; }; -emac: ethernet@01c0b000 { +emac: ethernet@1c0b000 { compatible = "allwinner,sun4i-a10-emac"; ... diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt index 8d6e4fd2468e..2c5c1be78360 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt @@ -14,7 +14,7 @@ Optional properties: Example: -timer@01c60000 { +timer@1c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = <0 51 1>, diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt index cb2bd83fa89a..50abb20fe319 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt @@ -16,7 +16,7 @@ Required properties: Example: - usb_otg: usb@01c13000 { + usb_otg: usb@1c13000 { compatible = "allwinner,sun4i-a10-musb"; reg = <0x01c13000 0x0400>; clocks = <&ahb_gates 0>; diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt index 16920d78e1b8..7a33f22c815a 100644 --- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt @@ -181,7 +181,7 @@ usb: usb@47400000 { "tx14", "tx15"; }; - cppi41dma: dma-controller@07402000 { + cppi41dma: dma-controller@7402000 { compatible = "ti,am3359-cppi41"; reg = <0x47400000 0x1000 0x47402000 0x1000 diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index ad8ea56a9ed3..44e80153b148 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -18,7 +18,7 @@ Required properties: - atmel,oc-gpio: If present, specifies a gpio that needs to be activated for the overcurrent detection. -usb0: ohci@00500000 { +usb0: ohci@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; @@ -39,7 +39,7 @@ Required properties: "ehci_clk" for the peripheral clock "usb_clk" for the UTMI clock -usb1: ehci@00800000 { +usb1: ehci@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 4>; diff --git a/Documentation/devicetree/bindings/usb/ohci-da8xx.txt b/Documentation/devicetree/bindings/usb/ohci-da8xx.txt index 2dc8f67eda39..24a826d5015e 100644 --- a/Documentation/devicetree/bindings/usb/ohci-da8xx.txt +++ b/Documentation/devicetree/bindings/usb/ohci-da8xx.txt @@ -13,7 +13,7 @@ Optional properties: Example: -ohci: usb@0225000 { +ohci: usb@225000 { compatible = "ti,da830-ohci"; reg = <0x225000 0x1000>; interrupts = <59>; diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt index a12d6012a40f..3efde12b5d68 100644 --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt @@ -30,7 +30,7 @@ Example (Sequoia 440EPx): }; Example (Allwinner sun4i A10 SoC): - ehci0: usb@01c14000 { + ehci0: usb@1c14000 { compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; reg = <0x01c14000 0x100>; interrupts = <39>; diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt index e8766b08c93b..09e70c875bc6 100644 --- a/Documentation/devicetree/bindings/usb/usb-ohci.txt +++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt @@ -19,7 +19,7 @@ Optional properties: Example: - ohci0: usb@01c14400 { + ohci0: usb@1c14400 { compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; reg = <0x01c14400 0x100>; interrupts = <64>; diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt index c1a0a9191d26..057dd384d473 100644 --- a/Documentation/devicetree/bindings/usb/usb3503.txt +++ b/Documentation/devicetree/bindings/usb/usb3503.txt @@ -26,7 +26,7 @@ Optional properties: clock frequencies table is used) Examples: - usb3503@08 { + usb3503@8 { compatible = "smsc,usb3503"; reg = <0x08>; connect-gpios = <&gpx3 0 1>; diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt index f1e27faf528e..a85a631ec434 100644 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt @@ -10,7 +10,7 @@ Required properties: - reg: Should contain registers location and length Examples: -usbmisc@02184800 { +usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 235de0683bb6..5b38a30e608c 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,7 +13,7 @@ Required properties: Example: -wdt: watchdog@010000000 { +wdt: watchdog@10000000 { compatible = "mediatek,mt6589-wdt"; reg = <0x10000000 0x18>; }; diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index b8f75c51453a..62dd5baad70e 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -8,7 +8,7 @@ Required properties: Example: -wdt: watchdog@01c20c90 { +wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; -- cgit v1.2.3 From 8ddef132a36f4081b7cc7a34bce6a666e78083e3 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 1 Nov 2017 16:20:05 -0700 Subject: dt-bindings: rng: Document BCM7278 RNG200 compatible BCM7278 includes a RGN200 hardware random number generator, document the compatible string for that version of the IP. Signed-off-by: Florian Fainelli Acked-by: Rob Herring Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt index e25a456664b9..0014da9145af 100644 --- a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt +++ b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt @@ -1,7 +1,9 @@ HWRNG support for the iproc-rng200 driver Required properties: -- compatible : "brcm,iproc-rng200" +- compatible : Must be one of: + "brcm,bcm7278-rng200" + "brcm,iproc-rng200" - reg : base address and size of control register block Example: -- cgit v1.2.3 From 842ff286166e8512450573f6b6eb5e04e626a07f Mon Sep 17 00:00:00 2001 From: Anthony Kim Date: Wed, 25 Oct 2017 14:57:04 -0700 Subject: Input: add support for HiDeep touchscreen The HiDeep touchscreen device is a capacitive multi-touch controller mainly for multi-touch supported devices use. It use I2C interface for communication to IC and provide axis X, Y, Z locations for ten finger touch through input event interface to userspace. It support the Crimson and the Lime two type IC. They are different the number of channel supported and FW size. But the working protocol is same. Signed-off-by: Anthony Kim Acked-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/hideep.txt | 42 + .../devicetree/bindings/vendor-prefixes.txt | 1 + drivers/input/touchscreen/Kconfig | 11 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/hideep.c | 1120 ++++++++++++++++++++ 5 files changed, 1175 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/hideep.txt create mode 100644 drivers/input/touchscreen/hideep.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/hideep.txt b/Documentation/devicetree/bindings/input/touchscreen/hideep.txt new file mode 100644 index 000000000000..121d9b7c79a2 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/hideep.txt @@ -0,0 +1,42 @@ +* HiDeep Finger and Stylus touchscreen controller + +Required properties: +- compatible : must be "hideep,hideep-ts" +- reg : I2C slave address, (e.g. 0x6C). +- interrupt-parent : Interrupt controller to which the chip is connected. +- interrupts : Interrupt to which the chip is connected. + +Optional properties: +- vdd-supply : It is the controller supply for controlling + main voltage(3.3V) through the regulator. +- vid-supply : It is the controller supply for controlling + IO voltage(1.8V) through the regulator. +- reset-gpios : Define for reset gpio pin. + It is to use for reset IC. +- touchscreen-size-x : X axis size of touchscreen +- touchscreen-size-y : Y axis size of touchscreen +- linux,keycodes : Specifies an array of numeric keycode values to + be used for reporting button presses. The array can + contain up to 3 entries. + +Example: + +#include "dt-bindings/input/input.h" + +i2c@00000000 { + + /* ... */ + + touchscreen@6c { + compatible = "hideep,hideep-ts"; + reg = <0x6c>; + interrupt-parent = <&gpx1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&ldo15_reg>"; + vid-supply = <&ldo18_reg>; + reset-gpios = <&gpx1 5 0>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + linux,keycodes = , , ; + }; +}; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1afd298eddd7..138895e99508 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -137,6 +137,7 @@ gw Gateworks Corporation hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. hardkernel Hardkernel Co., Ltd +hideep HiDeep Inc. himax Himax Technologies, Inc. hisilicon Hisilicon Limited. hit Hitachi Ltd. diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 26a66bc7b2df..dbe33fc3a286 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -354,6 +354,17 @@ config TOUCHSCREEN_GOODIX To compile this driver as a module, choose M here: the module will be called goodix. +config TOUCHSCREEN_HIDEEP + tristate "HiDeep Touch IC" + depends on I2C + help + Say Y here if you have a touchscreen using HiDeep. + + If unsure, say N. + + To compile this driver as a moudle, choose M here : the + module will be called hideep_ts. + config TOUCHSCREEN_ILI210X tristate "Ilitek ILI210X based touchscreen" depends on I2C diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 2fa458088e3b..d9a7024c8cd9 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_TOUCHSCREEN_EGALAX_SERIAL) += egalax_ts_serial.o obj-$(CONFIG_TOUCHSCREEN_EXC3000) += exc3000.o obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o +obj-$(CONFIG_TOUCHSCREEN_HIDEEP) += hideep.o obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o obj-$(CONFIG_TOUCHSCREEN_IMX6UL_TSC) += imx6ul_tsc.o obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o diff --git a/drivers/input/touchscreen/hideep.c b/drivers/input/touchscreen/hideep.c new file mode 100644 index 000000000000..fc080a7c2e1f --- /dev/null +++ b/drivers/input/touchscreen/hideep.c @@ -0,0 +1,1120 @@ +/* + * Copyright (C) 2012-2017 Hideep, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 + * as published by the Free Software Foudation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HIDEEP_TS_NAME "HiDeep Touchscreen" +#define HIDEEP_I2C_NAME "hideep_ts" + +#define HIDEEP_MT_MAX 10 +#define HIDEEP_KEY_MAX 3 + +/* count(2) + touch data(100) + key data(6) */ +#define HIDEEP_MAX_EVENT 108UL + +#define HIDEEP_TOUCH_EVENT_INDEX 2 +#define HIDEEP_KEY_EVENT_INDEX 102 + +/* Touch & key event */ +#define HIDEEP_EVENT_ADDR 0x240 + +/* command list */ +#define HIDEEP_RESET_CMD 0x9800 + +/* event bit */ +#define HIDEEP_MT_RELEASED BIT(4) +#define HIDEEP_KEY_PRESSED BIT(7) +#define HIDEEP_KEY_FIRST_PRESSED BIT(8) +#define HIDEEP_KEY_PRESSED_MASK (HIDEEP_KEY_PRESSED | \ + HIDEEP_KEY_FIRST_PRESSED) + +#define HIDEEP_KEY_IDX_MASK 0x0f + +/* For NVM */ +#define HIDEEP_YRAM_BASE 0x40000000 +#define HIDEEP_PERIPHERAL_BASE 0x50000000 +#define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000) +#define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000) +#define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000) + +#define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000) +#define HIDEEP_SYSCON_SPC_CON (HIDEEP_SYSCON_BASE + 0x0004) +#define HIDEEP_SYSCON_CLK_CON (HIDEEP_SYSCON_BASE + 0x0008) +#define HIDEEP_SYSCON_CLK_ENA (HIDEEP_SYSCON_BASE + 0x000C) +#define HIDEEP_SYSCON_RST_CON (HIDEEP_SYSCON_BASE + 0x0010) +#define HIDEEP_SYSCON_WDT_CON (HIDEEP_SYSCON_BASE + 0x0014) +#define HIDEEP_SYSCON_WDT_CNT (HIDEEP_SYSCON_BASE + 0x0018) +#define HIDEEP_SYSCON_PWR_CON (HIDEEP_SYSCON_BASE + 0x0020) +#define HIDEEP_SYSCON_PGM_ID (HIDEEP_SYSCON_BASE + 0x00F4) + +#define HIDEEP_FLASH_CON (HIDEEP_FLASH_BASE + 0x0000) +#define HIDEEP_FLASH_STA (HIDEEP_FLASH_BASE + 0x0004) +#define HIDEEP_FLASH_CFG (HIDEEP_FLASH_BASE + 0x0008) +#define HIDEEP_FLASH_TIM (HIDEEP_FLASH_BASE + 0x000C) +#define HIDEEP_FLASH_CACHE_CFG (HIDEEP_FLASH_BASE + 0x0010) +#define HIDEEP_FLASH_PIO_SIG (HIDEEP_FLASH_BASE + 0x400000) + +#define HIDEEP_ESI_TX_INVALID (HIDEEP_ESI_BASE + 0x0008) + +#define HIDEEP_PERASE 0x00040000 +#define HIDEEP_WRONLY 0x00100000 + +#define HIDEEP_NVM_MASK_OFS 0x0000000C +#define HIDEEP_NVM_DEFAULT_PAGE 0 +#define HIDEEP_NVM_SFR_WPAGE 1 +#define HIDEEP_NVM_SFR_RPAGE 2 + +#define HIDEEP_PIO_SIG 0x00400000 +#define HIDEEP_PROT_MODE 0x03400000 + +#define HIDEEP_NVM_PAGE_SIZE 128 + +#define HIDEEP_DWZ_INFO 0x000002C0 + +struct hideep_event { + __le16 x; + __le16 y; + __le16 z; + u8 w; + u8 flag; + u8 type; + u8 index; +}; + +struct dwz_info { + __be32 code_start; + u8 code_crc[12]; + + __be32 c_code_start; + __be16 gen_ver; + __be16 c_code_len; + + __be32 vr_start; + __be16 rsv0; + __be16 vr_len; + + __be32 ft_start; + __be16 vr_version; + __be16 ft_len; + + __be16 core_ver; + __be16 boot_ver; + + __be16 release_ver; + __be16 custom_ver; + + u8 factory_id; + u8 panel_type; + u8 model_name[6]; + + __be16 extra_option; + __be16 product_code; + + __be16 vendor_id; + __be16 product_id; +}; + +struct pgm_packet { + struct { + u8 unused[3]; + u8 len; + __be32 addr; + } header; + __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)]; +}; + +#define HIDEEP_XFER_BUF_SIZE sizeof(struct pgm_packet) + +struct hideep_ts { + struct i2c_client *client; + struct input_dev *input_dev; + struct regmap *reg; + + struct touchscreen_properties prop; + + struct gpio_desc *reset_gpio; + + struct regulator *vcc_vdd; + struct regulator *vcc_vid; + + struct mutex dev_mutex; + + u32 tch_count; + u32 lpm_count; + + /* + * Data buffer to read packet from the device (contacts and key + * states). We align it on double-word boundary to keep word-sized + * fields in contact data and double-word-sized fields in program + * packet aligned. + */ + u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4); + + int key_num; + u32 key_codes[HIDEEP_KEY_MAX]; + + struct dwz_info dwz_info; + + unsigned int fw_size; + u32 nvm_mask; +}; + +static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr, + const __be32 *data, size_t count) +{ + struct pgm_packet *packet = (void *)ts->xfer_buf; + size_t len = count * sizeof(*data); + struct i2c_msg msg = { + .addr = ts->client->addr, + .len = len + sizeof(packet->header.len) + + sizeof(packet->header.addr), + .buf = &packet->header.len, + }; + int ret; + + if (len > HIDEEP_NVM_PAGE_SIZE) + return -EINVAL; + + packet->header.len = 0x80 | (count - 1); + packet->header.addr = cpu_to_be32(addr); + memcpy(packet->payload, data, len); + + ret = i2c_transfer(ts->client->adapter, &msg, 1); + if (ret != 1) + return ret < 0 ? ret : -EIO; + + return 0; +} + +static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr, + __be32 *data, size_t count) +{ + struct pgm_packet *packet = (void *)ts->xfer_buf; + size_t len = count * sizeof(*data); + struct i2c_msg msg[] = { + { + .addr = ts->client->addr, + .len = sizeof(packet->header.len) + + sizeof(packet->header.addr), + .buf = &packet->header.len, + }, + { + .addr = ts->client->addr, + .flags = I2C_M_RD, + .len = len, + .buf = (u8 *)data, + }, + }; + int ret; + + if (len > HIDEEP_NVM_PAGE_SIZE) + return -EINVAL; + + packet->header.len = count - 1; + packet->header.addr = cpu_to_be32(addr); + + ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg)); + if (ret != ARRAY_SIZE(msg)) + return ret < 0 ? ret : -EIO; + + return 0; +} + +static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val) +{ + __be32 data; + int error; + + error = hideep_pgm_r_mem(ts, addr, &data, 1); + if (error) { + dev_err(&ts->client->dev, + "read of register %#08x failed: %d\n", + addr, error); + return error; + } + + *val = be32_to_cpu(data); + return 0; +} + +static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val) +{ + __be32 data = cpu_to_be32(val); + int error; + + error = hideep_pgm_w_mem(ts, addr, &data, 1); + if (error) { + dev_err(&ts->client->dev, + "write to register %#08x (%#08x) failed: %d\n", + addr, val, error); + return error; + } + + return 0; +} + +#define SW_RESET_IN_PGM(clk) \ +{ \ + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \ + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \ + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01); \ +} + +#define SET_FLASH_PIO(ce) \ + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \ + 0x01 | ((ce) << 1)) + +#define SET_PIO_SIG(x, y) \ + hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y)) + +#define SET_FLASH_HWCONTROL() \ + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00) + +#define NVM_W_SFR(x, y) \ +{ \ + SET_FLASH_PIO(1); \ + SET_PIO_SIG(x, y); \ + SET_FLASH_PIO(0); \ +} + +static void hideep_pgm_set(struct hideep_ts *ts) +{ + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00); + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00); + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF); + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01); + hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01); + hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03); + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00); +} + +static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern) +{ + u16 p1 = 0xAF39; + u16 p2 = 0xDF9D; + int error; + + error = regmap_bulk_write(ts->reg, p1, &p2, 1); + if (error) { + dev_err(&ts->client->dev, + "%s: regmap_bulk_write() failed with %d\n", + __func__, error); + return error; + } + + usleep_range(1000, 1100); + + /* flush invalid Tx load register */ + error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01); + if (error) + return error; + + error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern); + if (error) + return error; + + return 0; +} + +static int hideep_enter_pgm(struct hideep_ts *ts) +{ + int retry_count = 10; + u32 pattern; + int error; + + while (retry_count--) { + error = hideep_pgm_get_pattern(ts, &pattern); + if (error) { + dev_err(&ts->client->dev, + "hideep_pgm_get_pattern failed: %d\n", error); + } else if (pattern != 0x39AF9DDF) { + dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n", + __func__, pattern); + } else { + dev_dbg(&ts->client->dev, "found magic code"); + + hideep_pgm_set(ts); + usleep_range(1000, 1100); + + return 0; + } + } + + dev_err(&ts->client->dev, "failed to enter pgm mode\n"); + SW_RESET_IN_PGM(1000); + return -EIO; +} + +static void hideep_nvm_unlock(struct hideep_ts *ts) +{ + u32 unmask_code; + + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE); + hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code); + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE); + + /* make it unprotected code */ + unmask_code &= ~HIDEEP_PROT_MODE; + + /* compare unmask code */ + if (unmask_code != ts->nvm_mask) + dev_warn(&ts->client->dev, + "read mask code different %#08x vs %#08x", + unmask_code, ts->nvm_mask); + + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE); + SET_FLASH_PIO(0); + + NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask); + SET_FLASH_HWCONTROL(); + hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE); +} + +static int hideep_check_status(struct hideep_ts *ts) +{ + int time_out = 100; + int status; + int error; + + while (time_out--) { + error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status); + if (!error && status) + return 0; + + usleep_range(1000, 1100); + } + + return -ETIMEDOUT; +} + +static int hideep_program_page(struct hideep_ts *ts, u32 addr, + const __be32 *ucode, size_t xfer_count) +{ + u32 val; + int error; + + error = hideep_check_status(ts); + if (error) + return -EBUSY; + + addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1); + + SET_FLASH_PIO(0); + SET_FLASH_PIO(1); + + /* erase page */ + SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF); + + SET_FLASH_PIO(0); + + error = hideep_check_status(ts); + if (error) + return -EBUSY; + + /* write page */ + SET_FLASH_PIO(1); + + val = be32_to_cpu(ucode[0]); + SET_PIO_SIG(HIDEEP_WRONLY | addr, val); + + hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY, + ucode, xfer_count); + + val = be32_to_cpu(ucode[xfer_count - 1]); + SET_PIO_SIG(124, val); + + SET_FLASH_PIO(0); + + usleep_range(1000, 1100); + + error = hideep_check_status(ts); + if (error) + return -EBUSY; + + SET_FLASH_HWCONTROL(); + + return 0; +} + +static int hideep_program_nvm(struct hideep_ts *ts, + const __be32 *ucode, size_t ucode_len) +{ + struct pgm_packet *packet_r = (void *)ts->xfer_buf; + __be32 *current_ucode = packet_r->payload; + size_t xfer_len; + size_t xfer_count; + u32 addr = 0; + int error; + + hideep_nvm_unlock(ts); + + while (ucode_len > 0) { + xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE); + xfer_count = xfer_len / sizeof(*ucode); + + error = hideep_pgm_r_mem(ts, 0x00000000 + addr, + current_ucode, xfer_count); + if (error) { + dev_err(&ts->client->dev, + "%s: failed to read page at offset %#08x: %d\n", + __func__, addr, error); + return error; + } + + /* See if the page needs updating */ + if (memcmp(ucode, current_ucode, xfer_len)) { + error = hideep_program_page(ts, addr, + ucode, xfer_count); + if (error) { + dev_err(&ts->client->dev, + "%s: iwrite failure @%#08x: %d\n", + __func__, addr, error); + return error; + } + + usleep_range(1000, 1100); + } + + ucode += xfer_count; + addr += xfer_len; + ucode_len -= xfer_len; + } + + return 0; +} + +static int hideep_verify_nvm(struct hideep_ts *ts, + const __be32 *ucode, size_t ucode_len) +{ + struct pgm_packet *packet_r = (void *)ts->xfer_buf; + __be32 *current_ucode = packet_r->payload; + size_t xfer_len; + size_t xfer_count; + u32 addr = 0; + int i; + int error; + + while (ucode_len > 0) { + xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE); + xfer_count = xfer_len / sizeof(*ucode); + + error = hideep_pgm_r_mem(ts, 0x00000000 + addr, + current_ucode, xfer_count); + if (error) { + dev_err(&ts->client->dev, + "%s: failed to read page at offset %#08x: %d\n", + __func__, addr, error); + return error; + } + + if (memcmp(ucode, current_ucode, xfer_len)) { + const u8 *ucode_bytes = (const u8 *)ucode; + const u8 *current_bytes = (const u8 *)current_ucode; + + for (i = 0; i < xfer_len; i++) + if (ucode_bytes[i] != current_bytes[i]) + dev_err(&ts->client->dev, + "%s: mismatch @%#08x: (%#02x vs %#02x)\n", + __func__, addr + i, + ucode_bytes[i], + current_bytes[i]); + + return -EIO; + } + + ucode += xfer_count; + addr += xfer_len; + ucode_len -= xfer_len; + } + + return 0; +} + +static int hideep_load_dwz(struct hideep_ts *ts) +{ + u16 product_code; + int error; + + error = hideep_enter_pgm(ts); + if (error) + return error; + + msleep(50); + + error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO, + (void *)&ts->dwz_info, + sizeof(ts->dwz_info) / sizeof(__be32)); + + SW_RESET_IN_PGM(10); + msleep(50); + + if (error) { + dev_err(&ts->client->dev, + "failed to fetch DWZ data: %d\n", error); + return error; + } + + product_code = be16_to_cpu(ts->dwz_info.product_code); + + switch (product_code & 0xF0) { + case 0x40: + dev_dbg(&ts->client->dev, "used crimson IC"); + ts->fw_size = 1024 * 48; + ts->nvm_mask = 0x00310000; + break; + case 0x60: + dev_dbg(&ts->client->dev, "used lime IC"); + ts->fw_size = 1024 * 64; + ts->nvm_mask = 0x0030027B; + break; + default: + dev_err(&ts->client->dev, "product code is wrong: %#04x", + product_code); + return -EINVAL; + } + + dev_dbg(&ts->client->dev, "firmware release version: %#04x", + be16_to_cpu(ts->dwz_info.release_ver)); + + return 0; +} + +static int hideep_flash_firmware(struct hideep_ts *ts, + const __be32 *ucode, size_t ucode_len) +{ + int retry_cnt = 3; + int error; + + while (retry_cnt--) { + error = hideep_program_nvm(ts, ucode, ucode_len); + if (!error) { + error = hideep_verify_nvm(ts, ucode, ucode_len); + if (!error) + return 0; + } + } + + return error; +} + +static int hideep_update_firmware(struct hideep_ts *ts, + const __be32 *ucode, size_t ucode_len) +{ + int error, error2; + + dev_dbg(&ts->client->dev, "starting firmware update"); + + /* enter program mode */ + error = hideep_enter_pgm(ts); + if (error) + return error; + + error = hideep_flash_firmware(ts, ucode, ucode_len); + if (error) + dev_err(&ts->client->dev, + "firmware update failed: %d\n", error); + else + dev_dbg(&ts->client->dev, "firmware updated successfully\n"); + + SW_RESET_IN_PGM(1000); + + error2 = hideep_load_dwz(ts); + if (error2) + dev_err(&ts->client->dev, + "failed to load dwz after firmware update: %d\n", + error2); + + return error ?: error2; +} + +static int hideep_power_on(struct hideep_ts *ts) +{ + int error = 0; + + error = regulator_enable(ts->vcc_vdd); + if (error) + dev_err(&ts->client->dev, + "failed to enable 'vdd' regulator: %d", error); + + usleep_range(999, 1000); + + error = regulator_enable(ts->vcc_vid); + if (error) + dev_err(&ts->client->dev, + "failed to enable 'vcc_vid' regulator: %d", + error); + + msleep(30); + + if (ts->reset_gpio) { + gpiod_set_value_cansleep(ts->reset_gpio, 0); + } else { + error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01); + if (error) + dev_err(&ts->client->dev, + "failed to send 'reset' command: %d\n", error); + } + + msleep(50); + + return error; +} + +static void hideep_power_off(void *data) +{ + struct hideep_ts *ts = data; + + if (ts->reset_gpio) + gpiod_set_value(ts->reset_gpio, 1); + + regulator_disable(ts->vcc_vid); + regulator_disable(ts->vcc_vdd); +} + +#define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN) + +static void hideep_report_slot(struct input_dev *input, + const struct hideep_event *event) +{ + input_mt_slot(input, event->index & 0x0f); + input_mt_report_slot_state(input, + __GET_MT_TOOL_TYPE(event->type), + !(event->flag & HIDEEP_MT_RELEASED)); + if (!(event->flag & HIDEEP_MT_RELEASED)) { + input_report_abs(input, ABS_MT_POSITION_X, + le16_to_cpup(&event->x)); + input_report_abs(input, ABS_MT_POSITION_Y, + le16_to_cpup(&event->y)); + input_report_abs(input, ABS_MT_PRESSURE, + le16_to_cpup(&event->z)); + input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w); + } +} + +static void hideep_parse_and_report(struct hideep_ts *ts) +{ + const struct hideep_event *events = + (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX]; + const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX]; + int touch_count = ts->xfer_buf[0]; + int key_count = ts->xfer_buf[1] & 0x0f; + int lpm_count = ts->xfer_buf[1] & 0xf0; + int i; + + /* get touch event count */ + dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x", + touch_count, key_count, lpm_count); + + touch_count = min(touch_count, HIDEEP_MT_MAX); + for (i = 0; i < touch_count; i++) + hideep_report_slot(ts->input_dev, events + i); + + key_count = min(key_count, HIDEEP_KEY_MAX); + for (i = 0; i < key_count; i++) { + u8 key_data = keys[i * 2]; + + input_report_key(ts->input_dev, + ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK], + key_data & HIDEEP_KEY_PRESSED_MASK); + } + + input_mt_sync_frame(ts->input_dev); + input_sync(ts->input_dev); +} + +static irqreturn_t hideep_irq(int irq, void *handle) +{ + struct hideep_ts *ts = handle; + int error; + + BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE); + + error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR, + ts->xfer_buf, HIDEEP_MAX_EVENT / 2); + if (error) { + dev_err(&ts->client->dev, "failed to read events: %d\n", error); + goto out; + } + + hideep_parse_and_report(ts); + +out: + return IRQ_HANDLED; +} + +static int hideep_get_axis_info(struct hideep_ts *ts) +{ + __le16 val[2]; + int error; + + error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val)); + if (error) + return error; + + ts->prop.max_x = le16_to_cpup(val); + ts->prop.max_y = le16_to_cpup(val + 1); + + dev_dbg(&ts->client->dev, "X: %d, Y: %d", + ts->prop.max_x, ts->prop.max_y); + + return 0; +} + +static int hideep_init_input(struct hideep_ts *ts) +{ + struct device *dev = &ts->client->dev; + int i; + int error; + + ts->input_dev = devm_input_allocate_device(dev); + if (!ts->input_dev) { + dev_err(dev, "failed to allocate input device\n"); + return -ENOMEM; + } + + ts->input_dev->name = HIDEEP_TS_NAME; + ts->input_dev->id.bustype = BUS_I2C; + input_set_drvdata(ts->input_dev, ts); + + input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X); + input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y); + input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0); + input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); + input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE, + 0, MT_TOOL_MAX, 0, 0); + touchscreen_parse_properties(ts->input_dev, true, &ts->prop); + + if (ts->prop.max_x == 0 || ts->prop.max_y == 0) { + error = hideep_get_axis_info(ts); + if (error) + return error; + } + + error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX, + INPUT_MT_DIRECT); + if (error) + return error; + + ts->key_num = device_property_read_u32_array(dev, "linux,keycodes", + NULL, 0); + if (ts->key_num > HIDEEP_KEY_MAX) { + dev_err(dev, "too many keys defined: %d\n", + ts->key_num); + return -EINVAL; + } + + if (ts->key_num <= 0) { + dev_dbg(dev, + "missing or malformed 'linux,keycodes' property\n"); + } else { + error = device_property_read_u32_array(dev, "linux,keycodes", + ts->key_codes, + ts->key_num); + if (error) { + dev_dbg(dev, "failed to read keymap: %d", error); + return error; + } + + if (ts->key_num) { + ts->input_dev->keycode = ts->key_codes; + ts->input_dev->keycodesize = sizeof(ts->key_codes[0]); + ts->input_dev->keycodemax = ts->key_num; + + for (i = 0; i < ts->key_num; i++) + input_set_capability(ts->input_dev, EV_KEY, + ts->key_codes[i]); + } + } + + error = input_register_device(ts->input_dev); + if (error) { + dev_err(dev, "failed to register input device: %d", error); + return error; + } + + return 0; +} + +static ssize_t hideep_update_fw(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct hideep_ts *ts = i2c_get_clientdata(client); + const struct firmware *fw_entry; + char *fw_name; + int mode; + int error; + + error = kstrtoint(buf, 0, &mode); + if (error) + return error; + + fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin", + be16_to_cpu(ts->dwz_info.product_id)); + if (!fw_name) + return -ENOMEM; + + error = request_firmware(&fw_entry, fw_name, dev); + if (error) { + dev_err(dev, "failed to request firmware %s: %d", + fw_name, error); + goto out_free_fw_name; + } + + if (fw_entry->size % sizeof(__be32)) { + dev_err(dev, "invalid firmware size %zu\n", fw_entry->size); + error = -EINVAL; + goto out_release_fw; + } + + if (fw_entry->size > ts->fw_size) { + dev_err(dev, "fw size (%zu) is too big (memory size %d)\n", + fw_entry->size, ts->fw_size); + error = -EFBIG; + goto out_release_fw; + } + + mutex_lock(&ts->dev_mutex); + disable_irq(client->irq); + + error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data, + fw_entry->size); + + enable_irq(client->irq); + mutex_unlock(&ts->dev_mutex); + +out_release_fw: + release_firmware(fw_entry); +out_free_fw_name: + kfree(fw_name); + + return error ?: count; +} + +static ssize_t hideep_fw_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct hideep_ts *ts = i2c_get_clientdata(client); + ssize_t len; + + mutex_lock(&ts->dev_mutex); + len = scnprintf(buf, PAGE_SIZE, "%04x\n", + be16_to_cpu(ts->dwz_info.release_ver)); + mutex_unlock(&ts->dev_mutex); + + return len; +} + +static ssize_t hideep_product_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct hideep_ts *ts = i2c_get_clientdata(client); + ssize_t len; + + mutex_lock(&ts->dev_mutex); + len = scnprintf(buf, PAGE_SIZE, "%04x\n", + be16_to_cpu(ts->dwz_info.product_id)); + mutex_unlock(&ts->dev_mutex); + + return len; +} + +static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL); +static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL); +static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw); + +static struct attribute *hideep_ts_sysfs_entries[] = { + &dev_attr_version.attr, + &dev_attr_product_id.attr, + &dev_attr_update_fw.attr, + NULL, +}; + +static const struct attribute_group hideep_ts_attr_group = { + .attrs = hideep_ts_sysfs_entries, +}; + +static int __maybe_unused hideep_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct hideep_ts *ts = i2c_get_clientdata(client); + + disable_irq(client->irq); + hideep_power_off(ts); + + return 0; +} + +static int __maybe_unused hideep_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct hideep_ts *ts = i2c_get_clientdata(client); + int error; + + error = hideep_power_on(ts); + if (error) { + dev_err(&client->dev, "power on failed"); + return error; + } + + enable_irq(client->irq); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume); + +static const struct regmap_config hideep_regmap_config = { + .reg_bits = 16, + .reg_format_endian = REGMAP_ENDIAN_LITTLE, + .val_bits = 16, + .val_format_endian = REGMAP_ENDIAN_LITTLE, + .max_register = 0xffff, +}; + +static int hideep_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct hideep_ts *ts; + int error; + + /* check i2c bus */ + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + dev_err(&client->dev, "check i2c device error"); + return -ENODEV; + } + + if (client->irq <= 0) { + dev_err(&client->dev, "missing irq: %d\n", client->irq); + return -EINVAL; + } + + ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + ts->client = client; + i2c_set_clientdata(client, ts); + mutex_init(&ts->dev_mutex); + + ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config); + if (IS_ERR(ts->reg)) { + error = PTR_ERR(ts->reg); + dev_err(&client->dev, + "failed to initialize regmap: %d\n", error); + return error; + } + + ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd"); + if (IS_ERR(ts->vcc_vdd)) + return PTR_ERR(ts->vcc_vdd); + + ts->vcc_vid = devm_regulator_get(&client->dev, "vid"); + if (IS_ERR(ts->vcc_vid)) + return PTR_ERR(ts->vcc_vid); + + ts->reset_gpio = devm_gpiod_get_optional(&client->dev, + "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ts->reset_gpio)) + return PTR_ERR(ts->reset_gpio); + + error = hideep_power_on(ts); + if (error) { + dev_err(&client->dev, "power on failed: %d\n", error); + return error; + } + + error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts); + if (error) + return error; + + error = hideep_load_dwz(ts); + if (error) { + dev_err(&client->dev, "failed to load dwz: %d", error); + return error; + } + + error = hideep_init_input(ts); + if (error) + return error; + + error = devm_request_threaded_irq(&client->dev, client->irq, + NULL, hideep_irq, IRQF_ONESHOT, + client->name, ts); + if (error) { + dev_err(&client->dev, "failed to request irq %d: %d\n", + client->irq, error); + return error; + } + + error = devm_device_add_group(&client->dev, &hideep_ts_attr_group); + if (error) { + dev_err(&client->dev, + "failed to add sysfs attributes: %d\n", error); + return error; + } + + return 0; +} + +static const struct i2c_device_id hideep_i2c_id[] = { + { HIDEEP_I2C_NAME, 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, hideep_i2c_id); + +#ifdef CONFIG_ACPI +static const struct acpi_device_id hideep_acpi_id[] = { + { "HIDP0001", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, hideep_acpi_id); +#endif + +#ifdef CONFIG_OF +static const struct of_device_id hideep_match_table[] = { + { .compatible = "hideep,hideep-ts" }, + { } +}; +MODULE_DEVICE_TABLE(of, hideep_match_table); +#endif + +static struct i2c_driver hideep_driver = { + .driver = { + .name = HIDEEP_I2C_NAME, + .of_match_table = of_match_ptr(hideep_match_table), + .acpi_match_table = ACPI_PTR(hideep_acpi_id), + .pm = &hideep_pm_ops, + }, + .id_table = hideep_i2c_id, + .probe = hideep_probe, +}; + +module_i2c_driver(hideep_driver); + +MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller"); +MODULE_AUTHOR("anthony.kim@hideep.com"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 0145a7141e597e14c60f7561add76bea874768b2 Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Thu, 9 Nov 2017 23:10:06 -0800 Subject: Input: add support for the Samsung S6SY761 touchscreen The S6SY761 touchscreen is a capicitive multi-touch controller for mobile use. It's connected with i2c at the address 0x48. This commit provides a basic version of the driver which can handle only initialization, touch events and power states. The controller is controlled by a firmware which, in the version I currently have, doesn't provide all the possible functionalities mentioned in the datasheet. Signed-off-by: Andi Shyti Acked-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/samsung,s6sy761.txt | 34 ++ drivers/input/touchscreen/Kconfig | 11 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/s6sy761.c | 559 +++++++++++++++++++++ 4 files changed, 605 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt create mode 100644 drivers/input/touchscreen/s6sy761.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt b/Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt new file mode 100644 index 000000000000..d9b7c2ff611e --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/samsung,s6sy761.txt @@ -0,0 +1,34 @@ +* Samsung S6SY761 touchscreen controller + +Required properties: +- compatible : must be "samsung,s6sy761" +- reg : I2C slave address, (e.g. 0x48) +- interrupt-parent : the phandle to the interrupt controller which provides + the interrupt +- interrupts : interrupt specification +- avdd-supply : analogic power supply +- vdd-supply : power supply + +Optional properties: +- touchscreen-size-x : see touchscreen.txt. This property is embedded in the + device. If defined it forces a different x resolution. +- touchscreen-size-y : see touchscreen.txt. This property is embedded in the + device. If defined it forces a different y resolution. + +Example: + +i2c@00000000 { + + /* ... */ + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&gpa1>; + interrupts = <1 IRQ_TYPE_NONE>; + avdd-supply = <&ldo30_reg>; + vdd-supply = <&ldo31_reg>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; +}; diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index dbe33fc3a286..0cfdb7cb610e 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -404,6 +404,17 @@ config TOUCHSCREEN_S3C2410 To compile this driver as a module, choose M here: the module will be called s3c2410_ts. +config TOUCHSCREEN_S6SY761 + tristate "Samsung S6SY761 Touchscreen driver" + depends on I2C + help + Say Y if you have the Samsung S6SY761 driver + + If unsure, say N + + To compile this driver as module, choose M here: the + module will be called s6sy761. + config TOUCHSCREEN_GUNZE tristate "Gunze AHL-51S touchscreen" select SERIO diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index d9a7024c8cd9..d2a2b3b7af27 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o obj-$(CONFIG_TOUCHSCREEN_PIXCIR) += pixcir_i2c_ts.o obj-$(CONFIG_TOUCHSCREEN_RM_TS) += raydium_i2c_ts.o obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o +obj-$(CONFIG_TOUCHSCREEN_S6SY761) += s6sy761.o obj-$(CONFIG_TOUCHSCREEN_SILEAD) += silead.o obj-$(CONFIG_TOUCHSCREEN_SIS_I2C) += sis_i2c.o obj-$(CONFIG_TOUCHSCREEN_ST1232) += st1232.o diff --git a/drivers/input/touchscreen/s6sy761.c b/drivers/input/touchscreen/s6sy761.c new file mode 100644 index 000000000000..26b1cb8a88ec --- /dev/null +++ b/drivers/input/touchscreen/s6sy761.c @@ -0,0 +1,559 @@ +/* + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * Author: Andi Shyti + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Samsung S6SY761 Touchscreen device driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* commands */ +#define S6SY761_SENSE_ON 0x10 +#define S6SY761_SENSE_OFF 0x11 +#define S6SY761_TOUCH_FUNCTION 0x30 /* R/W for get/set */ +#define S6SY761_FIRMWARE_INTEGRITY 0x21 +#define S6SY761_PANEL_INFO 0x23 +#define S6SY761_DEVICE_ID 0x52 +#define S6SY761_BOOT_STATUS 0x55 +#define S6SY761_READ_ONE_EVENT 0x60 +#define S6SY761_READ_ALL_EVENT 0x61 +#define S6SY761_CLEAR_EVENT_STACK 0x62 +#define S6SY761_APPLICATION_MODE 0xe4 + +/* events */ +#define S6SY761_EVENT_INFO 0x02 +#define S6SY761_EVENT_VENDOR_INFO 0x07 + +/* info */ +#define S6SY761_INFO_BOOT_COMPLETE 0x00 + +/* firmware status */ +#define S6SY761_FW_OK 0x80 + +/* + * the functionalities are put as a reference + * as in the device I am using none of them + * works therefore not used in this driver yet. + */ +/* touchscreen functionalities */ +#define S6SY761_MASK_TOUCH BIT(0) +#define S6SY761_MASK_HOVER BIT(1) +#define S6SY761_MASK_COVER BIT(2) +#define S6SY761_MASK_GLOVE BIT(3) +#define S6SY761_MASK_STYLUS BIT(4) +#define S6SY761_MASK_PALM BIT(5) +#define S6SY761_MASK_WET BIT(6) +#define S6SY761_MASK_PROXIMITY BIT(7) + +/* boot status (BS) */ +#define S6SY761_BS_BOOT_LOADER 0x10 +#define S6SY761_BS_APPLICATION 0x20 + +/* event id */ +#define S6SY761_EVENT_ID_COORDINATE 0x00 +#define S6SY761_EVENT_ID_STATUS 0x01 + +/* event register masks */ +#define S6SY761_MASK_TOUCH_STATE 0xc0 /* byte 0 */ +#define S6SY761_MASK_TID 0x3c +#define S6SY761_MASK_EID 0x03 +#define S6SY761_MASK_X 0xf0 /* byte 3 */ +#define S6SY761_MASK_Y 0x0f +#define S6SY761_MASK_Z 0x3f /* byte 6 */ +#define S6SY761_MASK_LEFT_EVENTS 0x3f /* byte 7 */ +#define S6SY761_MASK_TOUCH_TYPE 0xc0 /* MSB in byte 6, LSB in byte 7 */ + +/* event touch state values */ +#define S6SY761_TS_NONE 0x00 +#define S6SY761_TS_PRESS 0x01 +#define S6SY761_TS_MOVE 0x02 +#define S6SY761_TS_RELEASE 0x03 + +/* application modes */ +#define S6SY761_APP_NORMAL 0x0 +#define S6SY761_APP_LOW_POWER 0x1 +#define S6SY761_APP_TEST 0x2 +#define S6SY761_APP_FLASH 0x3 +#define S6SY761_APP_SLEEP 0x4 + +#define S6SY761_EVENT_SIZE 8 +#define S6SY761_EVENT_COUNT 32 +#define S6SY761_DEVID_SIZE 3 +#define S6SY761_PANEL_ID_SIZE 11 +#define S6SY761_TS_STATUS_SIZE 5 +#define S6SY761_MAX_FINGERS 10 + +#define S6SY761_DEV_NAME "s6sy761" + +enum s6sy761_regulators { + S6SY761_REGULATOR_VDD, + S6SY761_REGULATOR_AVDD, +}; + +struct s6sy761_data { + struct i2c_client *client; + struct regulator_bulk_data regulators[2]; + struct input_dev *input; + struct touchscreen_properties prop; + + u8 data[S6SY761_EVENT_SIZE * S6SY761_EVENT_COUNT]; + + u16 devid; + u8 tx_channel; +}; + +/* + * We can't simply use i2c_smbus_read_i2c_block_data because we + * need to read more than 255 bytes + */ +static int s6sy761_read_events(struct s6sy761_data *sdata, u16 n_events) +{ + u8 cmd = S6SY761_READ_ALL_EVENT; + struct i2c_msg msgs[2] = { + { + .addr = sdata->client->addr, + .len = 1, + .buf = &cmd, + }, + { + .addr = sdata->client->addr, + .flags = I2C_M_RD, + .len = (n_events * S6SY761_EVENT_SIZE), + .buf = sdata->data + S6SY761_EVENT_SIZE, + }, + }; + int ret; + + ret = i2c_transfer(sdata->client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret < 0) + return ret; + + return ret == ARRAY_SIZE(msgs) ? 0 : -EIO; +} + +static void s6sy761_report_coordinates(struct s6sy761_data *sdata, + u8 *event, u8 tid) +{ + u8 major = event[4]; + u8 minor = event[5]; + u8 z = event[6] & S6SY761_MASK_Z; + u16 x = (event[1] << 3) | ((event[3] & S6SY761_MASK_X) >> 4); + u16 y = (event[2] << 3) | (event[3] & S6SY761_MASK_Y); + + input_mt_slot(sdata->input, tid); + + input_mt_report_slot_state(sdata->input, MT_TOOL_FINGER, true); + input_report_abs(sdata->input, ABS_MT_POSITION_X, x); + input_report_abs(sdata->input, ABS_MT_POSITION_Y, y); + input_report_abs(sdata->input, ABS_MT_TOUCH_MAJOR, major); + input_report_abs(sdata->input, ABS_MT_TOUCH_MINOR, minor); + input_report_abs(sdata->input, ABS_MT_PRESSURE, z); + + input_sync(sdata->input); +} + +static void s6sy761_report_release(struct s6sy761_data *sdata, + u8 *event, u8 tid) +{ + input_mt_slot(sdata->input, tid); + input_mt_report_slot_state(sdata->input, MT_TOOL_FINGER, false); + + input_sync(sdata->input); +} + +static void s6sy761_handle_coordinates(struct s6sy761_data *sdata, u8 *event) +{ + u8 tid; + u8 touch_state; + + if (unlikely(!(event[0] & S6SY761_MASK_TID))) + return; + + tid = ((event[0] & S6SY761_MASK_TID) >> 2) - 1; + touch_state = (event[0] & S6SY761_MASK_TOUCH_STATE) >> 6; + + switch (touch_state) { + + case S6SY761_TS_NONE: + break; + case S6SY761_TS_RELEASE: + s6sy761_report_release(sdata, event, tid); + break; + case S6SY761_TS_PRESS: + case S6SY761_TS_MOVE: + s6sy761_report_coordinates(sdata, event, tid); + break; + } +} + +static void s6sy761_handle_events(struct s6sy761_data *sdata, u8 n_events) +{ + int i; + + for (i = 0; i < n_events; i++) { + u8 *event = &sdata->data[i * S6SY761_EVENT_SIZE]; + u8 event_id = event[0] & S6SY761_MASK_EID; + + if (!event[0]) + return; + + switch (event_id) { + + case S6SY761_EVENT_ID_COORDINATE: + s6sy761_handle_coordinates(sdata, event); + break; + + case S6SY761_EVENT_ID_STATUS: + break; + + default: + break; + } + } +} + +static irqreturn_t s6sy761_irq_handler(int irq, void *dev) +{ + struct s6sy761_data *sdata = dev; + int ret; + u8 n_events; + + ret = i2c_smbus_read_i2c_block_data(sdata->client, + S6SY761_READ_ONE_EVENT, + S6SY761_EVENT_SIZE, + sdata->data); + if (ret < 0) { + dev_err(&sdata->client->dev, "failed to read events\n"); + return IRQ_HANDLED; + } + + if (!sdata->data[0]) + return IRQ_HANDLED; + + n_events = sdata->data[7] & S6SY761_MASK_LEFT_EVENTS; + if (unlikely(n_events > S6SY761_EVENT_COUNT - 1)) + return IRQ_HANDLED; + + if (n_events) { + ret = s6sy761_read_events(sdata, n_events); + if (ret < 0) { + dev_err(&sdata->client->dev, "failed to read events\n"); + return IRQ_HANDLED; + } + } + + s6sy761_handle_events(sdata, n_events + 1); + + return IRQ_HANDLED; +} + +static int s6sy761_input_open(struct input_dev *dev) +{ + struct s6sy761_data *sdata = input_get_drvdata(dev); + + return i2c_smbus_write_byte(sdata->client, S6SY761_SENSE_ON); +} + +static void s6sy761_input_close(struct input_dev *dev) +{ + struct s6sy761_data *sdata = input_get_drvdata(dev); + int ret; + + ret = i2c_smbus_write_byte(sdata->client, S6SY761_SENSE_OFF); + if (ret) + dev_err(&sdata->client->dev, "failed to turn off sensing\n"); +} + +static ssize_t s6sy761_sysfs_devid(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s6sy761_data *sdata = dev_get_drvdata(dev); + + return sprintf(buf, "%#x\n", sdata->devid); +} + +static DEVICE_ATTR(devid, 0444, s6sy761_sysfs_devid, NULL); + +static struct attribute *s6sy761_sysfs_attrs[] = { + &dev_attr_devid.attr, + NULL +}; + +static struct attribute_group s6sy761_attribute_group = { + .attrs = s6sy761_sysfs_attrs +}; + +static int s6sy761_power_on(struct s6sy761_data *sdata) +{ + u8 buffer[S6SY761_EVENT_SIZE]; + u8 event; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(sdata->regulators), + sdata->regulators); + if (ret) + return ret; + + msleep(140); + + /* double check whether the touch is functional */ + ret = i2c_smbus_read_i2c_block_data(sdata->client, + S6SY761_READ_ONE_EVENT, + S6SY761_EVENT_SIZE, + buffer); + if (ret < 0) + return ret; + + event = (buffer[0] >> 2) & 0xf; + + if ((event != S6SY761_EVENT_INFO && + event != S6SY761_EVENT_VENDOR_INFO) || + buffer[1] != S6SY761_INFO_BOOT_COMPLETE) { + return -ENODEV; + } + + ret = i2c_smbus_read_byte_data(sdata->client, S6SY761_BOOT_STATUS); + if (ret < 0) + return ret; + + /* for some reasons the device might be stuck in the bootloader */ + if (ret != S6SY761_BS_APPLICATION) + return -ENODEV; + + /* enable touch functionality */ + ret = i2c_smbus_write_word_data(sdata->client, + S6SY761_TOUCH_FUNCTION, + S6SY761_MASK_TOUCH); + if (ret) + return ret; + + return 0; +} + +static int s6sy761_hw_init(struct s6sy761_data *sdata, + unsigned int *max_x, unsigned int *max_y) +{ + u8 buffer[S6SY761_PANEL_ID_SIZE]; /* larger read size */ + int ret; + + ret = s6sy761_power_on(sdata); + if (ret) + return ret; + + ret = i2c_smbus_read_i2c_block_data(sdata->client, + S6SY761_DEVICE_ID, + S6SY761_DEVID_SIZE, + buffer); + if (ret < 0) + return ret; + + sdata->devid = get_unaligned_be16(buffer + 1); + + ret = i2c_smbus_read_i2c_block_data(sdata->client, + S6SY761_PANEL_INFO, + S6SY761_PANEL_ID_SIZE, + buffer); + if (ret < 0) + return ret; + + *max_x = get_unaligned_be16(buffer); + *max_y = get_unaligned_be16(buffer + 2); + + /* if no tx channels defined, at least keep one */ + sdata->tx_channel = max_t(u8, buffer[8], 1); + + ret = i2c_smbus_read_byte_data(sdata->client, + S6SY761_FIRMWARE_INTEGRITY); + if (ret < 0) + return ret; + else if (ret != S6SY761_FW_OK) + return -ENODEV; + + return 0; +} + +static void s6sy761_power_off(void *data) +{ + struct s6sy761_data *sdata = data; + + disable_irq(sdata->client->irq); + regulator_bulk_disable(ARRAY_SIZE(sdata->regulators), + sdata->regulators); +} + +static int s6sy761_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct s6sy761_data *sdata; + unsigned int max_x, max_y; + int err; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_I2C_BLOCK)) + return -ENODEV; + + sdata = devm_kzalloc(&client->dev, sizeof(*sdata), GFP_KERNEL); + if (!sdata) + return -ENOMEM; + + i2c_set_clientdata(client, sdata); + sdata->client = client; + + sdata->regulators[S6SY761_REGULATOR_VDD].supply = "vdd"; + sdata->regulators[S6SY761_REGULATOR_AVDD].supply = "avdd"; + err = devm_regulator_bulk_get(&client->dev, + ARRAY_SIZE(sdata->regulators), + sdata->regulators); + if (err) + return err; + + err = devm_add_action_or_reset(&client->dev, s6sy761_power_off, sdata); + if (err) + return err; + + err = s6sy761_hw_init(sdata, &max_x, &max_y); + if (err) + return err; + + sdata->input = devm_input_allocate_device(&client->dev); + if (!sdata->input) + return -ENOMEM; + + sdata->input->name = S6SY761_DEV_NAME; + sdata->input->id.bustype = BUS_I2C; + sdata->input->open = s6sy761_input_open; + sdata->input->close = s6sy761_input_close; + + input_set_abs_params(sdata->input, ABS_MT_POSITION_X, 0, max_x, 0, 0); + input_set_abs_params(sdata->input, ABS_MT_POSITION_Y, 0, max_y, 0, 0); + input_set_abs_params(sdata->input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); + input_set_abs_params(sdata->input, ABS_MT_TOUCH_MINOR, 0, 255, 0, 0); + input_set_abs_params(sdata->input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); + input_set_abs_params(sdata->input, ABS_MT_TOUCH_MINOR, 0, 255, 0, 0); + input_set_abs_params(sdata->input, ABS_MT_PRESSURE, 0, 255, 0, 0); + + touchscreen_parse_properties(sdata->input, true, &sdata->prop); + + if (!input_abs_get_max(sdata->input, ABS_X) || + !input_abs_get_max(sdata->input, ABS_Y)) { + dev_warn(&client->dev, "the axis have not been set\n"); + } + + err = input_mt_init_slots(sdata->input, sdata->tx_channel, + INPUT_MT_DIRECT); + if (err) + return err; + + input_set_drvdata(sdata->input, sdata); + + err = input_register_device(sdata->input); + if (err) + return err; + + err = devm_request_threaded_irq(&client->dev, client->irq, NULL, + s6sy761_irq_handler, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "s6sy761_irq", sdata); + if (err) + return err; + + err = devm_device_add_group(&client->dev, &s6sy761_attribute_group); + if (err) + return err; + + pm_runtime_enable(&client->dev); + + return 0; +} + +static int s6sy761_remove(struct i2c_client *client) +{ + pm_runtime_disable(&client->dev); + + return 0; +} + +static int __maybe_unused s6sy761_runtime_suspend(struct device *dev) +{ + struct s6sy761_data *sdata = dev_get_drvdata(dev); + + return i2c_smbus_write_byte_data(sdata->client, + S6SY761_APPLICATION_MODE, S6SY761_APP_SLEEP); +} + +static int __maybe_unused s6sy761_runtime_resume(struct device *dev) +{ + struct s6sy761_data *sdata = dev_get_drvdata(dev); + + return i2c_smbus_write_byte_data(sdata->client, + S6SY761_APPLICATION_MODE, S6SY761_APP_NORMAL); +} + +static int __maybe_unused s6sy761_suspend(struct device *dev) +{ + struct s6sy761_data *sdata = dev_get_drvdata(dev); + + s6sy761_power_off(sdata); + + return 0; +} + +static int __maybe_unused s6sy761_resume(struct device *dev) +{ + struct s6sy761_data *sdata = dev_get_drvdata(dev); + + enable_irq(sdata->client->irq); + + return s6sy761_power_on(sdata); +} + +static const struct dev_pm_ops s6sy761_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(s6sy761_suspend, s6sy761_resume) + SET_RUNTIME_PM_OPS(s6sy761_runtime_suspend, + s6sy761_runtime_resume, NULL) +}; + +#ifdef CONFIG_OF +static const struct of_device_id s6sy761_of_match[] = { + { .compatible = "samsung,s6sy761", }, + { }, +}; +MODULE_DEVICE_TABLE(of, s6sy761_of_match); +#endif + +static const struct i2c_device_id s6sy761_id[] = { + { "s6sy761", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, s6sy761_id); + +static struct i2c_driver s6sy761_driver = { + .driver = { + .name = S6SY761_DEV_NAME, + .of_match_table = of_match_ptr(s6sy761_of_match), + .pm = &s6sy761_pm_ops, + }, + .probe = s6sy761_probe, + .remove = s6sy761_remove, + .id_table = s6sy761_id, +}; + +module_i2c_driver(s6sy761_driver); + +MODULE_AUTHOR("Andi Shyti "); +MODULE_DESCRIPTION("Samsung S6SY761 Touch Screen"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From b8b0d10c3a9b6ee94d56d0c3b162d05c177fb101 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Thu, 9 Nov 2017 15:07:57 +0100 Subject: ASoC: add mclk-fs to audio graph card binding Add mclk-fs support to audio graph card as initially supported in simple card. Signed-off-by: Olivier Moysan Acked-by: Kuninori Morimoto Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/audio-graph-card.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-card.txt index 6e6720aa33f1..d04ea3b1a1dd 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph-card.txt +++ b/Documentation/devicetree/bindings/sound/audio-graph-card.txt @@ -17,6 +17,7 @@ Below are same as Simple-Card. - bitclock-master - bitclock-inversion - frame-inversion +- mclk-fs - dai-tdm-slot-num - dai-tdm-slot-width - clocks / system-clock-frequency -- cgit v1.2.3 From 3ec26c7944a405e9dbd21b31ff46a3b4e6095adb Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 9 Nov 2017 18:09:26 +0100 Subject: bindings: net: stmmac: correctify note about LPI interrupt There are two different combined signal for various interrupt events: In EQOS-CORE and EQOS-MTL configurations, mci_intr_o is the interrupt signal. In EQOS-DMA, EQOS-AHB and EQOS-AXI configurations, these interrupt events are combined with the events in the DMA on the sbd_intr_o signal. Depending on configuration, the device tree irq "macirq" will refer to either mci_intr_o or sbd_intr_o. The databook states: "The MAC generates the LPI interrupt when the Tx or Rx side enters or exits the LPI state. The interrupt mci_intr_o (sbd_intr_o in certain configurations) is asserted when the LPI interrupt status is set. When the MAC exits the Rx LPI state, then in addition to the mci_intr_o (sbd_intr_o in certain configurations), the sideband signal lpi_intr_o is asserted. If you do not want to gate-off the application clock during the Rx LPI state, you can leave the lpi_intr_o signal unconnected and use the mci_intr_o (sbd_intr_o in certain configurations) signal to detect Rx LPI exit." Since the "macirq" is always raised when Tx or Rx enters/exits the LPI state, "eth_lpi" must therefore refer to lpi_intr_o, which is only raised when Rx exits the LPI state. Update the DT binding description to reflect reality. Signed-off-by: Niklas Cassel Acked-by: Alexandre TORGUE Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/stmmac.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt index c3a7be6615c5..3a28a5d8857d 100644 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt @@ -12,7 +12,7 @@ Required properties: Valid interrupt names are: - "macirq" (combined signal for various interrupt events) - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection) - - "eth_lpi" (the interrupt that occurs when Tx or Rx enters/exits LPI state) + - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state) - phy-mode: See ethernet.txt file in the same directory. - snps,reset-gpio gpio number for phy reset. - snps,reset-active-low boolean flag to indicate if phy reset is active low. -- cgit v1.2.3 From aa25e446ce76c37bfd75ac06598c316af94e9a26 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Nov 2017 16:00:55 -0600 Subject: dt-bindings: usb: add #phy-cells to usb-nop-xceiv Consumers of usb-nop-xceiv use the phy binding, but #phy-cells is missing from the binding. This is probably because this binding predates the common phy binding. So add #phy-cells as a required property. This should not break any users as missing should be treated as 0 cells. Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt index 5be01c859b7a..4dc6a8ee3071 100644 --- a/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt +++ b/Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt @@ -2,6 +2,7 @@ USB NOP PHY Required properties: - compatible: should be usb-nop-xceiv +- #phy-cells: Must be 0 Optional properties: - clocks: phandle to the PHY clock. Use as per Documentation/devicetree @@ -33,6 +34,7 @@ Example: reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; vbus-detect-gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; vbus-regulator = <&vbus_regulator>; + #phy-cells = <0>; }; hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator -- cgit v1.2.3 From ccb4e74aebb6fbd56fc6783f4d5c6ded48bc2f5d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 4 Oct 2017 19:10:38 +0900 Subject: dt-bindings: pwm: Add R-Car D3 device tree bindings Add device tree bindings for the PWM controller found on R-Car D3 SoCs. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index 7e94b802395d..74c118015980 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -9,6 +9,7 @@ Required Properties: - "renesas,pwm-r8a7794": for R-Car E2 - "renesas,pwm-r8a7795": for R-Car H3 - "renesas,pwm-r8a7796": for R-Car M3-W + - "renesas,pwm-r8a77995": for R-Car D3 - reg: base address and length of the registers block for the PWM. - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. -- cgit v1.2.3 From 8f6596f4c94a155b93a809989314e5e8c01d0618 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Thu, 9 Nov 2017 11:34:16 +0800 Subject: dt-bindings: rtc: Add Spreadtrum SC27xx RTC documentation This patch adds the binding documentation for Spreadtrum SC27xx series RTC device. Signed-off-by: Baolin Wang Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/sprd,sc27xx-rtc.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt b/Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt new file mode 100644 index 000000000000..7c170da0d4b7 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sprd,sc27xx-rtc.txt @@ -0,0 +1,27 @@ +Spreadtrum SC27xx Real Time Clock + +Required properties: +- compatible: should be "sprd,sc2731-rtc". +- reg: address offset of rtc register. +- interrupt-parent: phandle for the interrupt controller. +- interrupts: rtc alarm interrupt. + +Example: + + sc2731_pmic: pmic@0 { + compatible = "sprd,sc2731"; + reg = <0>; + spi-max-frequency = <26000000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@280 { + compatible = "sprd,sc2731-rtc"; + reg = <0x280>; + interrupt-parent = <&sc2731_pmic>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + }; -- cgit v1.2.3 From 1759f27027c88adfd94b436fda219eb80531bf6d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 9 Nov 2017 18:07:16 +0100 Subject: dt-bindings: usb: fix example hub node name According to the OF Recommended Practice for USB, hub nodes shall be named "hub", but the example had mixed up the label and node names. Fix the node name and drop the redundant label. While at it, remove a newline and add a missing semicolon to the example source. Signed-off-by: Johan Hovold Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/usb/usb-device.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt b/Documentation/devicetree/bindings/usb/usb-device.txt index ce02cebac26a..4df7e22e0084 100644 --- a/Documentation/devicetree/bindings/usb/usb-device.txt +++ b/Documentation/devicetree/bindings/usb/usb-device.txt @@ -16,12 +16,11 @@ Required properties: Example: &usb1 { - #address-cells = <1>; #size-cells = <0>; - hub: genesys@1 { + hub@1 { compatible = "usb5e3,608"; reg = <1>; }; -} +}; -- cgit v1.2.3 From f42ae7b0540937e00fe005812997f126aaac4bc2 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 9 Nov 2017 18:07:17 +0100 Subject: dt-bindings: usb: fix reg-property port-number range The USB hub port-number range for USB 2.0 is 1-255 and not 1-31 which reflects an arbitrary limit set by the current Linux implementation. Note that for USB 3.1 hubs the valid range is 1-15. Increase the documented valid range in the binding to 255, which is the maximum allowed by the specifications. Signed-off-by: Johan Hovold Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/usb/usb-device.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt b/Documentation/devicetree/bindings/usb/usb-device.txt index 4df7e22e0084..b749fb9f2674 100644 --- a/Documentation/devicetree/bindings/usb/usb-device.txt +++ b/Documentation/devicetree/bindings/usb/usb-device.txt @@ -11,7 +11,7 @@ Required properties: be used, but a device adhering to this binding may leave out all except for usbVID,PID. - reg: the port number which this device is connecting to, the range - is 1-31. + is 1-255. Example: -- cgit v1.2.3 From bfebcf54608a749800a171ffd01f7d5b450e9a55 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 9 Nov 2017 18:07:18 +0100 Subject: dt-bindings: usb: clean up compatible property Add quotation marks around the compatible string to avoid ambiguity due to following punctuation, and define the VID and PID components. Signed-off-by: Johan Hovold Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/usb/usb-device.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt b/Documentation/devicetree/bindings/usb/usb-device.txt index b749fb9f2674..e0b562e35a0c 100644 --- a/Documentation/devicetree/bindings/usb/usb-device.txt +++ b/Documentation/devicetree/bindings/usb/usb-device.txt @@ -5,11 +5,11 @@ The reference binding doc is from: http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps Required properties: -- compatible: usbVID,PID. The textual representation of VID, PID shall - be in lower case hexadecimal with leading zeroes suppressed. The - other compatible strings from the above standard binding could also - be used, but a device adhering to this binding may leave out all except - for usbVID,PID. +- compatible: "usbVID,PID", where VID is the vendor id and PID the product id. + The textual representation of VID and PID shall be in lower case hexadecimal + with leading zeroes suppressed. The other compatible strings from the above + standard binding could also be used, but a device adhering to this binding + may leave out all except for "usbVID,PID". - reg: the port number which this device is connecting to, the range is 1-255. -- cgit v1.2.3 From f877918cdd793373fb7a960c72ba3639786e8e8f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 9 Nov 2017 18:07:19 +0100 Subject: dt-bindings: usb: document hub and host-controller properties Hub nodes and host-controller nodes with child nodes must specify values for #address-cells (1) and #size-cells (0). Also make the definition of the related reg property a bit more stringent, and add comments to the example source. Signed-off-by: Johan Hovold Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/usb/usb-device.txt | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt b/Documentation/devicetree/bindings/usb/usb-device.txt index e0b562e35a0c..1b27cebb47f4 100644 --- a/Documentation/devicetree/bindings/usb/usb-device.txt +++ b/Documentation/devicetree/bindings/usb/usb-device.txt @@ -4,22 +4,34 @@ Usually, we only use device tree for hard wired USB device. The reference binding doc is from: http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps + Required properties: - compatible: "usbVID,PID", where VID is the vendor id and PID the product id. The textual representation of VID and PID shall be in lower case hexadecimal with leading zeroes suppressed. The other compatible strings from the above standard binding could also be used, but a device adhering to this binding may leave out all except for "usbVID,PID". -- reg: the port number which this device is connecting to, the range - is 1-255. +- reg: the number of the USB hub port or the USB host-controller port to which + this device is attached. The range is 1-255. + + +Required properties for hub nodes with device nodes: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + + +Required properties for host-controller nodes with device nodes: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + Example: -&usb1 { +&usb1 { /* host controller */ #address-cells = <1>; #size-cells = <0>; - hub@1 { + hub@1 { /* hub connected to port 1 */ compatible = "usb5e3,608"; reg = <1>; }; -- cgit v1.2.3 From def4db33e69609a43b28b399d569b6a0d3ba272a Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 18 Nov 2017 03:22:32 +0100 Subject: dt-bindings: trivial-devices: Remove fsl,mc13892 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device's bindings are not trivial: Additional properties are documented in in Documentation/devicetree/bindings/mfd/mc13xxx.txt. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Fabio Estevam Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/trivial-devices.txt | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index 4b169caab0eb..21e2d96295fe 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -55,7 +55,6 @@ epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE emmicro,em3027 EM Microelectronic EM3027 Real-time Clock fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer -fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor -- cgit v1.2.3 From 87c9fd81825363237ac5560822e2261535800597 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 15 Nov 2017 10:59:53 -0200 Subject: dt-bindings: rtc: imxdi: Improve the bindings text Improve the bindings text by doing the following changes: - Remove the i.MX53 reference, as the RTC on i.MX53 is a different hardware - Add 'clocks' to the list of required properties - Explain that the optional security violation irq is the second entry - Use the real unit address and irq numbers for i.MX25 Signed-off-by: Fabio Estevam Acked-by: Juergen Borleis Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/imxdi-rtc.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt index 323cf26374cb..c797bc9d77d2 100644 --- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt @@ -1,20 +1,20 @@ * i.MX25 Real Time Clock controller -This binding supports the following chips: i.MX25, i.MX53 - Required properties: - compatible: should be: "fsl,imx25-rtc" - reg: physical base address of the controller and length of memory mapped region. +- clocks: should contain the phandle for the rtc clock - interrupts: rtc alarm interrupt Optional properties: -- interrupts: dryice security violation interrupt +- interrupts: dryice security violation interrupt (second entry) Example: -rtc@80056000 { - compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; - reg = <0x80056000 2000>; - interrupts = <29 56>; +rtc@53ffc000 { + compatible = "fsl,imx25-rtc"; + reg = <0x53ffc000 0x4000>; + clocks = <&clks 81>; + interrupts = <25 56>; }; -- cgit v1.2.3 From 68615eb01f82256c19e41967bfb3eef902f77033 Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Mon, 27 Nov 2017 17:31:00 +0100 Subject: hwmon: (jc42) optionally try to disable the SMBUS timeout With a nxp,se97 chip on an atmel sama5d31 board, the I2C adapter driver is not always capable of avoiding the 25-35 ms timeout as specified by the SMBUS protocol. This may cause silent corruption of the last bit of any transfer, e.g. a one is read instead of a zero if the sensor chip times out. This also affects the eeprom half of the nxp-se97 chip, where this silent corruption was originally noticed. Other I2C adapters probably suffer similar issues, e.g. bit-banging comes to mind as risky... The SMBUS register in the nxp chip is not a standard Jedec register, but it is not special to the nxp chips either, at least the atmel chips have the same mechanism. Therefore, do not special case this on the manufacturer, it is opt-in via the device property anyway. Cc: stable@vger.kernel.org # 4.9+ Signed-off-by: Peter Rosin Acked-by: Rob Herring Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/jc42.txt | 4 ++++ drivers/hwmon/jc42.c | 21 +++++++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/jc42.txt b/Documentation/devicetree/bindings/hwmon/jc42.txt index 07a250498fbb..f569db58f64a 100644 --- a/Documentation/devicetree/bindings/hwmon/jc42.txt +++ b/Documentation/devicetree/bindings/hwmon/jc42.txt @@ -34,6 +34,10 @@ Required properties: - reg: I2C address +Optional properties: +- smbus-timeout-disable: When set, the smbus timeout function will be disabled. + This is not supported on all chips. + Example: temp-sensor@1a { diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c index 5f11dc014ed6..e5234f953a6d 100644 --- a/drivers/hwmon/jc42.c +++ b/drivers/hwmon/jc42.c @@ -22,6 +22,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include #include #include #include @@ -45,6 +46,7 @@ static const unsigned short normal_i2c[] = { #define JC42_REG_TEMP 0x05 #define JC42_REG_MANID 0x06 #define JC42_REG_DEVICEID 0x07 +#define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */ /* Status bits in temperature register */ #define JC42_ALARM_CRIT_BIT 15 @@ -75,6 +77,9 @@ static const unsigned short normal_i2c[] = { #define GT_MANID 0x1c68 /* Giantec */ #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */ +/* SMBUS register */ +#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */ + /* Supported chips */ /* Analog Devices */ @@ -495,6 +500,22 @@ static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id) data->extended = !!(cap & JC42_CAP_RANGE); + if (device_property_read_bool(dev, "smbus-timeout-disable")) { + int smbus; + + /* + * Not all chips support this register, but from a + * quick read of various datasheets no chip appears + * incompatible with the below attempt to disable + * the timeout. And the whole thing is opt-in... + */ + smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS); + if (smbus < 0) + return smbus; + i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS, + smbus | SMBUS_STMOUT); + } + config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); if (config < 0) return config; -- cgit v1.2.3