From e58dfab6063bef96d0f5293e07d4a4448255861d Mon Sep 17 00:00:00 2001
From: Paul Handrigan <Paul.Handrigan@cirrus.com>
Date: Wed, 12 Oct 2016 13:53:29 -0500
Subject: ASoC: cs35l34: Add device tree bindings file for cs35l34
Add device tree bindings file for the cs35l34 8V boosted
class D amplifier.
Signed-off-by: Paul Handrigan <Paul.Handrigan@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/cs35l34.txt | 64 ++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/cs35l34.txt
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/cs35l34.txt b/Documentation/devicetree/bindings/sound/cs35l34.txt
new file mode 100644
index 000000000000..b218ead2e68e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs35l34.txt
@@ -0,0 +1,64 @@
+CS35L34 Speaker Amplifier
+
+Required properties:
+
+ - compatible : "cirrus,cs35l34"
+
+ - reg : the I2C address of the device for I2C.
+
+ - VA-supply, VP-supply : power supplies for the device,
+ as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+ - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost
+ converter's output voltage in mV. The range is from VP to 8V with
+ increments of 100mV.
+
+ - cirrus,boost-nanohenry: Inductor value for boost converter. The value is
+ in nH and they can be values of 1000nH, 1100nH, 1200nH, 1500nH, and 2200nH.
+
+Optional properties:
+
+ - reset-gpios: GPIO used to reset the amplifier.
+
+ - interrupt-parent : Specifies the phandle of the interrupt controller to
+ which the IRQs from CS35L34 are delivered to.
+ - interrupts : IRQ line info CS35L34.
+ (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+ for further information relating to interrupt properties)
+
+ - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The
+ range starts at 1200mA and goes to a maximum of 3840mA with increments of
+ 80mA. The default value is 2480mA.
+
+ - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the
+ received mono data is in the left or right portion of the I2S frame
+ according to the AD0 pin or directly via this configuration.
+ 0x0 (Default) = Selected by AD0 input (if AD0 = LOW, use left channel),
+ 0x2 = Left,
+ 0x1 = Selected by the inversion of the AD0 input (if AD0 = LOW, use right
+ channel),
+ 0x3 = Right.
+
+ - cirrus,gain-zc-disable: Boolean property. If set, the gain change will take
+ effect without waiting for a zero cross.
+
+ - cirrus,tdm-rising-edge: Boolean property. If set, data is on the rising edge of
+ SCLK. Otherwise, data is on the falling edge of SCLK.
+
+
+Example:
+
+cs35l34: cs35l34@40 {
+ compatible = "cirrus,cs35l34";
+ reg = <0x40>;
+
+ interrupt-parent = <&gpio8>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&gpio 10 0>;
+
+ cirrus,boost-vtge-milltvolt = <8000>; /* 8V */
+ cirrus,boost-ind-nanohenry = <1000>; /* 1uH */
+ cirrus,boost-peak-milliamp = <3000>; /* 3A */
+};
--
cgit v1.2.3
From a545f5d859c7988ab61850395a4565bfe507dc0a Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 21 Oct 2016 10:51:15 +0200
Subject: ASoC: davinci-mcbsp: DT fix s/interrupts-names/interrupt-names/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/davinci-mcbsp.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
index 55b53e1fd72c..e0b6165c9cfc 100644
--- a/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
+++ b/Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
@@ -43,7 +43,7 @@ mcbsp0: mcbsp@1d10000 {
<0x00310000 0x1000>;
reg-names = "mpu", "dat";
interrupts = <97 98>;
- interrupts-names = "rx", "tx";
+ interrupt-names = "rx", "tx";
dmas = <&edma0 3 1
&edma0 2 1>;
dma-names = "tx", "rx";
--
cgit v1.2.3
From 73444723b2b5b53ca2759daeecda90c9c7fa3629 Mon Sep 17 00:00:00 2001
From: Bard Liao <bardliao@realtek.com>
Date: Fri, 21 Oct 2016 11:02:28 +0800
Subject: ASoC: rt5663: rename rt5668 as rt5663 v2
The "rt5668" codec supported in this driver is actually a revision
of "rt5663". So the patch is renamed to "rt5663 v2"
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/rt5663.txt | 6 +-
sound/soc/codecs/rt5663.c | 1130 ++++++++++---------
sound/soc/codecs/rt5663.h | 1154 ++++++++++----------
3 files changed, 1140 insertions(+), 1150 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt
index 7d3c974c6e2e..70eaeaed2b18 100644
--- a/Documentation/devicetree/bindings/sound/rt5663.txt
+++ b/Documentation/devicetree/bindings/sound/rt5663.txt
@@ -1,10 +1,10 @@
-RT5663/RT5668 audio CODEC
+RT5663 audio CODEC
This device supports I2C only.
Required properties:
-- compatible : One of "realtek,rt5663" or "realtek,rt5668".
+- compatible : "realtek,rt5663".
- reg : The I2C address of the device.
@@ -12,7 +12,7 @@ Required properties:
Optional properties:
-Pins on the device (for linking into audio routes) for RT5663/RT5668:
+Pins on the device (for linking into audio routes) for RT5663:
* IN1P
* IN1N
diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c
index f30e0b461602..ff968d93f31f 100644
--- a/sound/soc/codecs/rt5663.c
+++ b/sound/soc/codecs/rt5663.c
@@ -1,5 +1,5 @@
/*
- * rt5663.c -- RT5668/RT5663 ALSA SoC audio codec driver
+ * rt5663.c -- RT5663 ALSA SoC audio codec driver
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Jack Yu <jack.yu@realtek.com>
@@ -30,12 +30,12 @@
#include "rt5663.h"
#include "rl6231.h"
-#define RT5668_DEVICE_ID 0x6451
-#define RT5663_DEVICE_ID 0x6406
+#define RT5663_DEVICE_ID_2 0x6451
+#define RT5663_DEVICE_ID_1 0x6406
enum {
- CODEC_TYPE_RT5668,
- CODEC_TYPE_RT5663,
+ CODEC_VER_1,
+ CODEC_VER_0,
};
struct rt5663_priv {
@@ -45,7 +45,7 @@ struct rt5663_priv {
struct snd_soc_jack *hs_jack;
struct timer_list btn_check_timer;
- int codec_type;
+ int codec_ver;
int sysclk;
int sysclk_src;
int lrck;
@@ -57,7 +57,7 @@ struct rt5663_priv {
int jack_type;
};
-static const struct reg_default rt5668_reg[] = {
+static const struct reg_default rt5663_v2_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0001, 0xc8c8 },
{ 0x0002, 0x8080 },
@@ -730,7 +730,7 @@ static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5663_INT_ST_2:
- case RT5663_GPIO_STA:
+ case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
@@ -846,7 +846,7 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
case RT5663_INT_ST_2:
case RT5663_GPIO_1:
case RT5663_GPIO_2:
- case RT5663_GPIO_STA:
+ case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
@@ -1036,23 +1036,23 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
}
}
-static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
+static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_RESET:
- case RT5668_CBJ_TYPE_2:
- case RT5668_PDM_OUT_CTL:
- case RT5668_PDM_I2C_DATA_CTL1:
- case RT5668_PDM_I2C_DATA_CTL4:
- case RT5668_ALC_BK_GAIN:
+ case RT5663_CBJ_TYPE_2:
+ case RT5663_PDM_OUT_CTL:
+ case RT5663_PDM_I2C_DATA_CTL1:
+ case RT5663_PDM_I2C_DATA_CTL4:
+ case RT5663_ALC_BK_GAIN:
case RT5663_PLL_2:
case RT5663_MICBIAS_1:
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
- case RT5668_GPIO_STA:
+ case RT5663_GPIO_STA2:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
- case RT5668_A_JD_CTRL:
+ case RT5663_A_JD_CTRL:
case RT5663_JD_CTRL2:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
@@ -1061,15 +1061,15 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
case RT5663_STO_DRE_5:
case RT5663_STO_DRE_6:
case RT5663_STO_DRE_7:
- case RT5668_MONO_DYNA_6:
- case RT5668_STO1_SIL_DET:
- case RT5668_MONOL_SIL_DET:
- case RT5668_MONOR_SIL_DET:
- case RT5668_STO2_DAC_SIL:
- case RT5668_MONO_AMP_CAL_ST1:
- case RT5668_MONO_AMP_CAL_ST2:
- case RT5668_MONO_AMP_CAL_ST3:
- case RT5668_MONO_AMP_CAL_ST4:
+ case RT5663_MONO_DYNA_6:
+ case RT5663_STO1_SIL_DET:
+ case RT5663_MONOL_SIL_DET:
+ case RT5663_MONOR_SIL_DET:
+ case RT5663_STO2_DAC_SIL:
+ case RT5663_MONO_AMP_CAL_ST1:
+ case RT5663_MONO_AMP_CAL_ST2:
+ case RT5663_MONO_AMP_CAL_ST3:
+ case RT5663_MONO_AMP_CAL_ST4:
case RT5663_HP_IMP_SEN_2:
case RT5663_HP_IMP_SEN_3:
case RT5663_HP_IMP_SEN_4:
@@ -1083,218 +1083,218 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
case RT5663_HP_CALIB_ST7:
case RT5663_HP_CALIB_ST8:
case RT5663_HP_CALIB_ST9:
- case RT5668_HP_CALIB_ST10:
- case RT5668_HP_CALIB_ST11:
+ case RT5663_HP_CALIB_ST10:
+ case RT5663_HP_CALIB_ST11:
return true;
default:
return false;
}
}
-static bool rt5668_readable_register(struct device *dev, unsigned int reg)
+static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
- case RT5668_LOUT_CTRL:
- case RT5668_HP_AMP_2:
- case RT5668_MONO_OUT:
- case RT5668_MONO_GAIN:
- case RT5668_AEC_BST:
- case RT5668_IN1_IN2:
- case RT5668_IN3_IN4:
- case RT5668_INL1_INR1:
- case RT5668_CBJ_TYPE_2:
- case RT5668_CBJ_TYPE_3:
- case RT5668_CBJ_TYPE_4:
- case RT5668_CBJ_TYPE_5:
- case RT5668_CBJ_TYPE_8:
- case RT5668_DAC3_DIG_VOL:
- case RT5668_DAC3_CTRL:
- case RT5668_MONO_ADC_DIG_VOL:
- case RT5668_STO2_ADC_DIG_VOL:
- case RT5668_MONO_ADC_BST_GAIN:
- case RT5668_STO2_ADC_BST_GAIN:
- case RT5668_SIDETONE_CTRL:
- case RT5668_MONO1_ADC_MIXER:
- case RT5668_STO2_ADC_MIXER:
- case RT5668_MONO_DAC_MIXER:
- case RT5668_DAC2_SRC_CTRL:
- case RT5668_IF_3_4_DATA_CTL:
- case RT5668_IF_5_DATA_CTL:
- case RT5668_PDM_OUT_CTL:
- case RT5668_PDM_I2C_DATA_CTL1:
- case RT5668_PDM_I2C_DATA_CTL2:
- case RT5668_PDM_I2C_DATA_CTL3:
- case RT5668_PDM_I2C_DATA_CTL4:
- case RT5668_RECMIX1_NEW:
- case RT5668_RECMIX1L_0:
- case RT5668_RECMIX1L:
- case RT5668_RECMIX1R_0:
- case RT5668_RECMIX1R:
- case RT5668_RECMIX2_NEW:
- case RT5668_RECMIX2_L_2:
- case RT5668_RECMIX2_R:
- case RT5668_RECMIX2_R_2:
- case RT5668_CALIB_REC_LR:
- case RT5668_ALC_BK_GAIN:
- case RT5668_MONOMIX_GAIN:
- case RT5668_MONOMIX_IN_GAIN:
- case RT5668_OUT_MIXL_GAIN:
- case RT5668_OUT_LMIX_IN_GAIN:
- case RT5668_OUT_RMIX_IN_GAIN:
- case RT5668_OUT_RMIX_IN_GAIN1:
- case RT5668_LOUT_MIXER_CTRL:
- case RT5668_PWR_VOL:
- case RT5668_ADCDAC_RST:
- case RT5668_I2S34_SDP:
- case RT5668_I2S5_SDP:
- case RT5668_TDM_5:
- case RT5668_TDM_6:
- case RT5668_TDM_7:
- case RT5668_TDM_8:
- case RT5668_ASRC_3:
- case RT5668_ASRC_6:
- case RT5668_ASRC_7:
- case RT5668_PLL_TRK_13:
- case RT5668_I2S_M_CLK_CTL:
- case RT5668_FDIV_I2S34_M_CLK:
- case RT5668_FDIV_I2S34_M_CLK2:
- case RT5668_FDIV_I2S5_M_CLK:
- case RT5668_FDIV_I2S5_M_CLK2:
- case RT5668_IRQ_4:
- case RT5668_GPIO_3:
- case RT5668_GPIO_4:
- case RT5668_GPIO_STA:
- case RT5668_HP_AMP_DET1:
- case RT5668_HP_AMP_DET2:
- case RT5668_HP_AMP_DET3:
- case RT5668_MID_BD_HP_AMP:
- case RT5668_LOW_BD_HP_AMP:
- case RT5668_SOF_VOL_ZC2:
- case RT5668_ADC_STO2_ADJ1:
- case RT5668_ADC_STO2_ADJ2:
- case RT5668_A_JD_CTRL:
- case RT5668_JD1_TRES_CTRL:
- case RT5668_JD2_TRES_CTRL:
- case RT5668_JD_CTRL2:
- case RT5668_DUM_REG_2:
- case RT5668_DUM_REG_3:
+ case RT5663_LOUT_CTRL:
+ case RT5663_HP_AMP_2:
+ case RT5663_MONO_OUT:
+ case RT5663_MONO_GAIN:
+ case RT5663_AEC_BST:
+ case RT5663_IN1_IN2:
+ case RT5663_IN3_IN4:
+ case RT5663_INL1_INR1:
+ case RT5663_CBJ_TYPE_2:
+ case RT5663_CBJ_TYPE_3:
+ case RT5663_CBJ_TYPE_4:
+ case RT5663_CBJ_TYPE_5:
+ case RT5663_CBJ_TYPE_8:
+ case RT5663_DAC3_DIG_VOL:
+ case RT5663_DAC3_CTRL:
+ case RT5663_MONO_ADC_DIG_VOL:
+ case RT5663_STO2_ADC_DIG_VOL:
+ case RT5663_MONO_ADC_BST_GAIN:
+ case RT5663_STO2_ADC_BST_GAIN:
+ case RT5663_SIDETONE_CTRL:
+ case RT5663_MONO1_ADC_MIXER:
+ case RT5663_STO2_ADC_MIXER:
+ case RT5663_MONO_DAC_MIXER:
+ case RT5663_DAC2_SRC_CTRL:
+ case RT5663_IF_3_4_DATA_CTL:
+ case RT5663_IF_5_DATA_CTL:
+ case RT5663_PDM_OUT_CTL:
+ case RT5663_PDM_I2C_DATA_CTL1:
+ case RT5663_PDM_I2C_DATA_CTL2:
+ case RT5663_PDM_I2C_DATA_CTL3:
+ case RT5663_PDM_I2C_DATA_CTL4:
+ case RT5663_RECMIX1_NEW:
+ case RT5663_RECMIX1L_0:
+ case RT5663_RECMIX1L:
+ case RT5663_RECMIX1R_0:
+ case RT5663_RECMIX1R:
+ case RT5663_RECMIX2_NEW:
+ case RT5663_RECMIX2_L_2:
+ case RT5663_RECMIX2_R:
+ case RT5663_RECMIX2_R_2:
+ case RT5663_CALIB_REC_LR:
+ case RT5663_ALC_BK_GAIN:
+ case RT5663_MONOMIX_GAIN:
+ case RT5663_MONOMIX_IN_GAIN:
+ case RT5663_OUT_MIXL_GAIN:
+ case RT5663_OUT_LMIX_IN_GAIN:
+ case RT5663_OUT_RMIX_IN_GAIN:
+ case RT5663_OUT_RMIX_IN_GAIN1:
+ case RT5663_LOUT_MIXER_CTRL:
+ case RT5663_PWR_VOL:
+ case RT5663_ADCDAC_RST:
+ case RT5663_I2S34_SDP:
+ case RT5663_I2S5_SDP:
+ case RT5663_TDM_6:
+ case RT5663_TDM_7:
+ case RT5663_TDM_8:
+ case RT5663_TDM_9:
+ case RT5663_ASRC_3:
+ case RT5663_ASRC_6:
+ case RT5663_ASRC_7:
+ case RT5663_PLL_TRK_13:
+ case RT5663_I2S_M_CLK_CTL:
+ case RT5663_FDIV_I2S34_M_CLK:
+ case RT5663_FDIV_I2S34_M_CLK2:
+ case RT5663_FDIV_I2S5_M_CLK:
+ case RT5663_FDIV_I2S5_M_CLK2:
+ case RT5663_V2_IRQ_4:
+ case RT5663_GPIO_3:
+ case RT5663_GPIO_4:
+ case RT5663_GPIO_STA2:
+ case RT5663_HP_AMP_DET1:
+ case RT5663_HP_AMP_DET2:
+ case RT5663_HP_AMP_DET3:
+ case RT5663_MID_BD_HP_AMP:
+ case RT5663_LOW_BD_HP_AMP:
+ case RT5663_SOF_VOL_ZC2:
+ case RT5663_ADC_STO2_ADJ1:
+ case RT5663_ADC_STO2_ADJ2:
+ case RT5663_A_JD_CTRL:
+ case RT5663_JD1_TRES_CTRL:
+ case RT5663_JD2_TRES_CTRL:
+ case RT5663_V2_JD_CTRL2:
+ case RT5663_DUM_REG_2:
+ case RT5663_DUM_REG_3:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
- case RT5668_DACADC_DIG_VOL2:
- case RT5668_DIG_IN_PIN2:
- case RT5668_PAD_DRV_CTL1:
- case RT5668_SOF_RAM_DEPOP:
- case RT5668_VOL_TEST:
- case RT5668_TEST_MODE_3:
- case RT5668_TEST_MODE_4:
+ case RT5663_DACADC_DIG_VOL2:
+ case RT5663_DIG_IN_PIN2:
+ case RT5663_PAD_DRV_CTL1:
+ case RT5663_SOF_RAM_DEPOP:
+ case RT5663_VOL_TEST:
+ case RT5663_TEST_MODE_4:
+ case RT5663_TEST_MODE_5:
case RT5663_STO_DRE_9:
- case RT5668_MONO_DYNA_1:
- case RT5668_MONO_DYNA_2:
- case RT5668_MONO_DYNA_3:
- case RT5668_MONO_DYNA_4:
- case RT5668_MONO_DYNA_5:
- case RT5668_MONO_DYNA_6:
- case RT5668_STO1_SIL_DET:
- case RT5668_MONOL_SIL_DET:
- case RT5668_MONOR_SIL_DET:
- case RT5668_STO2_DAC_SIL:
- case RT5668_PWR_SAV_CTL1:
- case RT5668_PWR_SAV_CTL2:
- case RT5668_PWR_SAV_CTL3:
- case RT5668_PWR_SAV_CTL4:
- case RT5668_PWR_SAV_CTL5:
- case RT5668_PWR_SAV_CTL6:
- case RT5668_MONO_AMP_CAL1:
- case RT5668_MONO_AMP_CAL2:
- case RT5668_MONO_AMP_CAL3:
- case RT5668_MONO_AMP_CAL4:
- case RT5668_MONO_AMP_CAL5:
- case RT5668_MONO_AMP_CAL6:
- case RT5668_MONO_AMP_CAL7:
- case RT5668_MONO_AMP_CAL_ST1:
- case RT5668_MONO_AMP_CAL_ST2:
- case RT5668_MONO_AMP_CAL_ST3:
- case RT5668_MONO_AMP_CAL_ST4:
- case RT5668_MONO_AMP_CAL_ST5:
- case RT5668_HP_IMP_SEN_13:
- case RT5668_HP_IMP_SEN_14:
- case RT5668_HP_IMP_SEN_6:
- case RT5668_HP_IMP_SEN_7:
- case RT5668_HP_IMP_SEN_8:
- case RT5668_HP_IMP_SEN_9:
- case RT5668_HP_IMP_SEN_10:
- case RT5668_HP_LOGIC_3:
- case RT5668_HP_CALIB_ST10:
- case RT5668_HP_CALIB_ST11:
- case RT5668_PRO_REG_TBL_4:
- case RT5668_PRO_REG_TBL_5:
- case RT5668_PRO_REG_TBL_6:
- case RT5668_PRO_REG_TBL_7:
- case RT5668_PRO_REG_TBL_8:
- case RT5668_PRO_REG_TBL_9:
- case RT5668_SAR_ADC_INL_1:
- case RT5668_SAR_ADC_INL_2:
- case RT5668_SAR_ADC_INL_3:
- case RT5668_SAR_ADC_INL_4:
- case RT5668_SAR_ADC_INL_5:
- case RT5668_SAR_ADC_INL_6:
- case RT5668_SAR_ADC_INL_7:
- case RT5668_SAR_ADC_INL_8:
- case RT5668_SAR_ADC_INL_9:
- case RT5668_SAR_ADC_INL_10:
- case RT5668_SAR_ADC_INL_11:
- case RT5668_SAR_ADC_INL_12:
- case RT5668_DRC_CTRL_1:
- case RT5668_DRC1_CTRL_2:
- case RT5668_DRC1_CTRL_3:
- case RT5668_DRC1_CTRL_4:
- case RT5668_DRC1_CTRL_5:
- case RT5668_DRC1_CTRL_6:
- case RT5668_DRC1_HD_CTRL_1:
- case RT5668_DRC1_HD_CTRL_2:
- case RT5668_DRC1_PRI_REG_1:
- case RT5668_DRC1_PRI_REG_2:
- case RT5668_DRC1_PRI_REG_3:
- case RT5668_DRC1_PRI_REG_4:
- case RT5668_DRC1_PRI_REG_5:
- case RT5668_DRC1_PRI_REG_6:
- case RT5668_DRC1_PRI_REG_7:
- case RT5668_DRC1_PRI_REG_8:
- case RT5668_ALC_PGA_CTL_1:
- case RT5668_ALC_PGA_CTL_2:
- case RT5668_ALC_PGA_CTL_3:
- case RT5668_ALC_PGA_CTL_4:
- case RT5668_ALC_PGA_CTL_5:
- case RT5668_ALC_PGA_CTL_6:
- case RT5668_ALC_PGA_CTL_7:
- case RT5668_ALC_PGA_CTL_8:
- case RT5668_ALC_PGA_REG_1:
- case RT5668_ALC_PGA_REG_2:
- case RT5668_ALC_PGA_REG_3:
- case RT5668_ADC_EQ_RECOV_1:
- case RT5668_ADC_EQ_RECOV_2:
- case RT5668_ADC_EQ_RECOV_3:
- case RT5668_ADC_EQ_RECOV_4:
- case RT5668_ADC_EQ_RECOV_5:
- case RT5668_ADC_EQ_RECOV_6:
- case RT5668_ADC_EQ_RECOV_7:
- case RT5668_ADC_EQ_RECOV_8:
- case RT5668_ADC_EQ_RECOV_9:
- case RT5668_ADC_EQ_RECOV_10:
- case RT5668_ADC_EQ_RECOV_11:
- case RT5668_ADC_EQ_RECOV_12:
- case RT5668_ADC_EQ_RECOV_13:
- case RT5668_VID_HIDDEN:
- case RT5668_VID_CUSTOMER:
- case RT5668_SCAN_MODE:
- case RT5668_I2C_BYPA:
+ case RT5663_MONO_DYNA_1:
+ case RT5663_MONO_DYNA_2:
+ case RT5663_MONO_DYNA_3:
+ case RT5663_MONO_DYNA_4:
+ case RT5663_MONO_DYNA_5:
+ case RT5663_MONO_DYNA_6:
+ case RT5663_STO1_SIL_DET:
+ case RT5663_MONOL_SIL_DET:
+ case RT5663_MONOR_SIL_DET:
+ case RT5663_STO2_DAC_SIL:
+ case RT5663_PWR_SAV_CTL1:
+ case RT5663_PWR_SAV_CTL2:
+ case RT5663_PWR_SAV_CTL3:
+ case RT5663_PWR_SAV_CTL4:
+ case RT5663_PWR_SAV_CTL5:
+ case RT5663_PWR_SAV_CTL6:
+ case RT5663_MONO_AMP_CAL1:
+ case RT5663_MONO_AMP_CAL2:
+ case RT5663_MONO_AMP_CAL3:
+ case RT5663_MONO_AMP_CAL4:
+ case RT5663_MONO_AMP_CAL5:
+ case RT5663_MONO_AMP_CAL6:
+ case RT5663_MONO_AMP_CAL7:
+ case RT5663_MONO_AMP_CAL_ST1:
+ case RT5663_MONO_AMP_CAL_ST2:
+ case RT5663_MONO_AMP_CAL_ST3:
+ case RT5663_MONO_AMP_CAL_ST4:
+ case RT5663_MONO_AMP_CAL_ST5:
+ case RT5663_V2_HP_IMP_SEN_13:
+ case RT5663_V2_HP_IMP_SEN_14:
+ case RT5663_V2_HP_IMP_SEN_6:
+ case RT5663_V2_HP_IMP_SEN_7:
+ case RT5663_V2_HP_IMP_SEN_8:
+ case RT5663_V2_HP_IMP_SEN_9:
+ case RT5663_V2_HP_IMP_SEN_10:
+ case RT5663_HP_LOGIC_3:
+ case RT5663_HP_CALIB_ST10:
+ case RT5663_HP_CALIB_ST11:
+ case RT5663_PRO_REG_TBL_4:
+ case RT5663_PRO_REG_TBL_5:
+ case RT5663_PRO_REG_TBL_6:
+ case RT5663_PRO_REG_TBL_7:
+ case RT5663_PRO_REG_TBL_8:
+ case RT5663_PRO_REG_TBL_9:
+ case RT5663_SAR_ADC_INL_1:
+ case RT5663_SAR_ADC_INL_2:
+ case RT5663_SAR_ADC_INL_3:
+ case RT5663_SAR_ADC_INL_4:
+ case RT5663_SAR_ADC_INL_5:
+ case RT5663_SAR_ADC_INL_6:
+ case RT5663_SAR_ADC_INL_7:
+ case RT5663_SAR_ADC_INL_8:
+ case RT5663_SAR_ADC_INL_9:
+ case RT5663_SAR_ADC_INL_10:
+ case RT5663_SAR_ADC_INL_11:
+ case RT5663_SAR_ADC_INL_12:
+ case RT5663_DRC_CTRL_1:
+ case RT5663_DRC1_CTRL_2:
+ case RT5663_DRC1_CTRL_3:
+ case RT5663_DRC1_CTRL_4:
+ case RT5663_DRC1_CTRL_5:
+ case RT5663_DRC1_CTRL_6:
+ case RT5663_DRC1_HD_CTRL_1:
+ case RT5663_DRC1_HD_CTRL_2:
+ case RT5663_DRC1_PRI_REG_1:
+ case RT5663_DRC1_PRI_REG_2:
+ case RT5663_DRC1_PRI_REG_3:
+ case RT5663_DRC1_PRI_REG_4:
+ case RT5663_DRC1_PRI_REG_5:
+ case RT5663_DRC1_PRI_REG_6:
+ case RT5663_DRC1_PRI_REG_7:
+ case RT5663_DRC1_PRI_REG_8:
+ case RT5663_ALC_PGA_CTL_1:
+ case RT5663_ALC_PGA_CTL_2:
+ case RT5663_ALC_PGA_CTL_3:
+ case RT5663_ALC_PGA_CTL_4:
+ case RT5663_ALC_PGA_CTL_5:
+ case RT5663_ALC_PGA_CTL_6:
+ case RT5663_ALC_PGA_CTL_7:
+ case RT5663_ALC_PGA_CTL_8:
+ case RT5663_ALC_PGA_REG_1:
+ case RT5663_ALC_PGA_REG_2:
+ case RT5663_ALC_PGA_REG_3:
+ case RT5663_ADC_EQ_RECOV_1:
+ case RT5663_ADC_EQ_RECOV_2:
+ case RT5663_ADC_EQ_RECOV_3:
+ case RT5663_ADC_EQ_RECOV_4:
+ case RT5663_ADC_EQ_RECOV_5:
+ case RT5663_ADC_EQ_RECOV_6:
+ case RT5663_ADC_EQ_RECOV_7:
+ case RT5663_ADC_EQ_RECOV_8:
+ case RT5663_ADC_EQ_RECOV_9:
+ case RT5663_ADC_EQ_RECOV_10:
+ case RT5663_ADC_EQ_RECOV_11:
+ case RT5663_ADC_EQ_RECOV_12:
+ case RT5663_ADC_EQ_RECOV_13:
+ case RT5663_VID_HIDDEN:
+ case RT5663_VID_CUSTOMER:
+ case RT5663_SCAN_MODE:
+ case RT5663_I2C_BYPA:
return true;
case RT5663_TDM_1:
case RT5663_DEPOP_3:
case RT5663_ASRC_11_2:
case RT5663_INT_ST_2:
- case RT5663_GPIO_STA:
+ case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
@@ -1344,7 +1344,7 @@ static bool rt5668_readable_register(struct device *dev, unsigned int reg)
}
static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
-static const DECLARE_TLV_DB_SCALE(rt5668_hp_vol_tlv, -2250, 150, 0);
+static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
@@ -1374,57 +1374,57 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
if (enable) {
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
- RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_EN);
+ RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
/* reset in-line command */
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
- RT5668_RESET_4BTN_INL_MASK,
- RT5668_RESET_4BTN_INL_RESET);
+ RT5663_RESET_4BTN_INL_MASK,
+ RT5663_RESET_4BTN_INL_RESET);
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
- RT5668_RESET_4BTN_INL_MASK,
- RT5668_RESET_4BTN_INL_NOR);
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
+ RT5663_RESET_4BTN_INL_MASK,
+ RT5663_RESET_4BTN_INL_NOR);
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
snd_soc_update_bits(codec, RT5663_IRQ_3,
- RT5668_EN_IRQ_INLINE_MASK,
- RT5668_EN_IRQ_INLINE_NOR);
+ RT5663_V2_EN_IRQ_INLINE_MASK,
+ RT5663_V2_EN_IRQ_INLINE_NOR);
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
snd_soc_update_bits(codec, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_NOR);
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
}
} else {
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
snd_soc_update_bits(codec, RT5663_IRQ_3,
- RT5668_EN_IRQ_INLINE_MASK,
- RT5668_EN_IRQ_INLINE_BYP);
+ RT5663_V2_EN_IRQ_INLINE_MASK,
+ RT5663_V2_EN_IRQ_INLINE_BYP);
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
snd_soc_update_bits(codec, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_BYP);
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
}
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
- RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_DIS);
+ RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
/* reset in-line command */
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
- RT5668_RESET_4BTN_INL_MASK,
- RT5668_RESET_4BTN_INL_RESET);
+ RT5663_RESET_4BTN_INL_MASK,
+ RT5663_RESET_4BTN_INL_RESET);
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
- RT5668_RESET_4BTN_INL_MASK,
- RT5668_RESET_4BTN_INL_NOR);
+ RT5663_RESET_4BTN_INL_MASK,
+ RT5663_RESET_4BTN_INL_NOR);
}
}
/**
- * rt5668_jack_detect - Detect headset.
+ * rt5663_v2_jack_detect - Detect headset.
* @codec: SoC audio codec device.
* @jack_insert: Jack insert or not.
*
@@ -1433,16 +1433,16 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
* Returns detect status.
*/
-static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
+static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
{
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
- struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
+ struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
if (jack_insert) {
- snd_soc_write(codec, RT5668_CBJ_TYPE_2, 0x8040);
- snd_soc_write(codec, RT5668_CBJ_TYPE_3, 0x1484);
+ snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
+ snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
@@ -1450,12 +1450,12 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
snd_soc_update_bits(codec, RT5663_RC_CLK,
- RT5668_DIG_1M_CLK_MASK, RT5668_DIG_1M_CLK_EN);
+ RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
while (i < 5) {
msleep(sleep_time[i]);
- val = snd_soc_read(codec, RT5668_CBJ_TYPE_2) & 0x0003;
+ val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
if (val == 0x1 || val == 0x2 || val == 0x3)
break;
dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
@@ -1466,7 +1466,7 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
switch (val) {
case 1:
case 2:
- rt5668->jack_type = SND_JACK_HEADSET;
+ rt5663->jack_type = SND_JACK_HEADSET;
rt5663_enable_push_button_irq(codec, true);
break;
default:
@@ -1475,13 +1475,13 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
- rt5668->jack_type = SND_JACK_HEADPHONE;
+ rt5663->jack_type = SND_JACK_HEADPHONE;
break;
}
} else {
snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
- if (rt5668->jack_type == SND_JACK_HEADSET) {
+ if (rt5663->jack_type == SND_JACK_HEADSET) {
rt5663_enable_push_button_irq(codec, false);
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
@@ -1489,11 +1489,11 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
}
- rt5668->jack_type = 0;
+ rt5663->jack_type = 0;
}
- dev_dbg(codec->dev, "jack_type = %d\n", rt5668->jack_type);
- return rt5668->jack_type;
+ dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
+ return rt5663->jack_type;
}
/**
@@ -1514,11 +1514,11 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
if (jack_insert) {
snd_soc_update_bits(codec, RT5663_DIG_MISC,
- RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
+ RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
- RT5663_SI_HP_MASK | RT5668_OSW_HP_L_MASK |
- RT5668_OSW_HP_R_MASK, RT5663_SI_HP_EN |
- RT5668_OSW_HP_L_DIS | RT5668_OSW_HP_R_DIS);
+ RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
+ RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
+ RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
snd_soc_update_bits(codec, RT5663_DUMMY_1,
RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
@@ -1530,17 +1530,17 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
/* BST1 power on for JD */
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
- RT5668_PWR_BST1_MASK, RT5668_PWR_BST1_ON);
+ RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
- RT5668_PWR_MB_MASK | RT5668_LDO1_DVO_MASK |
- RT5668_AMP_HP_MASK, RT5668_PWR_MB |
- RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
+ RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
+ RT5663_AMP_HP_MASK, RT5663_PWR_MB |
+ RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
- RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
+ RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
snd_soc_update_bits(codec, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
while (i < 5) {
@@ -1619,13 +1619,13 @@ static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
/* JD1 */
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
return !(val & 0x2000);
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
return !(val & 0x1000);
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
}
return false;
@@ -1645,15 +1645,16 @@ static void rt5663_jack_detect_work(struct work_struct *work)
/* jack in */
if (rt5663->jack_type == 0) {
/* jack was out, report jack type */
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
- report = rt5668_jack_detect(rt5663->codec, 1);
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
+ report = rt5663_v2_jack_detect(
+ rt5663->codec, 1);
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->codec, 1);
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
}
} else {
/* jack is already in, report button event */
@@ -1702,15 +1703,15 @@ static void rt5663_jack_detect_work(struct work_struct *work)
}
} else {
/* jack out */
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
- report = rt5668_jack_detect(rt5663->codec, 0);
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
+ report = rt5663_v2_jack_detect(rt5663->codec, 0);
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->codec, 0);
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
}
}
dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
@@ -1722,24 +1723,24 @@ static void rt5663_jack_detect_work(struct work_struct *work)
static const struct snd_kcontrol_new rt5663_snd_controls[] = {
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
- RT5668_DAC_L1_VOL_SHIFT + 1, RT5668_DAC_R1_VOL_SHIFT + 1,
+ RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
87, 0, dac_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
- RT5668_ADC_L_MUTE_SHIFT, RT5668_ADC_R_MUTE_SHIFT, 1, 1),
+ RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
- RT5668_ADC_L_VOL_SHIFT + 1, RT5668_ADC_R_VOL_SHIFT + 1,
+ RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
63, 0, adc_vol_tlv),
};
-static const struct snd_kcontrol_new rt5668_specific_controls[] = {
+static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
- RT5663_HP_RCH_DRE, RT5668_GAIN_HP_SHIFT, 15, 1,
- rt5668_hp_vol_tlv),
+ RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
+ rt5663_v2_hp_vol_tlv),
/* Mic Boost Volume */
- SOC_SINGLE_TLV("IN1 Capture Volume", RT5668_AEC_BST,
- RT5668_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
+ SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
+ RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
};
static const struct snd_kcontrol_new rt5663_specific_controls[] = {
@@ -1775,15 +1776,15 @@ static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
- if (rt5663->codec_type == CODEC_TYPE_RT5668) {
+ if (rt5663->codec_ver == CODEC_VER_1) {
switch (w->shift) {
- case RT5668_ADC_STO1_ASRC_SHIFT:
- reg = RT5668_ASRC_3;
- shift = RT5668_AD_STO1_TRACK_SHIFT;
+ case RT5663_ADC_STO1_ASRC_SHIFT:
+ reg = RT5663_ASRC_3;
+ shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
- case RT5668_DAC_STO1_ASRC_SHIFT:
+ case RT5663_DAC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_2;
- shift = RT5668_DA_STO1_TRACK_SHIFT;
+ shift = RT5663_DA_STO1_TRACK_SHIFT;
break;
default:
return 0;
@@ -1820,17 +1821,17 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
- ad_asrc_en = (snd_soc_read(codec, RT5668_ASRC_3) &
- RT5668_AD_STO1_TRACK_MASK) ? 1 : 0;
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
+ ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
+ RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
return 1;
}
@@ -1849,7 +1850,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
* @filter_mask: mask of filters.
* @clk_src: clock source
*
- * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
+ * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
@@ -1860,7 +1861,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
unsigned int filter_mask, unsigned int clk_src)
{
- struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
+ struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
unsigned int asrc3_mask = 0;
@@ -1876,22 +1877,22 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
}
if (filter_mask & RT5663_DA_STEREO_FILTER) {
- asrc2_mask |= RT5668_DA_STO1_TRACK_MASK;
- asrc2_value |= clk_src << RT5668_DA_STO1_TRACK_SHIFT;
+ asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
+ asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
}
if (filter_mask & RT5663_AD_STEREO_FILTER) {
- switch (rt5668->codec_type) {
- case CODEC_TYPE_RT5668:
- asrc3_mask |= RT5668_AD_STO1_TRACK_MASK;
- asrc3_value |= clk_src << RT5668_AD_STO1_TRACK_SHIFT;
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
+ asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
+ asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
}
}
@@ -1900,7 +1901,7 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
asrc2_value);
if (asrc3_mask)
- snd_soc_update_bits(codec, RT5668_ASRC_3, asrc3_mask,
+ snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
asrc3_value);
return 0;
@@ -1908,82 +1909,82 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
/* Analog Mixer */
-static const struct snd_kcontrol_new rt5668_recmix1l[] = {
- SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1L,
- RT5668_RECMIX1L_BST2_SHIFT, 1, 1),
- SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5668_RECMIX1L,
- RT5668_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
+static const struct snd_kcontrol_new rt5663_recmix1l[] = {
+ SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
+ RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
+ RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
};
-static const struct snd_kcontrol_new rt5668_recmix1r[] = {
- SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1R,
- RT5668_RECMIX1R_BST2_SHIFT, 1, 1),
+static const struct snd_kcontrol_new rt5663_recmix1r[] = {
+ SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
+ RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
};
/* Digital Mixer */
static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
- RT5668_M_STO1_ADC_L1_SHIFT, 1, 1),
+ RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
- RT5668_M_STO1_ADC_L2_SHIFT, 1, 1),
+ RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
};
-static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
+static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
- RT5668_M_STO1_ADC_R1_SHIFT, 1, 1),
+ RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
- RT5668_M_STO1_ADC_R2_SHIFT, 1, 1),
+ RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
- RT5668_M_ADCMIX_L_SHIFT, 1, 1),
+ RT5663_M_ADCMIX_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
- RT5668_M_DAC1_L_SHIFT, 1, 1),
+ RT5663_M_DAC1_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
- RT5668_M_ADCMIX_R_SHIFT, 1, 1),
+ RT5663_M_ADCMIX_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
- RT5668_M_DAC1_R_SHIFT, 1, 1),
+ RT5663_M_DAC1_R_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
- RT5668_M_DAC_L1_STO_L_SHIFT, 1, 1),
+ RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
- RT5668_M_DAC_R1_STO_L_SHIFT, 1, 1),
+ RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
- RT5668_M_DAC_L1_STO_R_SHIFT, 1, 1),
+ RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
- RT5668_M_DAC_R1_STO_R_SHIFT, 1, 1),
+ RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
};
/* Out Switch */
-static const struct snd_kcontrol_new rt5668_hpo_switch =
- SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_AMP_2,
- RT5668_EN_DAC_HPO_SHIFT, 1, 0);
+static const struct snd_kcontrol_new rt5663_hpo_switch =
+ SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
+ RT5663_EN_DAC_HPO_SHIFT, 1, 0);
/* Stereo ADC source */
-static const char * const rt5668_sto1_adc_src[] = {
+static const char * const rt5663_sto1_adc_src[] = {
"ADC L", "ADC R"
};
-static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
- RT5668_STO1_ADC_L_SRC_SHIFT, rt5668_sto1_adc_src);
+static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
+ RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
-static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
- SOC_DAPM_ENUM("STO1 ADC L Mux", rt5668_sto1_adcl_enum);
+static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
+ SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
-static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
- RT5668_STO1_ADC_R_SRC_SHIFT, rt5668_sto1_adc_src);
+static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
+ RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
-static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
- SOC_DAPM_ENUM("STO1 ADC R Mux", rt5668_sto1_adcr_enum);
+static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
+ SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
/* RT5663: Analog DACL1 input source */
static const char * const rt5663_alg_dacl_src[] = {
@@ -2015,12 +2016,12 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
- if (rt5663->codec_type == CODEC_TYPE_RT5668) {
+ if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
- RT5668_SEL_PM_HP_SHIFT, RT5668_SEL_PM_HP_HIGH);
+ RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
- RT5668_HP_SIG_SRC1_MASK,
- RT5668_HP_SIG_SRC1_SILENCE);
+ RT5663_HP_SIG_SRC1_MASK,
+ RT5663_HP_SIG_SRC1_SILENCE);
} else {
snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
@@ -2028,7 +2029,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
0x0030);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
- RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_DIS);
+ RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
@@ -2041,14 +2042,14 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
break;
case SND_SOC_DAPM_PRE_PMD:
- if (rt5663->codec_type == CODEC_TYPE_RT5668) {
+ if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
- RT5668_HP_SIG_SRC1_MASK,
- RT5668_HP_SIG_SRC1_REG);
+ RT5663_HP_SIG_SRC1_MASK,
+ RT5663_HP_SIG_SRC1_REG);
} else {
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
- RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_EN);
+ RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
0x000b);
@@ -2062,7 +2063,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
return 0;
}
-static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
+static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
@@ -2070,13 +2071,13 @@ static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
- RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK,
- RT5668_PWR_BST2 | RT5668_PWR_BST2_OP);
+ RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
+ RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
- RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 0);
+ RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
break;
default:
@@ -2110,14 +2111,14 @@ static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
}
static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
- SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5668_PWR_PLL_SHIFT, 0,
+ SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
NULL, 0),
/* micbias */
SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
- RT5668_PWR_MB1_SHIFT, 0),
+ RT5663_PWR_MB1_SHIFT, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
- RT5668_PWR_MB2_SHIFT, 0),
+ RT5663_PWR_MB2_SHIFT, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN1P"),
@@ -2125,14 +2126,14 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* REC Mixer Power */
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
- RT5668_PWR_RECMIX1_SHIFT, 0, NULL, 0),
+ RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
- RT5668_PWR_ADC_L1_SHIFT, 0, NULL, 0),
+ RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
- RT5668_CKGEN_ADCC_SHIFT, 0, NULL, 0),
+ RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
/* ADC Mixer */
SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
@@ -2141,10 +2142,10 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* ADC Filter Power */
SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
- RT5668_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
+ RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
/* Digital Interface */
- SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5668_PWR_I2S1_SHIFT, 0,
+ SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -2166,7 +2167,7 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
- RT5668_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
+ RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
@@ -2174,9 +2175,9 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* DACs */
SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
- RT5668_PWR_DAC_L1_SHIFT, 0, NULL, 0),
+ RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
- RT5668_PWR_DAC_R1_SHIFT, 0, NULL, 0),
+ RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
@@ -2189,21 +2190,21 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HPOR"),
};
-static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
+static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
- RT5668_PWR_LDO2_SHIFT, 0, NULL, 0),
- SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5668_PWR_VOL,
- RT5668_PWR_MIC_DET_SHIFT, 0, NULL, 0),
+ RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
+ RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
- RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
+ RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
- RT5668_I2S1_ASRC_SHIFT, 0, NULL, 0),
+ RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
- RT5668_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
+ RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
- RT5668_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
+ RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN2P"),
@@ -2212,51 +2213,51 @@ static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
- RT5668_PWR_CBJ_SHIFT, 0, NULL, 0),
+ RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
- rt5668_bst2_power, SND_SOC_DAPM_PRE_PMD |
+ rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* REC Mixer */
- SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_recmix1l,
- ARRAY_SIZE(rt5668_recmix1l)),
- SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5668_recmix1r,
- ARRAY_SIZE(rt5668_recmix1r)),
+ SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
+ ARRAY_SIZE(rt5663_recmix1l)),
+ SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
+ ARRAY_SIZE(rt5663_recmix1r)),
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
- RT5668_PWR_RECMIX2_SHIFT, 0, NULL, 0),
+ RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
- RT5668_PWR_ADC_R1_SHIFT, 0, NULL, 0),
+ RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
- RT5668_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
+ RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
- RT5668_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
+ RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
- RT5668_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
+ RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
- RT5668_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
+ RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
- &rt5668_sto1_adcl_mux),
+ &rt5663_sto1_adcl_mux),
SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
- &rt5668_sto1_adcr_mux),
+ &rt5663_sto1_adcr_mux),
/* ADC Mix */
SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
- rt5668_sto1_adc_r_mix, ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
+ rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
/* Analog DAC Clock */
SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
- RT5668_CKGEN_DAC1_SHIFT, 0, NULL, 0),
+ RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
/* Headphone out */
SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
- &rt5668_hpo_switch),
+ &rt5663_hpo_switch),
};
static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
@@ -2267,7 +2268,7 @@ static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
/* LDO */
SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
- RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
+ RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
@@ -2341,7 +2342,7 @@ static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
{ "HP Amp", NULL, "DAC R" },
};
-static const struct snd_soc_dapm_route rt5668_specific_dapm_routes[] = {
+static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
{ "MICBIAS1", NULL, "LDO2" },
{ "MICBIAS2", NULL, "LDO2" },
@@ -2440,26 +2441,26 @@ static int rt5663_hw_params(struct snd_pcm_substream *substream,
switch (params_width(params)) {
case 8:
- val_len = RT5668_I2S_DL_8;
+ val_len = RT5663_I2S_DL_8;
break;
case 16:
- val_len = RT5668_I2S_DL_16;
+ val_len = RT5663_I2S_DL_16;
break;
case 20:
- val_len = RT5668_I2S_DL_20;
+ val_len = RT5663_I2S_DL_20;
break;
case 24:
- val_len = RT5668_I2S_DL_24;
+ val_len = RT5663_I2S_DL_24;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_I2S1_SDP,
- RT5668_I2S_DL_MASK, val_len);
+ RT5663_I2S_DL_MASK, val_len);
snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
- RT5668_I2S_PD1_MASK, pre_div << RT5668_I2S_PD1_SHIFT);
+ RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
return 0;
}
@@ -2473,7 +2474,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_CBM_CFM:
break;
case SND_SOC_DAIFMT_CBS_CFS:
- reg_val |= RT5668_I2S_MS_S;
+ reg_val |= RT5663_I2S_MS_S;
break;
default:
return -EINVAL;
@@ -2483,7 +2484,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
- reg_val |= RT5668_I2S_BP_INV;
+ reg_val |= RT5663_I2S_BP_INV;
break;
default:
return -EINVAL;
@@ -2493,20 +2494,20 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
- reg_val |= RT5668_I2S_DF_LEFT;
+ reg_val |= RT5663_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
- reg_val |= RT5668_I2S_DF_PCM_A;
+ reg_val |= RT5663_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
- reg_val |= RT5668_I2S_DF_PCM_B;
+ reg_val |= RT5663_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
- snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5668_I2S_MS_MASK |
- RT5668_I2S_BP_MASK | RT5668_I2S_DF_MASK, reg_val);
+ snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
+ RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
return 0;
}
@@ -2535,7 +2536,7 @@ static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
- snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5668_SCLK_SRC_MASK,
+ snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
reg_val);
rt5663->sysclk = freq;
rt5663->sysclk_src = clk_id;
@@ -2569,17 +2570,17 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
return 0;
}
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
- mask = RT5668_PLL1_SRC_MASK;
- shift = RT5668_PLL1_SRC_SHIFT;
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
+ mask = RT5663_V2_PLL1_SRC_MASK;
+ shift = RT5663_V2_PLL1_SRC_SHIFT;
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
mask = RT5663_PLL1_SRC_MASK;
shift = RT5663_PLL1_SRC_SHIFT;
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
@@ -2607,10 +2608,10 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
pll_code.k_code);
snd_soc_write(codec, RT5663_PLL_1,
- pll_code.n_code << RT5668_PLL_N_SHIFT | pll_code.k_code);
+ pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
snd_soc_write(codec, RT5663_PLL_2,
- (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SHIFT |
- pll_code.m_bp << RT5668_PLL_M_BP_SHIFT);
+ (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
+ pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
rt5663->pll_in = freq_in;
rt5663->pll_out = freq_out;
@@ -2627,20 +2628,20 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int val = 0, reg;
if (rx_mask || tx_mask)
- val |= RT5668_TDM_MODE_TDM;
+ val |= RT5663_TDM_MODE_TDM;
switch (slots) {
case 4:
- val |= RT5668_TDM_IN_CH_4;
- val |= RT5668_TDM_OUT_CH_4;
+ val |= RT5663_TDM_IN_CH_4;
+ val |= RT5663_TDM_OUT_CH_4;
break;
case 6:
- val |= RT5668_TDM_IN_CH_6;
- val |= RT5668_TDM_OUT_CH_6;
+ val |= RT5663_TDM_IN_CH_6;
+ val |= RT5663_TDM_OUT_CH_6;
break;
case 8:
- val |= RT5668_TDM_IN_CH_8;
- val |= RT5668_TDM_OUT_CH_8;
+ val |= RT5663_TDM_IN_CH_8;
+ val |= RT5663_TDM_OUT_CH_8;
break;
case 2:
break;
@@ -2650,16 +2651,16 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
switch (slot_width) {
case 20:
- val |= RT5668_TDM_IN_LEN_20;
- val |= RT5668_TDM_OUT_LEN_20;
+ val |= RT5663_TDM_IN_LEN_20;
+ val |= RT5663_TDM_OUT_LEN_20;
break;
case 24:
- val |= RT5668_TDM_IN_LEN_24;
- val |= RT5668_TDM_OUT_LEN_24;
+ val |= RT5663_TDM_IN_LEN_24;
+ val |= RT5663_TDM_OUT_LEN_24;
break;
case 32:
- val |= RT5668_TDM_IN_LEN_32;
- val |= RT5668_TDM_OUT_LEN_32;
+ val |= RT5663_TDM_IN_LEN_32;
+ val |= RT5663_TDM_OUT_LEN_32;
break;
case 16:
break;
@@ -2667,21 +2668,21 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
return -EINVAL;
}
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
reg = RT5663_TDM_2;
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
reg = RT5663_TDM_1;
break;
default:
- dev_err(codec->dev, "Unknown CODEC_TYPE\n");
+ dev_err(codec->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
- snd_soc_update_bits(codec, reg, RT5668_TDM_MODE_MASK |
- RT5668_TDM_IN_CH_MASK | RT5668_TDM_OUT_CH_MASK |
- RT5668_TDM_IN_LEN_MASK | RT5668_TDM_OUT_LEN_MASK, val);
+ snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
+ RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
+ RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
return 0;
}
@@ -2694,8 +2695,8 @@ static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
- if (rt5663->codec_type == CODEC_TYPE_RT5668)
- reg = RT5668_TDM_8;
+ if (rt5663->codec_ver == CODEC_VER_1)
+ reg = RT5663_TDM_9;
else
reg = RT5663_TDM_5;
@@ -2736,47 +2737,47 @@ static int rt5663_set_bias_level(struct snd_soc_codec *codec,
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
- RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK,
- RT5668_PWR_FV1 | RT5668_PWR_FV2);
+ RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
+ RT5663_PWR_FV1 | RT5663_PWR_FV2);
break;
case SND_SOC_BIAS_PREPARE:
- if (rt5663->codec_type == CODEC_TYPE_RT5668) {
+ if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_DIG_MISC,
- RT5668_DIG_GATE_CTRL_MASK,
- RT5668_DIG_GATE_CTRL_EN);
+ RT5663_DIG_GATE_CTRL_MASK,
+ RT5663_DIG_GATE_CTRL_EN);
snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
- RT5668_EN_ANA_CLK_DET_MASK |
- RT5668_PWR_CLK_DET_MASK,
- RT5668_EN_ANA_CLK_DET_AUTO |
- RT5668_PWR_CLK_DET_EN);
+ RT5663_EN_ANA_CLK_DET_MASK |
+ RT5663_PWR_CLK_DET_MASK,
+ RT5663_EN_ANA_CLK_DET_AUTO |
+ RT5663_PWR_CLK_DET_EN);
}
break;
case SND_SOC_BIAS_STANDBY:
- if (rt5663->codec_type == CODEC_TYPE_RT5668)
+ if (rt5663->codec_ver == CODEC_VER_1)
snd_soc_update_bits(codec, RT5663_DIG_MISC,
- RT5668_DIG_GATE_CTRL_MASK,
- RT5668_DIG_GATE_CTRL_DIS);
+ RT5663_DIG_GATE_CTRL_MASK,
+ RT5663_DIG_GATE_CTRL_DIS);
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
- RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
- RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK |
- RT5668_PWR_MB_MASK, RT5668_PWR_VREF1 |
- RT5668_PWR_VREF2 | RT5668_PWR_MB);
+ RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
+ RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
+ RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
+ RT5663_PWR_VREF2 | RT5663_PWR_MB);
usleep_range(10000, 10005);
- if (rt5663->codec_type == CODEC_TYPE_RT5668) {
+ if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
- RT5668_EN_ANA_CLK_DET_MASK |
- RT5668_PWR_CLK_DET_MASK,
- RT5668_EN_ANA_CLK_DET_DIS |
- RT5668_PWR_CLK_DET_DIS);
+ RT5663_EN_ANA_CLK_DET_MASK |
+ RT5663_PWR_CLK_DET_MASK,
+ RT5663_EN_ANA_CLK_DET_DIS |
+ RT5663_PWR_CLK_DET_DIS);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
- RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
- RT5668_PWR_FV1 | RT5668_PWR_FV2, 0x0);
+ RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
+ RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
break;
default:
@@ -2793,18 +2794,18 @@ static int rt5663_probe(struct snd_soc_codec *codec)
rt5663->codec = codec;
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
snd_soc_dapm_new_controls(dapm,
- rt5668_specific_dapm_widgets,
- ARRAY_SIZE(rt5668_specific_dapm_widgets));
+ rt5663_v2_specific_dapm_widgets,
+ ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
- rt5668_specific_dapm_routes,
- ARRAY_SIZE(rt5668_specific_dapm_routes));
- snd_soc_add_codec_controls(codec, rt5668_specific_controls,
- ARRAY_SIZE(rt5668_specific_controls));
+ rt5663_v2_specific_dapm_routes,
+ ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
+ snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
+ ARRAY_SIZE(rt5663_v2_specific_controls));
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
snd_soc_dapm_new_controls(dapm,
rt5663_specific_dapm_widgets,
ARRAY_SIZE(rt5663_specific_dapm_widgets));
@@ -2905,16 +2906,16 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
}
};
-static const struct regmap_config rt5668_regmap = {
+static const struct regmap_config rt5663_v2_regmap = {
.reg_bits = 16,
.val_bits = 16,
.use_single_rw = true,
.max_register = 0x07fa,
- .volatile_reg = rt5668_volatile_register,
- .readable_reg = rt5668_readable_register,
+ .volatile_reg = rt5663_v2_volatile_register,
+ .readable_reg = rt5663_v2_readable_register,
.cache_type = REGCACHE_RBTREE,
- .reg_defaults = rt5668_reg,
- .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
+ .reg_defaults = rt5663_v2_reg,
+ .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
};
static const struct regmap_config rt5663_regmap = {
@@ -2939,7 +2940,6 @@ static const struct regmap_config temp_regmap = {
};
static const struct i2c_device_id rt5663_i2c_id[] = {
- { "rt5668", 0 },
{ "rt5663", 0 },
{}
};
@@ -2947,7 +2947,6 @@ MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5663_of_match[] = {
- { .compatible = "realtek,rt5668", },
{ .compatible = "realtek,rt5663", },
{},
};
@@ -2956,80 +2955,79 @@ MODULE_DEVICE_TABLE(of, rt5663_of_match);
#ifdef CONFIG_ACPI
static struct acpi_device_id rt5663_acpi_match[] = {
- { "10EC5668", 0},
{ "10EC5663", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
#endif
-static void rt5668_calibrate(struct rt5663_priv *rt5668)
+static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
{
- regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0xa402);
- regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x0100);
- regmap_write(rt5668->regmap, RT5663_RECMIX, 0x4040);
- regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x0001);
- regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0380);
- regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
- regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1000);
- regmap_write(rt5668->regmap, RT5663_CHOP_DAC_L, 0x3030);
- regmap_write(rt5668->regmap, RT5663_CALIB_ADC, 0x3c05);
- regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa23e);
+ regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
+ regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
+ regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
+ regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
+ regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
+ regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
+ regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
+ regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
+ regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
+ regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
msleep(40);
- regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf23e);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x0321);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0xfc00);
+ regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
msleep(500);
}
-static void rt5663_calibrate(struct rt5663_priv *rt5668)
+static void rt5663_calibrate(struct rt5663_priv *rt5663)
{
int value, count;
- regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0280);
- regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
- regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x8001);
- regmap_write(rt5668->regmap, RT5663_VREF_RECMIX, 0x0032);
- regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa2be);
+ regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0280);
+ regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
+ regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
+ regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
+ regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
msleep(20);
- regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf2be);
- regmap_write(rt5668->regmap, RT5663_PWR_DIG_2, 0x8400);
- regmap_write(rt5668->regmap, RT5663_CHOP_ADC, 0x3000);
- regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
- regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x8df8);
- regmap_write(rt5668->regmap, RT5663_PWR_ANLG_2, 0x0003);
- regmap_write(rt5668->regmap, RT5663_PWR_ANLG_3, 0x018c);
- regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1111);
- regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
- regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
- regmap_write(rt5668->regmap, RT5663_DEPOP_2, 0x3003);
- regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
- regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
- regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
- regmap_write(rt5668->regmap, RT5663_DACREF_LDO, 0x3b0b);
- regmap_write(rt5668->regmap, RT5663_STO_DAC_MIXER, 0x2080);
- regmap_write(rt5668->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
- regmap_write(rt5668->regmap, RT5663_HP_BIAS, 0xabba);
- regmap_write(rt5668->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
- regmap_write(rt5668->regmap, RT5663_HP_OUT_EN, 0x8088);
- regmap_write(rt5668->regmap, RT5663_STO_DRE_9, 0x0017);
- regmap_write(rt5668->regmap, RT5663_STO_DRE_10, 0x0017);
- regmap_write(rt5668->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
- regmap_write(rt5668->regmap, RT5663_RECMIX, 0x0005);
- regmap_write(rt5668->regmap, RT5663_ADDA_RST, 0xc000);
- regmap_write(rt5668->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x00c9);
- regmap_write(rt5668->regmap, RT5663_DUMMY_1, 0x004c);
- regmap_write(rt5668->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
- regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0x4702);
+ regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
+ regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
+ regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
+ regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
+ regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
+ regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0003);
+ regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
+ regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1111);
+ regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
+ regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
+ regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
+ regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
+ regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
+ regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
+ regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
+ regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x2080);
+ regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
+ regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xabba);
+ regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
+ regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
+ regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
+ regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
+ regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
+ regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
+ regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
+ regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
+ regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
+ regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
+ regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4702);
msleep(200);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0x0069);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_3, 0x06c2);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
- regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06c2);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
+ regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
count = 0;
while (true) {
- regmap_read(rt5668->regmap, RT5663_HP_CALIB_1_1, &value);
+ regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
@@ -3066,17 +3064,17 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
}
regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
switch (val) {
- case RT5668_DEVICE_ID:
- rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
- rt5663->codec_type = CODEC_TYPE_RT5668;
+ case RT5663_DEVICE_ID_2:
+ rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
+ rt5663->codec_ver = CODEC_VER_1;
break;
- case RT5663_DEVICE_ID:
+ case RT5663_DEVICE_ID_1:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
- rt5663->codec_type = CODEC_TYPE_RT5663;
+ rt5663->codec_ver = CODEC_VER_0;
break;
default:
dev_err(&i2c->dev,
- "Device with ID register %#x is not rt5663 or rt5668\n",
+ "Device with ID register %#x is not rt5663\n",
val);
return -ENODEV;
}
@@ -3091,11 +3089,11 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
/* reset and calibrate */
regmap_write(rt5663->regmap, RT5663_RESET, 0);
regcache_cache_bypass(rt5663->regmap, true);
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
- rt5668_calibrate(rt5663);
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
+ rt5663_v2_calibrate(rt5663);
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
rt5663_calibrate(rt5663);
break;
default:
@@ -3106,44 +3104,44 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
dev_dbg(&i2c->dev, "calibrate done\n");
/* GPIO1 as IRQ */
- regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5668_GP1_PIN_MASK,
- RT5668_GP1_PIN_IRQ);
+ regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
+ RT5663_GP1_PIN_IRQ);
/* 4btn inline command debounce */
regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
- RT5668_4BTN_CLK_DEB_MASK, RT5668_4BTN_CLK_DEB_65MS);
+ RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
- switch (rt5663->codec_type) {
- case CODEC_TYPE_RT5668:
+ switch (rt5663->codec_ver) {
+ case CODEC_VER_1:
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
/* JD1 */
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
- RT5668_IRQ_POW_SAV_MASK | RT5668_IRQ_POW_SAV_JD1_MASK,
- RT5668_IRQ_POW_SAV_EN | RT5668_IRQ_POW_SAV_JD1_EN);
+ RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
+ RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
- RT5668_PWR_JD1_MASK, RT5668_PWR_JD1);
+ RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
- RT5668_EN_CB_JD_MASK, RT5668_EN_CB_JD_EN);
+ RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
- RT5668_HP_SIG_SRC1_MASK, RT5668_HP_SIG_SRC1_REG);
+ RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
- RT5668_VREF_BIAS_MASK | RT5668_CBJ_DET_MASK |
- RT5668_DET_TYPE_MASK, RT5668_VREF_BIAS_REG |
- RT5668_CBJ_DET_EN | RT5668_DET_TYPE_QFN);
+ RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
+ RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
+ RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
/* Set GPIO4 and GPIO8 as input for combo jack */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
- RT5668_GP4_PIN_CONF_MASK, RT5668_GP4_PIN_CONF_INPUT);
- regmap_update_bits(rt5663->regmap, RT5668_GPIO_3,
- RT5668_GP8_PIN_CONF_MASK, RT5668_GP8_PIN_CONF_INPUT);
+ RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
+ regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
+ RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
- RT5668_LDO1_DVO_MASK | RT5668_AMP_HP_MASK,
- RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
+ RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
+ RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
break;
- case CODEC_TYPE_RT5663:
+ case CODEC_VER_0:
regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
- RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
+ RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
- RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
+ RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
diff --git a/sound/soc/codecs/rt5663.h b/sound/soc/codecs/rt5663.h
index 252c2761791e..d77fae619f2f 100644
--- a/sound/soc/codecs/rt5663.h
+++ b/sound/soc/codecs/rt5663.h
@@ -18,655 +18,652 @@
#define RT5663_VENDOR_ID_1 0x00fe
#define RT5663_VENDOR_ID_2 0x00ff
-#define RT5668_LOUT_CTRL 0x0001
-#define RT5668_HP_AMP_2 0x0003
-#define RT5668_MONO_OUT 0x0004
-#define RT5668_MONO_GAIN 0x0007
-
-#define RT5668_AEC_BST 0x000b
-#define RT5668_IN1_IN2 0x000c
-#define RT5668_IN3_IN4 0x000d
-#define RT5668_INL1_INR1 0x000f
-#define RT5668_CBJ_TYPE_2 0x0011
-#define RT5668_CBJ_TYPE_3 0x0012
-#define RT5668_CBJ_TYPE_4 0x0013
-#define RT5668_CBJ_TYPE_5 0x0014
-#define RT5668_CBJ_TYPE_8 0x0017
+#define RT5663_LOUT_CTRL 0x0001
+#define RT5663_HP_AMP_2 0x0003
+#define RT5663_MONO_OUT 0x0004
+#define RT5663_MONO_GAIN 0x0007
+
+#define RT5663_AEC_BST 0x000b
+#define RT5663_IN1_IN2 0x000c
+#define RT5663_IN3_IN4 0x000d
+#define RT5663_INL1_INR1 0x000f
+#define RT5663_CBJ_TYPE_2 0x0011
+#define RT5663_CBJ_TYPE_3 0x0012
+#define RT5663_CBJ_TYPE_4 0x0013
+#define RT5663_CBJ_TYPE_5 0x0014
+#define RT5663_CBJ_TYPE_8 0x0017
/* I/O - ADC/DAC/DMIC */
-#define RT5668_DAC3_DIG_VOL 0x001a
-#define RT5668_DAC3_CTRL 0x001b
-#define RT5668_MONO_ADC_DIG_VOL 0x001d
-#define RT5668_STO2_ADC_DIG_VOL 0x001e
-#define RT5668_MONO_ADC_BST_GAIN 0x0020
-#define RT5668_STO2_ADC_BST_GAIN 0x0021
-#define RT5668_SIDETONE_CTRL 0x0024
+#define RT5663_DAC3_DIG_VOL 0x001a
+#define RT5663_DAC3_CTRL 0x001b
+#define RT5663_MONO_ADC_DIG_VOL 0x001d
+#define RT5663_STO2_ADC_DIG_VOL 0x001e
+#define RT5663_MONO_ADC_BST_GAIN 0x0020
+#define RT5663_STO2_ADC_BST_GAIN 0x0021
+#define RT5663_SIDETONE_CTRL 0x0024
/* Mixer - D-D */
-#define RT5668_MONO1_ADC_MIXER 0x0027
-#define RT5668_STO2_ADC_MIXER 0x0028
-#define RT5668_MONO_DAC_MIXER 0x002b
-#define RT5668_DAC2_SRC_CTRL 0x002e
-#define RT5668_IF_3_4_DATA_CTL 0x002f
-#define RT5668_IF_5_DATA_CTL 0x0030
-#define RT5668_PDM_OUT_CTL 0x0031
-#define RT5668_PDM_I2C_DATA_CTL1 0x0032
-#define RT5668_PDM_I2C_DATA_CTL2 0x0033
-#define RT5668_PDM_I2C_DATA_CTL3 0x0034
-#define RT5668_PDM_I2C_DATA_CTL4 0x0035
+#define RT5663_MONO1_ADC_MIXER 0x0027
+#define RT5663_STO2_ADC_MIXER 0x0028
+#define RT5663_MONO_DAC_MIXER 0x002b
+#define RT5663_DAC2_SRC_CTRL 0x002e
+#define RT5663_IF_3_4_DATA_CTL 0x002f
+#define RT5663_IF_5_DATA_CTL 0x0030
+#define RT5663_PDM_OUT_CTL 0x0031
+#define RT5663_PDM_I2C_DATA_CTL1 0x0032
+#define RT5663_PDM_I2C_DATA_CTL2 0x0033
+#define RT5663_PDM_I2C_DATA_CTL3 0x0034
+#define RT5663_PDM_I2C_DATA_CTL4 0x0035
/*Mixer - Analog*/
-#define RT5668_RECMIX1_NEW 0x003a
-#define RT5668_RECMIX1L_0 0x003b
-#define RT5668_RECMIX1L 0x003c
-#define RT5668_RECMIX1R_0 0x003d
-#define RT5668_RECMIX1R 0x003e
-#define RT5668_RECMIX2_NEW 0x003f
-#define RT5668_RECMIX2_L_2 0x0041
-#define RT5668_RECMIX2_R 0x0042
-#define RT5668_RECMIX2_R_2 0x0043
-#define RT5668_CALIB_REC_LR 0x0044
-#define RT5668_ALC_BK_GAIN 0x0049
-#define RT5668_MONOMIX_GAIN 0x004a
-#define RT5668_MONOMIX_IN_GAIN 0x004b
-#define RT5668_OUT_MIXL_GAIN 0x004d
-#define RT5668_OUT_LMIX_IN_GAIN 0x004e
-#define RT5668_OUT_RMIX_IN_GAIN 0x004f
-#define RT5668_OUT_RMIX_IN_GAIN1 0x0050
-#define RT5668_LOUT_MIXER_CTRL 0x0052
+#define RT5663_RECMIX1_NEW 0x003a
+#define RT5663_RECMIX1L_0 0x003b
+#define RT5663_RECMIX1L 0x003c
+#define RT5663_RECMIX1R_0 0x003d
+#define RT5663_RECMIX1R 0x003e
+#define RT5663_RECMIX2_NEW 0x003f
+#define RT5663_RECMIX2_L_2 0x0041
+#define RT5663_RECMIX2_R 0x0042
+#define RT5663_RECMIX2_R_2 0x0043
+#define RT5663_CALIB_REC_LR 0x0044
+#define RT5663_ALC_BK_GAIN 0x0049
+#define RT5663_MONOMIX_GAIN 0x004a
+#define RT5663_MONOMIX_IN_GAIN 0x004b
+#define RT5663_OUT_MIXL_GAIN 0x004d
+#define RT5663_OUT_LMIX_IN_GAIN 0x004e
+#define RT5663_OUT_RMIX_IN_GAIN 0x004f
+#define RT5663_OUT_RMIX_IN_GAIN1 0x0050
+#define RT5663_LOUT_MIXER_CTRL 0x0052
/* Power */
-#define RT5668_PWR_VOL 0x0067
+#define RT5663_PWR_VOL 0x0067
-#define RT5668_ADCDAC_RST 0x006d
+#define RT5663_ADCDAC_RST 0x006d
/* Format - ADC/DAC */
-#define RT5668_I2S34_SDP 0x0071
-#define RT5668_I2S5_SDP 0x0072
-/* Format - TDM Control */
-#define RT5668_TDM_5 0x007c
-#define RT5668_TDM_6 0x007d
-#define RT5668_TDM_7 0x007e
-#define RT5668_TDM_8 0x007f
+#define RT5663_I2S34_SDP 0x0071
+#define RT5663_I2S5_SDP 0x0072
/* Function - Analog */
-#define RT5668_ASRC_3 0x0085
-#define RT5668_ASRC_6 0x0088
-#define RT5668_ASRC_7 0x0089
-#define RT5668_PLL_TRK_13 0x0099
-#define RT5668_I2S_M_CLK_CTL 0x00a0
-#define RT5668_FDIV_I2S34_M_CLK 0x00a1
-#define RT5668_FDIV_I2S34_M_CLK2 0x00a2
-#define RT5668_FDIV_I2S5_M_CLK 0x00a3
-#define RT5668_FDIV_I2S5_M_CLK2 0x00a4
+#define RT5663_ASRC_3 0x0085
+#define RT5663_ASRC_6 0x0088
+#define RT5663_ASRC_7 0x0089
+#define RT5663_PLL_TRK_13 0x0099
+#define RT5663_I2S_M_CLK_CTL 0x00a0
+#define RT5663_FDIV_I2S34_M_CLK 0x00a1
+#define RT5663_FDIV_I2S34_M_CLK2 0x00a2
+#define RT5663_FDIV_I2S5_M_CLK 0x00a3
+#define RT5663_FDIV_I2S5_M_CLK2 0x00a4
/* Function - Digital */
-#define RT5668_IRQ_4 0x00b9
-#define RT5668_GPIO_3 0x00c2
-#define RT5668_GPIO_4 0x00c3
-#define RT5668_GPIO_STA 0x00c4
-#define RT5668_HP_AMP_DET1 0x00d0
-#define RT5668_HP_AMP_DET2 0x00d1
-#define RT5668_HP_AMP_DET3 0x00d2
-#define RT5668_MID_BD_HP_AMP 0x00d3
-#define RT5668_LOW_BD_HP_AMP 0x00d4
-#define RT5668_SOF_VOL_ZC2 0x00da
-#define RT5668_ADC_STO2_ADJ1 0x00ee
-#define RT5668_ADC_STO2_ADJ2 0x00ef
+#define RT5663_V2_IRQ_4 0x00b9
+#define RT5663_GPIO_3 0x00c2
+#define RT5663_GPIO_4 0x00c3
+#define RT5663_GPIO_STA2 0x00c4
+#define RT5663_HP_AMP_DET1 0x00d0
+#define RT5663_HP_AMP_DET2 0x00d1
+#define RT5663_HP_AMP_DET3 0x00d2
+#define RT5663_MID_BD_HP_AMP 0x00d3
+#define RT5663_LOW_BD_HP_AMP 0x00d4
+#define RT5663_SOF_VOL_ZC2 0x00da
+#define RT5663_ADC_STO2_ADJ1 0x00ee
+#define RT5663_ADC_STO2_ADJ2 0x00ef
/* General Control */
-#define RT5668_A_JD_CTRL 0x00f0
-#define RT5668_JD1_TRES_CTRL 0x00f1
-#define RT5668_JD2_TRES_CTRL 0x00f2
-#define RT5668_JD_CTRL2 0x00f7
-#define RT5668_DUM_REG_2 0x00fb
-#define RT5668_DUM_REG_3 0x00fc
-
-
-#define RT5668_DACADC_DIG_VOL2 0x0101
-#define RT5668_DIG_IN_PIN2 0x0133
-#define RT5668_PAD_DRV_CTL1 0x0136
-#define RT5668_SOF_RAM_DEPOP 0x0138
-#define RT5668_VOL_TEST 0x013f
-#define RT5668_TEST_MODE_3 0x0147
-#define RT5668_TEST_MODE_4 0x0148
-#define RT5668_MONO_DYNA_1 0x0170
-#define RT5668_MONO_DYNA_2 0x0171
-#define RT5668_MONO_DYNA_3 0x0172
-#define RT5668_MONO_DYNA_4 0x0173
-#define RT5668_MONO_DYNA_5 0x0174
-#define RT5668_MONO_DYNA_6 0x0175
-#define RT5668_STO1_SIL_DET 0x0190
-#define RT5668_MONOL_SIL_DET 0x0191
-#define RT5668_MONOR_SIL_DET 0x0192
-#define RT5668_STO2_DAC_SIL 0x0193
-#define RT5668_PWR_SAV_CTL1 0x0194
-#define RT5668_PWR_SAV_CTL2 0x0195
-#define RT5668_PWR_SAV_CTL3 0x0196
-#define RT5668_PWR_SAV_CTL4 0x0197
-#define RT5668_PWR_SAV_CTL5 0x0198
-#define RT5668_PWR_SAV_CTL6 0x0199
-#define RT5668_MONO_AMP_CAL1 0x01a0
-#define RT5668_MONO_AMP_CAL2 0x01a1
-#define RT5668_MONO_AMP_CAL3 0x01a2
-#define RT5668_MONO_AMP_CAL4 0x01a3
-#define RT5668_MONO_AMP_CAL5 0x01a4
-#define RT5668_MONO_AMP_CAL6 0x01a5
-#define RT5668_MONO_AMP_CAL7 0x01a6
-#define RT5668_MONO_AMP_CAL_ST1 0x01a7
-#define RT5668_MONO_AMP_CAL_ST2 0x01a8
-#define RT5668_MONO_AMP_CAL_ST3 0x01a9
-#define RT5668_MONO_AMP_CAL_ST4 0x01aa
-#define RT5668_MONO_AMP_CAL_ST5 0x01ab
-#define RT5668_HP_IMP_SEN_13 0x01b9
-#define RT5668_HP_IMP_SEN_14 0x01ba
-#define RT5668_HP_IMP_SEN_6 0x01bb
-#define RT5668_HP_IMP_SEN_7 0x01bc
-#define RT5668_HP_IMP_SEN_8 0x01bd
-#define RT5668_HP_IMP_SEN_9 0x01be
-#define RT5668_HP_IMP_SEN_10 0x01bf
-#define RT5668_HP_LOGIC_3 0x01dc
-#define RT5668_HP_CALIB_ST10 0x01f3
-#define RT5668_HP_CALIB_ST11 0x01f4
-#define RT5668_PRO_REG_TBL_4 0x0203
-#define RT5668_PRO_REG_TBL_5 0x0204
-#define RT5668_PRO_REG_TBL_6 0x0205
-#define RT5668_PRO_REG_TBL_7 0x0206
-#define RT5668_PRO_REG_TBL_8 0x0207
-#define RT5668_PRO_REG_TBL_9 0x0208
-#define RT5668_SAR_ADC_INL_1 0x0210
-#define RT5668_SAR_ADC_INL_2 0x0211
-#define RT5668_SAR_ADC_INL_3 0x0212
-#define RT5668_SAR_ADC_INL_4 0x0213
-#define RT5668_SAR_ADC_INL_5 0x0214
-#define RT5668_SAR_ADC_INL_6 0x0215
-#define RT5668_SAR_ADC_INL_7 0x0216
-#define RT5668_SAR_ADC_INL_8 0x0217
-#define RT5668_SAR_ADC_INL_9 0x0218
-#define RT5668_SAR_ADC_INL_10 0x0219
-#define RT5668_SAR_ADC_INL_11 0x021a
-#define RT5668_SAR_ADC_INL_12 0x021b
-#define RT5668_DRC_CTRL_1 0x02ff
-#define RT5668_DRC1_CTRL_2 0x0301
-#define RT5668_DRC1_CTRL_3 0x0302
-#define RT5668_DRC1_CTRL_4 0x0303
-#define RT5668_DRC1_CTRL_5 0x0304
-#define RT5668_DRC1_CTRL_6 0x0305
-#define RT5668_DRC1_HD_CTRL_1 0x0306
-#define RT5668_DRC1_HD_CTRL_2 0x0307
-#define RT5668_DRC1_PRI_REG_1 0x0310
-#define RT5668_DRC1_PRI_REG_2 0x0311
-#define RT5668_DRC1_PRI_REG_3 0x0312
-#define RT5668_DRC1_PRI_REG_4 0x0313
-#define RT5668_DRC1_PRI_REG_5 0x0314
-#define RT5668_DRC1_PRI_REG_6 0x0315
-#define RT5668_DRC1_PRI_REG_7 0x0316
-#define RT5668_DRC1_PRI_REG_8 0x0317
-#define RT5668_ALC_PGA_CTL_1 0x0330
-#define RT5668_ALC_PGA_CTL_2 0x0331
-#define RT5668_ALC_PGA_CTL_3 0x0332
-#define RT5668_ALC_PGA_CTL_4 0x0333
-#define RT5668_ALC_PGA_CTL_5 0x0334
-#define RT5668_ALC_PGA_CTL_6 0x0335
-#define RT5668_ALC_PGA_CTL_7 0x0336
-#define RT5668_ALC_PGA_CTL_8 0x0337
-#define RT5668_ALC_PGA_REG_1 0x0338
-#define RT5668_ALC_PGA_REG_2 0x0339
-#define RT5668_ALC_PGA_REG_3 0x033a
-#define RT5668_ADC_EQ_RECOV_1 0x03c0
-#define RT5668_ADC_EQ_RECOV_2 0x03c1
-#define RT5668_ADC_EQ_RECOV_3 0x03c2
-#define RT5668_ADC_EQ_RECOV_4 0x03c3
-#define RT5668_ADC_EQ_RECOV_5 0x03c4
-#define RT5668_ADC_EQ_RECOV_6 0x03c5
-#define RT5668_ADC_EQ_RECOV_7 0x03c6
-#define RT5668_ADC_EQ_RECOV_8 0x03c7
-#define RT5668_ADC_EQ_RECOV_9 0x03c8
-#define RT5668_ADC_EQ_RECOV_10 0x03c9
-#define RT5668_ADC_EQ_RECOV_11 0x03ca
-#define RT5668_ADC_EQ_RECOV_12 0x03cb
-#define RT5668_ADC_EQ_RECOV_13 0x03cc
-#define RT5668_VID_HIDDEN 0x03fe
-#define RT5668_VID_CUSTOMER 0x03ff
-#define RT5668_SCAN_MODE 0x07f0
-#define RT5668_I2C_BYPA 0x07fa
+#define RT5663_A_JD_CTRL 0x00f0
+#define RT5663_JD1_TRES_CTRL 0x00f1
+#define RT5663_JD2_TRES_CTRL 0x00f2
+#define RT5663_V2_JD_CTRL2 0x00f7
+#define RT5663_DUM_REG_2 0x00fb
+#define RT5663_DUM_REG_3 0x00fc
+
+
+#define RT5663_DACADC_DIG_VOL2 0x0101
+#define RT5663_DIG_IN_PIN2 0x0133
+#define RT5663_PAD_DRV_CTL1 0x0136
+#define RT5663_SOF_RAM_DEPOP 0x0138
+#define RT5663_VOL_TEST 0x013f
+#define RT5663_MONO_DYNA_1 0x0170
+#define RT5663_MONO_DYNA_2 0x0171
+#define RT5663_MONO_DYNA_3 0x0172
+#define RT5663_MONO_DYNA_4 0x0173
+#define RT5663_MONO_DYNA_5 0x0174
+#define RT5663_MONO_DYNA_6 0x0175
+#define RT5663_STO1_SIL_DET 0x0190
+#define RT5663_MONOL_SIL_DET 0x0191
+#define RT5663_MONOR_SIL_DET 0x0192
+#define RT5663_STO2_DAC_SIL 0x0193
+#define RT5663_PWR_SAV_CTL1 0x0194
+#define RT5663_PWR_SAV_CTL2 0x0195
+#define RT5663_PWR_SAV_CTL3 0x0196
+#define RT5663_PWR_SAV_CTL4 0x0197
+#define RT5663_PWR_SAV_CTL5 0x0198
+#define RT5663_PWR_SAV_CTL6 0x0199
+#define RT5663_MONO_AMP_CAL1 0x01a0
+#define RT5663_MONO_AMP_CAL2 0x01a1
+#define RT5663_MONO_AMP_CAL3 0x01a2
+#define RT5663_MONO_AMP_CAL4 0x01a3
+#define RT5663_MONO_AMP_CAL5 0x01a4
+#define RT5663_MONO_AMP_CAL6 0x01a5
+#define RT5663_MONO_AMP_CAL7 0x01a6
+#define RT5663_MONO_AMP_CAL_ST1 0x01a7
+#define RT5663_MONO_AMP_CAL_ST2 0x01a8
+#define RT5663_MONO_AMP_CAL_ST3 0x01a9
+#define RT5663_MONO_AMP_CAL_ST4 0x01aa
+#define RT5663_MONO_AMP_CAL_ST5 0x01ab
+#define RT5663_V2_HP_IMP_SEN_13 0x01b9
+#define RT5663_V2_HP_IMP_SEN_14 0x01ba
+#define RT5663_V2_HP_IMP_SEN_6 0x01bb
+#define RT5663_V2_HP_IMP_SEN_7 0x01bc
+#define RT5663_V2_HP_IMP_SEN_8 0x01bd
+#define RT5663_V2_HP_IMP_SEN_9 0x01be
+#define RT5663_V2_HP_IMP_SEN_10 0x01bf
+#define RT5663_HP_LOGIC_3 0x01dc
+#define RT5663_HP_CALIB_ST10 0x01f3
+#define RT5663_HP_CALIB_ST11 0x01f4
+#define RT5663_PRO_REG_TBL_4 0x0203
+#define RT5663_PRO_REG_TBL_5 0x0204
+#define RT5663_PRO_REG_TBL_6 0x0205
+#define RT5663_PRO_REG_TBL_7 0x0206
+#define RT5663_PRO_REG_TBL_8 0x0207
+#define RT5663_PRO_REG_TBL_9 0x0208
+#define RT5663_SAR_ADC_INL_1 0x0210
+#define RT5663_SAR_ADC_INL_2 0x0211
+#define RT5663_SAR_ADC_INL_3 0x0212
+#define RT5663_SAR_ADC_INL_4 0x0213
+#define RT5663_SAR_ADC_INL_5 0x0214
+#define RT5663_SAR_ADC_INL_6 0x0215
+#define RT5663_SAR_ADC_INL_7 0x0216
+#define RT5663_SAR_ADC_INL_8 0x0217
+#define RT5663_SAR_ADC_INL_9 0x0218
+#define RT5663_SAR_ADC_INL_10 0x0219
+#define RT5663_SAR_ADC_INL_11 0x021a
+#define RT5663_SAR_ADC_INL_12 0x021b
+#define RT5663_DRC_CTRL_1 0x02ff
+#define RT5663_DRC1_CTRL_2 0x0301
+#define RT5663_DRC1_CTRL_3 0x0302
+#define RT5663_DRC1_CTRL_4 0x0303
+#define RT5663_DRC1_CTRL_5 0x0304
+#define RT5663_DRC1_CTRL_6 0x0305
+#define RT5663_DRC1_HD_CTRL_1 0x0306
+#define RT5663_DRC1_HD_CTRL_2 0x0307
+#define RT5663_DRC1_PRI_REG_1 0x0310
+#define RT5663_DRC1_PRI_REG_2 0x0311
+#define RT5663_DRC1_PRI_REG_3 0x0312
+#define RT5663_DRC1_PRI_REG_4 0x0313
+#define RT5663_DRC1_PRI_REG_5 0x0314
+#define RT5663_DRC1_PRI_REG_6 0x0315
+#define RT5663_DRC1_PRI_REG_7 0x0316
+#define RT5663_DRC1_PRI_REG_8 0x0317
+#define RT5663_ALC_PGA_CTL_1 0x0330
+#define RT5663_ALC_PGA_CTL_2 0x0331
+#define RT5663_ALC_PGA_CTL_3 0x0332
+#define RT5663_ALC_PGA_CTL_4 0x0333
+#define RT5663_ALC_PGA_CTL_5 0x0334
+#define RT5663_ALC_PGA_CTL_6 0x0335
+#define RT5663_ALC_PGA_CTL_7 0x0336
+#define RT5663_ALC_PGA_CTL_8 0x0337
+#define RT5663_ALC_PGA_REG_1 0x0338
+#define RT5663_ALC_PGA_REG_2 0x0339
+#define RT5663_ALC_PGA_REG_3 0x033a
+#define RT5663_ADC_EQ_RECOV_1 0x03c0
+#define RT5663_ADC_EQ_RECOV_2 0x03c1
+#define RT5663_ADC_EQ_RECOV_3 0x03c2
+#define RT5663_ADC_EQ_RECOV_4 0x03c3
+#define RT5663_ADC_EQ_RECOV_5 0x03c4
+#define RT5663_ADC_EQ_RECOV_6 0x03c5
+#define RT5663_ADC_EQ_RECOV_7 0x03c6
+#define RT5663_ADC_EQ_RECOV_8 0x03c7
+#define RT5663_ADC_EQ_RECOV_9 0x03c8
+#define RT5663_ADC_EQ_RECOV_10 0x03c9
+#define RT5663_ADC_EQ_RECOV_11 0x03ca
+#define RT5663_ADC_EQ_RECOV_12 0x03cb
+#define RT5663_ADC_EQ_RECOV_13 0x03cc
+#define RT5663_VID_HIDDEN 0x03fe
+#define RT5663_VID_CUSTOMER 0x03ff
+#define RT5663_SCAN_MODE 0x07f0
+#define RT5663_I2C_BYPA 0x07fa
/* Headphone Amp Control 2 (0x0003) */
-#define RT5668_EN_DAC_HPO_MASK (0x1 << 14)
-#define RT5668_EN_DAC_HPO_SHIFT 14
-#define RT5668_EN_DAC_HPO_DIS (0x0 << 14)
-#define RT5668_EN_DAC_HPO_EN (0x1 << 14)
+#define RT5663_EN_DAC_HPO_MASK (0x1 << 14)
+#define RT5663_EN_DAC_HPO_SHIFT 14
+#define RT5663_EN_DAC_HPO_DIS (0x0 << 14)
+#define RT5663_EN_DAC_HPO_EN (0x1 << 14)
/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
-#define RT5668_GAIN_HP (0x1f << 8)
-#define RT5668_GAIN_HP_SHIFT 8
+#define RT5663_GAIN_HP (0x1f << 8)
+#define RT5663_GAIN_HP_SHIFT 8
/* AEC BST Control (0x000b) */
-#define RT5668_GAIN_CBJ_MASK (0xf << 8)
-#define RT5668_GAIN_CBJ_SHIFT 8
+#define RT5663_GAIN_CBJ_MASK (0xf << 8)
+#define RT5663_GAIN_CBJ_SHIFT 8
/* IN1 Control / MIC GND REF (0x000c) */
-#define RT5668_IN1_DF_MASK (0x1 << 15)
-#define RT5668_IN1_DF_SHIFT 15
+#define RT5663_IN1_DF_MASK (0x1 << 15)
+#define RT5663_IN1_DF_SHIFT 15
/* Combo Jack and Type Detection Control 1 (0x0010) */
-#define RT5668_CBJ_DET_MASK (0x1 << 15)
-#define RT5668_CBJ_DET_SHIFT 15
-#define RT5668_CBJ_DET_DIS (0x0 << 15)
-#define RT5668_CBJ_DET_EN (0x1 << 15)
-#define RT5668_DET_TYPE_MASK (0x1 << 12)
-#define RT5668_DET_TYPE_SHIFT 12
-#define RT5668_DET_TYPE_WLCSP (0x0 << 12)
-#define RT5668_DET_TYPE_QFN (0x1 << 12)
-#define RT5668_VREF_BIAS_MASK (0x1 << 6)
-#define RT5668_VREF_BIAS_SHIFT 6
-#define RT5668_VREF_BIAS_FSM (0x0 << 6)
-#define RT5668_VREF_BIAS_REG (0x1 << 6)
+#define RT5663_CBJ_DET_MASK (0x1 << 15)
+#define RT5663_CBJ_DET_SHIFT 15
+#define RT5663_CBJ_DET_DIS (0x0 << 15)
+#define RT5663_CBJ_DET_EN (0x1 << 15)
+#define RT5663_DET_TYPE_MASK (0x1 << 12)
+#define RT5663_DET_TYPE_SHIFT 12
+#define RT5663_DET_TYPE_WLCSP (0x0 << 12)
+#define RT5663_DET_TYPE_QFN (0x1 << 12)
+#define RT5663_VREF_BIAS_MASK (0x1 << 6)
+#define RT5663_VREF_BIAS_SHIFT 6
+#define RT5663_VREF_BIAS_FSM (0x0 << 6)
+#define RT5663_VREF_BIAS_REG (0x1 << 6)
/* REC Left Mixer Control 2 (0x003c) */
-#define RT5668_RECMIX1L_BST1_CBJ (0x1 << 7)
-#define RT5668_RECMIX1L_BST1_CBJ_SHIFT 7
-#define RT5668_RECMIX1L_BST2 (0x1 << 4)
-#define RT5668_RECMIX1L_BST2_SHIFT 4
+#define RT5663_RECMIX1L_BST1_CBJ (0x1 << 7)
+#define RT5663_RECMIX1L_BST1_CBJ_SHIFT 7
+#define RT5663_RECMIX1L_BST2 (0x1 << 4)
+#define RT5663_RECMIX1L_BST2_SHIFT 4
/* REC Right Mixer Control 2 (0x003e) */
-#define RT5668_RECMIX1R_BST2 (0x1 << 4)
-#define RT5668_RECMIX1R_BST2_SHIFT 4
+#define RT5663_RECMIX1R_BST2 (0x1 << 4)
+#define RT5663_RECMIX1R_BST2_SHIFT 4
/* DAC1 Digital Volume (0x0019) */
-#define RT5668_DAC_L1_VOL_MASK (0xff << 8)
-#define RT5668_DAC_L1_VOL_SHIFT 8
-#define RT5668_DAC_R1_VOL_MASK (0xff)
-#define RT5668_DAC_R1_VOL_SHIFT 0
+#define RT5663_DAC_L1_VOL_MASK (0xff << 8)
+#define RT5663_DAC_L1_VOL_SHIFT 8
+#define RT5663_DAC_R1_VOL_MASK (0xff)
+#define RT5663_DAC_R1_VOL_SHIFT 0
/* ADC Digital Volume Control (0x001c) */
-#define RT5668_ADC_L_MUTE_MASK (0x1 << 15)
-#define RT5668_ADC_L_MUTE_SHIFT 15
-#define RT5668_ADC_L_VOL_MASK (0x7f << 8)
-#define RT5668_ADC_L_VOL_SHIFT 8
-#define RT5668_ADC_R_MUTE_MASK (0x1 << 7)
-#define RT5668_ADC_R_MUTE_SHIFT 7
-#define RT5668_ADC_R_VOL_MASK (0x7f)
-#define RT5668_ADC_R_VOL_SHIFT 0
+#define RT5663_ADC_L_MUTE_MASK (0x1 << 15)
+#define RT5663_ADC_L_MUTE_SHIFT 15
+#define RT5663_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5663_ADC_L_VOL_SHIFT 8
+#define RT5663_ADC_R_MUTE_MASK (0x1 << 7)
+#define RT5663_ADC_R_MUTE_SHIFT 7
+#define RT5663_ADC_R_VOL_MASK (0x7f)
+#define RT5663_ADC_R_VOL_SHIFT 0
/* Stereo ADC Mixer Control (0x0026) */
-#define RT5668_M_STO1_ADC_L1 (0x1 << 15)
-#define RT5668_M_STO1_ADC_L1_SHIFT 15
-#define RT5668_M_STO1_ADC_L2 (0x1 << 14)
-#define RT5668_M_STO1_ADC_L2_SHIFT 14
-#define RT5668_STO1_ADC_L1_SRC (0x1 << 13)
-#define RT5668_STO1_ADC_L1_SRC_SHIFT 13
-#define RT5668_STO1_ADC_L2_SRC (0x1 << 12)
-#define RT5668_STO1_ADC_L2_SRC_SHIFT 12
-#define RT5668_STO1_ADC_L_SRC (0x3 << 10)
-#define RT5668_STO1_ADC_L_SRC_SHIFT 10
-#define RT5668_M_STO1_ADC_R1 (0x1 << 7)
-#define RT5668_M_STO1_ADC_R1_SHIFT 7
-#define RT5668_M_STO1_ADC_R2 (0x1 << 6)
-#define RT5668_M_STO1_ADC_R2_SHIFT 6
-#define RT5668_STO1_ADC_R1_SRC (0x1 << 5)
-#define RT5668_STO1_ADC_R1_SRC_SHIFT 5
-#define RT5668_STO1_ADC_R2_SRC (0x1 << 4)
-#define RT5668_STO1_ADC_R2_SRC_SHIFT 4
-#define RT5668_STO1_ADC_R_SRC (0x3 << 2)
-#define RT5668_STO1_ADC_R_SRC_SHIFT 2
+#define RT5663_M_STO1_ADC_L1 (0x1 << 15)
+#define RT5663_M_STO1_ADC_L1_SHIFT 15
+#define RT5663_M_STO1_ADC_L2 (0x1 << 14)
+#define RT5663_M_STO1_ADC_L2_SHIFT 14
+#define RT5663_STO1_ADC_L1_SRC (0x1 << 13)
+#define RT5663_STO1_ADC_L1_SRC_SHIFT 13
+#define RT5663_STO1_ADC_L2_SRC (0x1 << 12)
+#define RT5663_STO1_ADC_L2_SRC_SHIFT 12
+#define RT5663_STO1_ADC_L_SRC (0x3 << 10)
+#define RT5663_STO1_ADC_L_SRC_SHIFT 10
+#define RT5663_M_STO1_ADC_R1 (0x1 << 7)
+#define RT5663_M_STO1_ADC_R1_SHIFT 7
+#define RT5663_M_STO1_ADC_R2 (0x1 << 6)
+#define RT5663_M_STO1_ADC_R2_SHIFT 6
+#define RT5663_STO1_ADC_R1_SRC (0x1 << 5)
+#define RT5663_STO1_ADC_R1_SRC_SHIFT 5
+#define RT5663_STO1_ADC_R2_SRC (0x1 << 4)
+#define RT5663_STO1_ADC_R2_SRC_SHIFT 4
+#define RT5663_STO1_ADC_R_SRC (0x3 << 2)
+#define RT5663_STO1_ADC_R_SRC_SHIFT 2
/* ADC Mixer to DAC Mixer Control (0x0029) */
-#define RT5668_M_ADCMIX_L (0x1 << 15)
-#define RT5668_M_ADCMIX_L_SHIFT 15
-#define RT5668_M_DAC1_L (0x1 << 14)
-#define RT5668_M_DAC1_L_SHIFT 14
-#define RT5668_M_ADCMIX_R (0x1 << 7)
-#define RT5668_M_ADCMIX_R_SHIFT 7
-#define RT5668_M_DAC1_R (0x1 << 6)
-#define RT5668_M_DAC1_R_SHIFT 6
+#define RT5663_M_ADCMIX_L (0x1 << 15)
+#define RT5663_M_ADCMIX_L_SHIFT 15
+#define RT5663_M_DAC1_L (0x1 << 14)
+#define RT5663_M_DAC1_L_SHIFT 14
+#define RT5663_M_ADCMIX_R (0x1 << 7)
+#define RT5663_M_ADCMIX_R_SHIFT 7
+#define RT5663_M_DAC1_R (0x1 << 6)
+#define RT5663_M_DAC1_R_SHIFT 6
/* Stereo DAC Mixer Control (0x002a) */
-#define RT5668_M_DAC_L1_STO_L (0x1 << 15)
-#define RT5668_M_DAC_L1_STO_L_SHIFT 15
-#define RT5668_M_DAC_R1_STO_L (0x1 << 13)
-#define RT5668_M_DAC_R1_STO_L_SHIFT 13
-#define RT5668_M_DAC_L1_STO_R (0x1 << 7)
-#define RT5668_M_DAC_L1_STO_R_SHIFT 7
-#define RT5668_M_DAC_R1_STO_R (0x1 << 5)
-#define RT5668_M_DAC_R1_STO_R_SHIFT 5
+#define RT5663_M_DAC_L1_STO_L (0x1 << 15)
+#define RT5663_M_DAC_L1_STO_L_SHIFT 15
+#define RT5663_M_DAC_R1_STO_L (0x1 << 13)
+#define RT5663_M_DAC_R1_STO_L_SHIFT 13
+#define RT5663_M_DAC_L1_STO_R (0x1 << 7)
+#define RT5663_M_DAC_L1_STO_R_SHIFT 7
+#define RT5663_M_DAC_R1_STO_R (0x1 << 5)
+#define RT5663_M_DAC_R1_STO_R_SHIFT 5
/* Power Management for Digital 1 (0x0061) */
-#define RT5668_PWR_I2S1 (0x1 << 15)
-#define RT5668_PWR_I2S1_SHIFT 15
-#define RT5668_PWR_DAC_L1 (0x1 << 11)
-#define RT5668_PWR_DAC_L1_SHIFT 11
-#define RT5668_PWR_DAC_R1 (0x1 << 10)
-#define RT5668_PWR_DAC_R1_SHIFT 10
-#define RT5668_PWR_LDO_DACREF_MASK (0x1 << 8)
-#define RT5668_PWR_LDO_DACREF_SHIFT 8
-#define RT5668_PWR_LDO_DACREF_ON (0x1 << 8)
-#define RT5668_PWR_LDO_DACREF_DOWN (0x0 << 8)
-#define RT5668_PWR_LDO_SHIFT 8
-#define RT5668_PWR_ADC_L1 (0x1 << 4)
-#define RT5668_PWR_ADC_L1_SHIFT 4
-#define RT5668_PWR_ADC_R1 (0x1 << 3)
-#define RT5668_PWR_ADC_R1_SHIFT 3
+#define RT5663_PWR_I2S1 (0x1 << 15)
+#define RT5663_PWR_I2S1_SHIFT 15
+#define RT5663_PWR_DAC_L1 (0x1 << 11)
+#define RT5663_PWR_DAC_L1_SHIFT 11
+#define RT5663_PWR_DAC_R1 (0x1 << 10)
+#define RT5663_PWR_DAC_R1_SHIFT 10
+#define RT5663_PWR_LDO_DACREF_MASK (0x1 << 8)
+#define RT5663_PWR_LDO_DACREF_SHIFT 8
+#define RT5663_PWR_LDO_DACREF_ON (0x1 << 8)
+#define RT5663_PWR_LDO_DACREF_DOWN (0x0 << 8)
+#define RT5663_PWR_LDO_SHIFT 8
+#define RT5663_PWR_ADC_L1 (0x1 << 4)
+#define RT5663_PWR_ADC_L1_SHIFT 4
+#define RT5663_PWR_ADC_R1 (0x1 << 3)
+#define RT5663_PWR_ADC_R1_SHIFT 3
/* Power Management for Digital 2 (0x0062) */
-#define RT5668_PWR_ADC_S1F (0x1 << 15)
-#define RT5668_PWR_ADC_S1F_SHIFT 15
-#define RT5668_PWR_DAC_S1F (0x1 << 10)
-#define RT5668_PWR_DAC_S1F_SHIFT 10
+#define RT5663_PWR_ADC_S1F (0x1 << 15)
+#define RT5663_PWR_ADC_S1F_SHIFT 15
+#define RT5663_PWR_DAC_S1F (0x1 << 10)
+#define RT5663_PWR_DAC_S1F_SHIFT 10
/* Power Management for Analog 1 (0x0063) */
-#define RT5668_PWR_VREF1 (0x1 << 15)
-#define RT5668_PWR_VREF1_MASK (0x1 << 15)
-#define RT5668_PWR_VREF1_SHIFT 15
-#define RT5668_PWR_FV1 (0x1 << 14)
-#define RT5668_PWR_FV1_MASK (0x1 << 14)
-#define RT5668_PWR_FV1_SHIFT 14
-#define RT5668_PWR_VREF2 (0x1 << 13)
-#define RT5668_PWR_VREF2_MASK (0x1 << 13)
-#define RT5668_PWR_VREF2_SHIFT 13
-#define RT5668_PWR_FV2 (0x1 << 12)
-#define RT5668_PWR_FV2_MASK (0x1 << 12)
-#define RT5668_PWR_FV2_SHIFT 12
-#define RT5668_PWR_MB (0x1 << 9)
-#define RT5668_PWR_MB_MASK (0x1 << 9)
-#define RT5668_PWR_MB_SHIFT 9
-#define RT5668_AMP_HP_MASK (0x3 << 2)
-#define RT5668_AMP_HP_SHIFT 2
-#define RT5668_AMP_HP_1X (0x0 << 2)
-#define RT5668_AMP_HP_3X (0x1 << 2)
-#define RT5668_AMP_HP_5X (0x3 << 2)
-#define RT5668_LDO1_DVO_MASK (0x3)
-#define RT5668_LDO1_DVO_SHIFT 0
-#define RT5668_LDO1_DVO_0_9V (0x0)
-#define RT5668_LDO1_DVO_1_0V (0x1)
-#define RT5668_LDO1_DVO_1_2V (0x2)
-#define RT5668_LDO1_DVO_1_4V (0x3)
+#define RT5663_PWR_VREF1 (0x1 << 15)
+#define RT5663_PWR_VREF1_MASK (0x1 << 15)
+#define RT5663_PWR_VREF1_SHIFT 15
+#define RT5663_PWR_FV1 (0x1 << 14)
+#define RT5663_PWR_FV1_MASK (0x1 << 14)
+#define RT5663_PWR_FV1_SHIFT 14
+#define RT5663_PWR_VREF2 (0x1 << 13)
+#define RT5663_PWR_VREF2_MASK (0x1 << 13)
+#define RT5663_PWR_VREF2_SHIFT 13
+#define RT5663_PWR_FV2 (0x1 << 12)
+#define RT5663_PWR_FV2_MASK (0x1 << 12)
+#define RT5663_PWR_FV2_SHIFT 12
+#define RT5663_PWR_MB (0x1 << 9)
+#define RT5663_PWR_MB_MASK (0x1 << 9)
+#define RT5663_PWR_MB_SHIFT 9
+#define RT5663_AMP_HP_MASK (0x3 << 2)
+#define RT5663_AMP_HP_SHIFT 2
+#define RT5663_AMP_HP_1X (0x0 << 2)
+#define RT5663_AMP_HP_3X (0x1 << 2)
+#define RT5663_AMP_HP_5X (0x3 << 2)
+#define RT5663_LDO1_DVO_MASK (0x3)
+#define RT5663_LDO1_DVO_SHIFT 0
+#define RT5663_LDO1_DVO_0_9V (0x0)
+#define RT5663_LDO1_DVO_1_0V (0x1)
+#define RT5663_LDO1_DVO_1_2V (0x2)
+#define RT5663_LDO1_DVO_1_4V (0x3)
/* Power Management for Analog 2 (0x0064) */
-#define RT5668_PWR_BST1 (0x1 << 15)
-#define RT5668_PWR_BST1_MASK (0x1 << 15)
-#define RT5668_PWR_BST1_SHIFT 15
-#define RT5668_PWR_BST1_OFF (0x0 << 15)
-#define RT5668_PWR_BST1_ON (0x1 << 15)
-#define RT5668_PWR_BST2 (0x1 << 14)
-#define RT5668_PWR_BST2_MASK (0x1 << 14)
-#define RT5668_PWR_BST2_SHIFT 14
-#define RT5668_PWR_MB1 (0x1 << 11)
-#define RT5668_PWR_MB1_SHIFT 11
-#define RT5668_PWR_MB2 (0x1 << 10)
-#define RT5668_PWR_MB2_SHIFT 10
-#define RT5668_PWR_BST2_OP (0x1 << 6)
-#define RT5668_PWR_BST2_OP_MASK (0x1 << 6)
-#define RT5668_PWR_BST2_OP_SHIFT 6
-#define RT5668_PWR_JD1 (0x1 << 3)
-#define RT5668_PWR_JD1_MASK (0x1 << 3)
-#define RT5668_PWR_JD1_SHIFT 3
-#define RT5668_PWR_JD2 (0x1 << 2)
-#define RT5668_PWR_JD2_MASK (0x1 << 2)
-#define RT5668_PWR_JD2_SHIFT 2
-#define RT5668_PWR_RECMIX1 (0x1 << 1)
-#define RT5668_PWR_RECMIX1_SHIFT 1
-#define RT5668_PWR_RECMIX2 (0x1)
-#define RT5668_PWR_RECMIX2_SHIFT 0
+#define RT5663_PWR_BST1 (0x1 << 15)
+#define RT5663_PWR_BST1_MASK (0x1 << 15)
+#define RT5663_PWR_BST1_SHIFT 15
+#define RT5663_PWR_BST1_OFF (0x0 << 15)
+#define RT5663_PWR_BST1_ON (0x1 << 15)
+#define RT5663_PWR_BST2 (0x1 << 14)
+#define RT5663_PWR_BST2_MASK (0x1 << 14)
+#define RT5663_PWR_BST2_SHIFT 14
+#define RT5663_PWR_MB1 (0x1 << 11)
+#define RT5663_PWR_MB1_SHIFT 11
+#define RT5663_PWR_MB2 (0x1 << 10)
+#define RT5663_PWR_MB2_SHIFT 10
+#define RT5663_PWR_BST2_OP (0x1 << 6)
+#define RT5663_PWR_BST2_OP_MASK (0x1 << 6)
+#define RT5663_PWR_BST2_OP_SHIFT 6
+#define RT5663_PWR_JD1 (0x1 << 3)
+#define RT5663_PWR_JD1_MASK (0x1 << 3)
+#define RT5663_PWR_JD1_SHIFT 3
+#define RT5663_PWR_JD2 (0x1 << 2)
+#define RT5663_PWR_JD2_MASK (0x1 << 2)
+#define RT5663_PWR_JD2_SHIFT 2
+#define RT5663_PWR_RECMIX1 (0x1 << 1)
+#define RT5663_PWR_RECMIX1_SHIFT 1
+#define RT5663_PWR_RECMIX2 (0x1)
+#define RT5663_PWR_RECMIX2_SHIFT 0
/* Power Management for Analog 3 (0x0065) */
-#define RT5668_PWR_CBJ_MASK (0x1 << 9)
-#define RT5668_PWR_CBJ_SHIFT 9
-#define RT5668_PWR_CBJ_OFF (0x0 << 9)
-#define RT5668_PWR_CBJ_ON (0x1 << 9)
-#define RT5668_PWR_PLL (0x1 << 6)
-#define RT5668_PWR_PLL_SHIFT 6
-#define RT5668_PWR_LDO2 (0x1 << 2)
-#define RT5668_PWR_LDO2_SHIFT 2
+#define RT5663_PWR_CBJ_MASK (0x1 << 9)
+#define RT5663_PWR_CBJ_SHIFT 9
+#define RT5663_PWR_CBJ_OFF (0x0 << 9)
+#define RT5663_PWR_CBJ_ON (0x1 << 9)
+#define RT5663_PWR_PLL (0x1 << 6)
+#define RT5663_PWR_PLL_SHIFT 6
+#define RT5663_PWR_LDO2 (0x1 << 2)
+#define RT5663_PWR_LDO2_SHIFT 2
/* Power Management for Volume (0x0067) */
-#define RT5668_PWR_MIC_DET (0x1 << 5)
-#define RT5668_PWR_MIC_DET_SHIFT 5
+#define RT5663_V2_PWR_MIC_DET (0x1 << 5)
+#define RT5663_V2_PWR_MIC_DET_SHIFT 5
/* MCLK and System Clock Detection Control (0x006b) */
-#define RT5668_EN_ANA_CLK_DET_MASK (0x1 << 15)
-#define RT5668_EN_ANA_CLK_DET_SHIFT 15
-#define RT5668_EN_ANA_CLK_DET_DIS (0x0 << 15)
-#define RT5668_EN_ANA_CLK_DET_AUTO (0x1 << 15)
-#define RT5668_PWR_CLK_DET_MASK (0x1)
-#define RT5668_PWR_CLK_DET_SHIFT 0
-#define RT5668_PWR_CLK_DET_DIS (0x0)
-#define RT5668_PWR_CLK_DET_EN (0x1)
+#define RT5663_EN_ANA_CLK_DET_MASK (0x1 << 15)
+#define RT5663_EN_ANA_CLK_DET_SHIFT 15
+#define RT5663_EN_ANA_CLK_DET_DIS (0x0 << 15)
+#define RT5663_EN_ANA_CLK_DET_AUTO (0x1 << 15)
+#define RT5663_PWR_CLK_DET_MASK (0x1)
+#define RT5663_PWR_CLK_DET_SHIFT 0
+#define RT5663_PWR_CLK_DET_DIS (0x0)
+#define RT5663_PWR_CLK_DET_EN (0x1)
/* I2S1 Audio Serial Data Port Control (0x0070) */
-#define RT5668_I2S_MS_MASK (0x1 << 15)
-#define RT5668_I2S_MS_SHIFT 15
-#define RT5668_I2S_MS_M (0x0 << 15)
-#define RT5668_I2S_MS_S (0x1 << 15)
-#define RT5668_I2S_BP_MASK (0x1 << 8)
-#define RT5668_I2S_BP_SHIFT 8
-#define RT5668_I2S_BP_NOR (0x0 << 8)
-#define RT5668_I2S_BP_INV (0x1 << 8)
-#define RT5668_I2S_DL_MASK (0x3 << 4)
-#define RT5668_I2S_DL_SHIFT 4
-#define RT5668_I2S_DL_16 (0x0 << 4)
-#define RT5668_I2S_DL_20 (0x1 << 4)
-#define RT5668_I2S_DL_24 (0x2 << 4)
-#define RT5668_I2S_DL_8 (0x3 << 4)
-#define RT5668_I2S_DF_MASK (0x7)
-#define RT5668_I2S_DF_SHIFT 0
-#define RT5668_I2S_DF_I2S (0x0)
-#define RT5668_I2S_DF_LEFT (0x1)
-#define RT5668_I2S_DF_PCM_A (0x2)
-#define RT5668_I2S_DF_PCM_B (0x3)
-#define RT5668_I2S_DF_PCM_A_N (0x6)
-#define RT5668_I2S_DF_PCM_B_N (0x7)
+#define RT5663_I2S_MS_MASK (0x1 << 15)
+#define RT5663_I2S_MS_SHIFT 15
+#define RT5663_I2S_MS_M (0x0 << 15)
+#define RT5663_I2S_MS_S (0x1 << 15)
+#define RT5663_I2S_BP_MASK (0x1 << 8)
+#define RT5663_I2S_BP_SHIFT 8
+#define RT5663_I2S_BP_NOR (0x0 << 8)
+#define RT5663_I2S_BP_INV (0x1 << 8)
+#define RT5663_I2S_DL_MASK (0x3 << 4)
+#define RT5663_I2S_DL_SHIFT 4
+#define RT5663_I2S_DL_16 (0x0 << 4)
+#define RT5663_I2S_DL_20 (0x1 << 4)
+#define RT5663_I2S_DL_24 (0x2 << 4)
+#define RT5663_I2S_DL_8 (0x3 << 4)
+#define RT5663_I2S_DF_MASK (0x7)
+#define RT5663_I2S_DF_SHIFT 0
+#define RT5663_I2S_DF_I2S (0x0)
+#define RT5663_I2S_DF_LEFT (0x1)
+#define RT5663_I2S_DF_PCM_A (0x2)
+#define RT5663_I2S_DF_PCM_B (0x3)
+#define RT5663_I2S_DF_PCM_A_N (0x6)
+#define RT5663_I2S_DF_PCM_B_N (0x7)
/* ADC/DAC Clock Control 1 (0x0073) */
-#define RT5668_I2S_PD1_MASK (0x7 << 12)
-#define RT5668_I2S_PD1_SHIFT 12
-#define RT5668_M_I2S_DIV_MASK (0x7 << 8)
-#define RT5668_M_I2S_DIV_SHIFT 8
-#define RT5668_CLK_SRC_MASK (0x3 << 4)
-#define RT5668_CLK_SRC_MCLK (0x0 << 4)
-#define RT5668_CLK_SRC_PLL_OUT (0x1 << 4)
-#define RT5668_CLK_SRC_DIV (0x2 << 4)
-#define RT5668_CLK_SRC_RC (0x3 << 4)
-#define RT5668_DAC_OSR_MASK (0x3 << 2)
-#define RT5668_DAC_OSR_SHIFT 2
-#define RT5668_DAC_OSR_128 (0x0 << 2)
-#define RT5668_DAC_OSR_64 (0x1 << 2)
-#define RT5668_DAC_OSR_32 (0x2 << 2)
-#define RT5668_ADC_OSR_MASK (0x3)
-#define RT5668_ADC_OSR_SHIFT 0
-#define RT5668_ADC_OSR_128 (0x0)
-#define RT5668_ADC_OSR_64 (0x1)
-#define RT5668_ADC_OSR_32 (0x2)
+#define RT5663_I2S_PD1_MASK (0x7 << 12)
+#define RT5663_I2S_PD1_SHIFT 12
+#define RT5663_M_I2S_DIV_MASK (0x7 << 8)
+#define RT5663_M_I2S_DIV_SHIFT 8
+#define RT5663_CLK_SRC_MASK (0x3 << 4)
+#define RT5663_CLK_SRC_MCLK (0x0 << 4)
+#define RT5663_CLK_SRC_PLL_OUT (0x1 << 4)
+#define RT5663_CLK_SRC_DIV (0x2 << 4)
+#define RT5663_CLK_SRC_RC (0x3 << 4)
+#define RT5663_DAC_OSR_MASK (0x3 << 2)
+#define RT5663_DAC_OSR_SHIFT 2
+#define RT5663_DAC_OSR_128 (0x0 << 2)
+#define RT5663_DAC_OSR_64 (0x1 << 2)
+#define RT5663_DAC_OSR_32 (0x2 << 2)
+#define RT5663_ADC_OSR_MASK (0x3)
+#define RT5663_ADC_OSR_SHIFT 0
+#define RT5663_ADC_OSR_128 (0x0)
+#define RT5663_ADC_OSR_64 (0x1)
+#define RT5663_ADC_OSR_32 (0x2)
/* TDM1 control 1 (0x0078) */
-#define RT5668_TDM_MODE_MASK (0x1 << 15)
-#define RT5668_TDM_MODE_SHIFT 15
-#define RT5668_TDM_MODE_I2S (0x0 << 15)
-#define RT5668_TDM_MODE_TDM (0x1 << 15)
-#define RT5668_TDM_IN_CH_MASK (0x3 << 10)
-#define RT5668_TDM_IN_CH_SHIFT 10
-#define RT5668_TDM_IN_CH_2 (0x0 << 10)
-#define RT5668_TDM_IN_CH_4 (0x1 << 10)
-#define RT5668_TDM_IN_CH_6 (0x2 << 10)
-#define RT5668_TDM_IN_CH_8 (0x3 << 10)
-#define RT5668_TDM_OUT_CH_MASK (0x3 << 8)
-#define RT5668_TDM_OUT_CH_SHIFT 8
-#define RT5668_TDM_OUT_CH_2 (0x0 << 8)
-#define RT5668_TDM_OUT_CH_4 (0x1 << 8)
-#define RT5668_TDM_OUT_CH_6 (0x2 << 8)
-#define RT5668_TDM_OUT_CH_8 (0x3 << 8)
-#define RT5668_TDM_IN_LEN_MASK (0x3 << 6)
-#define RT5668_TDM_IN_LEN_SHIFT 6
-#define RT5668_TDM_IN_LEN_16 (0x0 << 6)
-#define RT5668_TDM_IN_LEN_20 (0x1 << 6)
-#define RT5668_TDM_IN_LEN_24 (0x2 << 6)
-#define RT5668_TDM_IN_LEN_32 (0x3 << 6)
-#define RT5668_TDM_OUT_LEN_MASK (0x3 << 4)
-#define RT5668_TDM_OUT_LEN_SHIFT 4
-#define RT5668_TDM_OUT_LEN_16 (0x0 << 4)
-#define RT5668_TDM_OUT_LEN_20 (0x1 << 4)
-#define RT5668_TDM_OUT_LEN_24 (0x2 << 4)
-#define RT5668_TDM_OUT_LEN_32 (0x3 << 4)
+#define RT5663_TDM_MODE_MASK (0x1 << 15)
+#define RT5663_TDM_MODE_SHIFT 15
+#define RT5663_TDM_MODE_I2S (0x0 << 15)
+#define RT5663_TDM_MODE_TDM (0x1 << 15)
+#define RT5663_TDM_IN_CH_MASK (0x3 << 10)
+#define RT5663_TDM_IN_CH_SHIFT 10
+#define RT5663_TDM_IN_CH_2 (0x0 << 10)
+#define RT5663_TDM_IN_CH_4 (0x1 << 10)
+#define RT5663_TDM_IN_CH_6 (0x2 << 10)
+#define RT5663_TDM_IN_CH_8 (0x3 << 10)
+#define RT5663_TDM_OUT_CH_MASK (0x3 << 8)
+#define RT5663_TDM_OUT_CH_SHIFT 8
+#define RT5663_TDM_OUT_CH_2 (0x0 << 8)
+#define RT5663_TDM_OUT_CH_4 (0x1 << 8)
+#define RT5663_TDM_OUT_CH_6 (0x2 << 8)
+#define RT5663_TDM_OUT_CH_8 (0x3 << 8)
+#define RT5663_TDM_IN_LEN_MASK (0x3 << 6)
+#define RT5663_TDM_IN_LEN_SHIFT 6
+#define RT5663_TDM_IN_LEN_16 (0x0 << 6)
+#define RT5663_TDM_IN_LEN_20 (0x1 << 6)
+#define RT5663_TDM_IN_LEN_24 (0x2 << 6)
+#define RT5663_TDM_IN_LEN_32 (0x3 << 6)
+#define RT5663_TDM_OUT_LEN_MASK (0x3 << 4)
+#define RT5663_TDM_OUT_LEN_SHIFT 4
+#define RT5663_TDM_OUT_LEN_16 (0x0 << 4)
+#define RT5663_TDM_OUT_LEN_20 (0x1 << 4)
+#define RT5663_TDM_OUT_LEN_24 (0x2 << 4)
+#define RT5663_TDM_OUT_LEN_32 (0x3 << 4)
/* Global Clock Control (0x0080) */
-#define RT5668_SCLK_SRC_MASK (0x3 << 14)
-#define RT5668_SCLK_SRC_SHIFT 14
-#define RT5668_SCLK_SRC_MCLK (0x0 << 14)
-#define RT5668_SCLK_SRC_PLL1 (0x1 << 14)
-#define RT5668_SCLK_SRC_RCCLK (0x2 << 14)
-#define RT5668_PLL1_SRC_MASK (0x7 << 8)
-#define RT5668_PLL1_SRC_SHIFT 8
-#define RT5668_PLL1_SRC_MCLK (0x0 << 8)
-#define RT5668_PLL1_SRC_BCLK1 (0x1 << 8)
-#define RT5668_PLL1_PD_MASK (0x1 << 4)
-#define RT5668_PLL1_PD_SHIFT 4
-
-#define RT5668_PLL_INP_MAX 40000000
-#define RT5668_PLL_INP_MIN 256000
+#define RT5663_SCLK_SRC_MASK (0x3 << 14)
+#define RT5663_SCLK_SRC_SHIFT 14
+#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
+#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
+#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
+#define RT5663_PLL1_SRC_MASK (0x7 << 11)
+#define RT5663_PLL1_SRC_SHIFT 11
+#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
+#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
+#define RT5663_V2_PLL1_SRC_MASK (0x7 << 8)
+#define RT5663_V2_PLL1_SRC_SHIFT 8
+#define RT5663_V2_PLL1_SRC_MCLK (0x0 << 8)
+#define RT5663_V2_PLL1_SRC_BCLK1 (0x1 << 8)
+#define RT5663_PLL1_PD_MASK (0x1 << 4)
+#define RT5663_PLL1_PD_SHIFT 4
+
+#define RT5663_PLL_INP_MAX 40000000
+#define RT5663_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x0081) */
-#define RT5668_PLL_N_MAX 0x001ff
-#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)
-#define RT5668_PLL_N_SHIFT 7
-#define RT5668_PLL_K_MAX 0x001f
-#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)
-#define RT5668_PLL_K_SHIFT 0
+#define RT5663_PLL_N_MAX 0x001ff
+#define RT5663_PLL_N_MASK (RT5663_PLL_N_MAX << 7)
+#define RT5663_PLL_N_SHIFT 7
+#define RT5663_PLL_K_MAX 0x001f
+#define RT5663_PLL_K_MASK (RT5663_PLL_K_MAX)
+#define RT5663_PLL_K_SHIFT 0
/* PLL M/N/K Code Control 2 (0x0082) */
-#define RT5668_PLL_M_MAX 0x00f
-#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
-#define RT5668_PLL_M_SHIFT 12
-#define RT5668_PLL_M_BP (0x1 << 11)
-#define RT5668_PLL_M_BP_SHIFT 11
+#define RT5663_PLL_M_MAX 0x00f
+#define RT5663_PLL_M_MASK (RT5663_PLL_M_MAX << 12)
+#define RT5663_PLL_M_SHIFT 12
+#define RT5663_PLL_M_BP (0x1 << 11)
+#define RT5663_PLL_M_BP_SHIFT 11
/* PLL tracking mode 1 (0x0083) */
-#define RT5668_I2S1_ASRC_MASK (0x1 << 13)
-#define RT5668_I2S1_ASRC_SHIFT 13
-#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
-#define RT5668_DAC_STO1_ASRC_SHIFT 12
-#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 4)
-#define RT5668_ADC_STO1_ASRC_SHIFT 4
+#define RT5663_V2_I2S1_ASRC_MASK (0x1 << 13)
+#define RT5663_V2_I2S1_ASRC_SHIFT 13
+#define RT5663_V2_DAC_STO1_ASRC_MASK (0x1 << 12)
+#define RT5663_V2_DAC_STO1_ASRC_SHIFT 12
+#define RT5663_V2_ADC_STO1_ASRC_MASK (0x1 << 4)
+#define RT5663_V2_ADC_STO1_ASRC_SHIFT 4
/* PLL tracking mode 2 (0x0084)*/
-#define RT5668_DA_STO1_TRACK_MASK (0x7 << 12)
-#define RT5668_DA_STO1_TRACK_SHIFT 12
-#define RT5668_DA_STO1_TRACK_SYSCLK (0x0 << 12)
-#define RT5668_DA_STO1_TRACK_I2S1 (0x1 << 12)
+#define RT5663_DA_STO1_TRACK_MASK (0x7 << 12)
+#define RT5663_DA_STO1_TRACK_SHIFT 12
+#define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12)
+#define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12)
/* PLL tracking mode 3 (0x0085)*/
-#define RT5668_AD_STO1_TRACK_MASK (0x7 << 12)
-#define RT5668_AD_STO1_TRACK_SHIFT 12
-#define RT5668_AD_STO1_TRACK_SYSCLK (0x0 << 12)
-#define RT5668_AD_STO1_TRACK_I2S1 (0x1 << 12)
+#define RT5663_V2_AD_STO1_TRACK_MASK (0x7 << 12)
+#define RT5663_V2_AD_STO1_TRACK_SHIFT 12
+#define RT5663_V2_AD_STO1_TRACK_SYSCLK (0x0 << 12)
+#define RT5663_V2_AD_STO1_TRACK_I2S1 (0x1 << 12)
/* HPOUT Charge pump control 1 (0x0091) */
-#define RT5668_OSW_HP_L_MASK (0x1 << 11)
-#define RT5668_OSW_HP_L_SHIFT 11
-#define RT5668_OSW_HP_L_EN (0x1 << 11)
-#define RT5668_OSW_HP_L_DIS (0x0 << 11)
-#define RT5668_OSW_HP_R_MASK (0x1 << 10)
-#define RT5668_OSW_HP_R_SHIFT 10
-#define RT5668_OSW_HP_R_EN (0x1 << 10)
-#define RT5668_OSW_HP_R_DIS (0x0 << 10)
-#define RT5668_SEL_PM_HP_MASK (0x3 << 8)
-#define RT5668_SEL_PM_HP_SHIFT 8
-#define RT5668_SEL_PM_HP_0_6 (0x0 << 8)
-#define RT5668_SEL_PM_HP_0_9 (0x1 << 8)
-#define RT5668_SEL_PM_HP_1_8 (0x2 << 8)
-#define RT5668_SEL_PM_HP_HIGH (0x3 << 8)
-#define RT5668_OVCD_HP_MASK (0x1 << 2)
-#define RT5668_OVCD_HP_SHIFT 2
-#define RT5668_OVCD_HP_EN (0x1 << 2)
-#define RT5668_OVCD_HP_DIS (0x0 << 2)
+#define RT5663_OSW_HP_L_MASK (0x1 << 11)
+#define RT5663_OSW_HP_L_SHIFT 11
+#define RT5663_OSW_HP_L_EN (0x1 << 11)
+#define RT5663_OSW_HP_L_DIS (0x0 << 11)
+#define RT5663_OSW_HP_R_MASK (0x1 << 10)
+#define RT5663_OSW_HP_R_SHIFT 10
+#define RT5663_OSW_HP_R_EN (0x1 << 10)
+#define RT5663_OSW_HP_R_DIS (0x0 << 10)
+#define RT5663_SEL_PM_HP_MASK (0x3 << 8)
+#define RT5663_SEL_PM_HP_SHIFT 8
+#define RT5663_SEL_PM_HP_0_6 (0x0 << 8)
+#define RT5663_SEL_PM_HP_0_9 (0x1 << 8)
+#define RT5663_SEL_PM_HP_1_8 (0x2 << 8)
+#define RT5663_SEL_PM_HP_HIGH (0x3 << 8)
+#define RT5663_OVCD_HP_MASK (0x1 << 2)
+#define RT5663_OVCD_HP_SHIFT 2
+#define RT5663_OVCD_HP_EN (0x1 << 2)
+#define RT5663_OVCD_HP_DIS (0x0 << 2)
/* RC Clock Control (0x0094) */
-#define RT5668_DIG_25M_CLK_MASK (0x1 << 9)
-#define RT5668_DIG_25M_CLK_SHIFT 9
-#define RT5668_DIG_25M_CLK_DIS (0x0 << 9)
-#define RT5668_DIG_25M_CLK_EN (0x1 << 9)
-#define RT5668_DIG_1M_CLK_MASK (0x1 << 8)
-#define RT5668_DIG_1M_CLK_SHIFT 8
-#define RT5668_DIG_1M_CLK_DIS (0x0 << 8)
-#define RT5668_DIG_1M_CLK_EN (0x1 << 8)
+#define RT5663_DIG_25M_CLK_MASK (0x1 << 9)
+#define RT5663_DIG_25M_CLK_SHIFT 9
+#define RT5663_DIG_25M_CLK_DIS (0x0 << 9)
+#define RT5663_DIG_25M_CLK_EN (0x1 << 9)
+#define RT5663_DIG_1M_CLK_MASK (0x1 << 8)
+#define RT5663_DIG_1M_CLK_SHIFT 8
+#define RT5663_DIG_1M_CLK_DIS (0x0 << 8)
+#define RT5663_DIG_1M_CLK_EN (0x1 << 8)
/* Auto Turn On 1M RC CLK (0x009f) */
-#define RT5668_IRQ_POW_SAV_MASK (0x1 << 15)
-#define RT5668_IRQ_POW_SAV_SHIFT 15
-#define RT5668_IRQ_POW_SAV_DIS (0x0 << 15)
-#define RT5668_IRQ_POW_SAV_EN (0x1 << 15)
-#define RT5668_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
-#define RT5668_IRQ_POW_SAV_JD1_SHIFT 14
-#define RT5668_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
-#define RT5668_IRQ_POW_SAV_JD1_EN (0x1 << 14)
+#define RT5663_IRQ_POW_SAV_MASK (0x1 << 15)
+#define RT5663_IRQ_POW_SAV_SHIFT 15
+#define RT5663_IRQ_POW_SAV_DIS (0x0 << 15)
+#define RT5663_IRQ_POW_SAV_EN (0x1 << 15)
+#define RT5663_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
+#define RT5663_IRQ_POW_SAV_JD1_SHIFT 14
+#define RT5663_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
+#define RT5663_IRQ_POW_SAV_JD1_EN (0x1 << 14)
/* IRQ Control 1 (0x00b6) */
-#define RT5668_EN_CB_JD_MASK (0x1 << 3)
-#define RT5668_EN_CB_JD_SHIFT 3
-#define RT5668_EN_CB_JD_EN (0x1 << 3)
-#define RT5668_EN_CB_JD_DIS (0x0 << 3)
+#define RT5663_EN_CB_JD_MASK (0x1 << 3)
+#define RT5663_EN_CB_JD_SHIFT 3
+#define RT5663_EN_CB_JD_EN (0x1 << 3)
+#define RT5663_EN_CB_JD_DIS (0x0 << 3)
/* IRQ Control 3 (0x00b8) */
-#define RT5668_EN_IRQ_INLINE_MASK (0x1 << 6)
-#define RT5668_EN_IRQ_INLINE_SHIFT 6
-#define RT5668_EN_IRQ_INLINE_BYP (0x0 << 6)
-#define RT5668_EN_IRQ_INLINE_NOR (0x1 << 6)
+#define RT5663_V2_EN_IRQ_INLINE_MASK (0x1 << 6)
+#define RT5663_V2_EN_IRQ_INLINE_SHIFT 6
+#define RT5663_V2_EN_IRQ_INLINE_BYP (0x0 << 6)
+#define RT5663_V2_EN_IRQ_INLINE_NOR (0x1 << 6)
/* GPIO Control 1 (0x00c0) */
-#define RT5668_GP1_PIN_MASK (0x1 << 15)
-#define RT5668_GP1_PIN_SHIFT 15
-#define RT5668_GP1_PIN_GPIO1 (0x0 << 15)
-#define RT5668_GP1_PIN_IRQ (0x1 << 15)
+#define RT5663_GP1_PIN_MASK (0x1 << 15)
+#define RT5663_GP1_PIN_SHIFT 15
+#define RT5663_GP1_PIN_GPIO1 (0x0 << 15)
+#define RT5663_GP1_PIN_IRQ (0x1 << 15)
/* GPIO Control 2 (0x00c1) */
-#define RT5668_GP4_PIN_CONF_MASK (0x1 << 5)
-#define RT5668_GP4_PIN_CONF_SHIFT 5
-#define RT5668_GP4_PIN_CONF_INPUT (0x0 << 5)
-#define RT5668_GP4_PIN_CONF_OUTPUT (0x1 << 5)
+#define RT5663_GP4_PIN_CONF_MASK (0x1 << 5)
+#define RT5663_GP4_PIN_CONF_SHIFT 5
+#define RT5663_GP4_PIN_CONF_INPUT (0x0 << 5)
+#define RT5663_GP4_PIN_CONF_OUTPUT (0x1 << 5)
/* GPIO Control 2 (0x00c2) */
-#define RT5668_GP8_PIN_CONF_MASK (0x1 << 13)
-#define RT5668_GP8_PIN_CONF_SHIFT 13
-#define RT5668_GP8_PIN_CONF_INPUT (0x0 << 13)
-#define RT5668_GP8_PIN_CONF_OUTPUT (0x1 << 13)
+#define RT5663_GP8_PIN_CONF_MASK (0x1 << 13)
+#define RT5663_GP8_PIN_CONF_SHIFT 13
+#define RT5663_GP8_PIN_CONF_INPUT (0x0 << 13)
+#define RT5663_GP8_PIN_CONF_OUTPUT (0x1 << 13)
/* 4 Buttons Inline Command Function 1 (0x00df) */
-#define RT5668_4BTN_CLK_DEB_MASK (0x3 << 2)
-#define RT5668_4BTN_CLK_DEB_SHIFT 2
-#define RT5668_4BTN_CLK_DEB_8MS (0x0 << 2)
-#define RT5668_4BTN_CLK_DEB_16MS (0x1 << 2)
-#define RT5668_4BTN_CLK_DEB_32MS (0x2 << 2)
-#define RT5668_4BTN_CLK_DEB_65MS (0x3 << 2)
+#define RT5663_4BTN_CLK_DEB_MASK (0x3 << 2)
+#define RT5663_4BTN_CLK_DEB_SHIFT 2
+#define RT5663_4BTN_CLK_DEB_8MS (0x0 << 2)
+#define RT5663_4BTN_CLK_DEB_16MS (0x1 << 2)
+#define RT5663_4BTN_CLK_DEB_32MS (0x2 << 2)
+#define RT5663_4BTN_CLK_DEB_65MS (0x3 << 2)
/* Inline Command Function 6 (0x00e0) */
-#define RT5668_EN_4BTN_INL_MASK (0x1 << 15)
-#define RT5668_EN_4BTN_INL_SHIFT 15
-#define RT5668_EN_4BTN_INL_DIS (0x0 << 15)
-#define RT5668_EN_4BTN_INL_EN (0x1 << 15)
-#define RT5668_RESET_4BTN_INL_MASK (0x1 << 14)
-#define RT5668_RESET_4BTN_INL_SHIFT 14
-#define RT5668_RESET_4BTN_INL_RESET (0x0 << 14)
-#define RT5668_RESET_4BTN_INL_NOR (0x1 << 14)
+#define RT5663_EN_4BTN_INL_MASK (0x1 << 15)
+#define RT5663_EN_4BTN_INL_SHIFT 15
+#define RT5663_EN_4BTN_INL_DIS (0x0 << 15)
+#define RT5663_EN_4BTN_INL_EN (0x1 << 15)
+#define RT5663_RESET_4BTN_INL_MASK (0x1 << 14)
+#define RT5663_RESET_4BTN_INL_SHIFT 14
+#define RT5663_RESET_4BTN_INL_RESET (0x0 << 14)
+#define RT5663_RESET_4BTN_INL_NOR (0x1 << 14)
/* Digital Misc Control (0x00fa) */
-#define RT5668_DIG_GATE_CTRL_MASK 0x1
-#define RT5668_DIG_GATE_CTRL_SHIFT (0)
-#define RT5668_DIG_GATE_CTRL_DIS 0x0
-#define RT5668_DIG_GATE_CTRL_EN 0x1
+#define RT5663_DIG_GATE_CTRL_MASK 0x1
+#define RT5663_DIG_GATE_CTRL_SHIFT (0)
+#define RT5663_DIG_GATE_CTRL_DIS 0x0
+#define RT5663_DIG_GATE_CTRL_EN 0x1
/* Chopper and Clock control for DAC L (0x013a)*/
-#define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
-#define RT5668_CKXEN_DAC1_SHIFT 13
-#define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
-#define RT5668_CKGEN_DAC1_SHIFT 12
+#define RT5663_CKXEN_DAC1_MASK (0x1 << 13)
+#define RT5663_CKXEN_DAC1_SHIFT 13
+#define RT5663_CKGEN_DAC1_MASK (0x1 << 12)
+#define RT5663_CKGEN_DAC1_SHIFT 12
/* Chopper and Clock control for ADC (0x013b)*/
-#define RT5668_CKXEN_ADCC_MASK (0x1 << 13)
-#define RT5668_CKXEN_ADCC_SHIFT 13
-#define RT5668_CKGEN_ADCC_MASK (0x1 << 12)
-#define RT5668_CKGEN_ADCC_SHIFT 12
+#define RT5663_CKXEN_ADCC_MASK (0x1 << 13)
+#define RT5663_CKXEN_ADCC_SHIFT 13
+#define RT5663_CKGEN_ADCC_MASK (0x1 << 12)
+#define RT5663_CKGEN_ADCC_SHIFT 12
/* HP Behavior Logic Control 2 (0x01db) */
-#define RT5668_HP_SIG_SRC1_MASK (0x3)
-#define RT5668_HP_SIG_SRC1_SHIFT 0
-#define RT5668_HP_SIG_SRC1_HP_DC (0x0)
-#define RT5668_HP_SIG_SRC1_HP_CALIB (0x1)
-#define RT5668_HP_SIG_SRC1_REG (0x2)
-#define RT5668_HP_SIG_SRC1_SILENCE (0x3)
+#define RT5663_HP_SIG_SRC1_MASK (0x3)
+#define RT5663_HP_SIG_SRC1_SHIFT 0
+#define RT5663_HP_SIG_SRC1_HP_DC (0x0)
+#define RT5663_HP_SIG_SRC1_HP_CALIB (0x1)
+#define RT5663_HP_SIG_SRC1_REG (0x2)
+#define RT5663_HP_SIG_SRC1_SILENCE (0x3)
/* RT5663 specific register */
#define RT5663_HP_OUT_EN 0x0002
@@ -707,6 +704,10 @@
#define RT5663_TDM_3 0x0079
#define RT5663_TDM_4 0x007a
#define RT5663_TDM_5 0x007b
+#define RT5663_TDM_6 0x007c
+#define RT5663_TDM_7 0x007d
+#define RT5663_TDM_8 0x007e
+#define RT5663_TDM_9 0x007f
#define RT5663_GLB_CLK 0x0080
#define RT5663_PLL_1 0x0081
#define RT5663_PLL_2 0x0082
@@ -739,7 +740,7 @@
#define RT5663_INT_ST_2 0x00bf
#define RT5663_GPIO_1 0x00c0
#define RT5663_GPIO_2 0x00c1
-#define RT5663_GPIO_STA 0x00c5
+#define RT5663_GPIO_STA1 0x00c5
#define RT5663_SIN_GEN_1 0x00cb
#define RT5663_SIN_GEN_2 0x00cc
#define RT5663_SIN_GEN_3 0x00cd
@@ -800,6 +801,8 @@
#define RT5663_TEST_MODE_1 0x0144
#define RT5663_TEST_MODE_2 0x0145
#define RT5663_TEST_MODE_3 0x0146
+#define RT5663_TEST_MODE_4 0x0147
+#define RT5663_TEST_MODE_5 0x0148
#define RT5663_STO_DRE_1 0x0160
#define RT5663_STO_DRE_2 0x0161
#define RT5663_STO_DRE_3 0x0162
@@ -921,19 +924,19 @@
#define RT5663_ADC_EQ_POST_VOL_L 0x03f2
#define RT5663_ADC_EQ_POST_VOL_R 0x03f3
-/* RT5663: RECMIX Control (0x0010) */
+/* RECMIX Control (0x0010) */
#define RT5663_RECMIX1_BST1_MASK (0x1)
#define RT5663_RECMIX1_BST1_SHIFT 0
#define RT5663_RECMIX1_BST1_ON (0x0)
#define RT5663_RECMIX1_BST1_OFF (0x1)
-/* RT5663: Bypass Stereo1 DAC Mixer Control (0x002d) */
+/* Bypass Stereo1 DAC Mixer Control (0x002d) */
#define RT5663_DACL1_SRC_MASK (0x1 << 3)
#define RT5663_DACL1_SRC_SHIFT 3
#define RT5663_DACR1_SRC_MASK (0x1 << 2)
#define RT5663_DACR1_SRC_SHIFT 2
-/* RT5663: TDM control 2 (0x0078) */
+/* TDM control 2 (0x0078) */
#define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14)
#define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14
#define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14)
@@ -941,7 +944,7 @@
#define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14)
#define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14)
-/* RT5663: TDM control 5 (0x007b) */
+/* TDM control 5 (0x007b) */
#define RT5663_TDM_LENGTN_MASK (0x3)
#define RT5663_TDM_LENGTN_SHIFT 0
#define RT5663_TDM_LENGTN_16 (0x0)
@@ -949,17 +952,6 @@
#define RT5663_TDM_LENGTN_24 (0x2)
#define RT5663_TDM_LENGTN_32 (0x3)
-/* RT5663: Global Clock Control (0x0080) */
-#define RT5663_SCLK_SRC_MASK (0x3 << 14)
-#define RT5663_SCLK_SRC_SHIFT 14
-#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
-#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
-#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
-#define RT5663_PLL1_SRC_MASK (0x7 << 11)
-#define RT5663_PLL1_SRC_SHIFT 11
-#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
-#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
-
/* PLL tracking mode 1 (0x0083) */
#define RT5663_I2S1_ASRC_MASK (0x1 << 11)
#define RT5663_I2S1_ASRC_SHIFT 11
@@ -978,31 +970,31 @@
#define RT5663_AD_STO1_TRACK_SYSCLK (0x0)
#define RT5663_AD_STO1_TRACK_I2S1 (0x1)
-/* RT5663: HPOUT Charge pump control 1 (0x0091) */
+/* HPOUT Charge pump control 1 (0x0091) */
#define RT5663_SI_HP_MASK (0x1 << 12)
#define RT5663_SI_HP_SHIFT 12
#define RT5663_SI_HP_EN (0x1 << 12)
#define RT5663_SI_HP_DIS (0x0 << 12)
-/* RT5663: GPIO Control 2 (0x00b6) */
+/* GPIO Control 2 (0x00b6) */
#define RT5663_GP1_PIN_CONF_MASK (0x1 << 2)
#define RT5663_GP1_PIN_CONF_SHIFT 2
#define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2)
#define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2)
-/* RT5663: GPIO Control 2 (0x00b7) */
+/* GPIO Control 2 (0x00b7) */
#define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3)
#define RT5663_EN_IRQ_INLINE_SHIFT 3
#define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3)
#define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3)
-/* RT5663: GPIO Control 1 (0x00c0) */
+/* GPIO Control 1 (0x00c0) */
#define RT5663_GPIO1_TYPE_MASK (0x1 << 15)
#define RT5663_GPIO1_TYPE_SHIFT 15
#define RT5663_GPIO1_TYPE_EN (0x1 << 15)
#define RT5663_GPIO1_TYPE_DIS (0x0 << 15)
-/* RT5663: IRQ Control 1 (0x00c1) */
+/* IRQ Control 1 (0x00c1) */
#define RT5663_EN_IRQ_JD1_MASK (0x1 << 6)
#define RT5663_EN_IRQ_JD1_SHIFT 6
#define RT5663_EN_IRQ_JD1_EN (0x1 << 6)
@@ -1012,13 +1004,13 @@
#define RT5663_SEL_GPIO1_EN (0x1 << 2)
#define RT5663_SEL_GPIO1_DIS (0x0 << 2)
-/* RT5663: Inline Command Function 2 (0x00dc) */
+/* Inline Command Function 2 (0x00dc) */
#define RT5663_PWR_MIC_DET_MASK (0x1)
#define RT5663_PWR_MIC_DET_SHIFT 0
#define RT5663_PWR_MIC_DET_ON (0x1)
#define RT5663_PWR_MIC_DET_OFF (0x0)
-/* RT5663: Embeeded Jack and Type Detection Control 1 (0x00e6)*/
+/* Embeeded Jack and Type Detection Control 1 (0x00e6)*/
#define RT5663_CBJ_DET_MASK (0x1 << 15)
#define RT5663_CBJ_DET_SHIFT 15
#define RT5663_CBJ_DET_DIS (0x0 << 15)
@@ -1032,17 +1024,17 @@
#define RT5663_POL_EXT_JD_EN (0x1 << 10)
#define RT5663_POL_EXT_JD_DIS (0x0 << 10)
-/* RT5663: DACREF LDO Control (0x0112)*/
+/* DACREF LDO Control (0x0112)*/
#define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9)
#define RT5663_PWR_LDO_DACREFL_SHIFT 9
#define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1)
#define RT5663_PWR_LDO_DACREFR_SHIFT 1
-/* RT5663: Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
+/* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
#define RT5663_DRE_GAIN_HP_MASK (0x1f)
#define RT5663_DRE_GAIN_HP_SHIFT 0
-/* RT5663: Combo Jack Control (0x0250) */
+/* Combo Jack Control (0x0250) */
#define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11)
#define RT5663_INBUF_CBJ_BST1_SHIFT 11
#define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11)
@@ -1052,11 +1044,11 @@
#define RT5663_CBJ_SENSE_BST1_L (0x1 << 10)
#define RT5663_CBJ_SENSE_BST1_R (0x0 << 10)
-/* RT5663: Combo Jack Control (0x0251) */
+/* Combo Jack Control (0x0251) */
#define RT5663_GAIN_BST1_MASK (0xf)
#define RT5663_GAIN_BST1_SHIFT 0
-/* RT5663: Dummy register 1 (0x02fa) */
+/* Dummy register 1 (0x02fa) */
#define RT5663_EMB_CLK_MASK (0x1 << 9)
#define RT5663_EMB_CLK_SHIFT 9
#define RT5663_EMB_CLK_EN (0x1 << 9)
--
cgit v1.2.3
From 585e881e5b9e9b495978e93fcf4ed3fedb0b8cdb Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Thu, 20 Oct 2016 15:20:45 +0100
Subject: ASoC: codecs: Add msm8916-wcd analog codec
msm8916-wcd codec is found in Qualcomm msm8916 and apq8016 processors.
This codec IP is split in to two parts (Digital & Analog).
Analog part is integrated in to PMIC PM8916 and the digital part is
integrated into Application processor. Data transfer between Analog and
Digital Die is done via a internal bus called PDM.
This patch adds support to Analog part of the Codec which is integrated
into PMIC PM8916.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../bindings/sound/qcom,msm8916-wcd-analog.txt | 85 ++
sound/soc/codecs/Kconfig | 4 +
sound/soc/codecs/Makefile | 3 +-
sound/soc/codecs/msm8916-wcd-analog.c | 890 +++++++++++++++++++++
4 files changed, 981 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt
create mode 100644 sound/soc/codecs/msm8916-wcd-analog.c
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt
new file mode 100644
index 000000000000..ccb401cfef9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt
@@ -0,0 +1,85 @@
+msm8916 analog audio CODEC
+
+Bindings for codec Analog IP which is integrated in pmic pm8916,
+
+## Bindings for codec core on pmic:
+
+Required properties
+ - compatible = "qcom,pm8916-wcd-analog-codec";
+ - reg: represents the slave base address provided to the peripheral.
+ - interrupt-parent : The parent interrupt controller.
+ - interrupts: List of interrupts in given SPMI peripheral.
+ - interrupt-names: Names specified to above list of interrupts in same
+ order. List of supported interrupt names are:
+ "cdc_spk_cnp_int" - Speaker click and pop interrupt.
+ "cdc_spk_clip_int" - Speaker clip interrupt.
+ "cdc_spk_ocp_int" - Speaker over current protect interrupt.
+ "mbhc_ins_rem_det1" - jack insert removal detect interrupt 1.
+ "mbhc_but_rel_det" - button release interrupt.
+ "mbhc_but_press_det" - button press event
+ "mbhc_ins_rem_det" - jack insert removal detect interrupt.
+ "mbhc_switch_int" - multi button headset interrupt.
+ "cdc_ear_ocp_int" - Earphone over current protect interrupt.
+ "cdc_hphr_ocp_int" - Headphone R over current protect interrupt.
+ "cdc_hphl_ocp_det" - Headphone L over current protect interrupt.
+ "cdc_ear_cnp_int" - earphone cnp interrupt.
+ "cdc_hphr_cnp_int" - hphr click and pop interrupt.
+ "cdc_hphl_cnp_int" - hphl click and pop interrupt.
+
+ - clocks: Handle to mclk.
+ - clock-names: should be "mclk"
+ - vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node.
+ - vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node.
+ - vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node.
+
+Optional Properties:
+- qcom,micbias1-ext-cap: boolean, present if micbias1 has external capacitor
+ connected.
+- qcom,micbias2-ext-cap: boolean, present if micbias2 has external capacitor
+ connected.
+
+Example:
+
+spmi_bus {
+ ...
+ audio-codec@f000{
+ compatible = "qcom,pm8916-wcd-analog-codec";
+ reg = <0xf000 0x200>;
+ reg-names = "pmic-codec-core";
+ clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
+ clock-names = "mclk";
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "cdc_spk_cnp_int",
+ "cdc_spk_clip_int",
+ "cdc_spk_ocp_int",
+ "mbhc_ins_rem_det1",
+ "mbhc_but_rel_det",
+ "mbhc_but_press_det",
+ "mbhc_ins_rem_det",
+ "mbhc_switch_int",
+ "cdc_ear_ocp_int",
+ "cdc_hphr_ocp_int",
+ "cdc_hphl_ocp_det",
+ "cdc_ear_cnp_int",
+ "cdc_hphr_cnp_int",
+ "cdc_hphl_cnp_int";
+ VDD-CDC-IO-supply = <&pm8916_l5>;
+ VDD-CDC-TX-RX-CX-supply = <&pm8916_l5>;
+ VDD-MICBIAS-supply = <&pm8916_l13>;
+ #sound-dai-cells = <1>;
+ };
+};
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c67667bb970f..4a98ce65b993 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -581,6 +581,10 @@ config SND_SOC_MAX9860
depends on I2C
select REGMAP_I2C
+config SND_SOC_MSM8916_WCD_ANALOG
+ tristate "Qualcomm MSM8916 WCD Analog Codec"
+ depends on SPMI || COMPILE_TEST
+
config SND_SOC_PCM1681
tristate "Texas Instruments PCM1681 CODEC"
depends on I2C
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 958cd4912fbc..32d90184f764 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -86,6 +86,7 @@ snd-soc-max9850-objs := max9850.o
snd-soc-max9860-objs := max9860.o
snd-soc-mc13783-objs := mc13783.o
snd-soc-ml26124-objs := ml26124.o
+snd-soc-msm8916-analog-objs := msm8916-wcd-analog.o
snd-soc-nau8810-objs := nau8810.o
snd-soc-nau8825-objs := nau8825.o
snd-soc-hdmi-codec-objs := hdmi-codec.o
@@ -214,7 +215,6 @@ snd-soc-wm9705-objs := wm9705.o
snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
snd-soc-wm-hubs-objs := wm_hubs.o
-
# Amp
snd-soc-max9877-objs := max9877.o
snd-soc-max98504-objs := max98504.o
@@ -310,6 +310,7 @@ obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
+obj-$(CONFIG_SND_SOC_MSM8916_WCD_ANALOG) +=snd-soc-msm8916-analog.o
obj-$(CONFIG_SND_SOC_NAU8810) += snd-soc-nau8810.o
obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o
obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o
diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c
new file mode 100644
index 000000000000..d9f999b14b28
--- /dev/null
+++ b/sound/soc/codecs/msm8916-wcd-analog.c
@@ -0,0 +1,890 @@
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/tlv.h>
+
+#define CDC_D_REVISION1 (0xf000)
+#define CDC_D_PERPH_SUBTYPE (0xf005)
+#define CDC_D_CDC_RST_CTL (0xf046)
+#define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
+#define RST_CTL_DIG_SW_RST_N_RESET 0
+#define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
+
+#define CDC_D_CDC_TOP_CLK_CTL (0xf048)
+#define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
+#define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
+#define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
+
+#define CDC_D_CDC_ANA_CLK_CTL (0xf049)
+#define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
+#define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
+#define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
+#define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
+#define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
+#define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
+
+#define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
+#define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
+#define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
+#define DIG_CLK_CTL_RXD3_CLK_EN BIT(3)
+#define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
+#define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
+#define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
+#define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
+#define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
+
+#define CDC_D_CDC_CONN_TX1_CTL (0xf050)
+#define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
+#define CONN_TX1_SERIAL_TX1_ADC_1 0x0
+#define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
+#define CONN_TX1_SERIAL_TX1_ZERO 0x2
+
+#define CDC_D_CDC_CONN_TX2_CTL (0xf051)
+#define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
+#define CONN_TX2_SERIAL_TX2_ADC_2 0x0
+#define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
+#define CONN_TX2_SERIAL_TX2_ZERO 0x2
+#define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
+#define CDC_D_CDC_CONN_RX1_CTL (0xf053)
+#define CDC_D_CDC_CONN_RX2_CTL (0xf054)
+#define CDC_D_CDC_CONN_RX3_CTL (0xf055)
+#define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
+#define CDC_D_SEC_ACCESS (0xf0D0)
+#define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
+#define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
+#define CDC_A_REVISION1 (0xf100)
+#define CDC_A_REVISION2 (0xf101)
+#define CDC_A_REVISION3 (0xf102)
+#define CDC_A_REVISION4 (0xf103)
+#define CDC_A_PERPH_TYPE (0xf104)
+#define CDC_A_PERPH_SUBTYPE (0xf105)
+#define CDC_A_INT_RT_STS (0xf110)
+#define CDC_A_INT_SET_TYPE (0xf111)
+#define CDC_A_INT_POLARITY_HIGH (0xf112)
+#define CDC_A_INT_POLARITY_LOW (0xf113)
+#define CDC_A_INT_LATCHED_CLR (0xf114)
+#define CDC_A_INT_EN_SET (0xf115)
+#define CDC_A_INT_EN_CLR (0xf116)
+#define CDC_A_INT_LATCHED_STS (0xf118)
+#define CDC_A_INT_PENDING_STS (0xf119)
+#define CDC_A_INT_MID_SEL (0xf11A)
+#define CDC_A_INT_PRIORITY (0xf11B)
+#define CDC_A_MICB_1_EN (0xf140)
+#define MICB_1_EN_MICB_ENABLE BIT(7)
+#define MICB_1_EN_BYP_CAP_MASK BIT(6)
+#define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
+#define MICB_1_EN_EXT_BYP_CAP 0
+#define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
+#define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
+#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
+#define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
+#define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
+#define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
+#define MICB_1_EN_TX3_GND_SEL_TX_GND 0
+
+#define CDC_A_MICB_1_VAL (0xf141)
+#define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
+#define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
+#define CDC_A_MICB_1_CTL (0xf142)
+
+#define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
+#define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
+#define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
+#define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
+#define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
+#define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
+
+#define CDC_A_MICB_1_INT_RBIAS (0xf143)
+#define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
+#define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
+#define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
+
+#define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
+#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
+#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
+
+#define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
+#define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
+#define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
+#define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
+#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
+#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
+
+#define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
+#define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
+#define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
+#define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
+#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
+#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
+
+#define CDC_A_MICB_2_EN (0xf144)
+#define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
+#define CDC_A_MASTER_BIAS_CTL (0xf146)
+#define CDC_A_TX_1_EN (0xf160)
+#define CDC_A_TX_2_EN (0xf161)
+#define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
+#define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
+#define CDC_A_TX_1_2_ATEST_CTL (0xf164)
+#define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
+#define CDC_A_TX_3_EN (0xf167)
+#define CDC_A_NCP_EN (0xf180)
+#define CDC_A_NCP_CLK (0xf181)
+#define CDC_A_NCP_FBCTRL (0xf183)
+#define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
+#define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
+#define CDC_A_NCP_BIAS (0xf184)
+#define CDC_A_NCP_VCTRL (0xf185)
+#define CDC_A_NCP_TEST (0xf186)
+#define CDC_A_NCP_CLIM_ADDR (0xf187)
+#define CDC_A_RX_CLOCK_DIVIDER (0xf190)
+#define CDC_A_RX_COM_OCP_CTL (0xf191)
+#define CDC_A_RX_COM_OCP_COUNT (0xf192)
+#define CDC_A_RX_COM_BIAS_DAC (0xf193)
+#define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
+#define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
+#define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
+#define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
+
+#define CDC_A_RX_HPH_BIAS_PA (0xf194)
+#define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
+#define CDC_A_RX_HPH_BIAS_CNP (0xf196)
+#define CDC_A_RX_HPH_CNP_EN (0xf197)
+#define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
+#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
+#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
+#define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
+#define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
+#define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
+
+#define CDC_A_RX_EAR_CTL (0xf19E)
+#define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
+#define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
+
+#define CDC_A_SPKR_DAC_CTL (0xf1B0)
+#define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
+#define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
+
+#define CDC_A_SPKR_DRV_CTL (0xf1B2)
+#define SPKR_DRV_CTL_DEF_MASK 0xEF
+#define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
+#define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
+#define SPKR_DRV_CAL_EN BIT(6)
+#define SPKR_DRV_SETTLE_EN BIT(5)
+#define SPKR_DRV_FW_EN BIT(3)
+#define SPKR_DRV_BOOST_SET BIT(2)
+#define SPKR_DRV_CMFB_SET BIT(1)
+#define SPKR_DRV_GAIN_SET BIT(0)
+#define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
+ SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
+ SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
+ SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
+#define CDC_A_SPKR_OCP_CTL (0xf1B4)
+#define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
+#define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
+#define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
+#define SPKR_PWRSTG_CTL_MASK 0xE0
+#define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
+#define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
+#define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
+#define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
+#define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
+#define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
+
+#define CDC_A_SPKR_DRV_DBG (0xf1B7)
+#define CDC_A_CURRENT_LIMIT (0xf1C0)
+#define CDC_A_BOOST_EN_CTL (0xf1C3)
+#define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
+#define CDC_A_SEC_ACCESS (0xf1D0)
+#define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
+#define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
+
+#define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
+#define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+static const char * const supply_names[] = {
+ "vdd-cdc-io",
+ "vdd-cdc-tx-rx-cx",
+};
+
+struct pm8916_wcd_analog_priv {
+ u16 pmic_rev;
+ u16 codec_version;
+ struct clk *mclk;
+ struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
+ bool micbias1_cap_mode;
+ bool micbias2_cap_mode;
+};
+
+static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
+static const char *const rdac2_mux_text[] = { "ZERO", "RX2", "RX1" };
+static const char *const hph_text[] = { "ZERO", "Switch", };
+
+static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
+ ARRAY_SIZE(hph_text), hph_text);
+
+static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
+static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
+
+/* ADC2 MUX */
+static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
+ ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
+
+/* RDAC2 MUX */
+static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
+ CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 3, rdac2_mux_text);
+
+static const struct snd_kcontrol_new spkr_switch[] = {
+ SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
+};
+
+static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
+ "RDAC2 MUX Mux", rdac2_mux_enum);
+static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
+ "ADC2 MUX Mux", adc2_enum);
+
+/* Analog Gain control 0 dB to +24 dB in 6 dB steps */
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
+
+static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
+ SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
+ SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
+ SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
+};
+
+static void pm8916_wcd_analog_micbias_enable(struct snd_soc_codec *codec)
+{
+ snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
+ MICB_1_CTL_EXT_PRECHARG_EN_MASK |
+ MICB_1_CTL_INT_PRECHARG_BYP_MASK,
+ MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
+ | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
+
+ snd_soc_write(codec, CDC_A_MICB_1_VAL, MICB_1_VAL_MICB_OUT_VAL_V2P70V);
+ /*
+ * Special headset needs MICBIAS as 2.7V so wait for
+ * 50 msec for the MICBIAS to reach 2.7 volts.
+ */
+ msleep(50);
+ snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
+ MICB_1_CTL_EXT_PRECHARG_EN_MASK |
+ MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
+
+}
+
+static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_codec
+ *codec, int event,
+ int reg, u32 cap_mode)
+{
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ pm8916_wcd_analog_micbias_enable(codec);
+ snd_soc_update_bits(codec, CDC_A_MICB_1_EN,
+ MICB_1_EN_BYP_CAP_MASK, cap_mode);
+ break;
+ }
+
+ return 0;
+}
+
+static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_codec
+ *codec, int event,
+ int reg, u32 cap_mode)
+{
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, CDC_A_MICB_1_INT_RBIAS,
+ MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
+ MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
+ snd_soc_update_bits(codec, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0);
+ snd_soc_update_bits(codec, CDC_A_MICB_1_EN,
+ MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
+ MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
+
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ pm8916_wcd_analog_micbias_enable(codec);
+ snd_soc_update_bits(codec, CDC_A_MICB_1_EN,
+ MICB_1_EN_BYP_CAP_MASK, cap_mode);
+ break;
+ }
+
+ return 0;
+}
+
+static int pm8916_wcd_analog_enable_micbias_ext1(struct
+ snd_soc_dapm_widget
+ *w, struct snd_kcontrol
+ *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
+
+ return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg,
+ wcd->micbias1_cap_mode);
+}
+
+static int pm8916_wcd_analog_enable_micbias_ext2(struct
+ snd_soc_dapm_widget
+ *w, struct snd_kcontrol
+ *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
+
+ return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg,
+ wcd->micbias2_cap_mode);
+
+}
+
+static int pm8916_wcd_analog_enable_micbias_int2(struct
+ snd_soc_dapm_widget
+ *w, struct snd_kcontrol
+ *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
+
+ return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg,
+ wcd->micbias2_cap_mode);
+}
+
+static int pm8916_wcd_analog_enable_micbias_int1(struct
+ snd_soc_dapm_widget
+ *w, struct snd_kcontrol
+ *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
+
+ return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg,
+ wcd->micbias2_cap_mode);
+}
+
+static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
+ u8 init_bit_shift;
+
+ if (w->reg == CDC_A_TX_1_EN)
+ init_bit_shift = 5;
+ else
+ init_bit_shift = 4;
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (w->reg == CDC_A_TX_2_EN)
+ snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
+ MICB_1_CTL_CFILT_REF_SEL_MASK,
+ MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
+ /*
+ * Add delay of 10 ms to give sufficient time for the voltage
+ * to shoot up and settle so that the txfe init does not
+ * happen when the input voltage is changing too much.
+ */
+ usleep_range(10000, 10010);
+ snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
+ 1 << init_bit_shift);
+ switch (w->reg) {
+ case CDC_A_TX_1_EN:
+ snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL,
+ CONN_TX1_SERIAL_TX1_MUX,
+ CONN_TX1_SERIAL_TX1_ADC_1);
+ break;
+ case CDC_A_TX_2_EN:
+ case CDC_A_TX_3_EN:
+ snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL,
+ CONN_TX2_SERIAL_TX2_MUX,
+ CONN_TX2_SERIAL_TX2_ADC_2);
+ break;
+ }
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ /*
+ * Add delay of 12 ms before deasserting the init
+ * to reduce the tx pop
+ */
+ usleep_range(12000, 12010);
+ snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ switch (w->reg) {
+ case CDC_A_TX_1_EN:
+ snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL,
+ CONN_TX1_SERIAL_TX1_MUX,
+ CONN_TX1_SERIAL_TX1_ZERO);
+ break;
+ case CDC_A_TX_2_EN:
+ snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
+ MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
+ case CDC_A_TX_3_EN:
+ snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL,
+ CONN_TX2_SERIAL_TX2_MUX,
+ CONN_TX2_SERIAL_TX2_ZERO);
+ break;
+ }
+
+
+ break;
+ }
+ return 0;
+}
+
+static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL,
+ SPKR_PWRSTG_CTL_DAC_EN_MASK |
+ SPKR_PWRSTG_CTL_BBM_MASK |
+ SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
+ SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
+ SPKR_PWRSTG_CTL_DAC_EN|
+ SPKR_PWRSTG_CTL_BBM_EN |
+ SPKR_PWRSTG_CTL_HBRDGE_EN |
+ SPKR_PWRSTG_CTL_CLAMP_EN);
+
+ snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL,
+ RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
+ RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, CDC_A_SPKR_DRV_CTL,
+ SPKR_DRV_CTL_DEF_MASK,
+ SPKR_DRV_CTL_DEF_VAL);
+ snd_soc_update_bits(codec, w->reg,
+ SPKR_DRV_CLASSD_PA_EN_MASK,
+ SPKR_DRV_CLASSD_PA_EN_ENABLE);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL,
+ SPKR_PWRSTG_CTL_DAC_EN_MASK|
+ SPKR_PWRSTG_CTL_BBM_MASK |
+ SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
+ SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
+
+ snd_soc_update_bits(codec, CDC_A_SPKR_DAC_CTL,
+ SPKR_DAC_CTL_DAC_RESET_MASK,
+ SPKR_DAC_CTL_DAC_RESET_NORMAL);
+ snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL,
+ RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
+ break;
+ }
+ return 0;
+}
+
+static const struct reg_default wcd_reg_defaults_2_0[] = {
+ {CDC_A_RX_COM_OCP_CTL, 0xD1},
+ {CDC_A_RX_COM_OCP_COUNT, 0xFF},
+ {CDC_D_SEC_ACCESS, 0xA5},
+ {CDC_D_PERPH_RESET_CTL3, 0x0F},
+ {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
+ {CDC_A_NCP_FBCTRL, 0x28},
+ {CDC_A_SPKR_DRV_CTL, 0x69},
+ {CDC_A_SPKR_DRV_DBG, 0x01},
+ {CDC_A_BOOST_EN_CTL, 0x5F},
+ {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
+ {CDC_A_SEC_ACCESS, 0xA5},
+ {CDC_A_PERPH_RESET_CTL3, 0x0F},
+ {CDC_A_CURRENT_LIMIT, 0x82},
+ {CDC_A_SPKR_DAC_CTL, 0x03},
+ {CDC_A_SPKR_OCP_CTL, 0xE1},
+ {CDC_A_MASTER_BIAS_CTL, 0x30},
+};
+
+static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
+{
+ struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev);
+ int err, reg;
+
+ err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
+ if (err != 0) {
+ dev_err(codec->dev, "failed to enable regulators (%d)\n", err);
+ return err;
+ }
+
+ snd_soc_codec_set_drvdata(codec, priv);
+ priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
+ priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
+
+ dev_info(codec->dev, "PMIC REV: %d\t CODEC Version: %d\n",
+ priv->pmic_rev, priv->codec_version);
+
+ snd_soc_write(codec, CDC_D_PERPH_RESET_CTL4, 0x01);
+ snd_soc_write(codec, CDC_A_PERPH_RESET_CTL4, 0x01);
+
+ for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
+ snd_soc_write(codec, wcd_reg_defaults_2_0[reg].reg,
+ wcd_reg_defaults_2_0[reg].def);
+
+ return 0;
+}
+
+static int pm8916_wcd_analog_remove(struct snd_soc_codec *codec)
+{
+ struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev);
+
+ return regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
+ priv->supplies);
+}
+
+static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
+
+ {"PDM_RX1", NULL, "PDM Playback"},
+ {"PDM_RX2", NULL, "PDM Playback"},
+ {"PDM_RX3", NULL, "PDM Playback"},
+ {"PDM Capture", NULL, "PDM_TX"},
+
+ /* ADC Connections */
+ {"PDM_TX", NULL, "ADC2"},
+ {"PDM_TX", NULL, "ADC3"},
+ {"ADC2", NULL, "ADC2 MUX"},
+ {"ADC3", NULL, "ADC2 MUX"},
+ {"ADC2 MUX", "INP2", "ADC2_INP2"},
+ {"ADC2 MUX", "INP3", "ADC2_INP3"},
+
+ {"PDM_TX", NULL, "ADC1"},
+ {"ADC1", NULL, "AMIC1"},
+ {"ADC2_INP2", NULL, "AMIC2"},
+ {"ADC2_INP3", NULL, "AMIC3"},
+
+ /* RDAC Connections */
+ {"HPHR DAC", NULL, "RDAC2 MUX"},
+ {"RDAC2 MUX", "RX1", "PDM_RX1"},
+ {"RDAC2 MUX", "RX2", "PDM_RX2"},
+ {"HPHL DAC", NULL, "PDM_RX1"},
+ {"PDM_RX1", NULL, "RXD1_CLK"},
+ {"PDM_RX2", NULL, "RXD2_CLK"},
+ {"PDM_RX3", NULL, "RXD3_CLK"},
+
+ {"PDM_RX1", NULL, "RXD_PDM_CLK"},
+ {"PDM_RX2", NULL, "RXD_PDM_CLK"},
+ {"PDM_RX3", NULL, "RXD_PDM_CLK"},
+
+ {"ADC1", NULL, "TXD_CLK"},
+ {"ADC2", NULL, "TXD_CLK"},
+ {"ADC3", NULL, "TXD_CLK"},
+
+ {"ADC1", NULL, "TXA_CLK25"},
+ {"ADC2", NULL, "TXA_CLK25"},
+ {"ADC3", NULL, "TXA_CLK25"},
+
+ {"PDM_RX1", NULL, "A_MCLK2"},
+ {"PDM_RX2", NULL, "A_MCLK2"},
+ {"PDM_RX3", NULL, "A_MCLK2"},
+
+ {"PDM_TX", NULL, "A_MCLK2"},
+ {"A_MCLK2", NULL, "A_MCLK"},
+
+ /* Headset (RX MIX1 and RX MIX2) */
+ {"HEADPHONE", NULL, "HPHL PA"},
+ {"HEADPHONE", NULL, "HPHR PA"},
+
+ {"HPHL PA", NULL, "EAR_HPHL_CLK"},
+ {"HPHR PA", NULL, "EAR_HPHR_CLK"},
+
+ {"CP", NULL, "NCP_CLK"},
+
+ {"HPHL PA", NULL, "HPHL"},
+ {"HPHR PA", NULL, "HPHR"},
+ {"HPHL PA", NULL, "CP"},
+ {"HPHL PA", NULL, "RX_BIAS"},
+ {"HPHR PA", NULL, "CP"},
+ {"HPHR PA", NULL, "RX_BIAS"},
+ {"HPHL", "Switch", "HPHL DAC"},
+ {"HPHR", "Switch", "HPHR DAC"},
+
+ {"RX_BIAS", NULL, "DAC_REF"},
+
+ {"SPK_OUT", NULL, "SPK PA"},
+ {"SPK PA", NULL, "RX_BIAS"},
+ {"SPK PA", NULL, "SPKR_CLK"},
+ {"SPK PA", NULL, "SPK DAC"},
+ {"SPK DAC", "Switch", "PDM_RX3"},
+
+ {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
+ {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
+ {"MIC BIAS External1", NULL, "INT_LDO_H"},
+ {"MIC BIAS External2", NULL, "INT_LDO_H"},
+ {"MIC BIAS Internal1", NULL, "vdd-micbias"},
+ {"MIC BIAS Internal2", NULL, "vdd-micbias"},
+ {"MIC BIAS External1", NULL, "vdd-micbias"},
+ {"MIC BIAS External2", NULL, "vdd-micbias"},
+};
+
+static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
+
+ SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_INPUT("AMIC1"),
+ SND_SOC_DAPM_INPUT("AMIC3"),
+ SND_SOC_DAPM_INPUT("AMIC2"),
+ SND_SOC_DAPM_OUTPUT("HEADPHONE"),
+
+ /* RX stuff */
+ SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
+
+ SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
+ SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
+ SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
+ 0),
+ SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
+ SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
+ SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
+ 0),
+ SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
+ spkr_switch, ARRAY_SIZE(spkr_switch)),
+
+ /* Speaker */
+ SND_SOC_DAPM_OUTPUT("SPK_OUT"),
+ SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
+ 6, 0, NULL, 0,
+ pm8916_wcd_analog_enable_spk_pa,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
+ SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
+
+ /* TX */
+ SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0,
+ pm8916_wcd_analog_enable_micbias_int1,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0,
+ pm8916_wcd_analog_enable_micbias_int2,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0,
+ pm8916_wcd_analog_enable_micbias_ext1,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0,
+ pm8916_wcd_analog_enable_micbias_ext2,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
+ pm8916_wcd_analog_enable_adc,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
+ pm8916_wcd_analog_enable_adc,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
+ pm8916_wcd_analog_enable_adc,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
+ SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
+
+ /* Analog path clocks */
+ SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
+ 0),
+ SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
+ 0),
+ SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
+
+ /* Digital path clocks */
+
+ SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
+ 0),
+
+ /* System Clock source */
+ SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
+ /* TX ADC and RX DAC Clock source. */
+ SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
+};
+
+static struct regmap *pm8916_get_regmap(struct device *dev)
+{
+ return dev_get_regmap(dev->parent, NULL);
+}
+
+static int pm8916_wcd_analog_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_soc_update_bits(dai->codec, CDC_D_CDC_RST_CTL,
+ RST_CTL_DIG_SW_RST_N_MASK,
+ RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
+
+ return 0;
+}
+
+static void pm8916_wcd_analog_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_soc_update_bits(dai->codec, CDC_D_CDC_RST_CTL,
+ RST_CTL_DIG_SW_RST_N_MASK, 0);
+}
+
+static struct snd_soc_dai_ops pm8916_wcd_analog_dai_ops = {
+ .startup = pm8916_wcd_analog_startup,
+ .shutdown = pm8916_wcd_analog_shutdown,
+};
+
+static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
+ [0] = {
+ .name = "pm8916_wcd_analog_pdm_rx",
+ .id = 0,
+ .playback = {
+ .stream_name = "PDM Playback",
+ .rates = MSM8916_WCD_ANALOG_RATES,
+ .formats = MSM8916_WCD_ANALOG_FORMATS,
+ .channels_min = 1,
+ .channels_max = 3,
+ },
+ .ops = &pm8916_wcd_analog_dai_ops,
+ },
+ [1] = {
+ .name = "pm8916_wcd_analog_pdm_tx",
+ .id = 1,
+ .capture = {
+ .stream_name = "PDM Capture",
+ .rates = MSM8916_WCD_ANALOG_RATES,
+ .formats = MSM8916_WCD_ANALOG_FORMATS,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &pm8916_wcd_analog_dai_ops,
+ },
+};
+
+static struct snd_soc_codec_driver pm8916_wcd_analog = {
+ .probe = pm8916_wcd_analog_probe,
+ .remove = pm8916_wcd_analog_remove,
+ .get_regmap = pm8916_get_regmap,
+ .component_driver = {
+ .controls = pm8916_wcd_analog_snd_controls,
+ .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
+ .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
+ .dapm_routes = pm8916_wcd_analog_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
+ },
+};
+
+static int pm8916_wcd_analog_parse_dt(struct device *dev,
+ struct pm8916_wcd_analog_priv *priv)
+{
+ int ret, i;
+
+ if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
+ priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
+ else
+ priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
+
+ if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
+ priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
+ else
+ priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
+
+ priv->mclk = devm_clk_get(dev, "mclk");
+ if (IS_ERR(priv->mclk)) {
+ dev_err(dev, "failed to get mclk\n");
+ return PTR_ERR(priv->mclk);
+ }
+ for (i = 0; i < ARRAY_SIZE(supply_names); i++)
+ priv->supplies[i].supply = supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
+ priv->supplies);
+ if (ret) {
+ dev_err(dev, "Failed to get regulator supplies %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
+{
+ struct pm8916_wcd_analog_priv *priv;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ ret = pm8916_wcd_analog_parse_dt(dev, priv);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(priv->mclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable mclk %d\n", ret);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ return snd_soc_register_codec(dev, &pm8916_wcd_analog,
+ pm8916_wcd_analog_dai,
+ ARRAY_SIZE(pm8916_wcd_analog_dai));
+}
+
+static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
+{
+ struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ snd_soc_unregister_codec(&pdev->dev);
+ clk_disable_unprepare(priv->mclk);
+
+ return 0;
+}
+
+static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
+ { .compatible = "qcom,pm8916-wcd-analog-codec", },
+ { }
+};
+
+static struct platform_driver pm8916_wcd_analog_spmi_driver = {
+ .driver = {
+ .name = "qcom,pm8916-wcd-spmi-codec",
+ .of_match_table = pm8916_wcd_analog_spmi_match_table,
+ },
+ .probe = pm8916_wcd_analog_spmi_probe,
+ .remove = pm8916_wcd_analog_spmi_remove,
+};
+
+module_platform_driver(pm8916_wcd_analog_spmi_driver);
+
+MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
+MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
+MODULE_LICENSE("GPL v2");
--
cgit v1.2.3
From 150db8c5afa10c43597dbc4db1c3e4af630e2ac0 Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Thu, 20 Oct 2016 15:20:46 +0100
Subject: ASoC: codecs: Add msm8916-wcd digital codec
msm8916-wcd codec is found in Qualcomm msm8916 and apq8016 processors.
This codec IP is split in to two parts(Digital & Analog).
Analog part is integrated in to PMIC PM8916 and the digital part is
integrated into Application processor. Data transfer between Analog and
Digital Die is done via a internal bus called PDM.
This patch adds support to Digital part of the Codec which is integrated
into Application Processor.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../bindings/sound/qcom,msm8916-wcd-digital.txt | 20 +
sound/soc/codecs/Kconfig | 3 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/msm8916-wcd-digital.c | 923 +++++++++++++++++++++
4 files changed, 948 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt
create mode 100644 sound/soc/codecs/msm8916-wcd-digital.c
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt
new file mode 100644
index 000000000000..1c8e4cb25176
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital.txt
@@ -0,0 +1,20 @@
+msm8916 digital audio CODEC
+
+## Bindings for codec core in lpass:
+
+Required properties
+ - compatible = "qcom,msm8916-wcd-digital-codec";
+ - reg: address space for lpass codec.
+ - clocks: Handle to mclk and ahbclk
+ - clock-names: should be "mclk", "ahbix-clk".
+
+Example:
+
+audio-codec@771c000{
+ compatible = "qcom,msm8916-wcd-digital-codec";
+ reg = <0x0771c000 0x400>;
+ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+ <&gcc GCC_CODEC_DIGCODEC_CLK>;
+ clock-names = "ahbix-clk", "mclk";
+ #sound-dai-cells = <1>;
+};
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 4a98ce65b993..28c7b84f13a5 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -585,6 +585,9 @@ config SND_SOC_MSM8916_WCD_ANALOG
tristate "Qualcomm MSM8916 WCD Analog Codec"
depends on SPMI || COMPILE_TEST
+config SND_SOC_MSM8916_WCD_DIGITAL
+ tristate "Qualcomm MSM8916 WCD DIGITAL Codec"
+
config SND_SOC_PCM1681
tristate "Texas Instruments PCM1681 CODEC"
depends on I2C
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 32d90184f764..472a7720a316 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -87,6 +87,7 @@ snd-soc-max9860-objs := max9860.o
snd-soc-mc13783-objs := mc13783.o
snd-soc-ml26124-objs := ml26124.o
snd-soc-msm8916-analog-objs := msm8916-wcd-analog.o
+snd-soc-msm8916-digital-objs := msm8916-wcd-digital.o
snd-soc-nau8810-objs := nau8810.o
snd-soc-nau8825-objs := nau8825.o
snd-soc-hdmi-codec-objs := hdmi-codec.o
@@ -311,6 +312,7 @@ obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
obj-$(CONFIG_SND_SOC_MSM8916_WCD_ANALOG) +=snd-soc-msm8916-analog.o
+obj-$(CONFIG_SND_SOC_MSM8916_WCD_DIGITAL) +=snd-soc-msm8916-digital.o
obj-$(CONFIG_SND_SOC_NAU8810) += snd-soc-nau8810.o
obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o
obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o
diff --git a/sound/soc/codecs/msm8916-wcd-digital.c b/sound/soc/codecs/msm8916-wcd-digital.c
new file mode 100644
index 000000000000..e35501af91ab
--- /dev/null
+++ b/sound/soc/codecs/msm8916-wcd-digital.c
@@ -0,0 +1,923 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <sound/soc.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/tlv.h>
+
+#define LPASS_CDC_CLK_RX_RESET_CTL (0x000)
+#define LPASS_CDC_CLK_TX_RESET_B1_CTL (0x004)
+#define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
+#define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
+#define LPASS_CDC_CLK_DMIC_B1_CTL (0x008)
+#define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1)
+#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 (0x0 << 1)
+#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 (0x1 << 1)
+#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 (0x2 << 1)
+#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 (0x3 << 1)
+#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 (0x4 << 1)
+#define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
+#define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
+
+#define LPASS_CDC_CLK_RX_I2S_CTL (0x00C)
+#define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
+#define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
+#define RX_I2S_CTL_RX_I2S_MODE_32 0
+#define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0)
+#define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ 0x0
+#define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ 0x1
+#define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ 0x2
+#define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ 0x3
+#define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ 0x4
+#define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5
+#define LPASS_CDC_CLK_TX_I2S_CTL (0x010)
+#define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5)
+#define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5)
+#define TX_I2S_CTL_TX_I2S_MODE_32 0
+#define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0)
+#define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ 0x0
+#define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ 0x1
+#define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ 0x2
+#define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ 0x3
+#define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ 0x4
+#define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5
+
+#define LPASS_CDC_CLK_OTHR_RESET_B1_CTL (0x014)
+#define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL (0x018)
+#define LPASS_CDC_CLK_OTHR_CTL (0x01C)
+#define LPASS_CDC_CLK_RX_B1_CTL (0x020)
+#define LPASS_CDC_CLK_MCLK_CTL (0x024)
+#define MCLK_CTL_MCLK_EN_MASK BIT(0)
+#define MCLK_CTL_MCLK_EN_ENABLE BIT(0)
+#define MCLK_CTL_MCLK_EN_DISABLE 0
+#define LPASS_CDC_CLK_PDM_CTL (0x028)
+#define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0)
+#define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0)
+#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1)
+#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1)
+#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK 0
+
+#define LPASS_CDC_CLK_SD_CTL (0x02C)
+#define LPASS_CDC_RX1_B1_CTL (0x040)
+#define LPASS_CDC_RX2_B1_CTL (0x060)
+#define LPASS_CDC_RX3_B1_CTL (0x080)
+#define LPASS_CDC_RX1_B2_CTL (0x044)
+#define LPASS_CDC_RX2_B2_CTL (0x064)
+#define LPASS_CDC_RX3_B2_CTL (0x084)
+#define LPASS_CDC_RX1_B3_CTL (0x048)
+#define LPASS_CDC_RX2_B3_CTL (0x068)
+#define LPASS_CDC_RX3_B3_CTL (0x088)
+#define LPASS_CDC_RX1_B4_CTL (0x04C)
+#define LPASS_CDC_RX2_B4_CTL (0x06C)
+#define LPASS_CDC_RX3_B4_CTL (0x08C)
+#define LPASS_CDC_RX1_B5_CTL (0x050)
+#define LPASS_CDC_RX2_B5_CTL (0x070)
+#define LPASS_CDC_RX3_B5_CTL (0x090)
+#define LPASS_CDC_RX1_B6_CTL (0x054)
+#define RXn_B6_CTL_MUTE_MASK BIT(0)
+#define RXn_B6_CTL_MUTE_ENABLE BIT(0)
+#define RXn_B6_CTL_MUTE_DISABLE 0
+#define LPASS_CDC_RX2_B6_CTL (0x074)
+#define LPASS_CDC_RX3_B6_CTL (0x094)
+#define LPASS_CDC_RX1_VOL_CTL_B1_CTL (0x058)
+#define LPASS_CDC_RX2_VOL_CTL_B1_CTL (0x078)
+#define LPASS_CDC_RX3_VOL_CTL_B1_CTL (0x098)
+#define LPASS_CDC_RX1_VOL_CTL_B2_CTL (0x05C)
+#define LPASS_CDC_RX2_VOL_CTL_B2_CTL (0x07C)
+#define LPASS_CDC_RX3_VOL_CTL_B2_CTL (0x09C)
+#define LPASS_CDC_TOP_GAIN_UPDATE (0x0A0)
+#define LPASS_CDC_TOP_CTL (0x0A4)
+#define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0)
+#define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ 0
+#define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0)
+
+#define LPASS_CDC_DEBUG_DESER1_CTL (0x0E0)
+#define LPASS_CDC_DEBUG_DESER2_CTL (0x0E4)
+#define LPASS_CDC_DEBUG_B1_CTL_CFG (0x0E8)
+#define LPASS_CDC_DEBUG_B2_CTL_CFG (0x0EC)
+#define LPASS_CDC_DEBUG_B3_CTL_CFG (0x0F0)
+#define LPASS_CDC_IIR1_GAIN_B1_CTL (0x100)
+#define LPASS_CDC_IIR2_GAIN_B1_CTL (0x140)
+#define LPASS_CDC_IIR1_GAIN_B2_CTL (0x104)
+#define LPASS_CDC_IIR2_GAIN_B2_CTL (0x144)
+#define LPASS_CDC_IIR1_GAIN_B3_CTL (0x108)
+#define LPASS_CDC_IIR2_GAIN_B3_CTL (0x148)
+#define LPASS_CDC_IIR1_GAIN_B4_CTL (0x10C)
+#define LPASS_CDC_IIR2_GAIN_B4_CTL (0x14C)
+#define LPASS_CDC_IIR1_GAIN_B5_CTL (0x110)
+#define LPASS_CDC_IIR2_GAIN_B5_CTL (0x150)
+#define LPASS_CDC_IIR1_GAIN_B6_CTL (0x114)
+#define LPASS_CDC_IIR2_GAIN_B6_CTL (0x154)
+#define LPASS_CDC_IIR1_GAIN_B7_CTL (0x118)
+#define LPASS_CDC_IIR2_GAIN_B7_CTL (0x158)
+#define LPASS_CDC_IIR1_GAIN_B8_CTL (0x11C)
+#define LPASS_CDC_IIR2_GAIN_B8_CTL (0x15C)
+#define LPASS_CDC_IIR1_CTL (0x120)
+#define LPASS_CDC_IIR2_CTL (0x160)
+#define LPASS_CDC_IIR1_GAIN_TIMER_CTL (0x124)
+#define LPASS_CDC_IIR2_GAIN_TIMER_CTL (0x164)
+#define LPASS_CDC_IIR1_COEF_B1_CTL (0x128)
+#define LPASS_CDC_IIR2_COEF_B1_CTL (0x168)
+#define LPASS_CDC_IIR1_COEF_B2_CTL (0x12C)
+#define LPASS_CDC_IIR2_COEF_B2_CTL (0x16C)
+#define LPASS_CDC_CONN_RX1_B1_CTL (0x180)
+#define LPASS_CDC_CONN_RX1_B2_CTL (0x184)
+#define LPASS_CDC_CONN_RX1_B3_CTL (0x188)
+#define LPASS_CDC_CONN_RX2_B1_CTL (0x18C)
+#define LPASS_CDC_CONN_RX2_B2_CTL (0x190)
+#define LPASS_CDC_CONN_RX2_B3_CTL (0x194)
+#define LPASS_CDC_CONN_RX3_B1_CTL (0x198)
+#define LPASS_CDC_CONN_RX3_B2_CTL (0x19C)
+#define LPASS_CDC_CONN_TX_B1_CTL (0x1A0)
+#define LPASS_CDC_CONN_EQ1_B1_CTL (0x1A8)
+#define LPASS_CDC_CONN_EQ1_B2_CTL (0x1AC)
+#define LPASS_CDC_CONN_EQ1_B3_CTL (0x1B0)
+#define LPASS_CDC_CONN_EQ1_B4_CTL (0x1B4)
+#define LPASS_CDC_CONN_EQ2_B1_CTL (0x1B8)
+#define LPASS_CDC_CONN_EQ2_B2_CTL (0x1BC)
+#define LPASS_CDC_CONN_EQ2_B3_CTL (0x1C0)
+#define LPASS_CDC_CONN_EQ2_B4_CTL (0x1C4)
+#define LPASS_CDC_CONN_TX_I2S_SD1_CTL (0x1C8)
+#define LPASS_CDC_TX1_VOL_CTL_TIMER (0x280)
+#define LPASS_CDC_TX2_VOL_CTL_TIMER (0x2A0)
+#define LPASS_CDC_TX1_VOL_CTL_GAIN (0x284)
+#define LPASS_CDC_TX2_VOL_CTL_GAIN (0x2A4)
+#define LPASS_CDC_TX1_VOL_CTL_CFG (0x288)
+#define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0)
+#define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0)
+
+#define LPASS_CDC_TX2_VOL_CTL_CFG (0x2A8)
+#define LPASS_CDC_TX1_MUX_CTL (0x28C)
+#define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4)
+#define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT 4
+#define TX_MUX_CTL_CF_NEG_3DB_4HZ (0x0 << 4)
+#define TX_MUX_CTL_CF_NEG_3DB_75HZ (0x1 << 4)
+#define TX_MUX_CTL_CF_NEG_3DB_150HZ (0x2 << 4)
+#define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3)
+#define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3)
+#define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS 0
+
+#define LPASS_CDC_TX2_MUX_CTL (0x2AC)
+#define LPASS_CDC_TX1_CLK_FS_CTL (0x290)
+#define LPASS_CDC_TX2_CLK_FS_CTL (0x2B0)
+#define LPASS_CDC_TX1_DMIC_CTL (0x294)
+#define LPASS_CDC_TX2_DMIC_CTL (0x2B4)
+#define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0)
+#define TXN_DMIC_CTL_CLK_SEL_DIV2 0x0
+#define TXN_DMIC_CTL_CLK_SEL_DIV3 0x1
+#define TXN_DMIC_CTL_CLK_SEL_DIV4 0x2
+#define TXN_DMIC_CTL_CLK_SEL_DIV6 0x3
+#define TXN_DMIC_CTL_CLK_SEL_DIV16 0x4
+
+#define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
+ SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_48000)
+#define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+struct msm8916_wcd_digital_priv {
+ struct clk *ahbclk, *mclk;
+};
+
+static const unsigned long rx_gain_reg[] = {
+ LPASS_CDC_RX1_VOL_CTL_B2_CTL,
+ LPASS_CDC_RX2_VOL_CTL_B2_CTL,
+ LPASS_CDC_RX3_VOL_CTL_B2_CTL,
+};
+
+static const unsigned long tx_gain_reg[] = {
+ LPASS_CDC_TX1_VOL_CTL_GAIN,
+ LPASS_CDC_TX2_VOL_CTL_GAIN,
+};
+
+static const char *const rx_mix1_text[] = {
+ "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
+};
+
+static const char *const dec_mux_text[] = {
+ "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
+};
+static const char *const rx_mix2_text[] = { "ZERO", "IIR1", "IIR2" };
+static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
+
+/* RX1 MIX1 */
+static const struct soc_enum rx_mix1_inp_enum[] = {
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
+};
+
+/* RX1 MIX2 */
+static const struct soc_enum rx_mix2_inp1_chain_enum = SOC_ENUM_SINGLE(
+ LPASS_CDC_CONN_RX1_B3_CTL, 0, 3, rx_mix2_text);
+
+/* RX2 MIX1 */
+static const struct soc_enum rx2_mix1_inp_enum[] = {
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
+};
+
+/* RX2 MIX2 */
+static const struct soc_enum rx2_mix2_inp1_chain_enum = SOC_ENUM_SINGLE(
+ LPASS_CDC_CONN_RX2_B3_CTL, 0, 3, rx_mix2_text);
+
+/* RX3 MIX1 */
+static const struct soc_enum rx3_mix1_inp_enum[] = {
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
+ SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
+};
+
+/* DEC */
+static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
+ LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
+static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
+ LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
+
+/* RDAC2 MUX */
+static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
+ "DEC1 MUX Mux", dec1_mux_enum);
+static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
+ "DEC2 MUX Mux", dec2_mux_enum);
+static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
+ "RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
+static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
+ "RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
+static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
+ "RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
+static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
+ "RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
+static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
+ "RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
+static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
+ "RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
+static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
+ "RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
+static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
+ "RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
+static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
+ "RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
+
+/* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */
+static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0);
+
+/* Cutoff Freq for High Pass Filter at -3dB */
+static const char * const hpf_cutoff_text[] = {
+ "4Hz", "75Hz", "150Hz",
+};
+
+static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
+ hpf_cutoff_text);
+static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
+ hpf_cutoff_text);
+
+/* cut off for dc blocker inside rx chain */
+static const char * const dc_blocker_cutoff_text[] = {
+ "4Hz", "75Hz", "150Hz",
+};
+
+static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
+ dc_blocker_cutoff_text);
+static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
+ dc_blocker_cutoff_text);
+static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
+ dc_blocker_cutoff_text);
+
+static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
+ SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
+ -128, 127, digital_gain),
+ SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
+ -128, 127, digital_gain),
+ SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
+ -128, 127, digital_gain),
+ SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
+ -128, 127, digital_gain),
+ SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
+ -128, 127, digital_gain),
+ SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
+ SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
+ SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
+ SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
+ SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
+ SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
+ SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
+ SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
+ SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
+};
+
+static int msm8916_wcd_digital_enable_interpolator(
+ struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ /* apply the digital gain after the interpolator is enabled */
+ usleep_range(10000, 10100);
+ snd_soc_write(codec, rx_gain_reg[w->shift],
+ snd_soc_read(codec, rx_gain_reg[w->shift]));
+ break;
+ }
+ return 0;
+}
+
+static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ unsigned int decimator = w->shift + 1;
+ u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
+ u8 dec_hpf_cut_of_freq;
+
+ dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
+ tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
+ tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Enable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg,
+ TX_VOL_CTL_CFG_MUTE_EN_MASK,
+ TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
+ dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg) &
+ TX_MUX_CTL_CUT_OFF_FREQ_MASK;
+ dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
+ if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
+ /* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg,
+ TX_MUX_CTL_CUT_OFF_FREQ_MASK,
+ TX_MUX_CTL_CF_NEG_3DB_150HZ);
+ }
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ /* enable HPF */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg,
+ TX_MUX_CTL_HPF_BP_SEL_MASK,
+ TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
+ /* apply the digital gain after the decimator is enabled */
+ snd_soc_write(codec, tx_gain_reg[w->shift],
+ snd_soc_read(codec, tx_gain_reg[w->shift]));
+ snd_soc_update_bits(codec, tx_vol_ctl_reg,
+ TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, tx_vol_ctl_reg,
+ TX_VOL_CTL_CFG_MUTE_EN_MASK,
+ TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
+ snd_soc_update_bits(codec, tx_mux_ctl_reg,
+ TX_MUX_CTL_HPF_BP_SEL_MASK,
+ TX_MUX_CTL_HPF_BP_SEL_BYPASS);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
+ 1 << w->shift);
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
+ snd_soc_update_bits(codec, tx_mux_ctl_reg,
+ TX_MUX_CTL_HPF_BP_SEL_MASK,
+ TX_MUX_CTL_HPF_BP_SEL_BYPASS);
+ snd_soc_update_bits(codec, tx_vol_ctl_reg,
+ TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
+ break;
+ }
+
+ return 0;
+}
+
+static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ unsigned int dmic;
+ int ret;
+ /* get dmic number out of widget name */
+ char *dmic_num = strpbrk(w->name, "12");
+
+ if (dmic_num == NULL) {
+ dev_err(codec->dev, "Invalid DMIC\n");
+ return -EINVAL;
+ }
+ ret = kstrtouint(dmic_num, 10, &dmic);
+ if (ret < 0 || dmic > 2) {
+ dev_err(codec->dev, "Invalid DMIC line on the codec\n");
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, LPASS_CDC_CLK_DMIC_B1_CTL,
+ DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
+ DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
+ switch (dmic) {
+ case 1:
+ snd_soc_update_bits(codec, LPASS_CDC_TX1_DMIC_CTL,
+ TXN_DMIC_CTL_CLK_SEL_MASK,
+ TXN_DMIC_CTL_CLK_SEL_DIV3);
+ break;
+ case 2:
+ snd_soc_update_bits(codec, LPASS_CDC_TX2_DMIC_CTL,
+ TXN_DMIC_CTL_CLK_SEL_MASK,
+ TXN_DMIC_CTL_CLK_SEL_DIV3);
+ break;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
+ /*RX stuff */
+ SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_OUTPUT("PDM_RX1"),
+ SND_SOC_DAPM_OUTPUT("PDM_RX2"),
+ SND_SOC_DAPM_OUTPUT("PDM_RX3"),
+
+ SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
+
+ SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Interpolator */
+ SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
+ 0, msm8916_wcd_digital_enable_interpolator,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
+ 0, msm8916_wcd_digital_enable_interpolator,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
+ 0, msm8916_wcd_digital_enable_interpolator,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp3_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp3_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp3_mux),
+
+ /* TX */
+ SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
+ &dec1_mux, msm8916_wcd_digital_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
+ &dec2_mux, msm8916_wcd_digital_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
+
+ /* Digital Mic Inputs */
+ SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+ msm8916_wcd_digital_enable_dmic,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
+ msm8916_wcd_digital_enable_dmic,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
+ 4, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
+ NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
+ /* Connectivity Clock */
+ SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
+ NULL, 0),
+
+};
+
+static int msm8916_wcd_digital_parse_dt(struct platform_device *pdev,
+ struct msm8916_wcd_digital_priv *priv)
+{
+ struct device *dev = &pdev->dev;
+
+ priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
+ if (IS_ERR(priv->ahbclk)) {
+ dev_err(dev, "failed to get ahbix clk\n");
+ return PTR_ERR(priv->ahbclk);
+ }
+
+ priv->mclk = devm_clk_get(dev, "mclk");
+ if (IS_ERR(priv->mclk)) {
+ dev_err(dev, "failed to get mclk\n");
+ return PTR_ERR(priv->mclk);
+ }
+
+ return 0;
+}
+
+static int msm8916_wcd_digital_codec_probe(struct snd_soc_codec *codec)
+{
+ struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(codec->dev);
+
+ snd_soc_codec_set_drvdata(codec, priv);
+
+ return 0;
+}
+
+static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ u8 tx_fs_rate;
+ u8 rx_fs_rate;
+
+ switch (params_rate(params)) {
+ case 8000:
+ tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
+ rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
+ break;
+ case 16000:
+ tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
+ rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
+ break;
+ case 32000:
+ tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
+ rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
+ break;
+ case 48000:
+ tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
+ rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
+ break;
+ default:
+ dev_err(dai->codec->dev, "Invalid sampling rate %d\n",
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ switch (substream->stream) {
+ case SNDRV_PCM_STREAM_CAPTURE:
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL,
+ TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
+ break;
+ case SNDRV_PCM_STREAM_PLAYBACK:
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_RX_I2S_CTL,
+ RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL,
+ TX_I2S_CTL_TX_I2S_MODE_MASK,
+ TX_I2S_CTL_TX_I2S_MODE_16);
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_RX_I2S_CTL,
+ RX_I2S_CTL_RX_I2S_MODE_MASK,
+ RX_I2S_CTL_RX_I2S_MODE_16);
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL,
+ TX_I2S_CTL_TX_I2S_MODE_MASK,
+ TX_I2S_CTL_TX_I2S_MODE_32);
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_RX_I2S_CTL,
+ RX_I2S_CTL_RX_I2S_MODE_MASK,
+ RX_I2S_CTL_RX_I2S_MODE_32);
+ break;
+ default:
+ dev_err(dai->dev, "%s: wrong format selected\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
+
+ {"I2S RX1", NULL, "AIF1 Playback"},
+ {"I2S RX2", NULL, "AIF1 Playback"},
+ {"I2S RX3", NULL, "AIF1 Playback"},
+
+ {"AIF1 Capture", NULL, "I2S TX1"},
+ {"AIF1 Capture", NULL, "I2S TX2"},
+ {"AIF1 Capture", NULL, "I2S TX3"},
+
+ /* Decimator Inputs */
+ {"DEC1 MUX", "DMIC1", "DMIC1"},
+ {"DEC1 MUX", "DMIC2", "DMIC2"},
+ {"DEC1 MUX", "ADC1", "ADC1"},
+ {"DEC1 MUX", "ADC2", "ADC2"},
+ {"DEC1 MUX", "ADC3", "ADC3"},
+ {"DEC1 MUX", NULL, "CDC_CONN"},
+
+ {"DEC2 MUX", "DMIC1", "DMIC1"},
+ {"DEC2 MUX", "DMIC2", "DMIC2"},
+ {"DEC2 MUX", "ADC1", "ADC1"},
+ {"DEC2 MUX", "ADC2", "ADC2"},
+ {"DEC2 MUX", "ADC3", "ADC3"},
+ {"DEC2 MUX", NULL, "CDC_CONN"},
+
+ {"DMIC1", NULL, "DMIC_CLK"},
+ {"DMIC2", NULL, "DMIC_CLK"},
+
+ {"I2S TX1", NULL, "DEC1 MUX"},
+ {"I2S TX2", NULL, "DEC2 MUX"},
+
+ {"I2S TX1", NULL, "TX_I2S_CLK"},
+ {"I2S TX2", NULL, "TX_I2S_CLK"},
+
+ {"TX_I2S_CLK", NULL, "MCLK"},
+ {"TX_I2S_CLK", NULL, "PDM_CLK"},
+
+ {"ADC1", NULL, "LPASS_PDM_TX"},
+ {"ADC2", NULL, "LPASS_PDM_TX"},
+ {"ADC3", NULL, "LPASS_PDM_TX"},
+
+ {"I2S RX1", NULL, "RX_I2S_CLK"},
+ {"I2S RX2", NULL, "RX_I2S_CLK"},
+ {"I2S RX3", NULL, "RX_I2S_CLK"},
+
+ {"RX_I2S_CLK", NULL, "PDM_CLK"},
+ {"RX_I2S_CLK", NULL, "MCLK"},
+ {"RX_I2S_CLK", NULL, "CDC_CONN"},
+
+ /* RX1 PATH.. */
+ {"PDM_RX1", NULL, "RX1 INT"},
+ {"RX1 INT", NULL, "RX1 MIX1"},
+
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
+
+ {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
+
+ {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
+
+ {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
+
+ /* RX2 PATH */
+ {"PDM_RX2", NULL, "RX2 INT"},
+ {"RX2 INT", NULL, "RX2 MIX1"},
+
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
+
+ {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
+
+ {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
+
+ {"RX2 MIX1 INP3", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP3", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP3", "RX3", "I2S RX3"},
+
+ /* RX3 PATH */
+ {"PDM_RX3", NULL, "RX3 INT"},
+ {"RX3 INT", NULL, "RX3 MIX1"},
+
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
+
+ {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
+
+ {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
+
+ {"RX3 MIX1 INP3", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP3", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP3", "RX3", "I2S RX3"},
+
+};
+
+static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct msm8916_wcd_digital_priv *msm8916_wcd;
+ unsigned long mclk_rate;
+
+ msm8916_wcd = snd_soc_codec_get_drvdata(codec);
+ snd_soc_update_bits(codec, LPASS_CDC_CLK_MCLK_CTL,
+ MCLK_CTL_MCLK_EN_MASK,
+ MCLK_CTL_MCLK_EN_ENABLE);
+ snd_soc_update_bits(codec, LPASS_CDC_CLK_PDM_CTL,
+ LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
+ LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
+
+ mclk_rate = clk_get_rate(msm8916_wcd->mclk);
+ switch (mclk_rate) {
+ case 12288000:
+ snd_soc_update_bits(codec, LPASS_CDC_TOP_CTL,
+ TOP_CTL_DIG_MCLK_FREQ_MASK,
+ TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
+ break;
+ case 9600000:
+ snd_soc_update_bits(codec, LPASS_CDC_TOP_CTL,
+ TOP_CTL_DIG_MCLK_FREQ_MASK,
+ TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid mclk rate %ld\n", mclk_rate);
+ break;
+ }
+ return 0;
+}
+
+static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_PDM_CTL,
+ LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
+}
+
+static struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
+ .startup = msm8916_wcd_digital_startup,
+ .shutdown = msm8916_wcd_digital_shutdown,
+ .hw_params = msm8916_wcd_digital_hw_params,
+};
+
+static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
+ [0] = {
+ .name = "msm8916_wcd_digital_i2s_rx1",
+ .id = 0,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = MSM8916_WCD_DIGITAL_RATES,
+ .formats = MSM8916_WCD_DIGITAL_FORMATS,
+ .channels_min = 1,
+ .channels_max = 3,
+ },
+ .ops = &msm8916_wcd_digital_dai_ops,
+ },
+ [1] = {
+ .name = "msm8916_wcd_digital_i2s_tx1",
+ .id = 1,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = MSM8916_WCD_DIGITAL_RATES,
+ .formats = MSM8916_WCD_DIGITAL_FORMATS,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &msm8916_wcd_digital_dai_ops,
+ },
+};
+
+static struct snd_soc_codec_driver msm8916_wcd_digital = {
+ .probe = msm8916_wcd_digital_codec_probe,
+ .component_driver = {
+ .controls = msm8916_wcd_digital_snd_controls,
+ .num_controls = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
+ .dapm_widgets = msm8916_wcd_digital_dapm_widgets,
+ .num_dapm_widgets =
+ ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
+ .dapm_routes = msm8916_wcd_digital_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
+ },
+};
+
+static const struct regmap_config msm8916_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = LPASS_CDC_TX2_DMIC_CTL,
+ .cache_type = REGCACHE_FLAT,
+};
+
+static int msm8916_wcd_digital_probe(struct platform_device *pdev)
+{
+ struct msm8916_wcd_digital_priv *priv;
+ struct device *dev = &pdev->dev;
+ void __iomem *base;
+ struct resource *mem_res;
+ struct regmap *digital_map;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, mem_res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ digital_map =
+ devm_regmap_init_mmio(&pdev->dev, base,
+ &msm8916_codec_regmap_config);
+ if (IS_ERR(digital_map))
+ return PTR_ERR(digital_map);
+
+ ret = msm8916_wcd_digital_parse_dt(pdev, priv);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(priv->ahbclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable ahbclk %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->mclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable mclk %d\n", ret);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ return snd_soc_register_codec(dev, &msm8916_wcd_digital,
+ msm8916_wcd_digital_dai,
+ ARRAY_SIZE(msm8916_wcd_digital_dai));
+}
+
+static int msm8916_wcd_digital_remove(struct platform_device *pdev)
+{
+ struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ snd_soc_unregister_codec(&pdev->dev);
+ clk_disable_unprepare(priv->mclk);
+ clk_disable_unprepare(priv->ahbclk);
+
+ return 0;
+}
+
+static const struct of_device_id msm8916_wcd_digital_match_table[] = {
+ { .compatible = "qcom,msm8916-wcd-digital-codec" },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
+
+static struct platform_driver msm8916_wcd_digital_driver = {
+ .driver = {
+ .name = "msm8916-wcd-digital-codec",
+ .of_match_table = msm8916_wcd_digital_match_table,
+ },
+ .probe = msm8916_wcd_digital_probe,
+ .remove = msm8916_wcd_digital_remove,
+};
+
+module_platform_driver(msm8916_wcd_digital_driver);
+
+MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
+MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
+MODULE_LICENSE("GPL v2");
--
cgit v1.2.3
From 393ac586236c25d36f1a1ea9650ac3f3c3b91bce Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Thu, 20 Oct 2016 15:20:47 +0100
Subject: ASoC: apq8016-sbc: dt bindings: remove incorrect property
This patch removes capture-dai property which should not have existed
in this document in the first place. It looks like leftover from old
version of patches by mistake.
Remove it to avoid any confusion in future.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt | 1 -
1 file changed, 1 deletion(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt
index d9d8635ff94c..72c192801a69 100644
--- a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt
+++ b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt
@@ -45,7 +45,6 @@ Required CPU/CODEC subnodes properties:
-link-name : Name of the dai link.
-sound-dai : phandle and port of CPU/CODEC
--capture-dai : phandle and port of CPU/CODEC
Example:
--
cgit v1.2.3
From 09065f8b44a3e2a742565368b89b5848387eaf38 Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Date: Thu, 20 Oct 2016 15:20:48 +0100
Subject: ASoC: qcom: apq8016-sbc: Add support to multi codec.
This patch adds support to multi codec, as the msm8916 codec is now
split into two codecs, Analog and Digital.
Also update the bindings and example to show that the card supports
multicodec.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt | 4 ++--
sound/soc/qcom/apq8016_sbc.c | 11 +++--------
2 files changed, 5 insertions(+), 10 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt
index 72c192801a69..6a4aadc4ce06 100644
--- a/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt
+++ b/Documentation/devicetree/bindings/sound/qcom,apq8016-sbc.txt
@@ -44,7 +44,7 @@ Required dai-link subnodes:
Required CPU/CODEC subnodes properties:
-link-name : Name of the dai link.
--sound-dai : phandle and port of CPU/CODEC
+-sound-dai : phandle/s and port of CPU/CODEC
Example:
@@ -72,7 +72,7 @@ sound: sound {
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
- sound-dai = <&wcd_codec 0>;
+ sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
};
};
diff --git a/sound/soc/qcom/apq8016_sbc.c b/sound/soc/qcom/apq8016_sbc.c
index 07f91e918b23..d084d7468299 100644
--- a/sound/soc/qcom/apq8016_sbc.c
+++ b/sound/soc/qcom/apq8016_sbc.c
@@ -123,20 +123,15 @@ static struct apq8016_sbc_data *apq8016_sbc_parse_of(struct snd_soc_card *card)
return ERR_PTR(-EINVAL);
}
- link->codec_of_node = of_parse_phandle(codec, "sound-dai", 0);
- if (!link->codec_of_node) {
- dev_err(card->dev, "error getting codec phandle\n");
- return ERR_PTR(-EINVAL);
- }
-
ret = snd_soc_of_get_dai_name(cpu, &link->cpu_dai_name);
if (ret) {
dev_err(card->dev, "error getting cpu dai name\n");
return ERR_PTR(ret);
}
- ret = snd_soc_of_get_dai_name(codec, &link->codec_dai_name);
- if (ret) {
+ ret = snd_soc_of_get_dai_link_codecs(dev, codec, link);
+
+ if (ret < 0) {
dev_err(card->dev, "error getting codec dai name\n");
return ERR_PTR(ret);
}
--
cgit v1.2.3
From 028f5a5bc85378317099be47995269d1027b0309 Mon Sep 17 00:00:00 2001
From: Matt Flax <flatmax@flatmax.org>
Date: Thu, 20 Oct 2016 10:29:14 +1100
Subject: ASoC: wm8580: Add the wm8581 codec to the driver
This patch adds support for the wm8581 codec to the wm8580 driver.
The wm8581 codec hardware adds a fourth DAC and otherwise is
compatible with the wm8580 codec.
of_device_id data is used to allow the driver to select the
suitable DAC count specified in the device tree codec selection.
The wm8580_driver_data struct is used to store the number of DACs.
The snd_soc_dai_driver no longer lists the channels_max for the
playback substream. This variable is set during the i2c probe
from the of_device_id supplied wm8580_driver_data struct.
With knowledge of the number of DACs in use, the DAC4 controls,
widgets and routes are added as required for DAC4.
The device tree documentation for the wm8580 is altered to list
the wm8581 codec support, as is the Kconfig file.
Signed-off-by: Matt Flax <flatmax@flatmax.org>
Reviewed-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/wm8580.txt | 4 +-
sound/soc/codecs/Kconfig | 2 +-
sound/soc/codecs/wm8580.c | 98 ++++++++++++++++++++--
3 files changed, 92 insertions(+), 12 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt
index 7d9821f348da..78fce9b14954 100644
--- a/Documentation/devicetree/bindings/sound/wm8580.txt
+++ b/Documentation/devicetree/bindings/sound/wm8580.txt
@@ -1,10 +1,10 @@
-WM8580 audio CODEC
+WM8580 and WM8581 audio CODEC
This device supports I2C only.
Required properties:
- - compatible : "wlf,wm8580"
+ - compatible : "wlf,wm8580", "wlf,wm8581"
- reg : the I2C address of the device.
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c67667bb970f..199bec88d4ae 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -914,7 +914,7 @@ config SND_SOC_WM8523
depends on I2C
config SND_SOC_WM8580
- tristate "Wolfson Microelectronics WM8523 CODEC"
+ tristate "Wolfson Microelectronics WM8580 and WM8581 CODECs"
depends on I2C
config SND_SOC_WM8711
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index faa7287a5253..aecd3c99e604 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -1,5 +1,5 @@
/*
- * wm8580.c -- WM8580 ALSA Soc Audio driver
+ * wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver
*
* Copyright 2008-12 Wolfson Microelectronics PLC.
*
@@ -12,6 +12,9 @@
* The WM8580 is a multichannel codec with S/PDIF support, featuring six
* DAC channels and two ADC channels.
*
+ * The WM8581 is a multichannel codec with S/PDIF support, featuring eight
+ * DAC channels and two ADC channels.
+ *
* Currently only the primary audio interface is supported - S/PDIF and
* the secondary audio interfaces are not.
*/
@@ -65,6 +68,8 @@
#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
+#define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A
+#define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B
#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
#define WM8580_ADC_CONTROL1 0x1D
#define WM8580_SPDTXCHAN0 0x1E
@@ -236,12 +241,17 @@ static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
"PVDD",
};
+struct wm8580_driver_data {
+ int num_dacs;
+};
+
/* codec private data */
struct wm8580_priv {
struct regmap *regmap;
struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
struct pll_state a;
struct pll_state b;
+ const struct wm8580_driver_data *drvdata;
int sysclk[2];
};
@@ -306,6 +316,19 @@ SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
};
+static const struct snd_kcontrol_new wm8581_snd_controls[] = {
+SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
+ WM8581_DIGITAL_ATTENUATION_DACL4,
+ WM8581_DIGITAL_ATTENUATION_DACR4,
+ 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
+
+SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
+
+SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0),
+
+SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
+};
+
static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
@@ -324,6 +347,13 @@ SND_SOC_DAPM_INPUT("AINL"),
SND_SOC_DAPM_INPUT("AINR"),
};
+static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
+SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
+
+SND_SOC_DAPM_OUTPUT("VOUT4L"),
+SND_SOC_DAPM_OUTPUT("VOUT4R"),
+};
+
static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
{ "VOUT1L", NULL, "DAC1" },
{ "VOUT1R", NULL, "DAC1" },
@@ -338,6 +368,11 @@ static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
{ "ADC", NULL, "AINR" },
};
+static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
+ { "VOUT4L", NULL, "DAC4" },
+ { "VOUT4R", NULL, "DAC4" },
+};
+
/* PLL divisors */
struct _pll_div {
u32 prescale:1;
@@ -815,10 +850,21 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
return 0;
}
+static int wm8580_playback_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
+
+ return snd_pcm_hw_constraint_minmax(substream->runtime,
+ SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
+}
+
#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
+ .startup = wm8580_playback_startup,
.set_sysclk = wm8580_set_sysclk,
.hw_params = wm8580_paif_hw_params,
.set_fmt = wm8580_set_paif_dai_fmt,
@@ -842,7 +888,6 @@ static struct snd_soc_dai_driver wm8580_dai[] = {
.playback = {
.stream_name = "Playback",
.channels_min = 1,
- .channels_max = 6,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = WM8580_FORMATS,
},
@@ -865,8 +910,22 @@ static struct snd_soc_dai_driver wm8580_dai[] = {
static int wm8580_probe(struct snd_soc_codec *codec)
{
struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
+ struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
int ret = 0;
+ switch (wm8580->drvdata->num_dacs) {
+ case 4:
+ snd_soc_add_codec_controls(codec, wm8581_snd_controls,
+ ARRAY_SIZE(wm8581_snd_controls));
+ snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
+ ARRAY_SIZE(wm8581_dapm_widgets));
+ snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
+ ARRAY_SIZE(wm8581_dapm_routes));
+ break;
+ default:
+ break;
+ }
+
ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
wm8580->supplies);
if (ret != 0) {
@@ -914,12 +973,6 @@ static const struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
},
};
-static const struct of_device_id wm8580_of_match[] = {
- { .compatible = "wlf,wm8580" },
- { },
-};
-MODULE_DEVICE_TABLE(of, wm8580_of_match);
-
static const struct regmap_config wm8580_regmap = {
.reg_bits = 7,
.val_bits = 9,
@@ -932,10 +985,26 @@ static const struct regmap_config wm8580_regmap = {
.volatile_reg = wm8580_volatile,
};
+const struct wm8580_driver_data wm8580_data = {
+ .num_dacs = 3,
+};
+
+const struct wm8580_driver_data wm8581_data = {
+ .num_dacs = 4,
+};
+
+static const struct of_device_id wm8580_of_match[] = {
+ { .compatible = "wlf,wm8580", .data = &wm8580_data },
+ { .compatible = "wlf,wm8581", .data = &wm8581_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, wm8580_of_match);
+
#if IS_ENABLED(CONFIG_I2C)
static int wm8580_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
+ const struct of_device_id *of_id;
struct wm8580_priv *wm8580;
int ret, i;
@@ -960,6 +1029,15 @@ static int wm8580_i2c_probe(struct i2c_client *i2c,
i2c_set_clientdata(i2c, wm8580);
+ of_id = of_match_device(wm8580_of_match, &i2c->dev);
+ if (of_id)
+ wm8580->drvdata = of_id->data;
+
+ if (!wm8580->drvdata) {
+ dev_err(&i2c->dev, "failed to find driver data\n");
+ return -EINVAL;
+ }
+
ret = snd_soc_register_codec(&i2c->dev,
&soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
@@ -973,7 +1051,8 @@ static int wm8580_i2c_remove(struct i2c_client *client)
}
static const struct i2c_device_id wm8580_i2c_id[] = {
- { "wm8580", 0 },
+ { "wm8580", (kernel_ulong_t)&wm8580_data },
+ { "wm8581", (kernel_ulong_t)&wm8581_data },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
@@ -1014,4 +1093,5 @@ module_exit(wm8580_exit);
MODULE_DESCRIPTION("ASoC WM8580 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
MODULE_LICENSE("GPL");
--
cgit v1.2.3
From a5461fd6c8f70b3d897f5f76612e890ad47a5b93 Mon Sep 17 00:00:00 2001
From: Oder Chiou <oder_chiou@realtek.com>
Date: Tue, 25 Oct 2016 19:27:26 +0800
Subject: ASoC: rt5514: Add the DMIC initial delay to wait it ready.
Due to the DMIC that needs time to initial after the MCLK is provided, the
field of delay time is implemented by the platform data.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/rt5514.txt | 3 +++
include/sound/rt5514.h | 20 ++++++++++++++++++++
sound/soc/codecs/rt5514.c | 17 +++++++++++++++++
sound/soc/codecs/rt5514.h | 2 ++
4 files changed, 42 insertions(+)
create mode 100644 include/sound/rt5514.h
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt
index 9cabfc18cb57..929ca6756b02 100644
--- a/Documentation/devicetree/bindings/sound/rt5514.txt
+++ b/Documentation/devicetree/bindings/sound/rt5514.txt
@@ -13,6 +13,9 @@ Optional properties:
- clocks: The phandle of the master clock to the CODEC
- clock-names: Should be "mclk"
+- realtek,dmic-init-delay-ms
+ Set the DMIC initial delay (ms) to wait it ready.
+
Pins on the device (for linking into audio routes) for RT5514:
* DMIC1L
diff --git a/include/sound/rt5514.h b/include/sound/rt5514.h
new file mode 100644
index 000000000000..ef18494769ee
--- /dev/null
+++ b/include/sound/rt5514.h
@@ -0,0 +1,20 @@
+/*
+ * linux/sound/rt5514.h -- Platform data for RT5514
+ *
+ * Copyright 2016 Realtek Semiconductor Corp.
+ * Author: Oder Chiou <oder_chiou@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_SND_RT5514_H
+#define __LINUX_SND_RT5514_H
+
+struct rt5514_platform_data {
+ unsigned int dmic_init_delay;
+};
+
+#endif
+
diff --git a/sound/soc/codecs/rt5514.c b/sound/soc/codecs/rt5514.c
index f24b7cfd3a89..b281a46d769d 100644
--- a/sound/soc/codecs/rt5514.c
+++ b/sound/soc/codecs/rt5514.c
@@ -452,6 +452,9 @@ static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
RT5514_CLK_DMIC_OUT_SEL_MASK,
idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
+ if (rt5514->pdata.dmic_init_delay)
+ msleep(rt5514->pdata.dmic_init_delay);
+
return idx;
}
@@ -1073,9 +1076,18 @@ static const struct of_device_id rt5514_of_match[] = {
MODULE_DEVICE_TABLE(of, rt5514_of_match);
#endif
+static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev)
+{
+ device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
+ &rt5514->pdata.dmic_init_delay);
+
+ return 0;
+}
+
static int rt5514_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
+ struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct rt5514_priv *rt5514;
int ret;
unsigned int val;
@@ -1087,6 +1099,11 @@ static int rt5514_i2c_probe(struct i2c_client *i2c,
i2c_set_clientdata(i2c, rt5514);
+ if (pdata)
+ rt5514->pdata = *pdata;
+ else if (i2c->dev.of_node)
+ rt5514_parse_dt(rt5514, &i2c->dev);
+
rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
if (IS_ERR(rt5514->i2c_regmap)) {
ret = PTR_ERR(rt5514->i2c_regmap);
diff --git a/sound/soc/codecs/rt5514.h b/sound/soc/codecs/rt5514.h
index 229de0e2c88c..5d343fb6d125 100644
--- a/sound/soc/codecs/rt5514.h
+++ b/sound/soc/codecs/rt5514.h
@@ -13,6 +13,7 @@
#define __RT5514_H__
#include <linux/clk.h>
+#include <sound/rt5514.h>
#define RT5514_DEVICE_ID 0x10ec5514
@@ -243,6 +244,7 @@ enum {
};
struct rt5514_priv {
+ struct rt5514_platform_data pdata;
struct snd_soc_codec *codec;
struct regmap *i2c_regmap, *regmap;
struct clk *mclk;
--
cgit v1.2.3
From 0553d8d0b03ad58f9917460c40a2e2b680f5bfdb Mon Sep 17 00:00:00 2001
From: Alexandre TORGUE <alexandre.torgue@st.com>
Date: Thu, 20 Oct 2016 15:26:52 +0200
Subject: pinctrl: stm32: move gpio irqs binding to optional
stm32 pinctrl driver could be probed even if no interrupt controller
is defined to manage gpio irqs. Entries related to gpio irq management
are moved to optional.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index f9753c416974..b24583aa34c3 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,11 +14,6 @@ Required properies:
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
- - interrupt-parent: phandle of the interrupt parent to which the external
- GPIO interrupts are forwarded to.
- - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
- which includes IRQ mux selection register, and the offset of the IRQ mux
- selection register.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
@@ -37,6 +32,11 @@ Required properties:
Optional properties:
- reset: : Reference to the reset controller
+ - interrupt-parent: phandle of the interrupt parent to which the external
+ GPIO interrupts are forwarded to.
+ - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
+ which includes IRQ mux selection register, and the offset of the IRQ mux
+ selection register.
Example:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
--
cgit v1.2.3
From 8d9e4c9e993f34e7f74bf36f417920a01a42c4b0 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Thu, 3 Nov 2016 15:55:48 +0800
Subject: ASoC: sun4i-codec: Add support for A31 playback through headphone
output
The A31 has a similar codec to the A10/A20. The PCM parts are very
similar, with different register offsets. The analog paths are very
different. There are more inputs and outputs. The ADC mux has been
replaced with a proper mixer.
This patch adds support for the basic playback path of the A31 codec,
from the DAC to the headphones. Headphone detection, microphone,
signaling, other inputs/outputs and capture will be added later.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/sun4i-codec.txt | 22 +-
sound/soc/sunxi/sun4i-codec.c | 271 ++++++++++++++++++++-
2 files changed, 287 insertions(+), 6 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
index 0dce690f78f5..bf480e9683a3 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
@@ -1,8 +1,10 @@
* Allwinner A10 Codec
Required properties:
-- compatible: must be either "allwinner,sun4i-a10-codec" or
- "allwinner,sun7i-a20-codec"
+- compatible: must be one of the following compatibles:
+ - "allwinner,sun4i-a10-codec"
+ - "allwinner,sun6i-a31-codec"
+ - "allwinner,sun7i-a20-codec"
- reg: must contain the registers location and length
- interrupts: must contain the codec interrupt
- dmas: DMA channels for tx and rx dma. See the DMA client binding,
@@ -17,6 +19,10 @@ Required properties:
Optional properties:
- allwinner,pa-gpios: gpio to enable external amplifier
+Required properties for the following compatibles:
+ - "allwinner,sun6i-a31-codec"
+- resets: phandle to the reset control for this device
+
Example:
codec: codec@01c22c00 {
#sound-dai-cells = <0>;
@@ -28,3 +34,15 @@ codec: codec@01c22c00 {
dmas = <&dma 0 19>, <&dma 0 19>;
dma-names = "rx", "tx";
};
+
+codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun6i-a31-codec";
+ reg = <0x01c22c00 0x98>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_APB1_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+};
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index d867b96d367b..d4b2186b5d84 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -109,6 +109,109 @@
/* Microphone controls (sun7i only) */
#define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c)
+/*
+ * sun6i specific registers
+ *
+ * sun6i shares the same digital control and FIFO registers as sun4i,
+ * but only the DAC digital controls are at the same offset. The others
+ * have been moved around to accommodate extra analog controls.
+ */
+
+/* Codec DAC digital controls and FIFO registers */
+#define SUN6I_CODEC_ADC_FIFOC (0x10)
+#define SUN6I_CODEC_ADC_FIFOC_EN_AD (28)
+#define SUN6I_CODEC_ADC_FIFOS (0x14)
+#define SUN6I_CODEC_ADC_RXDATA (0x18)
+
+/* Output mixer and gain controls */
+#define SUN6I_CODEC_OM_DACA_CTRL (0x20)
+#define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31)
+#define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18)
+#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11)
+#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10)
+#define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9)
+#define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8)
+#define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7)
+#define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6)
+#define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0)
+#define SUN6I_CODEC_OM_PA_CTRL (0x24)
+#define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31)
+#define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29)
+#define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28)
+#define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15)
+#define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12)
+#define SUN6I_CODEC_OM_PA_CTRL_LINEING (9)
+#define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6)
+#define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3)
+#define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0)
+
+/* Microphone, line out and phone out controls */
+#define SUN6I_CODEC_MIC_CTRL (0x28)
+#define SUN6I_CODEC_MIC_CTRL_HBIASEN (31)
+#define SUN6I_CODEC_MIC_CTRL_MBIASEN (30)
+#define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28)
+#define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25)
+#define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24)
+#define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21)
+#define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16)
+#define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11)
+#define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8)
+
+/* ADC mixer controls */
+#define SUN6I_CODEC_ADC_ACTL (0x2c)
+#define SUN6I_CODEC_ADC_ACTL_ADCREN (31)
+#define SUN6I_CODEC_ADC_ACTL_ADCLEN (30)
+#define SUN6I_CODEC_ADC_ACTL_ADCRG (27)
+#define SUN6I_CODEC_ADC_ACTL_ADCLG (24)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8)
+#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1)
+#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0)
+
+/* Analog performance tuning controls */
+#define SUN6I_CODEC_ADDA_TUNE (0x30)
+
+/* Calibration controls */
+#define SUN6I_CODEC_CALIBRATION (0x34)
+
+/* FIFO counters */
+#define SUN6I_CODEC_DAC_TXCNT (0x40)
+#define SUN6I_CODEC_ADC_RXCNT (0x44)
+
+/* headset jack detection and button support registers */
+#define SUN6I_CODEC_HMIC_CTL (0x50)
+#define SUN6I_CODEC_HMIC_DATA (0x54)
+
+/* TODO sun6i DAP (Digital Audio Processing) bits */
+
struct sun4i_codec {
struct device *dev;
struct regmap *regmap;
@@ -214,9 +317,14 @@ static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
* Allwinner's code mentions that it is related
* related to microphone gain
*/
- regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
- 0x3 << 25,
- 0x1 << 25);
+ if (of_device_is_compatible(scodec->dev->of_node,
+ "allwinner,sun4i-a10-codec") ||
+ of_device_is_compatible(scodec->dev->of_node,
+ "allwinner,sun7i-a20-codec")) {
+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
+ 0x3 << 25,
+ 0x1 << 25);
+ }
if (of_device_is_compatible(scodec->dev->of_node,
"allwinner,sun7i-a20-codec"))
@@ -516,7 +624,7 @@ static struct snd_soc_dai_driver sun4i_codec_dai = {
},
};
-/*** Codec ***/
+/*** sun4i Codec ***/
static const struct snd_kcontrol_new sun4i_codec_pa_mute =
SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
@@ -652,6 +760,122 @@ static struct snd_soc_codec_driver sun4i_codec_codec = {
},
};
+/*** sun6i Codec ***/
+
+/* mixer controls */
+static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
+ SOC_DAPM_DOUBLE("DAC Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0),
+ SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0),
+};
+
+/* headphone controls */
+static const char * const sun6i_codec_hp_src_enum_text[] = {
+ "DAC", "Mixer",
+};
+
+static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
+ SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
+ sun6i_codec_hp_src_enum_text);
+
+static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
+ SOC_DAPM_ENUM("Headphone Source Playback Route",
+ sun6i_codec_hp_src_enum),
+};
+
+/* volume / mute controls */
+static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0);
+static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1);
+
+static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
+ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
+ sun6i_codec_dvol_scale),
+ SOC_SINGLE_TLV("Headphone Playback Volume",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0,
+ sun6i_codec_hp_vol_scale),
+ SOC_DOUBLE("Headphone Playback Switch",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE,
+ SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
+ /* Digital parts of the DACs */
+ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_EN_DA, 0,
+ NULL, 0),
+
+ /* Analog parts of the DACs */
+ SND_SOC_DAPM_DAC("Left DAC", "Codec Playback",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0),
+ SND_SOC_DAPM_DAC("Right DAC", "Codec Playback",
+ SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0),
+
+ /* Mixers */
+ SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0,
+ sun6i_codec_mixer_controls),
+ SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL,
+ SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0,
+ sun6i_codec_mixer_controls),
+
+ /* Headphone output path */
+ SND_SOC_DAPM_MUX("Headphone Source Playback Route",
+ SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
+ SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL,
+ SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL,
+ SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0),
+ SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL,
+ SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0),
+ SND_SOC_DAPM_OUTPUT("HP"),
+};
+
+static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
+ /* DAC Routes */
+ { "Left DAC", NULL, "DAC Enable" },
+ { "Right DAC", NULL, "DAC Enable" },
+
+ /* Left Mixer Routes */
+ { "Left Mixer", "DAC Playback Switch", "Left DAC" },
+ { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
+
+ /* Right Mixer Routes */
+ { "Right Mixer", "DAC Playback Switch", "Right DAC" },
+ { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
+
+ /* Headphone Routes */
+ { "Headphone Source Playback Route", "DAC", "Left DAC" },
+ { "Headphone Source Playback Route", "DAC", "Right DAC" },
+ { "Headphone Source Playback Route", "Mixer", "Left Mixer" },
+ { "Headphone Source Playback Route", "Mixer", "Right Mixer" },
+ { "Headphone Amp", NULL, "Headphone Source Playback Route" },
+ { "HP", NULL, "Headphone Amp" },
+ { "HPCOM", NULL, "HPCOM Protection" },
+};
+
+static struct snd_soc_codec_driver sun6i_codec_codec = {
+ .component_driver = {
+ .controls = sun6i_codec_codec_widgets,
+ .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets),
+ .dapm_widgets = sun6i_codec_codec_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets),
+ .dapm_routes = sun6i_codec_codec_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes),
+ },
+};
+
static const struct snd_soc_component_driver sun4i_codec_component = {
.name = "sun4i-codec",
};
@@ -756,6 +980,24 @@ static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
return card;
};
+static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->name = "A31 Audio Codec";
+
+ return card;
+};
+
static const struct regmap_config sun4i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -763,6 +1005,13 @@ static const struct regmap_config sun4i_codec_regmap_config = {
.max_register = SUN4I_CODEC_ADC_RXCNT,
};
+static const struct regmap_config sun6i_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN6I_CODEC_HMIC_DATA,
+};
+
static const struct regmap_config sun7i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -788,6 +1037,16 @@ static const struct sun4i_codec_quirks sun4i_codec_quirks = {
.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
};
+static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
+ .regmap_config = &sun6i_codec_regmap_config,
+ .codec = &sun6i_codec_codec,
+ .create_card = sun6i_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
static const struct sun4i_codec_quirks sun7i_codec_quirks = {
.regmap_config = &sun7i_codec_regmap_config,
.codec = &sun4i_codec_codec,
@@ -802,6 +1061,10 @@ static const struct of_device_id sun4i_codec_of_match[] = {
.compatible = "allwinner,sun4i-a10-codec",
.data = &sun4i_codec_quirks,
},
+ {
+ .compatible = "allwinner,sun6i-a31-codec",
+ .data = &sun6i_a31_codec_quirks,
+ },
{
.compatible = "allwinner,sun7i-a20-codec",
.data = &sun7i_codec_quirks,
--
cgit v1.2.3
From 300a18d13f7eaec789e79dc45bce026e098b45da Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Thu, 3 Nov 2016 15:55:53 +0800
Subject: ASoC: sun4i-codec: Add support for A31 board level audio routing
The A31 SoC's codec has various inputs, outputs and microphone bias
supplies. These can be routed on the board in different ways, such as:
- HPCOM may be connected to have the headphone DC coupled.
- Microphones all use the MBIAS main microphone supply or one mic may
use the HBIAS supply, which supports headset detection and buttons.
- Line Out may be routed to an audio jack, or an onboard speaker amp
with power controls.
Add support for specifying the audio routes in the device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/sun4i-codec.txt | 33 ++++++++++++++++++++++
sound/soc/sunxi/sun4i-codec.c | 21 ++++++++++++--
2 files changed, 52 insertions(+), 2 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
index bf480e9683a3..d91a95377f49 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
@@ -22,6 +22,31 @@ Optional properties:
Required properties for the following compatibles:
- "allwinner,sun6i-a31-codec"
- resets: phandle to the reset control for this device
+- allwinner,audio-routing: A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source. Valid names include:
+
+ Audio pins on the SoC:
+ "HP"
+ "HPCOM"
+ "LINEIN"
+ "LINEOUT"
+ "MIC1"
+ "MIC2"
+ "MIC3"
+
+ Microphone biases from the SoC:
+ "HBIAS"
+ "MBIAS"
+
+ Board connectors:
+ "Headphone"
+ "Headset Mic"
+ "Line In"
+ "Line Out"
+ "Mic"
+ "Speaker"
Example:
codec: codec@01c22c00 {
@@ -45,4 +70,12 @@ codec: codec@01c22c00 {
resets = <&ccu RST_APB1_CODEC>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "rx", "tx";
+ allwinner,audio-routing =
+ "Headphone", "HP",
+ "Speaker", "LINEOUT",
+ "LINEIN", "Line In",
+ "MIC1", "MBIAS",
+ "MIC1", "Mic",
+ "MIC2", "HBIAS",
+ "MIC2", "Headset Mic";
};
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index f55718fe7c5b..1934db29b2b5 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -1104,9 +1104,19 @@ static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
return card;
};
+static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
+ SND_SOC_DAPM_HP("Headphone", NULL),
+ SND_SOC_DAPM_LINE("Line In", NULL),
+ SND_SOC_DAPM_LINE("Line Out", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("Mic", NULL),
+ SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
+};
+
static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
{
struct snd_soc_card *card;
+ int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
@@ -1116,8 +1126,15 @@ static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
if (!card->dai_link)
return ERR_PTR(-ENOMEM);
- card->dev = dev;
- card->name = "A31 Audio Codec";
+ card->dev = dev;
+ card->name = "A31 Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
return card;
};
--
cgit v1.2.3
From 9a76a3ac3b9b6326a317c59126cdf9e758f85375 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Mon, 31 Oct 2016 11:49:41 +0900
Subject: Documentation: synopsys-dw-mshc: add binding for reset-names
Add reset-names property for binding dw-mmc controller.
It might be used together with "reset" property.
- Note: It must be "reset" as name.
Fixes: d6786fefe816 ("mmc: dw_mmc: add reset support to dwmmc host controller")
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 5 +++++
1 file changed, 5 insertions(+)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 4e00e859e885..bfa461aaac99 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -43,6 +43,9 @@ Optional properties:
reset signal present internally in some host controller IC designs.
See Documentation/devicetree/bindings/reset/reset.txt for details.
+* reset-names: request name for using "resets" property. Must be "reset".
+ (It will be used together with "resets" property.)
+
* clocks: from common clock binding: handle to biu and ciu clocks for the
bus interface unit clock and the card interface unit clock.
@@ -103,6 +106,8 @@ board specific portions as listed below.
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst 20>;
+ reset-names = "reset";
};
[board specific internal DMA resources]
--
cgit v1.2.3
From 1219e3db7ecb59ab269e9c8b1a199d82b8d088bb Mon Sep 17 00:00:00 2001
From: "H. Nikolaus Schaller" <hns@goldelico.com>
Date: Tue, 25 Oct 2016 19:38:11 +0200
Subject: ASoC: omap-abe-twl6040: fix typo in bindings documentation
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Acked-by: Peter Ujfalusi <perter.ujfalusi@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
index fd40c852d7c7..462b04e8209f 100644
--- a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
+++ b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
@@ -12,7 +12,7 @@ Required properties:
Optional properties:
- ti,dmic: phandle for the OMAP dmic node if the machine have it connected
-- ti,jack_detection: Need to be present if the board capable to detect jack
+- ti,jack-detection: Need to be present if the board capable to detect jack
insertion, removal.
Available audio endpoints for the audio-routing table:
--
cgit v1.2.3
From da16c55793539a8c83c81240984915ce6d0140fe Mon Sep 17 00:00:00 2001
From: James Schulman <james.schulman@cirrus.com>
Date: Mon, 7 Nov 2016 14:38:38 -0600
Subject: ASoC: cs42l42: Add devicetree bindings for CS42L42
Add devicetree bindings documentation file for Cirrus
Logic CS42L42 codec.
Signed-off-by: James Schulman <james.schulman@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/cs42l42.txt | 110 +++++++++++++++++++++
1 file changed, 110 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/cs42l42.txt
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/cs42l42.txt b/Documentation/devicetree/bindings/sound/cs42l42.txt
new file mode 100644
index 000000000000..9a2c5e2423d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs42l42.txt
@@ -0,0 +1,110 @@
+CS42L42 audio CODEC
+
+Required properties:
+
+ - compatible : "cirrus,cs42l42"
+
+ - reg : the I2C address of the device for I2C.
+
+ - VP-supply, VCP-supply, VD_FILT-supply, VL-supply, VA-supply :
+ power supplies for the device, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+Optional properties:
+
+ - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
+ deasserted before communication to the codec starts.
+
+ - interrupt-parent : Specifies the phandle of the interrupt controller to
+ which the IRQs from CS42L42 are delivered to.
+
+ - interrupts : IRQ line info CS42L42.
+ (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+ for further information relating to interrupt properties)
+
+ - cirrus,ts-inv : Boolean property. For jacks that invert the tip sense
+ polarity. Normal jacks will short tip sense pin to HS1 when headphones are
+ plugged in and leave tip sense floating when not plugged in. Inverting jacks
+ short tip sense when unplugged and float when plugged in.
+
+ 0 = (Default) Non-inverted
+ 1 = Inverted
+
+ - cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no
+ debounce, the tip sense pin might be noisy on a plug event.
+
+ 0 - 0ms,
+ 1 - 125ms,
+ 2 - 250ms,
+ 3 - 500ms,
+ 4 - 750ms,
+ 5 - (Default) 1s,
+ 6 - 1.25s,
+ 7 - 1.5s,
+
+ - cirrus,ts-dbnc-fall : Debounce the falling edge of TIP_SENSE_UNPLUG.
+ With no debounce, the tip sense pin might be noisy on an unplug event.
+
+ 0 - 0ms,
+ 1 - 125ms,
+ 2 - 250ms,
+ 3 - 500ms,
+ 4 - 750ms,
+ 5 - (Default) 1s,
+ 6 - 1.25s,
+ 7 - 1.5s,
+
+ - cirrus,btn-det-init-dbnce : This sets how long the driver sleeps after
+ enabling button detection interrupts. After auto-detection and before
+ servicing button interrupts, the HS bias needs time to settle. If you
+ don't wait, there is possibility for erroneous button interrupt.
+
+ 0ms - 200ms,
+ Default = 100ms
+
+ - cirrus,btn-det-event-dbnce : This sets how long the driver delays after
+ receiving a button press interrupt. With level detect interrupts, you want
+ to wait a small amount of time to make sure the button press is making a
+ clean connection with the bias resistors.
+
+ 0ms - 20ms,
+ Default = 10ms
+
+ - cirrus,bias-lvls : For a level-detect headset button scheme, each button
+ will bias the mic pin to a certain voltage. To determine which button was
+ pressed, the driver will compare this biased voltage to sequential,
+ decreasing voltages and will stop when a comparator is tripped,
+ indicating a comparator voltage < bias voltage. This value represents a
+ percentage of the internally generated HS bias voltage. For different
+ hardware setups, a designer might want to tweak this. This is an array of
+ descending values for the comparator voltage.
+
+ Array of 4 values
+ Each 0-63
+ < x1 x2 x3 x4 >
+ Default = < 15 8 4 1>
+
+
+Example:
+
+cs42l42: cs42l42@48 {
+ compatible = "cirrus,cs42l42";
+ reg = <0x48>;
+ VA-supply = <&dummy_vreg>;
+ VP-supply = <&dummy_vreg>;
+ VCP-supply = <&dummy_vreg>;
+ VD_FILT-supply = <&dummy_vreg>;
+ VL-supply = <&dummy_vreg>;
+
+ reset-gpios = <&axi_gpio_0 1 0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <55 8>
+
+ cirrus,ts-inv = <0x00>;
+ cirrus,ts-dbnc-rise = <0x05>;
+ cirrus,ts-dbnc-fall = <0x00>;
+ cirrus,btn-det-init-dbnce = <100>;
+ cirrus,btn-det-event-dbnce = <10>;
+ cirrus,bias-lvls = <0x0F 0x08 0x04 0x01>;
+ cirrus,hs-bias-ramp-rate = <0x02>;
+};
\ No newline at end of file
--
cgit v1.2.3
From 31a3a7b5b26f75fbe82de10ca99f2b673f6c26b4 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Thu, 10 Nov 2016 11:14:37 -0600
Subject: PCI: rockchip: Add three new resets as required properties
pm_rst, aclk_rst, pclk_rst was controlled by ROM code so the software
wasn't needed to control it again in theory. But it didn't work properly,
so we do need to do it again and add enough delay between the assert of
pm_rst and the deassert of pm_rst. The Soc intergrated with this
controller, rk3399, is still under MP test internally, so the backward
compatibility won't be a big deal.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pci/rockchip-pcie.txt | 11 ++--
drivers/pci/host/pcie-rockchip.c | 62 ++++++++++++++++++++++
2 files changed, 70 insertions(+), 3 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index ba67b39939c1..71aeda1ca055 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -26,13 +26,16 @@ Required properties:
- "sys"
- "legacy"
- "client"
-- resets: Must contain five entries for each entry in reset-names.
+- resets: Must contain seven entries for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following names
- "core"
- "mgmt"
- "mgmt-sticky"
- "pipe"
+ - "pm"
+ - "aclk"
+ - "pclk"
- pinctrl-names : The pin control state names
- pinctrl-0: The "default" pinctrl state
- #interrupt-cells: specifies the number of cells needed to encode an
@@ -86,8 +89,10 @@ pcie0: pcie@f8000000 {
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
reg-names = "axi-base", "apb-base";
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
- <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
- reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
+ <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+ "pm", "pclk", "aclk";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
pinctrl-names = "default";
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e0b22dab9b7a..e04f69beb42d 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -190,6 +190,9 @@ struct rockchip_pcie {
struct reset_control *mgmt_rst;
struct reset_control *mgmt_sticky_rst;
struct reset_control *pipe_rst;
+ struct reset_control *pm_rst;
+ struct reset_control *aclk_rst;
+ struct reset_control *pclk_rst;
struct clk *aclk_pcie;
struct clk *aclk_perf_pcie;
struct clk *hclk_pcie;
@@ -408,6 +411,44 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
gpiod_set_value(rockchip->ep_gpio, 0);
+ err = reset_control_assert(rockchip->aclk_rst);
+ if (err) {
+ dev_err(dev, "assert aclk_rst err %d\n", err);
+ return err;
+ }
+
+ err = reset_control_assert(rockchip->pclk_rst);
+ if (err) {
+ dev_err(dev, "assert pclk_rst err %d\n", err);
+ return err;
+ }
+
+ err = reset_control_assert(rockchip->pm_rst);
+ if (err) {
+ dev_err(dev, "assert pm_rst err %d\n", err);
+ return err;
+ }
+
+ udelay(10);
+
+ err = reset_control_deassert(rockchip->pm_rst);
+ if (err) {
+ dev_err(dev, "deassert pm_rst err %d\n", err);
+ return err;
+ }
+
+ err = reset_control_deassert(rockchip->aclk_rst);
+ if (err) {
+ dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
+ return err;
+ }
+
+ err = reset_control_deassert(rockchip->pclk_rst);
+ if (err) {
+ dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
+ return err;
+ }
+
err = phy_init(rockchip->phy);
if (err < 0) {
dev_err(dev, "fail to init phy, err %d\n", err);
@@ -781,6 +822,27 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
return PTR_ERR(rockchip->pipe_rst);
}
+ rockchip->pm_rst = devm_reset_control_get(dev, "pm");
+ if (IS_ERR(rockchip->pm_rst)) {
+ if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing pm reset property in node\n");
+ return PTR_ERR(rockchip->pm_rst);
+ }
+
+ rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
+ if (IS_ERR(rockchip->pclk_rst)) {
+ if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing pclk reset property in node\n");
+ return PTR_ERR(rockchip->pclk_rst);
+ }
+
+ rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
+ if (IS_ERR(rockchip->aclk_rst)) {
+ if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
+ dev_err(dev, "missing aclk reset property in node\n");
+ return PTR_ERR(rockchip->aclk_rst);
+ }
+
rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
if (IS_ERR(rockchip->ep_gpio)) {
dev_err(dev, "missing ep-gpios property in node\n");
--
cgit v1.2.3
From 4e2cc814eb2755df286ea890078fb636e1aa0f69 Mon Sep 17 00:00:00 2001
From: Peter Ujfalusi <peter.ujfalusi@ti.com>
Date: Thu, 10 Nov 2016 09:55:55 +0200
Subject: ASoC: tlv320aic31xx: Add support for tlv320dac3101
The DAC3101 is mostly identical to DAC3100 with the exception that it has
stereo speaker AMP instead of mono used in DAC3100.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/tlv320aic31xx.txt | 1 +
sound/soc/codecs/tlv320aic31xx.c | 2 ++
sound/soc/codecs/tlv320aic31xx.h | 1 +
3 files changed, 4 insertions(+)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
index 9340d2ddcc54..6fbba562eaa7 100644
--- a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
+++ b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
@@ -12,6 +12,7 @@ Required properties:
"ti,tlv320aic3120" - TLV320AIC3120 (mono speaker amp, MiniDSP)
"ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP)
"ti,tlv320dac3100" - TLV320DAC3100 (no ADC, mono speaker amp, no MiniDSP)
+ "ti,tlv320dac3101" - TLV320DAC3101 (no ADC, stereo speaker amp, no MiniDSP)
- reg - <int> - I2C slave address
- HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply,
diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c
index 8880f6be3336..f8a90ba8cd71 100644
--- a/sound/soc/codecs/tlv320aic31xx.c
+++ b/sound/soc/codecs/tlv320aic31xx.c
@@ -1254,6 +1254,7 @@ static const struct of_device_id tlv320aic31xx_of_match[] = {
{ .compatible = "ti,tlv320aic3120" },
{ .compatible = "ti,tlv320aic3111" },
{ .compatible = "ti,tlv320dac3100" },
+ { .compatible = "ti,tlv320dac3101" },
{},
};
MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
@@ -1380,6 +1381,7 @@ static const struct i2c_device_id aic31xx_i2c_id[] = {
{ "tlv320aic3120", AIC3120 },
{ "tlv320aic3111", AIC3111 },
{ "tlv320dac3100", DAC3100 },
+ { "tlv320dac3101", DAC3101 },
{ }
};
MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
diff --git a/sound/soc/codecs/tlv320aic31xx.h b/sound/soc/codecs/tlv320aic31xx.h
index 5acd5b69fb83..730fb2058869 100644
--- a/sound/soc/codecs/tlv320aic31xx.h
+++ b/sound/soc/codecs/tlv320aic31xx.h
@@ -32,6 +32,7 @@ enum aic31xx_type {
AIC3120 = AIC31XX_MINIDSP_BIT,
AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT),
DAC3100 = DAC31XX_BIT,
+ DAC3101 = DAC31XX_BIT | AIC31XX_STEREO_CLASS_D_BIT,
};
struct aic31xx_pdata {
--
cgit v1.2.3
From 33ada14a26c8f174dac8765f4236ca66c64ae5be Mon Sep 17 00:00:00 2001
From: Bard Liao <bardliao@realtek.com>
Date: Mon, 14 Nov 2016 11:00:10 +0800
Subject: ASoC: add rt5665 codec driver
This is the initial codec driver for rt5665.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/rt5665.txt | 68 +
include/sound/rt5665.h | 47 +
sound/soc/codecs/Kconfig | 6 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/rt5665.c | 4875 ++++++++++++++++++++
sound/soc/codecs/rt5665.h | 1990 ++++++++
6 files changed, 6988 insertions(+)
create mode 100755 Documentation/devicetree/bindings/sound/rt5665.txt
create mode 100755 include/sound/rt5665.h
create mode 100644 sound/soc/codecs/rt5665.c
create mode 100644 sound/soc/codecs/rt5665.h
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt
new file mode 100755
index 000000000000..419c89219681
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5665.txt
@@ -0,0 +1,68 @@
+RT5665/RT5666/RT5668 audio CODEC
+
+This device supports I2C only.
+
+Required properties:
+
+- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668".
+
+- reg : The I2C address of the device.
+
+- interrupts : The CODEC's interrupt output.
+
+Optional properties:
+
+- realtek,in1-differential
+- realtek,in2-differential
+- realtek,in3-differential
+- realtek,in4-differential
+ Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended.
+
+- realtek,dmic1-data-pin
+ 0: dmic1 is not used
+ 1: using GPIO4 pin as dmic1 data pin
+ 2: using IN2N pin as dmic2 data pin
+
+- realtek,dmic2-data-pin
+ 0: dmic2 is not used
+ 1: using GPIO5 pin as dmic2 data pin
+ 2: using IN2P pin as dmic2 data pin
+
+- realtek,jd-src
+ 0: No JD is used
+ 1: using JD1 as JD source
+
+- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
+
+Pins on the device (for linking into audio routes) for RT5659/RT5658:
+
+ * DMIC L1
+ * DMIC R1
+ * DMIC L2
+ * DMIC R2
+ * IN1P
+ * IN1N
+ * IN2P
+ * IN2N
+ * IN3P
+ * IN3N
+ * IN4P
+ * IN4N
+ * HPOL
+ * HPOR
+ * LOUTL
+ * LOUTR
+ * MONOOUT
+ * PDML
+ * PDMR
+
+Example:
+
+rt5659 {
+ compatible = "realtek,rt5665";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+ realtek,ldo1-en-gpios =
+ <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+};
diff --git a/include/sound/rt5665.h b/include/sound/rt5665.h
new file mode 100755
index 000000000000..963229e71dc7
--- /dev/null
+++ b/include/sound/rt5665.h
@@ -0,0 +1,47 @@
+/*
+ * linux/sound/rt5665.h -- Platform data for RT5665
+ *
+ * Copyright 2016 Realtek Microelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_SND_RT5665_H
+#define __LINUX_SND_RT5665_H
+
+enum rt5665_dmic1_data_pin {
+ RT5665_DMIC1_NULL,
+ RT5665_DMIC1_DATA_GPIO4,
+ RT5665_DMIC1_DATA_IN2N,
+};
+
+enum rt5665_dmic2_data_pin {
+ RT5665_DMIC2_NULL,
+ RT5665_DMIC2_DATA_GPIO5,
+ RT5665_DMIC2_DATA_IN2P,
+};
+
+enum rt5665_jd_src {
+ RT5665_JD_NULL,
+ RT5665_JD1,
+};
+
+struct rt5665_platform_data {
+ bool in1_diff;
+ bool in2_diff;
+ bool in3_diff;
+ bool in4_diff;
+
+ int ldo1_en; /* GPIO for LDO1_EN */
+
+ enum rt5665_dmic1_data_pin dmic1_data_pin;
+ enum rt5665_dmic2_data_pin dmic2_data_pin;
+ enum rt5665_jd_src jd_src;
+
+ unsigned int sar_hs_type;
+};
+
+#endif
+
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c67667bb970f..f1de9720d9d3 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -114,6 +114,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_RT5651 if I2C
select SND_SOC_RT5659 if I2C
select SND_SOC_RT5660 if I2C
+ select SND_SOC_RT5665 if I2C
select SND_SOC_RT5663 if I2C
select SND_SOC_RT5670 if I2C
select SND_SOC_RT5677 if I2C && SPI_MASTER
@@ -649,6 +650,7 @@ config SND_SOC_RL6231
default y if SND_SOC_RT5651=y
default y if SND_SOC_RT5659=y
default y if SND_SOC_RT5660=y
+ default y if SND_SOC_RT5665=y
default y if SND_SOC_RT5663=y
default y if SND_SOC_RT5670=y
default y if SND_SOC_RT5677=y
@@ -659,6 +661,7 @@ config SND_SOC_RL6231
default m if SND_SOC_RT5651=m
default m if SND_SOC_RT5659=m
default m if SND_SOC_RT5660=m
+ default m if SND_SOC_RT5665=m
default m if SND_SOC_RT5663=m
default m if SND_SOC_RT5670=m
default m if SND_SOC_RT5677=m
@@ -708,6 +711,9 @@ config SND_SOC_RT5659
config SND_SOC_RT5660
tristate
+config SND_SOC_RT5665
+ tristate
+
config SND_SOC_RT5663
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 958cd4912fbc..e1704e09806c 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -114,6 +114,7 @@ snd-soc-rt5645-objs := rt5645.o
snd-soc-rt5651-objs := rt5651.o
snd-soc-rt5659-objs := rt5659.o
snd-soc-rt5660-objs := rt5660.o
+snd-soc-rt5665-objs := rt5665.o
snd-soc-rt5663-objs := rt5663.o
snd-soc-rt5670-objs := rt5670.o
snd-soc-rt5677-objs := rt5677.o
@@ -338,6 +339,7 @@ obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o
obj-$(CONFIG_SND_SOC_RT5660) += snd-soc-rt5660.o
+obj-$(CONFIG_SND_SOC_RT5665) += snd-soc-rt5665.o
obj-$(CONFIG_SND_SOC_RT5663) += snd-soc-rt5663.o
obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
diff --git a/sound/soc/codecs/rt5665.c b/sound/soc/codecs/rt5665.c
new file mode 100644
index 000000000000..34254fd47efe
--- /dev/null
+++ b/sound/soc/codecs/rt5665.c
@@ -0,0 +1,4875 @@
+/*
+ * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
+ *
+ * Copyright 2016 Realtek Semiconductor Corp.
+ * Author: Bard Liao <bardliao@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/acpi.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mutex.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/jack.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/rt5665.h>
+
+#include "rl6231.h"
+#include "rt5665.h"
+
+#define RT5665_NUM_SUPPLIES 3
+
+static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
+ "AVDD",
+ "MICVDD",
+ "VBAT",
+};
+
+struct rt5665_priv {
+ struct snd_soc_codec *codec;
+ struct rt5665_platform_data pdata;
+ struct regmap *regmap;
+ struct gpio_desc *gpiod_ldo1_en;
+ struct gpio_desc *gpiod_reset;
+ struct snd_soc_jack *hs_jack;
+ struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
+ struct delayed_work jack_detect_work;
+ struct delayed_work calibrate_work;
+ struct delayed_work jd_check_work;
+ struct mutex calibrate_mutex;
+
+ int sysclk;
+ int sysclk_src;
+ int lrck[RT5665_AIFS];
+ int bclk[RT5665_AIFS];
+ int master[RT5665_AIFS];
+ int id;
+
+ int pll_src;
+ int pll_in;
+ int pll_out;
+
+ int jack_type;
+ int irq_work_delay_time;
+ unsigned int sar_adc_value;
+};
+
+static const struct reg_default rt5665_reg[] = {
+ {0x0000, 0x0000},
+ {0x0001, 0xc8c8},
+ {0x0002, 0x8080},
+ {0x0003, 0x8000},
+ {0x0004, 0xc80a},
+ {0x0005, 0x0000},
+ {0x0006, 0x0000},
+ {0x0007, 0x0000},
+ {0x000a, 0x0000},
+ {0x000b, 0x0000},
+ {0x000c, 0x0000},
+ {0x000d, 0x0000},
+ {0x000f, 0x0808},
+ {0x0010, 0x4040},
+ {0x0011, 0x0000},
+ {0x0012, 0x1404},
+ {0x0013, 0x1000},
+ {0x0014, 0xa00a},
+ {0x0015, 0x0404},
+ {0x0016, 0x0404},
+ {0x0017, 0x0011},
+ {0x0018, 0xafaf},
+ {0x0019, 0xafaf},
+ {0x001a, 0xafaf},
+ {0x001b, 0x0011},
+ {0x001c, 0x2f2f},
+ {0x001d, 0x2f2f},
+ {0x001e, 0x2f2f},
+ {0x001f, 0x0000},
+ {0x0020, 0x0000},
+ {0x0021, 0x0000},
+ {0x0022, 0x5757},
+ {0x0023, 0x0039},
+ {0x0026, 0xc0c0},
+ {0x0027, 0xc0c0},
+ {0x0028, 0xc0c0},
+ {0x0029, 0x8080},
+ {0x002a, 0xaaaa},
+ {0x002b, 0xaaaa},
+ {0x002c, 0xaba8},
+ {0x002d, 0x0000},
+ {0x002e, 0x0000},
+ {0x002f, 0x0000},
+ {0x0030, 0x0000},
+ {0x0031, 0x5000},
+ {0x0032, 0x0000},
+ {0x0033, 0x0000},
+ {0x0034, 0x0000},
+ {0x0035, 0x0000},
+ {0x003a, 0x0000},
+ {0x003b, 0x0000},
+ {0x003c, 0x00ff},
+ {0x003d, 0x0000},
+ {0x003e, 0x00ff},
+ {0x003f, 0x0000},
+ {0x0040, 0x0000},
+ {0x0041, 0x00ff},
+ {0x0042, 0x0000},
+ {0x0043, 0x00ff},
+ {0x0044, 0x0c0c},
+ {0x0049, 0xc00b},
+ {0x004a, 0x0000},
+ {0x004b, 0x031f},
+ {0x004d, 0x0000},
+ {0x004e, 0x001f},
+ {0x004f, 0x0000},
+ {0x0050, 0x001f},
+ {0x0052, 0xf000},
+ {0x0061, 0x0000},
+ {0x0062, 0x0000},
+ {0x0063, 0x003e},
+ {0x0064, 0x0000},
+ {0x0065, 0x0000},
+ {0x0066, 0x003f},
+ {0x0067, 0x0000},
+ {0x006b, 0x0000},
+ {0x006d, 0xff00},
+ {0x006e, 0x2808},
+ {0x006f, 0x000a},
+ {0x0070, 0x8000},
+ {0x0071, 0x8000},
+ {0x0072, 0x8000},
+ {0x0073, 0x7000},
+ {0x0074, 0x7770},
+ {0x0075, 0x0002},
+ {0x0076, 0x0001},
+ {0x0078, 0x00f0},
+ {0x0079, 0x0000},
+ {0x007a, 0x0000},
+ {0x007b, 0x0000},
+ {0x007c, 0x0000},
+ {0x007d, 0x0123},
+ {0x007e, 0x4500},
+ {0x007f, 0x8003},
+ {0x0080, 0x0000},
+ {0x0081, 0x0000},
+ {0x0082, 0x0000},
+ {0x0083, 0x0000},
+ {0x0084, 0x0000},
+ {0x0085, 0x0000},
+ {0x0086, 0x0008},
+ {0x0087, 0x0000},
+ {0x0088, 0x0000},
+ {0x0089, 0x0000},
+ {0x008a, 0x0000},
+ {0x008b, 0x0000},
+ {0x008c, 0x0003},
+ {0x008e, 0x0060},
+ {0x008f, 0x1000},
+ {0x0091, 0x0c26},
+ {0x0092, 0x0073},
+ {0x0093, 0x0000},
+ {0x0094, 0x0080},
+ {0x0098, 0x0000},
+ {0x0099, 0x0000},
+ {0x009a, 0x0007},
+ {0x009f, 0x0000},
+ {0x00a0, 0x0000},
+ {0x00a1, 0x0002},
+ {0x00a2, 0x0001},
+ {0x00a3, 0x0002},
+ {0x00a4, 0x0001},
+ {0x00ae, 0x2040},
+ {0x00af, 0x0000},
+ {0x00b6, 0x0000},
+ {0x00b7, 0x0000},
+ {0x00b8, 0x0000},
+ {0x00b9, 0x0000},
+ {0x00ba, 0x0002},
+ {0x00bb, 0x0000},
+ {0x00be, 0x0000},
+ {0x00c0, 0x0000},
+ {0x00c1, 0x0aaa},
+ {0x00c2, 0xaa80},
+ {0x00c3, 0x0003},
+ {0x00c4, 0x0000},
+ {0x00d0, 0x0000},
+ {0x00d1, 0x2244},
+ {0x00d3, 0x3300},
+ {0x00d4, 0x2200},
+ {0x00d9, 0x0809},
+ {0x00da, 0x0000},
+ {0x00db, 0x0008},
+ {0x00dc, 0x00c0},
+ {0x00dd, 0x6724},
+ {0x00de, 0x3131},
+ {0x00df, 0x0008},
+ {0x00e0, 0x4000},
+ {0x00e1, 0x3131},
+ {0x00e2, 0x600c},
+ {0x00ea, 0xb320},
+ {0x00eb, 0x0000},
+ {0x00ec, 0xb300},
+ {0x00ed, 0x0000},
+ {0x00ee, 0xb320},
+ {0x00ef, 0x0000},
+ {0x00f0, 0x0201},
+ {0x00f1, 0x0ddd},
+ {0x00f2, 0x0ddd},
+ {0x00f6, 0x0000},
+ {0x00f7, 0x0000},
+ {0x00f8, 0x0000},
+ {0x00fa, 0x0000},
+ {0x00fb, 0x0000},
+ {0x00fc, 0x0000},
+ {0x00fd, 0x0000},
+ {0x00fe, 0x10ec},
+ {0x00ff, 0x6451},
+ {0x0100, 0xaaaa},
+ {0x0101, 0x000a},
+ {0x010a, 0xaaaa},
+ {0x010b, 0xa0a0},
+ {0x010c, 0xaeae},
+ {0x010d, 0xaaaa},
+ {0x010e, 0xaaaa},
+ {0x010f, 0xaaaa},
+ {0x0110, 0xe002},
+ {0x0111, 0xa402},
+ {0x0112, 0xaaaa},
+ {0x0113, 0x2000},
+ {0x0117, 0x0f00},
+ {0x0125, 0x0410},
+ {0x0132, 0x0000},
+ {0x0133, 0x0000},
+ {0x0137, 0x5540},
+ {0x0138, 0x3700},
+ {0x0139, 0x79a1},
+ {0x013a, 0x2020},
+ {0x013b, 0x2020},
+ {0x013c, 0x2005},
+ {0x013f, 0x0000},
+ {0x0145, 0x0002},
+ {0x0146, 0x0000},
+ {0x0147, 0x0000},
+ {0x0148, 0x0000},
+ {0x0150, 0x0000},
+ {0x0160, 0x4eff},
+ {0x0161, 0x0080},
+ {0x0162, 0x0200},
+ {0x0163, 0x0800},
+ {0x0164, 0x0000},
+ {0x0165, 0x0000},
+ {0x0166, 0x0000},
+ {0x0167, 0x000f},
+ {0x0170, 0x4e87},
+ {0x0171, 0x0080},
+ {0x0172, 0x0200},
+ {0x0173, 0x0800},
+ {0x0174, 0x00ff},
+ {0x0175, 0x0000},
+ {0x0190, 0x413d},
+ {0x0191, 0x4139},
+ {0x0192, 0x4135},
+ {0x0193, 0x413d},
+ {0x0194, 0x0000},
+ {0x0195, 0x0000},
+ {0x0196, 0x0000},
+ {0x0197, 0x0000},
+ {0x0198, 0x0000},
+ {0x0199, 0x0000},
+ {0x01a0, 0x1e64},
+ {0x01a1, 0x06a3},
+ {0x01a2, 0x0000},
+ {0x01a3, 0x0000},
+ {0x01a4, 0x0000},
+ {0x01a5, 0x0000},
+ {0x01a6, 0x0000},
+ {0x01a7, 0x8000},
+ {0x01a8, 0x0000},
+ {0x01a9, 0x0000},
+ {0x01aa, 0x0000},
+ {0x01ab, 0x0000},
+ {0x01b5, 0x0000},
+ {0x01b6, 0x01c3},
+ {0x01b7, 0x02a0},
+ {0x01b8, 0x03e9},
+ {0x01b9, 0x1389},
+ {0x01ba, 0xc351},
+ {0x01bb, 0x0009},
+ {0x01bc, 0x0018},
+ {0x01bd, 0x002a},
+ {0x01be, 0x004c},
+ {0x01bf, 0x0097},
+ {0x01c0, 0x433d},
+ {0x01c1, 0x0000},
+ {0x01c2, 0x0000},
+ {0x01c3, 0x0000},
+ {0x01c4, 0x0000},
+ {0x01c5, 0x0000},
+ {0x01c6, 0x0000},
+ {0x01c7, 0x0000},
+ {0x01c8, 0x40af},
+ {0x01c9, 0x0702},
+ {0x01ca, 0x0000},
+ {0x01cb, 0x0000},
+ {0x01cc, 0x5757},
+ {0x01cd, 0x5757},
+ {0x01ce, 0x5757},
+ {0x01cf, 0x5757},
+ {0x01d0, 0x5757},
+ {0x01d1, 0x5757},
+ {0x01d2, 0x5757},
+ {0x01d3, 0x5757},
+ {0x01d4, 0x5757},
+ {0x01d5, 0x5757},
+ {0x01d6, 0x003c},
+ {0x01da, 0x0000},
+ {0x01db, 0x0000},
+ {0x01dc, 0x0000},
+ {0x01de, 0x7c00},
+ {0x01df, 0x0320},
+ {0x01e0, 0x06a1},
+ {0x01e1, 0x0000},
+ {0x01e2, 0x0000},
+ {0x01e3, 0x0000},
+ {0x01e4, 0x0000},
+ {0x01e6, 0x0001},
+ {0x01e7, 0x0000},
+ {0x01e8, 0x0000},
+ {0x01ea, 0xbf3f},
+ {0x01eb, 0x0000},
+ {0x01ec, 0x0000},
+ {0x01ed, 0x0000},
+ {0x01ee, 0x0000},
+ {0x01ef, 0x0000},
+ {0x01f0, 0x0000},
+ {0x01f1, 0x0000},
+ {0x01f2, 0x0000},
+ {0x01f3, 0x0000},
+ {0x01f4, 0x0000},
+ {0x0200, 0x0000},
+ {0x0201, 0x0000},
+ {0x0202, 0x0000},
+ {0x0203, 0x0000},
+ {0x0204, 0x0000},
+ {0x0205, 0x0000},
+ {0x0206, 0x0000},
+ {0x0207, 0x0000},
+ {0x0208, 0x0000},
+ {0x0210, 0x60b1},
+ {0x0211, 0xa005},
+ {0x0212, 0x024c},
+ {0x0213, 0xf7ff},
+ {0x0214, 0x024c},
+ {0x0215, 0x0102},
+ {0x0216, 0x00a3},
+ {0x0217, 0x0048},
+ {0x0218, 0xa2c0},
+ {0x0219, 0x0400},
+ {0x021a, 0x00c8},
+ {0x021b, 0x00c0},
+ {0x02ff, 0x0110},
+ {0x0300, 0x001f},
+ {0x0301, 0x032c},
+ {0x0302, 0x5f21},
+ {0x0303, 0x4000},
+ {0x0304, 0x4000},
+ {0x0305, 0x06d5},
+ {0x0306, 0x8000},
+ {0x0307, 0x0700},
+ {0x0310, 0x4560},
+ {0x0311, 0xa4a8},
+ {0x0312, 0x7418},
+ {0x0313, 0x0000},
+ {0x0314, 0x0006},
+ {0x0315, 0xffff},
+ {0x0316, 0xc400},
+ {0x0317, 0x0000},
+ {0x0330, 0x00a6},
+ {0x0331, 0x04c3},
+ {0x0332, 0x27c8},
+ {0x0333, 0xbf50},
+ {0x0334, 0x0045},
+ {0x0335, 0x0007},
+ {0x0336, 0x7418},
+ {0x0337, 0x0501},
+ {0x0338, 0x0000},
+ {0x0339, 0x0010},
+ {0x033a, 0x1010},
+ {0x03c0, 0x7e00},
+ {0x03c1, 0x8000},
+ {0x03c2, 0x8000},
+ {0x03c3, 0x8000},
+ {0x03c4, 0x8000},
+ {0x03c5, 0x8000},
+ {0x03c6, 0x8000},
+ {0x03c7, 0x8000},
+ {0x03c8, 0x8000},
+ {0x03c9, 0x8000},
+ {0x03ca, 0x8000},
+ {0x03cb, 0x8000},
+ {0x03cc, 0x8000},
+ {0x03d0, 0x0000},
+ {0x03d1, 0x0000},
+ {0x03d2, 0x0000},
+ {0x03d3, 0x0000},
+ {0x03d4, 0x2000},
+ {0x03d5, 0x2000},
+ {0x03d6, 0x0000},
+ {0x03d7, 0x0000},
+ {0x03d8, 0x2000},
+ {0x03d9, 0x2000},
+ {0x03da, 0x2000},
+ {0x03db, 0x2000},
+ {0x03dc, 0x0000},
+ {0x03dd, 0x0000},
+ {0x03de, 0x0000},
+ {0x03df, 0x2000},
+ {0x03e0, 0x0000},
+ {0x03e1, 0x0000},
+ {0x03e2, 0x0000},
+ {0x03e3, 0x0000},
+ {0x03e4, 0x0000},
+ {0x03e5, 0x0000},
+ {0x03e6, 0x0000},
+ {0x03e7, 0x0000},
+ {0x03e8, 0x0000},
+ {0x03e9, 0x0000},
+ {0x03ea, 0x0000},
+ {0x03eb, 0x0000},
+ {0x03ec, 0x0000},
+ {0x03ed, 0x0000},
+ {0x03ee, 0x0000},
+ {0x03ef, 0x0000},
+ {0x03f0, 0x0800},
+ {0x03f1, 0x0800},
+ {0x03f2, 0x0800},
+ {0x03f3, 0x0800},
+};
+
+static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case RT5665_RESET:
+ case RT5665_EJD_CTRL_2:
+ case RT5665_GPIO_STA:
+ case RT5665_INT_ST_1:
+ case RT5665_IL_CMD_1:
+ case RT5665_4BTN_IL_CMD_1:
+ case RT5665_PSV_IL_CMD_1:
+ case RT5665_AJD1_CTRL:
+ case RT5665_JD_CTRL_3:
+ case RT5665_STO_NG2_CTRL_1:
+ case RT5665_SAR_IL_CMD_4:
+ case RT5665_DEVICE_ID:
+ case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
+ case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
+ case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
+ case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool rt5665_readable_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case RT5665_RESET:
+ case RT5665_VENDOR_ID:
+ case RT5665_VENDOR_ID_1:
+ case RT5665_DEVICE_ID:
+ case RT5665_LOUT:
+ case RT5665_HP_CTRL_1:
+ case RT5665_HP_CTRL_2:
+ case RT5665_MONO_OUT:
+ case RT5665_HPL_GAIN:
+ case RT5665_HPR_GAIN:
+ case RT5665_MONO_GAIN:
+ case RT5665_CAL_BST_CTRL:
+ case RT5665_CBJ_BST_CTRL:
+ case RT5665_IN1_IN2:
+ case RT5665_IN3_IN4:
+ case RT5665_INL1_INR1_VOL:
+ case RT5665_EJD_CTRL_1:
+ case RT5665_EJD_CTRL_2:
+ case RT5665_EJD_CTRL_3:
+ case RT5665_EJD_CTRL_4:
+ case RT5665_EJD_CTRL_5:
+ case RT5665_EJD_CTRL_6:
+ case RT5665_EJD_CTRL_7:
+ case RT5665_DAC2_CTRL:
+ case RT5665_DAC2_DIG_VOL:
+ case RT5665_DAC1_DIG_VOL:
+ case RT5665_DAC3_DIG_VOL:
+ case RT5665_DAC3_CTRL:
+ case RT5665_STO1_ADC_DIG_VOL:
+ case RT5665_MONO_ADC_DIG_VOL:
+ case RT5665_STO2_ADC_DIG_VOL:
+ case RT5665_STO1_ADC_BOOST:
+ case RT5665_MONO_ADC_BOOST:
+ case RT5665_STO2_ADC_BOOST:
+ case RT5665_HP_IMP_GAIN_1:
+ case RT5665_HP_IMP_GAIN_2:
+ case RT5665_STO1_ADC_MIXER:
+ case RT5665_MONO_ADC_MIXER:
+ case RT5665_STO2_ADC_MIXER:
+ case RT5665_AD_DA_MIXER:
+ case RT5665_STO1_DAC_MIXER:
+ case RT5665_MONO_DAC_MIXER:
+ case RT5665_STO2_DAC_MIXER:
+ case RT5665_A_DAC1_MUX:
+ case RT5665_A_DAC2_MUX:
+ case RT5665_DIG_INF2_DATA:
+ case RT5665_DIG_INF3_DATA:
+ case RT5665_PDM_OUT_CTRL:
+ case RT5665_PDM_DATA_CTRL_1:
+ case RT5665_PDM_DATA_CTRL_2:
+ case RT5665_PDM_DATA_CTRL_3:
+ case RT5665_PDM_DATA_CTRL_4:
+ case RT5665_REC1_GAIN:
+ case RT5665_REC1_L1_MIXER:
+ case RT5665_REC1_L2_MIXER:
+ case RT5665_REC1_R1_MIXER:
+ case RT5665_REC1_R2_MIXER:
+ case RT5665_REC2_GAIN:
+ case RT5665_REC2_L1_MIXER:
+ case RT5665_REC2_L2_MIXER:
+ case RT5665_REC2_R1_MIXER:
+ case RT5665_REC2_R2_MIXER:
+ case RT5665_CAL_REC:
+ case RT5665_ALC_BACK_GAIN:
+ case RT5665_MONOMIX_GAIN:
+ case RT5665_MONOMIX_IN_GAIN:
+ case RT5665_OUT_L_GAIN:
+ case RT5665_OUT_L_MIXER:
+ case RT5665_OUT_R_GAIN:
+ case RT5665_OUT_R_MIXER:
+ case RT5665_LOUT_MIXER:
+ case RT5665_PWR_DIG_1:
+ case RT5665_PWR_DIG_2:
+ case RT5665_PWR_ANLG_1:
+ case RT5665_PWR_ANLG_2:
+ case RT5665_PWR_ANLG_3:
+ case RT5665_PWR_MIXER:
+ case RT5665_PWR_VOL:
+ case RT5665_CLK_DET:
+ case RT5665_HPF_CTRL1:
+ case RT5665_DMIC_CTRL_1:
+ case RT5665_DMIC_CTRL_2:
+ case RT5665_I2S1_SDP:
+ case RT5665_I2S2_SDP:
+ case RT5665_I2S3_SDP:
+ case RT5665_ADDA_CLK_1:
+ case RT5665_ADDA_CLK_2:
+ case RT5665_I2S1_F_DIV_CTRL_1:
+ case RT5665_I2S1_F_DIV_CTRL_2:
+ case RT5665_TDM_CTRL_1:
+ case RT5665_TDM_CTRL_2:
+ case RT5665_TDM_CTRL_3:
+ case RT5665_TDM_CTRL_4:
+ case RT5665_TDM_CTRL_5:
+ case RT5665_TDM_CTRL_6:
+ case RT5665_TDM_CTRL_7:
+ case RT5665_TDM_CTRL_8:
+ case RT5665_GLB_CLK:
+ case RT5665_PLL_CTRL_1:
+ case RT5665_PLL_CTRL_2:
+ case RT5665_ASRC_1:
+ case RT5665_ASRC_2:
+ case RT5665_ASRC_3:
+ case RT5665_ASRC_4:
+ case RT5665_ASRC_5:
+ case RT5665_ASRC_6:
+ case RT5665_ASRC_7:
+ case RT5665_ASRC_8:
+ case RT5665_ASRC_9:
+ case RT5665_ASRC_10:
+ case RT5665_DEPOP_1:
+ case RT5665_DEPOP_2:
+ case RT5665_HP_CHARGE_PUMP_1:
+ case RT5665_HP_CHARGE_PUMP_2:
+ case RT5665_MICBIAS_1:
+ case RT5665_MICBIAS_2:
+ case RT5665_ASRC_12:
+ case RT5665_ASRC_13:
+ case RT5665_ASRC_14:
+ case RT5665_RC_CLK_CTRL:
+ case RT5665_I2S_M_CLK_CTRL_1:
+ case RT5665_I2S2_F_DIV_CTRL_1:
+ case RT5665_I2S2_F_DIV_CTRL_2:
+ case RT5665_I2S3_F_DIV_CTRL_1:
+ case RT5665_I2S3_F_DIV_CTRL_2:
+ case RT5665_EQ_CTRL_1:
+ case RT5665_EQ_CTRL_2:
+ case RT5665_IRQ_CTRL_1:
+ case RT5665_IRQ_CTRL_2:
+ case RT5665_IRQ_CTRL_3:
+ case RT5665_IRQ_CTRL_4:
+ case RT5665_IRQ_CTRL_5:
+ case RT5665_IRQ_CTRL_6:
+ case RT5665_INT_ST_1:
+ case RT5665_GPIO_CTRL_1:
+ case RT5665_GPIO_CTRL_2:
+ case RT5665_GPIO_CTRL_3:
+ case RT5665_GPIO_CTRL_4:
+ case RT5665_GPIO_STA:
+ case RT5665_HP_AMP_DET_CTRL_1:
+ case RT5665_HP_AMP_DET_CTRL_2:
+ case RT5665_MID_HP_AMP_DET:
+ case RT5665_LOW_HP_AMP_DET:
+ case RT5665_SV_ZCD_1:
+ case RT5665_SV_ZCD_2:
+ case RT5665_IL_CMD_1:
+ case RT5665_IL_CMD_2:
+ case RT5665_IL_CMD_3:
+ case RT5665_IL_CMD_4:
+ case RT5665_4BTN_IL_CMD_1:
+ case RT5665_4BTN_IL_CMD_2:
+ case RT5665_4BTN_IL_CMD_3:
+ case RT5665_PSV_IL_CMD_1:
+ case RT5665_ADC_STO1_HP_CTRL_1:
+ case RT5665_ADC_STO1_HP_CTRL_2:
+ case RT5665_ADC_MONO_HP_CTRL_1:
+ case RT5665_ADC_MONO_HP_CTRL_2:
+ case RT5665_ADC_STO2_HP_CTRL_1:
+ case RT5665_ADC_STO2_HP_CTRL_2:
+ case RT5665_AJD1_CTRL:
+ case RT5665_JD1_THD:
+ case RT5665_JD2_THD:
+ case RT5665_JD_CTRL_1:
+ case RT5665_JD_CTRL_2:
+ case RT5665_JD_CTRL_3:
+ case RT5665_DIG_MISC:
+ case RT5665_DUMMY_2:
+ case RT5665_DUMMY_3:
+ case RT5665_DAC_ADC_DIG_VOL1:
+ case RT5665_DAC_ADC_DIG_VOL2:
+ case RT5665_BIAS_CUR_CTRL_1:
+ case RT5665_BIAS_CUR_CTRL_2:
+ case RT5665_BIAS_CUR_CTRL_3:
+ case RT5665_BIAS_CUR_CTRL_4:
+ case RT5665_BIAS_CUR_CTRL_5:
+ case RT5665_BIAS_CUR_CTRL_6:
+ case RT5665_BIAS_CUR_CTRL_7:
+ case RT5665_BIAS_CUR_CTRL_8:
+ case RT5665_BIAS_CUR_CTRL_9:
+ case RT5665_BIAS_CUR_CTRL_10:
+ case RT5665_VREF_REC_OP_FB_CAP_CTRL:
+ case RT5665_CHARGE_PUMP_1:
+ case RT5665_DIG_IN_CTRL_1:
+ case RT5665_DIG_IN_CTRL_2:
+ case RT5665_PAD_DRIVING_CTRL:
+ case RT5665_SOFT_RAMP_DEPOP:
+ case RT5665_PLL:
+ case RT5665_CHOP_DAC:
+ case RT5665_CHOP_ADC:
+ case RT5665_CALIB_ADC_CTRL:
+ case RT5665_VOL_TEST:
+ case RT5665_TEST_MODE_CTRL_1:
+ case RT5665_TEST_MODE_CTRL_2:
+ case RT5665_TEST_MODE_CTRL_3:
+ case RT5665_TEST_MODE_CTRL_4:
+ case RT5665_BASSBACK_CTRL:
+ case RT5665_STO_NG2_CTRL_1:
+ case RT5665_STO_NG2_CTRL_2:
+ case RT5665_STO_NG2_CTRL_3:
+ case RT5665_STO_NG2_CTRL_4:
+ case RT5665_STO_NG2_CTRL_5:
+ case RT5665_STO_NG2_CTRL_6:
+ case RT5665_STO_NG2_CTRL_7:
+ case RT5665_STO_NG2_CTRL_8:
+ case RT5665_MONO_NG2_CTRL_1:
+ case RT5665_MONO_NG2_CTRL_2:
+ case RT5665_MONO_NG2_CTRL_3:
+ case RT5665_MONO_NG2_CTRL_4:
+ case RT5665_MONO_NG2_CTRL_5:
+ case RT5665_MONO_NG2_CTRL_6:
+ case RT5665_STO1_DAC_SIL_DET:
+ case RT5665_MONOL_DAC_SIL_DET:
+ case RT5665_MONOR_DAC_SIL_DET:
+ case RT5665_STO2_DAC_SIL_DET:
+ case RT5665_SIL_PSV_CTRL1:
+ case RT5665_SIL_PSV_CTRL2:
+ case RT5665_SIL_PSV_CTRL3:
+ case RT5665_SIL_PSV_CTRL4:
+ case RT5665_SIL_PSV_CTRL5:
+ case RT5665_SIL_PSV_CTRL6:
+ case RT5665_MONO_AMP_CALIB_CTRL_1:
+ case RT5665_MONO_AMP_CALIB_CTRL_2:
+ case RT5665_MONO_AMP_CALIB_CTRL_3:
+ case RT5665_MONO_AMP_CALIB_CTRL_4:
+ case RT5665_MONO_AMP_CALIB_CTRL_5:
+ case RT5665_MONO_AMP_CALIB_CTRL_6:
+ case RT5665_MONO_AMP_CALIB_CTRL_7:
+ case RT5665_MONO_AMP_CALIB_STA1:
+ case RT5665_MONO_AMP_CALIB_STA2:
+ case RT5665_MONO_AMP_CALIB_STA3:
+ case RT5665_MONO_AMP_CALIB_STA4:
+ case RT5665_MONO_AMP_CALIB_STA6:
+ case RT5665_HP_IMP_SENS_CTRL_01:
+ case RT5665_HP_IMP_SENS_CTRL_02:
+ case RT5665_HP_IMP_SENS_CTRL_03:
+ case RT5665_HP_IMP_SENS_CTRL_04:
+ case RT5665_HP_IMP_SENS_CTRL_05:
+ case RT5665_HP_IMP_SENS_CTRL_06:
+ case RT5665_HP_IMP_SENS_CTRL_07:
+ case RT5665_HP_IMP_SENS_CTRL_08:
+ case RT5665_HP_IMP_SENS_CTRL_09:
+ case RT5665_HP_IMP_SENS_CTRL_10:
+ case RT5665_HP_IMP_SENS_CTRL_11:
+ case RT5665_HP_IMP_SENS_CTRL_12:
+ case RT5665_HP_IMP_SENS_CTRL_13:
+ case RT5665_HP_IMP_SENS_CTRL_14:
+ case RT5665_HP_IMP_SENS_CTRL_15:
+ case RT5665_HP_IMP_SENS_CTRL_16:
+ case RT5665_HP_IMP_SENS_CTRL_17:
+ case RT5665_HP_IMP_SENS_CTRL_18:
+ case RT5665_HP_IMP_SENS_CTRL_19:
+ case RT5665_HP_IMP_SENS_CTRL_20:
+ case RT5665_HP_IMP_SENS_CTRL_21:
+ case RT5665_HP_IMP_SENS_CTRL_22:
+ case RT5665_HP_IMP_SENS_CTRL_23:
+ case RT5665_HP_IMP_SENS_CTRL_24:
+ case RT5665_HP_IMP_SENS_CTRL_25:
+ case RT5665_HP_IMP_SENS_CTRL_26:
+ case RT5665_HP_IMP_SENS_CTRL_27:
+ case RT5665_HP_IMP_SENS_CTRL_28:
+ case RT5665_HP_IMP_SENS_CTRL_29:
+ case RT5665_HP_IMP_SENS_CTRL_30:
+ case RT5665_HP_IMP_SENS_CTRL_31:
+ case RT5665_HP_IMP_SENS_CTRL_32:
+ case RT5665_HP_IMP_SENS_CTRL_33:
+ case RT5665_HP_IMP_SENS_CTRL_34:
+ case RT5665_HP_LOGIC_CTRL_1:
+ case RT5665_HP_LOGIC_CTRL_2:
+ case RT5665_HP_LOGIC_CTRL_3:
+ case RT5665_HP_CALIB_CTRL_1:
+ case RT5665_HP_CALIB_CTRL_2:
+ case RT5665_HP_CALIB_CTRL_3:
+ case RT5665_HP_CALIB_CTRL_4:
+ case RT5665_HP_CALIB_CTRL_5:
+ case RT5665_HP_CALIB_CTRL_6:
+ case RT5665_HP_CALIB_CTRL_7:
+ case RT5665_HP_CALIB_CTRL_9:
+ case RT5665_HP_CALIB_CTRL_10:
+ case RT5665_HP_CALIB_CTRL_11:
+ case RT5665_HP_CALIB_STA_1:
+ case RT5665_HP_CALIB_STA_2:
+ case RT5665_HP_CALIB_STA_3:
+ case RT5665_HP_CALIB_STA_4:
+ case RT5665_HP_CALIB_STA_5:
+ case RT5665_HP_CALIB_STA_6:
+ case RT5665_HP_CALIB_STA_7:
+ case RT5665_HP_CALIB_STA_8:
+ case RT5665_HP_CALIB_STA_9:
+ case RT5665_HP_CALIB_STA_10:
+ case RT5665_HP_CALIB_STA_11:
+ case RT5665_PGM_TAB_CTRL1:
+ case RT5665_PGM_TAB_CTRL2:
+ case RT5665_PGM_TAB_CTRL3:
+ case RT5665_PGM_TAB_CTRL4:
+ case RT5665_PGM_TAB_CTRL5:
+ case RT5665_PGM_TAB_CTRL6:
+ case RT5665_PGM_TAB_CTRL7:
+ case RT5665_PGM_TAB_CTRL8:
+ case RT5665_PGM_TAB_CTRL9:
+ case RT5665_SAR_IL_CMD_1:
+ case RT5665_SAR_IL_CMD_2:
+ case RT5665_SAR_IL_CMD_3:
+ case RT5665_SAR_IL_CMD_4:
+ case RT5665_SAR_IL_CMD_5:
+ case RT5665_SAR_IL_CMD_6:
+ case RT5665_SAR_IL_CMD_7:
+ case RT5665_SAR_IL_CMD_8:
+ case RT5665_SAR_IL_CMD_9:
+ case RT5665_SAR_IL_CMD_10:
+ case RT5665_SAR_IL_CMD_11:
+ case RT5665_SAR_IL_CMD_12:
+ case RT5665_DRC1_CTRL_0:
+ case RT5665_DRC1_CTRL_1:
+ case RT5665_DRC1_CTRL_2:
+ case RT5665_DRC1_CTRL_3:
+ case RT5665_DRC1_CTRL_4:
+ case RT5665_DRC1_CTRL_5:
+ case RT5665_DRC1_CTRL_6:
+ case RT5665_DRC1_HARD_LMT_CTRL_1:
+ case RT5665_DRC1_HARD_LMT_CTRL_2:
+ case RT5665_DRC1_PRIV_1:
+ case RT5665_DRC1_PRIV_2:
+ case RT5665_DRC1_PRIV_3:
+ case RT5665_DRC1_PRIV_4:
+ case RT5665_DRC1_PRIV_5:
+ case RT5665_DRC1_PRIV_6:
+ case RT5665_DRC1_PRIV_7:
+ case RT5665_DRC1_PRIV_8:
+ case RT5665_ALC_PGA_CTRL_1:
+ case RT5665_ALC_PGA_CTRL_2:
+ case RT5665_ALC_PGA_CTRL_3:
+ case RT5665_ALC_PGA_CTRL_4:
+ case RT5665_ALC_PGA_CTRL_5:
+ case RT5665_ALC_PGA_CTRL_6:
+ case RT5665_ALC_PGA_CTRL_7:
+ case RT5665_ALC_PGA_CTRL_8:
+ case RT5665_ALC_PGA_STA_1:
+ case RT5665_ALC_PGA_STA_2:
+ case RT5665_ALC_PGA_STA_3:
+ case RT5665_EQ_AUTO_RCV_CTRL1:
+ case RT5665_EQ_AUTO_RCV_CTRL2:
+ case RT5665_EQ_AUTO_RCV_CTRL3:
+ case RT5665_EQ_AUTO_RCV_CTRL4:
+ case RT5665_EQ_AUTO_RCV_CTRL5:
+ case RT5665_EQ_AUTO_RCV_CTRL6:
+ case RT5665_EQ_AUTO_RCV_CTRL7:
+ case RT5665_EQ_AUTO_RCV_CTRL8:
+ case RT5665_EQ_AUTO_RCV_CTRL9:
+ case RT5665_EQ_AUTO_RCV_CTRL10:
+ case RT5665_EQ_AUTO_RCV_CTRL11:
+ case RT5665_EQ_AUTO_RCV_CTRL12:
+ case RT5665_EQ_AUTO_RCV_CTRL13:
+ case RT5665_ADC_L_EQ_LPF1_A1:
+ case RT5665_R_EQ_LPF1_A1:
+ case RT5665_L_EQ_LPF1_H0:
+ case RT5665_R_EQ_LPF1_H0:
+ case RT5665_L_EQ_BPF1_A1:
+ case RT5665_R_EQ_BPF1_A1:
+ case RT5665_L_EQ_BPF1_A2:
+ case RT5665_R_EQ_BPF1_A2:
+ case RT5665_L_EQ_BPF1_H0:
+ case RT5665_R_EQ_BPF1_H0:
+ case RT5665_L_EQ_BPF2_A1:
+ case RT5665_R_EQ_BPF2_A1:
+ case RT5665_L_EQ_BPF2_A2:
+ case RT5665_R_EQ_BPF2_A2:
+ case RT5665_L_EQ_BPF2_H0:
+ case RT5665_R_EQ_BPF2_H0:
+ case RT5665_L_EQ_BPF3_A1:
+ case RT5665_R_EQ_BPF3_A1:
+ case RT5665_L_EQ_BPF3_A2:
+ case RT5665_R_EQ_BPF3_A2:
+ case RT5665_L_EQ_BPF3_H0:
+ case RT5665_R_EQ_BPF3_H0:
+ case RT5665_L_EQ_BPF4_A1:
+ case RT5665_R_EQ_BPF4_A1:
+ case RT5665_L_EQ_BPF4_A2:
+ case RT5665_R_EQ_BPF4_A2:
+ case RT5665_L_EQ_BPF4_H0:
+ case RT5665_R_EQ_BPF4_H0:
+ case RT5665_L_EQ_HPF1_A1:
+ case RT5665_R_EQ_HPF1_A1:
+ case RT5665_L_EQ_HPF1_H0:
+ case RT5665_R_EQ_HPF1_H0:
+ case RT5665_L_EQ_PRE_VOL:
+ case RT5665_R_EQ_PRE_VOL:
+ case RT5665_L_EQ_POST_VOL:
+ case RT5665_R_EQ_POST_VOL:
+ case RT5665_SCAN_MODE_CTRL:
+ case RT5665_I2C_MODE:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
+static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
+static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
+static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
+
+/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
+static const DECLARE_TLV_DB_RANGE(bst_tlv,
+ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
+ 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
+ 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
+ 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
+ 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
+ 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
+);
+
+/* Interface data select */
+static const char * const rt5665_data_select[] = {
+ "L/R", "R/L", "L/L", "R/R"
+};
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
+ RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
+ RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
+ RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
+ RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
+ RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
+ RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
+ RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
+
+static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
+ SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
+ SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
+
+static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
+ SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
+ SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
+
+static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
+ SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
+
+static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
+ SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
+
+static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
+ SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
+
+static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ int ret = snd_soc_put_volsw(kcontrol, ucontrol);
+
+ if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
+ snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
+ snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_EN);
+ }
+
+ return ret;
+}
+
+static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ int ret = snd_soc_put_volsw(kcontrol, ucontrol);
+
+ if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
+ snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
+ snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_EN);
+ }
+
+ return ret;
+}
+
+/**
+ * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
+ * @codec: SoC audio codec device.
+ * @filter_mask: mask of filters.
+ * @clk_src: clock source
+ *
+ * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
+ * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
+ * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
+ * ASRC function will track i2s clock and generate a corresponding system clock
+ * for codec. This function provides an API to select the clock source for a
+ * set of filters specified by the mask. And the codec driver will turn on ASRC
+ * for these filters if ASRC is selected as their clock source.
+ */
+int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
+ unsigned int filter_mask, unsigned int clk_src)
+{
+ unsigned int asrc2_mask = 0;
+ unsigned int asrc2_value = 0;
+ unsigned int asrc3_mask = 0;
+ unsigned int asrc3_value = 0;
+
+ switch (clk_src) {
+ case RT5665_CLK_SEL_SYS:
+ case RT5665_CLK_SEL_I2S1_ASRC:
+ case RT5665_CLK_SEL_I2S2_ASRC:
+ case RT5665_CLK_SEL_I2S3_ASRC:
+ case RT5665_CLK_SEL_SYS2:
+ case RT5665_CLK_SEL_SYS3:
+ case RT5665_CLK_SEL_SYS4:
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ if (filter_mask & RT5665_DA_STEREO1_FILTER) {
+ asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
+ asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
+ | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_DA_STEREO2_FILTER) {
+ asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
+ asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
+ | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_DA_MONO_L_FILTER) {
+ asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
+ asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
+ | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_DA_MONO_R_FILTER) {
+ asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
+ asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
+ | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_AD_STEREO1_FILTER) {
+ asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
+ asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
+ | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_AD_STEREO2_FILTER) {
+ asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
+ asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
+ | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_AD_MONO_L_FILTER) {
+ asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
+ asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
+ | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
+ }
+
+ if (filter_mask & RT5665_AD_MONO_R_FILTER) {
+ asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
+ asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
+ | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
+ }
+
+ if (asrc2_mask)
+ snd_soc_update_bits(codec, RT5665_ASRC_2,
+ asrc2_mask, asrc2_value);
+
+ if (asrc3_mask)
+ snd_soc_update_bits(codec, RT5665_ASRC_3,
+ asrc3_mask, asrc3_value);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
+
+static int rt5665_button_detect(struct snd_soc_codec *codec)
+{
+ int btn_type, val;
+
+ val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
+ btn_type = val & 0xfff0;
+ snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
+
+ return btn_type;
+}
+
+static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
+ bool enable)
+{
+ if (enable) {
+ snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x000b);
+ snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
+ snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
+ RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
+ RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
+ snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
+ RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
+ } else {
+ snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
+ RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
+ snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
+ RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
+ snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
+ RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
+ }
+}
+
+/**
+ * rt5665_headset_detect - Detect headset.
+ * @codec: SoC audio codec device.
+ * @jack_insert: Jack insert or not.
+ *
+ * Detect whether is headset or not when jack inserted.
+ *
+ * Returns detect status.
+ */
+static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+ struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
+ unsigned int sar_hs_type, val;
+
+ if (jack_insert) {
+ snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
+ snd_soc_dapm_sync(dapm);
+
+ regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
+ 0x100);
+
+ regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
+ if (val & 0x4) {
+ regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
+ 0x100, 0);
+
+ regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
+ while (val & 0x4) {
+ usleep_range(10000, 15000);
+ regmap_read(rt5665->regmap, RT5665_GPIO_STA,
+ &val);
+ }
+ }
+
+ regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
+ 0x180, 0x180);
+ regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
+ regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
+
+ rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
+ RT5665_SAR_IL_CMD_4) & 0x7ff;
+
+ sar_hs_type = rt5665->pdata.sar_hs_type ?
+ rt5665->pdata.sar_hs_type : 729;
+
+ if (rt5665->sar_adc_value > sar_hs_type) {
+ rt5665->jack_type = SND_JACK_HEADSET;
+ rt5665_enable_push_button_irq(codec, true);
+ } else {
+ rt5665->jack_type = SND_JACK_HEADPHONE;
+ regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
+ 0x2291);
+ regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
+ 0x100, 0);
+ snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
+ snd_soc_dapm_sync(dapm);
+ }
+ } else {
+ regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
+ regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
+ snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
+ snd_soc_dapm_sync(dapm);
+ if (rt5665->jack_type == SND_JACK_HEADSET)
+ rt5665_enable_push_button_irq(codec, false);
+ rt5665->jack_type = 0;
+ }
+
+ dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
+ return rt5665->jack_type;
+}
+
+static irqreturn_t rt5665_irq(int irq, void *data)
+{
+ struct rt5665_priv *rt5665 = data;
+
+ mod_delayed_work(system_power_efficient_wq,
+ &rt5665->jack_detect_work, msecs_to_jiffies(250));
+
+ return IRQ_HANDLED;
+}
+
+static void rt5665_jd_check_handler(struct work_struct *work)
+{
+ struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
+ calibrate_work.work);
+
+ if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
+ /* jack out */
+ rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
+
+ snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
+ SND_JACK_HEADSET |
+ SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+ SND_JACK_BTN_2 | SND_JACK_BTN_3);
+ } else {
+ schedule_delayed_work(&rt5665->jd_check_work, 500);
+ }
+}
+
+int rt5665_set_jack_detect(struct snd_soc_codec *codec,
+ struct snd_soc_jack *hs_jack)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ switch (rt5665->pdata.jd_src) {
+ case RT5665_JD1:
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
+ RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
+ regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
+ 0xc000, 0xc000);
+ regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
+ RT5665_PWR_JD1, RT5665_PWR_JD1);
+ regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
+ break;
+
+ case RT5665_JD_NULL:
+ break;
+
+ default:
+ dev_warn(codec->dev, "Wrong JD source\n");
+ break;
+ }
+
+ rt5665->hs_jack = hs_jack;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(rt5665_set_jack_detect);
+
+static void rt5665_jack_detect_handler(struct work_struct *work)
+{
+ struct rt5665_priv *rt5665 =
+ container_of(work, struct rt5665_priv, jack_detect_work.work);
+ int val, btn_type;
+
+ while (!rt5665->codec) {
+ pr_debug("%s codec = null\n", __func__);
+ usleep_range(10000, 15000);
+ }
+
+ while (!rt5665->codec->component.card->instantiated) {
+ pr_debug("%s\n", __func__);
+ usleep_range(10000, 15000);
+ }
+
+ mutex_lock(&rt5665->calibrate_mutex);
+
+ val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
+ if (!val) {
+ /* jack in */
+ if (rt5665->jack_type == 0) {
+ /* jack was out, report jack type */
+ rt5665->jack_type =
+ rt5665_headset_detect(rt5665->codec, 1);
+ } else {
+ /* jack is already in, report button event */
+ rt5665->jack_type = SND_JACK_HEADSET;
+ btn_type = rt5665_button_detect(rt5665->codec);
+ /**
+ * rt5665 can report three kinds of button behavior,
+ * one click, double click and hold. However,
+ * currently we will report button pressed/released
+ * event. So all the three button behaviors are
+ * treated as button pressed.
+ */
+ switch (btn_type) {
+ case 0x8000:
+ case 0x4000:
+ case 0x2000:
+ rt5665->jack_type |= SND_JACK_BTN_0;
+ break;
+ case 0x1000:
+ case 0x0800:
+ case 0x0400:
+ rt5665->jack_type |= SND_JACK_BTN_1;
+ break;
+ case 0x0200:
+ case 0x0100:
+ case 0x0080:
+ rt5665->jack_type |= SND_JACK_BTN_2;
+ break;
+ case 0x0040:
+ case 0x0020:
+ case 0x0010:
+ rt5665->jack_type |= SND_JACK_BTN_3;
+ break;
+ case 0x0000: /* unpressed */
+ break;
+ default:
+ btn_type = 0;
+ dev_err(rt5665->codec->dev,
+ "Unexpected button code 0x%04x\n",
+ btn_type);
+ break;
+ }
+ }
+ } else {
+ /* jack out */
+ rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
+ }
+
+ snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
+ SND_JACK_HEADSET |
+ SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+ SND_JACK_BTN_2 | SND_JACK_BTN_3);
+
+ if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+ SND_JACK_BTN_2 | SND_JACK_BTN_3))
+ schedule_delayed_work(&rt5665->jd_check_work, 0);
+ else
+ cancel_delayed_work_sync(&rt5665->jd_check_work);
+
+ mutex_unlock(&rt5665->calibrate_mutex);
+}
+
+static const struct snd_kcontrol_new rt5665_snd_controls[] = {
+ /* Headphone Output Volume */
+ SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
+ RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
+ rt5665_hp_vol_put, hp_vol_tlv),
+
+ /* Mono Output Volume */
+ SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
+ RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
+ rt5665_mono_vol_put, mono_vol_tlv),
+
+ /* Output Volume */
+ SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
+ RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
+
+ /* DAC Digital Volume */
+ SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
+ RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
+ SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
+ RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
+ SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
+ RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
+
+ /* IN1/IN2/IN3/IN4 Volume */
+ SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
+ RT5665_BST1_SFT, 69, 0, in_bst_tlv),
+ SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
+ RT5665_BST2_SFT, 69, 0, in_bst_tlv),
+ SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
+ RT5665_BST3_SFT, 69, 0, in_bst_tlv),
+ SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
+ RT5665_BST4_SFT, 69, 0, in_bst_tlv),
+ SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
+ RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
+
+ /* INL/INR Volume Control */
+ SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
+ RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
+
+ /* ADC Digital Volume Control */
+ SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
+ RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
+ RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
+ SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
+ RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
+ RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
+ SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
+ RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
+ SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
+ RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
+
+ /* ADC Boost Volume Control */
+ SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
+ RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
+ 3, 0, adc_bst_tlv),
+
+ SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
+ RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
+ 3, 0, adc_bst_tlv),
+
+ SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
+ RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
+ 3, 0, adc_bst_tlv),
+};
+
+/**
+ * set_dmic_clk - Set parameter of dmic.
+ *
+ * @w: DAPM widget.
+ * @kcontrol: The kcontrol of this widget.
+ * @event: Event id.
+ *
+ * Choose dmic clock between 1MHz and 3MHz.
+ * It is better for clock to approximate 3MHz.
+ */
+static int set_dmic_clk(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+ int pd, idx = -EINVAL;
+
+ pd = rl6231_get_pre_div(rt5665->regmap,
+ RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
+ idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
+
+ if (idx < 0)
+ dev_err(codec->dev, "Failed to set DMIC clock\n");
+ else {
+ snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
+ }
+ return idx;
+}
+
+static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
+ RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
+ RT5665_PM_HP_HV | RT5665_OSW_L_EN);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
+ RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
+ RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
+ struct snd_soc_dapm_widget *sink)
+{
+ unsigned int val;
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ val = snd_soc_read(codec, RT5665_GLB_CLK);
+ val &= RT5665_SCLK_SRC_MASK;
+ if (val == RT5665_SCLK_SRC_PLL1)
+ return 1;
+ else
+ return 0;
+}
+
+static int is_using_asrc(struct snd_soc_dapm_widget *w,
+ struct snd_soc_dapm_widget *sink)
+{
+ unsigned int reg, shift, val;
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (w->shift) {
+ case RT5665_ADC_MONO_R_ASRC_SFT:
+ reg = RT5665_ASRC_3;
+ shift = RT5665_AD_MONOR_CLK_SEL_SFT;
+ break;
+ case RT5665_ADC_MONO_L_ASRC_SFT:
+ reg = RT5665_ASRC_3;
+ shift = RT5665_AD_MONOL_CLK_SEL_SFT;
+ break;
+ case RT5665_ADC_STO1_ASRC_SFT:
+ reg = RT5665_ASRC_3;
+ shift = RT5665_AD_STO1_CLK_SEL_SFT;
+ break;
+ case RT5665_ADC_STO2_ASRC_SFT:
+ reg = RT5665_ASRC_3;
+ shift = RT5665_AD_STO2_CLK_SEL_SFT;
+ break;
+ case RT5665_DAC_MONO_R_ASRC_SFT:
+ reg = RT5665_ASRC_2;
+ shift = RT5665_DA_MONOR_CLK_SEL_SFT;
+ break;
+ case RT5665_DAC_MONO_L_ASRC_SFT:
+ reg = RT5665_ASRC_2;
+ shift = RT5665_DA_MONOL_CLK_SEL_SFT;
+ break;
+ case RT5665_DAC_STO1_ASRC_SFT:
+ reg = RT5665_ASRC_2;
+ shift = RT5665_DA_STO1_CLK_SEL_SFT;
+ break;
+ case RT5665_DAC_STO2_ASRC_SFT:
+ reg = RT5665_ASRC_2;
+ shift = RT5665_DA_STO2_CLK_SEL_SFT;
+ break;
+ default:
+ return 0;
+ }
+
+ val = (snd_soc_read(codec, reg) >> shift) & 0xf;
+ switch (val) {
+ case RT5665_CLK_SEL_I2S1_ASRC:
+ case RT5665_CLK_SEL_I2S2_ASRC:
+ case RT5665_CLK_SEL_I2S3_ASRC:
+ /* I2S_Pre_Div1 should be 1 in asrc mode */
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
+ RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
+ return 1;
+ default:
+ return 0;
+ }
+
+}
+
+/* Digital Mixer */
+static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
+ RT5665_M_STO1_ADC_L1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
+ RT5665_M_STO1_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
+ RT5665_M_STO1_ADC_R1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
+ RT5665_M_STO1_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
+ RT5665_M_STO2_ADC_L1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
+ RT5665_M_STO2_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
+ RT5665_M_STO2_ADC_R1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
+ RT5665_M_STO2_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
+ RT5665_M_MONO_ADC_L1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
+ RT5665_M_MONO_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
+ SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
+ RT5665_M_MONO_ADC_R1_SFT, 1, 1),
+ SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
+ RT5665_M_MONO_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
+ RT5665_M_ADCMIX_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
+ RT5665_M_DAC1_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
+ RT5665_M_ADCMIX_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
+ RT5665_M_DAC1_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
+ RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
+ RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
+ RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
+ RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
+ RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
+ RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
+ RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
+ RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
+};
+
+/* Analog Input Mixer */
+static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
+ SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_CBJ_RM1_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_INL_RM1_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_INR_RM1_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_BST4_RM1_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_BST3_RM1_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_BST2_RM1_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
+ RT5665_M_BST1_RM1_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
+ SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
+ RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
+ RT5665_M_INR_RM1_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
+ RT5665_M_BST4_RM1_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
+ RT5665_M_BST3_RM1_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
+ RT5665_M_BST2_RM1_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
+ RT5665_M_BST1_RM1_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
+ SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_INL_RM2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_INR_RM2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_CBJ_RM2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_BST4_RM2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_BST3_RM2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_BST2_RM2_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
+ RT5665_M_BST1_RM2_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
+ SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_INL_RM2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_INR_RM2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_BST4_RM2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_BST3_RM2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_BST2_RM2_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
+ RT5665_M_BST1_RM2_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_DAC_L2_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_RECMIC2L_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_BST1_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_BST2_MM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_BST3_MM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
+ RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
+ RT5665_M_IN_L_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
+ RT5665_M_BST1_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
+ RT5665_M_BST2_OM_L_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
+ RT5665_M_BST3_OM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
+ RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
+ RT5665_M_IN_R_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
+ RT5665_M_BST2_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
+ RT5665_M_BST3_OM_R_SFT, 1, 1),
+ SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
+ RT5665_M_BST4_OM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_mono_mix[] = {
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_DAC_L2_MA_SFT, 1, 1),
+ SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
+ RT5665_M_MONOVOL_MA_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
+ SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
+ RT5665_M_DAC_L2_LM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
+ RT5665_M_OV_L_LM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
+ SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
+ RT5665_M_DAC_R2_LM_SFT, 1, 1),
+ SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
+ RT5665_M_OV_R_LM_SFT, 1, 1),
+};
+
+/*DAC L2, DAC R2*/
+/*MX-17 [6:4], MX-17 [2:0]*/
+static const char * const rt5665_dac2_src[] = {
+ "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
+ RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
+
+static const struct snd_kcontrol_new rt5665_dac_l2_mux =
+ SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
+ RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
+
+static const struct snd_kcontrol_new rt5665_dac_r2_mux =
+ SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
+
+/*DAC L3, DAC R3*/
+/*MX-1B [6:4], MX-1B [2:0]*/
+static const char * const rt5665_dac3_src[] = {
+ "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
+ RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
+
+static const struct snd_kcontrol_new rt5665_dac_l3_mux =
+ SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
+ RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
+
+static const struct snd_kcontrol_new rt5665_dac_r3_mux =
+ SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
+
+/* STO1 ADC1 Source */
+/* MX-26 [13] [5] */
+static const char * const rt5665_sto1_adc1_src[] = {
+ "DD Mux", "ADC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
+ SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
+ SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
+
+/* STO1 ADC Source */
+/* MX-26 [11:10] [3:2] */
+static const char * const rt5665_sto1_adc_src[] = {
+ "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
+ SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
+ SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
+
+/* STO1 ADC2 Source */
+/* MX-26 [12] [4] */
+static const char * const rt5665_sto1_adc2_src[] = {
+ "DAC MIX", "DMIC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
+ SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
+ SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
+
+/* STO1 DMIC Source */
+/* MX-26 [8] */
+static const char * const rt5665_sto1_dmic_src[] = {
+ "DMIC1", "DMIC2"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
+ SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
+
+/* MX-26 [9] */
+static const char * const rt5665_sto1_dd_l_src[] = {
+ "STO2 DAC", "MONO DAC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
+ SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
+
+/* MX-26 [1:0] */
+static const char * const rt5665_sto1_dd_r_src[] = {
+ "STO2 DAC", "MONO DAC", "AEC REF"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
+ RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
+
+static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
+ SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
+
+/* MONO ADC L2 Source */
+/* MX-27 [12] */
+static const char * const rt5665_mono_adc_l2_src[] = {
+ "DAC MIXL", "DMIC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
+
+static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
+ SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
+
+
+/* MONO ADC L1 Source */
+/* MX-27 [13] */
+static const char * const rt5665_mono_adc_l1_src[] = {
+ "DD Mux", "ADC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
+
+static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
+ SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
+
+/* MX-27 [9][1]*/
+static const char * const rt5665_mono_dd_src[] = {
+ "STO2 DAC", "MONO DAC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
+
+static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
+ SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
+
+static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
+ SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
+
+/* MONO ADC L Source, MONO ADC R Source*/
+/* MX-27 [11:10], MX-27 [3:2] */
+static const char * const rt5665_mono_adc_src[] = {
+ "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
+
+static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
+ SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
+
+static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
+ SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
+
+/* MONO DMIC L Source */
+/* MX-27 [8] */
+static const char * const rt5665_mono_dmic_l_src[] = {
+ "DMIC1 L", "DMIC2 L"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
+
+static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
+ SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
+
+/* MONO ADC R2 Source */
+/* MX-27 [4] */
+static const char * const rt5665_mono_adc_r2_src[] = {
+ "DAC MIXR", "DMIC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
+
+static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
+ SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
+
+/* MONO ADC R1 Source */
+/* MX-27 [5] */
+static const char * const rt5665_mono_adc_r1_src[] = {
+ "DD Mux", "ADC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
+
+static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
+ SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
+
+/* MONO DMIC R Source */
+/* MX-27 [0] */
+static const char * const rt5665_mono_dmic_r_src[] = {
+ "DMIC1 R", "DMIC2 R"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
+ RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
+
+static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
+ SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
+
+
+/* STO2 ADC1 Source */
+/* MX-28 [13] [5] */
+static const char * const rt5665_sto2_adc1_src[] = {
+ "DD Mux", "ADC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
+ SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
+ SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
+
+/* STO2 ADC Source */
+/* MX-28 [11:10] [3:2] */
+static const char * const rt5665_sto2_adc_src[] = {
+ "ADC1 L", "ADC1 R", "ADC2 L"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
+ SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
+ SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
+
+/* STO2 ADC2 Source */
+/* MX-28 [12] [4] */
+static const char * const rt5665_sto2_adc2_src[] = {
+ "DAC MIX", "DMIC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
+ SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
+ SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
+
+/* STO2 DMIC Source */
+/* MX-28 [8] */
+static const char * const rt5665_sto2_dmic_src[] = {
+ "DMIC1", "DMIC2"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
+ SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
+
+/* MX-28 [9] */
+static const char * const rt5665_sto2_dd_l_src[] = {
+ "STO2 DAC", "MONO DAC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
+ SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
+
+/* MX-28 [1] */
+static const char * const rt5665_sto2_dd_r_src[] = {
+ "STO2 DAC", "MONO DAC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
+ RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
+
+static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
+ SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
+
+/* DAC R1 Source, DAC L1 Source*/
+/* MX-29 [11:10], MX-29 [9:8]*/
+static const char * const rt5665_dac1_src[] = {
+ "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
+ RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
+
+static const struct snd_kcontrol_new rt5665_dac_r1_mux =
+ SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
+ RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
+
+static const struct snd_kcontrol_new rt5665_dac_l1_mux =
+ SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
+
+/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
+/* MX-2D [13:12], MX-2D [9:8]*/
+static const char * const rt5665_dig_dac_mix_src[] = {
+ "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
+ RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
+
+static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
+ SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
+ RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
+
+static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
+ SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
+
+/* Analog DAC L1 Source, Analog DAC R1 Source*/
+/* MX-2D [5:4], MX-2D [1:0]*/
+static const char * const rt5665_alg_dac1_src[] = {
+ "Stereo1 DAC Mixer", "DAC1", "DMIC1"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
+ RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
+
+static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
+ SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
+ RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
+
+static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
+ SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
+
+/* Analog DAC LR Source, Analog DAC R2 Source*/
+/* MX-2E [5:4], MX-2E [0]*/
+static const char * const rt5665_alg_dac2_src[] = {
+ "Mono DAC Mixer", "DAC2"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
+ RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
+
+static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
+ SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
+ RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
+
+static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
+ SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
+
+/* Interface2 ADC Data Input*/
+/* MX-2F [14:12] */
+static const char * const rt5665_if2_1_adc_in_src[] = {
+ "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
+ "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
+ RT5665_IF3_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
+
+static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
+ SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
+
+/* MX-2F [6:4] */
+static const char * const rt5665_if2_2_adc_in_src[] = {
+ "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
+ "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
+ RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
+
+static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
+ SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
+
+/* Interface3 ADC Data Input*/
+/* MX-30 [6:4] */
+static const char * const rt5665_if3_adc_in_src[] = {
+ "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
+ "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
+ RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
+
+static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
+ SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
+
+/* PDM 1 L/R*/
+/* MX-31 [11:10] [9:8] */
+static const char * const rt5665_pdm_src[] = {
+ "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
+ RT5665_PDM1_L_SFT, rt5665_pdm_src);
+
+static const struct snd_kcontrol_new rt5665_pdm_l_mux =
+ SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
+ RT5665_PDM1_R_SFT, rt5665_pdm_src);
+
+static const struct snd_kcontrol_new rt5665_pdm_r_mux =
+ SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
+
+
+/* I2S1 TDM ADCDAT Source */
+/* MX-7a[10] */
+static const char * const rt5665_if1_1_adc1_data_src[] = {
+ "STO1 ADC", "IF2_1 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
+ RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
+ SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
+
+/* MX-7a[9] */
+static const char * const rt5665_if1_1_adc2_data_src[] = {
+ "STO2 ADC", "IF2_2 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
+ RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
+ SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
+
+/* MX-7a[8] */
+static const char * const rt5665_if1_1_adc3_data_src[] = {
+ "MONO ADC", "IF3 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
+ RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
+ SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
+
+/* MX-7b[10] */
+static const char * const rt5665_if1_2_adc1_data_src[] = {
+ "STO1 ADC", "IF1 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
+ RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
+ SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
+
+/* MX-7b[9] */
+static const char * const rt5665_if1_2_adc2_data_src[] = {
+ "STO2 ADC", "IF2_1 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
+ RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
+ SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
+
+/* MX-7b[8] */
+static const char * const rt5665_if1_2_adc3_data_src[] = {
+ "MONO ADC", "IF2_2 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
+ RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
+ SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
+
+/* MX-7b[7] */
+static const char * const rt5665_if1_2_adc4_data_src[] = {
+ "DAC1", "IF3 DAC",
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
+ RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
+
+static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
+ SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
+
+/* MX-7a[4:0] MX-7b[4:0] */
+static const char * const rt5665_tdm_adc_data_src[] = {
+ "1234", "1243", "1324", "1342", "1432", "1423",
+ "2134", "2143", "2314", "2341", "2431", "2413",
+ "3124", "3142", "3214", "3241", "3412", "3421",
+ "4123", "4132", "4213", "4231", "4312", "4321"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
+ RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
+
+static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
+ SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
+
+static const SOC_ENUM_SINGLE_DECL(
+ rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
+ RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
+
+static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
+ SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
+
+/* Out Volume Switch */
+static const struct snd_kcontrol_new monovol_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
+
+static const struct snd_kcontrol_new outvol_l_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
+
+static const struct snd_kcontrol_new outvol_r_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
+
+/* Out Switch */
+static const struct snd_kcontrol_new mono_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
+
+static const struct snd_kcontrol_new hpo_switch =
+ SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
+ RT5665_VOL_L_SFT, 1, 0);
+
+static const struct snd_kcontrol_new lout_l_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
+
+static const struct snd_kcontrol_new lout_r_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
+
+static const struct snd_kcontrol_new pdm_l_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
+ RT5665_M_PDM1_L_SFT, 1, 1);
+
+static const struct snd_kcontrol_new pdm_r_switch =
+ SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
+ RT5665_M_PDM1_R_SFT, 1, 1);
+
+static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_EN);
+ snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
+ 0x0);
+ snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
+ snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
+ snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
+ snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
+ 0x40);
+ snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+
+}
+
+static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_EN);
+ snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
+ snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
+ RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+
+}
+
+static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, RT5665_DEPOP_1,
+ RT5665_PUMP_EN, RT5665_PUMP_EN);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, RT5665_DEPOP_1,
+ RT5665_PUMP_EN, 0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+
+}
+
+static int set_dmic_power(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ /*Add delay to avoid pop noise*/
+ msleep(150);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ switch (w->shift) {
+ case RT5665_PWR_VREF1_BIT:
+ snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
+ RT5665_PWR_FV1, 0);
+ break;
+
+ case RT5665_PWR_VREF2_BIT:
+ snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
+ RT5665_PWR_FV2, 0);
+ break;
+
+ case RT5665_PWR_VREF3_BIT:
+ snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
+ RT5665_PWR_FV3, 0);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(15000, 20000);
+ switch (w->shift) {
+ case RT5665_PWR_VREF1_BIT:
+ snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
+ RT5665_PWR_FV1, RT5665_PWR_FV1);
+ break;
+
+ case RT5665_PWR_VREF2_BIT:
+ snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
+ RT5665_PWR_FV2, RT5665_PWR_FV2);
+ break;
+
+ case RT5665_PWR_VREF3_BIT:
+ snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
+ RT5665_PWR_FV3, RT5665_PWR_FV3);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+
+static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
+ SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
+ NULL, 0),
+ SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
+ RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
+ rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
+ rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
+ rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
+
+ /* ASRC */
+ SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
+ RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
+ RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
+ RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
+ RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
+ RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
+ RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
+ RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
+ RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
+ RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
+ RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
+ RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
+ RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
+ RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
+ RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
+
+ /* Input Side */
+ SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
+ 0, NULL, 0),
+
+ /* Input Lines */
+ SND_SOC_DAPM_INPUT("DMIC L1"),
+ SND_SOC_DAPM_INPUT("DMIC R1"),
+ SND_SOC_DAPM_INPUT("DMIC L2"),
+ SND_SOC_DAPM_INPUT("DMIC R2"),
+
+ SND_SOC_DAPM_INPUT("IN1P"),
+ SND_SOC_DAPM_INPUT("IN1N"),
+ SND_SOC_DAPM_INPUT("IN2P"),
+ SND_SOC_DAPM_INPUT("IN2N"),
+ SND_SOC_DAPM_INPUT("IN3P"),
+ SND_SOC_DAPM_INPUT("IN3N"),
+ SND_SOC_DAPM_INPUT("IN4P"),
+ SND_SOC_DAPM_INPUT("IN4N"),
+
+ SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
+ set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
+
+ /* Boost */
+ SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
+ 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
+ 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
+ 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
+ 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
+ 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST1_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST3_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST4_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
+ RT5665_PWR_CBJ_BIT, 0, NULL, 0),
+
+
+ /* Input Volume */
+ SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
+ 0, NULL, 0),
+
+ /* REC Mixer */
+ SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
+ ARRAY_SIZE(rt5665_rec1_l_mix)),
+ SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
+ ARRAY_SIZE(rt5665_rec1_r_mix)),
+ SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
+ ARRAY_SIZE(rt5665_rec2_l_mix)),
+ SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
+ ARRAY_SIZE(rt5665_rec2_r_mix)),
+ SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
+ RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
+ RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
+ RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
+
+ /* ADCs */
+ SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
+ RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
+ RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
+ RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
+ RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
+ RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
+ RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
+
+ /* ADC Mux */
+ SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_dmic_mux),
+ SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_dmic_mux),
+ SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_adc1l_mux),
+ SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_adc1r_mux),
+ SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_adc2l_mux),
+ SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_adc2r_mux),
+ SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_adcl_mux),
+ SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_adcr_mux),
+ SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_dd_l_mux),
+ SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto1_dd_r_mux),
+ SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_adc_l2_mux),
+ SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_adc_r2_mux),
+ SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_adc_l1_mux),
+ SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_adc_r1_mux),
+ SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_dmic_l_mux),
+ SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_dmic_r_mux),
+ SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_adc_l_mux),
+ SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_adc_r_mux),
+ SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_dd_l_mux),
+ SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_mono_dd_r_mux),
+ SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_dmic_mux),
+ SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_dmic_mux),
+ SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_adc1l_mux),
+ SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_adc1r_mux),
+ SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_adc2l_mux),
+ SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_adc2r_mux),
+ SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_adcl_mux),
+ SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_adcr_mux),
+ SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_dd_l_mux),
+ SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_sto2_dd_r_mux),
+ /* ADC Mixer */
+ SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
+ RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
+ ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
+ SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
+ RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
+ ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
+ SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
+ RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
+ ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
+ SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
+ RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
+ ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
+ SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
+ RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
+ ARRAY_SIZE(rt5665_mono_adc_l_mix)),
+ SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
+ RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
+ ARRAY_SIZE(rt5665_mono_adc_r_mix)),
+
+ /* ADC PGA */
+ SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Digital Interface */
+ SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
+ 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Digital Interface Select */
+ SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_adc1_mux),
+ SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_adc2_mux),
+ SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_adc3_mux),
+ SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_adc1_mux),
+ SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_adc2_mux),
+ SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_adc3_mux),
+ SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_adc4_mux),
+ SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm1_adc_mux),
+ SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm1_adc_mux),
+ SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm1_adc_mux),
+ SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm1_adc_mux),
+ SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm2_adc_mux),
+ SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm2_adc_mux),
+ SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm2_adc_mux),
+ SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_tdm2_adc_mux),
+ SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if2_1_adc_in_mux),
+ SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if2_2_adc_in_mux),
+ SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if3_adc_in_mux),
+ SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_01_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_01_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_23_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_23_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_45_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_45_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_67_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_1_67_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_01_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_01_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_23_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_23_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_45_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_45_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_67_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if1_2_67_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if2_1_dac_swap_mux),
+ SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if2_1_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if2_2_dac_swap_mux),
+ SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if2_2_adc_swap_mux),
+ SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if3_dac_swap_mux),
+ SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
+ &rt5665_if3_adc_swap_mux),
+
+ /* Audio Interface */
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
+ 1, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
+ 2, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
+ 3, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
+ 4, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
+ 5, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
+ 6, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
+ 7, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
+ 1, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
+ 2, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
+ 3, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
+ 4, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
+ 5, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
+ 6, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
+ 7, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
+ 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
+ 0, SND_SOC_NOPM, 0, 0),
+
+ /* Output Side */
+ /* DAC mixer before sound effect */
+ SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
+ rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
+ rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
+
+ /* DAC channel Mux */
+ SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
+ SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
+ SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
+ SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
+ SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
+ SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
+
+ SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
+ &rt5665_alg_dac_l1_mux),
+ SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
+ &rt5665_alg_dac_r1_mux),
+ SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
+ &rt5665_alg_dac_l2_mux),
+ SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
+ &rt5665_alg_dac_r2_mux),
+
+ /* DAC Mixer */
+ SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
+ RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
+ rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
+ rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
+ SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
+ rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
+ rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
+ SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
+ rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
+ SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
+ rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
+ SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
+ &rt5665_dig_dac_mixl_mux),
+ SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
+ &rt5665_dig_dac_mixr_mux),
+
+ /* DACs */
+ SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
+ RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
+ RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
+ RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
+ RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
+
+ /* OUT Mixer */
+ SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
+ 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
+ SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
+ 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
+ SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
+ 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
+
+ /* Output Volume */
+ SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
+ &monovol_switch),
+ SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
+ &outvol_l_switch),
+ SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
+ &outvol_r_switch),
+
+ /* MONO/HPO/LOUT */
+ SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
+ ARRAY_SIZE(rt5665_mono_mix)),
+ SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
+ ARRAY_SIZE(rt5665_lout_l_mix)),
+ SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
+ ARRAY_SIZE(rt5665_lout_r_mix)),
+ SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
+ 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
+ SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
+ SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
+ SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
+ RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
+ SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
+
+ SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
+ rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
+ &mono_switch),
+ SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
+ &hpo_switch),
+ SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
+ &lout_l_switch),
+ SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
+ &lout_r_switch),
+ SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
+ &pdm_l_switch),
+ SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
+ &pdm_r_switch),
+
+ /* PDM */
+ SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
+ RT5665_PWR_PDM1_BIT, 0, NULL, 0),
+ SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
+ 0, 1, &rt5665_pdm_l_mux),
+ SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
+ 0, 1, &rt5665_pdm_r_mux),
+
+ /* CLK DET */
+ SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
+ 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
+ 0, NULL, 0),
+
+ /* Output Lines */
+ SND_SOC_DAPM_OUTPUT("HPOL"),
+ SND_SOC_DAPM_OUTPUT("HPOR"),
+ SND_SOC_DAPM_OUTPUT("LOUTL"),
+ SND_SOC_DAPM_OUTPUT("LOUTR"),
+ SND_SOC_DAPM_OUTPUT("MONOOUT"),
+ SND_SOC_DAPM_OUTPUT("PDML"),
+ SND_SOC_DAPM_OUTPUT("PDMR"),
+};
+
+static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
+ /*PLL*/
+ {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
+ {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
+
+ /*ASRC*/
+ {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
+ {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
+ {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
+ {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
+ {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
+ {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
+ {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
+
+ /*Vref*/
+ {"Mic Det Power", NULL, "Vref2"},
+ {"MICBIAS1", NULL, "Vref1"},
+ {"MICBIAS1", NULL, "Vref2"},
+ {"MICBIAS2", NULL, "Vref1"},
+ {"MICBIAS2", NULL, "Vref2"},
+ {"MICBIAS3", NULL, "Vref1"},
+ {"MICBIAS3", NULL, "Vref2"},
+
+ {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
+ {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
+ {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
+ {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
+ {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
+ {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
+
+ {"I2S1_1", NULL, "I2S1 ASRC"},
+ {"I2S1_2", NULL, "I2S1 ASRC"},
+ {"I2S2_1", NULL, "I2S2 ASRC"},
+ {"I2S2_2", NULL, "I2S2 ASRC"},
+ {"I2S3", NULL, "I2S3 ASRC"},
+
+ {"CLKDET SYS", NULL, "CLKDET"},
+ {"CLKDET HP", NULL, "CLKDET"},
+ {"CLKDET MONO", NULL, "CLKDET"},
+ {"CLKDET LOUT", NULL, "CLKDET"},
+
+ {"IN1P", NULL, "LDO2"},
+ {"IN2P", NULL, "LDO2"},
+ {"IN3P", NULL, "LDO2"},
+ {"IN4P", NULL, "LDO2"},
+
+ {"DMIC1", NULL, "DMIC L1"},
+ {"DMIC1", NULL, "DMIC R1"},
+ {"DMIC2", NULL, "DMIC L2"},
+ {"DMIC2", NULL, "DMIC R2"},
+
+ {"BST1", NULL, "IN1P"},
+ {"BST1", NULL, "IN1N"},
+ {"BST1", NULL, "BST1 Power"},
+ {"BST1", NULL, "BST1P Power"},
+ {"BST2", NULL, "IN2P"},
+ {"BST2", NULL, "IN2N"},
+ {"BST2", NULL, "BST2 Power"},
+ {"BST2", NULL, "BST2P Power"},
+ {"BST3", NULL, "IN3P"},
+ {"BST3", NULL, "IN3N"},
+ {"BST3", NULL, "BST3 Power"},
+ {"BST3", NULL, "BST3P Power"},
+ {"BST4", NULL, "IN4P"},
+ {"BST4", NULL, "IN4N"},
+ {"BST4", NULL, "BST4 Power"},
+ {"BST4", NULL, "BST4P Power"},
+ {"BST1 CBJ", NULL, "IN1P"},
+ {"BST1 CBJ", NULL, "IN1N"},
+ {"BST1 CBJ", NULL, "CBJ Power"},
+ {"CBJ Power", NULL, "Vref2"},
+
+ {"INL VOL", NULL, "IN3P"},
+ {"INR VOL", NULL, "IN3N"},
+
+ {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
+ {"RECMIX1L", "INL Switch", "INL VOL"},
+ {"RECMIX1L", "INR Switch", "INR VOL"},
+ {"RECMIX1L", "BST4 Switch", "BST4"},
+ {"RECMIX1L", "BST3 Switch", "BST3"},
+ {"RECMIX1L", "BST2 Switch", "BST2"},
+ {"RECMIX1L", "BST1 Switch", "BST1"},
+ {"RECMIX1L", NULL, "RECMIX1L Power"},
+
+ {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
+ {"RECMIX1R", "INR Switch", "INR VOL"},
+ {"RECMIX1R", "BST4 Switch", "BST4"},
+ {"RECMIX1R", "BST3 Switch", "BST3"},
+ {"RECMIX1R", "BST2 Switch", "BST2"},
+ {"RECMIX1R", "BST1 Switch", "BST1"},
+ {"RECMIX1R", NULL, "RECMIX1R Power"},
+
+ {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
+ {"RECMIX2L", "INL Switch", "INL VOL"},
+ {"RECMIX2L", "INR Switch", "INR VOL"},
+ {"RECMIX2L", "BST4 Switch", "BST4"},
+ {"RECMIX2L", "BST3 Switch", "BST3"},
+ {"RECMIX2L", "BST2 Switch", "BST2"},
+ {"RECMIX2L", "BST1 Switch", "BST1"},
+ {"RECMIX2L", NULL, "RECMIX2L Power"},
+
+ {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
+ {"RECMIX2R", "INL Switch", "INL VOL"},
+ {"RECMIX2R", "INR Switch", "INR VOL"},
+ {"RECMIX2R", "BST4 Switch", "BST4"},
+ {"RECMIX2R", "BST3 Switch", "BST3"},
+ {"RECMIX2R", "BST2 Switch", "BST2"},
+ {"RECMIX2R", "BST1 Switch", "BST1"},
+ {"RECMIX2R", NULL, "RECMIX2R Power"},
+
+ {"ADC1 L", NULL, "RECMIX1L"},
+ {"ADC1 L", NULL, "ADC1 L Power"},
+ {"ADC1 L", NULL, "ADC1 clock"},
+ {"ADC1 R", NULL, "RECMIX1R"},
+ {"ADC1 R", NULL, "ADC1 R Power"},
+ {"ADC1 R", NULL, "ADC1 clock"},
+
+ {"ADC2 L", NULL, "RECMIX2L"},
+ {"ADC2 L", NULL, "ADC2 L Power"},
+ {"ADC2 L", NULL, "ADC2 clock"},
+ {"ADC2 R", NULL, "RECMIX2R"},
+ {"ADC2 R", NULL, "ADC2 R Power"},
+ {"ADC2 R", NULL, "ADC2 clock"},
+
+ {"DMIC L1", NULL, "DMIC CLK"},
+ {"DMIC L1", NULL, "DMIC1 Power"},
+ {"DMIC R1", NULL, "DMIC CLK"},
+ {"DMIC R1", NULL, "DMIC1 Power"},
+ {"DMIC L2", NULL, "DMIC CLK"},
+ {"DMIC L2", NULL, "DMIC2 Power"},
+ {"DMIC R2", NULL, "DMIC CLK"},
+ {"DMIC R2", NULL, "DMIC2 Power"},
+
+ {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
+ {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
+
+ {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
+ {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
+
+ {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
+ {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
+
+ {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
+ {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
+
+ {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
+ {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
+
+ {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
+ {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
+
+ {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
+ {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
+ {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
+ {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
+ {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
+ {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
+ {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
+ {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
+
+ {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
+ {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
+
+ {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
+ {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
+
+ {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
+ {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
+ {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
+ {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
+
+ {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
+ {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
+ {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
+ {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
+
+ {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
+ {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
+ {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
+ {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
+
+ {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
+ {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
+ {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
+ {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
+
+ {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
+ {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
+
+ {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
+ {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
+
+ {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
+ {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
+ {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
+ {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
+
+ {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
+ {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
+ {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
+ {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
+
+ {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
+ {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
+ {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
+ {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
+ {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
+ {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
+
+ {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
+ {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
+
+ {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
+ {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
+
+ {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
+ {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
+ {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
+ {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
+
+ {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
+ {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
+ {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
+ {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
+
+ {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
+ {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
+ {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
+
+ {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
+ {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
+ {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
+
+ {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
+ {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
+ {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
+
+ {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
+ {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
+ {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
+
+ {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
+ {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
+ {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
+
+ {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
+ {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
+ {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
+
+ {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
+ {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
+ {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
+ {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
+ {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
+ {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
+
+ {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
+ {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
+ {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
+ {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
+ {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
+ {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
+ {"IF1_1_ADC4", NULL, "DAC1 MIX"},
+
+ {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
+ {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
+ {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
+ {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
+ {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
+ {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
+ {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
+ {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
+
+ {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
+ {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
+ {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
+ {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
+ {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
+ {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
+ {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
+
+ {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
+ {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
+ {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
+ {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
+ {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
+ {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
+ {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
+
+ {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
+ {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
+ {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
+ {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
+ {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
+ {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
+ {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
+
+ {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
+ {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
+ {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
+ {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
+ {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
+ {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
+ {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
+ {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
+ {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
+ {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
+
+
+ {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
+
+ {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
+
+ {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
+
+ {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
+ {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
+ {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
+ {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
+ {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
+
+ {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
+ {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
+ {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
+ {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
+ {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
+ {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
+ {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
+ {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
+ {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
+ {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
+ {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
+ {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
+ {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
+ {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
+ {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
+ {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
+ {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
+ {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
+ {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
+ {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
+ {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
+ {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
+ {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
+ {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
+ {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
+ {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
+ {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
+ {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
+ {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
+ {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
+ {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
+ {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
+
+ {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
+ {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
+ {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
+ {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
+ {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
+ {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
+ {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
+ {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
+ {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
+ {"IF2_1 ADC", NULL, "I2S2_1"},
+
+ {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
+ {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
+ {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
+ {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
+ {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
+ {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
+ {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
+ {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
+ {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
+ {"IF2_2 ADC", NULL, "I2S2_2"},
+
+ {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
+ {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
+ {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
+ {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
+ {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
+ {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
+ {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
+ {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
+ {"IF3 ADC", NULL, "IF3 ADC Mux"},
+ {"IF3 ADC", NULL, "I2S3"},
+
+ {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
+ {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
+ {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
+ {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
+ {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
+ {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
+ {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
+ {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
+ {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
+ {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
+ {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
+ {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
+ {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
+ {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
+ {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
+ {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
+ {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
+ {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
+ {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
+ {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
+ {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
+ {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
+ {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
+ {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
+ {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
+ {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
+ {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
+ {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
+ {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
+ {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
+ {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
+
+ {"IF1 DAC1", NULL, "AIF1RX"},
+ {"IF1 DAC2", NULL, "AIF1RX"},
+ {"IF1 DAC3", NULL, "AIF1RX"},
+ {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
+ {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
+ {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
+ {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
+ {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
+ {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
+ {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
+ {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
+ {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
+ {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
+ {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
+ {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
+ {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
+ {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
+ {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
+
+ {"IF1 DAC1", NULL, "I2S1_1"},
+ {"IF1 DAC2", NULL, "I2S1_1"},
+ {"IF1 DAC3", NULL, "I2S1_1"},
+ {"IF2_1 DAC", NULL, "I2S2_1"},
+ {"IF2_2 DAC", NULL, "I2S2_2"},
+ {"IF3 DAC", NULL, "I2S3"},
+
+ {"IF1 DAC1 L", NULL, "IF1 DAC1"},
+ {"IF1 DAC1 R", NULL, "IF1 DAC1"},
+ {"IF1 DAC2 L", NULL, "IF1 DAC2"},
+ {"IF1 DAC2 R", NULL, "IF1 DAC2"},
+ {"IF1 DAC3 L", NULL, "IF1 DAC3"},
+ {"IF1 DAC3 R", NULL, "IF1 DAC3"},
+ {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
+ {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
+ {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
+ {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
+ {"IF3 DAC L", NULL, "IF3 DAC"},
+ {"IF3 DAC R", NULL, "IF3 DAC"},
+
+ {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
+ {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
+ {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
+ {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
+ {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
+
+ {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
+ {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
+ {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
+ {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
+ {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
+
+ {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
+ {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
+ {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
+ {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
+
+ {"DAC1 MIX", NULL, "DAC1 MIXL"},
+ {"DAC1 MIX", NULL, "DAC1 MIXR"},
+
+ {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
+ {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
+ {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
+ {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
+ {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
+ {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
+
+ {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
+ {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
+ {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
+ {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
+ {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
+ {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
+
+ {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
+ {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
+ {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
+ {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
+ {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
+ {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
+
+ {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
+ {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
+ {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
+ {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
+ {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
+ {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
+
+ {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
+ {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
+ {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+ {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
+
+ {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
+ {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
+ {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
+ {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+
+ {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
+ {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+ {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
+
+ {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
+ {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+ {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
+
+ {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
+ {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
+ {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+ {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
+ {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
+ {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
+ {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
+ {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+
+ {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
+ {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
+ {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
+ {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
+ {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
+ {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
+
+ {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
+ {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
+ {"DAC L1 Source", "DMIC1", "DMIC L1"},
+ {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
+ {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
+ {"DAC R1 Source", "DMIC1", "DMIC R1"},
+
+ {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
+ {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
+ {"DAC L2 Source", NULL, "DAC L2 Power"},
+ {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
+ {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
+ {"DAC R2 Source", NULL, "DAC R2 Power"},
+
+ {"DAC L1", NULL, "DAC L1 Source"},
+ {"DAC R1", NULL, "DAC R1 Source"},
+ {"DAC L2", NULL, "DAC L2 Source"},
+ {"DAC R2", NULL, "DAC R2 Source"},
+
+ {"DAC L1", NULL, "DAC 1 Clock"},
+ {"DAC R1", NULL, "DAC 1 Clock"},
+ {"DAC L2", NULL, "DAC 2 Clock"},
+ {"DAC R2", NULL, "DAC 2 Clock"},
+
+ {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
+ {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
+ {"MONOVOL MIX", "BST1 Switch", "BST1"},
+ {"MONOVOL MIX", "BST2 Switch", "BST2"},
+ {"MONOVOL MIX", "BST3 Switch", "BST3"},
+
+ {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
+ {"OUT MIXL", "INL Switch", "INL VOL"},
+ {"OUT MIXL", "BST1 Switch", "BST1"},
+ {"OUT MIXL", "BST2 Switch", "BST2"},
+ {"OUT MIXL", "BST3 Switch", "BST3"},
+ {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
+ {"OUT MIXR", "INR Switch", "INR VOL"},
+ {"OUT MIXR", "BST2 Switch", "BST2"},
+ {"OUT MIXR", "BST3 Switch", "BST3"},
+ {"OUT MIXR", "BST4 Switch", "BST4"},
+
+ {"MONOVOL", "Switch", "MONOVOL MIX"},
+ {"Mono MIX", "DAC L2 Switch", "DAC L2"},
+ {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
+ {"Mono Amp", NULL, "Mono MIX"},
+ {"Mono Amp", NULL, "Vref2"},
+ {"Mono Amp", NULL, "CLKDET SYS"},
+ {"Mono Amp", NULL, "CLKDET MONO"},
+ {"Mono Playback", "Switch", "Mono Amp"},
+ {"MONOOUT", NULL, "Mono Playback"},
+
+ {"HP Amp", NULL, "DAC L1"},
+ {"HP Amp", NULL, "DAC R1"},
+ {"HP Amp", NULL, "Charge Pump"},
+ {"HP Amp", NULL, "CLKDET SYS"},
+ {"HP Amp", NULL, "CLKDET HP"},
+ {"HP Amp", NULL, "CBJ Power"},
+ {"HP Amp", NULL, "Vref2"},
+ {"HPO Playback", "Switch", "HP Amp"},
+ {"HPOL", NULL, "HPO Playback"},
+ {"HPOR", NULL, "HPO Playback"},
+
+ {"OUTVOL L", "Switch", "OUT MIXL"},
+ {"OUTVOL R", "Switch", "OUT MIXR"},
+ {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
+ {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
+ {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
+ {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
+ {"LOUT Amp", NULL, "LOUT L MIX"},
+ {"LOUT Amp", NULL, "LOUT R MIX"},
+ {"LOUT Amp", NULL, "Vref1"},
+ {"LOUT Amp", NULL, "Vref2"},
+ {"LOUT Amp", NULL, "CLKDET SYS"},
+ {"LOUT Amp", NULL, "CLKDET LOUT"},
+ {"LOUT L Playback", "Switch", "LOUT Amp"},
+ {"LOUT R Playback", "Switch", "LOUT Amp"},
+ {"LOUTL", NULL, "LOUT L Playback"},
+ {"LOUTR", NULL, "LOUT R Playback"},
+
+ {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
+ {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
+ {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
+ {"PDM L Mux", NULL, "PDM Power"},
+ {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
+ {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
+ {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
+ {"PDM R Mux", NULL, "PDM Power"},
+ {"PDM L Playback", "Switch", "PDM L Mux"},
+ {"PDM R Playback", "Switch", "PDM R Mux"},
+ {"PDML", NULL, "PDM L Playback"},
+ {"PDMR", NULL, "PDM R Playback"},
+};
+
+static int rt5665_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+ unsigned int val_len = 0, val_clk, mask_clk, val_bits = 0x0100;
+ int pre_div, frame_size;
+
+ rt5665->lrck[dai->id] = params_rate(params);
+ pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
+ if (pre_div < 0) {
+ dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
+ rt5665->lrck[dai->id], dai->id);
+ return -EINVAL;
+ }
+ frame_size = snd_soc_params_to_frame_size(params);
+ if (frame_size < 0) {
+ dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
+ return -EINVAL;
+ }
+
+ dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
+ rt5665->lrck[dai->id], pre_div, dai->id);
+
+ switch (params_width(params)) {
+ case 16:
+ val_bits = 0x0100;
+ break;
+ case 20:
+ val_len |= RT5665_I2S_DL_20;
+ val_bits = 0x1300;
+ break;
+ case 24:
+ val_len |= RT5665_I2S_DL_24;
+ val_bits = 0x2500;
+ break;
+ case 8:
+ val_len |= RT5665_I2S_DL_8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (dai->id) {
+ case RT5665_AIF1_1:
+ case RT5665_AIF1_2:
+ mask_clk = RT5665_I2S_PD1_MASK;
+ val_clk = pre_div << RT5665_I2S_PD1_SFT;
+ snd_soc_update_bits(codec, RT5665_I2S1_SDP,
+ RT5665_I2S_DL_MASK, val_len);
+ break;
+ case RT5665_AIF2_1:
+ case RT5665_AIF2_2:
+ mask_clk = RT5665_I2S_PD2_MASK;
+ val_clk = pre_div << RT5665_I2S_PD2_SFT;
+ snd_soc_update_bits(codec, RT5665_I2S2_SDP,
+ RT5665_I2S_DL_MASK, val_len);
+ break;
+ case RT5665_AIF3:
+ mask_clk = RT5665_I2S_PD3_MASK;
+ val_clk = pre_div << RT5665_I2S_PD3_SFT;
+ snd_soc_update_bits(codec, RT5665_I2S3_SDP,
+ RT5665_I2S_DL_MASK, val_len);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
+ return -EINVAL;
+ }
+
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1, mask_clk, val_clk);
+ snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
+
+ switch (rt5665->lrck[dai->id]) {
+ case 192000:
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
+ RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
+ RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
+ break;
+ case 96000:
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
+ RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
+ RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
+ break;
+ default:
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
+ RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
+ RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
+ break;
+ }
+
+ return 0;
+}
+
+static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+ unsigned int reg_val = 0;
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBM_CFM:
+ rt5665->master[dai->id] = 1;
+ break;
+ case SND_SOC_DAIFMT_CBS_CFS:
+ reg_val |= RT5665_I2S_MS_S;
+ rt5665->master[dai->id] = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ reg_val |= RT5665_I2S_BP_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ reg_val |= RT5665_I2S_DF_LEFT;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ reg_val |= RT5665_I2S_DF_PCM_A;
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+ reg_val |= RT5665_I2S_DF_PCM_B;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (dai->id) {
+ case RT5665_AIF1_1:
+ case RT5665_AIF1_2:
+ snd_soc_update_bits(codec, RT5665_I2S1_SDP,
+ RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
+ RT5665_I2S_DF_MASK, reg_val);
+ break;
+ case RT5665_AIF2_1:
+ case RT5665_AIF2_2:
+ snd_soc_update_bits(codec, RT5665_I2S2_SDP,
+ RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
+ RT5665_I2S_DF_MASK, reg_val);
+ break;
+ case RT5665_AIF3:
+ snd_soc_update_bits(codec, RT5665_I2S3_SDP,
+ RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
+ RT5665_I2S_DF_MASK, reg_val);
+ break;
+ default:
+ dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int rt5665_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+ unsigned int reg_val = 0;
+
+ if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
+ return 0;
+
+ switch (clk_id) {
+ case RT5665_SCLK_S_MCLK:
+ reg_val |= RT5665_SCLK_SRC_MCLK;
+ break;
+ case RT5665_SCLK_S_PLL1:
+ reg_val |= RT5665_SCLK_SRC_PLL1;
+ break;
+ case RT5665_SCLK_S_RCCLK:
+ reg_val |= RT5665_SCLK_SRC_RCCLK;
+ break;
+ default:
+ dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
+ return -EINVAL;
+ }
+ snd_soc_update_bits(codec, RT5665_GLB_CLK,
+ RT5665_SCLK_SRC_MASK, reg_val);
+ rt5665->sysclk = freq;
+ rt5665->sysclk_src = clk_id;
+
+ dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
+
+ return 0;
+}
+
+static int rt5665_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int Source,
+ unsigned int freq_in, unsigned int freq_out)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+ struct rl6231_pll_code pll_code;
+ int ret;
+
+ if (Source == rt5665->pll_src && freq_in == rt5665->pll_in &&
+ freq_out == rt5665->pll_out)
+ return 0;
+
+ if (!freq_in || !freq_out) {
+ dev_dbg(codec->dev, "PLL disabled\n");
+
+ rt5665->pll_in = 0;
+ rt5665->pll_out = 0;
+ snd_soc_update_bits(codec, RT5665_GLB_CLK,
+ RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
+ return 0;
+ }
+
+ switch (Source) {
+ case RT5665_PLL1_S_MCLK:
+ snd_soc_update_bits(codec, RT5665_GLB_CLK,
+ RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
+ break;
+ case RT5665_PLL1_S_BCLK1:
+ snd_soc_update_bits(codec, RT5665_GLB_CLK,
+ RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
+ break;
+ case RT5665_PLL1_S_BCLK2:
+ snd_soc_update_bits(codec, RT5665_GLB_CLK,
+ RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
+ break;
+ case RT5665_PLL1_S_BCLK3:
+ snd_soc_update_bits(codec, RT5665_GLB_CLK,
+ RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
+ break;
+ default:
+ dev_err(codec->dev, "Unknown PLL Source %d\n", Source);
+ return -EINVAL;
+ }
+
+ ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
+ if (ret < 0) {
+ dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
+ return ret;
+ }
+
+ dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
+ pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
+ pll_code.n_code, pll_code.k_code);
+
+ snd_soc_write(codec, RT5665_PLL_CTRL_1,
+ pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
+ snd_soc_write(codec, RT5665_PLL_CTRL_2,
+ (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
+ pll_code.m_bp << RT5665_PLL_M_BP_SFT);
+
+ rt5665->pll_in = freq_in;
+ rt5665->pll_out = freq_out;
+ rt5665->pll_src = Source;
+
+ return 0;
+}
+
+static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
+ unsigned int rx_mask, int slots, int slot_width)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ unsigned int val = 0;
+
+ if (rx_mask || tx_mask)
+ val |= RT5665_I2S1_MODE_TDM;
+
+ switch (slots) {
+ case 4:
+ val |= RT5665_TDM_IN_CH_4;
+ val |= RT5665_TDM_OUT_CH_4;
+ break;
+ case 6:
+ val |= RT5665_TDM_IN_CH_6;
+ val |= RT5665_TDM_OUT_CH_6;
+ break;
+ case 8:
+ val |= RT5665_TDM_IN_CH_8;
+ val |= RT5665_TDM_OUT_CH_8;
+ break;
+ case 2:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (slot_width) {
+ case 20:
+ val |= RT5665_TDM_IN_LEN_20;
+ val |= RT5665_TDM_OUT_LEN_20;
+ break;
+ case 24:
+ val |= RT5665_TDM_IN_LEN_24;
+ val |= RT5665_TDM_OUT_LEN_24;
+ break;
+ case 32:
+ val |= RT5665_TDM_IN_LEN_32;
+ val |= RT5665_TDM_OUT_LEN_32;
+ break;
+ case 16:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
+ RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
+ RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
+ RT5665_TDM_OUT_LEN_MASK, val);
+
+ return 0;
+}
+
+static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
+
+ rt5665->bclk[dai->id] = ratio;
+
+ if (ratio == 64) {
+ switch (dai->id) {
+ case RT5665_AIF2_1:
+ case RT5665_AIF2_2:
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
+ RT5665_I2S_BCLK_MS2_MASK,
+ RT5665_I2S_BCLK_MS2_64);
+ break;
+ case RT5665_AIF3:
+ snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
+ RT5665_I2S_BCLK_MS3_MASK,
+ RT5665_I2S_BCLK_MS3_64);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int rt5665_set_bias_level(struct snd_soc_codec *codec,
+ enum snd_soc_bias_level level)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ switch (level) {
+ case SND_SOC_BIAS_PREPARE:
+ regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
+ RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
+ break;
+
+ case SND_SOC_BIAS_STANDBY:
+ regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
+ RT5665_PWR_LDO, RT5665_PWR_LDO);
+ regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
+ RT5665_PWR_MB, RT5665_PWR_MB);
+ regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
+ RT5665_DIG_GATE_CTRL, 0);
+ break;
+ case SND_SOC_BIAS_OFF:
+ regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
+ RT5665_PWR_LDO, 0);
+ regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
+ RT5665_PWR_MB, 0);
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int rt5665_probe(struct snd_soc_codec *codec)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ rt5665->codec = codec;
+
+ schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
+
+ return 0;
+}
+
+static int rt5665_remove(struct snd_soc_codec *codec)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int rt5665_suspend(struct snd_soc_codec *codec)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ regcache_cache_only(rt5665->regmap, true);
+ regcache_mark_dirty(rt5665->regmap);
+ return 0;
+}
+
+static int rt5665_resume(struct snd_soc_codec *codec)
+{
+ struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
+
+ regcache_cache_only(rt5665->regmap, false);
+ regcache_sync(rt5665->regmap);
+
+ return 0;
+}
+#else
+#define rt5665_suspend NULL
+#define rt5665_resume NULL
+#endif
+
+#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
+#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
+
+static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
+ .hw_params = rt5665_hw_params,
+ .set_fmt = rt5665_set_dai_fmt,
+ .set_sysclk = rt5665_set_dai_sysclk,
+ .set_tdm_slot = rt5665_set_tdm_slot,
+ .set_pll = rt5665_set_dai_pll,
+ .set_bclk_ratio = rt5665_set_bclk_ratio,
+};
+
+static struct snd_soc_dai_driver rt5665_dai[] = {
+ {
+ .name = "rt5665-aif1_1",
+ .id = RT5665_AIF1_1,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF1_1 Capture",
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .ops = &rt5665_aif_dai_ops,
+ },
+ {
+ .name = "rt5665-aif1_2",
+ .id = RT5665_AIF1_2,
+ .capture = {
+ .stream_name = "AIF1_2 Capture",
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .ops = &rt5665_aif_dai_ops,
+ },
+ {
+ .name = "rt5665-aif2_1",
+ .id = RT5665_AIF2_1,
+ .playback = {
+ .stream_name = "AIF2_1 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF2_1 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .ops = &rt5665_aif_dai_ops,
+ },
+ {
+ .name = "rt5665-aif2_2",
+ .id = RT5665_AIF2_2,
+ .playback = {
+ .stream_name = "AIF2_2 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF2_2 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .ops = &rt5665_aif_dai_ops,
+ },
+ {
+ .name = "rt5665-aif3",
+ .id = RT5665_AIF3,
+ .playback = {
+ .stream_name = "AIF3 Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .capture = {
+ .stream_name = "AIF3 Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = RT5665_STEREO_RATES,
+ .formats = RT5665_FORMATS,
+ },
+ .ops = &rt5665_aif_dai_ops,
+ },
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
+ .probe = rt5665_probe,
+ .remove = rt5665_remove,
+ .suspend = rt5665_suspend,
+ .resume = rt5665_resume,
+ .set_bias_level = rt5665_set_bias_level,
+ .idle_bias_off = true,
+ .component_driver = {
+ .controls = rt5665_snd_controls,
+ .num_controls = ARRAY_SIZE(rt5665_snd_controls),
+ .dapm_widgets = rt5665_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
+ .dapm_routes = rt5665_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
+ }
+};
+
+
+static const struct regmap_config rt5665_regmap = {
+ .reg_bits = 16,
+ .val_bits = 16,
+ .max_register = 0x0400,
+ .volatile_reg = rt5665_volatile_register,
+ .readable_reg = rt5665_readable_register,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = rt5665_reg,
+ .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
+ .use_single_rw = true,
+};
+
+static const struct i2c_device_id rt5665_i2c_id[] = {
+ {"rt5665", 0},
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
+
+static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
+{
+ rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
+ "realtek,in1-differential");
+ rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
+ "realtek,in2-differential");
+ rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
+ "realtek,in3-differential");
+ rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
+ "realtek,in4-differential");
+
+ of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
+ &rt5665->pdata.dmic1_data_pin);
+ of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
+ &rt5665->pdata.dmic2_data_pin);
+ of_property_read_u32(dev->of_node, "realtek,jd-src",
+ &rt5665->pdata.jd_src);
+
+ rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
+ "realtek,ldo1-en-gpios", 0);
+
+ return 0;
+}
+
+static void rt5665_calibrate(struct rt5665_priv *rt5665)
+{
+ int value, count;
+
+ mutex_lock(&rt5665->calibrate_mutex);
+
+ regcache_cache_bypass(rt5665->regmap, true);
+
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+ regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
+ regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
+ regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
+ regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
+ regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
+ regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
+ regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
+ regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
+ regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
+ regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
+ regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
+ regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
+ regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
+ regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
+ regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
+ usleep_range(15000, 20000);
+ regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
+ regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
+
+ regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
+ count = 0;
+ while (true) {
+ regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
+ if (value & 0x8000)
+ usleep_range(10000, 10005);
+ else
+ break;
+
+ if (count > 60) {
+ pr_err("HP Calibration Failure\n");
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+ regcache_cache_bypass(rt5665->regmap, false);
+ return;
+ }
+
+ count++;
+ }
+
+ regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
+ count = 0;
+ while (true) {
+ regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
+ if (value & 0x8000)
+ usleep_range(10000, 10005);
+ else
+ break;
+
+ if (count > 60) {
+ pr_err("MONO Calibration Failure\n");
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+ regcache_cache_bypass(rt5665->regmap, false);
+ return;
+ }
+
+ count++;
+ }
+
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+ regcache_cache_bypass(rt5665->regmap, false);
+
+ regcache_mark_dirty(rt5665->regmap);
+ regcache_sync(rt5665->regmap);
+
+ regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
+ regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
+
+ mutex_unlock(&rt5665->calibrate_mutex);
+}
+
+static void rt5665_calibrate_handler(struct work_struct *work)
+{
+ struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
+ calibrate_work.work);
+
+ while (!rt5665->codec->component.card->instantiated) {
+ pr_debug("%s\n", __func__);
+ usleep_range(10000, 15000);
+ }
+
+ rt5665_calibrate(rt5665);
+}
+
+static int rt5665_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
+ struct rt5665_priv *rt5665;
+ int i, ret;
+ unsigned int val;
+
+ rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
+ GFP_KERNEL);
+
+ if (rt5665 == NULL)
+ return -ENOMEM;
+
+ i2c_set_clientdata(i2c, rt5665);
+
+ if (pdata)
+ rt5665->pdata = *pdata;
+ else
+ rt5665_parse_dt(rt5665, &i2c->dev);
+
+ for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
+ rt5665->supplies[i].supply = rt5665_supply_names[i];
+
+ ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
+ rt5665->supplies);
+ if (ret != 0) {
+ dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
+ rt5665->supplies);
+ if (ret != 0) {
+ dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
+ return ret;
+ }
+
+ if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
+ if (devm_gpio_request(&i2c->dev, rt5665->pdata.ldo1_en,
+ "rt5665"))
+ dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
+ else if (gpio_direction_output(rt5665->pdata.ldo1_en, 1))
+ dev_err(&i2c->dev, "Fail gpio_direction gpio_ldo\n");
+ }
+
+ /* Sleep for 300 ms miniumum */
+ usleep_range(300000, 350000);
+
+ rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
+ if (IS_ERR(rt5665->regmap)) {
+ ret = PTR_ERR(rt5665->regmap);
+ dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
+ ret);
+ return ret;
+ }
+
+ regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
+ if (val != DEVICE_ID) {
+ dev_err(&i2c->dev,
+ "Device with ID register %x is not rt5665\n", val);
+ return -ENODEV;
+ }
+
+ regmap_read(rt5665->regmap, RT5665_RESET, &val);
+ switch (val) {
+ case 0x0:
+ rt5665->id = CODEC_5666;
+ break;
+ case 0x6:
+ rt5665->id = CODEC_5668;
+ break;
+ case 0x3:
+ default:
+ rt5665->id = CODEC_5665;
+ break;
+ }
+
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+
+ /* line in diff mode*/
+ if (rt5665->pdata.in1_diff)
+ regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
+ RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
+ if (rt5665->pdata.in2_diff)
+ regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
+ RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
+ if (rt5665->pdata.in3_diff)
+ regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
+ RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
+ if (rt5665->pdata.in4_diff)
+ regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
+ RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
+
+ /* DMIC pin*/
+ if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
+ rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
+ RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
+ RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
+ switch (rt5665->pdata.dmic1_data_pin) {
+ case RT5665_DMIC1_DATA_IN2N:
+ regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
+ break;
+
+ case RT5665_DMIC1_DATA_GPIO4:
+ regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
+ RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
+ break;
+
+ default:
+ dev_dbg(&i2c->dev, "no DMIC1\n");
+ break;
+ }
+
+ switch (rt5665->pdata.dmic2_data_pin) {
+ case RT5665_DMIC2_DATA_IN2P:
+ regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
+ break;
+
+ case RT5665_DMIC2_DATA_GPIO5:
+ regmap_update_bits(rt5665->regmap,
+ RT5665_DMIC_CTRL_1,
+ RT5665_DMIC_2_DP_MASK,
+ RT5665_DMIC_2_DP_GPIO5);
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
+ RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
+ break;
+
+ default:
+ dev_dbg(&i2c->dev, "no DMIC2\n");
+ break;
+
+ }
+ }
+
+ regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
+ regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
+ 0xf000 | RT5665_VREF_POW_MASK, 0xd000 | RT5665_VREF_POW_REG);
+ /* Work around for pow_pump */
+ regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
+ RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
+
+ regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
+ RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
+
+ /* Set GPIO4,8 as input for combo jack */
+ if (rt5665->id == CODEC_5666) {
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
+ RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
+ regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
+ RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
+ }
+
+ /* Enhance performance*/
+ regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
+ RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
+ RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_09);
+
+ INIT_DELAYED_WORK(&rt5665->jack_detect_work,
+ rt5665_jack_detect_handler);
+ INIT_DELAYED_WORK(&rt5665->calibrate_work,
+ rt5665_calibrate_handler);
+ INIT_DELAYED_WORK(&rt5665->jd_check_work,
+ rt5665_jd_check_handler);
+
+ mutex_init(&rt5665->calibrate_mutex);
+
+ if (i2c->irq) {
+ ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
+ rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
+ | IRQF_ONESHOT, "rt5665", rt5665);
+ if (ret)
+ dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
+
+ }
+
+ return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
+ rt5665_dai, ARRAY_SIZE(rt5665_dai));
+}
+
+static int rt5665_i2c_remove(struct i2c_client *i2c)
+{
+ snd_soc_unregister_codec(&i2c->dev);
+
+ return 0;
+}
+
+static void rt5665_i2c_shutdown(struct i2c_client *client)
+{
+ struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
+
+ regmap_write(rt5665->regmap, RT5665_RESET, 0);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id rt5665_of_match[] = {
+ {.compatible = "realtek,rt5665"},
+ {.compatible = "realtek,rt5666"},
+ {.compatible = "realtek,rt5668"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, rt5665_of_match);
+#endif
+
+#ifdef CONFIG_ACPI
+static struct acpi_device_id rt5665_acpi_match[] = {
+ {"10EC5665", 0,},
+ {"10EC5666", 0,},
+ {"10EC5668", 0,},
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
+#endif
+
+struct i2c_driver rt5665_i2c_driver = {
+ .driver = {
+ .name = "rt5665",
+ .of_match_table = of_match_ptr(rt5665_of_match),
+ .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
+ },
+ .probe = rt5665_i2c_probe,
+ .remove = rt5665_i2c_remove,
+ .shutdown = rt5665_i2c_shutdown,
+ .id_table = rt5665_i2c_id,
+};
+module_i2c_driver(rt5665_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC RT5665 driver");
+MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5665.h b/sound/soc/codecs/rt5665.h
new file mode 100644
index 000000000000..12f7080a0d3c
--- /dev/null
+++ b/sound/soc/codecs/rt5665.h
@@ -0,0 +1,1990 @@
+/*
+ * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
+ *
+ * Copyright 2016 Realtek Microelectronics
+ * Author: Bard Liao <bardliao@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT5665_H__
+#define __RT5665_H__
+
+#include <sound/rt5665.h>
+
+#define DEVICE_ID 0x6451
+
+/* Info */
+#define RT5665_RESET 0x0000
+#define RT5665_VENDOR_ID 0x00fd
+#define RT5665_VENDOR_ID_1 0x00fe
+#define RT5665_DEVICE_ID 0x00ff
+/* I/O - Output */
+#define RT5665_LOUT 0x0001
+#define RT5665_HP_CTRL_1 0x0002
+#define RT5665_HP_CTRL_2 0x0003
+#define RT5665_MONO_OUT 0x0004
+#define RT5665_HPL_GAIN 0x0005
+#define RT5665_HPR_GAIN 0x0006
+#define RT5665_MONO_GAIN 0x0007
+
+/* I/O - Input */
+#define RT5665_CAL_BST_CTRL 0x000a
+#define RT5665_CBJ_BST_CTRL 0x000b
+#define RT5665_IN1_IN2 0x000c
+#define RT5665_IN3_IN4 0x000d
+#define RT5665_INL1_INR1_VOL 0x000f
+/* I/O - Speaker */
+#define RT5665_EJD_CTRL_1 0x0010
+#define RT5665_EJD_CTRL_2 0x0011
+#define RT5665_EJD_CTRL_3 0x0012
+#define RT5665_EJD_CTRL_4 0x0013
+#define RT5665_EJD_CTRL_5 0x0014
+#define RT5665_EJD_CTRL_6 0x0015
+#define RT5665_EJD_CTRL_7 0x0016
+/* I/O - ADC/DAC/DMIC */
+#define RT5665_DAC2_CTRL 0x0017
+#define RT5665_DAC2_DIG_VOL 0x0018
+#define RT5665_DAC1_DIG_VOL 0x0019
+#define RT5665_DAC3_DIG_VOL 0x001a
+#define RT5665_DAC3_CTRL 0x001b
+#define RT5665_STO1_ADC_DIG_VOL 0x001c
+#define RT5665_MONO_ADC_DIG_VOL 0x001d
+#define RT5665_STO2_ADC_DIG_VOL 0x001e
+#define RT5665_STO1_ADC_BOOST 0x001f
+#define RT5665_MONO_ADC_BOOST 0x0020
+#define RT5665_STO2_ADC_BOOST 0x0021
+#define RT5665_HP_IMP_GAIN_1 0x0022
+#define RT5665_HP_IMP_GAIN_2 0x0023
+/* Mixer - D-D */
+#define RT5665_STO1_ADC_MIXER 0x0026
+#define RT5665_MONO_ADC_MIXER 0x0027
+#define RT5665_STO2_ADC_MIXER 0x0028
+#define RT5665_AD_DA_MIXER 0x0029
+#define RT5665_STO1_DAC_MIXER 0x002a
+#define RT5665_MONO_DAC_MIXER 0x002b
+#define RT5665_STO2_DAC_MIXER 0x002c
+#define RT5665_A_DAC1_MUX 0x002d
+#define RT5665_A_DAC2_MUX 0x002e
+#define RT5665_DIG_INF2_DATA 0x002f
+#define RT5665_DIG_INF3_DATA 0x0030
+/* Mixer - PDM */
+#define RT5665_PDM_OUT_CTRL 0x0031
+#define RT5665_PDM_DATA_CTRL_1 0x0032
+#define RT5665_PDM_DATA_CTRL_2 0x0033
+#define RT5665_PDM_DATA_CTRL_3 0x0034
+#define RT5665_PDM_DATA_CTRL_4 0x0035
+/* Mixer - ADC */
+#define RT5665_REC1_GAIN 0x003a
+#define RT5665_REC1_L1_MIXER 0x003b
+#define RT5665_REC1_L2_MIXER 0x003c
+#define RT5665_REC1_R1_MIXER 0x003d
+#define RT5665_REC1_R2_MIXER 0x003e
+#define RT5665_REC2_GAIN 0x003f
+#define RT5665_REC2_L1_MIXER 0x0040
+#define RT5665_REC2_L2_MIXER 0x0041
+#define RT5665_REC2_R1_MIXER 0x0042
+#define RT5665_REC2_R2_MIXER 0x0043
+#define RT5665_CAL_REC 0x0044
+/* Mixer - DAC */
+#define RT5665_ALC_BACK_GAIN 0x0049
+#define RT5665_MONOMIX_GAIN 0x004a
+#define RT5665_MONOMIX_IN_GAIN 0x004b
+#define RT5665_OUT_L_GAIN 0x004d
+#define RT5665_OUT_L_MIXER 0x004e
+#define RT5665_OUT_R_GAIN 0x004f
+#define RT5665_OUT_R_MIXER 0x0050
+#define RT5665_LOUT_MIXER 0x0052
+/* Power */
+#define RT5665_PWR_DIG_1 0x0061
+#define RT5665_PWR_DIG_2 0x0062
+#define RT5665_PWR_ANLG_1 0x0063
+#define RT5665_PWR_ANLG_2 0x0064
+#define RT5665_PWR_ANLG_3 0x0065
+#define RT5665_PWR_MIXER 0x0066
+#define RT5665_PWR_VOL 0x0067
+/* Clock Detect */
+#define RT5665_CLK_DET 0x006b
+/* Filter */
+#define RT5665_HPF_CTRL1 0x006d
+/* DMIC */
+#define RT5665_DMIC_CTRL_1 0x006e
+#define RT5665_DMIC_CTRL_2 0x006f
+/* Format - ADC/DAC */
+#define RT5665_I2S1_SDP 0x0070
+#define RT5665_I2S2_SDP 0x0071
+#define RT5665_I2S3_SDP 0x0072
+#define RT5665_ADDA_CLK_1 0x0073
+#define RT5665_ADDA_CLK_2 0x0074
+#define RT5665_I2S1_F_DIV_CTRL_1 0x0075
+#define RT5665_I2S1_F_DIV_CTRL_2 0x0076
+/* Format - TDM Control */
+#define RT5665_TDM_CTRL_1 0x0078
+#define RT5665_TDM_CTRL_2 0x0079
+#define RT5665_TDM_CTRL_3 0x007a
+#define RT5665_TDM_CTRL_4 0x007b
+#define RT5665_TDM_CTRL_5 0x007c
+#define RT5665_TDM_CTRL_6 0x007d
+#define RT5665_TDM_CTRL_7 0x007e
+#define RT5665_TDM_CTRL_8 0x007f
+/* Function - Analog */
+#define RT5665_GLB_CLK 0x0080
+#define RT5665_PLL_CTRL_1 0x0081
+#define RT5665_PLL_CTRL_2 0x0082
+#define RT5665_ASRC_1 0x0083
+#define RT5665_ASRC_2 0x0084
+#define RT5665_ASRC_3 0x0085
+#define RT5665_ASRC_4 0x0086
+#define RT5665_ASRC_5 0x0087
+#define RT5665_ASRC_6 0x0088
+#define RT5665_ASRC_7 0x0089
+#define RT5665_ASRC_8 0x008a
+#define RT5665_ASRC_9 0x008b
+#define RT5665_ASRC_10 0x008c
+#define RT5665_DEPOP_1 0x008e
+#define RT5665_DEPOP_2 0x008f
+#define RT5665_HP_CHARGE_PUMP_1 0x0091
+#define RT5665_HP_CHARGE_PUMP_2 0x0092
+#define RT5665_MICBIAS_1 0x0093
+#define RT5665_MICBIAS_2 0x0094
+#define RT5665_ASRC_12 0x0098
+#define RT5665_ASRC_13 0x0099
+#define RT5665_ASRC_14 0x009a
+#define RT5665_RC_CLK_CTRL 0x009f
+#define RT5665_I2S_M_CLK_CTRL_1 0x00a0
+#define RT5665_I2S2_F_DIV_CTRL_1 0x00a1
+#define RT5665_I2S2_F_DIV_CTRL_2 0x00a2
+#define RT5665_I2S3_F_DIV_CTRL_1 0x00a3
+#define RT5665_I2S3_F_DIV_CTRL_2 0x00a4
+/* Function - Digital */
+#define RT5665_EQ_CTRL_1 0x00ae
+#define RT5665_EQ_CTRL_2 0x00af
+#define RT5665_IRQ_CTRL_1 0x00b6
+#define RT5665_IRQ_CTRL_2 0x00b7
+#define RT5665_IRQ_CTRL_3 0x00b8
+#define RT5665_IRQ_CTRL_4 0x00b9
+#define RT5665_IRQ_CTRL_5 0x00ba
+#define RT5665_IRQ_CTRL_6 0x00bb
+#define RT5665_INT_ST_1 0x00be
+#define RT5665_GPIO_CTRL_1 0x00c0
+#define RT5665_GPIO_CTRL_2 0x00c1
+#define RT5665_GPIO_CTRL_3 0x00c2
+#define RT5665_GPIO_CTRL_4 0x00c3
+#define RT5665_GPIO_STA 0x00c4
+#define RT5665_HP_AMP_DET_CTRL_1 0x00d0
+#define RT5665_HP_AMP_DET_CTRL_2 0x00d1
+#define RT5665_MID_HP_AMP_DET 0x00d3
+#define RT5665_LOW_HP_AMP_DET 0x00d4
+#define RT5665_SV_ZCD_1 0x00d9
+#define RT5665_SV_ZCD_2 0x00da
+#define RT5665_IL_CMD_1 0x00db
+#define RT5665_IL_CMD_2 0x00dc
+#define RT5665_IL_CMD_3 0x00dd
+#define RT5665_IL_CMD_4 0x00de
+#define RT5665_4BTN_IL_CMD_1 0x00df
+#define RT5665_4BTN_IL_CMD_2 0x00e0
+#define RT5665_4BTN_IL_CMD_3 0x00e1
+#define RT5665_PSV_IL_CMD_1 0x00e2
+
+#define RT5665_ADC_STO1_HP_CTRL_1 0x00ea
+#define RT5665_ADC_STO1_HP_CTRL_2 0x00eb
+#define RT5665_ADC_MONO_HP_CTRL_1 0x00ec
+#define RT5665_ADC_MONO_HP_CTRL_2 0x00ed
+#define RT5665_ADC_STO2_HP_CTRL_1 0x00ee
+#define RT5665_ADC_STO2_HP_CTRL_2 0x00ef
+#define RT5665_AJD1_CTRL 0x00f0
+#define RT5665_JD1_THD 0x00f1
+#define RT5665_JD2_THD 0x00f2
+#define RT5665_JD_CTRL_1 0x00f6
+#define RT5665_JD_CTRL_2 0x00f7
+#define RT5665_JD_CTRL_3 0x00f8
+/* General Control */
+#define RT5665_DIG_MISC 0x00fa
+#define RT5665_DUMMY_2 0x00fb
+#define RT5665_DUMMY_3 0x00fc
+
+#define RT5665_DAC_ADC_DIG_VOL1 0x0100
+#define RT5665_DAC_ADC_DIG_VOL2 0x0101
+#define RT5665_BIAS_CUR_CTRL_1 0x010a
+#define RT5665_BIAS_CUR_CTRL_2 0x010b
+#define RT5665_BIAS_CUR_CTRL_3 0x010c
+#define RT5665_BIAS_CUR_CTRL_4 0x010d
+#define RT5665_BIAS_CUR_CTRL_5 0x010e
+#define RT5665_BIAS_CUR_CTRL_6 0x010f
+#define RT5665_BIAS_CUR_CTRL_7 0x0110
+#define RT5665_BIAS_CUR_CTRL_8 0x0111
+#define RT5665_BIAS_CUR_CTRL_9 0x0112
+#define RT5665_BIAS_CUR_CTRL_10 0x0113
+#define RT5665_VREF_REC_OP_FB_CAP_CTRL 0x0117
+#define RT5665_CHARGE_PUMP_1 0x0125
+#define RT5665_DIG_IN_CTRL_1 0x0132
+#define RT5665_DIG_IN_CTRL_2 0x0133
+#define RT5665_PAD_DRIVING_CTRL 0x0137
+#define RT5665_SOFT_RAMP_DEPOP 0x0138
+#define RT5665_PLL 0x0139
+#define RT5665_CHOP_DAC 0x013a
+#define RT5665_CHOP_ADC 0x013b
+#define RT5665_CALIB_ADC_CTRL 0x013c
+#define RT5665_VOL_TEST 0x013f
+#define RT5665_TEST_MODE_CTRL_1 0x0145
+#define RT5665_TEST_MODE_CTRL_2 0x0146
+#define RT5665_TEST_MODE_CTRL_3 0x0147
+#define RT5665_TEST_MODE_CTRL_4 0x0148
+#define RT5665_BASSBACK_CTRL 0x0150
+#define RT5665_STO_NG2_CTRL_1 0x0160
+#define RT5665_STO_NG2_CTRL_2 0x0161
+#define RT5665_STO_NG2_CTRL_3 0x0162
+#define RT5665_STO_NG2_CTRL_4 0x0163
+#define RT5665_STO_NG2_CTRL_5 0x0164
+#define RT5665_STO_NG2_CTRL_6 0x0165
+#define RT5665_STO_NG2_CTRL_7 0x0166
+#define RT5665_STO_NG2_CTRL_8 0x0167
+#define RT5665_MONO_NG2_CTRL_1 0x0170
+#define RT5665_MONO_NG2_CTRL_2 0x0171
+#define RT5665_MONO_NG2_CTRL_3 0x0172
+#define RT5665_MONO_NG2_CTRL_4 0x0173
+#define RT5665_MONO_NG2_CTRL_5 0x0174
+#define RT5665_MONO_NG2_CTRL_6 0x0175
+#define RT5665_STO1_DAC_SIL_DET 0x0190
+#define RT5665_MONOL_DAC_SIL_DET 0x0191
+#define RT5665_MONOR_DAC_SIL_DET 0x0192
+#define RT5665_STO2_DAC_SIL_DET 0x0193
+#define RT5665_SIL_PSV_CTRL1 0x0194
+#define RT5665_SIL_PSV_CTRL2 0x0195
+#define RT5665_SIL_PSV_CTRL3 0x0196
+#define RT5665_SIL_PSV_CTRL4 0x0197
+#define RT5665_SIL_PSV_CTRL5 0x0198
+#define RT5665_SIL_PSV_CTRL6 0x0199
+#define RT5665_MONO_AMP_CALIB_CTRL_1 0x01a0
+#define RT5665_MONO_AMP_CALIB_CTRL_2 0x01a1
+#define RT5665_MONO_AMP_CALIB_CTRL_3 0x01a2
+#define RT5665_MONO_AMP_CALIB_CTRL_4 0x01a3
+#define RT5665_MONO_AMP_CALIB_CTRL_5 0x01a4
+#define RT5665_MONO_AMP_CALIB_CTRL_6 0x01a5
+#define RT5665_MONO_AMP_CALIB_CTRL_7 0x01a6
+#define RT5665_MONO_AMP_CALIB_STA1 0x01a7
+#define RT5665_MONO_AMP_CALIB_STA2 0x01a8
+#define RT5665_MONO_AMP_CALIB_STA3 0x01a9
+#define RT5665_MONO_AMP_CALIB_STA4 0x01aa
+#define RT5665_MONO_AMP_CALIB_STA6 0x01ab
+#define RT5665_HP_IMP_SENS_CTRL_01 0x01b5
+#define RT5665_HP_IMP_SENS_CTRL_02 0x01b6
+#define RT5665_HP_IMP_SENS_CTRL_03 0x01b7
+#define RT5665_HP_IMP_SENS_CTRL_04 0x01b8
+#define RT5665_HP_IMP_SENS_CTRL_05 0x01b9
+#define RT5665_HP_IMP_SENS_CTRL_06 0x01ba
+#define RT5665_HP_IMP_SENS_CTRL_07 0x01bb
+#define RT5665_HP_IMP_SENS_CTRL_08 0x01bc
+#define RT5665_HP_IMP_SENS_CTRL_09 0x01bd
+#define RT5665_HP_IMP_SENS_CTRL_10 0x01be
+#define RT5665_HP_IMP_SENS_CTRL_11 0x01bf
+#define RT5665_HP_IMP_SENS_CTRL_12 0x01c0
+#define RT5665_HP_IMP_SENS_CTRL_13 0x01c1
+#define RT5665_HP_IMP_SENS_CTRL_14 0x01c2
+#define RT5665_HP_IMP_SENS_CTRL_15 0x01c3
+#define RT5665_HP_IMP_SENS_CTRL_16 0x01c4
+#define RT5665_HP_IMP_SENS_CTRL_17 0x01c5
+#define RT5665_HP_IMP_SENS_CTRL_18 0x01c6
+#define RT5665_HP_IMP_SENS_CTRL_19 0x01c7
+#define RT5665_HP_IMP_SENS_CTRL_20 0x01c8
+#define RT5665_HP_IMP_SENS_CTRL_21 0x01c9
+#define RT5665_HP_IMP_SENS_CTRL_22 0x01ca
+#define RT5665_HP_IMP_SENS_CTRL_23 0x01cb
+#define RT5665_HP_IMP_SENS_CTRL_24 0x01cc
+#define RT5665_HP_IMP_SENS_CTRL_25 0x01cd
+#define RT5665_HP_IMP_SENS_CTRL_26 0x01ce
+#define RT5665_HP_IMP_SENS_CTRL_27 0x01cf
+#define RT5665_HP_IMP_SENS_CTRL_28 0x01d0
+#define RT5665_HP_IMP_SENS_CTRL_29 0x01d1
+#define RT5665_HP_IMP_SENS_CTRL_30 0x01d2
+#define RT5665_HP_IMP_SENS_CTRL_31 0x01d3
+#define RT5665_HP_IMP_SENS_CTRL_32 0x01d4
+#define RT5665_HP_IMP_SENS_CTRL_33 0x01d5
+#define RT5665_HP_IMP_SENS_CTRL_34 0x01d6
+#define RT5665_HP_LOGIC_CTRL_1 0x01da
+#define RT5665_HP_LOGIC_CTRL_2 0x01db
+#define RT5665_HP_LOGIC_CTRL_3 0x01dc
+#define RT5665_HP_CALIB_CTRL_1 0x01de
+#define RT5665_HP_CALIB_CTRL_2 0x01df
+#define RT5665_HP_CALIB_CTRL_3 0x01e0
+#define RT5665_HP_CALIB_CTRL_4 0x01e1
+#define RT5665_HP_CALIB_CTRL_5 0x01e2
+#define RT5665_HP_CALIB_CTRL_6 0x01e3
+#define RT5665_HP_CALIB_CTRL_7 0x01e4
+#define RT5665_HP_CALIB_CTRL_9 0x01e6
+#define RT5665_HP_CALIB_CTRL_10 0x01e7
+#define RT5665_HP_CALIB_CTRL_11 0x01e8
+#define RT5665_HP_CALIB_STA_1 0x01ea
+#define RT5665_HP_CALIB_STA_2 0x01eb
+#define RT5665_HP_CALIB_STA_3 0x01ec
+#define RT5665_HP_CALIB_STA_4 0x01ed
+#define RT5665_HP_CALIB_STA_5 0x01ee
+#define RT5665_HP_CALIB_STA_6 0x01ef
+#define RT5665_HP_CALIB_STA_7 0x01f0
+#define RT5665_HP_CALIB_STA_8 0x01f1
+#define RT5665_HP_CALIB_STA_9 0x01f2
+#define RT5665_HP_CALIB_STA_10 0x01f3
+#define RT5665_HP_CALIB_STA_11 0x01f4
+#define RT5665_PGM_TAB_CTRL1 0x0200
+#define RT5665_PGM_TAB_CTRL2 0x0201
+#define RT5665_PGM_TAB_CTRL3 0x0202
+#define RT5665_PGM_TAB_CTRL4 0x0203
+#define RT5665_PGM_TAB_CTRL5 0x0204
+#define RT5665_PGM_TAB_CTRL6 0x0205
+#define RT5665_PGM_TAB_CTRL7 0x0206
+#define RT5665_PGM_TAB_CTRL8 0x0207
+#define RT5665_PGM_TAB_CTRL9 0x0208
+#define RT5665_SAR_IL_CMD_1 0x0210
+#define RT5665_SAR_IL_CMD_2 0x0211
+#define RT5665_SAR_IL_CMD_3 0x0212
+#define RT5665_SAR_IL_CMD_4 0x0213
+#define RT5665_SAR_IL_CMD_5 0x0214
+#define RT5665_SAR_IL_CMD_6 0x0215
+#define RT5665_SAR_IL_CMD_7 0x0216
+#define RT5665_SAR_IL_CMD_8 0x0217
+#define RT5665_SAR_IL_CMD_9 0x0218
+#define RT5665_SAR_IL_CMD_10 0x0219
+#define RT5665_SAR_IL_CMD_11 0x021a
+#define RT5665_SAR_IL_CMD_12 0x021b
+#define RT5665_DRC1_CTRL_0 0x02ff
+#define RT5665_DRC1_CTRL_1 0x0300
+#define RT5665_DRC1_CTRL_2 0x0301
+#define RT5665_DRC1_CTRL_3 0x0302
+#define RT5665_DRC1_CTRL_4 0x0303
+#define RT5665_DRC1_CTRL_5 0x0304
+#define RT5665_DRC1_CTRL_6 0x0305
+#define RT5665_DRC1_HARD_LMT_CTRL_1 0x0306
+#define RT5665_DRC1_HARD_LMT_CTRL_2 0x0307
+#define RT5665_DRC1_PRIV_1 0x0310
+#define RT5665_DRC1_PRIV_2 0x0311
+#define RT5665_DRC1_PRIV_3 0x0312
+#define RT5665_DRC1_PRIV_4 0x0313
+#define RT5665_DRC1_PRIV_5 0x0314
+#define RT5665_DRC1_PRIV_6 0x0315
+#define RT5665_DRC1_PRIV_7 0x0316
+#define RT5665_DRC1_PRIV_8 0x0317
+#define RT5665_ALC_PGA_CTRL_1 0x0330
+#define RT5665_ALC_PGA_CTRL_2 0x0331
+#define RT5665_ALC_PGA_CTRL_3 0x0332
+#define RT5665_ALC_PGA_CTRL_4 0x0333
+#define RT5665_ALC_PGA_CTRL_5 0x0334
+#define RT5665_ALC_PGA_CTRL_6 0x0335
+#define RT5665_ALC_PGA_CTRL_7 0x0336
+#define RT5665_ALC_PGA_CTRL_8 0x0337
+#define RT5665_ALC_PGA_STA_1 0x0338
+#define RT5665_ALC_PGA_STA_2 0x0339
+#define RT5665_ALC_PGA_STA_3 0x033a
+#define RT5665_EQ_AUTO_RCV_CTRL1 0x03c0
+#define RT5665_EQ_AUTO_RCV_CTRL2 0x03c1
+#define RT5665_EQ_AUTO_RCV_CTRL3 0x03c2
+#define RT5665_EQ_AUTO_RCV_CTRL4 0x03c3
+#define RT5665_EQ_AUTO_RCV_CTRL5 0x03c4
+#define RT5665_EQ_AUTO_RCV_CTRL6 0x03c5
+#define RT5665_EQ_AUTO_RCV_CTRL7 0x03c6
+#define RT5665_EQ_AUTO_RCV_CTRL8 0x03c7
+#define RT5665_EQ_AUTO_RCV_CTRL9 0x03c8
+#define RT5665_EQ_AUTO_RCV_CTRL10 0x03c9
+#define RT5665_EQ_AUTO_RCV_CTRL11 0x03ca
+#define RT5665_EQ_AUTO_RCV_CTRL12 0x03cb
+#define RT5665_EQ_AUTO_RCV_CTRL13 0x03cc
+#define RT5665_ADC_L_EQ_LPF1_A1 0x03d0
+#define RT5665_R_EQ_LPF1_A1 0x03d1
+#define RT5665_L_EQ_LPF1_H0 0x03d2
+#define RT5665_R_EQ_LPF1_H0 0x03d3
+#define RT5665_L_EQ_BPF1_A1 0x03d4
+#define RT5665_R_EQ_BPF1_A1 0x03d5
+#define RT5665_L_EQ_BPF1_A2 0x03d6
+#define RT5665_R_EQ_BPF1_A2 0x03d7
+#define RT5665_L_EQ_BPF1_H0 0x03d8
+#define RT5665_R_EQ_BPF1_H0 0x03d9
+#define RT5665_L_EQ_BPF2_A1 0x03da
+#define RT5665_R_EQ_BPF2_A1 0x03db
+#define RT5665_L_EQ_BPF2_A2 0x03dc
+#define RT5665_R_EQ_BPF2_A2 0x03dd
+#define RT5665_L_EQ_BPF2_H0 0x03de
+#define RT5665_R_EQ_BPF2_H0 0x03df
+#define RT5665_L_EQ_BPF3_A1 0x03e0
+#define RT5665_R_EQ_BPF3_A1 0x03e1
+#define RT5665_L_EQ_BPF3_A2 0x03e2
+#define RT5665_R_EQ_BPF3_A2 0x03e3
+#define RT5665_L_EQ_BPF3_H0 0x03e4
+#define RT5665_R_EQ_BPF3_H0 0x03e5
+#define RT5665_L_EQ_BPF4_A1 0x03e6
+#define RT5665_R_EQ_BPF4_A1 0x03e7
+#define RT5665_L_EQ_BPF4_A2 0x03e8
+#define RT5665_R_EQ_BPF4_A2 0x03e9
+#define RT5665_L_EQ_BPF4_H0 0x03ea
+#define RT5665_R_EQ_BPF4_H0 0x03eb
+#define RT5665_L_EQ_HPF1_A1 0x03ec
+#define RT5665_R_EQ_HPF1_A1 0x03ed
+#define RT5665_L_EQ_HPF1_H0 0x03ee
+#define RT5665_R_EQ_HPF1_H0 0x03ef
+#define RT5665_L_EQ_PRE_VOL 0x03f0
+#define RT5665_R_EQ_PRE_VOL 0x03f1
+#define RT5665_L_EQ_POST_VOL 0x03f2
+#define RT5665_R_EQ_POST_VOL 0x03f3
+#define RT5665_SCAN_MODE_CTRL 0x07f0
+#define RT5665_I2C_MODE 0x07fa
+
+
+
+/* global definition */
+#define RT5665_L_MUTE (0x1 << 15)
+#define RT5665_L_MUTE_SFT 15
+#define RT5665_VOL_L_MUTE (0x1 << 14)
+#define RT5665_VOL_L_SFT 14
+#define RT5665_R_MUTE (0x1 << 7)
+#define RT5665_R_MUTE_SFT 7
+#define RT5665_VOL_R_MUTE (0x1 << 6)
+#define RT5665_VOL_R_SFT 6
+#define RT5665_L_VOL_MASK (0x3f << 8)
+#define RT5665_L_VOL_SFT 8
+#define RT5665_R_VOL_MASK (0x3f)
+#define RT5665_R_VOL_SFT 0
+
+/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
+#define RT5665_G_HP (0xf << 8)
+#define RT5665_G_HP_SFT 8
+#define RT5665_G_STO_DA_DMIX (0xf)
+#define RT5665_G_STO_DA_SFT 0
+
+/* CBJ Control (0x000b) */
+#define RT5665_BST_CBJ_MASK (0xf << 8)
+#define RT5665_BST_CBJ_SFT 8
+
+/* IN1/IN2 Control (0x000c) */
+#define RT5665_IN1_DF_MASK (0x1 << 15)
+#define RT5665_IN1_DF 15
+#define RT5665_BST1_MASK (0x7f << 8)
+#define RT5665_BST1_SFT 8
+#define RT5665_IN2_DF_MASK (0x1 << 7)
+#define RT5665_IN2_DF 7
+#define RT5665_BST2_MASK (0x7f)
+#define RT5665_BST2_SFT 0
+
+/* IN3/IN4 Control (0x000d) */
+#define RT5665_IN3_DF_MASK (0x1 << 15)
+#define RT5665_IN3_DF 15
+#define RT5665_BST3_MASK (0x7f << 8)
+#define RT5665_BST3_SFT 8
+#define RT5665_IN4_DF_MASK (0x1 << 7)
+#define RT5665_IN4_DF 7
+#define RT5665_BST4_MASK (0x7f)
+#define RT5665_BST4_SFT 0
+
+/* INL and INR Volume Control (0x000f) */
+#define RT5665_INL_VOL_MASK (0x1f << 8)
+#define RT5665_INL_VOL_SFT 8
+#define RT5665_INR_VOL_MASK (0x1f)
+#define RT5665_INR_VOL_SFT 0
+
+/* Embeeded Jack and Type Detection Control 1 (0x0010) */
+#define RT5665_EMB_JD_EN (0x1 << 15)
+#define RT5665_EMB_JD_EN_SFT 15
+#define RT5665_JD_MODE (0x1 << 13)
+#define RT5665_JD_MODE_SFT 13
+#define RT5665_POLA_EXT_JD_MASK (0x1 << 11)
+#define RT5665_POLA_EXT_JD_LOW (0x1 << 11)
+#define RT5665_POLA_EXT_JD_HIGH (0x0 << 11)
+#define RT5665_EXT_JD_DIG (0x1 << 9)
+#define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
+#define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
+#define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
+#define RT5665_VREF_POW_MASK (0x1 << 6)
+#define RT5665_VREF_POW_FSM (0x0 << 6)
+#define RT5665_VREF_POW_REG (0x1 << 6)
+#define RT5665_MB1_PATH_MASK (0x1 << 5)
+#define RT5665_CTRL_MB1_REG (0x1 << 5)
+#define RT5665_CTRL_MB1_FSM (0x0 << 5)
+#define RT5665_MB2_PATH_MASK (0x1 << 4)
+#define RT5665_CTRL_MB2_REG (0x1 << 4)
+#define RT5665_CTRL_MB2_FSM (0x0 << 4)
+#define RT5665_TRIG_JD_MASK (0x1 << 3)
+#define RT5665_TRIG_JD_HIGH (0x1 << 3)
+#define RT5665_TRIG_JD_LOW (0x0 << 3)
+
+/* Embeeded Jack and Type Detection Control 2 (0x0011) */
+#define RT5665_EXT_JD_SRC (0x7 << 4)
+#define RT5665_EXT_JD_SRC_SFT 4
+#define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
+#define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
+#define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4)
+#define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)
+#define RT5665_EXT_JD_SRC_JD2 (0x4 << 4)
+#define RT5665_EXT_JD_SRC_JD3 (0x5 << 4)
+#define RT5665_EXT_JD_SRC_MANUAL (0x6 << 4)
+
+/* Combo Jack and Type Detection Control 4 (0x0013) */
+#define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
+#define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
+#define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
+#define RT5665_CBJ_JD_TEST_MASK (0x1 << 6)
+#define RT5665_CBJ_JD_TEST_NORM (0x0 << 6)
+#define RT5665_CBJ_JD_TEST_MODE (0x1 << 6)
+
+/* Slience Detection Control (0x0015) */
+#define RT5665_SIL_DET_MASK (0x1 << 15)
+#define RT5665_SIL_DET_DIS (0x0 << 15)
+#define RT5665_SIL_DET_EN (0x1 << 15)
+
+/* DAC2 Control (0x0017) */
+#define RT5665_M_DAC2_L_VOL (0x1 << 13)
+#define RT5665_M_DAC2_L_VOL_SFT 13
+#define RT5665_M_DAC2_R_VOL (0x1 << 12)
+#define RT5665_M_DAC2_R_VOL_SFT 12
+#define RT5665_DAC_L2_SEL_MASK (0x7 << 4)
+#define RT5665_DAC_L2_SEL_SFT 4
+#define RT5665_DAC_R2_SEL_MASK (0x7 << 0)
+#define RT5665_DAC_R2_SEL_SFT 0
+
+/* Sidetone Control (0x0018) */
+#define RT5665_ST_SEL_MASK (0x7 << 9)
+#define RT5665_ST_SEL_SFT 9
+#define RT5665_ST_EN (0x1 << 6)
+#define RT5665_ST_EN_SFT 6
+
+/* DAC1 Digital Volume (0x0019) */
+#define RT5665_DAC_L1_VOL_MASK (0xff << 8)
+#define RT5665_DAC_L1_VOL_SFT 8
+#define RT5665_DAC_R1_VOL_MASK (0xff)
+#define RT5665_DAC_R1_VOL_SFT 0
+
+/* DAC2 Digital Volume (0x001a) */
+#define RT5665_DAC_L2_VOL_MASK (0xff << 8)
+#define RT5665_DAC_L2_VOL_SFT 8
+#define RT5665_DAC_R2_VOL_MASK (0xff)
+#define RT5665_DAC_R2_VOL_SFT 0
+
+/* DAC3 Control (0x001b) */
+#define RT5665_M_DAC3_L_VOL (0x1 << 13)
+#define RT5665_M_DAC3_L_VOL_SFT 13
+#define RT5665_M_DAC3_R_VOL (0x1 << 12)
+#define RT5665_M_DAC3_R_VOL_SFT 12
+#define RT5665_DAC_L3_SEL_MASK (0x7 << 4)
+#define RT5665_DAC_L3_SEL_SFT 4
+#define RT5665_DAC_R3_SEL_MASK (0x7 << 0)
+#define RT5665_DAC_R3_SEL_SFT 0
+
+/* ADC Digital Volume Control (0x001c) */
+#define RT5665_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5665_ADC_L_VOL_SFT 8
+#define RT5665_ADC_R_VOL_MASK (0x7f)
+#define RT5665_ADC_R_VOL_SFT 0
+
+/* Mono ADC Digital Volume Control (0x001d) */
+#define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5665_MONO_ADC_L_VOL_SFT 8
+#define RT5665_MONO_ADC_R_VOL_MASK (0x7f)
+#define RT5665_MONO_ADC_R_VOL_SFT 0
+
+/* Stereo1 ADC Boost Gain Control (0x001f) */
+#define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14)
+#define RT5665_STO1_ADC_L_BST_SFT 14
+#define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
+#define RT5665_STO1_ADC_R_BST_SFT 12
+
+/* Mono ADC Boost Gain Control (0x0020) */
+#define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14)
+#define RT5665_MONO_ADC_L_BST_SFT 14
+#define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
+#define RT5665_MONO_ADC_R_BST_SFT 12
+
+/* Stereo1 ADC Boost Gain Control (0x001f) */
+#define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14)
+#define RT5665_STO2_ADC_L_BST_SFT 14
+#define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
+#define RT5665_STO2_ADC_R_BST_SFT 12
+
+/* Stereo1 ADC Mixer Control (0x0026) */
+#define RT5665_M_STO1_ADC_L1 (0x1 << 15)
+#define RT5665_M_STO1_ADC_L1_SFT 15
+#define RT5665_M_STO1_ADC_L2 (0x1 << 14)
+#define RT5665_M_STO1_ADC_L2_SFT 14
+#define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)
+#define RT5665_STO1_ADC1L_SRC_SFT 13
+#define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)
+#define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13)
+#define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
+#define RT5665_STO1_ADC2L_SRC_SFT 12
+#define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10)
+#define RT5665_STO1_ADCL_SRC_SFT 10
+#define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)
+#define RT5665_STO1_DD_L_SRC_SFT 9
+#define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
+#define RT5665_STO1_DMIC_SRC_SFT 8
+#define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
+#define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
+#define RT5665_M_STO1_ADC_R1 (0x1 << 7)
+#define RT5665_M_STO1_ADC_R1_SFT 7
+#define RT5665_M_STO1_ADC_R2 (0x1 << 6)
+#define RT5665_M_STO1_ADC_R2_SFT 6
+#define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5)
+#define RT5665_STO1_ADC1R_SRC_SFT 5
+#define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4)
+#define RT5665_STO1_ADC2R_SRC_SFT 4
+#define RT5665_STO1_ADCR_SRC_MASK (0x3 << 2)
+#define RT5665_STO1_ADCR_SRC_SFT 2
+#define RT5665_STO1_DD_R_SRC_MASK (0x3)
+#define RT5665_STO1_DD_R_SRC_SFT 0
+
+
+/* Mono1 ADC Mixer control (0x0027) */
+#define RT5665_M_MONO_ADC_L1 (0x1 << 15)
+#define RT5665_M_MONO_ADC_L1_SFT 15
+#define RT5665_M_MONO_ADC_L2 (0x1 << 14)
+#define RT5665_M_MONO_ADC_L2_SFT 14
+#define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)
+#define RT5665_MONO_ADC_L1_SRC_SFT 13
+#define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
+#define RT5665_MONO_ADC_L2_SRC_SFT 12
+#define RT5665_MONO_ADC_L_SRC_MASK (0x3 << 10)
+#define RT5665_MONO_ADC_L_SRC_SFT 10
+#define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)
+#define RT5665_MONO_DD_L_SRC_SFT 9
+#define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
+#define RT5665_MONO_DMIC_L_SRC_SFT 8
+#define RT5665_M_MONO_ADC_R1 (0x1 << 7)
+#define RT5665_M_MONO_ADC_R1_SFT 7
+#define RT5665_M_MONO_ADC_R2 (0x1 << 6)
+#define RT5665_M_MONO_ADC_R2_SFT 6
+#define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5)
+#define RT5665_MONO_ADC_R1_SRC_SFT 5
+#define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4)
+#define RT5665_MONO_ADC_R2_SRC_SFT 4
+#define RT5665_MONO_ADC_R_SRC_MASK (0x3 << 2)
+#define RT5665_MONO_ADC_R_SRC_SFT 2
+#define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1)
+#define RT5665_MONO_DD_R_SRC_SFT 1
+#define RT5665_MONO_DMIC_R_SRC_MASK 0x1
+#define RT5665_MONO_DMIC_R_SRC_SFT 0
+
+/* Stereo2 ADC Mixer Control (0x0028) */
+#define RT5665_M_STO2_ADC_L1 (0x1 << 15)
+#define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)
+#define RT5665_M_STO2_ADC_L1_SFT 15
+#define RT5665_M_STO2_ADC_L2 (0x1 << 14)
+#define RT5665_M_STO2_ADC_L2_SFT 14
+#define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)
+#define RT5665_STO2_ADC1L_SRC_SFT 13
+#define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)
+#define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13)
+#define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
+#define RT5665_STO2_ADC2L_SRC_SFT 12
+#define RT5665_STO2_ADCL_SRC_MASK (0x3 << 10)
+#define RT5665_STO2_ADCL_SRC_SFT 10
+#define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)
+#define RT5665_STO2_DD_L_SRC_SFT 9
+#define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
+#define RT5665_STO2_DMIC_SRC_SFT 8
+#define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
+#define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
+#define RT5665_M_STO2_ADC_R1 (0x1 << 7)
+#define RT5665_M_STO2_ADC_R1_UN (0x0 << 7)
+#define RT5665_M_STO2_ADC_R1_SFT 7
+#define RT5665_M_STO2_ADC_R2 (0x1 << 6)
+#define RT5665_M_STO2_ADC_R2_SFT 6
+#define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5)
+#define RT5665_STO2_ADC1R_SRC_SFT 5
+#define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4)
+#define RT5665_STO2_ADC2R_SRC_SFT 4
+#define RT5665_STO2_ADCR_SRC_MASK (0x3 << 2)
+#define RT5665_STO2_ADCR_SRC_SFT 2
+#define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1)
+#define RT5665_STO2_DD_R_SRC_SFT 1
+
+/* ADC Mixer to DAC Mixer Control (0x0029) */
+#define RT5665_M_ADCMIX_L (0x1 << 15)
+#define RT5665_M_ADCMIX_L_SFT 15
+#define RT5665_M_DAC1_L (0x1 << 14)
+#define RT5665_M_DAC1_L_SFT 14
+#define RT5665_DAC1_R_SEL_MASK (0x3 << 10)
+#define RT5665_DAC1_R_SEL_SFT 10
+#define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
+#define RT5665_DAC1_L_SEL_SFT 8
+#define RT5665_M_ADCMIX_R (0x1 << 7)
+#define RT5665_M_ADCMIX_R_SFT 7
+#define RT5665_M_DAC1_R (0x1 << 6)
+#define RT5665_M_DAC1_R_SFT 6
+
+/* Stereo1 DAC Mixer Control (0x002a) */
+#define RT5665_M_DAC_L1_STO_L (0x1 << 15)
+#define RT5665_M_DAC_L1_STO_L_SFT 15
+#define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14)
+#define RT5665_G_DAC_L1_STO_L_SFT 14
+#define RT5665_M_DAC_R1_STO_L (0x1 << 13)
+#define RT5665_M_DAC_R1_STO_L_SFT 13
+#define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
+#define RT5665_G_DAC_R1_STO_L_SFT 12
+#define RT5665_M_DAC_L2_STO_L (0x1 << 11)
+#define RT5665_M_DAC_L2_STO_L_SFT 11
+#define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10)
+#define RT5665_G_DAC_L2_STO_L_SFT 10
+#define RT5665_M_DAC_R2_STO_L (0x1 << 9)
+#define RT5665_M_DAC_R2_STO_L_SFT 9
+#define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
+#define RT5665_G_DAC_R2_STO_L_SFT 8
+#define RT5665_M_DAC_L1_STO_R (0x1 << 7)
+#define RT5665_M_DAC_L1_STO_R_SFT 7
+#define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6)
+#define RT5665_G_DAC_L1_STO_R_SFT 6
+#define RT5665_M_DAC_R1_STO_R (0x1 << 5)
+#define RT5665_M_DAC_R1_STO_R_SFT 5
+#define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4)
+#define RT5665_G_DAC_R1_STO_R_SFT 4
+#define RT5665_M_DAC_L2_STO_R (0x1 << 3)
+#define RT5665_M_DAC_L2_STO_R_SFT 3
+#define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2)
+#define RT5665_G_DAC_L2_STO_R_SFT 2
+#define RT5665_M_DAC_R2_STO_R (0x1 << 1)
+#define RT5665_M_DAC_R2_STO_R_SFT 1
+#define RT5665_G_DAC_R2_STO_R_MASK (0x1)
+#define RT5665_G_DAC_R2_STO_R_SFT 0
+
+/* Mono DAC Mixer Control (0x002b) */
+#define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
+#define RT5665_M_DAC_L1_MONO_L_SFT 15
+#define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14)
+#define RT5665_G_DAC_L1_MONO_L_SFT 14
+#define RT5665_M_DAC_R1_MONO_L (0x1 << 13)
+#define RT5665_M_DAC_R1_MONO_L_SFT 13
+#define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
+#define RT5665_G_DAC_R1_MONO_L_SFT 12
+#define RT5665_M_DAC_L2_MONO_L (0x1 << 11)
+#define RT5665_M_DAC_L2_MONO_L_SFT 11
+#define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10)
+#define RT5665_G_DAC_L2_MONO_L_SFT 10
+#define RT5665_M_DAC_R2_MONO_L (0x1 << 9)
+#define RT5665_M_DAC_R2_MONO_L_SFT 9
+#define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
+#define RT5665_G_DAC_R2_MONO_L_SFT 8
+#define RT5665_M_DAC_L1_MONO_R (0x1 << 7)
+#define RT5665_M_DAC_L1_MONO_R_SFT 7
+#define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6)
+#define RT5665_G_DAC_L1_MONO_R_SFT 6
+#define RT5665_M_DAC_R1_MONO_R (0x1 << 5)
+#define RT5665_M_DAC_R1_MONO_R_SFT 5
+#define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4)
+#define RT5665_G_DAC_R1_MONO_R_SFT 4
+#define RT5665_M_DAC_L2_MONO_R (0x1 << 3)
+#define RT5665_M_DAC_L2_MONO_R_SFT 3
+#define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2)
+#define RT5665_G_DAC_L2_MONO_R_SFT 2
+#define RT5665_M_DAC_R2_MONO_R (0x1 << 1)
+#define RT5665_M_DAC_R2_MONO_R_SFT 1
+#define RT5665_G_DAC_R2_MONO_R_MASK (0x1)
+#define RT5665_G_DAC_R2_MONO_R_SFT 0
+
+/* Stereo2 DAC Mixer Control (0x002c) */
+#define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
+#define RT5665_M_DAC_L1_STO2_L_SFT 15
+#define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14)
+#define RT5665_G_DAC_L1_STO2_L_SFT 14
+#define RT5665_M_DAC_L2_STO2_L (0x1 << 13)
+#define RT5665_M_DAC_L2_STO2_L_SFT 13
+#define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
+#define RT5665_G_DAC_L2_STO2_L_SFT 12
+#define RT5665_M_DAC_L3_STO2_L (0x1 << 11)
+#define RT5665_M_DAC_L3_STO2_L_SFT 11
+#define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10)
+#define RT5665_G_DAC_L3_STO2_L_SFT 10
+#define RT5665_M_ST_DAC_L1 (0x1 << 9)
+#define RT5665_M_ST_DAC_L1_SFT 9
+#define RT5665_M_ST_DAC_R1 (0x1 << 8)
+#define RT5665_M_ST_DAC_R1_SFT 8
+#define RT5665_M_DAC_R1_STO2_R (0x1 << 7)
+#define RT5665_M_DAC_R1_STO2_R_SFT 7
+#define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6)
+#define RT5665_G_DAC_R1_STO2_R_SFT 6
+#define RT5665_M_DAC_R2_STO2_R (0x1 << 5)
+#define RT5665_M_DAC_R2_STO2_R_SFT 5
+#define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4)
+#define RT5665_G_DAC_R2_STO2_R_SFT 4
+#define RT5665_M_DAC_R3_STO2_R (0x1 << 3)
+#define RT5665_M_DAC_R3_STO2_R_SFT 3
+#define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2)
+#define RT5665_G_DAC_R3_STO2_R_SFT 2
+
+/* Analog DAC1 Input Source Control (0x002d) */
+#define RT5665_DAC_MIX_L_MASK (0x3 << 12)
+#define RT5665_DAC_MIX_L_SFT 12
+#define RT5665_DAC_MIX_R_MASK (0x3 << 8)
+#define RT5665_DAC_MIX_R_SFT 8
+#define RT5665_DAC_L1_SRC_MASK (0x3 << 4)
+#define RT5665_A_DACL1_SFT 4
+#define RT5665_DAC_R1_SRC_MASK (0x3)
+#define RT5665_A_DACR1_SFT 0
+
+/* Analog DAC Input Source Control (0x002e) */
+#define RT5665_A_DACL2_SEL (0x1 << 4)
+#define RT5665_A_DACL2_SFT 4
+#define RT5665_A_DACR2_SEL (0x1 << 0)
+#define RT5665_A_DACR2_SFT 0
+
+/* Digital Interface Data Control (0x002f) */
+#define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
+#define RT5665_IF2_1_ADC_IN_SFT 12
+#define RT5665_IF2_1_DAC_SEL_MASK (0x3 << 10)
+#define RT5665_IF2_1_DAC_SEL_SFT 10
+#define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
+#define RT5665_IF2_1_ADC_SEL_SFT 8
+#define RT5665_IF2_2_ADC_IN_MASK (0x7 << 4)
+#define RT5665_IF2_2_ADC_IN_SFT 4
+#define RT5665_IF2_2_DAC_SEL_MASK (0x3 << 2)
+#define RT5665_IF2_2_DAC_SEL_SFT 2
+#define RT5665_IF2_2_ADC_SEL_MASK (0x3 << 0)
+#define RT5665_IF2_2_ADC_SEL_SFT 0
+
+/* Digital Interface Data Control (0x0030) */
+#define RT5665_IF3_ADC_IN_MASK (0x7 << 4)
+#define RT5665_IF3_ADC_IN_SFT 4
+#define RT5665_IF3_DAC_SEL_MASK (0x3 << 2)
+#define RT5665_IF3_DAC_SEL_SFT 2
+#define RT5665_IF3_ADC_SEL_MASK (0x3 << 0)
+#define RT5665_IF3_ADC_SEL_SFT 0
+
+/* PDM Output Control (0x0031) */
+#define RT5665_M_PDM1_L (0x1 << 14)
+#define RT5665_M_PDM1_L_SFT 14
+#define RT5665_M_PDM1_R (0x1 << 12)
+#define RT5665_M_PDM1_R_SFT 12
+#define RT5665_PDM1_L_MASK (0x3 << 10)
+#define RT5665_PDM1_L_SFT 10
+#define RT5665_PDM1_R_MASK (0x3 << 8)
+#define RT5665_PDM1_R_SFT 8
+#define RT5665_PDM1_BUSY (0x1 << 6)
+#define RT5665_PDM_PATTERN (0x1 << 5)
+#define RT5665_PDM_GAIN (0x1 << 4)
+#define RT5665_LRCK_PDM_PI2C (0x1 << 3)
+#define RT5665_PDM_DIV_MASK (0x3)
+
+/*S/PDIF Output Control (0x0036) */
+#define RT5665_SPDIF_SEL_MASK (0x3 << 0)
+#define RT5665_SPDIF_SEL_SFT 0
+
+/* REC Left Mixer Control 2 (0x003c) */
+#define RT5665_M_CBJ_RM1_L (0x1 << 7)
+#define RT5665_M_CBJ_RM1_L_SFT 7
+#define RT5665_M_BST1_RM1_L (0x1 << 5)
+#define RT5665_M_BST1_RM1_L_SFT 5
+#define RT5665_M_BST2_RM1_L (0x1 << 4)
+#define RT5665_M_BST2_RM1_L_SFT 4
+#define RT5665_M_BST3_RM1_L (0x1 << 3)
+#define RT5665_M_BST3_RM1_L_SFT 3
+#define RT5665_M_BST4_RM1_L (0x1 << 2)
+#define RT5665_M_BST4_RM1_L_SFT 2
+#define RT5665_M_INL_RM1_L (0x1 << 1)
+#define RT5665_M_INL_RM1_L_SFT 1
+#define RT5665_M_INR_RM1_L (0x1)
+#define RT5665_M_INR_RM1_L_SFT 0
+
+/* REC Right Mixer Control 2 (0x003e) */
+#define RT5665_M_AEC_REF_RM1_R (0x1 << 7)
+#define RT5665_M_AEC_REF_RM1_R_SFT 7
+#define RT5665_M_BST1_RM1_R (0x1 << 5)
+#define RT5665_M_BST1_RM1_R_SFT 5
+#define RT5665_M_BST2_RM1_R (0x1 << 4)
+#define RT5665_M_BST2_RM1_R_SFT 4
+#define RT5665_M_BST3_RM1_R (0x1 << 3)
+#define RT5665_M_BST3_RM1_R_SFT 3
+#define RT5665_M_BST4_RM1_R (0x1 << 2)
+#define RT5665_M_BST4_RM1_R_SFT 2
+#define RT5665_M_INR_RM1_R (0x1 << 1)
+#define RT5665_M_INR_RM1_R_SFT 1
+#define RT5665_M_MONOVOL_RM1_R (0x1)
+#define RT5665_M_MONOVOL_RM1_R_SFT 0
+
+/* REC Mixer 2 Left Control 2 (0x0041) */
+#define RT5665_M_CBJ_RM2_L (0x1 << 7)
+#define RT5665_M_CBJ_RM2_L_SFT 7
+#define RT5665_M_BST1_RM2_L (0x1 << 5)
+#define RT5665_M_BST1_RM2_L_SFT 5
+#define RT5665_M_BST2_RM2_L (0x1 << 4)
+#define RT5665_M_BST2_RM2_L_SFT 4
+#define RT5665_M_BST3_RM2_L (0x1 << 3)
+#define RT5665_M_BST3_RM2_L_SFT 3
+#define RT5665_M_BST4_RM2_L (0x1 << 2)
+#define RT5665_M_BST4_RM2_L_SFT 2
+#define RT5665_M_INL_RM2_L (0x1 << 1)
+#define RT5665_M_INL_RM2_L_SFT 1
+#define RT5665_M_INR_RM2_L (0x1)
+#define RT5665_M_INR_RM2_L_SFT 0
+
+/* REC Mixer 2 Right Control 2 (0x0043) */
+#define RT5665_M_MONOVOL_RM2_R (0x1 << 7)
+#define RT5665_M_MONOVOL_RM2_R_SFT 7
+#define RT5665_M_BST1_RM2_R (0x1 << 5)
+#define RT5665_M_BST1_RM2_R_SFT 5
+#define RT5665_M_BST2_RM2_R (0x1 << 4)
+#define RT5665_M_BST2_RM2_R_SFT 4
+#define RT5665_M_BST3_RM2_R (0x1 << 3)
+#define RT5665_M_BST3_RM2_R_SFT 3
+#define RT5665_M_BST4_RM2_R (0x1 << 2)
+#define RT5665_M_BST4_RM2_R_SFT 2
+#define RT5665_M_INL_RM2_R (0x1 << 1)
+#define RT5665_M_INL_RM2_R_SFT 1
+#define RT5665_M_INR_RM2_R (0x1)
+#define RT5665_M_INR_RM2_R_SFT 0
+
+/* SPK Left Mixer Control (0x0046) */
+#define RT5665_M_BST3_SM_L (0x1 << 4)
+#define RT5665_M_BST3_SM_L_SFT 4
+#define RT5665_M_IN_R_SM_L (0x1 << 3)
+#define RT5665_M_IN_R_SM_L_SFT 3
+#define RT5665_M_IN_L_SM_L (0x1 << 2)
+#define RT5665_M_IN_L_SM_L_SFT 2
+#define RT5665_M_BST1_SM_L (0x1 << 1)
+#define RT5665_M_BST1_SM_L_SFT 1
+#define RT5665_M_DAC_L2_SM_L (0x1)
+#define RT5665_M_DAC_L2_SM_L_SFT 0
+
+/* SPK Right Mixer Control (0x0047) */
+#define RT5665_M_BST3_SM_R (0x1 << 4)
+#define RT5665_M_BST3_SM_R_SFT 4
+#define RT5665_M_IN_R_SM_R (0x1 << 3)
+#define RT5665_M_IN_R_SM_R_SFT 3
+#define RT5665_M_IN_L_SM_R (0x1 << 2)
+#define RT5665_M_IN_L_SM_R_SFT 2
+#define RT5665_M_BST4_SM_R (0x1 << 1)
+#define RT5665_M_BST4_SM_R_SFT 1
+#define RT5665_M_DAC_R2_SM_R (0x1)
+#define RT5665_M_DAC_R2_SM_R_SFT 0
+
+/* SPO Amp Input and Gain Control (0x0048) */
+#define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)
+#define RT5665_M_DAC_L2_SPKOMIX_SFT 13
+#define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
+#define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
+#define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)
+#define RT5665_M_DAC_R2_SPKOMIX_SFT 9
+#define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
+#define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
+
+/* MONOMIX Input and Gain Control (0x004b) */
+#define RT5665_G_MONOVOL_MA (0x1 << 10)
+#define RT5665_G_MONOVOL_MA_SFT 10
+#define RT5665_M_MONOVOL_MA (0x1 << 9)
+#define RT5665_M_MONOVOL_MA_SFT 9
+#define RT5665_M_DAC_L2_MA (0x1 << 8)
+#define RT5665_M_DAC_L2_MA_SFT 8
+#define RT5665_M_BST3_MM (0x1 << 4)
+#define RT5665_M_BST3_MM_SFT 4
+#define RT5665_M_BST2_MM (0x1 << 3)
+#define RT5665_M_BST2_MM_SFT 3
+#define RT5665_M_BST1_MM (0x1 << 2)
+#define RT5665_M_BST1_MM_SFT 2
+#define RT5665_M_RECMIC2L_MM (0x1 << 1)
+#define RT5665_M_RECMIC2L_MM_SFT 1
+#define RT5665_M_DAC_L2_MM (0x1)
+#define RT5665_M_DAC_L2_MM_SFT 0
+
+/* Output Left Mixer Control 1 (0x004d) */
+#define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
+#define RT5665_G_BST3_OM_L_SFT 12
+#define RT5665_G_BST2_OM_L_MASK (0x7 << 9)
+#define RT5665_G_BST2_OM_L_SFT 9
+#define RT5665_G_BST1_OM_L_MASK (0x7 << 6)
+#define RT5665_G_BST1_OM_L_SFT 6
+#define RT5665_G_IN_L_OM_L_MASK (0x7 << 3)
+#define RT5665_G_IN_L_OM_L_SFT 3
+#define RT5665_G_DAC_L2_OM_L_MASK (0x7 << 0)
+#define RT5665_G_DAC_L2_OM_L_SFT 0
+
+/* Output Left Mixer Input Control (0x004e) */
+#define RT5665_M_BST3_OM_L (0x1 << 4)
+#define RT5665_M_BST3_OM_L_SFT 4
+#define RT5665_M_BST2_OM_L (0x1 << 3)
+#define RT5665_M_BST2_OM_L_SFT 3
+#define RT5665_M_BST1_OM_L (0x1 << 2)
+#define RT5665_M_BST1_OM_L_SFT 2
+#define RT5665_M_IN_L_OM_L (0x1 << 1)
+#define RT5665_M_IN_L_OM_L_SFT 1
+#define RT5665_M_DAC_L2_OM_L (0x1)
+#define RT5665_M_DAC_L2_OM_L_SFT 0
+
+/* Output Right Mixer Input Control (0x0050) */
+#define RT5665_M_BST4_OM_R (0x1 << 4)
+#define RT5665_M_BST4_OM_R_SFT 4
+#define RT5665_M_BST3_OM_R (0x1 << 3)
+#define RT5665_M_BST3_OM_R_SFT 3
+#define RT5665_M_BST2_OM_R (0x1 << 2)
+#define RT5665_M_BST2_OM_R_SFT 2
+#define RT5665_M_IN_R_OM_R (0x1 << 1)
+#define RT5665_M_IN_R_OM_R_SFT 1
+#define RT5665_M_DAC_R2_OM_R (0x1)
+#define RT5665_M_DAC_R2_OM_R_SFT 0
+
+/* LOUT Mixer Control (0x0052) */
+#define RT5665_M_DAC_L2_LM (0x1 << 15)
+#define RT5665_M_DAC_L2_LM_SFT 15
+#define RT5665_M_DAC_R2_LM (0x1 << 14)
+#define RT5665_M_DAC_R2_LM_SFT 14
+#define RT5665_M_OV_L_LM (0x1 << 13)
+#define RT5665_M_OV_L_LM_SFT 13
+#define RT5665_M_OV_R_LM (0x1 << 12)
+#define RT5665_M_OV_R_LM_SFT 12
+#define RT5665_LOUT_BST_SFT 11
+#define RT5665_LOUT_DF (0x1 << 11)
+#define RT5665_LOUT_DF_SFT 11
+
+/* Power Management for Digital 1 (0x0061) */
+#define RT5665_PWR_I2S1_1 (0x1 << 15)
+#define RT5665_PWR_I2S1_1_BIT 15
+#define RT5665_PWR_I2S1_2 (0x1 << 14)
+#define RT5665_PWR_I2S1_2_BIT 14
+#define RT5665_PWR_I2S2_1 (0x1 << 13)
+#define RT5665_PWR_I2S2_1_BIT 13
+#define RT5665_PWR_I2S2_2 (0x1 << 12)
+#define RT5665_PWR_I2S2_2_BIT 12
+#define RT5665_PWR_DAC_L1 (0x1 << 11)
+#define RT5665_PWR_DAC_L1_BIT 11
+#define RT5665_PWR_DAC_R1 (0x1 << 10)
+#define RT5665_PWR_DAC_R1_BIT 10
+#define RT5665_PWR_I2S3 (0x1 << 9)
+#define RT5665_PWR_I2S3_BIT 9
+#define RT5665_PWR_LDO (0x1 << 8)
+#define RT5665_PWR_LDO_BIT 8
+#define RT5665_PWR_DAC_L2 (0x1 << 7)
+#define RT5665_PWR_DAC_L2_BIT 7
+#define RT5665_PWR_DAC_R2 (0x1 << 6)
+#define RT5665_PWR_DAC_R2_BIT 6
+#define RT5665_PWR_ADC_L1 (0x1 << 4)
+#define RT5665_PWR_ADC_L1_BIT 4
+#define RT5665_PWR_ADC_R1 (0x1 << 3)
+#define RT5665_PWR_ADC_R1_BIT 3
+#define RT5665_PWR_ADC_L2 (0x1 << 2)
+#define RT5665_PWR_ADC_L2_BIT 2
+#define RT5665_PWR_ADC_R2 (0x1 << 1)
+#define RT5665_PWR_ADC_R2_BIT 1
+
+/* Power Management for Digital 2 (0x0062) */
+#define RT5665_PWR_ADC_S1F (0x1 << 15)
+#define RT5665_PWR_ADC_S1F_BIT 15
+#define RT5665_PWR_ADC_S2F (0x1 << 14)
+#define RT5665_PWR_ADC_S2F_BIT 14
+#define RT5665_PWR_ADC_MF_L (0x1 << 13)
+#define RT5665_PWR_ADC_MF_L_BIT 13
+#define RT5665_PWR_ADC_MF_R (0x1 << 12)
+#define RT5665_PWR_ADC_MF_R_BIT 12
+#define RT5665_PWR_DAC_S2F (0x1 << 11)
+#define RT5665_PWR_DAC_S2F_BIT 11
+#define RT5665_PWR_DAC_S1F (0x1 << 10)
+#define RT5665_PWR_DAC_S1F_BIT 10
+#define RT5665_PWR_DAC_MF_L (0x1 << 9)
+#define RT5665_PWR_DAC_MF_L_BIT 9
+#define RT5665_PWR_DAC_MF_R (0x1 << 8)
+#define RT5665_PWR_DAC_MF_R_BIT 8
+#define RT5665_PWR_PDM1 (0x1 << 7)
+#define RT5665_PWR_PDM1_BIT 7
+
+/* Power Management for Analog 1 (0x0063) */
+#define RT5665_PWR_VREF1 (0x1 << 15)
+#define RT5665_PWR_VREF1_BIT 15
+#define RT5665_PWR_FV1 (0x1 << 14)
+#define RT5665_PWR_FV1_BIT 14
+#define RT5665_PWR_VREF2 (0x1 << 13)
+#define RT5665_PWR_VREF2_BIT 13
+#define RT5665_PWR_FV2 (0x1 << 12)
+#define RT5665_PWR_FV2_BIT 12
+#define RT5665_PWR_VREF3 (0x1 << 11)
+#define RT5665_PWR_VREF3_BIT 11
+#define RT5665_PWR_FV3 (0x1 << 10)
+#define RT5665_PWR_FV3_BIT 10
+#define RT5665_PWR_MB (0x1 << 9)
+#define RT5665_PWR_MB_BIT 9
+#define RT5665_PWR_LM (0x1 << 8)
+#define RT5665_PWR_LM_BIT 8
+#define RT5665_PWR_BG (0x1 << 7)
+#define RT5665_PWR_BG_BIT 7
+#define RT5665_PWR_MA (0x1 << 6)
+#define RT5665_PWR_MA_BIT 6
+#define RT5665_PWR_HA_L (0x1 << 5)
+#define RT5665_PWR_HA_L_BIT 5
+#define RT5665_PWR_HA_R (0x1 << 4)
+#define RT5665_PWR_HA_R_BIT 4
+#define RT5665_HP_DRIVER_MASK (0x3 << 2)
+#define RT5665_HP_DRIVER_1X (0x0 << 2)
+#define RT5665_HP_DRIVER_3X (0x1 << 2)
+#define RT5665_HP_DRIVER_5X (0x2 << 2)
+#define RT5665_LDO1_DVO_MASK (0x3)
+#define RT5665_LDO1_DVO_09 (0x0)
+#define RT5665_LDO1_DVO_10 (0x1)
+#define RT5665_LDO1_DVO_12 (0x2)
+#define RT5665_LDO1_DVO_14 (0x3)
+
+/* Power Management for Analog 2 (0x0064) */
+#define RT5665_PWR_BST1 (0x1 << 15)
+#define RT5665_PWR_BST1_BIT 15
+#define RT5665_PWR_BST2 (0x1 << 14)
+#define RT5665_PWR_BST2_BIT 14
+#define RT5665_PWR_BST3 (0x1 << 13)
+#define RT5665_PWR_BST3_BIT 13
+#define RT5665_PWR_BST4 (0x1 << 12)
+#define RT5665_PWR_BST4_BIT 12
+#define RT5665_PWR_MB1 (0x1 << 11)
+#define RT5665_PWR_MB1_PWR_DOWN (0x0 << 11)
+#define RT5665_PWR_MB1_BIT 11
+#define RT5665_PWR_MB2 (0x1 << 10)
+#define RT5665_PWR_MB2_PWR_DOWN (0x0 << 10)
+#define RT5665_PWR_MB2_BIT 10
+#define RT5665_PWR_MB3 (0x1 << 9)
+#define RT5665_PWR_MB3_BIT 9
+#define RT5665_PWR_BST1_P (0x1 << 7)
+#define RT5665_PWR_BST1_P_BIT 7
+#define RT5665_PWR_BST2_P (0x1 << 6)
+#define RT5665_PWR_BST2_P_BIT 6
+#define RT5665_PWR_BST3_P (0x1 << 5)
+#define RT5665_PWR_BST3_P_BIT 5
+#define RT5665_PWR_BST4_P (0x1 << 4)
+#define RT5665_PWR_BST4_P_BIT 4
+#define RT5665_PWR_JD1 (0x1 << 3)
+#define RT5665_PWR_JD1_BIT 3
+#define RT5665_PWR_JD2 (0x1 << 2)
+#define RT5665_PWR_JD2_BIT 2
+#define RT5665_PWR_RM1_L (0x1 << 1)
+#define RT5665_PWR_RM1_L_BIT 1
+#define RT5665_PWR_RM1_R (0x1)
+#define RT5665_PWR_RM1_R_BIT 0
+
+/* Power Management for Analog 3 (0x0065) */
+#define RT5665_PWR_CBJ (0x1 << 9)
+#define RT5665_PWR_CBJ_BIT 9
+#define RT5665_PWR_BST_L (0x1 << 8)
+#define RT5665_PWR_BST_L_BIT 8
+#define RT5665_PWR_BST_R (0x1 << 7)
+#define RT5665_PWR_BST_R_BIT 7
+#define RT5665_PWR_PLL (0x1 << 6)
+#define RT5665_PWR_PLL_BIT 6
+#define RT5665_PWR_LDO2 (0x1 << 2)
+#define RT5665_PWR_LDO2_BIT 2
+#define RT5665_PWR_SVD (0x1 << 1)
+#define RT5665_PWR_SVD_BIT 1
+
+/* Power Management for Mixer (0x0066) */
+#define RT5665_PWR_RM2_L (0x1 << 15)
+#define RT5665_PWR_RM2_L_BIT 15
+#define RT5665_PWR_RM2_R (0x1 << 14)
+#define RT5665_PWR_RM2_R_BIT 14
+#define RT5665_PWR_OM_L (0x1 << 13)
+#define RT5665_PWR_OM_L_BIT 13
+#define RT5665_PWR_OM_R (0x1 << 12)
+#define RT5665_PWR_OM_R_BIT 12
+#define RT5665_PWR_MM (0x1 << 11)
+#define RT5665_PWR_MM_BIT 11
+#define RT5665_PWR_AEC_REF (0x1 << 6)
+#define RT5665_PWR_AEC_REF_BIT 6
+#define RT5665_PWR_STO1_DAC_L (0x1 << 5)
+#define RT5665_PWR_STO1_DAC_L_BIT 5
+#define RT5665_PWR_STO1_DAC_R (0x1 << 4)
+#define RT5665_PWR_STO1_DAC_R_BIT 4
+#define RT5665_PWR_MONO_DAC_L (0x1 << 3)
+#define RT5665_PWR_MONO_DAC_L_BIT 3
+#define RT5665_PWR_MONO_DAC_R (0x1 << 2)
+#define RT5665_PWR_MONO_DAC_R_BIT 2
+#define RT5665_PWR_STO2_DAC_L (0x1 << 1)
+#define RT5665_PWR_STO2_DAC_L_BIT 1
+#define RT5665_PWR_STO2_DAC_R (0x1)
+#define RT5665_PWR_STO2_DAC_R_BIT 0
+
+/* Power Management for Volume (0x0067) */
+#define RT5665_PWR_OV_L (0x1 << 13)
+#define RT5665_PWR_OV_L_BIT 13
+#define RT5665_PWR_OV_R (0x1 << 12)
+#define RT5665_PWR_OV_R_BIT 12
+#define RT5665_PWR_IN_L (0x1 << 9)
+#define RT5665_PWR_IN_L_BIT 9
+#define RT5665_PWR_IN_R (0x1 << 8)
+#define RT5665_PWR_IN_R_BIT 8
+#define RT5665_PWR_MV (0x1 << 7)
+#define RT5665_PWR_MV_BIT 7
+#define RT5665_PWR_MIC_DET (0x1 << 5)
+#define RT5665_PWR_MIC_DET_BIT 5
+
+/* (0x006b) */
+#define RT5665_SYS_CLK_DET 15
+#define RT5665_HP_CLK_DET 14
+#define RT5665_MONO_CLK_DET 13
+#define RT5665_LOUT_CLK_DET 12
+#define RT5665_POW_CLK_DET 0
+
+/* Digital Microphone Control 1 (0x006e) */
+#define RT5665_DMIC_1_EN_MASK (0x1 << 15)
+#define RT5665_DMIC_1_EN_SFT 15
+#define RT5665_DMIC_1_DIS (0x0 << 15)
+#define RT5665_DMIC_1_EN (0x1 << 15)
+#define RT5665_DMIC_2_EN_MASK (0x1 << 14)
+#define RT5665_DMIC_2_EN_SFT 14
+#define RT5665_DMIC_2_DIS (0x0 << 14)
+#define RT5665_DMIC_2_EN (0x1 << 14)
+#define RT5665_DMIC_2_DP_MASK (0x1 << 9)
+#define RT5665_DMIC_2_DP_SFT 9
+#define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9)
+#define RT5665_DMIC_2_DP_IN2P (0x1 << 9)
+#define RT5665_DMIC_CLK_MASK (0x7 << 5)
+#define RT5665_DMIC_CLK_SFT 5
+#define RT5665_DMIC_1_DP_MASK (0x1 << 1)
+#define RT5665_DMIC_1_DP_SFT 1
+#define RT5665_DMIC_1_DP_GPIO4 (0x0 << 1)
+#define RT5665_DMIC_1_DP_IN2N (0x1 << 1)
+
+
+/* Digital Microphone Control 1 (0x006f) */
+#define RT5665_DMIC_2L_LH_MASK (0x1 << 3)
+#define RT5665_DMIC_2L_LH_SFT 3
+#define RT5665_DMIC_2L_LH_RISING (0x0 << 3)
+#define RT5665_DMIC_2L_LH_FALLING (0x1 << 3)
+#define RT5665_DMIC_2R_LH_MASK (0x1 << 2)
+#define RT5665_DMIC_2R_LH_SFT 2
+#define RT5665_DMIC_2R_LH_RISING (0x0 << 2)
+#define RT5665_DMIC_2R_LH_FALLING (0x1 << 2)
+#define RT5665_DMIC_1L_LH_MASK (0x1 << 1)
+#define RT5665_DMIC_1L_LH_SFT 1
+#define RT5665_DMIC_1L_LH_RISING (0x0 << 1)
+#define RT5665_DMIC_1L_LH_FALLING (0x1 << 1)
+#define RT5665_DMIC_1R_LH_MASK (0x1 << 0)
+#define RT5665_DMIC_1R_LH_SFT 0
+#define RT5665_DMIC_1R_LH_RISING (0x0)
+#define RT5665_DMIC_1R_LH_FALLING (0x1)
+
+/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
+#define RT5665_I2S_MS_MASK (0x1 << 15)
+#define RT5665_I2S_MS_SFT 15
+#define RT5665_I2S_MS_M (0x0 << 15)
+#define RT5665_I2S_MS_S (0x1 << 15)
+#define RT5665_I2S_PIN_CFG_MASK (0x1 << 14)
+#define RT5665_I2S_PIN_CFG_SFT 14
+#define RT5665_I2S_CLK_SEL_MASK (0x1 << 11)
+#define RT5665_I2S_CLK_SEL_SFT 11
+#define RT5665_I2S_BP_MASK (0x1 << 8)
+#define RT5665_I2S_BP_SFT 8
+#define RT5665_I2S_BP_NOR (0x0 << 8)
+#define RT5665_I2S_BP_INV (0x1 << 8)
+#define RT5665_I2S_DL_MASK (0x3 << 4)
+#define RT5665_I2S_DL_SFT 4
+#define RT5665_I2S_DL_16 (0x0 << 4)
+#define RT5665_I2S_DL_20 (0x1 << 4)
+#define RT5665_I2S_DL_24 (0x2 << 4)
+#define RT5665_I2S_DL_8 (0x3 << 4)
+#define RT5665_I2S_DF_MASK (0x7)
+#define RT5665_I2S_DF_SFT 0
+#define RT5665_I2S_DF_I2S (0x0)
+#define RT5665_I2S_DF_LEFT (0x1)
+#define RT5665_I2S_DF_PCM_A (0x2)
+#define RT5665_I2S_DF_PCM_B (0x3)
+#define RT5665_I2S_DF_PCM_A_N (0x6)
+#define RT5665_I2S_DF_PCM_B_N (0x7)
+
+/* ADC/DAC Clock Control 1 (0x0073) */
+#define RT5665_I2S_PD1_MASK (0x7 << 12)
+#define RT5665_I2S_PD1_SFT 12
+#define RT5665_I2S_PD1_1 (0x0 << 12)
+#define RT5665_I2S_PD1_2 (0x1 << 12)
+#define RT5665_I2S_PD1_3 (0x2 << 12)
+#define RT5665_I2S_PD1_4 (0x3 << 12)
+#define RT5665_I2S_PD1_6 (0x4 << 12)
+#define RT5665_I2S_PD1_8 (0x5 << 12)
+#define RT5665_I2S_PD1_12 (0x6 << 12)
+#define RT5665_I2S_PD1_16 (0x7 << 12)
+#define RT5665_I2S_M_PD2_MASK (0x7 << 8)
+#define RT5665_I2S_M_PD2_SFT 8
+#define RT5665_I2S_M_PD2_1 (0x0 << 8)
+#define RT5665_I2S_M_PD2_2 (0x1 << 8)
+#define RT5665_I2S_M_PD2_3 (0x2 << 8)
+#define RT5665_I2S_M_PD2_4 (0x3 << 8)
+#define RT5665_I2S_M_PD2_6 (0x4 << 8)
+#define RT5665_I2S_M_PD2_8 (0x5 << 8)
+#define RT5665_I2S_M_PD2_12 (0x6 << 8)
+#define RT5665_I2S_M_PD2_16 (0x7 << 8)
+#define RT5665_I2S_CLK_SRC_MASK (0x3 << 4)
+#define RT5665_I2S_CLK_SRC_SFT 4
+#define RT5665_I2S_CLK_SRC_MCLK (0x0 << 4)
+#define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4)
+#define RT5665_I2S_CLK_SRC_RCCLK (0x2 << 4)
+#define RT5665_DAC_OSR_MASK (0x3 << 2)
+#define RT5665_DAC_OSR_SFT 2
+#define RT5665_DAC_OSR_128 (0x0 << 2)
+#define RT5665_DAC_OSR_64 (0x1 << 2)
+#define RT5665_DAC_OSR_32 (0x2 << 2)
+#define RT5665_ADC_OSR_MASK (0x3)
+#define RT5665_ADC_OSR_SFT 0
+#define RT5665_ADC_OSR_128 (0x0)
+#define RT5665_ADC_OSR_64 (0x1)
+#define RT5665_ADC_OSR_32 (0x2)
+
+/* ADC/DAC Clock Control 2 (0x0074) */
+#define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
+#define RT5665_I2S_BCLK_MS2_SFT 15
+#define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)
+#define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
+#define RT5665_I2S_PD2_MASK (0x7 << 12)
+#define RT5665_I2S_PD2_SFT 12
+#define RT5665_I2S_PD2_1 (0x0 << 12)
+#define RT5665_I2S_PD2_2 (0x1 << 12)
+#define RT5665_I2S_PD2_3 (0x2 << 12)
+#define RT5665_I2S_PD2_4 (0x3 << 12)
+#define RT5665_I2S_PD2_6 (0x4 << 12)
+#define RT5665_I2S_PD2_8 (0x5 << 12)
+#define RT5665_I2S_PD2_12 (0x6 << 12)
+#define RT5665_I2S_PD2_16 (0x7 << 12)
+#define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11)
+#define RT5665_I2S_BCLK_MS3_SFT 11
+#define RT5665_I2S_BCLK_MS3_32 (0x0 << 11)
+#define RT5665_I2S_BCLK_MS3_64 (0x1 << 11)
+#define RT5665_I2S_PD3_MASK (0x7 << 8)
+#define RT5665_I2S_PD3_SFT 8
+#define RT5665_I2S_PD3_1 (0x0 << 8)
+#define RT5665_I2S_PD3_2 (0x1 << 8)
+#define RT5665_I2S_PD3_3 (0x2 << 8)
+#define RT5665_I2S_PD3_4 (0x3 << 8)
+#define RT5665_I2S_PD3_6 (0x4 << 8)
+#define RT5665_I2S_PD3_8 (0x5 << 8)
+#define RT5665_I2S_PD3_12 (0x6 << 8)
+#define RT5665_I2S_PD3_16 (0x7 << 8)
+#define RT5665_I2S_PD4_MASK (0x7 << 4)
+#define RT5665_I2S_PD4_SFT 4
+#define RT5665_I2S_PD4_1 (0x0 << 4)
+#define RT5665_I2S_PD4_2 (0x1 << 4)
+#define RT5665_I2S_PD4_3 (0x2 << 4)
+#define RT5665_I2S_PD4_4 (0x3 << 4)
+#define RT5665_I2S_PD4_6 (0x4 << 4)
+#define RT5665_I2S_PD4_8 (0x5 << 4)
+#define RT5665_I2S_PD4_12 (0x6 << 4)
+#define RT5665_I2S_PD4_16 (0x7 << 4)
+
+/* TDM control 1 (0x0078) */
+#define RT5665_I2S1_MODE_MASK (0x1 << 15)
+#define RT5665_I2S1_MODE_I2S (0x0 << 15)
+#define RT5665_I2S1_MODE_TDM (0x1 << 15)
+#define RT5665_TDM_IN_CH_MASK (0x3 << 10)
+#define RT5665_TDM_IN_CH_2 (0x0 << 10)
+#define RT5665_TDM_IN_CH_4 (0x1 << 10)
+#define RT5665_TDM_IN_CH_6 (0x2 << 10)
+#define RT5665_TDM_IN_CH_8 (0x3 << 10)
+#define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
+#define RT5665_TDM_OUT_CH_2 (0x0 << 8)
+#define RT5665_TDM_OUT_CH_4 (0x1 << 8)
+#define RT5665_TDM_OUT_CH_6 (0x2 << 8)
+#define RT5665_TDM_OUT_CH_8 (0x3 << 8)
+#define RT5665_TDM_IN_LEN_MASK (0x3 << 6)
+#define RT5665_TDM_IN_LEN_16 (0x0 << 6)
+#define RT5665_TDM_IN_LEN_20 (0x1 << 6)
+#define RT5665_TDM_IN_LEN_24 (0x2 << 6)
+#define RT5665_TDM_IN_LEN_32 (0x3 << 6)
+#define RT5665_TDM_OUT_LEN_MASK (0x3 << 4)
+#define RT5665_TDM_OUT_LEN_16 (0x0 << 4)
+#define RT5665_TDM_OUT_LEN_20 (0x1 << 4)
+#define RT5665_TDM_OUT_LEN_24 (0x2 << 4)
+#define RT5665_TDM_OUT_LEN_32 (0x3 << 4)
+
+
+/* TDM control 2 (0x0079) */
+#define RT5665_I2S1_1_DS_ADC_SLOT01_SFT 14
+#define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
+#define RT5665_I2S1_1_DS_ADC_SLOT45_SFT 10
+#define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
+#define RT5665_I2S1_2_DS_ADC_SLOT01_SFT 6
+#define RT5665_I2S1_2_DS_ADC_SLOT23_SFT 4
+#define RT5665_I2S1_2_DS_ADC_SLOT45_SFT 2
+#define RT5665_I2S1_2_DS_ADC_SLOT67_SFT 0
+
+/* TDM control 3/4 (0x007a) (0x007b) */
+#define RT5665_IF1_ADC1_SEL_SFT 10
+#define RT5665_IF1_ADC2_SEL_SFT 9
+#define RT5665_IF1_ADC3_SEL_SFT 8
+#define RT5665_IF1_ADC4_SEL_SFT 7
+#define RT5665_TDM_ADC_SEL_SFT 0
+#define RT5665_TDM_ADC_CTRL_MASK (0x1f << 0)
+#define RT5665_TDM_ADC_DATA_06 (0x6 << 0)
+
+/* Global Clock Control (0x0080) */
+#define RT5665_SCLK_SRC_MASK (0x3 << 14)
+#define RT5665_SCLK_SRC_SFT 14
+#define RT5665_SCLK_SRC_MCLK (0x0 << 14)
+#define RT5665_SCLK_SRC_PLL1 (0x1 << 14)
+#define RT5665_SCLK_SRC_RCCLK (0x2 << 14)
+#define RT5665_PLL1_SRC_MASK (0x7 << 8)
+#define RT5665_PLL1_SRC_SFT 8
+#define RT5665_PLL1_SRC_MCLK (0x0 << 8)
+#define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
+#define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
+#define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
+#define RT5665_PLL1_PD_MASK (0x7 << 4)
+#define RT5665_PLL1_PD_SFT 4
+
+
+#define RT5665_PLL_INP_MAX 40000000
+#define RT5665_PLL_INP_MIN 256000
+/* PLL M/N/K Code Control 1 (0x0081) */
+#define RT5665_PLL_N_MAX 0x001ff
+#define RT5665_PLL_N_MASK (RT5665_PLL_N_MAX << 7)
+#define RT5665_PLL_N_SFT 7
+#define RT5665_PLL_K_MAX 0x001f
+#define RT5665_PLL_K_MASK (RT5665_PLL_K_MAX)
+#define RT5665_PLL_K_SFT 0
+
+/* PLL M/N/K Code Control 2 (0x0082) */
+#define RT5665_PLL_M_MAX 0x00f
+#define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
+#define RT5665_PLL_M_SFT 12
+#define RT5665_PLL_M_BP (0x1 << 11)
+#define RT5665_PLL_M_BP_SFT 11
+#define RT5665_PLL_K_BP (0x1 << 10)
+#define RT5665_PLL_K_BP_SFT 10
+
+/* PLL tracking mode 1 (0x0083) */
+#define RT5665_I2S3_ASRC_MASK (0x1 << 15)
+#define RT5665_I2S3_ASRC_SFT 15
+#define RT5665_I2S2_ASRC_MASK (0x1 << 14)
+#define RT5665_I2S2_ASRC_SFT 14
+#define RT5665_I2S1_ASRC_MASK (0x1 << 13)
+#define RT5665_I2S1_ASRC_SFT 13
+#define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
+#define RT5665_DAC_STO1_ASRC_SFT 12
+#define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11)
+#define RT5665_DAC_STO2_ASRC_SFT 11
+#define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10)
+#define RT5665_DAC_MONO_L_ASRC_SFT 10
+#define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)
+#define RT5665_DAC_MONO_R_ASRC_SFT 9
+#define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
+#define RT5665_DMIC_STO1_ASRC_SFT 8
+#define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7)
+#define RT5665_DMIC_STO2_ASRC_SFT 7
+#define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6)
+#define RT5665_DMIC_MONO_L_ASRC_SFT 6
+#define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5)
+#define RT5665_DMIC_MONO_R_ASRC_SFT 5
+#define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4)
+#define RT5665_ADC_STO1_ASRC_SFT 4
+#define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3)
+#define RT5665_ADC_STO2_ASRC_SFT 3
+#define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2)
+#define RT5665_ADC_MONO_L_ASRC_SFT 2
+#define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1)
+#define RT5665_ADC_MONO_R_ASRC_SFT 1
+
+/* PLL tracking mode 2 (0x0084)*/
+#define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
+#define RT5665_DA_STO1_CLK_SEL_SFT 12
+#define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
+#define RT5665_DA_STO2_CLK_SEL_SFT 8
+#define RT5665_DA_MONOL_CLK_SEL_MASK (0x7 << 4)
+#define RT5665_DA_MONOL_CLK_SEL_SFT 4
+#define RT5665_DA_MONOR_CLK_SEL_MASK (0x7)
+#define RT5665_DA_MONOR_CLK_SEL_SFT 0
+
+/* PLL tracking mode 3 (0x0085)*/
+#define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
+#define RT5665_AD_STO1_CLK_SEL_SFT 12
+#define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
+#define RT5665_AD_STO2_CLK_SEL_SFT 8
+#define RT5665_AD_MONOL_CLK_SEL_MASK (0x7 << 4)
+#define RT5665_AD_MONOL_CLK_SEL_SFT 4
+#define RT5665_AD_MONOR_CLK_SEL_MASK (0x7)
+#define RT5665_AD_MONOR_CLK_SEL_SFT 0
+
+/* ASRC Control 4 (0x0086) */
+#define RT5665_I2S1_RATE_MASK (0xf << 12)
+#define RT5665_I2S1_RATE_SFT 12
+#define RT5665_I2S2_RATE_MASK (0xf << 8)
+#define RT5665_I2S2_RATE_SFT 8
+#define RT5665_I2S3_RATE_MASK (0xf << 4)
+#define RT5665_I2S3_RATE_SFT 4
+
+/* Depop Mode Control 1 (0x008e) */
+#define RT5665_PUMP_EN (0x1 << 3)
+
+/* Depop Mode Control 2 (0x8f) */
+#define RT5665_DEPOP_MASK (0x1 << 13)
+#define RT5665_DEPOP_SFT 13
+#define RT5665_DEPOP_AUTO (0x0 << 13)
+#define RT5665_DEPOP_MAN (0x1 << 13)
+#define RT5665_RAMP_MASK (0x1 << 12)
+#define RT5665_RAMP_SFT 12
+#define RT5665_RAMP_DIS (0x0 << 12)
+#define RT5665_RAMP_EN (0x1 << 12)
+#define RT5665_BPS_MASK (0x1 << 11)
+#define RT5665_BPS_SFT 11
+#define RT5665_BPS_DIS (0x0 << 11)
+#define RT5665_BPS_EN (0x1 << 11)
+#define RT5665_FAST_UPDN_MASK (0x1 << 10)
+#define RT5665_FAST_UPDN_SFT 10
+#define RT5665_FAST_UPDN_DIS (0x0 << 10)
+#define RT5665_FAST_UPDN_EN (0x1 << 10)
+#define RT5665_MRES_MASK (0x3 << 8)
+#define RT5665_MRES_SFT 8
+#define RT5665_MRES_15MO (0x0 << 8)
+#define RT5665_MRES_25MO (0x1 << 8)
+#define RT5665_MRES_35MO (0x2 << 8)
+#define RT5665_MRES_45MO (0x3 << 8)
+#define RT5665_VLO_MASK (0x1 << 7)
+#define RT5665_VLO_SFT 7
+#define RT5665_VLO_3V (0x0 << 7)
+#define RT5665_VLO_32V (0x1 << 7)
+#define RT5665_DIG_DP_MASK (0x1 << 6)
+#define RT5665_DIG_DP_SFT 6
+#define RT5665_DIG_DP_DIS (0x0 << 6)
+#define RT5665_DIG_DP_EN (0x1 << 6)
+#define RT5665_DP_TH_MASK (0x3 << 4)
+#define RT5665_DP_TH_SFT 4
+
+/* Depop Mode Control 3 (0x90) */
+#define RT5665_CP_SYS_MASK (0x7 << 12)
+#define RT5665_CP_SYS_SFT 12
+#define RT5665_CP_FQ1_MASK (0x7 << 8)
+#define RT5665_CP_FQ1_SFT 8
+#define RT5665_CP_FQ2_MASK (0x7 << 4)
+#define RT5665_CP_FQ2_SFT 4
+#define RT5665_CP_FQ3_MASK (0x7)
+#define RT5665_CP_FQ3_SFT 0
+#define RT5665_CP_FQ_1_5_KHZ 0
+#define RT5665_CP_FQ_3_KHZ 1
+#define RT5665_CP_FQ_6_KHZ 2
+#define RT5665_CP_FQ_12_KHZ 3
+#define RT5665_CP_FQ_24_KHZ 4
+#define RT5665_CP_FQ_48_KHZ 5
+#define RT5665_CP_FQ_96_KHZ 6
+#define RT5665_CP_FQ_192_KHZ 7
+
+/* HPOUT charge pump 1 (0x0091) */
+#define RT5665_OSW_L_MASK (0x1 << 11)
+#define RT5665_OSW_L_SFT 11
+#define RT5665_OSW_L_DIS (0x0 << 11)
+#define RT5665_OSW_L_EN (0x1 << 11)
+#define RT5665_OSW_R_MASK (0x1 << 10)
+#define RT5665_OSW_R_SFT 10
+#define RT5665_OSW_R_DIS (0x0 << 10)
+#define RT5665_OSW_R_EN (0x1 << 10)
+#define RT5665_PM_HP_MASK (0x3 << 8)
+#define RT5665_PM_HP_SFT 8
+#define RT5665_PM_HP_LV (0x0 << 8)
+#define RT5665_PM_HP_MV (0x1 << 8)
+#define RT5665_PM_HP_HV (0x2 << 8)
+#define RT5665_IB_HP_MASK (0x3 << 6)
+#define RT5665_IB_HP_SFT 6
+#define RT5665_IB_HP_125IL (0x0 << 6)
+#define RT5665_IB_HP_25IL (0x1 << 6)
+#define RT5665_IB_HP_5IL (0x2 << 6)
+#define RT5665_IB_HP_1IL (0x3 << 6)
+
+/* PV detection and SPK gain control (0x92) */
+#define RT5665_PVDD_DET_MASK (0x1 << 15)
+#define RT5665_PVDD_DET_SFT 15
+#define RT5665_PVDD_DET_DIS (0x0 << 15)
+#define RT5665_PVDD_DET_EN (0x1 << 15)
+#define RT5665_SPK_AG_MASK (0x1 << 14)
+#define RT5665_SPK_AG_SFT 14
+#define RT5665_SPK_AG_DIS (0x0 << 14)
+#define RT5665_SPK_AG_EN (0x1 << 14)
+
+/* Micbias Control1 (0x93) */
+#define RT5665_MIC1_BS_MASK (0x1 << 15)
+#define RT5665_MIC1_BS_SFT 15
+#define RT5665_MIC1_BS_9AV (0x0 << 15)
+#define RT5665_MIC1_BS_75AV (0x1 << 15)
+#define RT5665_MIC2_BS_MASK (0x1 << 14)
+#define RT5665_MIC2_BS_SFT 14
+#define RT5665_MIC2_BS_9AV (0x0 << 14)
+#define RT5665_MIC2_BS_75AV (0x1 << 14)
+#define RT5665_MIC1_CLK_MASK (0x1 << 13)
+#define RT5665_MIC1_CLK_SFT 13
+#define RT5665_MIC1_CLK_DIS (0x0 << 13)
+#define RT5665_MIC1_CLK_EN (0x1 << 13)
+#define RT5665_MIC2_CLK_MASK (0x1 << 12)
+#define RT5665_MIC2_CLK_SFT 12
+#define RT5665_MIC2_CLK_DIS (0x0 << 12)
+#define RT5665_MIC2_CLK_EN (0x1 << 12)
+#define RT5665_MIC1_OVCD_MASK (0x1 << 11)
+#define RT5665_MIC1_OVCD_SFT 11
+#define RT5665_MIC1_OVCD_DIS (0x0 << 11)
+#define RT5665_MIC1_OVCD_EN (0x1 << 11)
+#define RT5665_MIC1_OVTH_MASK (0x3 << 9)
+#define RT5665_MIC1_OVTH_SFT 9
+#define RT5665_MIC1_OVTH_600UA (0x0 << 9)
+#define RT5665_MIC1_OVTH_1500UA (0x1 << 9)
+#define RT5665_MIC1_OVTH_2000UA (0x2 << 9)
+#define RT5665_MIC2_OVCD_MASK (0x1 << 8)
+#define RT5665_MIC2_OVCD_SFT 8
+#define RT5665_MIC2_OVCD_DIS (0x0 << 8)
+#define RT5665_MIC2_OVCD_EN (0x1 << 8)
+#define RT5665_MIC2_OVTH_MASK (0x3 << 6)
+#define RT5665_MIC2_OVTH_SFT 6
+#define RT5665_MIC2_OVTH_600UA (0x0 << 6)
+#define RT5665_MIC2_OVTH_1500UA (0x1 << 6)
+#define RT5665_MIC2_OVTH_2000UA (0x2 << 6)
+#define RT5665_PWR_MB_MASK (0x1 << 5)
+#define RT5665_PWR_MB_SFT 5
+#define RT5665_PWR_MB_PD (0x0 << 5)
+#define RT5665_PWR_MB_PU (0x1 << 5)
+
+/* Micbias Control2 (0x94) */
+#define RT5665_PWR_CLK25M_MASK (0x1 << 9)
+#define RT5665_PWR_CLK25M_SFT 9
+#define RT5665_PWR_CLK25M_PD (0x0 << 9)
+#define RT5665_PWR_CLK25M_PU (0x1 << 9)
+#define RT5665_PWR_CLK1M_MASK (0x1 << 8)
+#define RT5665_PWR_CLK1M_SFT 8
+#define RT5665_PWR_CLK1M_PD (0x0 << 8)
+#define RT5665_PWR_CLK1M_PU (0x1 << 8)
+
+
+/* EQ Control 1 (0x00b0) */
+#define RT5665_EQ_SRC_DAC (0x0 << 15)
+#define RT5665_EQ_SRC_ADC (0x1 << 15)
+#define RT5665_EQ_UPD (0x1 << 14)
+#define RT5665_EQ_UPD_BIT 14
+#define RT5665_EQ_CD_MASK (0x1 << 13)
+#define RT5665_EQ_CD_SFT 13
+#define RT5665_EQ_CD_DIS (0x0 << 13)
+#define RT5665_EQ_CD_EN (0x1 << 13)
+#define RT5665_EQ_DITH_MASK (0x3 << 8)
+#define RT5665_EQ_DITH_SFT 8
+#define RT5665_EQ_DITH_NOR (0x0 << 8)
+#define RT5665_EQ_DITH_LSB (0x1 << 8)
+#define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
+#define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
+
+/* IRQ Control 1 (0x00b7) */
+#define RT5665_JD1_1_EN_MASK (0x1 << 15)
+#define RT5665_JD1_1_EN_SFT 15
+#define RT5665_JD1_1_DIS (0x0 << 15)
+#define RT5665_JD1_1_EN (0x1 << 15)
+#define RT5665_JD1_2_EN_MASK (0x1 << 12)
+#define RT5665_JD1_2_EN_SFT 12
+#define RT5665_JD1_2_DIS (0x0 << 12)
+#define RT5665_JD1_2_EN (0x1 << 12)
+
+/* IRQ Control 2 (0x00b8) */
+#define RT5665_IL_IRQ_MASK (0x1 << 6)
+#define RT5665_IL_IRQ_DIS (0x0 << 6)
+#define RT5665_IL_IRQ_EN (0x1 << 6)
+
+/* IRQ Control 5 (0x00ba) */
+#define RT5665_IRQ_JD_EN (0x1 << 3)
+#define RT5665_IRQ_JD_EN_SFT 3
+
+/* GPIO Control 1 (0x00c0) */
+#define RT5665_GP1_PIN_MASK (0x1 << 15)
+#define RT5665_GP1_PIN_SFT 15
+#define RT5665_GP1_PIN_GPIO1 (0x0 << 15)
+#define RT5665_GP1_PIN_IRQ (0x1 << 15)
+#define RT5665_GP2_PIN_MASK (0x3 << 13)
+#define RT5665_GP2_PIN_SFT 13
+#define RT5665_GP2_PIN_GPIO2 (0x0 << 13)
+#define RT5665_GP2_PIN_BCLK2 (0x1 << 13)
+#define RT5665_GP2_PIN_PDM_SCL (0x2 << 13)
+#define RT5665_GP3_PIN_MASK (0x3 << 11)
+#define RT5665_GP3_PIN_SFT 11
+#define RT5665_GP3_PIN_GPIO3 (0x0 << 11)
+#define RT5665_GP3_PIN_LRCK2 (0x1 << 11)
+#define RT5665_GP3_PIN_PDM_SDA (0x2 << 11)
+#define RT5665_GP4_PIN_MASK (0x3 << 9)
+#define RT5665_GP4_PIN_SFT 9
+#define RT5665_GP4_PIN_GPIO4 (0x0 << 9)
+#define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)
+#define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9)
+#define RT5665_GP5_PIN_MASK (0x3 << 7)
+#define RT5665_GP5_PIN_SFT 7
+#define RT5665_GP5_PIN_GPIO5 (0x0 << 7)
+#define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7)
+#define RT5665_GP5_PIN_DMIC2_SDA (0x2 << 7)
+#define RT5665_GP6_PIN_MASK (0x3 << 5)
+#define RT5665_GP6_PIN_SFT 5
+#define RT5665_GP6_PIN_GPIO6 (0x0 << 5)
+#define RT5665_GP6_PIN_BCLK3 (0x0 << 5)
+#define RT5665_GP6_PIN_PDM_SCL (0x1 << 5)
+#define RT5665_GP7_PIN_MASK (0x3 << 3)
+#define RT5665_GP7_PIN_SFT 3
+#define RT5665_GP7_PIN_GPIO7 (0x0 << 3)
+#define RT5665_GP7_PIN_LRCK3 (0x1 << 3)
+#define RT5665_GP7_PIN_PDM_SDA (0x2 << 3)
+#define RT5665_GP8_PIN_MASK (0x3 << 1)
+#define RT5665_GP8_PIN_SFT 1
+#define RT5665_GP8_PIN_GPIO8 (0x0 << 1)
+#define RT5665_GP8_PIN_DACDAT3 (0x1 << 1)
+#define RT5665_GP8_PIN_DMIC2_SCL (0x2 << 1)
+#define RT5665_GP8_PIN_DACDAT2_2 (0x3 << 1)
+
+
+/* GPIO Control 2 (0x00c1)*/
+#define RT5665_GP9_PIN_MASK (0x3 << 14)
+#define RT5665_GP9_PIN_SFT 14
+#define RT5665_GP9_PIN_GPIO9 (0x0 << 14)
+#define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14)
+#define RT5665_GP9_PIN_DMIC1_SCL (0x2 << 14)
+#define RT5665_GP9_PIN_ADCDAT2_2 (0x3 << 14)
+#define RT5665_GP10_PIN_MASK (0x3 << 12)
+#define RT5665_GP10_PIN_SFT 12
+#define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
+#define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
+#define RT5665_GP10_PIN_LPD (0x2 << 12)
+#define RT5665_GP1_PF_MASK (0x1 << 11)
+#define RT5665_GP1_PF_IN (0x0 << 11)
+#define RT5665_GP1_PF_OUT (0x1 << 11)
+#define RT5665_GP1_OUT_MASK (0x1 << 10)
+#define RT5665_GP1_OUT_H (0x0 << 10)
+#define RT5665_GP1_OUT_L (0x1 << 10)
+#define RT5665_GP2_PF_MASK (0x1 << 9)
+#define RT5665_GP2_PF_IN (0x0 << 9)
+#define RT5665_GP2_PF_OUT (0x1 << 9)
+#define RT5665_GP2_OUT_MASK (0x1 << 8)
+#define RT5665_GP2_OUT_H (0x0 << 8)
+#define RT5665_GP2_OUT_L (0x1 << 8)
+#define RT5665_GP3_PF_MASK (0x1 << 7)
+#define RT5665_GP3_PF_IN (0x0 << 7)
+#define RT5665_GP3_PF_OUT (0x1 << 7)
+#define RT5665_GP3_OUT_MASK (0x1 << 6)
+#define RT5665_GP3_OUT_H (0x0 << 6)
+#define RT5665_GP3_OUT_L (0x1 << 6)
+#define RT5665_GP4_PF_MASK (0x1 << 5)
+#define RT5665_GP4_PF_IN (0x0 << 5)
+#define RT5665_GP4_PF_OUT (0x1 << 5)
+#define RT5665_GP4_OUT_MASK (0x1 << 4)
+#define RT5665_GP4_OUT_H (0x0 << 4)
+#define RT5665_GP4_OUT_L (0x1 << 4)
+#define RT5665_GP5_PF_MASK (0x1 << 3)
+#define RT5665_GP5_PF_IN (0x0 << 3)
+#define RT5665_GP5_PF_OUT (0x1 << 3)
+#define RT5665_GP5_OUT_MASK (0x1 << 2)
+#define RT5665_GP5_OUT_H (0x0 << 2)
+#define RT5665_GP5_OUT_L (0x1 << 2)
+#define RT5665_GP6_PF_MASK (0x1 << 1)
+#define RT5665_GP6_PF_IN (0x0 << 1)
+#define RT5665_GP6_PF_OUT (0x1 << 1)
+#define RT5665_GP6_OUT_MASK (0x1)
+#define RT5665_GP6_OUT_H (0x0)
+#define RT5665_GP6_OUT_L (0x1)
+
+
+/* GPIO Control 3 (0x00c2) */
+#define RT5665_GP7_PF_MASK (0x1 << 15)
+#define RT5665_GP7_PF_IN (0x0 << 15)
+#define RT5665_GP7_PF_OUT (0x1 << 15)
+#define RT5665_GP7_OUT_MASK (0x1 << 14)
+#define RT5665_GP7_OUT_H (0x0 << 14)
+#define RT5665_GP7_OUT_L (0x1 << 14)
+#define RT5665_GP8_PF_MASK (0x1 << 13)
+#define RT5665_GP8_PF_IN (0x0 << 13)
+#define RT5665_GP8_PF_OUT (0x1 << 13)
+#define RT5665_GP8_OUT_MASK (0x1 << 12)
+#define RT5665_GP8_OUT_H (0x0 << 12)
+#define RT5665_GP8_OUT_L (0x1 << 12)
+#define RT5665_GP9_PF_MASK (0x1 << 11)
+#define RT5665_GP9_PF_IN (0x0 << 11)
+#define RT5665_GP9_PF_OUT (0x1 << 11)
+#define RT5665_GP9_OUT_MASK (0x1 << 10)
+#define RT5665_GP9_OUT_H (0x0 << 10)
+#define RT5665_GP9_OUT_L (0x1 << 10)
+#define RT5665_GP10_PF_MASK (0x1 << 9)
+#define RT5665_GP10_PF_IN (0x0 << 9)
+#define RT5665_GP10_PF_OUT (0x1 << 9)
+#define RT5665_GP10_OUT_MASK (0x1 << 8)
+#define RT5665_GP10_OUT_H (0x0 << 8)
+#define RT5665_GP10_OUT_L (0x1 << 8)
+#define RT5665_GP11_PF_MASK (0x1 << 7)
+#define RT5665_GP11_PF_IN (0x0 << 7)
+#define RT5665_GP11_PF_OUT (0x1 << 7)
+#define RT5665_GP11_OUT_MASK (0x1 << 6)
+#define RT5665_GP11_OUT_H (0x0 << 6)
+#define RT5665_GP11_OUT_L (0x1 << 6)
+
+/* Soft volume and zero cross control 1 (0x00d9) */
+#define RT5665_SV_MASK (0x1 << 15)
+#define RT5665_SV_SFT 15
+#define RT5665_SV_DIS (0x0 << 15)
+#define RT5665_SV_EN (0x1 << 15)
+#define RT5665_OUT_SV_MASK (0x1 << 13)
+#define RT5665_OUT_SV_SFT 13
+#define RT5665_OUT_SV_DIS (0x0 << 13)
+#define RT5665_OUT_SV_EN (0x1 << 13)
+#define RT5665_HP_SV_MASK (0x1 << 12)
+#define RT5665_HP_SV_SFT 12
+#define RT5665_HP_SV_DIS (0x0 << 12)
+#define RT5665_HP_SV_EN (0x1 << 12)
+#define RT5665_ZCD_DIG_MASK (0x1 << 11)
+#define RT5665_ZCD_DIG_SFT 11
+#define RT5665_ZCD_DIG_DIS (0x0 << 11)
+#define RT5665_ZCD_DIG_EN (0x1 << 11)
+#define RT5665_ZCD_MASK (0x1 << 10)
+#define RT5665_ZCD_SFT 10
+#define RT5665_ZCD_PD (0x0 << 10)
+#define RT5665_ZCD_PU (0x1 << 10)
+#define RT5665_SV_DLY_MASK (0xf)
+#define RT5665_SV_DLY_SFT 0
+
+/* Soft volume and zero cross control 2 (0x00da) */
+#define RT5665_ZCD_HP_MASK (0x1 << 15)
+#define RT5665_ZCD_HP_SFT 15
+#define RT5665_ZCD_HP_DIS (0x0 << 15)
+#define RT5665_ZCD_HP_EN (0x1 << 15)
+
+/* 4 Button Inline Command Control 2 (0x00e0) */
+#define RT5665_4BTN_IL_MASK (0x1 << 15)
+#define RT5665_4BTN_IL_EN (0x1 << 15)
+#define RT5665_4BTN_IL_DIS (0x0 << 15)
+#define RT5665_4BTN_IL_RST_MASK (0x1 << 14)
+#define RT5665_4BTN_IL_NOR (0x1 << 14)
+#define RT5665_4BTN_IL_RST (0x0 << 14)
+
+/* Analog JD Control 1 (0x00f0) */
+#define RT5665_JD1_MODE_MASK (0x3 << 0)
+#define RT5665_JD1_MODE_0 (0x0 << 0)
+#define RT5665_JD1_MODE_1 (0x1 << 0)
+#define RT5665_JD1_MODE_2 (0x2 << 0)
+
+/* Jack Detect Control 3 (0x00f8) */
+#define RT5665_JD_TRI_HPO_SEL_MASK (0x7)
+#define RT5665_JD_TRI_HPO_SEL_SFT (0)
+#define RT5665_JD_HPO_GPIO_JD1 (0x0)
+#define RT5665_JD_HPO_JD1_1 (0x1)
+#define RT5665_JD_HPO_JD1_2 (0x2)
+#define RT5665_JD_HPO_JD2 (0x3)
+#define RT5665_JD_HPO_GPIO_JD2 (0x4)
+#define RT5665_JD_HPO_JD3 (0x5)
+#define RT5665_JD_HPO_JD_D (0x6)
+
+/* Digital Misc Control (0x00fa) */
+#define RT5665_AM_MASK (0x1 << 7)
+#define RT5665_AM_EN (0x1 << 7)
+#define RT5665_AM_DIS (0x1 << 7)
+#define RT5665_DIG_GATE_CTRL 0x1
+#define RT5665_DIG_GATE_CTRL_SFT (0)
+
+/* Chopper and Clock control for ADC (0x011c)*/
+#define RT5665_M_RF_DIG_MASK (0x1 << 12)
+#define RT5665_M_RF_DIG_SFT 12
+#define RT5665_M_RI_DIG (0x1 << 11)
+
+/* Chopper and Clock control for DAC (0x013a)*/
+#define RT5665_CKXEN_DAC1_MASK (0x1 << 13)
+#define RT5665_CKXEN_DAC1_SFT 13
+#define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
+#define RT5665_CKGEN_DAC1_SFT 12
+#define RT5665_CKXEN_DAC2_MASK (0x1 << 5)
+#define RT5665_CKXEN_DAC2_SFT 5
+#define RT5665_CKGEN_DAC2_MASK (0x1 << 4)
+#define RT5665_CKGEN_DAC2_SFT 4
+
+/* Chopper and Clock control for ADC (0x013b)*/
+#define RT5665_CKXEN_ADC1_MASK (0x1 << 13)
+#define RT5665_CKXEN_ADC1_SFT 13
+#define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
+#define RT5665_CKGEN_ADC1_SFT 12
+#define RT5665_CKXEN_ADC2_MASK (0x1 << 5)
+#define RT5665_CKXEN_ADC2_SFT 5
+#define RT5665_CKGEN_ADC2_MASK (0x1 << 4)
+#define RT5665_CKGEN_ADC2_SFT 4
+
+/* Volume test (0x013f)*/
+#define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
+#define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
+#define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)
+
+/* Test Mode Control 1 (0x0145) */
+#define RT5665_AD2DA_LB_MASK (0x1 << 9)
+#define RT5665_AD2DA_LB_SFT 9
+
+/* Stereo Noise Gate Control 1 (0x0160) */
+#define RT5665_NG2_EN_MASK (0x1 << 15)
+#define RT5665_NG2_EN (0x1 << 15)
+#define RT5665_NG2_DIS (0x0 << 15)
+
+/* Stereo1 DAC Silence Detection Control (0x0190) */
+#define RT5665_DEB_STO_DAC_MASK (0x7 << 4)
+#define RT5665_DEB_80_MS (0x0 << 4)
+
+/* SAR ADC Inline Command Control 1 (0x0210) */
+#define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
+#define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
+#define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)
+#define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14)
+#define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14)
+#define RT5665_SAR_BUTDET_POW_NORM (0x0 << 14)
+#define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)
+#define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)
+#define RT5665_SAR_BUTDET_RST (0x0 << 13)
+#define RT5665_SAR_POW_MASK (0x1 << 12)
+#define RT5665_SAR_POW_EN (0x1 << 12)
+#define RT5665_SAR_POW_DIS (0x0 << 12)
+#define RT5665_SAR_RST_MASK (0x1 << 11)
+#define RT5665_SAR_RST_NORMAL (0x1 << 11)
+#define RT5665_SAR_RST (0x0 << 11)
+#define RT5665_SAR_BYPASS_MASK (0x1 << 10)
+#define RT5665_SAR_BYPASS_EN (0x1 << 10)
+#define RT5665_SAR_BYPASS_DIS (0x0 << 10)
+#define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)
+#define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)
+#define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9)
+#define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
+#define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
+#define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)
+#define RT5665_SAR_SEL_MODE_MASK (0x1 << 7)
+#define RT5665_SAR_SEL_MODE_CMP (0x1 << 7)
+#define RT5665_SAR_SEL_MODE_ADC (0x0 << 7)
+#define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
+#define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
+#define RT5665_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
+#define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4)
+#define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
+#define RT5665_SAR_SEL_SIGNAL_MANU (0x0 << 4)
+
+/* System Clock Source */
+enum {
+ RT5665_SCLK_S_MCLK,
+ RT5665_SCLK_S_PLL1,
+ RT5665_SCLK_S_RCCLK,
+};
+
+/* PLL1 Source */
+enum {
+ RT5665_PLL1_S_MCLK,
+ RT5665_PLL1_S_BCLK1,
+ RT5665_PLL1_S_BCLK2,
+ RT5665_PLL1_S_BCLK3,
+ RT5665_PLL1_S_BCLK4,
+};
+
+enum {
+ RT5665_AIF1_1,
+ RT5665_AIF1_2,
+ RT5665_AIF2_1,
+ RT5665_AIF2_2,
+ RT5665_AIF3,
+ RT5665_AIFS
+};
+
+enum {
+ CODEC_5665,
+ CODEC_5666,
+ CODEC_5668,
+};
+
+/* filter mask */
+enum {
+ RT5665_DA_STEREO1_FILTER = 0x1,
+ RT5665_DA_STEREO2_FILTER = (0x1 << 1),
+ RT5665_DA_MONO_L_FILTER = (0x1 << 2),
+ RT5665_DA_MONO_R_FILTER = (0x1 << 3),
+ RT5665_AD_STEREO1_FILTER = (0x1 << 4),
+ RT5665_AD_STEREO2_FILTER = (0x1 << 5),
+ RT5665_AD_MONO_L_FILTER = (0x1 << 6),
+ RT5665_AD_MONO_R_FILTER = (0x1 << 7),
+};
+
+enum {
+ RT5665_CLK_SEL_SYS,
+ RT5665_CLK_SEL_I2S1_ASRC,
+ RT5665_CLK_SEL_I2S2_ASRC,
+ RT5665_CLK_SEL_I2S3_ASRC,
+ RT5665_CLK_SEL_SYS2,
+ RT5665_CLK_SEL_SYS3,
+ RT5665_CLK_SEL_SYS4,
+};
+
+int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
+ unsigned int filter_mask, unsigned int clk_src);
+int rt5665_set_jack_detect(struct snd_soc_codec *codec,
+ struct snd_soc_jack *hs_jack);
+
+#endif /* __RT5665_H__ */
--
cgit v1.2.3
From c821d30148caab01f2559980ed322667e2919b99 Mon Sep 17 00:00:00 2001
From: Peter Rosin <peda@axentia.se>
Date: Tue, 15 Nov 2016 19:38:14 +0100
Subject: ASoC: tse850: document axentia,tse850-pcm5142 bindings
The TSE-850 is an FM Transmitter Station Equipment, designed to generate
baseband signals for FM, mainly the DARC subcarrier, but other signals
are also possible.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../bindings/sound/axentia,tse850-pcm5142.txt | 88 ++++++++++++++++++++++
MAINTAINERS | 6 ++
2 files changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt
new file mode 100644
index 000000000000..5b9b38f578bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt
@@ -0,0 +1,88 @@
+Devicetree bindings for the Axentia TSE-850 audio complex
+
+Required properties:
+ - compatible: "axentia,tse850-pcm5142"
+ - axentia,ssc-controller: The phandle of the atmel SSC controller used as
+ cpu dai.
+ - axentia,audio-codec: The phandle of the PCM5142 codec.
+ - axentia,add-gpios: gpio specifier that controls the mixer.
+ - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1.
+ - axentia,loop2-gpios: gpio specifier that controls loop relays on channel 2.
+ - axentia,ana-supply: Regulator that supplies the output amplifier. Must
+ support voltages in the 2V - 20V range, in 1V steps.
+
+The schematics explaining the gpios are as follows:
+
+ loop1 relays
+ IN1 +---o +------------+ o---+ OUT1
+ \ /
+ + +
+ | / |
+ +--o +--. |
+ | add | |
+ | V |
+ | .---. |
+ DAC +----------->|Sum|---+
+ | '---' |
+ | |
+ + +
+
+ IN2 +---o--+------------+--o---+ OUT2
+ loop2 relays
+
+The 'loop1' gpio pin controlls two relays, which are either in loop position,
+meaning that input and output are directly connected, or they are in mixer
+position, meaning that the signal is passed through the 'Sum' mixer. Similarly
+for 'loop2'.
+
+In the above, the 'loop1' relays are inactive, thus feeding IN1 to the mixer
+(if 'add' is active) and feeding the mixer output to OUT1. The 'loop2' relays
+are active, short-cutting the TSE-850 from channel 2. IN1, IN2, OUT1 and OUT2
+are TSE-850 connectors and DAC is the PCB name of the (filtered) output from
+the PCM5142 codec.
+
+Example:
+
+ &i2c {
+ codec: pcm5142@4c {
+ compatible = "ti,pcm5142";
+
+ reg = <0x4c>;
+
+ AVDD-supply = <®_3v3>;
+ DVDD-supply = <®_3v3>;
+ CPVDD-supply = <®_3v3>;
+
+ clocks = <&sck>;
+
+ pll-in = <3>;
+ pll-out = <6>;
+ };
+ };
+
+ ana: ana-reg {
+ compatible = "pwm-regulator";
+
+ regulator-name = "ANA";
+
+ pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>;
+ pwm-dutycycle-unit = <1000>;
+ pwm-dutycycle-range = <100 1000>;
+
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <20000000>;
+ regulator-ramp-delay = <1000>;
+ };
+
+ sound {
+ compatible = "axentia,tse850-pcm5142";
+
+ axentia,ssc-controller = <&ssc0>;
+ axentia,audio-codec = <&codec>;
+
+ axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>;
+ axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
+ axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>;
+
+ axentia,ana-supply = <&ana>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7e0064..35485fd86e73 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2317,6 +2317,12 @@ F: include/uapi/linux/ax25.h
F: include/net/ax25.h
F: net/ax25/
+AXENTIA ASOC DRIVERS
+M: Peter Rosin <peda@axentia.se>
+L: alsa-devel@alsa-project.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/sound/axentia,*
+
AZ6007 DVB DRIVER
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
M: Mauro Carvalho Chehab <mchehab@kernel.org>
--
cgit v1.2.3
From 1c8018f7a7a60a649260fdd7e8645a356299e920 Mon Sep 17 00:00:00 2001
From: Cédric Le Goater <clg@kaod.org>
Date: Wed, 2 Nov 2016 08:57:04 +0100
Subject: ipmi/bt-bmc: change compatible node to 'aspeed, ast2400-ibt-bmc'
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The Aspeed SoCs have two BT interfaces : one is IPMI compliant and the
other is H8S/2168 compliant.
The current ipmi/bt-bmc driver implements the IPMI version and we
should reflect its nature in the compatible node name using
'aspeed,ast2400-ibt-bmc' instead of 'aspeed,ast2400-bt-bmc'. The
latter should be used for a H8S interface driver if it is implemented
one day.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
---
.../bindings/ipmi/aspeed,ast2400-bt-bmc.txt | 23 ----------------------
.../bindings/ipmi/aspeed,ast2400-ibt-bmc.txt | 23 ++++++++++++++++++++++
drivers/char/ipmi/bt-bmc.c | 4 ++--
3 files changed, 25 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt
create mode 100644 Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt
deleted file mode 100644
index fbbacd958240..000000000000
--- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Aspeed BT (Block Transfer) IPMI interface
-
-The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
-(BaseBoard Management Controllers) and the BT interface can be used to
-perform in-band IPMI communication with their host.
-
-Required properties:
-
-- compatible : should be "aspeed,ast2400-bt-bmc"
-- reg: physical address and size of the registers
-
-Optional properties:
-
-- interrupts: interrupt generated by the BT interface. without an
- interrupt, the driver will operate in poll mode.
-
-Example:
-
- ibt@1e789140 {
- compatible = "aspeed,ast2400-bt-bmc";
- reg = <0x1e789140 0x18>;
- interrupts = <8>;
- };
diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt
new file mode 100644
index 000000000000..6f28969af9dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt
@@ -0,0 +1,23 @@
+* Aspeed BT (Block Transfer) IPMI interface
+
+The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
+(BaseBoard Management Controllers) and the BT interface can be used to
+perform in-band IPMI communication with their host.
+
+Required properties:
+
+- compatible : should be "aspeed,ast2400-ibt-bmc"
+- reg: physical address and size of the registers
+
+Optional properties:
+
+- interrupts: interrupt generated by the BT interface. without an
+ interrupt, the driver will operate in poll mode.
+
+Example:
+
+ ibt@1e789140 {
+ compatible = "aspeed,ast2400-ibt-bmc";
+ reg = <0x1e789140 0x18>;
+ interrupts = <8>;
+ };
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
index b49e61320952..fc9e8891eae3 100644
--- a/drivers/char/ipmi/bt-bmc.c
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -484,7 +484,7 @@ static int bt_bmc_remove(struct platform_device *pdev)
}
static const struct of_device_id bt_bmc_match[] = {
- { .compatible = "aspeed,ast2400-bt-bmc" },
+ { .compatible = "aspeed,ast2400-ibt-bmc" },
{ },
};
@@ -502,4 +502,4 @@ module_platform_driver(bt_bmc_driver);
MODULE_DEVICE_TABLE(of, bt_bmc_match);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>");
-MODULE_DESCRIPTION("Linux device interface to the BT interface");
+MODULE_DESCRIPTION("Linux device interface to the IPMI BT interface");
--
cgit v1.2.3
From 837e71847aefd82c903ee0bb2ff2589e70b0808f Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sat, 12 Nov 2016 14:46:39 +0800
Subject: ASoC: sunxi: Add bindings for A23/A33/H3 codec's analog path controls
The internal codec on A23/A33/H3 is split into 2 parts. The
analog path controls are routed through an embedded custom register
bus accessed through the PRCM block.
The SoCs share a common set of inputs, outputs, and audio paths.
The following table lists the differences.
----------------------------------------
| Feature \ SoC | A23 | A33 | H3 |
----------------------------------------
| Headphone | v | v | |
----------------------------------------
| Line Out | | | v |
----------------------------------------
| Phone In/Out | v | v | |
----------------------------------------
Add a binding for this hardware.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/sun8i-codec-analog.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
new file mode 100644
index 000000000000..779b735781ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
@@ -0,0 +1,16 @@
+* Allwinner Codec Analog Controls
+
+Required properties:
+- compatible: must be one of the following compatibles:
+ - "allwinner,sun8i-a23-codec-analog"
+ - "allwinner,sun8i-h3-codec-analog"
+
+Required properties if not a sub-node of the PRCM node:
+- reg: must contain the registers location and length
+
+Example:
+prcm: prcm@01f01400 {
+ codec_analog: codec-analog {
+ compatible = "allwinner,sun8i-a23-codec-analog";
+ };
+};
--
cgit v1.2.3
From e5f3a4a56ce2a707b2fb8ce37e4414dcac89c672 Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Fri, 25 Nov 2016 14:12:00 +0100
Subject: Documentation: devicetree: clarify usage of the RGMII phy-modes
RGMII requires special RX and/or TX delays depending on the actual
hardware circuit/wiring. These delays can be added by the MAC, the PHY
or the designer of the circuit (the latter means that no delay has to
be added by PHY or MAC).
There are 4 RGMII phy-modes used describe where a delay should be
applied:
- rgmii: the RX and TX delays are either added by the MAC (where the
exact delay is typically configurable, and can be turned off when no
extra delay is needed) or not needed at all (because the hardware
wiring adds the delay already). The PHY should neither add the RX nor
TX delay in this case.
- rgmii-rxid: configures the PHY to enable the RX delay. The MAC should
not add the RX delay in this case.
- rgmii-txid: configures the PHY to enable the TX delay. The MAC should
not add the TX delay in this case.
- rgmii-id: combines rgmii-rxid and rgmii-txid and thus configures the
PHY to enable the RX and TX delays. The MAC should neither add the RX
nor TX delay in this case.
Document these cases in the ethernet.txt documentation to make it clear
when to use each mode.
If applied incorrectly one might end up with MAC and PHY both enabling
for example the TX delay, which breaks ethernet TX traffic on 1000Mbit/s
links.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
Documentation/devicetree/bindings/net/ethernet.txt | 24 ++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
index e1d76812419c..05150957ecfd 100644
--- a/Documentation/devicetree/bindings/net/ethernet.txt
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -9,10 +9,26 @@ The following properties are common to the Ethernet controllers:
- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
the maximum frame size (there's contradiction in ePAPR).
-- phy-mode: string, operation mode of the PHY interface; supported values are
- "mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id",
- "rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii", "trgmii"; this is now a
- de-facto standard property;
+- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
+ standard property; supported values are:
+ * "mii"
+ * "gmii"
+ * "sgmii"
+ * "qsgmii"
+ * "tbi"
+ * "rev-mii"
+ * "rmii"
+ * "rgmii" (RX and TX delays are added by the MAC when required)
+ * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
+ MAC should not add the RX or TX delays in this case)
+ * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
+ should not add an RX delay in this case)
+ * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
+ should not add an TX delay in this case)
+ * "rtbi"
+ * "smii"
+ * "xgmii"
+ * "trgmii"
- phy-connection-type: the same as "phy-mode" property but described in ePAPR;
- phy-handle: phandle, specifies a reference to a node representing a PHY
device; this property is described in ePAPR and so preferred;
--
cgit v1.2.3
From dac5f86bc9e60eae87a28512f025362d1e2574e3 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 25 Nov 2016 20:34:36 +0800
Subject: ASoC: sun4i-codec: Add support for A23 codec
The codec in the A23 is similar to the one found on the A31. One key
difference is the analog path controls are routed through the PRCM
block. This is supported by the sun8i-codec-analog driver, and tied
into this codec driver with the audio card's aux_dev.
In addition, the A23 does not have LINEOUT, and it does not support
headset jack detection or buttons.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/sun4i-codec.txt | 11 ++-
sound/soc/sunxi/sun4i-codec.c | 108 +++++++++++++++++++++
2 files changed, 117 insertions(+), 2 deletions(-)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
index d91a95377f49..f7a548b604fc 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
@@ -5,6 +5,7 @@ Required properties:
- "allwinner,sun4i-a10-codec"
- "allwinner,sun6i-a31-codec"
- "allwinner,sun7i-a20-codec"
+ - "allwinner,sun8i-a23-codec"
- reg: must contain the registers location and length
- interrupts: must contain the codec interrupt
- dmas: DMA channels for tx and rx dma. See the DMA client binding,
@@ -21,6 +22,7 @@ Optional properties:
Required properties for the following compatibles:
- "allwinner,sun6i-a31-codec"
+ - "allwinner,sun8i-a23-codec"
- resets: phandle to the reset control for this device
- allwinner,audio-routing: A list of the connections between audio components.
Each entry is a pair of strings, the first being the
@@ -31,10 +33,10 @@ Required properties for the following compatibles:
"HP"
"HPCOM"
"LINEIN"
- "LINEOUT"
+ "LINEOUT" (not on sun8i-a23)
"MIC1"
"MIC2"
- "MIC3"
+ "MIC3" (sun6i-a31 only)
Microphone biases from the SoC:
"HBIAS"
@@ -48,6 +50,11 @@ Required properties for the following compatibles:
"Mic"
"Speaker"
+Required properties for the following compatibles:
+ - "allwinner,sun8i-a23-codec"
+- allwinner,codec-analog-controls: A phandle to the codec analog controls
+ block in the PRCM.
+
Example:
codec: codec@01c22c00 {
#sound-dai-cells = <0>;
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index 092fdcf6de95..ada5fa055950 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -213,6 +213,10 @@
/* TODO sun6i DAP (Digital Audio Processing) bits */
+/* FIFO counters moved on A23 */
+#define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
+#define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
+
struct sun4i_codec {
struct device *dev;
struct regmap *regmap;
@@ -1067,6 +1071,32 @@ static struct snd_soc_codec_driver sun6i_codec_codec = {
},
};
+/* sun8i A23 codec */
+static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = {
+ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
+ sun6i_codec_dvol_scale),
+};
+
+static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = {
+ /* Digital parts of the ADCs */
+ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
+ SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
+ /* Digital parts of the DACs */
+ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
+ SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
+
+};
+
+static struct snd_soc_codec_driver sun8i_a23_codec_codec = {
+ .component_driver = {
+ .controls = sun8i_a23_codec_codec_controls,
+ .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls),
+ .dapm_widgets = sun8i_a23_codec_codec_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets),
+ },
+};
+
static const struct snd_soc_component_driver sun4i_codec_component = {
.name = "sun4i-codec",
};
@@ -1206,6 +1236,63 @@ static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
return card;
};
+/* Connect digital side enables to analog side widgets */
+static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
+ /* ADC Routes */
+ { "Left ADC", NULL, "ADC Enable" },
+ { "Right ADC", NULL, "ADC Enable" },
+ { "Codec Capture", NULL, "Left ADC" },
+ { "Codec Capture", NULL, "Right ADC" },
+
+ /* DAC Routes */
+ { "Left DAC", NULL, "DAC Enable" },
+ { "Right DAC", NULL, "DAC Enable" },
+ { "Left DAC", NULL, "Codec Playback" },
+ { "Right DAC", NULL, "Codec Playback" },
+};
+
+static struct snd_soc_aux_dev aux_dev = {
+ .name = "Codec Analog Controls",
+};
+
+static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+ int ret;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
+ "allwinner,codec-analog-controls",
+ 0);
+ if (!aux_dev.codec_of_node) {
+ dev_err(dev, "Can't find analog controls for codec.\n");
+ return ERR_PTR(-EINVAL);
+ };
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->name = "A23 Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->dapm_routes = sun8i_codec_card_routes;
+ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
+ card->aux_dev = &aux_dev;
+ card->num_aux_devs = 1;
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+ return card;
+};
+
static const struct regmap_config sun4i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -1227,6 +1314,13 @@ static const struct regmap_config sun7i_codec_regmap_config = {
.max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
};
+static const struct regmap_config sun8i_a23_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_A23_CODEC_ADC_RXCNT,
+};
+
struct sun4i_codec_quirks {
const struct regmap_config *regmap_config;
const struct snd_soc_codec_driver *codec;
@@ -1265,6 +1359,16 @@ static const struct sun4i_codec_quirks sun7i_codec_quirks = {
.reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
};
+static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
+ .regmap_config = &sun8i_a23_codec_regmap_config,
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_a23_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
static const struct of_device_id sun4i_codec_of_match[] = {
{
.compatible = "allwinner,sun4i-a10-codec",
@@ -1278,6 +1382,10 @@ static const struct of_device_id sun4i_codec_of_match[] = {
.compatible = "allwinner,sun7i-a20-codec",
.data = &sun7i_codec_quirks,
},
+ {
+ .compatible = "allwinner,sun8i-a23-codec",
+ .data = &sun8i_a23_codec_quirks,
+ },
{}
};
MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
--
cgit v1.2.3
From 4a15b24a65f13778f7616ad0a65be78d8ec0b45a Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 25 Nov 2016 20:34:40 +0800
Subject: ASoC: sun4i-codec: Add support for H3 codec
The codec on the H3 is similar to the one found on the A31. One key
difference is the analog path controls are routed through the PRCM
block. This is supported by the sun8i-codec-analog driver, and tied
into this codec driver with the audio card's aux_dev.
In addition, the H3 has no HP (headphone) and HBIAS support, and no
MIC3 input. The FIFO related registers are slightly rearranged.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/sun4i-codec.txt | 3 +
sound/soc/sunxi/sun4i-codec.c | 71 ++++++++++++++++++++++
2 files changed, 74 insertions(+)
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
index f7a548b604fc..3033bd8aab0f 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
@@ -6,6 +6,7 @@ Required properties:
- "allwinner,sun6i-a31-codec"
- "allwinner,sun7i-a20-codec"
- "allwinner,sun8i-a23-codec"
+ - "allwinner,sun8i-h3-codec"
- reg: must contain the registers location and length
- interrupts: must contain the codec interrupt
- dmas: DMA channels for tx and rx dma. See the DMA client binding,
@@ -23,6 +24,7 @@ Optional properties:
Required properties for the following compatibles:
- "allwinner,sun6i-a31-codec"
- "allwinner,sun8i-a23-codec"
+ - "allwinner,sun8i-h3-codec"
- resets: phandle to the reset control for this device
- allwinner,audio-routing: A list of the connections between audio components.
Each entry is a pair of strings, the first being the
@@ -52,6 +54,7 @@ Required properties for the following compatibles:
Required properties for the following compatibles:
- "allwinner,sun8i-a23-codec"
+ - "allwinner,sun8i-h3-codec"
- allwinner,codec-analog-controls: A phandle to the codec analog controls
block in the PRCM.
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index ada5fa055950..848af01692a0 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -217,6 +217,13 @@
#define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
#define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
+/* TX FIFO moved on H3 */
+#define SUN8I_H3_CODEC_DAC_TXDATA (0x20)
+#define SUN8I_H3_CODEC_DAC_DBG (0x48)
+#define SUN8I_H3_CODEC_ADC_DBG (0x4c)
+
+/* TODO H3 DAP (Digital Audio Processing) bits */
+
struct sun4i_codec {
struct device *dev;
struct regmap *regmap;
@@ -1293,6 +1300,44 @@ static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
return card;
};
+static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev)
+{
+ struct snd_soc_card *card;
+ int ret;
+
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+ if (!card)
+ return ERR_PTR(-ENOMEM);
+
+ aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
+ "allwinner,codec-analog-controls",
+ 0);
+ if (!aux_dev.codec_of_node) {
+ dev_err(dev, "Can't find analog controls for codec.\n");
+ return ERR_PTR(-EINVAL);
+ };
+
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
+ if (!card->dai_link)
+ return ERR_PTR(-ENOMEM);
+
+ card->dev = dev;
+ card->name = "H3 Audio Codec";
+ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
+ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+ card->dapm_routes = sun8i_codec_card_routes;
+ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
+ card->aux_dev = &aux_dev;
+ card->num_aux_devs = 1;
+ card->fully_routed = true;
+
+ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+ if (ret)
+ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+ return card;
+};
+
static const struct regmap_config sun4i_codec_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -1321,6 +1366,13 @@ static const struct regmap_config sun8i_a23_codec_regmap_config = {
.max_register = SUN8I_A23_CODEC_ADC_RXCNT,
};
+static const struct regmap_config sun8i_h3_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN8I_H3_CODEC_ADC_DBG,
+};
+
struct sun4i_codec_quirks {
const struct regmap_config *regmap_config;
const struct snd_soc_codec_driver *codec;
@@ -1369,6 +1421,21 @@ static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
.has_reset = true,
};
+static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
+ .regmap_config = &sun8i_h3_codec_regmap_config,
+ /*
+ * TODO Share the codec structure with A23 for now.
+ * This should be split out when adding digital audio
+ * processing support for the H3.
+ */
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_h3_codec_create_card,
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
+ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+};
+
static const struct of_device_id sun4i_codec_of_match[] = {
{
.compatible = "allwinner,sun4i-a10-codec",
@@ -1386,6 +1453,10 @@ static const struct of_device_id sun4i_codec_of_match[] = {
.compatible = "allwinner,sun8i-a23-codec",
.data = &sun8i_a23_codec_quirks,
},
+ {
+ .compatible = "allwinner,sun8i-h3-codec",
+ .data = &sun8i_h3_codec_quirks,
+ },
{}
};
MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
--
cgit v1.2.3
From 48a760279ba31c59b8cfb14c5be9ed1c8e191038 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
Date: Wed, 2 Nov 2016 17:02:37 +0100
Subject: ASoC: samsung: Add DT bindings documentation for TM2 sound subsystem
This patch adds DT binding documentation for Exnos5433 based TM2
and TM2E boards sound subsystem.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../bindings/sound/samsung,tm2-audio.txt | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
(limited to 'Documentation/devicetree')
diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
new file mode 100644
index 000000000000..94442e5673b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt
@@ -0,0 +1,38 @@
+Samsung Exynos5433 TM2(E) audio complex with WM5110 codec
+
+Required properties:
+
+ - compatible : "samsung,tm2-audio"
+ - model : the user-visible name of this sound complex
+ - audio-codec : the phandle of the wm5110 audio codec node,
+ as described in ../mfd/arizona.txt
+ - i2s-controller : the phandle of the I2S controller
+ - audio-amplifier : the phandle of the MAX98504 amplifier
+ - samsung,audio-routing : a list of the connections between audio components;
+ each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source; valid names for sources and sinks are the
+ WM5110's and MAX98504's pins and the jacks on the
+ board: HP, SPK, Main Mic, Sub Mic, Third Mic,
+ Headset Mic
+ - mic-bias-gpios : GPIO pin that enables the Main Mic bias regulator
+
+
+Example:
+
+sound {
+ compatible = "samsung,tm2-audio";
+ audio-codec = <&wm5110>;
+ i2s-controller = <&i2s0>;
+ audio-amplifier = <&max98504>;
+ mic-bias-gpios = <&gpr3 2 0>;
+ model = "wm5110";
+ samsung,audio-routing =
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+ "SPK", "SPKOUT",
+ "SPKOUT", "HPOUT2L",
+ "SPKOUT", "HPOUT2R",
+ "Main Mic", "MICBIAS2",
+ "IN1R", "Main Mic";
+};
--
cgit v1.2.3