From 23e291c2e4c84a40a4b3de8539dec95bfda214f1 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Fri, 16 Dec 2016 16:59:16 -0800 Subject: spi: rockchip: support "sleep" pin configuration In the pattern of many other devices, support a system-sleep pin configuration. Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Tested-by: Caesar Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-rockchip.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt index d2ca153614f9..83da4931d832 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt @@ -31,6 +31,10 @@ Optional Properties: - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling Rx data (may need to be fine tuned for high capacitance lines). No delay (0) by default. +- pinctrl-names: Names for the pin configuration(s); may be "default" or + "sleep", where the "sleep" configuration may describe the state + the pins should be in during system suspend. See also + pinctrl/pinctrl-bindings.txt. Example: @@ -46,4 +50,7 @@ Example: interrupts = ; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; + pinctrl-0 = <&spi1_pins>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; }; -- cgit v1.2.3 From c95b0fec3cff0ba584fd2f9e71fd9001ad15381a Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 20 Dec 2016 18:05:47 +1030 Subject: pinctrl: aspeed: dt: Fix compatibles for the System Control Unit Reference the SoC-specific compatible string in the examples as required. Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt index 2ad18c4ea55c..b2efb73337c6 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -11,9 +11,14 @@ Required properties: "aspeed,ast2500-pinctrl" "aspeed,g5-pinctrl" -The pin controller node should be a child of a syscon node with the required +The pin controller node should be the child of a syscon node with the required property: -- compatible: "syscon", "simple-mfd" + +- compatible : Should be one of the following: + "aspeed,ast2400-scu", "syscon", "simple-mfd" + "aspeed,g4-scu", "syscon", "simple-mfd" + "aspeed,ast2500-scu", "syscon", "simple-mfd" + "aspeed,g5-scu", "syscon", "simple-mfd" Refer to the the bindings described in Documentation/devicetree/bindings/mfd/syscon.txt @@ -50,7 +55,7 @@ TIMER7 TIMER8 VGABIOSROM Examples: syscon: scu@1e6e2000 { - compatible = "syscon", "simple-mfd"; + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; pinctrl: pinctrl { -- cgit v1.2.3 From 7d29ed88acbbf00e2056634bd4c0172d55d2568c Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 20 Dec 2016 18:05:48 +1030 Subject: pinctrl: aspeed: Read and write bits in LPC and GFX controllers The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 80 ++++++++-- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 18 +-- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 48 ++++-- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 161 +++++++++++++-------- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 32 ++-- 5 files changed, 242 insertions(+), 97 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt index b2efb73337c6..fb7694ec033d 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -1,15 +1,23 @@ +====================== Aspeed Pin Controllers ----------------------- +====================== The Aspeed SoCs vary in functionality inside a generation but have a common mux device register layout. -Required properties: -- compatible : Should be any one of the following: - "aspeed,ast2400-pinctrl" - "aspeed,g4-pinctrl" - "aspeed,ast2500-pinctrl" - "aspeed,g5-pinctrl" +Required properties for g4: +- compatible : Should be one of the following: + "aspeed,ast2400-pinctrl" + "aspeed,g4-pinctrl" + +Required properties for g5: +- compatible : Should be one of the following: + "aspeed,ast2500-pinctrl" + "aspeed,g5-pinctrl" + +- aspeed,external-nodes: A cell of phandles to external controller nodes: + 0: compatible with "aspeed,ast2500-gfx", "syscon" + 1: compatible with "aspeed,ast2500-lhc", "syscon" The pin controller node should be the child of a syscon node with the required property: @@ -24,7 +32,7 @@ Refer to the the bindings described in Documentation/devicetree/bindings/mfd/syscon.txt Subnode Format --------------- +============== The required properties of child nodes are (as defined in pinctrl-bindings): - function @@ -51,8 +59,11 @@ I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 VGABIOSROM +Examples +======== -Examples: +g4 Example +---------- syscon: scu@1e6e2000 { compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; @@ -68,5 +79,56 @@ syscon: scu@1e6e2000 { }; }; +g5 Example +---------- + +ahb { + apb { + syscon: scu@1e6e2000 { + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl { + compatible = "aspeed,g5-pinctrl"; + aspeed,external-nodes = <&gfx &lhc>; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + }; + }; + + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + }; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; + + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; + }; + }; + }; +}; + Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices. diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index a21b071ff290..558bd102416c 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -292,7 +292,7 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); #define UART6_DESC SIG_DESC_SET(SCU90, 7) #define ROM16_DESC SIG_DESC_SET(SCU90, 6) #define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) -#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 } +#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } #define A8 56 SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); @@ -418,9 +418,9 @@ FUNC_GROUP_DECL(I2C8, G5, F3); #define U1 88 SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); -#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 } -#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } -#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 } +#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } +#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } #define T5 89 #define T5_DESC SIG_DESC_SET(SCU84, 17) @@ -641,11 +641,11 @@ SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); #define U19 139 SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); -#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 } -#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 } -#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 } -#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 } -#define VPO_OFF_12 { SCU94, 0x2, 0, 0 } +#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } +#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } +#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } +#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } +#define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 } #define VPO_24_OFF SIG_DESC_SET(SCU94, 1) #define V21 140 diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 87b46390b695..c5c9a1b6fa1c 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -26,8 +27,8 @@ #define ASPEED_G5_NR_PINS 228 -#define COND1 { SCU90, BIT(6), 0, 0 } -#define COND2 { SCU94, GENMASK(1, 0), 0, 0 } +#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } +#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } #define B14 0 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); @@ -186,9 +187,12 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); FUNC_GROUP_DECL(GPIE0, B20, C20); -#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 } -#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 } -#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 } +#define SPI1_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } +#define SPI1DEBUG_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } +#define SPI1PASSTHRU_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } #define C18 64 SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); @@ -325,10 +329,11 @@ SS_PIN_DECL(R1, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, P2, R1); -#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 } -#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 } -#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } -#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 } +#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 } +#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } +#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } + #define V2 104 #define V2_DESC SIG_DESC_SET(SCU88, 0) @@ -848,10 +853,35 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = { static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) { int i; + struct regmap *map; + struct device_node *node; for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) aspeed_g5_pins[i].number = i; + node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0); + map = syscon_node_to_regmap(node); + of_node_put(node); + if (IS_ERR(map)) { + dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n"); + map = NULL; + } + aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map; + + node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1); + if (node) { + map = syscon_node_to_regmap(node->parent); + if (IS_ERR(map)) { + dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n"); + map = NULL; + } + } else { + dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n"); + map = NULL; + } + of_node_put(node); + aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPC] = map; + return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, &aspeed_g5_pinctrl_data); } diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 49aeba912531..782c5c97f853 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -14,6 +14,12 @@ #include "../core.h" #include "pinctrl-aspeed.h" +static const char *const aspeed_pinmux_ips[] = { + [ASPEED_IP_SCU] = "SCU", + [ASPEED_IP_GFX] = "GFX", + [ASPEED_IP_LPC] = "LPC", +}; + int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -78,7 +84,8 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, static inline void aspeed_sig_desc_print_val( const struct aspeed_sig_desc *desc, bool enable, u32 rv) { - pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg, + pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n", + aspeed_pinmux_ips[desc->ip], desc->reg, desc->mask, enable ? desc->enable : desc->disable, (rv & desc->mask) >> __ffs(desc->mask), rv); } @@ -88,10 +95,11 @@ static inline void aspeed_sig_desc_print_val( * * @desc: The signal descriptor of interest * @enabled: True to query the enabled state, false to query disabled state - * @regmap: The SCU regmap instance + * @regmap: The IP block's regmap instance * - * @return True if the descriptor's bitfield is configured to the state - * selected by @enabled, false otherwise + * @return 1 if the descriptor's bitfield is configured to the state + * selected by @enabled, 0 if not, and less than zero if an unrecoverable + * failure occurred * * Evaluation of descriptor state is non-trivial in that it is not a binary * outcome: The bitfields can be greater than one bit in size and thus can take @@ -99,14 +107,19 @@ static inline void aspeed_sig_desc_print_val( * descriptor (typically this means a different function to the one of interest * is enabled). Thus we must explicitly test for either condition as required. */ -static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, +static int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled, struct regmap *map) { + int ret; unsigned int raw; u32 want; - if (regmap_read(map, desc->reg, &raw) < 0) - return false; + if (!map) + return -ENODEV; + + ret = regmap_read(map, desc->reg, &raw); + if (ret) + return ret; aspeed_sig_desc_print_val(desc, enabled, raw); want = enabled ? desc->enable : desc->disable; @@ -119,10 +132,10 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, * * @expr: An expression controlling the signal for a mux function on a pin * @enabled: True to query the enabled state, false to query disabled state - * @regmap: The SCU regmap instance + * @maps: The list of regmap instances * - * @return True if the expression composed by @enabled evaluates true, false - * otherwise + * @return 1 if the expression composed by @enabled evaluates true, 0 if not, + * and less than zero if an unrecoverable failure occurred. * * A mux function is enabled or disabled if the function's signal expression * for each pin in the function's pin group evaluates true for the desired @@ -135,19 +148,21 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, * neither the enabled nor disabled state. Thus we must explicitly test for * either condition as required. */ -static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, - bool enabled, struct regmap *map) +static int aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, + bool enabled, struct regmap * const *maps) { int i; + int ret; for (i = 0; i < expr->ndescs; i++) { const struct aspeed_sig_desc *desc = &expr->descs[i]; - if (!aspeed_sig_desc_eval(desc, enabled, map)) - return false; + ret = aspeed_sig_desc_eval(desc, enabled, maps[desc->ip]); + if (ret <= 0) + return ret; } - return true; + return 1; } /** @@ -158,19 +173,24 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, * configured * @enable: true to enable an function's signal through a pin's signal * expression, false to disable the function's signal - * @map: The SCU's regmap instance for pinmux register access. + * @maps: The list of regmap instances for pinmux register access. * - * @return true if the expression is configured as requested, false otherwise + * @return 0 if the expression is configured as requested and a negative error + * code otherwise */ -static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, - bool enable, struct regmap *map) +static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, + bool enable, struct regmap * const *maps) { + int ret; int i; for (i = 0; i < expr->ndescs; i++) { - bool ret; const struct aspeed_sig_desc *desc = &expr->descs[i]; u32 pattern = enable ? desc->enable : desc->disable; + u32 val = (pattern << __ffs(desc->mask)); + + if (!maps[desc->ip]) + return -ENODEV; /* * Strap registers are configured in hardware or by early-boot @@ -179,64 +199,79 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, * deconfigured and is the reason we re-evaluate after writing * all descriptor bits. */ - if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) + if ((desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) && + desc->ip == ASPEED_IP_SCU) continue; - ret = regmap_update_bits(map, desc->reg, desc->mask, - pattern << __ffs(desc->mask)) == 0; + ret = regmap_update_bits(maps[desc->ip], desc->reg, + desc->mask, val); - if (!ret) + if (ret) return ret; } - return aspeed_sig_expr_eval(expr, enable, map); + ret = aspeed_sig_expr_eval(expr, enable, maps); + if (ret < 0) + return ret; + + if (!ret) + return -EPERM; + + return 0; } -static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, - struct regmap *map) +static int aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, + struct regmap * const *maps) { - if (aspeed_sig_expr_eval(expr, true, map)) - return true; + int ret; + + ret = aspeed_sig_expr_eval(expr, true, maps); + if (ret < 0) + return ret; + + if (!ret) + return aspeed_sig_expr_set(expr, true, maps); - return aspeed_sig_expr_set(expr, true, map); + return 0; } -static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, - struct regmap *map) +static int aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, + struct regmap * const *maps) { - if (!aspeed_sig_expr_eval(expr, true, map)) - return true; + int ret; + + ret = aspeed_sig_expr_eval(expr, true, maps); + if (ret < 0) + return ret; + + if (ret) + return aspeed_sig_expr_set(expr, false, maps); - return aspeed_sig_expr_set(expr, false, map); + return 0; } /** * Disable a signal on a pin by disabling all provided signal expressions. * * @exprs: The list of signal expressions (from a priority level on a pin) - * @map: The SCU's regmap instance for pinmux register access. + * @maps: The list of regmap instances for pinmux register access. * - * @return true if all expressions in the list are successfully disabled, false - * otherwise + * @return 0 if all expressions are disabled, otherwise a negative error code */ -static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs, - struct regmap *map) +static int aspeed_disable_sig(const struct aspeed_sig_expr **exprs, + struct regmap * const *maps) { - bool disabled = true; + int ret = 0; if (!exprs) return true; - while (*exprs) { - bool ret; - - ret = aspeed_sig_expr_disable(*exprs, map); - disabled = disabled && ret; - + while (*exprs && !ret) { + ret = aspeed_sig_expr_disable(*exprs, maps); exprs++; } - return disabled; + return ret; } /** @@ -330,6 +365,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { int i; + int ret; const struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct aspeed_pin_group *pgroup = &pdata->groups[group]; @@ -343,6 +379,8 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, const struct aspeed_sig_expr **funcs; const struct aspeed_sig_expr ***prios; + pr_debug("Muxing pin %d for %s\n", pin, pfunc->name); + if (!pdesc) return -EINVAL; @@ -358,8 +396,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, if (expr) break; - if (!aspeed_disable_sig(funcs, pdata->map)) - return -EPERM; + ret = aspeed_disable_sig(funcs, pdata->maps); + if (ret) + return ret; prios++; } @@ -377,8 +416,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, return -ENXIO; } - if (!aspeed_sig_expr_enable(expr, pdata->map)) - return -EPERM; + ret = aspeed_sig_expr_enable(expr, pdata->maps); + if (ret) + return ret; } return 0; @@ -414,6 +454,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { + int ret; const struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data; @@ -432,8 +473,9 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, if (aspeed_gpio_in_exprs(funcs)) break; - if (!aspeed_disable_sig(funcs, pdata->map)) - return -EPERM; + ret = aspeed_disable_sig(funcs, pdata->maps); + if (ret) + return ret; prios++; } @@ -462,10 +504,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, * If GPIO is not the lowest priority signal type, assume there is only * one expression defined to enable the GPIO function */ - if (!aspeed_sig_expr_enable(expr, pdata->map)) - return -EPERM; - - return 0; + return aspeed_sig_expr_enable(expr, pdata->maps); } int aspeed_pinctrl_probe(struct platform_device *pdev, @@ -481,10 +520,10 @@ int aspeed_pinctrl_probe(struct platform_device *pdev, return -ENODEV; } - pdata->map = syscon_node_to_regmap(parent->of_node); - if (IS_ERR(pdata->map)) { + pdata->maps[ASPEED_IP_SCU] = syscon_node_to_regmap(parent->of_node); + if (IS_ERR(pdata->maps[ASPEED_IP_SCU])) { dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n"); - return PTR_ERR(pdata->map); + return PTR_ERR(pdata->maps[ASPEED_IP_SCU]); } pctl = pinctrl_register(pdesc, &pdev->dev, pdata); diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 3e72ef8c54bf..0e93cbf2ff33 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -232,6 +232,11 @@ * group. */ +#define ASPEED_IP_SCU 0 +#define ASPEED_IP_GFX 1 +#define ASPEED_IP_LPC 2 +#define ASPEED_NR_PINMUX_IPS 3 + /* * The "Multi-function Pins Mapping and Control" table in the SoC datasheet * references registers by the device/offset mnemonic. The register macros @@ -261,7 +266,9 @@ * A signal descriptor, which describes the register, bits and the * enable/disable values that should be compared or written. * - * @reg: The register offset from base in bytes + * @ip: The IP block identifier, used as an index into the regmap array in + * struct aspeed_pinctrl_data + * @reg: The register offset with respect to the base address of the IP block * @mask: The mask to apply to the register. The lowest set bit of the mask is * used to derive the shift value. * @enable: The value that enables the function. Value should be in the LSBs, @@ -270,6 +277,7 @@ * LSBs, not at the position of the mask. */ struct aspeed_sig_desc { + unsigned int ip; unsigned int reg; u32 mask; u32 enable; @@ -313,24 +321,30 @@ struct aspeed_pin_desc { /* Macro hell */ +#define SIG_DESC_IP_BIT(ip, reg, idx, val) \ + { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } + /** - * Short-hand macro for describing a configuration enabled by the state of one - * bit. The disable value is derived. + * Short-hand macro for describing an SCU descriptor enabled by the state of + * one bit. The disable value is derived. * * @reg: The signal's associated register, offset from base * @idx: The signal's bit index in the register * @val: The value (0 or 1) that enables the function */ #define SIG_DESC_BIT(reg, idx, val) \ - { reg, BIT_MASK(idx), val, (((val) + 1) & 1) } + SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) + +#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) /** - * A further short-hand macro describing a configuration enabled with a set bit. + * A further short-hand macro expanding to an SCU descriptor enabled by a set + * bit. * - * @reg: The configuration's associated register, offset from base - * @idx: The configuration's bit index in the register + * @reg: The register, offset from base + * @idx: The bit index in the register */ -#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1) +#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func #define SIG_DESC_LIST_DECL(sig, func, ...) \ @@ -500,7 +514,7 @@ struct aspeed_pin_desc { MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) struct aspeed_pinctrl_data { - struct regmap *map; + struct regmap *maps[ASPEED_NR_PINMUX_IPS]; const struct pinctrl_pin_desc *pins; const unsigned int npins; -- cgit v1.2.3 From 6d329f14a75f3858a1254abca8b94d4fab556a9a Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 20 Dec 2016 18:05:49 +1030 Subject: pinctrl: aspeed-g4: Add mux configuration for all pins The patch introducing the g4 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Cc: Timothy Pearson Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 19 +- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1097 +++++++++++++++++++- 2 files changed, 1096 insertions(+), 20 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt index fb7694ec033d..a645d0be3347 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -44,13 +44,18 @@ supported: aspeed,ast2400-pinctrl, aspeed,g4-pinctrl: -ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 -I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1 -MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3 -NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16 -ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3 -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30 -VPO12 VPO24 +ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 +ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2 +GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 +I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1 +MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 +NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0 +PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1 +ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK +SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ +SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4 +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS +VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 558bd102416c..09b668415c56 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -43,9 +43,18 @@ * Not all pins have their signals defined (yet). */ +#define D6 0 +SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); + +#define B5 1 +SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); + #define A4 2 SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); +#define E6 3 +SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); + #define I2C9_DESC SIG_DESC_SET(SCU90, 22) #define C5 4 @@ -80,6 +89,26 @@ MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); FUNC_GROUP_DECL(TIMER8, D5); FUNC_GROUP_DECL(MDIO2, A3, D5); +#define J21 8 +SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8)); + +#define J20 9 +SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9)); + +#define H18 10 +SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10)); + +#define F18 11 +SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11)); + +#define E19 12 +SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); +SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); +SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS); +SS_PIN_DECL(E19, GPIOB4, LPCRST); + +FUNC_GROUP_DECL(LPCRST, E19); + #define H19 13 #define H19_DESC SIG_DESC_SET(SCU80, 13) SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); @@ -92,6 +121,19 @@ FUNC_GROUP_DECL(LPCSMI, H19); #define H20 14 SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); +#define E18 15 +SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST, + SIG_DESC_SET(SCU80, 15), + SIG_DESC_BIT(SCU90, 31, 0), + SIG_DESC_SET(SCU3C, 3)); +SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1, + SIG_DESC_SET(SCU80, 15), + SIG_DESC_SET(SCU90, 31)); +MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1); + +FUNC_GROUP_DECL(EXTRST, E18); +FUNC_GROUP_DECL(SPICS1, E18); + #define SD1_DESC SIG_DESC_SET(SCU90, 0) #define I2C10_DESC SIG_DESC_SET(SCU90, 23) @@ -170,6 +212,62 @@ MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); FUNC_GROUP_DECL(GPID0, A18, D16); +#define GPID2_DESC SIG_DESC_SET(SCU8C, 9) + +#define B17 26 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); +MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN); + +#define A17 27 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); +MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT); + +FUNC_GROUP_DECL(GPID2, B17, A17); + +#define GPID4_DESC SIG_DESC_SET(SCU8C, 10) + +#define C16 28 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); +MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN); + +#define B16 29 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); +MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT); + +FUNC_GROUP_DECL(GPID4, C16, B16); + +#define GPID6_DESC SIG_DESC_SET(SCU8C, 11) + +#define A16 30 +SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); +MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN); + +#define E15 31 +SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); +MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT); + +FUNC_GROUP_DECL(GPID6, A16, E15); +FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15); +FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15); + #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) @@ -266,6 +364,15 @@ MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); FUNC_GROUP_DECL(NDCD4, B19); FUNC_GROUP_DECL(SIOPBI, B19); +#define A20 42 +SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); +MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD); +FUNC_GROUP_DECL(NDSR4, A20); +FUNC_GROUP_DECL(SIOPWRGD, A20); + #define D17 43 SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); @@ -275,7 +382,17 @@ MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); FUNC_GROUP_DECL(NRI4, D17); FUNC_GROUP_DECL(SIOPBO, D17); -FUNC_GROUP_DECL(ACPI, B19, D17); +#define B18 44 +SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28)); + +#define A19 45 +SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); +SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); +SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); +MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI); +FUNC_GROUP_DECL(NDTS4, A19); +FUNC_GROUP_DECL(SIOSCI, A19); #define E16 46 SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); @@ -283,6 +400,34 @@ SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); #define C17 47 SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); +#define A14 48 +SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0)); + +#define E13 49 +SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1)); + +#define D13 50 +SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); + +#define C13 51 +SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); + +#define B13 52 +SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); +MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1); + +FUNC_GROUP_DECL(OSCCLK, B13); +FUNC_GROUP_DECL(WDTRST1, B13); + +#define Y21 53 +SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); +MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2); + +FUNC_GROUP_DECL(USBCKI, Y21); +FUNC_GROUP_DECL(WDTRST2, Y21); + #define AA22 54 SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); @@ -352,6 +497,93 @@ MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); +#define SPI1_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } +#define SPI1DEBUG_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } +#define SPI1PASSTHRU_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } + +#define C22 64 +SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(C22, GPIOI0, SYSCS); + +#define G18 65 +SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(G18, GPIOI1, SYSCK); + +#define D19 66 +SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(D19, GPIOI2, SYSDO); + +#define C20 67 +SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(C20, GPIOI3, SYSDI); + +#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) + +#define B22 68 +SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), + SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), + SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS); + +#define G19 69 +SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), + SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), + SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK); + +#define C18 70 +SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1), + SIG_EXPR_PTR(SPI1DO, SPI1DEBUG), + SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO); + +#define E20 71 +SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1), + SIG_EXPR_PTR(SPI1DI, SPI1DEBUG), + SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI); + +FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20); +FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20); +FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20); +FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20); + +#define J5 72 +SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8)); + +#define J4 73 +SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9)); + +#define K5 74 +SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10)); + #define J3 75 SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); @@ -496,6 +728,102 @@ SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); FUNC_GROUP_DECL(RXD1, U5); +#define V3 96 +#define V3_DESC SIG_DESC_SET(SCU84, 24) +SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC); +SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC); +SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC); +SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18), + SIG_EXPR_PTR(VPIOB2, VPI24), + SIG_EXPR_PTR(VPIOB2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC); +MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2); +FUNC_GROUP_DECL(NCTS2, V3); + +#define W2 97 +#define W2_DESC SIG_DESC_SET(SCU84, 25) +SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC); +SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC); +SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC); +SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18), + SIG_EXPR_PTR(VPIOB3, VPI24), + SIG_EXPR_PTR(VPIOB3, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC); +MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2); +FUNC_GROUP_DECL(NDCD2, W2); + +#define Y1 98 +#define Y1_DESC SIG_DESC_SET(SCU84, 26) +SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); +SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); +SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); +SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18), + SIG_EXPR_PTR(VPIOB4, VPI24), + SIG_EXPR_PTR(VPIOB4, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC); +MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2); +FUNC_GROUP_DECL(NDSR2, Y1); + +#define V4 99 +#define V4_DESC SIG_DESC_SET(SCU84, 27) +SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC); +SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC); +SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC); +SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18), + SIG_EXPR_PTR(VPIOB5, VPI24), + SIG_EXPR_PTR(VPIOB5, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC); +MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2); +FUNC_GROUP_DECL(NRI2, V4); + +#define W3 100 +#define W3_DESC SIG_DESC_SET(SCU84, 28) +SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC); +SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC); +SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC); +SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18), + SIG_EXPR_PTR(VPIOB6, VPI24), + SIG_EXPR_PTR(VPIOB6, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC); +MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2); +FUNC_GROUP_DECL(NDTR2, W3); + +#define Y2 101 +#define Y2_DESC SIG_DESC_SET(SCU84, 29) +SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); +SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); +SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); +SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18), + SIG_EXPR_PTR(VPIOB7, VPI24), + SIG_EXPR_PTR(VPIOB7, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC); +MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2); +FUNC_GROUP_DECL(NRTS2, Y2); + +#define AA1 102 +#define AA1_DESC SIG_DESC_SET(SCU84, 30) +SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); +SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); +SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); +SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18), + SIG_EXPR_PTR(VPIOB8, VPI24), + SIG_EXPR_PTR(VPIOB8, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC); +MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2); +FUNC_GROUP_DECL(TXD2, AA1); + +#define V5 103 +#define V5_DESC SIG_DESC_SET(SCU84, 31) +SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC); +SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC); +SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC); +SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18), + SIG_EXPR_PTR(VPIOB9, VPI24), + SIG_EXPR_PTR(VPIOB9, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC); +MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2); +FUNC_GROUP_DECL(RXD2, V5); + #define W4 104 #define W4_DESC SIG_DESC_SET(SCU88, 0) SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); @@ -580,10 +908,57 @@ SS_PIN_DECL(V6, GPIOO0, VPIG8); SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); SS_PIN_DECL(Y5, GPIOO1, VPIG9); -FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2); -FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5); -FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3, - AB2); +#define AA4 114 +SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10)); +SS_PIN_DECL(AA4, GPIOO2, VPIR0); + +#define AB3 115 +SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11)); +SS_PIN_DECL(AB3, GPIOO3, VPIR1); + +#define W6 116 +SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12)); +SS_PIN_DECL(W6, GPIOO4, VPIR2); + +#define AA5 117 +SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13)); +SS_PIN_DECL(AA5, GPIOO5, VPIR3); + +#define AB4 118 +SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14)); +SS_PIN_DECL(AB4, GPIOO6, VPIR4); + +#define V7 119 +SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15)); +SS_PIN_DECL(V7, GPIOO7, VPIR5); + +#define Y6 120 +SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16)); +SS_PIN_DECL(Y6, GPIOP0, VPIR6); + +#define AB5 121 +SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17)); +SS_PIN_DECL(AB5, GPIOP1, VPIR7); + +#define W7 122 +SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18)); +SS_PIN_DECL(W7, GPIOP2, VPIR8); + +#define AA6 123 +SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19)); +SS_PIN_DECL(AA6, GPIOP3, VPIR9); + +FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, + AA22, W5, Y4, AA3, AB2); +FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, + AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7, + AA6); +FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, + V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3); + +#define AB6 124 +SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4); +MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4)); #define Y7 125 SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); @@ -619,6 +994,18 @@ SS_PIN_DECL(F5, GPIOQ3, SDA4); FUNC_GROUP_DECL(I2C4, B1, F5); +#define I2C14_DESC SIG_DESC_SET(SCU90, 27) + +#define H4 132 +SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); +SS_PIN_DECL(H4, GPIOQ4, SCL14); + +#define H3 133 +SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); +SS_PIN_DECL(H3, GPIOQ5, SDA14); + +FUNC_GROUP_DECL(I2C14, H4, H3); + #define DASH9028_DESC SIG_DESC_SET(SCU90, 28) #define H2 134 @@ -776,13 +1163,6 @@ SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8), SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF); MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5); -FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, - U19); -FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, - A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19); -FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20); -FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22); - #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) #define A12 152 @@ -827,6 +1207,50 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13), SIG_EXPR_LIST_PTR(RGMII1TXD3)); +#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) + +#define D9 158 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); +MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN), + SIG_EXPR_LIST_PTR(RGMII2TXCK)); + +#define E9 159 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); +MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9), + SIG_EXPR_LIST_PTR(RGMII2TXCTL)); + +#define A10 160 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); +MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), + SIG_EXPR_LIST_PTR(RGMII2TXD0)); + +#define B10 161 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); +MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), + SIG_EXPR_LIST_PTR(RGMII2TXD1)); + +#define C10 162 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); +MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10), + SIG_EXPR_LIST_PTR(RGMII2TXD2)); + +#define D10 163 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); +MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10), + SIG_EXPR_LIST_PTR(RGMII2TXD3)); + #define E11 164 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC); @@ -869,11 +1293,419 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), SIG_EXPR_LIST_PTR(RGMII1RXD3)); +#define C9 170 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); +MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK), + SIG_EXPR_LIST_PTR(RGMII2RXCK)); + +#define B9 171 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); +MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9), + SIG_EXPR_LIST_PTR(RGMII2RXCTL)); + +#define A9 172 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); +MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), + SIG_EXPR_LIST_PTR(RGMII2RXD0)); + +#define E8 173 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); +MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), + SIG_EXPR_LIST_PTR(RGMII2RXD1)); + +#define D8 174 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); +MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), + SIG_EXPR_LIST_PTR(RGMII2RXD2)); + +#define C8 175 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); +MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), + SIG_EXPR_LIST_PTR(RGMII2RXD3)); + FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, E10); FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, E10); +FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); +FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); + +#define L5 176 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); +MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +FUNC_GROUP_DECL(ADC0, L5); + +#define L4 177 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); +MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +FUNC_GROUP_DECL(ADC1, L4); + +#define L3 178 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); +MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +FUNC_GROUP_DECL(ADC2, L3); + +#define L2 179 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); +MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +FUNC_GROUP_DECL(ADC3, L2); + +#define L1 180 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); +MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +FUNC_GROUP_DECL(ADC4, L1); + +#define M5 181 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); +MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +FUNC_GROUP_DECL(ADC5, M5); + +#define M4 182 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); +MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +FUNC_GROUP_DECL(ADC6, M4); + +#define M3 183 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); +MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +FUNC_GROUP_DECL(ADC7, M3); + +#define M2 184 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); +MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +FUNC_GROUP_DECL(ADC8, M2); + +#define M1 185 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); +MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +FUNC_GROUP_DECL(ADC9, M1); + +#define N5 186 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); +MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +FUNC_GROUP_DECL(ADC10, N5); + +#define N4 187 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); +MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +FUNC_GROUP_DECL(ADC11, N4); + +#define N3 188 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); +MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +FUNC_GROUP_DECL(ADC12, N3); + +#define N2 189 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); +MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +FUNC_GROUP_DECL(ADC13, N2); + +#define N1 190 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); +MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +FUNC_GROUP_DECL(ADC14, N1); + +#define P5 191 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); +MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +FUNC_GROUP_DECL(ADC15, P5); + +#define C21 192 +SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); +SS_PIN_DECL(C21, GPIOY0, SIOS3); +FUNC_GROUP_DECL(SIOS3, C21); + +#define F20 193 +SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); +SS_PIN_DECL(F20, GPIOY1, SIOS5); +FUNC_GROUP_DECL(SIOS5, F20); + +#define G20 194 +SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); +SS_PIN_DECL(G20, GPIOY2, SIOPWREQ); +FUNC_GROUP_DECL(SIOPWREQ, G20); + +#define K20 195 +SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); +SS_PIN_DECL(K20, GPIOY3, SIOONCTRL); +FUNC_GROUP_DECL(SIOONCTRL, K20); + +FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20); + +#define R22 200 +#define R22_DESC SIG_DESC_SET(SCUA4, 16) +SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16); +SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12), + SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1)); +MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0); + +#define P18 201 +#define P18_DESC SIG_DESC_SET(SCUA4, 17) +SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16); +SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12), + SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1)); +MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1); + +#define P19 202 +#define P19_DESC SIG_DESC_SET(SCUA4, 18) +SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16); +SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12), + SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1)); +MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2); + +#define P20 203 +#define P20_DESC SIG_DESC_SET(SCUA4, 19) +SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16); +SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12), + SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1)); +MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3); + +#define P21 204 +#define P21_DESC SIG_DESC_SET(SCUA4, 20) +SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16); +SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12), + SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1)); +MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4); + +#define P22 205 +#define P22_DESC SIG_DESC_SET(SCUA4, 21) +SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16); +SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12), + SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1)); +MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5); + +#define M19 206 +#define M19_DESC SIG_DESC_SET(SCUA4, 22) +SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16); +SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12), + SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1)); +MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6); + +#define M20 207 +#define M20_DESC SIG_DESC_SET(SCUA4, 23) +SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16); +SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12), + SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1)); +MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7); + +#define M21 208 +#define M21_DESC SIG_DESC_SET(SCUA4, 24) +SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16); +SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12), + SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1)); +MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0); + +#define M22 209 +#define M22_DESC SIG_DESC_SET(SCUA4, 25) +SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16); +SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12), + SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1)); +MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1); + +#define L18 210 +#define L18_DESC SIG_DESC_SET(SCUA4, 26) +SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16); +SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12), + SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1)); +MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2); + +#define L19 211 +#define L19_DESC SIG_DESC_SET(SCUA4, 27) +SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16); +SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12), + SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1)); +MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3); + +#define L20 212 +#define L20_DESC SIG_DESC_SET(SCUA4, 28) +SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16); +SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1); +MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4); + +#define L21 213 +#define L21_DESC SIG_DESC_SET(SCUA4, 29) +SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16); +SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1); +MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5); + +#define T18 214 +#define T18_DESC SIG_DESC_SET(SCUA4, 30) +SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16); +SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1); +MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6); + +#define N18 215 +#define N18_DESC SIG_DESC_SET(SCUA4, 31) +SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16); +SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1); +MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7); + +#define N19 216 +#define N19_DESC SIG_DESC_SET(SCUA8, 0) +SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16); +SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1); +MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0); + +#define M18 217 +#define M18_DESC SIG_DESC_SET(SCUA8, 1) +SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16); +SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1); +MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1); + +#define N22 218 +#define N22_DESC SIG_DESC_SET(SCUA8, 2) +SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16); +SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1); +MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2); + +#define N20 219 +#define N20_DESC SIG_DESC_SET(SCUA8, 3) +SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_24_OFF); +SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_24_OFF); +SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16); +SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1); +MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3); + +FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, + U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, + L19, L20, L21, T18, N18, N19, M18, N22, N20); +FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, + A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19, + P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18, + N18, N19, M18, N22, N20); +FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19, + M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22, + N20); +FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, + P20, P21, P22, M19, M20, M21, M22, L18, L19); + /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 * pins becomes 220. */ @@ -883,84 +1715,180 @@ FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(A1), + ASPEED_PINCTRL_PIN(A10), ASPEED_PINCTRL_PIN(A11), ASPEED_PINCTRL_PIN(A12), ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(A14), ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A16), + ASPEED_PINCTRL_PIN(A17), ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A19), ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A20), ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A5), ASPEED_PINCTRL_PIN(A6), ASPEED_PINCTRL_PIN(A7), ASPEED_PINCTRL_PIN(A8), + ASPEED_PINCTRL_PIN(A9), + ASPEED_PINCTRL_PIN(AA1), ASPEED_PINCTRL_PIN(AA2), ASPEED_PINCTRL_PIN(AA22), ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(AA4), + ASPEED_PINCTRL_PIN(AA5), + ASPEED_PINCTRL_PIN(AA6), ASPEED_PINCTRL_PIN(AA7), ASPEED_PINCTRL_PIN(AB1), ASPEED_PINCTRL_PIN(AB2), + ASPEED_PINCTRL_PIN(AB3), + ASPEED_PINCTRL_PIN(AB4), + ASPEED_PINCTRL_PIN(AB5), + ASPEED_PINCTRL_PIN(AB6), ASPEED_PINCTRL_PIN(AB7), ASPEED_PINCTRL_PIN(B1), + ASPEED_PINCTRL_PIN(B10), ASPEED_PINCTRL_PIN(B11), ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(B13), ASPEED_PINCTRL_PIN(B14), ASPEED_PINCTRL_PIN(B15), + ASPEED_PINCTRL_PIN(B16), + ASPEED_PINCTRL_PIN(B17), + ASPEED_PINCTRL_PIN(B18), ASPEED_PINCTRL_PIN(B19), ASPEED_PINCTRL_PIN(B2), + ASPEED_PINCTRL_PIN(B22), ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B5), ASPEED_PINCTRL_PIN(B6), ASPEED_PINCTRL_PIN(B7), + ASPEED_PINCTRL_PIN(B9), ASPEED_PINCTRL_PIN(C1), + ASPEED_PINCTRL_PIN(C10), ASPEED_PINCTRL_PIN(C11), ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(C13), ASPEED_PINCTRL_PIN(C14), ASPEED_PINCTRL_PIN(C15), + ASPEED_PINCTRL_PIN(C16), ASPEED_PINCTRL_PIN(C17), + ASPEED_PINCTRL_PIN(C18), ASPEED_PINCTRL_PIN(C2), + ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C21), + ASPEED_PINCTRL_PIN(C22), ASPEED_PINCTRL_PIN(C3), ASPEED_PINCTRL_PIN(C4), ASPEED_PINCTRL_PIN(C5), ASPEED_PINCTRL_PIN(C6), ASPEED_PINCTRL_PIN(C7), + ASPEED_PINCTRL_PIN(C8), + ASPEED_PINCTRL_PIN(C9), ASPEED_PINCTRL_PIN(D1), + ASPEED_PINCTRL_PIN(D10), ASPEED_PINCTRL_PIN(D11), ASPEED_PINCTRL_PIN(D12), + ASPEED_PINCTRL_PIN(D13), ASPEED_PINCTRL_PIN(D14), ASPEED_PINCTRL_PIN(D15), ASPEED_PINCTRL_PIN(D16), ASPEED_PINCTRL_PIN(D17), ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D19), ASPEED_PINCTRL_PIN(D2), ASPEED_PINCTRL_PIN(D3), ASPEED_PINCTRL_PIN(D4), ASPEED_PINCTRL_PIN(D5), + ASPEED_PINCTRL_PIN(D6), ASPEED_PINCTRL_PIN(D7), + ASPEED_PINCTRL_PIN(D8), + ASPEED_PINCTRL_PIN(D9), ASPEED_PINCTRL_PIN(E10), ASPEED_PINCTRL_PIN(E11), ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(E13), ASPEED_PINCTRL_PIN(E14), + ASPEED_PINCTRL_PIN(E15), ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E18), + ASPEED_PINCTRL_PIN(E19), ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E20), ASPEED_PINCTRL_PIN(E3), ASPEED_PINCTRL_PIN(E5), + ASPEED_PINCTRL_PIN(E6), ASPEED_PINCTRL_PIN(E7), + ASPEED_PINCTRL_PIN(E8), + ASPEED_PINCTRL_PIN(E9), + ASPEED_PINCTRL_PIN(F18), + ASPEED_PINCTRL_PIN(F20), ASPEED_PINCTRL_PIN(F3), ASPEED_PINCTRL_PIN(F4), ASPEED_PINCTRL_PIN(F5), + ASPEED_PINCTRL_PIN(G18), + ASPEED_PINCTRL_PIN(G19), + ASPEED_PINCTRL_PIN(G20), ASPEED_PINCTRL_PIN(G5), ASPEED_PINCTRL_PIN(H1), + ASPEED_PINCTRL_PIN(H18), ASPEED_PINCTRL_PIN(H19), ASPEED_PINCTRL_PIN(H2), ASPEED_PINCTRL_PIN(H20), + ASPEED_PINCTRL_PIN(H3), + ASPEED_PINCTRL_PIN(H4), + ASPEED_PINCTRL_PIN(J20), + ASPEED_PINCTRL_PIN(J21), ASPEED_PINCTRL_PIN(J3), + ASPEED_PINCTRL_PIN(J4), + ASPEED_PINCTRL_PIN(J5), ASPEED_PINCTRL_PIN(K18), + ASPEED_PINCTRL_PIN(K20), + ASPEED_PINCTRL_PIN(K5), + ASPEED_PINCTRL_PIN(L1), + ASPEED_PINCTRL_PIN(L18), + ASPEED_PINCTRL_PIN(L19), + ASPEED_PINCTRL_PIN(L2), + ASPEED_PINCTRL_PIN(L20), + ASPEED_PINCTRL_PIN(L21), ASPEED_PINCTRL_PIN(L22), + ASPEED_PINCTRL_PIN(L3), + ASPEED_PINCTRL_PIN(L4), + ASPEED_PINCTRL_PIN(L5), + ASPEED_PINCTRL_PIN(M1), + ASPEED_PINCTRL_PIN(M18), + ASPEED_PINCTRL_PIN(M19), + ASPEED_PINCTRL_PIN(M2), + ASPEED_PINCTRL_PIN(M20), + ASPEED_PINCTRL_PIN(M21), + ASPEED_PINCTRL_PIN(M22), + ASPEED_PINCTRL_PIN(M3), + ASPEED_PINCTRL_PIN(M4), + ASPEED_PINCTRL_PIN(M5), + ASPEED_PINCTRL_PIN(N1), + ASPEED_PINCTRL_PIN(N18), + ASPEED_PINCTRL_PIN(N19), + ASPEED_PINCTRL_PIN(N2), + ASPEED_PINCTRL_PIN(N20), ASPEED_PINCTRL_PIN(N21), + ASPEED_PINCTRL_PIN(N22), + ASPEED_PINCTRL_PIN(N3), + ASPEED_PINCTRL_PIN(N4), + ASPEED_PINCTRL_PIN(N5), + ASPEED_PINCTRL_PIN(P18), + ASPEED_PINCTRL_PIN(P19), + ASPEED_PINCTRL_PIN(P20), + ASPEED_PINCTRL_PIN(P21), + ASPEED_PINCTRL_PIN(P22), + ASPEED_PINCTRL_PIN(P5), ASPEED_PINCTRL_PIN(R18), + ASPEED_PINCTRL_PIN(R22), ASPEED_PINCTRL_PIN(T1), + ASPEED_PINCTRL_PIN(T18), ASPEED_PINCTRL_PIN(T19), ASPEED_PINCTRL_PIN(T2), ASPEED_PINCTRL_PIN(T4), @@ -979,28 +1907,61 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(V20), ASPEED_PINCTRL_PIN(V21), ASPEED_PINCTRL_PIN(V22), + ASPEED_PINCTRL_PIN(V3), + ASPEED_PINCTRL_PIN(V4), + ASPEED_PINCTRL_PIN(V5), ASPEED_PINCTRL_PIN(V6), + ASPEED_PINCTRL_PIN(V7), ASPEED_PINCTRL_PIN(W1), + ASPEED_PINCTRL_PIN(W2), ASPEED_PINCTRL_PIN(W21), ASPEED_PINCTRL_PIN(W22), + ASPEED_PINCTRL_PIN(W3), ASPEED_PINCTRL_PIN(W4), ASPEED_PINCTRL_PIN(W5), + ASPEED_PINCTRL_PIN(W6), + ASPEED_PINCTRL_PIN(W7), + ASPEED_PINCTRL_PIN(Y1), + ASPEED_PINCTRL_PIN(Y2), + ASPEED_PINCTRL_PIN(Y21), ASPEED_PINCTRL_PIN(Y22), ASPEED_PINCTRL_PIN(Y3), ASPEED_PINCTRL_PIN(Y4), ASPEED_PINCTRL_PIN(Y5), + ASPEED_PINCTRL_PIN(Y6), ASPEED_PINCTRL_PIN(Y7), }; static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(ACPI), + ASPEED_PINCTRL_GROUP(ADC0), + ASPEED_PINCTRL_GROUP(ADC1), + ASPEED_PINCTRL_GROUP(ADC10), + ASPEED_PINCTRL_GROUP(ADC11), + ASPEED_PINCTRL_GROUP(ADC12), + ASPEED_PINCTRL_GROUP(ADC13), + ASPEED_PINCTRL_GROUP(ADC14), + ASPEED_PINCTRL_GROUP(ADC15), + ASPEED_PINCTRL_GROUP(ADC2), + ASPEED_PINCTRL_GROUP(ADC3), + ASPEED_PINCTRL_GROUP(ADC4), + ASPEED_PINCTRL_GROUP(ADC5), + ASPEED_PINCTRL_GROUP(ADC6), + ASPEED_PINCTRL_GROUP(ADC7), + ASPEED_PINCTRL_GROUP(ADC8), + ASPEED_PINCTRL_GROUP(ADC9), ASPEED_PINCTRL_GROUP(BMCINT), ASPEED_PINCTRL_GROUP(DDCCLK), ASPEED_PINCTRL_GROUP(DDCDAT), + ASPEED_PINCTRL_GROUP(EXTRST), ASPEED_PINCTRL_GROUP(FLACK), ASPEED_PINCTRL_GROUP(FLBUSY), ASPEED_PINCTRL_GROUP(FLWP), + ASPEED_PINCTRL_GROUP(GPID), ASPEED_PINCTRL_GROUP(GPID0), + ASPEED_PINCTRL_GROUP(GPID2), + ASPEED_PINCTRL_GROUP(GPID4), + ASPEED_PINCTRL_GROUP(GPID6), ASPEED_PINCTRL_GROUP(GPIE0), ASPEED_PINCTRL_GROUP(GPIE2), ASPEED_PINCTRL_GROUP(GPIE4), @@ -1009,6 +1970,7 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(I2C11), ASPEED_PINCTRL_GROUP(I2C12), ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(I2C14), ASPEED_PINCTRL_GROUP(I2C3), ASPEED_PINCTRL_GROUP(I2C4), ASPEED_PINCTRL_GROUP(I2C5), @@ -1018,25 +1980,37 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(I2C9), ASPEED_PINCTRL_GROUP(LPCPD), ASPEED_PINCTRL_GROUP(LPCPME), - ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCRST), ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(MAC1LINK), + ASPEED_PINCTRL_GROUP(MAC2LINK), ASPEED_PINCTRL_GROUP(MDIO1), ASPEED_PINCTRL_GROUP(MDIO2), ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS2), ASPEED_PINCTRL_GROUP(NCTS3), ASPEED_PINCTRL_GROUP(NCTS4), ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD2), ASPEED_PINCTRL_GROUP(NDCD3), ASPEED_PINCTRL_GROUP(NDCD4), ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR2), ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDSR4), ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR2), ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NDTR4), + ASPEED_PINCTRL_GROUP(NDTS4), ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI2), ASPEED_PINCTRL_GROUP(NRI3), ASPEED_PINCTRL_GROUP(NRI4), ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS2), ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(OSCCLK), ASPEED_PINCTRL_GROUP(PWM0), ASPEED_PINCTRL_GROUP(PWM1), ASPEED_PINCTRL_GROUP(PWM2), @@ -1046,7 +2020,9 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(PWM6), ASPEED_PINCTRL_GROUP(PWM7), ASPEED_PINCTRL_GROUP(RGMII1), + ASPEED_PINCTRL_GROUP(RGMII2), ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(RMII2), ASPEED_PINCTRL_GROUP(ROM16), ASPEED_PINCTRL_GROUP(ROM8), ASPEED_PINCTRL_GROUP(ROMCS1), @@ -1054,21 +2030,48 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(ROMCS3), ASPEED_PINCTRL_GROUP(ROMCS4), ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD2), ASPEED_PINCTRL_GROUP(RXD3), ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SALT1), + ASPEED_PINCTRL_GROUP(SALT2), + ASPEED_PINCTRL_GROUP(SALT3), + ASPEED_PINCTRL_GROUP(SALT4), ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(SGPMCK), ASPEED_PINCTRL_GROUP(SGPMI), + ASPEED_PINCTRL_GROUP(SGPMLD), + ASPEED_PINCTRL_GROUP(SGPMO), + ASPEED_PINCTRL_GROUP(SGPSCK), + ASPEED_PINCTRL_GROUP(SGPSI0), + ASPEED_PINCTRL_GROUP(SGPSI1), + ASPEED_PINCTRL_GROUP(SGPSLD), + ASPEED_PINCTRL_GROUP(SIOONCTRL), ASPEED_PINCTRL_GROUP(SIOPBI), ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(SIOPWREQ), + ASPEED_PINCTRL_GROUP(SIOPWRGD), + ASPEED_PINCTRL_GROUP(SIOS3), + ASPEED_PINCTRL_GROUP(SIOS5), + ASPEED_PINCTRL_GROUP(SIOSCI), + ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(SPI1DEBUG), + ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), + ASPEED_PINCTRL_GROUP(SPICS1), ASPEED_PINCTRL_GROUP(TIMER3), + ASPEED_PINCTRL_GROUP(TIMER4), ASPEED_PINCTRL_GROUP(TIMER5), ASPEED_PINCTRL_GROUP(TIMER6), ASPEED_PINCTRL_GROUP(TIMER7), ASPEED_PINCTRL_GROUP(TIMER8), ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD2), ASPEED_PINCTRL_GROUP(TXD3), ASPEED_PINCTRL_GROUP(TXD4), ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USBCKI), + ASPEED_PINCTRL_GROUP(VGABIOS_ROM), ASPEED_PINCTRL_GROUP(VGAHS), ASPEED_PINCTRL_GROUP(VGAVS), ASPEED_PINCTRL_GROUP(VPI18), @@ -1076,17 +2079,40 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(VPI30), ASPEED_PINCTRL_GROUP(VPO12), ASPEED_PINCTRL_GROUP(VPO24), + ASPEED_PINCTRL_GROUP(WDTRST1), + ASPEED_PINCTRL_GROUP(WDTRST2), }; static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(ACPI), + ASPEED_PINCTRL_FUNC(ADC0), + ASPEED_PINCTRL_FUNC(ADC1), + ASPEED_PINCTRL_FUNC(ADC10), + ASPEED_PINCTRL_FUNC(ADC11), + ASPEED_PINCTRL_FUNC(ADC12), + ASPEED_PINCTRL_FUNC(ADC13), + ASPEED_PINCTRL_FUNC(ADC14), + ASPEED_PINCTRL_FUNC(ADC15), + ASPEED_PINCTRL_FUNC(ADC2), + ASPEED_PINCTRL_FUNC(ADC3), + ASPEED_PINCTRL_FUNC(ADC4), + ASPEED_PINCTRL_FUNC(ADC5), + ASPEED_PINCTRL_FUNC(ADC6), + ASPEED_PINCTRL_FUNC(ADC7), + ASPEED_PINCTRL_FUNC(ADC8), + ASPEED_PINCTRL_FUNC(ADC9), ASPEED_PINCTRL_FUNC(BMCINT), ASPEED_PINCTRL_FUNC(DDCCLK), ASPEED_PINCTRL_FUNC(DDCDAT), + ASPEED_PINCTRL_FUNC(EXTRST), ASPEED_PINCTRL_FUNC(FLACK), ASPEED_PINCTRL_FUNC(FLBUSY), ASPEED_PINCTRL_FUNC(FLWP), + ASPEED_PINCTRL_FUNC(GPID), ASPEED_PINCTRL_FUNC(GPID0), + ASPEED_PINCTRL_FUNC(GPID2), + ASPEED_PINCTRL_FUNC(GPID4), + ASPEED_PINCTRL_FUNC(GPID6), ASPEED_PINCTRL_FUNC(GPIE0), ASPEED_PINCTRL_FUNC(GPIE2), ASPEED_PINCTRL_FUNC(GPIE4), @@ -1095,6 +2121,7 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(I2C11), ASPEED_PINCTRL_FUNC(I2C12), ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(I2C14), ASPEED_PINCTRL_FUNC(I2C3), ASPEED_PINCTRL_FUNC(I2C4), ASPEED_PINCTRL_FUNC(I2C5), @@ -1104,24 +2131,37 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(I2C9), ASPEED_PINCTRL_FUNC(LPCPD), ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCRST), ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(MAC1LINK), + ASPEED_PINCTRL_FUNC(MAC2LINK), ASPEED_PINCTRL_FUNC(MDIO1), ASPEED_PINCTRL_FUNC(MDIO2), ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS2), ASPEED_PINCTRL_FUNC(NCTS3), ASPEED_PINCTRL_FUNC(NCTS4), ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD2), ASPEED_PINCTRL_FUNC(NDCD3), ASPEED_PINCTRL_FUNC(NDCD4), ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR2), ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDSR4), ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR2), ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NDTR4), + ASPEED_PINCTRL_FUNC(NDTS4), ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI2), ASPEED_PINCTRL_FUNC(NRI3), ASPEED_PINCTRL_FUNC(NRI4), ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS2), ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(OSCCLK), ASPEED_PINCTRL_FUNC(PWM0), ASPEED_PINCTRL_FUNC(PWM1), ASPEED_PINCTRL_FUNC(PWM2), @@ -1131,7 +2171,9 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(PWM6), ASPEED_PINCTRL_FUNC(PWM7), ASPEED_PINCTRL_FUNC(RGMII1), + ASPEED_PINCTRL_FUNC(RGMII2), ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(RMII2), ASPEED_PINCTRL_FUNC(ROM16), ASPEED_PINCTRL_FUNC(ROM8), ASPEED_PINCTRL_FUNC(ROMCS1), @@ -1139,21 +2181,48 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(ROMCS3), ASPEED_PINCTRL_FUNC(ROMCS4), ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD2), ASPEED_PINCTRL_FUNC(RXD3), ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SALT1), + ASPEED_PINCTRL_FUNC(SALT2), + ASPEED_PINCTRL_FUNC(SALT3), + ASPEED_PINCTRL_FUNC(SALT4), ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SD2), + ASPEED_PINCTRL_FUNC(SGPMCK), ASPEED_PINCTRL_FUNC(SGPMI), + ASPEED_PINCTRL_FUNC(SGPMLD), + ASPEED_PINCTRL_FUNC(SGPMO), + ASPEED_PINCTRL_FUNC(SGPSCK), + ASPEED_PINCTRL_FUNC(SGPSI0), + ASPEED_PINCTRL_FUNC(SGPSI1), + ASPEED_PINCTRL_FUNC(SGPSLD), + ASPEED_PINCTRL_FUNC(SIOONCTRL), ASPEED_PINCTRL_FUNC(SIOPBI), ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(SIOPWREQ), + ASPEED_PINCTRL_FUNC(SIOPWRGD), + ASPEED_PINCTRL_FUNC(SIOS3), + ASPEED_PINCTRL_FUNC(SIOS5), + ASPEED_PINCTRL_FUNC(SIOSCI), + ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(SPI1DEBUG), + ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), + ASPEED_PINCTRL_FUNC(SPICS1), ASPEED_PINCTRL_FUNC(TIMER3), + ASPEED_PINCTRL_FUNC(TIMER4), ASPEED_PINCTRL_FUNC(TIMER5), ASPEED_PINCTRL_FUNC(TIMER6), ASPEED_PINCTRL_FUNC(TIMER7), ASPEED_PINCTRL_FUNC(TIMER8), ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD2), ASPEED_PINCTRL_FUNC(TXD3), ASPEED_PINCTRL_FUNC(TXD4), ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USBCKI), + ASPEED_PINCTRL_FUNC(VGABIOS_ROM), ASPEED_PINCTRL_FUNC(VGAHS), ASPEED_PINCTRL_FUNC(VGAVS), ASPEED_PINCTRL_FUNC(VPI18), @@ -1161,6 +2230,8 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(VPI30), ASPEED_PINCTRL_FUNC(VPO12), ASPEED_PINCTRL_FUNC(VPO24), + ASPEED_PINCTRL_FUNC(WDTRST1), + ASPEED_PINCTRL_FUNC(WDTRST2), }; static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { -- cgit v1.2.3 From f1337856dd88858bf58bd062306ccbfb63303085 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 20 Dec 2016 18:05:50 +1030 Subject: pinctrl: aspeed-g5: Add mux configuration for all pins The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 17 +- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1478 +++++++++++++++++++- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 1 + 3 files changed, 1488 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt index a645d0be3347..b98e6f030da8 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -59,10 +59,19 @@ VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: -GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 -I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 -RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6 -TIMER7 TIMER8 VGABIOSROM +ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 +ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4 +GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 +I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME +LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 +NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2 +NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4 +PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10 +SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9 +SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ +SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0 +SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 +TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2 Examples ======== diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index c5c9a1b6fa1c..43221a3c7e23 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -25,14 +25,28 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" -#define ASPEED_G5_NR_PINS 228 +#define ASPEED_G5_NR_PINS 232 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } +/* LHCR0 is offset from the end of the H8S/2168-compatible registers */ +#define LHCR0 0x20 +#define GFX064 0x64 + #define B14 0 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); +#define D14 1 +SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); + +#define D13 2 +SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); +SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); +MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3); +FUNC_GROUP_DECL(SPI1CS1, D13); +FUNC_GROUP_DECL(TIMER3, D13); + #define E13 3 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); @@ -72,6 +86,32 @@ FUNC_GROUP_DECL(TIMER8, B13); FUNC_GROUP_DECL(MDIO2, C13, B13); +#define K19 8 +GPIO_PIN_DECL(K19, GPIOB0); + +#define L19 9 +GPIO_PIN_DECL(L19, GPIOB1); + +#define L18 10 +GPIO_PIN_DECL(L18, GPIOB2); + +#define K18 11 +GPIO_PIN_DECL(K18, GPIOB3); + +#define J20 12 +SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); + +#define H21 13 +#define H21_DESC SIG_DESC_SET(SCU80, 13) +SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC); +MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI); +FUNC_GROUP_DECL(LPCPD, H21); +FUNC_GROUP_DECL(LPCSMI, H21); + +#define H22 14 +SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); + #define H20 15 GPIO_PIN_DECL(H20, GPIOB7); @@ -168,7 +208,44 @@ MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT); FUNC_GROUP_DECL(GPID2, F20, D20); -#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21) +#define GPID4_DESC SIG_DESC_SET(SCU8C, 10) + +#define D21 28 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); +MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN); + +#define E20 29 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); +MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT); + +FUNC_GROUP_DECL(GPID4, D21, E20); + +#define GPID6_DESC SIG_DESC_SET(SCU8C, 11) + +#define G18 30 +SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); +MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN); + +#define C21 31 +SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); +MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT); + +FUNC_GROUP_DECL(GPID6, G18, C21); +FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); + +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) #define B20 32 @@ -177,6 +254,7 @@ SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); +FUNC_GROUP_DECL(NCTS3, B20); #define C20 33 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); @@ -184,9 +262,227 @@ SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); +FUNC_GROUP_DECL(NDCD3, C20); FUNC_GROUP_DECL(GPIE0, B20, C20); +#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) + +#define F18 34 +SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); +MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN); +FUNC_GROUP_DECL(NDSR3, F18); + + +#define F17 35 +SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); +MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT); +FUNC_GROUP_DECL(NRI3, F17); + +FUNC_GROUP_DECL(GPIE2, F18, F17); + +#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) + +#define E18 36 +SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); +MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN); +FUNC_GROUP_DECL(NDTR3, E18); + +#define D19 37 +SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); +MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT); +FUNC_GROUP_DECL(NRTS3, D19); + +FUNC_GROUP_DECL(GPIE4, E18, D19); + +#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) + +#define A20 38 +SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); +MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN); +FUNC_GROUP_DECL(TXD3, A20); + +#define B19 39 +SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); +MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT); +FUNC_GROUP_DECL(RXD3, B19); + +FUNC_GROUP_DECL(GPIE6, A20, B19); + +#define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0) +#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30) + +#define J19 40 +SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); +MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4); +FUNC_GROUP_DECL(NCTS4, J19); + +#define J18 41 +SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4); +FUNC_GROUP_DECL(NDCD4, J18); + +#define B22 42 +SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4); +FUNC_GROUP_DECL(NDSR4, B22); + +#define B21 43 +SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4); +FUNC_GROUP_DECL(NRI4, B21); + +#define A21 44 +SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); +MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4); +FUNC_GROUP_DECL(NDTR4, A21); + +#define H19 45 +SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); +MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4); +FUNC_GROUP_DECL(NRTS4, H19); + +#define G17 46 +SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); +MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4); +FUNC_GROUP_DECL(TXD4, G17); + +#define H18 47 +SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); +MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4); +FUNC_GROUP_DECL(RXD4, H18); + +FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18); +FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18); + +#define A19 48 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); +SS_PIN_DECL(A19, GPIOG0, SGPS1CK); + +#define E19 49 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); +SS_PIN_DECL(E19, GPIOG1, SGPS1LD); + +#define C19 50 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); +SS_PIN_DECL(C19, GPIOG2, SGPS1I0); + +#define E16 51 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); +SS_PIN_DECL(E16, GPIOG3, SGPS1I1); + +FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16); + +#define SGPS2_DESC SIG_DESC_SET(SCU94, 12) + +#define E17 52 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); +MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1); +FUNC_GROUP_DECL(SALT1, E17); + +#define D16 53 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); +MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2); +FUNC_GROUP_DECL(SALT2, D16); + +#define D15 54 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); +MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3); +FUNC_GROUP_DECL(SALT3, D15); + +#define E14 55 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); +MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4); +FUNC_GROUP_DECL(SALT4, E14); + +FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); + +#define UART6_DESC SIG_DESC_SET(SCU90, 7) + +#define A18 56 +SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6); + +#define B18 57 +SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6); + +#define D17 58 +SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6); + +#define C17 59 +SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6); + +#define A17 60 +SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6); + +#define B17 61 +SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6); + +#define A16 62 +SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC); +SS_PIN_DECL(A16, GPIOH6, TXD6); + +#define D18 63 +SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC); +SS_PIN_DECL(D18, GPIOH7, RXD6); + +FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); + #define SPI1_DESC \ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } #define SPI1DEBUG_DESC \ @@ -281,6 +577,30 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO); SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); SS_PIN_DECL(N4, GPIOJ3, SGPMI); +#define N5 76 +SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); +SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); +MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5); +FUNC_GROUP_DECL(VGAHS, N5); + +#define R4 77 +SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); +SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); +MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4); +FUNC_GROUP_DECL(VGAVS, R4); + +#define R3 78 +SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); +SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); +MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3); +FUNC_GROUP_DECL(DDCCLK, R3); + +#define T3 79 +SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); +SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); +MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3); +FUNC_GROUP_DECL(DDCDAT, T3); + #define I2C5_DESC SIG_DESC_SET(SCU90, 18) #define L3 80 @@ -329,11 +649,119 @@ SS_PIN_DECL(R1, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, P2, R1); +#define T2 88 +SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); + #define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 } #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } #define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } - +#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5) + +#define T1 89 +#define T1_DESC SIG_DESC_SET(SCU84, 17) +SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2); +MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1); +FUNC_GROUP_DECL(NDCD1, T1); + +#define U1 90 +#define U1_DESC SIG_DESC_SET(SCU84, 18) +SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC); +MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1); +FUNC_GROUP_DECL(NDSR1, U1); + +#define U2 91 +#define U2_DESC SIG_DESC_SET(SCU84, 19) +SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2); +MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1); +FUNC_GROUP_DECL(NRI1, U2); + +#define P4 92 +#define P4_DESC SIG_DESC_SET(SCU84, 20) +SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2); +MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1); +FUNC_GROUP_DECL(NDTR1, P4); + +#define P3 93 +#define P3_DESC SIG_DESC_SET(SCU84, 21) +SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2); +MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1); +FUNC_GROUP_DECL(NRTS1, P3); + +#define V1 94 +#define V1_DESC SIG_DESC_SET(SCU84, 22) +SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2); +MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1); +FUNC_GROUP_DECL(TXD1, V1); + +#define W1 95 +#define W1_DESC SIG_DESC_SET(SCU84, 23) +SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2); +MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1); +FUNC_GROUP_DECL(RXD1, W1); + +#define Y1 96 +#define Y1_DESC SIG_DESC_SET(SCU84, 24) +SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2); +MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2); +FUNC_GROUP_DECL(NCTS2, Y1); + +#define AB2 97 +#define AB2_DESC SIG_DESC_SET(SCU84, 25) +SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2); +MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2); +FUNC_GROUP_DECL(NDCD2, AB2); + +#define AA1 98 +#define AA1_DESC SIG_DESC_SET(SCU84, 26) +SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2); +MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2); +FUNC_GROUP_DECL(NDSR2, AA1); + +#define Y2 99 +#define Y2_DESC SIG_DESC_SET(SCU84, 27) +SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2); +MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2); +FUNC_GROUP_DECL(NRI2, Y2); + +#define AA2 100 +#define AA2_DESC SIG_DESC_SET(SCU84, 28) +SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2); +MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2); +FUNC_GROUP_DECL(NDTR2, AA2); + +#define P5 101 +#define P5_DESC SIG_DESC_SET(SCU84, 29) +SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2); +MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2); +FUNC_GROUP_DECL(NRTS2, P5); + +#define R5 102 +#define R5_DESC SIG_DESC_SET(SCU84, 30) +SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2); +MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2); +FUNC_GROUP_DECL(TXD2, R5); + +#define T5 103 +#define T5_DESC SIG_DESC_SET(SCU84, 31) +SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2); +MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2); +FUNC_GROUP_DECL(RXD2, T5); #define V2 104 #define V2_DESC SIG_DESC_SET(SCU88, 0) @@ -399,9 +827,88 @@ SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); FUNC_GROUP_DECL(PWM7, T4); +#define U5 112 +SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), + COND2); +SS_PIN_DECL(U5, GPIOO0, VPIG8); + +#define U4 113 +SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), + COND2); +SS_PIN_DECL(U4, GPIOO1, VPIG9); + +#define V5 114 +SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC, + SIG_DESC_SET(SCU88, 10)); +SS_PIN_DECL(V5, GPIOO2, DASHV5); + +#define AB4 115 +SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC, + SIG_DESC_SET(SCU88, 11)); +SS_PIN_DECL(AB4, GPIOO3, DASHAB4); + +#define AB3 116 +SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12), + COND2); +SS_PIN_DECL(AB3, GPIOO4, VPIR2); + +#define Y4 117 +SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13), + COND2); +SS_PIN_DECL(Y4, GPIOO5, VPIR3); + +#define AA4 118 +SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14), + COND2); +SS_PIN_DECL(AA4, GPIOO6, VPIR4); + +#define W4 119 +SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15), + COND2); +SS_PIN_DECL(W4, GPIOO7, VPIR5); + +#define V4 120 +SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16), + COND2); +SS_PIN_DECL(V4, GPIOP0, VPIR6); + +#define W5 121 +SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17), + COND2); +SS_PIN_DECL(W5, GPIOP1, VPIR7); + +#define AA5 122 +SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18), + COND2); +SS_PIN_DECL(AA5, GPIOP2, VPIR8); + +#define AB5 123 +SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19), + COND2); +SS_PIN_DECL(AB5, GPIOP3, VPIR9); + +FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3, + U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, + AB5); + +#define Y6 124 +SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 20)); +SS_PIN_DECL(Y6, GPIOP4, DASHY6); + +#define Y5 125 +SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 21)); +SS_PIN_DECL(Y5, GPIOP5, DASHY5); + +#define W6 126 +SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 22)); +SS_PIN_DECL(W6, GPIOP6, DASHW6); + #define V6 127 SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), - SIG_DESC_SET(SCU88, 23)); + SIG_DESC_SET(SCU88, 23)); SS_PIN_DECL(V6, GPIOP7, DASHV6); #define I2C3_DESC SIG_DESC_SET(SCU90, 16) @@ -446,6 +953,24 @@ SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1)); #define N20 135 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29)); +#define AA19 136 +SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2); + +#define T19 137 +SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2); + +#define T17 138 +SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2); + +#define Y19 139 +SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2); + +#define W19 140 +SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2); + +#define V19 141 +SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2); + #define D8 142 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); SS_PIN_DECL(D8, GPIOR6, MDC1); @@ -456,6 +981,93 @@ SS_PIN_DECL(E10, GPIOR7, MDIO1); FUNC_GROUP_DECL(MDIO1, D8, E10); +#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } +#define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } +#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } +#define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } + +#define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7) + +#define V20 144 +#define V20_DESC SIG_DESC_SET(SCU8C, 0) +SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO), + SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC); +MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1); +FUNC_GROUP_DECL(SPI2CS1, V20); + +#define U19 145 +#define U19_DESC SIG_DESC_SET(SCU8C, 1) +SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO), + SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC); +MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT); +FUNC_GROUP_DECL(BMCINT, U19); + +#define R18 146 +#define R18_DESC SIG_DESC_SET(SCU8C, 2) +SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO), + SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC); +MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5); +FUNC_GROUP_DECL(SALT5, R18); + +#define P18 147 +#define P18_DESC SIG_DESC_SET(SCU8C, 3) +SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO), + SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC); +MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6); +FUNC_GROUP_DECL(SALT6, P18); + +#define R19 148 +#define R19_DESC SIG_DESC_SET(SCU8C, 4) +SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO), + SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2)); +SS_PIN_DECL(R19, GPIOS4, VPOB6); + +#define W20 149 +#define W20_DESC SIG_DESC_SET(SCU8C, 5) +SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO), + SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2)); +SS_PIN_DECL(W20, GPIOS5, VPOB7); + +#define U20 150 +#define U20_DESC SIG_DESC_SET(SCU8C, 6) +SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO), + SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2)); +SS_PIN_DECL(U20, GPIOS6, VPOB8); + +#define AA20 151 +#define AA20_DESC SIG_DESC_SET(SCU8C, 7) +SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO), + SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2)); +SS_PIN_DECL(AA20, GPIOS7, VPOB9); + /* RGMII1/RMII1 */ #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) @@ -637,6 +1249,481 @@ MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); +#define F4 176 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); +MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +FUNC_GROUP_DECL(ADC0, F4); + +#define F5 177 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); +MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +FUNC_GROUP_DECL(ADC1, F5); + +#define E2 178 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); +MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +FUNC_GROUP_DECL(ADC2, E2); + +#define E1 179 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); +MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +FUNC_GROUP_DECL(ADC3, E1); + +#define F3 180 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); +MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +FUNC_GROUP_DECL(ADC4, F3); + +#define E3 181 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); +MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +FUNC_GROUP_DECL(ADC5, E3); + +#define G5 182 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); +MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +FUNC_GROUP_DECL(ADC6, G5); + +#define G4 183 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); +MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +FUNC_GROUP_DECL(ADC7, G4); + +#define F2 184 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); +MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +FUNC_GROUP_DECL(ADC8, F2); + +#define G3 185 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); +MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +FUNC_GROUP_DECL(ADC9, G3); + +#define G2 186 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); +MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +FUNC_GROUP_DECL(ADC10, G2); + +#define F1 187 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); +MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +FUNC_GROUP_DECL(ADC11, F1); + +#define H5 188 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); +MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +FUNC_GROUP_DECL(ADC12, H5); + +#define G1 189 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); +MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +FUNC_GROUP_DECL(ADC13, G1); + +#define H3 190 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); +MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +FUNC_GROUP_DECL(ADC14, H3); + +#define H4 191 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); +MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +FUNC_GROUP_DECL(ADC15, H4); + +#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19) + +#define R22 192 +SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); +MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22); +FUNC_GROUP_DECL(SIOS3, R22); + +#define R21 193 +SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); +MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21); +FUNC_GROUP_DECL(SIOS5, R21); + +#define P22 194 +SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); +MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22); +FUNC_GROUP_DECL(SIOPWREQ, P22); + +#define P21 195 +SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); +MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21); +FUNC_GROUP_DECL(SIOONCTRL, P21); + +#define M18 196 +SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12)); + +#define M19 197 +SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13)); + +#define M20 198 +SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14)); + +#define P20 199 +SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15)); + +#define PNOR_DESC SIG_DESC_SET(SCU90, 31) + +#define Y20 200 +#define Y20_DESC SIG_DESC_SET(SCUA4, 16) +SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO), + SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2)); +SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC); +SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0); +MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI), + SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0)); +FUNC_GROUP_DECL(SIOPBI, Y20); + +#define AB20 201 +#define AB20_DESC SIG_DESC_SET(SCUA4, 17) +SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO), + SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2)); +SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC); +SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1); +MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD), + SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1)); +FUNC_GROUP_DECL(SIOPWRGD, AB20); + +#define AB21 202 +#define AB21_DESC SIG_DESC_SET(SCUA4, 18) +SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO), + SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2)); +SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC); +SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2); +MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO), + SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2)); +FUNC_GROUP_DECL(SIOPBO, AB21); + +#define AA21 203 +#define AA21_DESC SIG_DESC_SET(SCUA4, 19) +SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO), + SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2)); +SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC); +SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3); +MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI), + SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3)); +FUNC_GROUP_DECL(SIOSCI, AA21); + +FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); + +/* CRT DVO disabled, configured for single-edge mode */ +#define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 } + +/* CRT DVO disabled, configured for dual-edge mode */ +#define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 } + +/* CRT DVO enabled, configured for single-edge mode */ +#define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 } + +/* CRT DVO enabled, configured for dual-edge mode */ +#define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 } + +#define U21 204 +#define U21_DESC SIG_DESC_SET(SCUA4, 20) +SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO), + SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC); +MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4); + +#define W22 205 +#define W22_DESC SIG_DESC_SET(SCUA4, 21) +SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO), + SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC); +MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5); + +#define V22 206 +#define V22_DESC SIG_DESC_SET(SCUA4, 22) +SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO), + SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC); +MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6); + +#define W21 207 +#define W21_DESC SIG_DESC_SET(SCUA4, 23) +SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO), + SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC); +MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7); + +#define Y21 208 +#define Y21_DESC SIG_DESC_SET(SCUA4, 24) +SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO), + SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0); +MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7), + SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0)); +FUNC_GROUP_DECL(SALT7, Y21); + +#define V21 209 +#define V21_DESC SIG_DESC_SET(SCUA4, 25) +SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO), + SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1); +MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8), + SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1)); +FUNC_GROUP_DECL(SALT8, V21); + +#define Y22 210 +#define Y22_DESC SIG_DESC_SET(SCUA4, 26) +SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO), + SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2); +MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9), + SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2)); +FUNC_GROUP_DECL(SALT9, Y22); + +#define AA22 211 +#define AA22_DESC SIG_DESC_SET(SCUA4, 27) +SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO), + SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3); +MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10), + SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3)); +FUNC_GROUP_DECL(SALT10, AA22); + +#define U22 212 +#define U22_DESC SIG_DESC_SET(SCUA4, 28) +SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO), + SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4); +MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11), + SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4)); +FUNC_GROUP_DECL(SALT11, U22); + +#define T20 213 +#define T20_DESC SIG_DESC_SET(SCUA4, 29) +SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO), + SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5); +MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12), + SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5)); +FUNC_GROUP_DECL(SALT12, T20); + +#define N18 214 +#define N18_DESC SIG_DESC_SET(SCUA4, 30) +SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO), + SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6); +MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13), + SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6)); +FUNC_GROUP_DECL(SALT13, N18); + +#define P19 215 +#define P19_DESC SIG_DESC_SET(SCUA4, 31) +SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO), + SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7); +MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14), + SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7)); +FUNC_GROUP_DECL(SALT14, P19); + +#define N19 216 +#define N19_DESC SIG_DESC_SET(SCUA8, 0) +SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO), + SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC); +MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE); + +#define T21 217 +#define T21_DESC SIG_DESC_SET(SCUA8, 1) +SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO), + SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC); +MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE); + +FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, + AA22, U22, T20, N18, P19, N19, T21); + +#define T22 218 +#define T22_DESC SIG_DESC_SET(SCUA8, 2) +SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO), + SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC); +MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1); +FUNC_GROUP_DECL(WDTRST1, T22); + +#define R20 219 +#define R20_DESC SIG_DESC_SET(SCUA8, 3) +SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO), + SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC); +MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2); +FUNC_GROUP_DECL(WDTRST2, R20); + +FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, + AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20, + N18, P19, N19, T21, T22, R20); + +#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25) + +#define G21 224 +SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); +MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0); +FUNC_GROUP_DECL(LAD0, G21); + +#define G20 225 +SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); +MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1); +FUNC_GROUP_DECL(LAD1, G20); + +#define D22 226 +SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); +MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2); +FUNC_GROUP_DECL(LAD2, D22); + +#define E22 227 +SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); +MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3); +FUNC_GROUP_DECL(LAD3, E22); + +#define C22 228 +SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); +MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK); +FUNC_GROUP_DECL(LCLK, C22); + +#define F21 229 +SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); +MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME); +FUNC_GROUP_DECL(LFRAME, F21); + +#define F22 230 +SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); +MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ); +FUNC_GROUP_DECL(LSIRQ, F22); + +#define G22 231 +SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); +MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST); +FUNC_GROUP_DECL(LPCRST, G22); + +FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { @@ -646,12 +1733,32 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(A13), ASPEED_PINCTRL_PIN(A14), ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A16), + ASPEED_PINCTRL_PIN(A17), + ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A19), ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A20), + ASPEED_PINCTRL_PIN(A21), ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A5), ASPEED_PINCTRL_PIN(A9), + ASPEED_PINCTRL_PIN(AA1), + ASPEED_PINCTRL_PIN(AA19), + ASPEED_PINCTRL_PIN(AA2), + ASPEED_PINCTRL_PIN(AA20), + ASPEED_PINCTRL_PIN(AA21), + ASPEED_PINCTRL_PIN(AA22), ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(AA4), + ASPEED_PINCTRL_PIN(AA5), + ASPEED_PINCTRL_PIN(AB2), + ASPEED_PINCTRL_PIN(AB20), + ASPEED_PINCTRL_PIN(AB21), + ASPEED_PINCTRL_PIN(AB3), + ASPEED_PINCTRL_PIN(AB4), + ASPEED_PINCTRL_PIN(AB5), ASPEED_PINCTRL_PIN(B1), ASPEED_PINCTRL_PIN(B10), ASPEED_PINCTRL_PIN(B11), @@ -660,8 +1767,13 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(B14), ASPEED_PINCTRL_PIN(B15), ASPEED_PINCTRL_PIN(B16), + ASPEED_PINCTRL_PIN(B17), + ASPEED_PINCTRL_PIN(B18), + ASPEED_PINCTRL_PIN(B19), ASPEED_PINCTRL_PIN(B2), ASPEED_PINCTRL_PIN(B20), + ASPEED_PINCTRL_PIN(B21), + ASPEED_PINCTRL_PIN(B22), ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B4), ASPEED_PINCTRL_PIN(B5), @@ -673,62 +1785,210 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(C14), ASPEED_PINCTRL_PIN(C15), ASPEED_PINCTRL_PIN(C16), + ASPEED_PINCTRL_PIN(C17), ASPEED_PINCTRL_PIN(C18), + ASPEED_PINCTRL_PIN(C19), ASPEED_PINCTRL_PIN(C2), ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C21), + ASPEED_PINCTRL_PIN(C22), ASPEED_PINCTRL_PIN(C3), ASPEED_PINCTRL_PIN(C4), ASPEED_PINCTRL_PIN(C5), ASPEED_PINCTRL_PIN(D1), ASPEED_PINCTRL_PIN(D10), + ASPEED_PINCTRL_PIN(D13), + ASPEED_PINCTRL_PIN(D14), + ASPEED_PINCTRL_PIN(D15), + ASPEED_PINCTRL_PIN(D16), + ASPEED_PINCTRL_PIN(D17), + ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D19), ASPEED_PINCTRL_PIN(D2), ASPEED_PINCTRL_PIN(D20), + ASPEED_PINCTRL_PIN(D21), + ASPEED_PINCTRL_PIN(D22), ASPEED_PINCTRL_PIN(D4), ASPEED_PINCTRL_PIN(D5), ASPEED_PINCTRL_PIN(D6), ASPEED_PINCTRL_PIN(D7), ASPEED_PINCTRL_PIN(D8), ASPEED_PINCTRL_PIN(D9), + ASPEED_PINCTRL_PIN(E1), ASPEED_PINCTRL_PIN(E10), ASPEED_PINCTRL_PIN(E12), ASPEED_PINCTRL_PIN(E13), + ASPEED_PINCTRL_PIN(E14), ASPEED_PINCTRL_PIN(E15), + ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E17), + ASPEED_PINCTRL_PIN(E18), + ASPEED_PINCTRL_PIN(E19), + ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E20), ASPEED_PINCTRL_PIN(E21), + ASPEED_PINCTRL_PIN(E22), + ASPEED_PINCTRL_PIN(E3), ASPEED_PINCTRL_PIN(E6), ASPEED_PINCTRL_PIN(E7), ASPEED_PINCTRL_PIN(E9), + ASPEED_PINCTRL_PIN(F1), + ASPEED_PINCTRL_PIN(F17), + ASPEED_PINCTRL_PIN(F18), ASPEED_PINCTRL_PIN(F19), + ASPEED_PINCTRL_PIN(F2), ASPEED_PINCTRL_PIN(F20), + ASPEED_PINCTRL_PIN(F21), + ASPEED_PINCTRL_PIN(F22), + ASPEED_PINCTRL_PIN(F3), + ASPEED_PINCTRL_PIN(F4), + ASPEED_PINCTRL_PIN(F5), ASPEED_PINCTRL_PIN(F9), + ASPEED_PINCTRL_PIN(G1), + ASPEED_PINCTRL_PIN(G17), + ASPEED_PINCTRL_PIN(G18), + ASPEED_PINCTRL_PIN(G2), + ASPEED_PINCTRL_PIN(G20), + ASPEED_PINCTRL_PIN(G21), + ASPEED_PINCTRL_PIN(G22), + ASPEED_PINCTRL_PIN(G3), + ASPEED_PINCTRL_PIN(G4), + ASPEED_PINCTRL_PIN(G5), + ASPEED_PINCTRL_PIN(H18), + ASPEED_PINCTRL_PIN(H19), ASPEED_PINCTRL_PIN(H20), + ASPEED_PINCTRL_PIN(H21), + ASPEED_PINCTRL_PIN(H22), + ASPEED_PINCTRL_PIN(H3), + ASPEED_PINCTRL_PIN(H4), + ASPEED_PINCTRL_PIN(H5), + ASPEED_PINCTRL_PIN(J18), + ASPEED_PINCTRL_PIN(J19), + ASPEED_PINCTRL_PIN(J20), + ASPEED_PINCTRL_PIN(K18), + ASPEED_PINCTRL_PIN(K19), ASPEED_PINCTRL_PIN(L1), + ASPEED_PINCTRL_PIN(L18), + ASPEED_PINCTRL_PIN(L19), ASPEED_PINCTRL_PIN(L2), ASPEED_PINCTRL_PIN(L3), ASPEED_PINCTRL_PIN(L4), + ASPEED_PINCTRL_PIN(M18), + ASPEED_PINCTRL_PIN(M19), + ASPEED_PINCTRL_PIN(M20), ASPEED_PINCTRL_PIN(N1), + ASPEED_PINCTRL_PIN(N18), + ASPEED_PINCTRL_PIN(N19), ASPEED_PINCTRL_PIN(N2), ASPEED_PINCTRL_PIN(N20), ASPEED_PINCTRL_PIN(N21), ASPEED_PINCTRL_PIN(N22), ASPEED_PINCTRL_PIN(N3), ASPEED_PINCTRL_PIN(N4), + ASPEED_PINCTRL_PIN(N5), ASPEED_PINCTRL_PIN(P1), + ASPEED_PINCTRL_PIN(P18), + ASPEED_PINCTRL_PIN(P19), ASPEED_PINCTRL_PIN(P2), + ASPEED_PINCTRL_PIN(P20), + ASPEED_PINCTRL_PIN(P21), + ASPEED_PINCTRL_PIN(P22), + ASPEED_PINCTRL_PIN(P3), + ASPEED_PINCTRL_PIN(P4), + ASPEED_PINCTRL_PIN(P5), ASPEED_PINCTRL_PIN(R1), + ASPEED_PINCTRL_PIN(R18), + ASPEED_PINCTRL_PIN(R19), + ASPEED_PINCTRL_PIN(R2), + ASPEED_PINCTRL_PIN(R20), + ASPEED_PINCTRL_PIN(R21), + ASPEED_PINCTRL_PIN(R22), + ASPEED_PINCTRL_PIN(R3), + ASPEED_PINCTRL_PIN(R4), + ASPEED_PINCTRL_PIN(R5), + ASPEED_PINCTRL_PIN(T1), + ASPEED_PINCTRL_PIN(T17), + ASPEED_PINCTRL_PIN(T19), + ASPEED_PINCTRL_PIN(T2), + ASPEED_PINCTRL_PIN(T20), + ASPEED_PINCTRL_PIN(T21), + ASPEED_PINCTRL_PIN(T22), + ASPEED_PINCTRL_PIN(T3), ASPEED_PINCTRL_PIN(T4), + ASPEED_PINCTRL_PIN(T5), + ASPEED_PINCTRL_PIN(U1), + ASPEED_PINCTRL_PIN(U19), + ASPEED_PINCTRL_PIN(U2), + ASPEED_PINCTRL_PIN(U20), + ASPEED_PINCTRL_PIN(U21), + ASPEED_PINCTRL_PIN(U22), ASPEED_PINCTRL_PIN(U3), + ASPEED_PINCTRL_PIN(U4), + ASPEED_PINCTRL_PIN(U5), + ASPEED_PINCTRL_PIN(V1), + ASPEED_PINCTRL_PIN(V19), ASPEED_PINCTRL_PIN(V2), + ASPEED_PINCTRL_PIN(V20), + ASPEED_PINCTRL_PIN(V21), + ASPEED_PINCTRL_PIN(V22), ASPEED_PINCTRL_PIN(V3), + ASPEED_PINCTRL_PIN(V4), + ASPEED_PINCTRL_PIN(V5), ASPEED_PINCTRL_PIN(V6), + ASPEED_PINCTRL_PIN(W1), + ASPEED_PINCTRL_PIN(W19), ASPEED_PINCTRL_PIN(W2), + ASPEED_PINCTRL_PIN(W20), + ASPEED_PINCTRL_PIN(W21), + ASPEED_PINCTRL_PIN(W22), ASPEED_PINCTRL_PIN(W3), + ASPEED_PINCTRL_PIN(W4), + ASPEED_PINCTRL_PIN(W5), + ASPEED_PINCTRL_PIN(W6), + ASPEED_PINCTRL_PIN(Y1), + ASPEED_PINCTRL_PIN(Y19), + ASPEED_PINCTRL_PIN(Y2), + ASPEED_PINCTRL_PIN(Y20), + ASPEED_PINCTRL_PIN(Y21), + ASPEED_PINCTRL_PIN(Y22), ASPEED_PINCTRL_PIN(Y3), + ASPEED_PINCTRL_PIN(Y4), + ASPEED_PINCTRL_PIN(Y5), + ASPEED_PINCTRL_PIN(Y6), }; static const struct aspeed_pin_group aspeed_g5_groups[] = { + ASPEED_PINCTRL_GROUP(ACPI), + ASPEED_PINCTRL_GROUP(ADC0), + ASPEED_PINCTRL_GROUP(ADC1), + ASPEED_PINCTRL_GROUP(ADC10), + ASPEED_PINCTRL_GROUP(ADC11), + ASPEED_PINCTRL_GROUP(ADC12), + ASPEED_PINCTRL_GROUP(ADC13), + ASPEED_PINCTRL_GROUP(ADC14), + ASPEED_PINCTRL_GROUP(ADC15), + ASPEED_PINCTRL_GROUP(ADC2), + ASPEED_PINCTRL_GROUP(ADC3), + ASPEED_PINCTRL_GROUP(ADC4), + ASPEED_PINCTRL_GROUP(ADC5), + ASPEED_PINCTRL_GROUP(ADC6), + ASPEED_PINCTRL_GROUP(ADC7), + ASPEED_PINCTRL_GROUP(ADC8), + ASPEED_PINCTRL_GROUP(ADC9), + ASPEED_PINCTRL_GROUP(BMCINT), + ASPEED_PINCTRL_GROUP(DDCCLK), + ASPEED_PINCTRL_GROUP(DDCDAT), + ASPEED_PINCTRL_GROUP(ESPI), + ASPEED_PINCTRL_GROUP(FWSPICS1), + ASPEED_PINCTRL_GROUP(FWSPICS2), ASPEED_PINCTRL_GROUP(GPID0), ASPEED_PINCTRL_GROUP(GPID2), + ASPEED_PINCTRL_GROUP(GPID4), + ASPEED_PINCTRL_GROUP(GPID6), ASPEED_PINCTRL_GROUP(GPIE0), + ASPEED_PINCTRL_GROUP(GPIE2), + ASPEED_PINCTRL_GROUP(GPIE4), + ASPEED_PINCTRL_GROUP(GPIE6), ASPEED_PINCTRL_GROUP(I2C10), ASPEED_PINCTRL_GROUP(I2C11), ASPEED_PINCTRL_GROUP(I2C12), @@ -741,11 +2001,50 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(I2C7), ASPEED_PINCTRL_GROUP(I2C8), ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(LAD0), + ASPEED_PINCTRL_GROUP(LAD1), + ASPEED_PINCTRL_GROUP(LAD2), + ASPEED_PINCTRL_GROUP(LAD3), + ASPEED_PINCTRL_GROUP(LCLK), + ASPEED_PINCTRL_GROUP(LFRAME), + ASPEED_PINCTRL_GROUP(LPCHC), + ASPEED_PINCTRL_GROUP(LPCPD), + ASPEED_PINCTRL_GROUP(LPCPLUS), + ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCRST), + ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(LSIRQ), ASPEED_PINCTRL_GROUP(MAC1LINK), + ASPEED_PINCTRL_GROUP(MAC2LINK), ASPEED_PINCTRL_GROUP(MDIO1), ASPEED_PINCTRL_GROUP(MDIO2), + ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS2), + ASPEED_PINCTRL_GROUP(NCTS3), + ASPEED_PINCTRL_GROUP(NCTS4), + ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD2), + ASPEED_PINCTRL_GROUP(NDCD3), + ASPEED_PINCTRL_GROUP(NDCD4), + ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR2), + ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDSR4), + ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR2), + ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NDTR4), + ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI2), + ASPEED_PINCTRL_GROUP(NRI3), + ASPEED_PINCTRL_GROUP(NRI4), + ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS2), + ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(NRTS4), ASPEED_PINCTRL_GROUP(OSCCLK), ASPEED_PINCTRL_GROUP(PEWAKE), + ASPEED_PINCTRL_GROUP(PNOR), ASPEED_PINCTRL_GROUP(PWM0), ASPEED_PINCTRL_GROUP(PWM1), ASPEED_PINCTRL_GROUP(PWM2), @@ -758,22 +2057,102 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(RGMII2), ASPEED_PINCTRL_GROUP(RMII1), ASPEED_PINCTRL_GROUP(RMII2), + ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD2), + ASPEED_PINCTRL_GROUP(RXD3), + ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SALT1), + ASPEED_PINCTRL_GROUP(SALT10), + ASPEED_PINCTRL_GROUP(SALT11), + ASPEED_PINCTRL_GROUP(SALT12), + ASPEED_PINCTRL_GROUP(SALT13), + ASPEED_PINCTRL_GROUP(SALT14), + ASPEED_PINCTRL_GROUP(SALT2), + ASPEED_PINCTRL_GROUP(SALT3), + ASPEED_PINCTRL_GROUP(SALT4), + ASPEED_PINCTRL_GROUP(SALT5), + ASPEED_PINCTRL_GROUP(SALT6), + ASPEED_PINCTRL_GROUP(SALT7), + ASPEED_PINCTRL_GROUP(SALT8), + ASPEED_PINCTRL_GROUP(SALT9), + ASPEED_PINCTRL_GROUP(SCL1), + ASPEED_PINCTRL_GROUP(SCL2), ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(SDA1), + ASPEED_PINCTRL_GROUP(SDA2), + ASPEED_PINCTRL_GROUP(SGPS1), + ASPEED_PINCTRL_GROUP(SGPS2), + ASPEED_PINCTRL_GROUP(SIOONCTRL), + ASPEED_PINCTRL_GROUP(SIOPBI), + ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(SIOPWREQ), + ASPEED_PINCTRL_GROUP(SIOPWRGD), + ASPEED_PINCTRL_GROUP(SIOS3), + ASPEED_PINCTRL_GROUP(SIOS5), + ASPEED_PINCTRL_GROUP(SIOSCI), ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(SPI1CS1), ASPEED_PINCTRL_GROUP(SPI1DEBUG), ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), + ASPEED_PINCTRL_GROUP(SPI2CK), + ASPEED_PINCTRL_GROUP(SPI2CS0), + ASPEED_PINCTRL_GROUP(SPI2CS1), + ASPEED_PINCTRL_GROUP(SPI2MISO), + ASPEED_PINCTRL_GROUP(SPI2MOSI), + ASPEED_PINCTRL_GROUP(TIMER3), ASPEED_PINCTRL_GROUP(TIMER4), ASPEED_PINCTRL_GROUP(TIMER5), ASPEED_PINCTRL_GROUP(TIMER6), ASPEED_PINCTRL_GROUP(TIMER7), ASPEED_PINCTRL_GROUP(TIMER8), + ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD2), + ASPEED_PINCTRL_GROUP(TXD3), + ASPEED_PINCTRL_GROUP(TXD4), + ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USBCKI), ASPEED_PINCTRL_GROUP(VGABIOSROM), + ASPEED_PINCTRL_GROUP(VGAHS), + ASPEED_PINCTRL_GROUP(VGAVS), + ASPEED_PINCTRL_GROUP(VPI24), + ASPEED_PINCTRL_GROUP(VPO), + ASPEED_PINCTRL_GROUP(WDTRST1), + ASPEED_PINCTRL_GROUP(WDTRST2), }; static const struct aspeed_pin_function aspeed_g5_functions[] = { + ASPEED_PINCTRL_FUNC(ACPI), + ASPEED_PINCTRL_FUNC(ADC0), + ASPEED_PINCTRL_FUNC(ADC1), + ASPEED_PINCTRL_FUNC(ADC10), + ASPEED_PINCTRL_FUNC(ADC11), + ASPEED_PINCTRL_FUNC(ADC12), + ASPEED_PINCTRL_FUNC(ADC13), + ASPEED_PINCTRL_FUNC(ADC14), + ASPEED_PINCTRL_FUNC(ADC15), + ASPEED_PINCTRL_FUNC(ADC2), + ASPEED_PINCTRL_FUNC(ADC3), + ASPEED_PINCTRL_FUNC(ADC4), + ASPEED_PINCTRL_FUNC(ADC5), + ASPEED_PINCTRL_FUNC(ADC6), + ASPEED_PINCTRL_FUNC(ADC7), + ASPEED_PINCTRL_FUNC(ADC8), + ASPEED_PINCTRL_FUNC(ADC9), + ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(DDCCLK), + ASPEED_PINCTRL_FUNC(DDCDAT), + ASPEED_PINCTRL_FUNC(ESPI), + ASPEED_PINCTRL_FUNC(FWSPICS1), + ASPEED_PINCTRL_FUNC(FWSPICS2), ASPEED_PINCTRL_FUNC(GPID0), ASPEED_PINCTRL_FUNC(GPID2), + ASPEED_PINCTRL_FUNC(GPID4), + ASPEED_PINCTRL_FUNC(GPID6), ASPEED_PINCTRL_FUNC(GPIE0), + ASPEED_PINCTRL_FUNC(GPIE2), + ASPEED_PINCTRL_FUNC(GPIE4), + ASPEED_PINCTRL_FUNC(GPIE6), ASPEED_PINCTRL_FUNC(I2C10), ASPEED_PINCTRL_FUNC(I2C11), ASPEED_PINCTRL_FUNC(I2C12), @@ -786,11 +2165,50 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(I2C7), ASPEED_PINCTRL_FUNC(I2C8), ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(LAD0), + ASPEED_PINCTRL_FUNC(LAD1), + ASPEED_PINCTRL_FUNC(LAD2), + ASPEED_PINCTRL_FUNC(LAD3), + ASPEED_PINCTRL_FUNC(LCLK), + ASPEED_PINCTRL_FUNC(LFRAME), + ASPEED_PINCTRL_FUNC(LPCHC), + ASPEED_PINCTRL_FUNC(LPCPD), + ASPEED_PINCTRL_FUNC(LPCPLUS), + ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCRST), + ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(LSIRQ), ASPEED_PINCTRL_FUNC(MAC1LINK), + ASPEED_PINCTRL_FUNC(MAC2LINK), ASPEED_PINCTRL_FUNC(MDIO1), ASPEED_PINCTRL_FUNC(MDIO2), + ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS2), + ASPEED_PINCTRL_FUNC(NCTS3), + ASPEED_PINCTRL_FUNC(NCTS4), + ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD2), + ASPEED_PINCTRL_FUNC(NDCD3), + ASPEED_PINCTRL_FUNC(NDCD4), + ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR2), + ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDSR4), + ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR2), + ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NDTR4), + ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI2), + ASPEED_PINCTRL_FUNC(NRI3), + ASPEED_PINCTRL_FUNC(NRI4), + ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS2), + ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(NRTS4), ASPEED_PINCTRL_FUNC(OSCCLK), ASPEED_PINCTRL_FUNC(PEWAKE), + ASPEED_PINCTRL_FUNC(PNOR), ASPEED_PINCTRL_FUNC(PWM0), ASPEED_PINCTRL_FUNC(PWM1), ASPEED_PINCTRL_FUNC(PWM2), @@ -803,16 +2221,68 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(RGMII2), ASPEED_PINCTRL_FUNC(RMII1), ASPEED_PINCTRL_FUNC(RMII2), + ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD2), + ASPEED_PINCTRL_FUNC(RXD3), + ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SALT1), + ASPEED_PINCTRL_FUNC(SALT10), + ASPEED_PINCTRL_FUNC(SALT11), + ASPEED_PINCTRL_FUNC(SALT12), + ASPEED_PINCTRL_FUNC(SALT13), + ASPEED_PINCTRL_FUNC(SALT14), + ASPEED_PINCTRL_FUNC(SALT2), + ASPEED_PINCTRL_FUNC(SALT3), + ASPEED_PINCTRL_FUNC(SALT4), + ASPEED_PINCTRL_FUNC(SALT5), + ASPEED_PINCTRL_FUNC(SALT6), + ASPEED_PINCTRL_FUNC(SALT7), + ASPEED_PINCTRL_FUNC(SALT8), + ASPEED_PINCTRL_FUNC(SALT9), + ASPEED_PINCTRL_FUNC(SCL1), + ASPEED_PINCTRL_FUNC(SCL2), ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SD2), + ASPEED_PINCTRL_FUNC(SDA1), + ASPEED_PINCTRL_FUNC(SDA2), + ASPEED_PINCTRL_FUNC(SGPS1), + ASPEED_PINCTRL_FUNC(SGPS2), + ASPEED_PINCTRL_FUNC(SIOONCTRL), + ASPEED_PINCTRL_FUNC(SIOPBI), + ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(SIOPWREQ), + ASPEED_PINCTRL_FUNC(SIOPWRGD), + ASPEED_PINCTRL_FUNC(SIOS3), + ASPEED_PINCTRL_FUNC(SIOS5), + ASPEED_PINCTRL_FUNC(SIOSCI), ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(SPI1CS1), ASPEED_PINCTRL_FUNC(SPI1DEBUG), ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), + ASPEED_PINCTRL_FUNC(SPI2CK), + ASPEED_PINCTRL_FUNC(SPI2CS0), + ASPEED_PINCTRL_FUNC(SPI2CS1), + ASPEED_PINCTRL_FUNC(SPI2MISO), + ASPEED_PINCTRL_FUNC(SPI2MOSI), + ASPEED_PINCTRL_FUNC(TIMER3), ASPEED_PINCTRL_FUNC(TIMER4), ASPEED_PINCTRL_FUNC(TIMER5), ASPEED_PINCTRL_FUNC(TIMER6), ASPEED_PINCTRL_FUNC(TIMER7), ASPEED_PINCTRL_FUNC(TIMER8), + ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD2), + ASPEED_PINCTRL_FUNC(TXD3), + ASPEED_PINCTRL_FUNC(TXD4), + ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USBCKI), ASPEED_PINCTRL_FUNC(VGABIOSROM), + ASPEED_PINCTRL_FUNC(VGAHS), + ASPEED_PINCTRL_FUNC(VGAVS), + ASPEED_PINCTRL_FUNC(VPI24), + ASPEED_PINCTRL_FUNC(VPO), + ASPEED_PINCTRL_FUNC(WDTRST1), + ASPEED_PINCTRL_FUNC(WDTRST2), }; static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 0e93cbf2ff33..08a10d4db229 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -260,6 +260,7 @@ #define SCUA0 0xA0 /* Multi-function Pin Control #7 */ #define SCUA4 0xA4 /* Multi-function Pin Control #8 */ #define SCUA8 0xA8 /* Multi-function Pin Control #9 */ +#define SCUAC 0xAC /* Multi-function Pin Control #10 */ #define HW_STRAP2 0xD0 /* Strapping */ /** -- cgit v1.2.3 From 0e028b49d27caf5476974f4fe421295e65403dae Mon Sep 17 00:00:00 2001 From: Andreas Klinger Date: Wed, 14 Dec 2016 00:08:27 +0100 Subject: pinctrl: fix DT bindings for marvell,kirkwood-pinctrl On Marvell mv88f6180 mpp pins range from 0 to 19 as well as from 35 to 44. This is already fixed in commit: 9573e7923007961799beff38bc5c5a7635634eef This is the documentation change for above commit. Signed-off-by: Andreas Klinger Signed-off-by: Linus Walleij --- .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt index 730444a9a4de..6c0ea155b708 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt @@ -44,16 +44,16 @@ mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) mpp17 17 gpio, sdio(d3) mpp18 18 gpo, nand(io0) mpp19 19 gpo, nand(io1) -mpp20 20 gpio, mii(rxerr) -mpp21 21 gpio, audio(spdifi) -mpp22 22 gpio, audio(spdifo) -mpp23 23 gpio, audio(rmclk) -mpp24 24 gpio, audio(bclk) -mpp25 25 gpio, audio(sdo) -mpp26 26 gpio, audio(lrclk) -mpp27 27 gpio, audio(mclk) -mpp28 28 gpio, audio(sdi) -mpp29 29 gpio, audio(extclk) +mpp35 35 gpio, mii(rxerr) +mpp36 36 gpio, audio(spdifi) +mpp37 37 gpio, audio(spdifo) +mpp38 38 gpio, audio(rmclk) +mpp39 39 gpio, audio(bclk) +mpp40 40 gpio, audio(sdo) +mpp41 41 gpio, audio(lrclk) +mpp42 42 gpio, audio(mclk) +mpp43 43 gpio, audio(sdi) +mpp44 44 gpio, audio(extclk) * Marvell Kirkwood 88f6190 -- cgit v1.2.3 From 16545502d70641af0fc4d2cc0b2789cf27d9ca9d Mon Sep 17 00:00:00 2001 From: M'boumba Cedric Madianga Date: Tue, 13 Dec 2016 14:40:45 +0100 Subject: dt-bindings: stm32-dma: Fix typo regarding DMA client binding Only four cells are required for dma client binding not five. Signed-off-by: M'boumba Cedric Madianga Reviewed-by: Ludovic BARRE Acked-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/stm32-dma.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt index 70cd13f1588a..4408af693d0c 100644 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt @@ -40,8 +40,7 @@ Example: DMA clients connected to the STM32 DMA controller must use the format described in the dma.txt file, using a five-cell specifier for each -channel: a phandle plus four integer cells. -The four cells in order are: +channel: a phandle to the DMA controller plus the following four integer cells: 1. The channel id 2. The request line number @@ -61,7 +60,7 @@ The four cells in order are: 0x1: medium 0x2: high 0x3: very high -5. A 32bit mask specifying the DMA FIFO threshold configuration which are device +4. A 32bit mask specifying the DMA FIFO threshold configuration which are device dependent: -bit 0-1: Fifo threshold 0x0: 1/4 full FIFO -- cgit v1.2.3 From daa10170da271ed82b34c39a5f10f993569eec79 Mon Sep 17 00:00:00 2001 From: Rahul Bedarkar Date: Fri, 14 Oct 2016 11:25:55 +0530 Subject: MIPS: DTS: img: add device tree for Marduk board Add support for Imagination Technologies' Marduk board which is based on Pistachio SoC. It is also known as Creator Ci40. Marduk is legacy name and will be there for decades. Documentation for this board can be found on https://docs.creatordev.io/ci40/ This patch adds initial support for board with following peripherals: * PWM based heartbeat LED * GPIO based buttons * SPI NOR flash on SPI1 * UART0 and UART1 * SD card * Ethernet * USB * PWM * ADC * I2C Signed-off-by: Rahul Bedarkar Acked-by: Rob Herring Acked-by: James Hartley Cc: Mark Rutland Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14394/ Signed-off-by: Ralf Baechle --- .../bindings/mips/img/pistachio-marduk.txt | 10 ++ MAINTAINERS | 6 + arch/mips/boot/dts/img/Makefile | 9 ++ arch/mips/boot/dts/img/pistachio_marduk.dts | 163 +++++++++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt create mode 100644 arch/mips/boot/dts/img/Makefile create mode 100644 arch/mips/boot/dts/img/pistachio_marduk.dts (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt b/Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt new file mode 100644 index 000000000000..2d5126d529a2 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt @@ -0,0 +1,10 @@ +Imagination Technologies' Pistachio SoC based Marduk Board +========================================================== + +Compatible string must be "img,pistachio-marduk", "img,pistachio" + +Hardware and other related documentation is available at +https://docs.creatordev.io/ci40/ + +It is also known as Creator Ci40. Marduk is legacy name and will +be there for decades. diff --git a/MAINTAINERS b/MAINTAINERS index eaa1586d137a..3d93f53383fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7692,6 +7692,12 @@ W: http://www.kernel.org/doc/man-pages L: linux-man@vger.kernel.org S: Maintained +MARDUK (CREATOR CI40) DEVICE TREE SUPPORT +M: Rahul Bedarkar +L: linux-mips@linux-mips.org +S: Maintained +F: arch/mips/boot/dts/img/pistachio_marduk.dts + MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER M: Andrew Lunn M: Vivien Didelot diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile new file mode 100644 index 000000000000..69a65f0f82d2 --- /dev/null +++ b/arch/mips/boot/dts/img/Makefile @@ -0,0 +1,9 @@ +dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb + +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) + +# Force kbuild to make empty built-in.o if necessary +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts new file mode 100644 index 000000000000..cf9cebd52294 --- /dev/null +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2015, 2016 Imagination Technologies Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * IMG Marduk board is also known as Creator Ci40. + */ + +/dts-v1/; + +#include "pistachio.dtsi" + +/ { + model = "IMG Marduk (Creator Ci40)"; + compatible = "img,pistachio-marduk", "img,pistachio"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = &enet; + spi0 = &spfi0; + spi1 = &spfi1; + }; + + chosen { + bootargs = "root=/dev/sda1 rootwait ro lpj=723968"; + stdout-path = "serial1:115200"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "aux_adc_vref"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + internal_dac_supply: internal-dac-supply { + compatible = "regulator-fixed"; + regulator-name = "internal_dac_supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + leds { + compatible = "pwm-leds"; + heartbeat { + label = "marduk:red:heartbeat"; + pwms = <&pwm 3 300000>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + keys { + compatible = "gpio-keys"; + button@1 { + label = "Button 1"; + linux,code = <0x101>; /* BTN_1 */ + gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + }; + button@2 { + label = "Button 2"; + linux,code = <0x102>; /* BTN_2 */ + gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&internal_dac { + VDD-supply = <&internal_dac_supply>; +}; + +&spfi1 { + status = "okay"; + + pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>, + <&spim1_cs1_pin>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "spansion,s25fl016k", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&uart0 { + status = "okay"; + assigned-clock-rates = <114278400>, <1843200>; +}; + +&uart1 { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&enet { + status = "okay"; +}; + +&pin_enet { + drive-strength = <2>; +}; + +&pin_enet_phy_clk { + drive-strength = <2>; +}; + +&sdhost { + status = "okay"; + bus-width = <4>; + disable-wp; +}; + +&pin_sdhost_cmd { + drive-strength = <2>; +}; + +&pin_sdhost_data { + drive-strength = <2>; +}; + +&pwm { + status = "okay"; + + pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>, + <&pwmpdm3_pin>; + pinctrl-names = "default"; +}; + +&adc { + status = "okay"; + vref-supply = <®_1v8>; + adc-reserved-channels = <0x10>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; +}; -- cgit v1.2.3 From e64b8cc72bf9958efd4f38e55d2980c95e0ce679 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Tue, 6 Dec 2016 09:32:03 +0100 Subject: DT: leds: Improve examples by adding some context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During my work on some new LED trigger I tried adding example similar to the existing ones which received following comment from Rob: > It's not really clear in the example this is an LED node as it is > incomplete. Keeping that in mind I suggest adding context for the existing example entries in hope to make documentation more clear. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Jacek Anaszewski --- Documentation/devicetree/bindings/leds/common.txt | 28 +++++++++++++++-------- 1 file changed, 18 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt index 696be5792625..24b656014089 100644 --- a/Documentation/devicetree/bindings/leds/common.txt +++ b/Documentation/devicetree/bindings/leds/common.txt @@ -61,16 +61,24 @@ property can be omitted. Examples: -system-status { - label = "Status"; - linux,default-trigger = "heartbeat"; - ... +gpio-leds { + compatible = "gpio-leds"; + + system-status { + label = "Status"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; }; -camera-flash { - label = "Flash"; - led-sources = <0>, <1>; - led-max-microamp = <50000>; - flash-max-microamp = <320000>; - flash-max-timeout-us = <500000>; +max77693-led { + compatible = "maxim,max77693-led"; + + camera-flash { + label = "Flash"; + led-sources = <0>, <1>; + led-max-microamp = <50000>; + flash-max-microamp = <320000>; + flash-max-timeout-us = <500000>; + }; }; -- cgit v1.2.3 From 003910ebc83bcac2ea543dbc6dfff2bc4fa67789 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 5 Jan 2017 10:54:14 -0800 Subject: pinctrl: Introduce TI IOdelay configuration driver SoC family such as DRA7 family of processors have, in addition to the regular muxing of pins (as done by pinctrl-single), a separate hardware module called IODelay which is also expected to be configured. The "IODelay" module has it's own register space that is independent of the control module and the padconf register area. With recent changes to the pinctrl framework, we can now support this hardware with a reasonably minimal driver by using #pinctrl-cells, GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay reconfiguration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do as little of muxing as absolutely necessary without I/O isolation (which can only be done in initial stages of bootloader). NOTE: with the system wide I/O isolation scheme present in DRA7 SoC family, it is not reasonable to do stop all I/O operations for every such pad configuration scheme. So, we will let it glitch when used in this mode. Even with the above limitation, certain functionality such as MMC has mandatory need for IODelay reconfiguration requirements, depending on speed of transfer. In these cases, with careful examination of usecase involved, the expected glitch can be controlled such that it does not impact functionality. In short, IODelay module support as a padconf driver being introduced here is not expected to do SoC wide I/O Isolation and is meant for a limited subset of IODelay configuration requirements that need to be dynamic and whose glitchy behavior will not cause functionality failure for that interface. IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared to 0x0 at all times, even when configuring Manual IO Timing Modes. This is done by eliminating the LOCK_BIT=1 setting from Step of the Manual IO timing Mode configuration procedure. This option leaves the CFG_* registers unprotected from unintended writes to the CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured. This approach is taken to allow for a generic driver to exist in kernel world that has to be used carefully in required usecases. Signed-off-by: Nishanth Menon Signed-off-by: Lokesh Vutla [tony@atomide.com: updated to use generic pinctrl functions, added binding documentation, updated comments] Acked-by: Rob Herring Signed-off-by: Tony Lindgren Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/ti,iodelay.txt | 47 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/ti/Kconfig | 10 + drivers/pinctrl/ti/Makefile | 1 + drivers/pinctrl/ti/pinctrl-ti-iodelay.c | 944 +++++++++++++++++++++ 6 files changed, 1004 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt create mode 100644 drivers/pinctrl/ti/Kconfig create mode 100644 drivers/pinctrl/ti/Makefile create mode 100644 drivers/pinctrl/ti/pinctrl-ti-iodelay.c (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt new file mode 100644 index 000000000000..c3ed1232b6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt @@ -0,0 +1,47 @@ +* Pin configuration for TI IODELAY controller + +TI dra7 based SoCs such as am57xx have a controller for setting the IO delay +for each pin. For most part the IO delay values are programmed by the bootloader, +but some pins need to be configured dynamically by the kernel such as the +MMC pins. + +Required Properties: + + - compatible: Must be "ti,dra7-iodelay" + - reg: Base address and length of the memory resource used + - #address-cells: Number of address cells + - #size-cells: Size of cells + - #pinctrl-cells: Number of pinctrl cells, must be 2. See also + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example +------- + +In the SoC specific dtsi file: + + dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + }; + +In board-specific file: + +&dra7_iodelay_core { + mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + >; + }; +}; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e806f96fc8a3..8f8c2af45781 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -300,6 +300,7 @@ source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/stm32/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" +source "drivers/pinctrl/ti/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 25d50a86981d..a251f439626f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_PINCTRL_MTK) += mediatek/ diff --git a/drivers/pinctrl/ti/Kconfig b/drivers/pinctrl/ti/Kconfig new file mode 100644 index 000000000000..815a88673d38 --- /dev/null +++ b/drivers/pinctrl/ti/Kconfig @@ -0,0 +1,10 @@ +config PINCTRL_TI_IODELAY + tristate "TI IODelay Module pinconf driver" + depends on OF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to support Texas Instruments' IO delay pinconf driver. + IO delay module is used for the DRA7 SoC family. diff --git a/drivers/pinctrl/ti/Makefile b/drivers/pinctrl/ti/Makefile new file mode 100644 index 000000000000..913744e8b8fa --- /dev/null +++ b/drivers/pinctrl/ti/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_TI_IODELAY) += pinctrl-ti-iodelay.o diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c new file mode 100644 index 000000000000..3b86d3db7358 --- /dev/null +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -0,0 +1,944 @@ +/* + * Support for configuration of IO Delay module found on Texas Instruments SoCs + * such as DRA7 + * + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../devicetree.h" + +#define DRIVER_NAME "ti-iodelay" + +/** + * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance + * @signature_mask: CONFIG_REG mask for the signature bits (see TRM) + * @signature_value: CONFIG_REG signature value to be written (see TRM) + * @lock_mask: CONFIG_REG mask for the lock bits (see TRM) + * @lock_val: CONFIG_REG lock value for the lock bits (see TRM) + * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM) + * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM) + * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM) + * @reg_refclk_offset: Refclk register offset + * @refclk_period_mask: Refclk mask + * @reg_coarse_offset: Coarse register configuration offset + * @coarse_delay_count_mask: Coarse delay count mask + * @coarse_ref_count_mask: Coarse ref count mask + * @reg_fine_offset: Fine register configuration offset + * @fine_delay_count_mask: Fine delay count mask + * @fine_ref_count_mask: Fine ref count mask + * @reg_global_lock_offset: Global iodelay module lock register offset + * @global_lock_mask: Lock mask + * @global_unlock_val: Unlock value + * @global_lock_val: Lock value + * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8 + * @reg_nr_per_pin: Number of iodelay registers for each pin + * @regmap_config: Regmap configuration for the IODelay region + */ +struct ti_iodelay_reg_data { + u32 signature_mask; + u32 signature_value; + u32 lock_mask; + u32 lock_val; + u32 unlock_val; + u32 binary_data_coarse_mask; + u32 binary_data_fine_mask; + + u32 reg_refclk_offset; + u32 refclk_period_mask; + + u32 reg_coarse_offset; + u32 coarse_delay_count_mask; + u32 coarse_ref_count_mask; + + u32 reg_fine_offset; + u32 fine_delay_count_mask; + u32 fine_ref_count_mask; + + u32 reg_global_lock_offset; + u32 global_lock_mask; + u32 global_unlock_val; + u32 global_lock_val; + + u32 reg_start_offset; + u32 reg_nr_per_pin; + + struct regmap_config *regmap_config; +}; + +/** + * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM) + * @coarse_ref_count: Coarse reference count + * @coarse_delay_count: Coarse delay count + * @fine_ref_count: Fine reference count + * @fine_delay_count: Fine Delay count + * @ref_clk_period: Reference Clock period + * @cdpe: Coarse delay parameter + * @fdpe: Fine delay parameter + */ +struct ti_iodelay_reg_values { + u16 coarse_ref_count; + u16 coarse_delay_count; + + u16 fine_ref_count; + u16 fine_delay_count; + + u16 ref_clk_period; + + u32 cdpe; + u32 fdpe; +}; + +/** + * struct ti_iodelay_cfg - Description of each configuration parameters + * @offset: Configuration register offset + * @a_delay: Agnostic Delay (in ps) + * @g_delay: Gnostic Delay (in ps) + */ +struct ti_iodelay_cfg { + u16 offset; + u16 a_delay; + u16 g_delay; +}; + +/** + * struct ti_iodelay_pingroup - Structure that describes one group + * @cfg: configuration array for the pin (from dt) + * @ncfg: number of configuration values allocated + * @config: pinconf "Config" - currently a dummy value + */ +struct ti_iodelay_pingroup { + struct ti_iodelay_cfg *cfg; + int ncfg; + unsigned long config; +}; + +/** + * struct ti_iodelay_device - Represents information for a iodelay instance + * @dev: Device pointer + * @phys_base: Physical address base of the iodelay device + * @reg_base: Virtual address base of the iodelay device + * @regmap: Regmap for this iodelay instance + * @pctl: Pinctrl device + * @desc: pinctrl descriptor for pctl + * @pa: pinctrl pin wise description + * @reg_data: Register definition data for the IODelay instance + * @reg_init_conf_values: Initial configuration values. + */ +struct ti_iodelay_device { + struct device *dev; + unsigned long phys_base; + void __iomem *reg_base; + struct regmap *regmap; + + struct pinctrl_dev *pctl; + struct pinctrl_desc desc; + struct pinctrl_pin_desc *pa; + + const struct ti_iodelay_reg_data *reg_data; + struct ti_iodelay_reg_values reg_init_conf_values; +}; + +/** + * ti_iodelay_extract() - extract bits for a field + * @val: Register value + * @mask: Mask + * + * Return: extracted value which is appropriately shifted + */ +static inline u32 ti_iodelay_extract(u32 val, u32 mask) +{ + return (val & mask) >> __ffs(mask); +} + +/** + * ti_iodelay_compute_dpe() - Compute equation for delay parameter + * @period: Period to use + * @ref: Reference Count + * @delay: Delay count + * @delay_m: Delay multiplier + * + * Return: Computed delay parameter + */ +static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay, + u16 delay_m) +{ + u64 m, d; + + /* Handle overflow conditions */ + m = 10 * (u64)period * (u64)ref; + d = 2 * (u64)delay * (u64)delay_m; + + /* Truncate result back to 32 bits */ + return div64_u64(m, d); +} + +/** + * ti_iodelay_pinconf_set() - Configure the pin configuration + * @iod: iodelay device + * @cfg: Configuration + * + * Update the configuration register as per TRM and lockup once done. + * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only + * while in Isolation. But, then, isolation also implies that every pin + * on the SoC (including DDR) will be isolated out. The only benefit being + * a glitchless configuration, However, the intent of this driver is purely + * to support a "glitchy" configuration where applicable. + * + * Return: 0 in case of success, else appropriate error value + */ +static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, + struct ti_iodelay_cfg *cfg) +{ + const struct ti_iodelay_reg_data *reg = iod->reg_data; + struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; + struct device *dev = iod->dev; + u32 g_delay_coarse, g_delay_fine; + u32 a_delay_coarse, a_delay_fine; + u32 c_elements, f_elements; + u32 total_delay; + u32 reg_mask, reg_val, tmp_val; + int r; + + /* NOTE: Truncation is expected in all division below */ + g_delay_coarse = cfg->g_delay / 920; + g_delay_fine = ((cfg->g_delay % 920) * 10) / 60; + + a_delay_coarse = cfg->a_delay / ival->cdpe; + a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe; + + c_elements = g_delay_coarse + a_delay_coarse; + f_elements = (g_delay_fine + a_delay_fine) / 10; + + if (f_elements > 22) { + total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe; + c_elements = total_delay / ival->cdpe; + f_elements = (total_delay % ival->cdpe) / ival->fdpe; + } + + reg_mask = reg->signature_mask; + reg_val = reg->signature_value << __ffs(reg->signature_mask); + + reg_mask |= reg->binary_data_coarse_mask; + tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); + if (tmp_val & ~reg->binary_data_coarse_mask) { + dev_err(dev, "Masking overflow of coarse elements %08x\n", + tmp_val); + tmp_val &= reg->binary_data_coarse_mask; + } + reg_val |= tmp_val; + + reg_mask |= reg->binary_data_fine_mask; + tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); + if (tmp_val & ~reg->binary_data_fine_mask) { + dev_err(dev, "Masking overflow of fine elements %08x\n", + tmp_val); + tmp_val &= reg->binary_data_fine_mask; + } + reg_val |= tmp_val; + + /* + * NOTE: we leave the iodelay values unlocked - this is to work around + * situations such as those found with mmc mode change. + * However, this leaves open any unwarranted changes to padconf register + * impacting iodelay configuration. Use with care! + */ + reg_mask |= reg->lock_mask; + reg_val |= reg->unlock_val << __ffs(reg->lock_mask); + r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); + + dev_info(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n", + cfg->offset, cfg->a_delay, cfg->g_delay, c_elements, + f_elements, reg_val); + + return r; +} + +/** + * ti_iodelay_pinconf_init_dev() - Initialize IODelay device + * @iod: iodelay device + * + * Unlocks the iodelay region, computes the common parameters + * + * Return: 0 in case of success, else appropriate error value + */ +static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) +{ + const struct ti_iodelay_reg_data *reg = iod->reg_data; + struct device *dev = iod->dev; + struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; + u32 val; + int r; + + /* unlock the iodelay region */ + r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, + reg->global_lock_mask, reg->global_unlock_val); + if (r) + return r; + + /* Read up Recalibration sequence done by bootloader */ + r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); + if (r) + return r; + ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); + dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period); + + r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); + if (r) + return r; + ival->coarse_ref_count = + ti_iodelay_extract(val, reg->coarse_ref_count_mask); + ival->coarse_delay_count = + ti_iodelay_extract(val, reg->coarse_delay_count_mask); + if (!ival->coarse_delay_count) { + dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n", + val); + return -EINVAL; + } + ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, + ival->coarse_ref_count, + ival->coarse_delay_count, 88); + if (!ival->cdpe) { + dev_err(dev, "Invalid cdpe computed params = %d %d %d\n", + ival->ref_clk_period, ival->coarse_ref_count, + ival->coarse_delay_count); + return -EINVAL; + } + dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n", + ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe); + + r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); + if (r) + return r; + ival->fine_ref_count = + ti_iodelay_extract(val, reg->fine_ref_count_mask); + ival->fine_delay_count = + ti_iodelay_extract(val, reg->fine_delay_count_mask); + if (!ival->fine_delay_count) { + dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n", + val); + return -EINVAL; + } + ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, + ival->fine_ref_count, + ival->fine_delay_count, 264); + if (!ival->fdpe) { + dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n", + ival->ref_clk_period, ival->fine_ref_count, + ival->fine_delay_count); + return -EINVAL; + } + dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n", + ival->fine_ref_count, ival->fine_delay_count, ival->fdpe); + + return 0; +} + +/** + * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device + * @iod: IODelay device + * + * Deinitialize the IODelay device (basically just lock the region back up. + */ +static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod) +{ + const struct ti_iodelay_reg_data *reg = iod->reg_data; + + /* lock the iodelay region back again */ + regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, + reg->global_lock_mask, reg->global_lock_val); +} + +/** + * ti_iodelay_get_pingroup() - Find the group mapped by a group selector + * @iod: iodelay device + * @selector: Group Selector + * + * Return: Corresponding group representing group selector + */ +static struct ti_iodelay_pingroup * +ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector) +{ + struct group_desc *g; + + g = pinctrl_generic_get_group(iod->pctl, selector); + if (!g) { + dev_err(iod->dev, "%s could not find pingroup %i\n", __func__, + selector); + + return NULL; + } + + return g->data; +} + +/** + * ti_iodelay_offset_to_pin() - get a pin index based on the register offset + * @iod: iodelay driver instance + * @offset: register offset from the base + */ +static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod, + unsigned int offset) +{ + const struct ti_iodelay_reg_data *r = iod->reg_data; + unsigned int index; + + if (offset > r->regmap_config->max_register) { + dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n", + offset, r->regmap_config->max_register); + return -EINVAL; + } + + index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride; + index /= r->reg_nr_per_pin; + + return index; +} + +/** + * ti_iodelay_node_iterator() - Iterate iodelay node + * @pctldev: Pin controller driver + * @np: Device node + * @pinctrl_spec: Parsed arguments from device tree + * @pins: Array of pins in the pin group + * @pin_index: Pin index in the pin array + * @data: Pin controller driver specific data + * + */ +static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev, + struct device_node *np, + const struct of_phandle_args *pinctrl_spec, + int *pins, int pin_index, void *data) +{ + struct ti_iodelay_device *iod; + struct ti_iodelay_cfg *cfg = data; + const struct ti_iodelay_reg_data *r; + struct pinctrl_pin_desc *pd; + int pin; + + iod = pinctrl_dev_get_drvdata(pctldev); + if (!iod) + return -EINVAL; + + r = iod->reg_data; + + if (pinctrl_spec->args_count < r->reg_nr_per_pin) { + dev_err(iod->dev, "invalid args_count for spec: %i\n", + pinctrl_spec->args_count); + + return -EINVAL; + } + + /* Index plus two value cells */ + cfg[pin_index].offset = pinctrl_spec->args[0]; + cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff; + cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff; + + pin = ti_iodelay_offset_to_pin(iod, cfg[pin_index].offset); + if (pin < 0) { + dev_err(iod->dev, "could not add functions for %s %ux\n", + np->name, cfg[pin_index].offset); + return -ENODEV; + } + pins[pin_index] = pin; + + pd = &iod->pa[pin]; + pd->drv_data = &cfg[pin_index]; + + dev_dbg(iod->dev, "%s offset=%x a_delay = %d g_delay = %d\n", + np->name, cfg[pin_index].offset, cfg[pin_index].a_delay, + cfg[pin_index].g_delay); + + return 0; +} + +/** + * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group + * @pctldev: pinctrl device representing IODelay device + * @np: Node Pointer (device tree) + * @map: Pinctrl Map returned back to pinctrl framework + * @num_maps: Number of maps (1) + * + * Maps the device tree description into a group of configuration parameters + * for iodelay block entry. + * + * Return: 0 in case of success, else appropriate error value + */ +static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct ti_iodelay_device *iod; + struct ti_iodelay_cfg *cfg; + struct ti_iodelay_pingroup *g; + const char *name = "pinctrl-pin-array"; + int rows, *pins, error = -EINVAL, i; + + iod = pinctrl_dev_get_drvdata(pctldev); + if (!iod) + return -EINVAL; + + rows = pinctrl_count_index_with_args(np, name); + if (rows == -EINVAL) + return rows; + + *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL); + if (!*map) + return -ENOMEM; + *num_maps = 0; + + g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL); + if (!g) { + error = -ENOMEM; + goto free_map; + } + + pins = devm_kzalloc(iod->dev, sizeof(*pins) * rows, GFP_KERNEL); + if (!pins) + goto free_group; + + cfg = devm_kzalloc(iod->dev, sizeof(*cfg) * rows, GFP_KERNEL); + if (!cfg) { + error = -ENOMEM; + goto free_pins; + } + + for (i = 0; i < rows; i++) { + struct of_phandle_args pinctrl_spec; + + error = pinctrl_parse_index_with_args(np, name, i, + &pinctrl_spec); + if (error) + goto free_data; + + error = ti_iodelay_node_iterator(pctldev, np, &pinctrl_spec, + pins, i, cfg); + if (error) + goto free_data; + } + + g->cfg = cfg; + g->ncfg = i; + g->config = PIN_CONFIG_END; + + error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g); + if (error < 0) + goto free_data; + + (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)->data.configs.group_or_pin = np->name; + (*map)->data.configs.configs = &g->config; + (*map)->data.configs.num_configs = 1; + *num_maps = 1; + + return 0; + +free_data: + devm_kfree(iod->dev, cfg); +free_pins: + devm_kfree(iod->dev, pins); +free_group: + devm_kfree(iod->dev, g); +free_map: + devm_kfree(iod->dev, *map); + + return error; +} + +/** + * ti_iodelay_pinconf_group_get() - Get the group configuration + * @pctldev: pinctrl device representing IODelay device + * @selector: Group selector + * @config: Configuration returned + * + * Return: The configuration if the group is valid, else returns -EINVAL + */ +static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *config) +{ + struct ti_iodelay_device *iod; + struct device *dev; + struct ti_iodelay_pingroup *group; + + iod = pinctrl_dev_get_drvdata(pctldev); + dev = iod->dev; + group = ti_iodelay_get_pingroup(iod, selector); + + if (!group) + return -EINVAL; + + *config = group->config; + return 0; +} + +/** + * ti_iodelay_pinconf_group_set() - Configure the groups of pins + * @pctldev: pinctrl device representing IODelay device + * @selector: Group selector + * @configs: Configurations + * @num_configs: Number of configurations + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct ti_iodelay_device *iod; + struct device *dev; + struct ti_iodelay_pingroup *group; + int i; + + iod = pinctrl_dev_get_drvdata(pctldev); + dev = iod->dev; + group = ti_iodelay_get_pingroup(iod, selector); + + if (num_configs != 1) { + dev_err(dev, "Unsupported number of configurations %d\n", + num_configs); + return -EINVAL; + } + + if (*configs != PIN_CONFIG_END) { + dev_err(dev, "Unsupported configuration\n"); + return -EINVAL; + } + + for (i = 0; i < group->ncfg; i++) { + if (ti_iodelay_pinconf_set(iod, &group->cfg[i])) + return -ENOTSUPP; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +/** + * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index + * @iod: iodelay driver instance + * @selector: Pin index + */ +static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod, + unsigned int selector) +{ + const struct ti_iodelay_reg_data *r = iod->reg_data; + unsigned int offset; + + offset = selector * r->regmap_config->reg_stride; + offset *= r->reg_nr_per_pin; + offset += r->reg_start_offset; + + return offset; +} + +static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int pin) +{ + struct ti_iodelay_device *iod; + struct pinctrl_pin_desc *pd; + struct ti_iodelay_cfg *cfg; + const struct ti_iodelay_reg_data *r; + unsigned long offset; + u32 in, oen, out; + + iod = pinctrl_dev_get_drvdata(pctldev); + r = iod->reg_data; + + offset = ti_iodelay_pin_to_offset(iod, pin); + if (pin < 0) { + dev_err(iod->dev, "invalid pin offset for pin%i\n", pin); + + return; + } + + pd = &iod->pa[pin]; + cfg = pd->drv_data; + + regmap_read(iod->regmap, offset, &in); + regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen); + regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2, + &out); + + seq_printf(s, "%lx a: %i g: %i (%08x %08x %08x) %s ", + iod->phys_base + offset, + cfg ? cfg->a_delay : -1, + cfg ? cfg->g_delay : -1, + in, oen, out, DRIVER_NAME); +} + +/** + * ti_iodelay_pinconf_group_dbg_show() - show the group information + * @pctldev: Show the group information + * @s: Sequence file + * @selector: Group selector + * + * Provide the configuration information of the selected group + */ +static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int selector) +{ + struct ti_iodelay_device *iod; + struct device *dev; + struct ti_iodelay_pingroup *group; + int i; + + iod = pinctrl_dev_get_drvdata(pctldev); + dev = iod->dev; + group = ti_iodelay_get_pingroup(iod, selector); + if (!group) + return; + + for (i = 0; i < group->ncfg; i++) { + struct ti_iodelay_cfg *cfg; + u32 reg = 0; + + cfg = &group->cfg[i]; + regmap_read(iod->regmap, cfg->offset, ®), + seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)", + cfg->offset, reg, cfg->a_delay, + cfg->g_delay); + } +} +#endif + +static struct pinctrl_ops ti_iodelay_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = ti_iodelay_pin_dbg_show, +#endif + .dt_node_to_map = ti_iodelay_dt_node_to_map, +}; + +static struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = { + .pin_config_group_get = ti_iodelay_pinconf_group_get, + .pin_config_group_set = ti_iodelay_pinconf_group_set, +#ifdef CONFIG_DEBUG_FS + .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show, +#endif +}; + +/** + * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay + * @dev: Device pointer + * @iod: iodelay device + * @base_phy: Base Physical Address + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_alloc_pins(struct device *dev, + struct ti_iodelay_device *iod, u32 base_phy) +{ + const struct ti_iodelay_reg_data *r = iod->reg_data; + struct pinctrl_pin_desc *pin; + u32 phy_reg; + int nr_pins, i; + + nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register); + dev_dbg(dev, "Allocating %i pins\n", nr_pins); + + iod->pa = devm_kzalloc(dev, sizeof(*iod->pa) * nr_pins, GFP_KERNEL); + if (!iod->pa) + return -ENOMEM; + + iod->desc.pins = iod->pa; + iod->desc.npins = nr_pins; + + phy_reg = r->reg_start_offset + base_phy; + + for (i = 0; i < nr_pins; i++, phy_reg += 4) { + pin = &iod->pa[i]; + pin->number = i; + } + + return 0; +} + +static struct regmap_config dra7_iodelay_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xd1c, +}; + +static struct ti_iodelay_reg_data dra7_iodelay_data = { + .signature_mask = 0x0003f000, + .signature_value = 0x29, + .lock_mask = 0x00000400, + .lock_val = 1, + .unlock_val = 0, + .binary_data_coarse_mask = 0x000003e0, + .binary_data_fine_mask = 0x0000001f, + + .reg_refclk_offset = 0x14, + .refclk_period_mask = 0xffff, + + .reg_coarse_offset = 0x18, + .coarse_delay_count_mask = 0xffff0000, + .coarse_ref_count_mask = 0x0000ffff, + + .reg_fine_offset = 0x1C, + .fine_delay_count_mask = 0xffff0000, + .fine_ref_count_mask = 0x0000ffff, + + .reg_global_lock_offset = 0x2c, + .global_lock_mask = 0x0000ffff, + .global_unlock_val = 0x0000aaaa, + .global_lock_val = 0x0000aaab, + + .reg_start_offset = 0x30, + .reg_nr_per_pin = 3, + .regmap_config = &dra7_iodelay_regmap_config, +}; + +static const struct of_device_id ti_iodelay_of_match[] = { + {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data}, + { /* Hopefully no more.. */ }, +}; +MODULE_DEVICE_TABLE(of, ti_iodelay_of_match); + +/** + * ti_iodelay_probe() - Standard probe + * @pdev: platform device + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = of_node_get(dev->of_node); + const struct of_device_id *match; + struct resource *res; + struct ti_iodelay_device *iod; + int ret = 0; + + if (!np) { + ret = -EINVAL; + dev_err(dev, "No OF node\n"); + goto exit_out; + } + + match = of_match_device(ti_iodelay_of_match, dev); + if (!match) { + ret = -EINVAL; + dev_err(dev, "No DATA match\n"); + goto exit_out; + } + + iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL); + if (!iod) { + ret = -ENOMEM; + goto exit_out; + } + iod->dev = dev; + iod->reg_data = match->data; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Missing MEM resource\n"); + ret = -ENODEV; + goto exit_out; + } + + iod->phys_base = res->start; + iod->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(iod->reg_base)) { + ret = PTR_ERR(iod->reg_base); + goto exit_out; + } + + iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, + iod->reg_data->regmap_config); + if (IS_ERR(iod->regmap)) { + dev_err(dev, "Regmap MMIO init failed.\n"); + ret = PTR_ERR(iod->regmap); + goto exit_out; + } + + if (ti_iodelay_pinconf_init_dev(iod)) + goto exit_out; + + ret = ti_iodelay_alloc_pins(dev, iod, res->start); + if (ret) + goto exit_out; + + iod->desc.pctlops = &ti_iodelay_pinctrl_ops; + /* no pinmux ops - we are pinconf */ + iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops; + iod->desc.name = dev_name(dev); + iod->desc.owner = THIS_MODULE; + + iod->pctl = pinctrl_register(&iod->desc, dev, iod); + if (!iod->pctl) { + dev_err(dev, "Failed to register pinctrl\n"); + ret = -ENODEV; + goto exit_out; + } + + platform_set_drvdata(pdev, iod); + +exit_out: + of_node_put(np); + return ret; +} + +/** + * ti_iodelay_remove() - standard remove + * @pdev: platform device + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_remove(struct platform_device *pdev) +{ + struct ti_iodelay_device *iod = platform_get_drvdata(pdev); + + if (!iod) + return 0; + + if (iod->pctl) + pinctrl_unregister(iod->pctl); + + ti_iodelay_pinconf_deinit_dev(iod); + + /* Expect other allocations to be freed by devm */ + + return 0; +} + +static struct platform_driver ti_iodelay_driver = { + .probe = ti_iodelay_probe, + .remove = ti_iodelay_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + .of_match_table = ti_iodelay_of_match, + }, +}; +module_platform_driver(ti_iodelay_driver); + +MODULE_AUTHOR("Texas Instruments, Inc."); +MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 6e8b66c1b7aeb95cff643f358299cf1c5c630abb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 Jan 2017 22:55:43 -0200 Subject: pinctrl: imx7d-pinctrl: Fix a typo Fix a typo in "Peripherals". Signed-off-by: Fabio Estevam Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt index 457b2c68d47b..8c5d27c5b562 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -19,7 +19,7 @@ iomuxc: iomuxc@30330000 { reg = <0x30330000 0x10000>; }; -Pheriparials using pads from iomuxc-lpsr support low state retention power +Peripherals using pads from iomuxc-lpsr support low state retention power state, under LPSR mode GPIO's state of pads are retain. Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -- cgit v1.2.3 From 14a1699225957328e4fb07db7e4751cc9d02ae11 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 18 Jan 2017 02:46:37 -0800 Subject: regulator: qcom-smd: Add PM8994 regulator support This patch adds support for the PM8994 regulators found on msm8992, msm8994 and msm8996 platforms. Signed-off-by: Rajendra Nayak [bjorn: Add DT binding doc and vdd_lvs1_2 supply] Signed-off-by: Bjorn Andersson Signed-off-by: Mark Brown --- .../bindings/regulator/qcom,smd-rpm-regulator.txt | 56 +++++++++++ drivers/regulator/qcom_smd-regulator.c | 102 +++++++++++++++++++++ 2 files changed, 158 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt index 1f8d6f84b657..4e3dfb5b5f16 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt @@ -22,6 +22,7 @@ Regulator nodes are identified by their compatible: "qcom,rpm-pm8841-regulators" "qcom,rpm-pm8916-regulators" "qcom,rpm-pm8941-regulators" + "qcom,rpm-pm8994-regulators" "qcom,rpm-pma8084-regulators" - vdd_s1-supply: @@ -68,6 +69,56 @@ Regulator nodes are identified by their compatible: Definition: reference to regulator supplying the input pin, as described in the data sheet +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply: +- vdd_s6-supply: +- vdd_s7-supply: +- vdd_s8-supply: +- vdd_s9-supply: +- vdd_s10-supply: +- vdd_s11-supply: +- vdd_s12-supply: +- vdd_l1-supply: +- vdd_l2_l26_l28-supply: +- vdd_l3_l11-supply: +- vdd_l4_l27_l31-supply: +- vdd_l5_l7-supply: +- vdd_l6_l12_l32-supply: +- vdd_l5_l7-supply: +- vdd_l8_l16_l30-supply: +- vdd_l9_l10_l18_l22-supply: +- vdd_l9_l10_l18_l22-supply: +- vdd_l3_l11-supply: +- vdd_l6_l12_l32-supply: +- vdd_l13_l19_l23_l24-supply: +- vdd_l14_l15-supply: +- vdd_l14_l15-supply: +- vdd_l8_l16_l30-supply: +- vdd_l17_l29-supply: +- vdd_l9_l10_l18_l22-supply: +- vdd_l13_l19_l23_l24-supply: +- vdd_l20_l21-supply: +- vdd_l20_l21-supply: +- vdd_l9_l10_l18_l22-supply: +- vdd_l13_l19_l23_l24-supply: +- vdd_l13_l19_l23_l24-supply: +- vdd_l25-supply: +- vdd_l2_l26_l28-supply: +- vdd_l4_l27_l31-supply: +- vdd_l2_l26_l28-supply: +- vdd_l17_l29-supply: +- vdd_l8_l16_l30-supply: +- vdd_l4_l27_l31-supply: +- vdd_l6_l12_l32-supply: +- vdd_lvs1_2-supply: + Usage: optional (pm8994 only) + Value type: + Definition: reference to regulator supplying the input pin, as + described in the data sheet + - vdd_s1-supply: - vdd_s2-supply: - vdd_s3-supply: @@ -113,6 +164,11 @@ pm8941: l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3, 5vs1, 5vs2 +pm8994: + s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, + l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, + l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 + pma8084: s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 8ed46a9a55c8..f35994a2a5be 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -305,6 +305,56 @@ static const struct regulator_desc pm8916_buck_hvo_smps = { .ops = &rpm_smps_ldo_ops, }; +static const struct regulator_desc pm8994_hfsmps = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500), + REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000), + }, + .n_linear_ranges = 2, + .n_voltages = 159, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8994_ftsmps = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000), + REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000), + }, + .n_linear_ranges = 2, + .n_voltages = 350, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8994_nldo = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), + }, + .n_linear_ranges = 1, + .n_voltages = 64, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8994_pldo = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), + REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), + REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), + }, + .n_linear_ranges = 3, + .n_voltages = 164, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8994_switch = { + .ops = &rpm_switch_ops, +}; + +static const struct regulator_desc pm8994_lnldo = { + .fixed_uV = 1740000, + .n_voltages = 1, + .ops = &rpm_smps_ldo_ops_fixed, +}; + struct rpm_regulator_data { const char *name; u32 type; @@ -443,10 +493,62 @@ static const struct rpm_regulator_data rpm_pma8084_regulators[] = { {} }; +static const struct rpm_regulator_data rpm_pm8994_regulators[] = { + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" }, + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" }, + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" }, + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" }, + { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" }, + { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" }, + { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" }, + { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" }, + { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" }, + { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" }, + { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" }, + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" }, + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" }, + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" }, + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" }, + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" }, + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" }, + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" }, + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" }, + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" }, + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" }, + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" }, + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" }, + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" }, + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, + { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" }, + { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" }, + { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, + { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, + { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, + { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" }, + { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" }, + { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" }, + { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" }, + { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" }, + { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" }, + { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" }, + { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" }, + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" }, + { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" }, + + {} +}; + static const struct of_device_id rpm_of_match[] = { { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, + { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, {} }; -- cgit v1.2.3 From ca7734ad77b4ffb83a03c80b8d64d40c7ef49263 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 10 Jan 2017 08:30:14 -0800 Subject: regulator: anatop: Add support for "anatop-enable-bit" Add code to support support for "anatop-enable-bit" device-tree property. This property translates to LINREG_ENABLE bit in real hardware and is present on 1p1, 2p5 and 3p0 regulators on i.MX6 and 1p0d regulator on i.MX7. Signed-off-by: Andrey Smirnov Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/anatop-regulator.txt | 1 + drivers/regulator/anatop-regulator.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt index 37c4ea076f88..1d58c8cfdbc0 100644 --- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt @@ -14,6 +14,7 @@ Optional properties: - anatop-delay-bit-shift: Bit shift for the step time register - anatop-delay-bit-width: Number of bits used in the step time register - vin-supply: The supply for this regulator +- anatop-enable-bit: Regulator enable bit offset Any property defined as part of the core regulator binding, defined in regulator.txt, can also be used. diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c index 3a6d0290c54c..b041f277a38b 100644 --- a/drivers/regulator/anatop-regulator.c +++ b/drivers/regulator/anatop-regulator.c @@ -301,7 +301,19 @@ static int anatop_regulator_probe(struct platform_device *pdev) return -EINVAL; } } else { + u32 enable_bit; + rdesc->ops = &anatop_rops; + + if (!of_property_read_u32(np, "anatop-enable-bit", + &enable_bit)) { + anatop_rops.enable = regulator_enable_regmap; + anatop_rops.disable = regulator_disable_regmap; + anatop_rops.is_enabled = regulator_is_enabled_regmap; + + rdesc->enable_reg = sreg->control_reg; + rdesc->enable_mask = BIT(enable_bit); + } } /* register regulator */ -- cgit v1.2.3 From 9d7b1f28c1ff83a0c395f7898a9927ef8b2a0178 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 19 Jan 2017 14:48:44 +0100 Subject: pinctrl: samsung: Document Exynos3250 SoC support Add missing compatible id for Exynos3250 SoC to device tree docs. Exynos pin control driver supports it since commit d97f5b9804bfcdc1 ("pinctrl: exynos: Add driver data for Exynos3250"). Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Acked-by: Tomasz Figa Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 1baf19eecabf..5e00a21de2bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, + - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. -- cgit v1.2.3 From d7ae8f8dee7f3f759e119335e2d8deb2683a8161 Mon Sep 17 00:00:00 2001 From: Kalyan Kinthada Date: Mon, 30 Jan 2017 12:20:33 +1300 Subject: pinctrl: mvebu: pinctrl driver for 98DX3236 SoC This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada Signed-off-by: Chris Packham Acked-by: Rob Herring Acked-by: Sebastian Hesselbarth Signed-off-by: Linus Walleij --- .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++++ drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 156 +++++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt new file mode 100644 index 000000000000..97aef67ee769 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt @@ -0,0 +1,46 @@ +* Marvell 98dx3236 pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage + +Required properties: +- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants + +name pins functions +================================================================================ +mpp0 0 gpo, spi0(mosi), dev(ad8) +mpp1 1 gpio, spi0(miso), dev(ad9) +mpp2 2 gpo, spi0(sck), dev(ad10) +mpp3 3 gpio, spi0(cs0), dev(ad11) +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) +mpp6 6 gpo, sd0(clk), dev(a2) +mpp7 7 gpio, sd0(d0), dev(ale0) +mpp8 8 gpio, sd0(d1), dev(ale1) +mpp9 9 gpio, sd0(d2), dev(ready0) +mpp10 10 gpio, sd0(d3), dev(ad12) +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) +mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14) +mpp13 13 gpio, intr(out), dev(ad15) +mpp14 14 gpio, i2c0(sck) +mpp15 15 gpio, i2c0(sda) +mpp16 16 gpo, dev(oe) +mpp17 17 gpo, dev(clkout) +mpp18 18 gpio, uart1(txd) +mpp19 19 gpio, uart1(rxd), dev(rb) +mpp20 20 gpo, dev(we0) +mpp21 21 gpo, dev(ad0) +mpp22 22 gpo, dev(ad1) +mpp23 23 gpo, dev(ad2) +mpp24 24 gpo, dev(ad3) +mpp25 25 gpo, dev(ad4) +mpp26 26 gpo, dev(ad5) +mpp27 27 gpo, dev(ad6) +mpp28 28 gpo, dev(ad7) +mpp29 29 gpo, dev(a0) +mpp30 30 gpo, dev(a1) +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1) +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index e4ea71a9d985..705831ec8378 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -49,6 +49,10 @@ enum armada_xp_variant { V_MV78460 = BIT(2), V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460), V_MV78260_PLUS = (V_MV78260 | V_MV78460), + V_98DX3236 = BIT(3), + V_98DX3336 = BIT(4), + V_98DX4251 = BIT(5), + V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251), }; static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { @@ -360,6 +364,131 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)), }; +static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)), + MPP_MODE(22, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)), + MPP_MODE(23, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)), + MPP_MODE(24, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)), + MPP_MODE(26, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)), + MPP_MODE(28, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)), + MPP_MODE(29, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)), + MPP_MODE(31, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)), +}; + static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; static const struct of_device_id armada_xp_pinctrl_of_match[] = { @@ -375,6 +504,14 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = { .compatible = "marvell,mv78460-pinctrl", .data = (void *) V_MV78460, }, + { + .compatible = "marvell,98dx3236-pinctrl", + .data = (void *) V_98DX3236, + }, + { + .compatible = "marvell,98dx4251-pinctrl", + .data = (void *) V_98DX4251, + }, { }, }; @@ -407,6 +544,14 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(2, 64, 64, 3), }; +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = { + MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl), +}; + +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), +}; + static int armada_xp_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) { @@ -488,6 +633,17 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) soc->gpioranges = mv78460_mpp_gpio_ranges; soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges); break; + case V_98DX3236: + case V_98DX3336: + case V_98DX4251: + /* fall-through */ + soc->controls = mv98dx3236_mpp_controls; + soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls); + soc->modes = mv98dx3236_mpp_modes; + soc->nmodes = mv98dx3236_mpp_controls[0].npins; + soc->gpioranges = mv98dx3236_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges); + break; } nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); -- cgit v1.2.3 From 838adb576d4a3da03d4e35a3149dc015dfeec299 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 26 Jan 2017 23:48:51 +0800 Subject: drivers: pinctrl: add driver for Allwinner H5 SoC Based on the Allwinner H5 datasheet and the pinctrl driver of the backward-compatible H3 this introduces the pin multiplex assignments for the H5 SoC. H5 introduced some more pin functions (e.g. three more groups of TS pins, and one more groups of SIM pins) than H3. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 558 +++++++++++++++++++++ 4 files changed, 564 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index de1378b4efad..7c85dca4221a 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -23,6 +23,7 @@ Required properties: "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" "allwinner,sun50i-a64-pinctrl" + "allwinner,sun50i-h5-r-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 8ba10d830ce2..92d845827577 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -72,4 +72,8 @@ config PINCTRL_SUN50I_A64 bool select PINCTRL_SUNXI +config PINCTRL_SUN50I_H5 + bool + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 7bcb4683bce5..f9a3855c42f1 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o +obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c new file mode 100644 index 000000000000..ccf9419e9418 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -0,0 +1,558 @@ +/* + * Allwinner H5 SoC pinctrl driver. + * + * Copyright (C) 2016 Icenowy Zheng + * + * Based on pinctrl-sun8i-h3.c, which is: + * Copyright (C) 2015 Jens Kuske + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai + * Copyright (C) 2014 Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_h5_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x4, "mmc2")), /* DS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION(0x4, "ts2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION(0x4, "ts2")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */ + SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */ + SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXCK */ + SUNXI_FUNCTION(0x4, "ts2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */ + SUNXI_FUNCTION(0x4, "ts2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXERR */ + SUNXI_FUNCTION(0x4, "ts2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D3 */ + SUNXI_FUNCTION(0x5, "ts3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D4 */ + SUNXI_FUNCTION(0x5, "ts3")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D5 */ + SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D6 */ + SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* CRS */ + SUNXI_FUNCTION(0x4, "ts2"), /* D7 */ + SUNXI_FUNCTION(0x5, "ts3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXCK */ + SUNXI_FUNCTION(0x4, "sim")), /* PWREN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */ + SUNXI_FUNCTION(0x4, "sim")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXERR */ + SUNXI_FUNCTION(0x4, "sim")), /* DATA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */ + SUNXI_FUNCTION(0x4, "sim")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* MDC */ + SUNXI_FUNCTION(0x4, "sim")), /* DET */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "ts0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ts0")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x4, "ts1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "ts1")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts"), /* D7 */ + SUNXI_FUNCTION(0x4, "ts1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ +}; + +static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { + .pins = sun50i_h5_pins, + .npins = ARRAY_SIZE(sun50i_h5_pins), + .irq_banks = 2, + .irq_read_needs_mux = true +}; + +static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun50i_h5_pinctrl_data); +} + +static const struct of_device_id sun50i_h5_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h5-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_h5_pinctrl_driver = { + .probe = sun50i_h5_pinctrl_probe, + .driver = { + .name = "sun50i-h5-pinctrl", + .of_match_table = sun50i_h5_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_h5_pinctrl_driver); -- cgit v1.2.3 From 182c2909e22d8a3ec39f8a4530fa19867cbd989b Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Sun, 18 Dec 2016 09:11:37 -0200 Subject: [media] Documentation: bindings: add documentation for ir-spi device driver Document the ir-spi driver's binding which is a IR led driven through the SPI line. Signed-off-by: Andi Shyti Acked-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/leds/irled/spi-ir-led.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt b/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt new file mode 100644 index 000000000000..896b6997cf30 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt @@ -0,0 +1,29 @@ +Device tree bindings for IR LED connected through SPI bus which is used as +remote controller. + +The IR LED switch is connected to the MOSI line of the SPI device and the data +are delivered thourgh that. + +Required properties: + - compatible: should be "ir-spi-led". + +Optional properties: + - duty-cycle: 8 bit balue that represents the percentage of one period + in which the signal is active. It can be 50, 60, 70, 75, 80 or 90. + - led-active-low: boolean value that specifies whether the output is + negated with a NOT gate. + - power-supply: specifies the power source. It can either be a regulator + or a gpio which enables a regulator, i.e. a regulator-fixed as + described in + Documentation/devicetree/bindings/regulator/fixed-regulator.txt + +Example: + + irled@0 { + compatible = "ir-spi-led"; + reg = <0x0>; + spi-max-frequency = <5000000>; + power-supply = <&vdd_led>; + led-active-low; + duty-cycle = /bits/ 8 <60>; + }; -- cgit v1.2.3 From b513652443fc515ec90202d005230f2afee457ad Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Fri, 2 Dec 2016 15:29:02 +0900 Subject: PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433 This patch adds the detailed corrleation between sub-blocks and VDD_INT power line for Exynos5433. VDD_INT provided the power source to INT (Internal) block. Signed-off-by: Chanwoo Choi Signed-off-by: MyungJoo Ham --- Documentation/devicetree/bindings/devfreq/exynos-bus.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index d3ec8e676b6b..d085ef90d27c 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: |--- FSYS |--- FSYS2 +- In case of Exynos5433, there is VDD_INT power line as following: + VDD_INT |--- G2D (parent device) + |--- MSCL + |--- GSCL + |--- JPEG + |--- MFC + |--- HEVC + |--- BUS0 + |--- BUS1 + |--- BUS2 + |--- PERIS (Fixed clock rate) + |--- PERIC (Fixed clock rate) + |--- FSYS (Fixed clock rate) + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to -- cgit v1.2.3 From 330d432bc3a73cd0db273add46b592f57312ea1f Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Fri, 13 Jan 2017 05:35:37 -0200 Subject: [media] Documentation: devicetree: move shared property used by rc into a common place Most IR drivers uses the same label to identify the scancode/key table they used by multiple bindings and lack explanation well. So move the shared property into a common place and give better explanation. Signed-off-by: Sean Wang Acked-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/gpio-ir-receiver.txt | 3 +- .../devicetree/bindings/media/hix5hd2-ir.txt | 2 +- Documentation/devicetree/bindings/media/rc.txt | 116 +++++++++++++++++++++ .../devicetree/bindings/media/sunxi-ir.txt | 2 +- 4 files changed, 120 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/rc.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt b/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt index 56e726ef4bf2..58261fb7b408 100644 --- a/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt +++ b/Documentation/devicetree/bindings/media/gpio-ir-receiver.txt @@ -5,7 +5,8 @@ Required properties: - gpios: specifies GPIO used for IR signal reception. Optional properties: - - linux,rc-map-name: Linux specific remote control map name. + - linux,rc-map-name: see rc.txt file in the same + directory. Example node: diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt index 54e1bede6244..13ebc0fac9ea 100644 --- a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt +++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt @@ -10,7 +10,7 @@ Required properties: - clocks: clock phandle and specifier pair. Optional properties: - - linux,rc-map-name : Remote control map name. + - linux,rc-map-name: see rc.txt file in the same directory. - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files. Provide correct clocks instead. diff --git a/Documentation/devicetree/bindings/media/rc.txt b/Documentation/devicetree/bindings/media/rc.txt new file mode 100644 index 000000000000..0d16d14ccd2a --- /dev/null +++ b/Documentation/devicetree/bindings/media/rc.txt @@ -0,0 +1,116 @@ +The following properties are common to the infrared remote controllers: + +- linux,rc-map-name: string, specifies the scancode/key mapping table + defined in-kernel for the remote controller. Support values are: + * "rc-adstech-dvb-t-pci" + * "rc-alink-dtu-m" + * "rc-anysee" + * "rc-apac-viewcomp" + * "rc-asus-pc39" + * "rc-asus-ps3-100" + * "rc-ati-tv-wonder-hd-600" + * "rc-ati-x10" + * "rc-avermedia-a16d" + * "rc-avermedia-cardbus" + * "rc-avermedia-dvbt" + * "rc-avermedia-m135a" + * "rc-avermedia-m733a-rm-k6" + * "rc-avermedia-rm-ks" + * "rc-avermedia" + * "rc-avertv-303" + * "rc-azurewave-ad-tu700" + * "rc-behold-columbus" + * "rc-behold" + * "rc-budget-ci-old" + * "rc-cec" + * "rc-cinergy-1400" + * "rc-cinergy" + * "rc-delock-61959" + * "rc-dib0700-nec" + * "rc-dib0700-rc5" + * "rc-digitalnow-tinytwin" + * "rc-digittrade" + * "rc-dm1105-nec" + * "rc-dntv-live-dvbt-pro" + * "rc-dntv-live-dvb-t" + * "rc-dtt200u" + * "rc-dvbsky" + * "rc-empty" + * "rc-em-terratec" + * "rc-encore-enltv2" + * "rc-encore-enltv-fm53" + * "rc-encore-enltv" + * "rc-evga-indtube" + * "rc-eztv" + * "rc-flydvb" + * "rc-flyvideo" + * "rc-fusionhdtv-mce" + * "rc-gadmei-rm008z" + * "rc-genius-tvgo-a11mce" + * "rc-gotview7135" + * "rc-hauppauge" + * "rc-imon-mce" + * "rc-imon-pad" + * "rc-iodata-bctv7e" + * "rc-it913x-v1" + * "rc-it913x-v2" + * "rc-kaiomy" + * "rc-kworld-315u" + * "rc-kworld-pc150u" + * "rc-kworld-plus-tv-analog" + * "rc-leadtek-y04g0051" + * "rc-lirc" + * "rc-lme2510" + * "rc-manli" + * "rc-medion-x10" + * "rc-medion-x10-digitainer" + * "rc-medion-x10-or2x" + * "rc-msi-digivox-ii" + * "rc-msi-digivox-iii" + * "rc-msi-tvanywhere-plus" + * "rc-msi-tvanywhere" + * "rc-nebula" + * "rc-nec-terratec-cinergy-xs" + * "rc-norwood" + * "rc-npgtech" + * "rc-pctv-sedna" + * "rc-pinnacle-color" + * "rc-pinnacle-grey" + * "rc-pinnacle-pctv-hd" + * "rc-pixelview-new" + * "rc-pixelview" + * "rc-pixelview-002t" + * "rc-pixelview-mk12" + * "rc-powercolor-real-angel" + * "rc-proteus-2309" + * "rc-purpletv" + * "rc-pv951" + * "rc-hauppauge" + * "rc-rc5-tv" + * "rc-rc6-mce" + * "rc-real-audio-220-32-keys" + * "rc-reddo" + * "rc-snapstream-firefly" + * "rc-streamzap" + * "rc-tbs-nec" + * "rc-technisat-ts35" + * "rc-technisat-usb2" + * "rc-terratec-cinergy-c-pci" + * "rc-terratec-cinergy-s2-hd" + * "rc-terratec-cinergy-xs" + * "rc-terratec-slim" + * "rc-terratec-slim-2" + * "rc-tevii-nec" + * "rc-tivo" + * "rc-total-media-in-hand" + * "rc-total-media-in-hand-02" + * "rc-trekstor" + * "rc-tt-1500" + * "rc-twinhan-dtv-cab-ci" + * "rc-twinhan1027" + * "rc-videomate-k100" + * "rc-videomate-s350" + * "rc-videomate-tv-pvr" + * "rc-winfast" + * "rc-winfast-usbii-deluxe" + * "rc-su3000" diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt index 1811a067c72c..302a0b183cb8 100644 --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt @@ -9,7 +9,7 @@ Required properties: - reg : should contain IO map address for IR. Optional properties: -- linux,rc-map-name : Remote control map name. +- linux,rc-map-name: see rc.txt file in the same directory. - resets : phandle + reset specifier pair Example: -- cgit v1.2.3 From 2b4883d00baac8cde86ce8fa1fe2fe92bc05ab33 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Fri, 13 Jan 2017 05:35:38 -0200 Subject: [media] Documentation: devicetree: Add document bindings for mtk-cir This patch adds documentation for devicetree bindings for consumer Mediatek IR controller. Signed-off-by: Sean Wang Acked-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/mtk-cir.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mtk-cir.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/mtk-cir.txt b/Documentation/devicetree/bindings/media/mtk-cir.txt new file mode 100644 index 000000000000..2be2005577d6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mtk-cir.txt @@ -0,0 +1,24 @@ +Device-Tree bindings for Mediatek consumer IR controller +found in Mediatek SoC family + +Required properties: +- compatible : "mediatek,mt7623-cir" +- clocks : list of clock specifiers, corresponding to + entries in clock-names property; +- clock-names : should contain "clk" entries; +- interrupts : should contain IR IRQ number; +- reg : should contain IO map address for IR. + +Optional properties: +- linux,rc-map-name : see rc.txt file in the same directory. + +Example: + +cir: cir@10013000 { + compatible = "mediatek,mt7623-cir"; + reg = <0 0x10013000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IRRX>; + clock-names = "clk"; + linux,rc-map-name = "rc-rc6-mce"; +}; -- cgit v1.2.3 From faa3185114f7d64d5e731dbc890f115f49d52046 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 7 Dec 2016 16:30:24 -0200 Subject: [media] dt-bindings: add TI VPIF documentation Acked-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Kevin Hilman Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/ti,da850-vpif.txt | 83 ++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/ti,da850-vpif.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/ti,da850-vpif.txt b/Documentation/devicetree/bindings/media/ti,da850-vpif.txt new file mode 100644 index 000000000000..6d25d7f23d26 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,da850-vpif.txt @@ -0,0 +1,83 @@ +Texas Instruments VPIF +---------------------- + +The TI Video Port InterFace (VPIF) is the primary component for video +capture and display on the DA850/AM18x family of TI DaVinci/Sitara +SoCs. + +TI Document reference: SPRUH82C, Chapter 35 +http://www.ti.com/lit/pdf/spruh82 + +Required properties: +- compatible: must be "ti,da850-vpif" +- reg: physical base address and length of the registers set for the device; +- interrupts: should contain IRQ line for the VPIF + +Video Capture: + +VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a +single 16-bit channel. It should contain at least one port child node +with child 'endpoint' node. Please refer to the bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example using 2 8-bit input channels, one of which is connected to an +I2C-connected TVP5147 decoder: + + vpif: vpif@217000 { + compatible = "ti,da850-vpif"; + reg = <0x217000 0x1000>; + interrupts = <92>; + + port { + vpif_ch0: endpoint@0 { + reg = <0>; + bus-width = <8>; + remote-endpoint = <&composite>; + }; + + vpif_ch1: endpoint@1 { + reg = <1>; + bus-width = <8>; + data-shift = <8>; + }; + }; + }; + +[ ... ] + +&i2c0 { + + tvp5147@5d { + compatible = "ti,tvp5147"; + reg = <0x5d>; + status = "okay"; + + port { + composite: endpoint { + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + + /* VPIF channel 0 (lower 8-bits) */ + remote-endpoint = <&vpif_ch0>; + bus-width = <8>; + }; + }; + }; +}; + + +Alternatively, an example when the bus is configured as a single +16-bit input (e.g. for raw-capture mode): + + vpif: vpif@217000 { + compatible = "ti,da850-vpif"; + reg = <0x217000 0x1000>; + interrupts = <92>; + + port { + vpif_ch0: endpoint { + bus-width = <16>; + }; + }; + }; -- cgit v1.2.3 From 67c5900658fbe8210e47a8f8b09671af2f941849 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 20 Jan 2017 12:00:19 -0200 Subject: [media] dt-bindings: Add a binding for Video Data Order Adapter Add a DT binding documentation for the Video Data Order Adapter (VDOA) of the Freescale i.MX6 SoC. Also, add the compatible property and correct clock to the device tree to match the documentation. Signed-off-by: Philipp Zabel Signed-off-by: Michael Tretter Acked-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/fsl-vdoa.txt | 21 +++++++++++++++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 2 ++ 2 files changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/fsl-vdoa.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/fsl-vdoa.txt b/Documentation/devicetree/bindings/media/fsl-vdoa.txt new file mode 100644 index 000000000000..6c5628530bb7 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl-vdoa.txt @@ -0,0 +1,21 @@ +Freescale Video Data Order Adapter +================================== + +The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose +is to reorder video data from the macroblock tiled order produced by the CODA +960 VPU to the conventional raster-scan order for scanout. + +Required properties: +- compatible: must be "fsl,imx6q-vdoa" +- reg: the register base and size for the device registers +- interrupts: the VDOA interrupt +- clocks: the vdoa clock + +Example: + +vdoa@21e4000 { + compatible = "fsl,imx6q-vdoa"; + reg = <0x021e4000 0x4000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; +}; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 53e6e63cbb02..61569c86d28e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1157,8 +1157,10 @@ }; vdoa@021e4000 { + compatible = "fsl,imx6q-vdoa"; reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; }; uart2: serial@021e8000 { -- cgit v1.2.3 From ded9a92a626d69fc6891293d58e44d96eb7e34a9 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 14 Nov 2016 16:30:40 -0200 Subject: [media] media: et8ek8: add device tree binding documentation Add device tree binding documentation for toshiba et8ek8 sensor. Signed-off-by: Ivaylo Dimitrov Signed-off-by: Pavel Machek Acked-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../bindings/media/i2c/toshiba,et8ek8.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt new file mode 100644 index 000000000000..0b7b6a4d84ff --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt @@ -0,0 +1,48 @@ +Toshiba et8ek8 5MP sensor + +Toshiba et8ek8 5MP sensor is an image sensor found in Nokia N900 device + +More detailed documentation can be found in +Documentation/devicetree/bindings/media/video-interfaces.txt . + + +Mandatory properties +-------------------- + +- compatible: "toshiba,et8ek8" +- reg: I2C address (0x3e, or an alternative address) +- vana-supply: Analogue voltage supply (VANA), 2.8 volts +- clocks: External clock to the sensor +- clock-frequency: Frequency of the external clock to the sensor. Camera + driver will set this frequency on the external clock. The clock frequency is + a pre-determined frequency known to be suitable to the board. +- reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor + is in hardware standby mode when the signal is in the low state. + + +Endpoint node mandatory properties +---------------------------------- + +- remote-endpoint: A phandle to the bus receiver's endpoint node. + + +Example +------- + +&i2c3 { + clock-frequency = <400000>; + + cam1: camera@3e { + compatible = "toshiba,et8ek8"; + reg = <0x3e>; + vana-supply = <&vaux4>; + clocks = <&isp 0>; + clock-frequency = <9600000>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ + port { + csi_cam1: endpoint { + remote-endpoint = <&csi_out1>; + }; + }; + }; +}; -- cgit v1.2.3 From 031d3e18f31749dd34a41c886a578a07d2abbed9 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Jan 2017 19:21:12 -0200 Subject: [media] Documentation: devicetree: meson-ir: "linux,rc-map-name" is supported The driver already parses the "linux,rc-map-name" property. Add this information to the documentation so .dts maintainers don't have to look it up in the source-code. Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/meson-ir.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt b/Documentation/devicetree/bindings/media/meson-ir.txt index e7e3f3c4fc8f..efd9d29a8f10 100644 --- a/Documentation/devicetree/bindings/media/meson-ir.txt +++ b/Documentation/devicetree/bindings/media/meson-ir.txt @@ -8,6 +8,9 @@ Required properties: - reg : physical base address and length of the device registers - interrupts : a single specifier for the interrupt from the device +Optional properties: + - linux,rc-map-name: see rc.txt file in the same directory. + Example: ir-receiver@c8100480 { -- cgit v1.2.3 From 7a6628b5c321343647bcb8d79cb0d21222597ca5 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Jan 2017 19:13:42 -0200 Subject: [media] Documentation: devicetree: add the RC map name of the geekbox remote Keep the list up to date with include/media/rc-map.h Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/rc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/rc.txt b/Documentation/devicetree/bindings/media/rc.txt index 0d16d14ccd2a..d3e7a012bfda 100644 --- a/Documentation/devicetree/bindings/media/rc.txt +++ b/Documentation/devicetree/bindings/media/rc.txt @@ -46,6 +46,7 @@ The following properties are common to the infrared remote controllers: * "rc-flyvideo" * "rc-fusionhdtv-mce" * "rc-gadmei-rm008z" + * "rc-geekbox" * "rc-genius-tvgo-a11mce" * "rc-gotview7135" * "rc-hauppauge" -- cgit v1.2.3 From 0ad4c07edd413cb64abed217355d51af3649c5a3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 2 Feb 2017 15:43:57 -0800 Subject: regulator: cpcap: Add basic regulator support Many Motorola phones like droid 4 are using a custom PMIC called CPCAP or 6556002. This PMIC is used with several SoCs, I've noticed at least omap3, omap4 and Tegra2 based Motorola phones and tablets using it. Cc: devicetree@vger.kernel.org Cc: Marcel Partap Cc: Michael Scott Cc: Rob Herring Signed-off-by: Tony Lindgren Signed-off-by: Mark Brown --- .../bindings/regulator/cpcap-regulator.txt | 34 ++ drivers/regulator/Kconfig | 7 + drivers/regulator/Makefile | 1 + drivers/regulator/cpcap-regulator.c | 464 +++++++++++++++++++++ 4 files changed, 506 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/cpcap-regulator.txt create mode 100644 drivers/regulator/cpcap-regulator.c (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt b/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt new file mode 100644 index 000000000000..675f4437ce92 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/cpcap-regulator.txt @@ -0,0 +1,34 @@ +Motorola CPCAP PMIC voltage regulators +------------------------------------ + +Requires node properties: +- "compatible" value one of: + "motorola,cpcap-regulator" + "motorola,mapphone-cpcap-regulator" + +Required regulator properties: +- "regulator-name" +- "regulator-enable-ramp-delay" +- "regulator-min-microvolt" +- "regulator-max-microvolt" + +Optional regulator properties: +- "regulator-boot-on" + +See Documentation/devicetree/bindings/regulator/regulator.txt +for more details about the regulator properties. + +Example: + +cpcap_regulator: regulator { + compatible = "motorola,cpcap-regulator"; + + cpcap_regulators: regulators { + sw5: SW5 { + regulator-min-microvolt = <5050000>; + regulator-max-microvolt = <5050000>; + regulator-enable-ramp-delay = <50000>; + regulator-boot-on; + }; + }; +}; diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 936f7ccc9736..be06eb29c681 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -163,6 +163,13 @@ config REGULATOR_BCM590XX BCM590xx PMUs. This will enable support for the software controllable LDO/Switching regulators. +config REGULATOR_CPCAP + tristate "Motorola CPCAP regulator" + depends on MFD_CPCAP + help + Say y here for CPCAP regulator found on some Motorola phones + and tablets such as Droid 4. + config REGULATOR_DA903X tristate "Dialog Semiconductor DA9030/DA9034 regulators" depends on PMIC_DA903X diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 14294692beb9..ef7725e2592a 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o obj-$(CONFIG_REGULATOR_88PM800) += 88pm800.o obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o +obj-$(CONFIG_REGULATOR_CPCAP) += cpcap-regulator.o obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o obj-$(CONFIG_REGULATOR_AB8500) += ab8500-ext.o ab8500.o diff --git a/drivers/regulator/cpcap-regulator.c b/drivers/regulator/cpcap-regulator.c new file mode 100644 index 000000000000..cc98aceed1c1 --- /dev/null +++ b/drivers/regulator/cpcap-regulator.c @@ -0,0 +1,464 @@ +/* + * Motorola CPCAP PMIC regulator driver + * + * Based on cpcap-regulator.c from Motorola Linux kernel tree + * Copyright (C) 2009-2011 Motorola, Inc. + * + * Rewritten for mainline kernel to use device tree and regmap + * Copyright (C) 2017 Tony Lindgren + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Resource assignment register bits. These seem to control the state + * idle modes adn are used at least for omap4. + */ + +/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */ +#define CPCAP_BIT_VSDIO_SEL BIT(15) +#define CPCAP_BIT_VDIG_SEL BIT(14) +#define CPCAP_BIT_VCAM_SEL BIT(13) +#define CPCAP_BIT_SW6_SEL BIT(12) +#define CPCAP_BIT_SW5_SEL BIT(11) +#define CPCAP_BIT_SW4_SEL BIT(10) +#define CPCAP_BIT_SW3_SEL BIT(9) +#define CPCAP_BIT_SW2_SEL BIT(8) +#define CPCAP_BIT_SW1_SEL BIT(7) + +/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */ +#define CPCAP_BIT_VUSBINT2_SEL BIT(15) +#define CPCAP_BIT_VUSBINT1_SEL BIT(14) +#define CPCAP_BIT_VVIB_SEL BIT(13) +#define CPCAP_BIT_VWLAN1_SEL BIT(12) +#define CPCAP_BIT_VRF1_SEL BIT(11) +#define CPCAP_BIT_VHVIO_SEL BIT(10) +#define CPCAP_BIT_VDAC_SEL BIT(9) +#define CPCAP_BIT_VUSB_SEL BIT(8) +#define CPCAP_BIT_VSIM_SEL BIT(7) +#define CPCAP_BIT_VRFREF_SEL BIT(6) +#define CPCAP_BIT_VPLL_SEL BIT(5) +#define CPCAP_BIT_VFUSE_SEL BIT(4) +#define CPCAP_BIT_VCSI_SEL BIT(3) +#define CPCAP_BIT_SPARE_14_2 BIT(2) +#define CPCAP_BIT_VWLAN2_SEL BIT(1) +#define CPCAP_BIT_VRF2_SEL BIT(0) + +/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */ +#define CPCAP_BIT_VAUDIO_SEL BIT(0) + +/* + * Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic, + * and not limited to audio regulator. Let's use the Motorola kernel + * naming for now until we have a better understanding of the other + * enable register bits. No idea why BIT(3) is not defined. + */ +#define CPCAP_BIT_AUDIO_LOW_PWR BIT(6) +#define CPCAP_BIT_AUD_LOWPWR_SPEED BIT(5) +#define CPCAP_BIT_VAUDIOPRISTBY BIT(4) +#define CPCAP_BIT_VAUDIO_MODE1 BIT(2) +#define CPCAP_BIT_VAUDIO_MODE0 BIT(1) +#define CPCAP_BIT_V_AUDIO_EN BIT(0) + +/* + * Off mode configuration bit. Used currently only by SW5 on omap4. There's + * the following comment in Motorola Linux kernel tree for it: + * + * When set in the regulator mode, the regulator assignment will be changed + * to secondary when the regulator is disabled. The mode will be set back to + * primary when the regulator is turned on. + */ +#define CPCAP_REG_OFF_MODE_SEC BIT(15) + +/** + * SoC specific configuraion for CPCAP regulator. There are at least three + * different SoCs each with their own parameters: omap3, omap4 and tegra2. + * + * The assign_reg and assign_mask seem to allow toggling between primary + * and secondary mode that at least omap4 uses for off mode. + */ +struct cpcap_regulator { + struct regulator_desc rdesc; + const u16 assign_reg; + const u16 assign_mask; + const u16 vsel_shift; +}; + +#define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl, \ + mode_mask, volt_mask, volt_shft, \ + mode_val, off_val, volt_trans_time) { \ + .rdesc = { \ + .name = #_ID, \ + .of_match = of_match_ptr(#_ID), \ + .ops = &cpcap_regulator_ops, \ + .regulators_node = of_match_ptr("regulators"), \ + .type = REGULATOR_VOLTAGE, \ + .id = CPCAP_##_ID, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(val_tbl), \ + .volt_table = (val_tbl), \ + .vsel_reg = (reg), \ + .vsel_mask = (volt_mask), \ + .enable_reg = (reg), \ + .enable_mask = (mode_mask), \ + .enable_val = (mode_val), \ + .disable_val = (off_val), \ + .ramp_delay = (volt_trans_time), \ + }, \ + .assign_reg = (assignment_reg), \ + .assign_mask = (assignment_mask), \ + .vsel_shift = (volt_shft), \ +} + +struct cpcap_ddata { + struct regmap *reg; + struct device *dev; + const struct cpcap_regulator *soc; +}; + +enum cpcap_regulator_id { + CPCAP_SW1, + CPCAP_SW2, + CPCAP_SW3, + CPCAP_SW4, + CPCAP_SW5, + CPCAP_SW6, + CPCAP_VCAM, + CPCAP_VCSI, + CPCAP_VDAC, + CPCAP_VDIG, + CPCAP_VFUSE, + CPCAP_VHVIO, + CPCAP_VSDIO, + CPCAP_VPLL, + CPCAP_VRF1, + CPCAP_VRF2, + CPCAP_VRFREF, + CPCAP_VWLAN1, + CPCAP_VWLAN2, + CPCAP_VSIM, + CPCAP_VSIMCARD, + CPCAP_VVIB, + CPCAP_VUSB, + CPCAP_VAUDIO, + CPCAP_NR_REGULATORS, +}; + +/* + * We need to also configure regulator idle mode for SoC off mode if + * CPCAP_REG_OFF_MODE_SEC is set. + */ +static int cpcap_regulator_enable(struct regulator_dev *rdev) +{ + struct cpcap_regulator *regulator = rdev_get_drvdata(rdev); + int error, ignore; + + error = regulator_enable_regmap(rdev); + if (error) + return error; + + if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) { + error = regmap_update_bits(rdev->regmap, regulator->assign_reg, + regulator->assign_mask, + regulator->assign_mask); + if (error) + ignore = regulator_disable_regmap(rdev); + } + + return error; +} + +/* + * We need to also configure regulator idle mode for SoC off mode if + * CPCAP_REG_OFF_MODE_SEC is set. + */ +static int cpcap_regulator_disable(struct regulator_dev *rdev) +{ + struct cpcap_regulator *regulator = rdev_get_drvdata(rdev); + int error, ignore; + + if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) { + error = regmap_update_bits(rdev->regmap, regulator->assign_reg, + regulator->assign_mask, 0); + if (error) + return error; + } + + error = regulator_disable_regmap(rdev); + if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) { + ignore = regmap_update_bits(rdev->regmap, regulator->assign_reg, + regulator->assign_mask, + regulator->assign_mask); + } + + return error; +} + +static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev) +{ + int value; + + regmap_read(rdev->regmap, rdev->desc->enable_reg, &value); + + if (!(value & CPCAP_BIT_AUDIO_LOW_PWR)) + return REGULATOR_MODE_STANDBY; + + return REGULATOR_MODE_NORMAL; +} + +static int cpcap_regulator_set_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + int value; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + value = CPCAP_BIT_AUDIO_LOW_PWR; + break; + case REGULATOR_MODE_STANDBY: + value = 0; + break; + default: + return -EINVAL; + } + + return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + CPCAP_BIT_AUDIO_LOW_PWR, value); +} + +static struct regulator_ops cpcap_regulator_ops = { + .enable = cpcap_regulator_enable, + .disable = cpcap_regulator_disable, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_mode = cpcap_regulator_get_mode, + .set_mode = cpcap_regulator_set_mode, +}; + +static const unsigned int unknown_val_tbl[] = { 0, }; +static const unsigned int sw5_val_tbl[] = { 0, 5050000, }; +static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000, + 2900000, }; +static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, }; +static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000, + 2500000,}; +static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000, + 1875000, }; +static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000, + 1800000, 1900000, 2000000, + 2100000, 2200000, 2300000, + 2400000, 2500000, 2600000, + 2700000, 3150000, }; +static const unsigned int vhvio_val_tbl[] = { 2775000, }; +static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000, + 2600000, 2700000, 2800000, + 2900000, 3000000, }; +static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000, + 1800000, }; +/* Quirk: 2775000 is before 2500000 for vrf1 regulator */ +static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, }; +static const unsigned int vrf2_val_tbl[] = { 0, 2775000, }; +static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, }; +static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, }; +static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, + 3300000, }; +static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, }; +static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, }; +static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000, + 3000000, }; +static const unsigned int vusb_val_tbl[] = { 0, 3300000, }; +static const unsigned int vaudio_val_tbl[] = { 0, 2775000, }; + +/** + * SoC specific configuration for omap4. The data below is comes from Motorola + * Linux kernel tree. It's basically the values of cpcap_regltr_data, + * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see + * CPCAP_REG macro above. + * + * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and + * VSIMCARD have a shared resource assignment bit. + */ +static struct cpcap_regulator omap4_regulators[] = { + CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW1_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW2_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW3_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW4_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW5_SEL, sw5_val_tbl, + 0x28, 0, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0), + CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2, + CPCAP_BIT_SW6_SEL, unknown_val_tbl, + 0, 0, 0, 0, 0, 0), + CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2, + CPCAP_BIT_VCAM_SEL, vcam_val_tbl, + 0x87, 0x30, 4, 0x3, 0, 420), + CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VCSI_SEL, vcsi_val_tbl, + 0x47, 0x10, 4, 0x43, 0x41, 350), + CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VDAC_SEL, vdac_val_tbl, + 0x87, 0x30, 4, 0x3, 0, 420), + CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2, + CPCAP_BIT_VDIG_SEL, vdig_val_tbl, + 0x87, 0x30, 4, 0x82, 0, 420), + CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl, + 0x80, 0xf, 0, 0x80, 0, 420), + CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl, + 0x17, 0, 0, 0, 0x12, 0), + CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2, + CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl, + 0x87, 0x38, 3, 0x82, 0, 420), + CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VPLL_SEL, vpll_val_tbl, + 0x43, 0x18, 3, 0x2, 0, 420), + CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VRF1_SEL, vrf1_val_tbl, + 0xac, 0x2, 1, 0x4, 0, 10), + CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VRF2_SEL, vrf2_val_tbl, + 0x23, 0x8, 3, 0, 0, 10), + CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl, + 0x23, 0x8, 3, 0, 0, 420), + CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl, + 0x47, 0x10, 4, 0, 0, 420), + CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl, + 0x20c, 0xc0, 6, 0x20c, 0, 420), + CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, + 0xffff, vsim_val_tbl, + 0x23, 0x8, 3, 0x3, 0, 420), + CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, + 0xffff, vsimcard_val_tbl, + 0x1e80, 0x8, 3, 0x1e00, 0, 420), + CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VVIB_SEL, vvib_val_tbl, + 0x1, 0xc, 2, 0x1, 0, 500), + CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3, + CPCAP_BIT_VUSB_SEL, vusb_val_tbl, + 0x11c, 0x40, 6, 0xc, 0, 0), + CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4, + CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl, + 0x16, 0x1, 0, 0x4, 0, 0), + { /* sentinel */ }, +}; + +static const struct of_device_id cpcap_regulator_id_table[] = { + { + .compatible = "motorola,cpcap-regulator", + }, + { + .compatible = "motorola,mapphone-cpcap-regulator", + .data = omap4_regulators, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table); + +static int cpcap_regulator_probe(struct platform_device *pdev) +{ + struct cpcap_ddata *ddata; + const struct of_device_id *match; + struct regulator_config config; + struct regulator_init_data init_data; + int i; + + match = of_match_device(of_match_ptr(cpcap_regulator_id_table), + &pdev->dev); + if (!match) + return -EINVAL; + + if (!match->data) { + dev_err(&pdev->dev, "no configuration data found\n"); + + return -ENODEV; + } + + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->reg = dev_get_regmap(pdev->dev.parent, NULL); + if (!ddata->reg) + return -ENODEV; + + ddata->dev = &pdev->dev; + ddata->soc = match->data; + platform_set_drvdata(pdev, ddata); + + memset(&config, 0, sizeof(config)); + memset(&init_data, 0, sizeof(init_data)); + config.dev = &pdev->dev; + config.regmap = ddata->reg; + config.init_data = &init_data; + + for (i = 0; i < CPCAP_NR_REGULATORS; i++) { + const struct cpcap_regulator *regulator = &ddata->soc[i]; + struct regulator_dev *rdev; + + if (!regulator->rdesc.name) + break; + + if (regulator->rdesc.volt_table == unknown_val_tbl) + continue; + + config.driver_data = (void *)regulator; + rdev = devm_regulator_register(&pdev->dev, + ®ulator->rdesc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register regulator %s\n", + regulator->rdesc.name); + + return PTR_ERR(rdev); + } + } + + return 0; +} + +static struct platform_driver cpcap_regulator_driver = { + .probe = cpcap_regulator_probe, + .driver = { + .name = "cpcap-regulator", + .of_match_table = of_match_ptr(cpcap_regulator_id_table), + }, +}; + +module_platform_driver(cpcap_regulator_driver); + +MODULE_ALIAS("platform:cpcap-regulator"); +MODULE_AUTHOR("Tony Lindgren "); +MODULE_DESCRIPTION("CPCAP regulator driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 17db9f386632c9c9182a3318b89b742be08c1c2a Mon Sep 17 00:00:00 2001 From: Hans Holmberg Date: Fri, 3 Feb 2017 15:29:12 +0100 Subject: regulator: gpio: correct default type The driver defaults to voltage, not current, type so correct this in the device tree binding documentation. Signed-off-by: Hans Holmberg Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/gpio-regulator.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt index e5cac1e0ca8a..dd1ed789728e 100644 --- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt @@ -13,7 +13,7 @@ Optional properties: - startup-delay-us : Startup time in microseconds. - enable-active-high : Polarity of GPIO is active high (default is low). - regulator-type : Specifies what is being regulated, must be either - "voltage" or "current", defaults to current. + "voltage" or "current", defaults to voltage. Any property defined as part of the core regulator binding defined in regulator.txt can also be used. -- cgit v1.2.3 From 117bd6e842a8d52e48f0d18be260a05bf96dc854 Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Tue, 31 Jan 2017 14:14:20 +0100 Subject: pinctrl: Add STM32 pinctrl driver DT bindings Add compatible sting for stm32h743 MCU. Signed-off-by: Alexandre TORGUE Acked-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index b24583aa34c3..620c09b3d801 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -8,8 +8,9 @@ controllers onto these pads. Pin controller node: Required properies: - compatible: value should be one of the following: - (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + "st,stm32f429-pinctrl" + "st,stm32f746-pinctrl" + "st,stm32h743-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to -- cgit v1.2.3 From d4168be73c8fdc3e9cdc61aa4b513e6c9b7bcf10 Mon Sep 17 00:00:00 2001 From: Alexandre TORGUE Date: Fri, 27 Jan 2017 17:15:16 +0100 Subject: pinctrl: Amend bindings for STM32 pinctrl Adds "ngpios" and "gpio-ranges" bindings definition. Signed-off-by: Alexandre TORGUE Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/pinctrl/st,stm32-pinctrl.txt | 54 +++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 620c09b3d801..eac20aa33907 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -38,8 +38,23 @@ Optional properties: - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node which includes IRQ mux selection register, and the offset of the IRQ mux selection register. + - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less + than 16). + - gpio-ranges: Define a dedicated mapping between a pin-controller and + a gpio controller. Format is <&phandle a b c> with: + -(phandle): phandle of pin-controller. + -(a): gpio base offset in range. + -(b): pin base offset in range. + -(c): gpio count in range + This entry has to be used either if there are holes inside a bank: + GPIOB0/B1/B2/B14/B15 (see example 2) + or if banks are not contiguous: + GPIOA/B/C/E... + NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller + have to use a "gpio-ranges" entry. + More details in Documentation/devicetree/bindings/gpio/gpio.txt. -Example: +Example 1: #include ... @@ -61,6 +76,43 @@ Example: pin-functions nodes follow... }; +Example 2: +#include +... + + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOB"; + ngpios = 4; + gpio-ranges = <&pinctrl 0 16 3>, + <&pinctrl 14 30 2>; + }; + + + ... + pin-functions nodes follow... + }; + + Contents of function subnode node: ---------------------------------- Subnode format -- cgit v1.2.3 From ce0b001bda3a216e6df234e58bc2adf2dbe32858 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Thu, 2 Feb 2017 12:59:44 -0200 Subject: [media] Documentation: DT: add bindings for ST DELTA This patch adds DT binding documentation for STMicroelectronics DELTA V4L2 video decoder. Acked-by: Peter Griffin Signed-off-by: Hugues Fruchet Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/st,st-delta.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,st-delta.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/st,st-delta.txt b/Documentation/devicetree/bindings/media/st,st-delta.txt new file mode 100644 index 000000000000..a538ab30a617 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,st-delta.txt @@ -0,0 +1,17 @@ +* STMicroelectronics DELTA multi-format video decoder + +Required properties: +- compatible: should be "st,st-delta". +- clocks: from common clock binding: handle hardware IP needed clocks, the + number of clocks may depend on the SoC type. + See ../clock/clock-bindings.txt for details. +- clock-names: names of the clocks listed in clocks property in the same order. + +Example: + delta0 { + compatible = "st,st-delta"; + clock-names = "delta", "delta-st231", "delta-flash-promip"; + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; + }; -- cgit v1.2.3 From 953a0f18337406ab041252ce5a62db5d173bee5f Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Thu, 9 Feb 2017 09:35:49 -0600 Subject: Documentation: dt: add bindings for ti-cpufreq Add the device tree bindings document for the TI CPUFreq/OPP driver on AM33xx, AM43xx, DRA7xx, and AM57xx SoCs. The operating-points-v2 binding allows us to provide an opp-supported-hw property for each OPP to define when it is available. This driver is responsible for reading and parsing registers to determine which OPPs can be selectively enabled based on the specific SoC in use by matching against the opp-supported-hw data. Acked-by: Viresh Kumar Signed-off-by: Dave Gerlach Acked-by: Rob Herring Signed-off-by: Rafael J. Wysocki --- .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt new file mode 100644 index 000000000000..ba0e15ad5bd9 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt @@ -0,0 +1,128 @@ +TI CPUFreq and OPP bindings +================================ + +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx +families support different OPPs depending on the silicon variant in use. +The ti-cpufreq driver can use revision and an efuse value from the SoC to +provide the OPP framework with supported hardware information. This is +used to determine which OPPs from the operating-points-v2 table get enabled +when it is parsed by the OPP framework. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use. + +In 'operating-points-v2' table: +- compatible: Should be + - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs +- syscon: A phandle pointing to a syscon node representing the control module + register space of the SoC. + +Optional properties: +-------------------- +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + 1. Which revision of the SoC the OPP is supported by + 2. Which eFuse bits indicate this OPP is available + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +Example: +-------- + +/* From arch/arm/boot/dts/am33xx.dtsi */ +cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + + operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; +}; + +/* + * cpu0 has different OPPs depending on SoC revision and some on revisions + * 0x2 and 0x4 have eFuse bits that indicate if they are available or not + */ +cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + /* + * The three following nodes are marked with opp-suspend + * because they can not be enabled simultaneously on a + * single SoC. + */ + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100@275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; +}; -- cgit v1.2.3 From 4a80f77618f72f40b970d96f4e8492ea2dd6f2d9 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Fri, 6 Jan 2017 12:24:42 +0800 Subject: Documentation: synopsys-dw-mshc: add binding for fifo quirks Add fifo-addr property and fifo-watermark-quirk property to synopsys-dw-mshc bindings. It is intended to provide more dt interface to support SoCs specific configuration. Signed-off-by: Jun Nie Acked-by: Rob Herring Signed-off-by: Jaehoon Chung Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index 7fd17c3da116..bca30b69b8a1 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -75,6 +75,17 @@ Optional properties: * card-detect-delay: Delay in milli-seconds before detecting card after card insert event. The default value is 0. +* data-addr: Override fifo address with value provided by DT. The default FIFO reg + offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by + driver. If the controller does not follow this rule, please use this property + to set fifo address in device tree. + +* fifo-watermark-aligned: Data done irq is expected if data length is less than + watermark in PIO mode. But fifo watermark is requested to be aligned with data + length in some SoC so that TX/RX irq can be generated with data done irq. Add this + watermark quirk to mark this requirement and force fifo watermark setting + accordingly. + * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. @@ -102,6 +113,8 @@ board specific portions as listed below. interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; + data-addr = <0x200>; + fifo-watermark-aligned; resets = <&rst 20>; reset-names = "reset"; }; -- cgit v1.2.3 From 4c8a03c727d930b0633fa45fd8afcd1df88bb5b4 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Fri, 6 Jan 2017 12:24:45 +0800 Subject: mmc: dt-bindings: add ZTE ZX296718 MMC bindings Document the device-tree binding of ZTE MMC host on ZX296718 SoC. Signed-off-by: Jun Nie Acked-by: Rob Herring Signed-off-by: Jaehoon Chung Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/zx-dw-mshc.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt new file mode 100644 index 000000000000..eaade0e5adeb --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt @@ -0,0 +1,33 @@ +* ZTE specific extensions to the Synopsys Designware Mobile Storage + Host Controller + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the ZTE specific +extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: + +* compatible: should be + - "zte,zx296718-dw-mshc": for ZX SoCs + +Example: + + mmc1: mmc@1110000 { + compatible = "zte,zx296718-dw-mshc"; + reg = <0x01110000 0x1000>; + interrupts = ; + fifo-depth = <32>; + data-addr = <0x200>; + fifo-watermark-aligned; + bus-width = <4>; + clock-frequency = <50000000>; + clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; + clock-names = "biu", "ciu"; + num-slots = <1>; + max-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + status = "disabled"; + }; -- cgit v1.2.3 From bdf631082f7fd644bc9cf709692d285e1acf3c59 Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Fri, 6 Jan 2017 23:50:43 +0900 Subject: mmc: dt-bindings: Fix typo in mmc This patch fix some spelling typo found in devicetree/bindings/mmc. Signed-off-by: Masanari Iida Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 2 +- Documentation/devicetree/bindings/mmc/sdhci-st.txt | 2 +- Documentation/devicetree/bindings/mmc/sdhci.txt | 2 +- Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt index 7f95ec400863..50bf611a4d2c 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt @@ -17,7 +17,7 @@ Required properties: "core" - Main peripheral bus clock "clkin0" - Parent clock of internal mux "clkin1" - Other parent clock of internal mux - The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the + The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the clock rate requested by the MMC core. Example: diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt index 3cd4c43a3260..230fd696eb92 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-st.txt @@ -38,7 +38,7 @@ Optional properties: - bus-width: Number of data lines. See: Documentation/devicetree/bindings/mmc/mmc.txt. -- max-frequency: Can be 200MHz, 100Mz or 50MHz (default) and used for +- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for configuring the CCONFIG3 in the mmcss. See: Documentation/devicetree/bindings/mmc/mmc.txt. diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt index 1c95a1a555c3..0e9923a64024 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci.txt @@ -5,7 +5,7 @@ host controllers refer to the mmc[1] bindings. Optional properties: - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit - property corresponds to the bits in the sdhci capabilty register. If the bit + property corresponds to the bits in the sdhci capability register. If the bit is on in the mask then the bit is incorrect in the register and should be turned off, before applying sdhci-caps. - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index bca30b69b8a1..9cb55ca57461 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -16,7 +16,7 @@ Required Properties: each child-node representing a supported slot. There should be atleast one child node representing a card slot. The name of the child node representing the slot is recommended to be slot@n where n is the unique number of the slot - connnected to the controller. The following are optional properties which + connected to the controller. The following are optional properties which can be included in the slot child node. * reg: specifies the physical slot number. The valid values of this -- cgit v1.2.3 From e3fffc1f0b4750a2d6efc9a674b62c58477b8d20 Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Mon, 23 Jan 2017 19:08:29 -0800 Subject: devicetree: document new marvell-8xxx and pwrseq-sd8787 options Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Matt Ranostay Signed-off-by: Ulf Hansson Acked-by: Rob Herring --- .../devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt | 16 ++++++++++++++++ .../devicetree/bindings/net/wireless/marvell-8xxx.txt | 7 ++++++- 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt new file mode 100644 index 000000000000..22e9340e4ba2 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt @@ -0,0 +1,16 @@ +* Marvell SD8787 power sequence provider + +Required properties: +- compatible: must be "mmc-pwrseq-sd8787". +- powerdown-gpios: contains a power down GPIO specifier with the + default active state +- reset-gpios: contains a reset GPIO specifier with the default + active state + +Example: + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-sd8787"; + powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; + } diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt index 980b16df74c3..0854451ff91d 100644 --- a/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt +++ b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt @@ -1,4 +1,4 @@ -Marvell 8897/8997 (sd8897/sd8997/pcie8997) SDIO/PCIE devices +Marvell 8787/8897/8997 (sd8787/sd8897/sd8997/pcie8997) SDIO/PCIE devices ------ This node provides properties for controlling the Marvell SDIO/PCIE wireless device. @@ -8,6 +8,7 @@ connects the device to the system. Required properties: - compatible : should be one of the following: + * "marvell,sd8787" * "marvell,sd8897" * "marvell,sd8997" * "pci11ab,2b42" @@ -34,6 +35,9 @@ Optional properties: so that the wifi chip can wakeup host platform under certain condition. during system resume, the irq will be disabled to make sure unnecessary interrupt is not received. + - vmmc-supply: a phandle of a regulator, supplying VCC to the card + - mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*" + for documentation of MMC power sequence bindings. Example: @@ -46,6 +50,7 @@ so that firmware can wakeup host using this device side pin. &mmc3 { status = "okay"; vmmc-supply = <&wlan_en_reg>; + mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; cap-power-off-card; keep-power-in-suspend; -- cgit v1.2.3 From 62a4cdead56e5715c61aadd41ab66f49bd3170f1 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 25 Jan 2017 15:28:09 -0500 Subject: mmc: sh_mobile_sdhi: explain clock bindings In the case of a single clock source, you don't need names. However, if the controller has 2 clock sources, you need to name them correctly so the driver can find the 2nd one. The 2nd clock is for the internal card detect logic. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Ulf Hansson Reviewed-by: Wolfram Sang Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index a1650edfd2b7..4fd8b7acc510 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -25,6 +25,19 @@ Required properties: "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC +- clocks: Most controllers only have 1 clock source per channel. However, on + some variations of this controller, the internal card detection + logic that exists in this controller is sectioned off to be run by a + separate second clock source to allow the main core clock to be turned + off to save power. + If 2 clocks are specified by the hardware, you must name them as + "core" and "cd". If the controller only has 1 clock, naming is not + required. + Below is the number clocks for each supported SoC: + 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790 + R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796 + 2: R7S72100 + Optional properties: - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable - pinctrl-names: should be "default", "state_uhs" -- cgit v1.2.3 From 41efc76e0c0414d1e38a9d974a544aa80a653956 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Wed, 25 Jan 2017 12:44:13 +0100 Subject: mmc: dt: Document binding for eMMC DDR 3.3V I/O voltage support Cc: Cc: Rob Herring Signed-off-by: Ulf Hansson Reviewed-by: Shawn Lin Tested-by: Jan Glauber Tested-by: Stefan Wahren Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/mmc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 8a377827695b..c7f4a0ec48ed 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -40,6 +40,7 @@ Optional properties: - cap-mmc-hw-reset: eMMC hardware reset is supported - cap-sdio-irq: enable SDIO IRQ signalling on this interface - full-pwr-cycle: full power cycle of the card is supported +- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported -- cgit v1.2.3 From 3d33cb5ad582cef7d0c4f0397cf6a3307ce8802c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 30 Jan 2017 14:27:13 +0100 Subject: dt-bindings: mmc: sunxi: Document A64 eMMC compatible We introduced recently a new compatible to deal with the A64 eMMC controller, let's document its binding. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Acked-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt index 55cdd804cdba..7d53a799f140 100644 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt @@ -13,6 +13,7 @@ Required properties: * "allwinner,sun5i-a13-mmc" * "allwinner,sun7i-a20-mmc" * "allwinner,sun9i-a80-mmc" + * "allwinner,sun50i-a64-emmc" * "allwinner,sun50i-a64-mmc" - reg : mmc controller base registers - clocks : a list with 4 phandle + clock specifier pairs -- cgit v1.2.3 From 17f84b793c01452e8802ef80324863b8da7d900b Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 14 Feb 2017 00:31:11 +0100 Subject: spi: lantiq-ssc: add support for Lantiq SSC SPI controller This driver supports the Lantiq SSC SPI controller in master mode. This controller is found on Intel (former Lantiq) SoCs like the Danube, Falcon, xRX200, xRX300. The hardware uses two hardware FIFOs one for received and one for transferred bytes. When the driver writes data into the transmit FIFO the complete word is taken from the FIFO into a shift register. The data from this shift register is then written to the wire. This driver uses the interrupts signaling the status of the FIFOs and not the shift register. It is also possible to use the interrupts for the shift register, but they will send a signal after every word. When using the interrupts for the shift register we get a signal when the last word is written into the shift register and not when it is written to the wire. After all FIFOs are empty the driver busy waits till the hardware is not busy any more and returns the transfer status. Signed-off-by: Daniel Schwierzeck Signed-off-by: Hauke Mehrtens Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-lantiq-ssc.txt | 29 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-lantiq-ssc.c | 983 +++++++++++++++++++++ 4 files changed, 1021 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt create mode 100644 drivers/spi/spi-lantiq-ssc.c (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt new file mode 100644 index 000000000000..6069b95a883d --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt @@ -0,0 +1,29 @@ +Lantiq Synchronous Serial Controller (SSC) SPI master driver + +Required properties: +- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi" +- #address-cells: see spi-bus.txt +- #size-cells: see spi-bus.txt +- reg: address and length of the spi master registers +- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt. + + +Optional properties: +- clocks: spi clock phandle +- num-cs: see spi-bus.txt, set to 8 if unset +- base-cs: the number of the first chip select, set to 1 if unset. + +Example: + + +spi: spi@E100800 { + compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; + reg = <0xE100800 0x100>; + interrupt-parent = <&icu0>; + interrupts = <22 23 24>; + interrupt-names = "spi_rx", "spi_tx", "spi_err"; + #address-cells = <1>; + #size-cells = <1>; + num-cs = <6>; + base-cs = <1>; +}; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ec4aa252d6e8..1abba53c2334 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -415,6 +415,14 @@ config SPI_NUC900 help SPI driver for Nuvoton NUC900 series ARM SoCs +config SPI_LANTIQ_SSC + tristate "Lantiq SSC SPI controller" + depends on LANTIQ + help + This driver supports the Lantiq SSC SPI controller in master + mode. This controller is found on Intel (former Lantiq) SoCs like + the Danube, Falcon, xRX200, xRX300. + config SPI_OC_TINY tristate "OpenCores tiny SPI" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7a6b64662c82..b375a7a89216 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o obj-$(CONFIG_SPI_GPIO) += spi-gpio.o obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o obj-$(CONFIG_SPI_IMX) += spi-imx.o +obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o obj-$(CONFIG_SPI_JCORE) += spi-jcore.o obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c new file mode 100644 index 000000000000..8a626f7fccea --- /dev/null +++ b/drivers/spi/spi-lantiq-ssc.c @@ -0,0 +1,983 @@ +/* + * Copyright (C) 2011-2015 Daniel Schwierzeck + * Copyright (C) 2016 Hauke Mehrtens + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_LANTIQ +#include +#endif + +#define SPI_RX_IRQ_NAME "spi_rx" +#define SPI_TX_IRQ_NAME "spi_tx" +#define SPI_ERR_IRQ_NAME "spi_err" +#define SPI_FRM_IRQ_NAME "spi_frm" + +#define SPI_CLC 0x00 +#define SPI_PISEL 0x04 +#define SPI_ID 0x08 +#define SPI_CON 0x10 +#define SPI_STAT 0x14 +#define SPI_WHBSTATE 0x18 +#define SPI_TB 0x20 +#define SPI_RB 0x24 +#define SPI_RXFCON 0x30 +#define SPI_TXFCON 0x34 +#define SPI_FSTAT 0x38 +#define SPI_BRT 0x40 +#define SPI_BRSTAT 0x44 +#define SPI_SFCON 0x60 +#define SPI_SFSTAT 0x64 +#define SPI_GPOCON 0x70 +#define SPI_GPOSTAT 0x74 +#define SPI_FPGO 0x78 +#define SPI_RXREQ 0x80 +#define SPI_RXCNT 0x84 +#define SPI_DMACON 0xec +#define SPI_IRNEN 0xf4 +#define SPI_IRNICR 0xf8 +#define SPI_IRNCR 0xfc + +#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ +#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S) +#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ +#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S) +#define SPI_CLC_DISS BIT(1) /* Disable status bit */ +#define SPI_CLC_DISR BIT(0) /* Disable request bit */ + +#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ +#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S) +#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ +#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S) +#define SPI_ID_MOD_S 8 /* Module ID */ +#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S) +#define SPI_ID_CFG_S 5 /* DMA interface support */ +#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S) +#define SPI_ID_REV_M 0x1F /* Hardware revision number */ + +#define SPI_CON_BM_S 16 /* Data width selection */ +#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S) +#define SPI_CON_EM BIT(24) /* Echo mode */ +#define SPI_CON_IDLE BIT(23) /* Idle bit value */ +#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */ +#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ +#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ +#define SPI_CON_AEN BIT(10) /* Abort error enable */ +#define SPI_CON_REN BIT(9) /* Receive overflow error enable */ +#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ +#define SPI_CON_LB BIT(7) /* Loopback control */ +#define SPI_CON_PO BIT(6) /* Clock polarity control */ +#define SPI_CON_PH BIT(5) /* Clock phase control */ +#define SPI_CON_HB BIT(4) /* Heading control */ +#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */ +#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ + +#define SPI_STAT_RXBV_S 28 +#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S) +#define SPI_STAT_BSY BIT(13) /* Busy flag */ +#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ +#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ +#define SPI_STAT_AE BIT(10) /* Abort error flag */ +#define SPI_STAT_RE BIT(9) /* Receive error flag */ +#define SPI_STAT_TE BIT(8) /* Transmit error flag */ +#define SPI_STAT_ME BIT(7) /* Mode error flag */ +#define SPI_STAT_MS BIT(1) /* Master/slave select bit */ +#define SPI_STAT_EN BIT(0) /* Enable bit */ +#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \ + SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE) + +#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ +#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ +#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ +#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ +#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ +#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ +#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ +#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ +#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ +#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ +#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ +#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ +#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ +#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ +#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ +#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ +#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \ + SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \ + SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE) + +#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ +#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S) +#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ +#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ + +#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ +#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S) +#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ +#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ + +#define SPI_FSTAT_RXFFL_S 0 +#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S) +#define SPI_FSTAT_TXFFL_S 8 +#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S) + +#define SPI_GPOCON_ISCSBN_S 8 +#define SPI_GPOCON_INVOUTN_S 0 + +#define SPI_FGPO_SETOUTN_S 8 +#define SPI_FGPO_CLROUTN_S 0 + +#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ +#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ + +#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ +#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ +#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */ +#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ +#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ +#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ +#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ +#define SPI_IRNEN_ALL 0x1F + +struct lantiq_ssc_hwcfg { + unsigned int irnen_r; + unsigned int irnen_t; +}; + +struct lantiq_ssc_spi { + struct spi_master *master; + struct device *dev; + void __iomem *regbase; + struct clk *spi_clk; + struct clk *fpi_clk; + const struct lantiq_ssc_hwcfg *hwcfg; + + spinlock_t lock; + struct workqueue_struct *wq; + struct work_struct work; + + const u8 *tx; + u8 *rx; + unsigned int tx_todo; + unsigned int rx_todo; + unsigned int bits_per_word; + unsigned int speed_hz; + unsigned int tx_fifo_size; + unsigned int rx_fifo_size; + unsigned int base_cs; +}; + +static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg) +{ + return __raw_readl(spi->regbase + reg); +} + +static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val, + u32 reg) +{ + __raw_writel(val, spi->regbase + reg); +} + +static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, + u32 set, u32 reg) +{ + u32 val = __raw_readl(spi->regbase + reg); + + val &= ~clr; + val |= set; + __raw_writel(val, spi->regbase + reg); +} + +static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) +{ + u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); + + return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S; +} + +static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) +{ + u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); + + return fstat & SPI_FSTAT_RXFFL_M; +} + +static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) +{ + return spi->tx_fifo_size - tx_fifo_level(spi); +} + +static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) +{ + u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S; + + val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU; + lantiq_ssc_writel(spi, val, SPI_RXFCON); +} + +static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) +{ + u32 val = 1 << SPI_TXFCON_TXFITL_S; + + val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU; + lantiq_ssc_writel(spi, val, SPI_TXFCON); +} + +static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) +{ + lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON); +} + +static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) +{ + lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON); +} + +static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) +{ + lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE); +} + +static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) +{ + lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE); +} + +static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, + unsigned int max_speed_hz) +{ + u32 spi_clk, brt; + + /* + * SPI module clock is derived from FPI bus clock dependent on + * divider value in CLC.RMS which is always set to 1. + * + * f_SPI + * baudrate = -------------- + * 2 * (BR + 1) + */ + spi_clk = clk_get_rate(spi->fpi_clk) / 2; + + if (max_speed_hz > spi_clk) + brt = 0; + else + brt = spi_clk / max_speed_hz - 1; + + if (brt > 0xFFFF) + brt = 0xFFFF; + + dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", + spi_clk, max_speed_hz, brt); + + lantiq_ssc_writel(spi, brt, SPI_BRT); +} + +static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, + unsigned int bits_per_word) +{ + u32 bm; + + /* CON.BM value = bits_per_word - 1 */ + bm = (bits_per_word - 1) << SPI_CON_BM_S; + + lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON); +} + +static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, + unsigned int mode) +{ + u32 con_set = 0, con_clr = 0; + + /* + * SPI mode mapping in CON register: + * Mode CPOL CPHA CON.PO CON.PH + * 0 0 0 0 1 + * 1 0 1 0 0 + * 2 1 0 1 1 + * 3 1 1 1 0 + */ + if (mode & SPI_CPHA) + con_clr |= SPI_CON_PH; + else + con_set |= SPI_CON_PH; + + if (mode & SPI_CPOL) + con_set |= SPI_CON_PO | SPI_CON_IDLE; + else + con_clr |= SPI_CON_PO | SPI_CON_IDLE; + + /* Set heading control */ + if (mode & SPI_LSB_FIRST) + con_clr |= SPI_CON_HB; + else + con_set |= SPI_CON_HB; + + /* Set loopback mode */ + if (mode & SPI_LOOP) + con_set |= SPI_CON_LB; + else + con_clr |= SPI_CON_LB; + + lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON); +} + +static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) +{ + const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; + + /* + * Set clock divider for run mode to 1 to + * run at same frequency as FPI bus + */ + lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC); + + /* Put controller into config mode */ + hw_enter_config_mode(spi); + + /* Clear error flags */ + lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); + + /* Enable error checking, disable TX/RX */ + lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN | + SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); + + /* Setup default SPI mode */ + hw_setup_bits_per_word(spi, spi->bits_per_word); + hw_setup_clock_mode(spi, SPI_MODE_0); + + /* Enable master mode and clear error flags */ + lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS, + SPI_WHBSTATE); + + /* Reset GPIO/CS registers */ + lantiq_ssc_writel(spi, 0, SPI_GPOCON); + lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO); + + /* Enable and flush FIFOs */ + rx_fifo_reset(spi); + tx_fifo_reset(spi); + + /* Enable interrupts */ + lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E, + SPI_IRNEN); +} + +static int lantiq_ssc_setup(struct spi_device *spidev) +{ + struct spi_master *master = spidev->master; + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); + unsigned int cs = spidev->chip_select; + u32 gpocon; + + /* GPIOs are used for CS */ + if (gpio_is_valid(spidev->cs_gpio)) + return 0; + + dev_dbg(spi->dev, "using internal chipselect %u\n", cs); + + if (cs < spi->base_cs) { + dev_err(spi->dev, + "chipselect %i too small (min %i)\n", cs, spi->base_cs); + return -EINVAL; + } + + /* set GPO pin to CS mode */ + gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S); + + /* invert GPO pin */ + if (spidev->mode & SPI_CS_HIGH) + gpocon |= 1 << (cs - spi->base_cs); + + lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON); + + return 0; +} + +static int lantiq_ssc_prepare_message(struct spi_master *master, + struct spi_message *message) +{ + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); + + hw_enter_config_mode(spi); + hw_setup_clock_mode(spi, message->spi->mode); + hw_enter_active_mode(spi); + + return 0; +} + +static void hw_setup_transfer(struct lantiq_ssc_spi *spi, + struct spi_device *spidev, struct spi_transfer *t) +{ + unsigned int speed_hz = t->speed_hz; + unsigned int bits_per_word = t->bits_per_word; + u32 con; + + if (bits_per_word != spi->bits_per_word || + speed_hz != spi->speed_hz) { + hw_enter_config_mode(spi); + hw_setup_speed_hz(spi, speed_hz); + hw_setup_bits_per_word(spi, bits_per_word); + hw_enter_active_mode(spi); + + spi->speed_hz = speed_hz; + spi->bits_per_word = bits_per_word; + } + + /* Configure transmitter and receiver */ + con = lantiq_ssc_readl(spi, SPI_CON); + if (t->tx_buf) + con &= ~SPI_CON_TXOFF; + else + con |= SPI_CON_TXOFF; + + if (t->rx_buf) + con &= ~SPI_CON_RXOFF; + else + con |= SPI_CON_RXOFF; + + lantiq_ssc_writel(spi, con, SPI_CON); +} + +static int lantiq_ssc_unprepare_message(struct spi_master *master, + struct spi_message *message) +{ + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); + + flush_workqueue(spi->wq); + + /* Disable transmitter and receiver while idle */ + lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); + + return 0; +} + +static void tx_fifo_write(struct lantiq_ssc_spi *spi) +{ + const u8 *tx8; + const u16 *tx16; + const u32 *tx32; + u32 data; + unsigned int tx_free = tx_fifo_free(spi); + + while (spi->tx_todo && tx_free) { + switch (spi->bits_per_word) { + case 2 ... 8: + tx8 = spi->tx; + data = *tx8; + spi->tx_todo--; + spi->tx++; + break; + case 16: + tx16 = (u16 *) spi->tx; + data = *tx16; + spi->tx_todo -= 2; + spi->tx += 2; + break; + case 32: + tx32 = (u32 *) spi->tx; + data = *tx32; + spi->tx_todo -= 4; + spi->tx += 4; + break; + default: + WARN_ON(1); + data = 0; + break; + } + + lantiq_ssc_writel(spi, data, SPI_TB); + tx_free--; + } +} + +static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) +{ + u8 *rx8; + u16 *rx16; + u32 *rx32; + u32 data; + unsigned int rx_fill = rx_fifo_level(spi); + + while (rx_fill) { + data = lantiq_ssc_readl(spi, SPI_RB); + + switch (spi->bits_per_word) { + case 2 ... 8: + rx8 = spi->rx; + *rx8 = data; + spi->rx_todo--; + spi->rx++; + break; + case 16: + rx16 = (u16 *) spi->rx; + *rx16 = data; + spi->rx_todo -= 2; + spi->rx += 2; + break; + case 32: + rx32 = (u32 *) spi->rx; + *rx32 = data; + spi->rx_todo -= 4; + spi->rx += 4; + break; + default: + WARN_ON(1); + break; + } + + rx_fill--; + } +} + +static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) +{ + u32 data, *rx32; + u8 *rx8; + unsigned int rxbv, shift; + unsigned int rx_fill = rx_fifo_level(spi); + + /* + * In RX-only mode the bits per word value is ignored by HW. A value + * of 32 is used instead. Thus all 4 bytes per FIFO must be read. + * If remaining RX bytes are less than 4, the FIFO must be read + * differently. The amount of received and valid bytes is indicated + * by STAT.RXBV register value. + */ + while (rx_fill) { + if (spi->rx_todo < 4) { + rxbv = (lantiq_ssc_readl(spi, SPI_STAT) & + SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S; + data = lantiq_ssc_readl(spi, SPI_RB); + + shift = (rxbv - 1) * 8; + rx8 = spi->rx; + + while (rxbv) { + *rx8++ = (data >> shift) & 0xFF; + rxbv--; + shift -= 8; + spi->rx_todo--; + spi->rx++; + } + } else { + data = lantiq_ssc_readl(spi, SPI_RB); + rx32 = (u32 *) spi->rx; + + *rx32++ = data; + spi->rx_todo -= 4; + spi->rx += 4; + } + rx_fill--; + } +} + +static void rx_request(struct lantiq_ssc_spi *spi) +{ + unsigned int rxreq, rxreq_max; + + /* + * To avoid receive overflows at high clocks it is better to request + * only the amount of bytes that fits into all FIFOs. This value + * depends on the FIFO size implemented in hardware. + */ + rxreq = spi->rx_todo; + rxreq_max = spi->rx_fifo_size * 4; + if (rxreq > rxreq_max) + rxreq = rxreq_max; + + lantiq_ssc_writel(spi, rxreq, SPI_RXREQ); +} + +static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) +{ + struct lantiq_ssc_spi *spi = data; + + if (spi->tx) { + if (spi->rx && spi->rx_todo) + rx_fifo_read_full_duplex(spi); + + if (spi->tx_todo) + tx_fifo_write(spi); + else if (!tx_fifo_level(spi)) + goto completed; + } else if (spi->rx) { + if (spi->rx_todo) { + rx_fifo_read_half_duplex(spi); + + if (spi->rx_todo) + rx_request(spi); + else + goto completed; + } else { + goto completed; + } + } + + return IRQ_HANDLED; + +completed: + queue_work(spi->wq, &spi->work); + + return IRQ_HANDLED; +} + +static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) +{ + struct lantiq_ssc_spi *spi = data; + u32 stat = lantiq_ssc_readl(spi, SPI_STAT); + + if (!(stat & SPI_STAT_ERRORS)) + return IRQ_NONE; + + if (stat & SPI_STAT_RUE) + dev_err(spi->dev, "receive underflow error\n"); + if (stat & SPI_STAT_TUE) + dev_err(spi->dev, "transmit underflow error\n"); + if (stat & SPI_STAT_AE) + dev_err(spi->dev, "abort error\n"); + if (stat & SPI_STAT_RE) + dev_err(spi->dev, "receive overflow error\n"); + if (stat & SPI_STAT_TE) + dev_err(spi->dev, "transmit overflow error\n"); + if (stat & SPI_STAT_ME) + dev_err(spi->dev, "mode error\n"); + + /* Clear error flags */ + lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); + + /* set bad status so it can be retried */ + if (spi->master->cur_msg) + spi->master->cur_msg->status = -EIO; + queue_work(spi->wq, &spi->work); + + return IRQ_HANDLED; +} + +static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev, + struct spi_transfer *t) +{ + unsigned long flags; + + spin_lock_irqsave(&spi->lock, flags); + + spi->tx = t->tx_buf; + spi->rx = t->rx_buf; + + if (t->tx_buf) { + spi->tx_todo = t->len; + + /* initially fill TX FIFO */ + tx_fifo_write(spi); + } + + if (spi->rx) { + spi->rx_todo = t->len; + + /* start shift clock in RX-only mode */ + if (!spi->tx) + rx_request(spi); + } + + spin_unlock_irqrestore(&spi->lock, flags); + + return t->len; +} + +/* + * The driver only gets an interrupt when the FIFO is empty, but there + * is an additional shift register from which the data is written to + * the wire. We get the last interrupt when the controller starts to + * write the last word to the wire, not when it is finished. Do busy + * waiting till it finishes. + */ +static void lantiq_ssc_bussy_work(struct work_struct *work) +{ + struct lantiq_ssc_spi *spi; + unsigned long long timeout = 8LL * 1000LL; + unsigned long end; + + spi = container_of(work, typeof(*spi), work); + + do_div(timeout, spi->speed_hz); + timeout += timeout + 100; /* some tolerance */ + + end = jiffies + msecs_to_jiffies(timeout); + do { + u32 stat = lantiq_ssc_readl(spi, SPI_STAT); + + if (!(stat & SPI_STAT_BSY)) { + spi_finalize_current_transfer(spi->master); + return; + } + + cond_resched(); + } while (!time_after_eq(jiffies, end)); + + if (spi->master->cur_msg) + spi->master->cur_msg->status = -EIO; + spi_finalize_current_transfer(spi->master); +} + +static void lantiq_ssc_handle_err(struct spi_master *master, + struct spi_message *message) +{ + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); + + /* flush FIFOs on timeout */ + rx_fifo_flush(spi); + tx_fifo_flush(spi); +} + +static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) +{ + struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master); + unsigned int cs = spidev->chip_select; + u32 fgpo; + + if (!!(spidev->mode & SPI_CS_HIGH) == enable) + fgpo = (1 << (cs - spi->base_cs)); + else + fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S)); + + lantiq_ssc_writel(spi, fgpo, SPI_FPGO); +} + +static int lantiq_ssc_transfer_one(struct spi_master *master, + struct spi_device *spidev, + struct spi_transfer *t) +{ + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); + + hw_setup_transfer(spi, spidev, t); + + return transfer_start(spi, spidev, t); +} + +static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { + .irnen_r = SPI_IRNEN_R_XWAY, + .irnen_t = SPI_IRNEN_T_XWAY, +}; + +static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { + .irnen_r = SPI_IRNEN_R_XRX, + .irnen_t = SPI_IRNEN_T_XRX, +}; + +static const struct of_device_id lantiq_ssc_match[] = { + { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, }, + { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, }, + { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, }, + {}, +}; +MODULE_DEVICE_TABLE(of, lantiq_ssc_match); + +static int lantiq_ssc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_master *master; + struct resource *res; + struct lantiq_ssc_spi *spi; + const struct lantiq_ssc_hwcfg *hwcfg; + const struct of_device_id *match; + int err, rx_irq, tx_irq, err_irq; + u32 id, supports_dma, revision; + unsigned int num_cs; + + match = of_match_device(lantiq_ssc_match, dev); + if (!match) { + dev_err(dev, "no device match\n"); + return -EINVAL; + } + hwcfg = match->data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "failed to get resources\n"); + return -ENXIO; + } + + rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME); + if (rx_irq < 0) { + dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME); + return -ENXIO; + } + + tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME); + if (tx_irq < 0) { + dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME); + return -ENXIO; + } + + err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME); + if (err_irq < 0) { + dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME); + return -ENXIO; + } + + master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi)); + if (!master) + return -ENOMEM; + + spi = spi_master_get_devdata(master); + spi->master = master; + spi->dev = dev; + spi->hwcfg = hwcfg; + platform_set_drvdata(pdev, spi); + + spi->regbase = devm_ioremap_resource(dev, res); + if (IS_ERR(spi->regbase)) { + err = PTR_ERR(spi->regbase); + goto err_master_put; + } + + err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, + 0, SPI_RX_IRQ_NAME, spi); + if (err) + goto err_master_put; + + err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, + 0, SPI_TX_IRQ_NAME, spi); + if (err) + goto err_master_put; + + err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, + 0, SPI_ERR_IRQ_NAME, spi); + if (err) + goto err_master_put; + + spi->spi_clk = devm_clk_get(dev, "gate"); + if (IS_ERR(spi->spi_clk)) { + err = PTR_ERR(spi->spi_clk); + goto err_master_put; + } + err = clk_prepare_enable(spi->spi_clk); + if (err) + goto err_master_put; + + /* + * Use the old clk_get_fpi() function on Lantiq platform, till it + * supports common clk. + */ +#if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK) + spi->fpi_clk = clk_get_fpi(); +#else + spi->fpi_clk = clk_get(dev, "freq"); +#endif + if (IS_ERR(spi->fpi_clk)) { + err = PTR_ERR(spi->fpi_clk); + goto err_clk_disable; + } + + num_cs = 8; + of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + + spi->base_cs = 1; + of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs); + + spin_lock_init(&spi->lock); + spi->bits_per_word = 8; + spi->speed_hz = 0; + + master->dev.of_node = pdev->dev.of_node; + master->num_chipselect = num_cs; + master->setup = lantiq_ssc_setup; + master->set_cs = lantiq_ssc_set_cs; + master->handle_err = lantiq_ssc_handle_err; + master->prepare_message = lantiq_ssc_prepare_message; + master->unprepare_message = lantiq_ssc_unprepare_message; + master->transfer_one = lantiq_ssc_transfer_one; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH | + SPI_LOOP; + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) | + SPI_BPW_MASK(16) | SPI_BPW_MASK(32); + + spi->wq = alloc_ordered_workqueue(dev_name(dev), 0); + if (!spi->wq) { + err = -ENOMEM; + goto err_clk_put; + } + INIT_WORK(&spi->work, lantiq_ssc_bussy_work); + + id = lantiq_ssc_readl(spi, SPI_ID); + spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S; + spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S; + supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S; + revision = id & SPI_ID_REV_M; + + lantiq_ssc_hw_init(spi); + + dev_info(dev, + "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n", + revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma); + + err = devm_spi_register_master(dev, master); + if (err) { + dev_err(dev, "failed to register spi_master\n"); + goto err_wq_destroy; + } + + return 0; + +err_wq_destroy: + destroy_workqueue(spi->wq); +err_clk_put: + clk_put(spi->fpi_clk); +err_clk_disable: + clk_disable_unprepare(spi->spi_clk); +err_master_put: + spi_master_put(master); + + return err; +} + +static int lantiq_ssc_remove(struct platform_device *pdev) +{ + struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); + + lantiq_ssc_writel(spi, 0, SPI_IRNEN); + lantiq_ssc_writel(spi, 0, SPI_CLC); + rx_fifo_flush(spi); + tx_fifo_flush(spi); + hw_enter_config_mode(spi); + + destroy_workqueue(spi->wq); + clk_disable_unprepare(spi->spi_clk); + clk_put(spi->fpi_clk); + + return 0; +} + +static struct platform_driver lantiq_ssc_driver = { + .probe = lantiq_ssc_probe, + .remove = lantiq_ssc_remove, + .driver = { + .name = "spi-lantiq-ssc", + .owner = THIS_MODULE, + .of_match_table = lantiq_ssc_match, + }, +}; +module_platform_driver(lantiq_ssc_driver); + +MODULE_DESCRIPTION("Lantiq SSC SPI controller driver"); +MODULE_AUTHOR("Daniel Schwierzeck "); +MODULE_AUTHOR("Hauke Mehrtens "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:spi-lantiq-ssc"); -- cgit v1.2.3 From cb5cfd91a7ae5ae355e657e5ce4931836b7665eb Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 9 Feb 2017 18:03:56 -0800 Subject: devicetree: i2c-hid: Add regulator support Document a "vdd-supply" and an initialization delay. Can be used for powering on/off a HID. Signed-off-by: Caesar Wang Cc: Rob Herring Cc: Jiri Kosina Cc: linux-input@vger.kernel.org Signed-off-by: Brian Norris Acked-by: Rob Herring Signed-off-by: Jiri Kosina --- Documentation/devicetree/bindings/input/hid-over-i2c.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/input/hid-over-i2c.txt b/Documentation/devicetree/bindings/input/hid-over-i2c.txt index 488edcb264c4..28e8bd8b7d64 100644 --- a/Documentation/devicetree/bindings/input/hid-over-i2c.txt +++ b/Documentation/devicetree/bindings/input/hid-over-i2c.txt @@ -17,6 +17,22 @@ Required properties: - interrupt-parent: the phandle for the interrupt controller - interrupts: interrupt line +Additional optional properties: + +Some devices may support additional optional properties to help with, e.g., +power sequencing. The following properties can be supported by one or more +device-specific compatible properties, which should be used in addition to the +"hid-over-i2c" string. + +- compatible: + * "wacom,w9013" (Wacom W9013 digitizer). Supports: + - vdd-supply + - post-power-on-delay-ms + +- vdd-supply: phandle of the regulator that provides the supply voltage. +- post-power-on-delay-ms: time required by the device after enabling its regulators + before it is ready for communication. Must be used with 'vdd-supply'. + Example: i2c-hid-dev@2c { -- cgit v1.2.3