From 7b5bb891a6e44bd18bd8661ede2e09ccae258ef5 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Fri, 8 May 2015 23:31:57 +0900 Subject: h8300: clock driver Signed-off-by: Yoshinori Sato --- .../bindings/clock/renesas,h8300-div-clock.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt (limited to 'Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt') diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt new file mode 100644 index 000000000000..36c2b528245c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt @@ -0,0 +1,24 @@ +* Renesas H8/300 divider clock + +Required Properties: + + - compatible: Must be "renesas,sh73a0-h8300-div-clock" + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - reg: Base address and length of the divide rate selector + + - renesas,width: bit width of selector + +Example +------- + + cclk: cclk { + compatible = "renesas,h8300-div-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee01b 2>; + renesas,width = <2>; + }; -- cgit v1.2.3