From af4681097b23fe9c63a03d774de7c742fa3a920e Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU Date: Thu, 10 May 2012 10:42:32 +0300 Subject: ARM: tegra30: Add Tegra Memory Controller(MC) driver Tegra Memory Controller(MC) driver for Tegra30 Added to support MC General interrupts, mainly for IOMMU(SMMU). Signed-off-by: Hiroshi DOYU Acked-by: Stephen Warren Signed-off-by: Greg Kroah-Hartman --- .../bindings/arm/tegra/nvidia,tegra30-mc.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt (limited to 'Documentation/devicetree/bindings/arm/tegra') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt new file mode 100644 index 000000000000..e47e73f612f4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt @@ -0,0 +1,18 @@ +NVIDIA Tegra30 MC(Memory Controller) + +Required properties: +- compatible : "nvidia,tegra30-mc" +- reg : Should contain 4 register ranges(address and length); see the + example below. Note that the MC registers are interleaved with the + SMMU registers, and hence must be represented as multiple ranges. +- interrupts : Should contain MC General interrupt. + +Example: + mc { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x010 + 0x7000f03c 0x1b4 + 0x7000f200 0x028 + 0x7000f284 0x17c>; + interrupts = <0 77 0x04>; + }; -- cgit v1.2.3