From 1a88bb47a809433c5683e8d955f0611e7a188275 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 Oct 2025 19:33:26 +0300 Subject: drm/atomic: WARN about missing acquire_ctx in drm_atomic_get_private_obj_state() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The crtc/plane/connector counterparts of drm_atomic_get_private_obj_state() all WARN about a missing acquire_ctx. Do the same in drm_atomic_get_private_obj_state() for consistency. Cc: Maxime Ripard Cc: Dan Carpenter Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20251017163327.9074-1-ville.syrjala@linux.intel.com Reviewed-by: Maxime Ripard --- drivers/gpu/drm/drm_atomic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index be2cb6e43cb0..5d31b20e67ab 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -836,6 +836,8 @@ drm_atomic_get_private_obj_state(struct drm_atomic_state *state, struct __drm_private_objs_state *arr; struct drm_private_state *obj_state; + WARN_ON(!state->acquire_ctx); + obj_state = drm_atomic_get_new_private_obj_state(state, obj); if (obj_state) return obj_state; -- cgit v1.2.3 From 0a0e79a2d9ed846fc3c3f5ef92b691e81bc9721a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 Oct 2025 19:33:27 +0300 Subject: drm/atomic: WARN about invalid drm_foo_get_state() usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drm_{crtc,plane,connector,private_obj}_get_state() must not be called after the atomic check phase. At that point the commit has been carved in stone and no new objects must be introduced into it. WARN if anyone attempts to violate this rule. Cc: Maxime Ripard Cc: Dan Carpenter Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20251017163327.9074-2-ville.syrjala@linux.intel.com Reviewed-by: Maxime Ripard --- drivers/gpu/drm/drm_atomic.c | 8 ++++++++ include/drm/drm_atomic.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 5d31b20e67ab..e05820b18832 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -200,6 +200,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state) drm_dbg_atomic(dev, "Clearing atomic state %p\n", state); + state->checked = false; + for (i = 0; i < state->num_connector; i++) { struct drm_connector *connector = state->connectors[i].ptr; @@ -348,6 +350,7 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *state, struct drm_crtc_state *crtc_state; WARN_ON(!state->acquire_ctx); + drm_WARN_ON(state->dev, state->checked); crtc_state = drm_atomic_get_new_crtc_state(state, crtc); if (crtc_state) @@ -528,6 +531,7 @@ drm_atomic_get_plane_state(struct drm_atomic_state *state, struct drm_plane_state *plane_state; WARN_ON(!state->acquire_ctx); + drm_WARN_ON(state->dev, state->checked); /* the legacy pointers should never be set */ WARN_ON(plane->fb); @@ -837,6 +841,7 @@ drm_atomic_get_private_obj_state(struct drm_atomic_state *state, struct drm_private_state *obj_state; WARN_ON(!state->acquire_ctx); + drm_WARN_ON(state->dev, state->checked); obj_state = drm_atomic_get_new_private_obj_state(state, obj); if (obj_state) @@ -1131,6 +1136,7 @@ drm_atomic_get_connector_state(struct drm_atomic_state *state, struct drm_connector_state *connector_state; WARN_ON(!state->acquire_ctx); + drm_WARN_ON(state->dev, state->checked); ret = drm_modeset_lock(&config->connection_mutex, state->acquire_ctx); if (ret) @@ -1543,6 +1549,8 @@ int drm_atomic_check_only(struct drm_atomic_state *state) requested_crtc, affected_crtc); } + state->checked = true; + return 0; } EXPORT_SYMBOL(drm_atomic_check_only); diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 155e82f87e4d..2e433d44658d 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -523,6 +523,14 @@ struct drm_atomic_state { */ bool duplicated : 1; + /** + * @checked: + * + * Indicates the state has been checked and thus must no longer + * be mutated. For internal use only, do not consult from drivers. + */ + bool checked : 1; + /** * @planes: * -- cgit v1.2.3 From 42bbf82b73bda18bbc3e158cb6fda040bb586feb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:11 +0100 Subject: drm/rcar-du: dsi: Fix missing parameter in RXSETR_...EN macros The RXSETR_CRCEN(n) and RXSETR_ECCEN(n) macros both take parameter (n), add the missing macro parameter. Neither of those macros is used by the driver, so for now the bug is harmless. Fixes: 685e8dae19df ("drm/rcar-du: dsi: Implement DSI command support") Reviewed-by: Laurent Pinchart Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Reported-by: Laurent Pinchart Link: https://patch.msgid.link/20251028232959.109936-2-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 76521276e2af..dd871e17dcf5 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -50,8 +50,8 @@ #define TXCMPPD3R 0x16c #define RXSETR 0x200 -#define RXSETR_CRCEN (((n) & 0xf) << 24) -#define RXSETR_ECCEN (((n) & 0xf) << 16) +#define RXSETR_CRCEN(n) (((n) & 0xf) << 24) +#define RXSETR_ECCEN(n) (((n) & 0xf) << 16) #define RXPSETR 0x210 #define RXPSETR_LPPDACC (1 << 0) #define RXPSR 0x220 -- cgit v1.2.3 From 4723455e4b893099f5a1892ef0df899a9341abab Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:12 +0100 Subject: drm/rcar-du: dsi: Document TXVMSETR PIXWDTH as bitfield The register TXVMSETR bitfield PIXWDTH is not a single bit, but a bitfield. Add a MASK macro and document that the only allowed value that can ever be written into the bitfield is the current value, 1. No functional change. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-3-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index dd871e17dcf5..b8a719a13c00 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -143,7 +143,8 @@ #define TXVMSETR_SYNSEQ_PULSES (0 << 16) #define TXVMSETR_SYNSEQ_EVENTS (1 << 16) #define TXVMSETR_VSTPM (1 << 15) -#define TXVMSETR_PIXWDTH (1 << 8) +#define TXVMSETR_PIXWDTH_MASK (7 << 8) +#define TXVMSETR_PIXWDTH (1 << 8) /* Only allowed value */ #define TXVMSETR_VSEN_EN (1 << 4) #define TXVMSETR_VSEN_DIS (0 << 4) #define TXVMSETR_HFPBPEN_EN (1 << 2) -- cgit v1.2.3 From c979eb60a6f358380fffd74634b956d7ab04fa4c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:13 +0100 Subject: drm/rcar-du: dsi: Document PHTR TESTDOUT as bitfield The register PHTR bitfield TESTDOUT is not a single bit, but a bitfield. Add a MASK macro and a _TEST bitfield value, which is used by the driver to poll for completion. No functional change. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-4-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 4 ++-- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c index 5c73a513f678..c24721a1eddf 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c @@ -316,8 +316,8 @@ rcar_mipi_dsi_post_init_phtw_v4h(struct rcar_mipi_dsi *dsi, WRITE_PHTW(0x01020100, 0x00000180); ret = read_poll_timeout(rcar_mipi_dsi_read, status, - status & PHTR_TEST, 2000, 10000, false, - dsi, PHTR); + status & PHTR_TESTDOUT_TEST, + 2000, 10000, false, dsi, PHTR); if (ret < 0) { dev_err(dsi->dev, "failed to test PHTR\n"); return ret; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index b8a719a13c00..62341416ac6e 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -293,7 +293,8 @@ #define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0) #define PHTR 0x1038 -#define PHTR_TEST (1 << 16) +#define PHTR_TESTDOUT (0xff << 16) +#define PHTR_TESTDOUT_TEST (1 << 16) #define PHTC 0x103c #define PHTC_TESTCLR (1 << 0) -- cgit v1.2.3 From 1d89f8b4b977446dcc7556d99a3619246ba7417e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:14 +0100 Subject: drm/rcar-du: dsi: Deduplicate mipi_dsi_pixel_format_to_bpp() usage Call mipi_dsi_pixel_format_to_bpp() once in rcar_mipi_dsi_set_display_timing() and store the value into a variable. This slightly simplifies the code. No functional change. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-5-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c index c24721a1eddf..e13249e0134b 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c @@ -457,13 +457,17 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi, u32 vprmset4r; /* Configuration for Pixel Stream and Packet Header */ - if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24) + switch (mipi_dsi_pixel_format_to_bpp(dsi->format)) { + case 24: rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24); - else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18) + break; + case 18: rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18); - else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16) + break; + case 16: rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16); - else { + break; + default: dev_warn(dsi->dev, "unsupported format"); return; } -- cgit v1.2.3 From 52b464f8441e724fa6358ffe4082cb626832d51e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:15 +0100 Subject: drm/rcar-du: dsi: Clean up VCLKSET register macros Introduce VCLKSET_BPP_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift. Remove VCLKSET_COLOR_RGB which is never used, replace it with code comment. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-6-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 4 +++- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 12 ++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c index e13249e0134b..f6427476feb7 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Renesas Electronics Corporation */ +#include #include #include #include @@ -624,6 +625,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, vclkset = VCLKSET_CKEN; rcar_mipi_dsi_write(dsi, VCLKSET, vclkset); + /* Output is always RGB, never YCbCr */ if (dsi_format == 24) vclkset |= VCLKSET_BPP_24; else if (dsi_format == 18) @@ -635,7 +637,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, return -EINVAL; } - vclkset |= VCLKSET_COLOR_RGB | VCLKSET_LANE(dsi->lanes - 1); + vclkset |= VCLKSET_LANE(dsi->lanes - 1); switch (dsi->info->model) { case RCAR_DSI_V3U: diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 62341416ac6e..2db3dda030db 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -246,14 +246,14 @@ #define VCLKSET 0x100c #define VCLKSET_CKEN (1 << 16) -#define VCLKSET_COLOR_RGB (0 << 8) -#define VCLKSET_COLOR_YCC (1 << 8) +#define VCLKSET_COLOR_YCC (1 << 8) /* 0:RGB 1:YCbCr */ #define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4) #define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4) -#define VCLKSET_BPP_16 (0 << 2) -#define VCLKSET_BPP_18 (1 << 2) -#define VCLKSET_BPP_18L (2 << 2) -#define VCLKSET_BPP_24 (3 << 2) +#define VCLKSET_BPP_MASK (3 << 2) +#define VCLKSET_BPP_16 FIELD_PREP(VCLKSET_BPP_MASK, 0) +#define VCLKSET_BPP_18 FIELD_PREP(VCLKSET_BPP_MASK, 1) +#define VCLKSET_BPP_18L FIELD_PREP(VCLKSET_BPP_MASK, 2) +#define VCLKSET_BPP_24 FIELD_PREP(VCLKSET_BPP_MASK, 3) #define VCLKSET_LANE(x) (((x) & 0x3) << 0) #define VCLKEN 0x1010 -- cgit v1.2.3 From 0b0ec96ba6beb6be67a7e1b7bf68b38649952063 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:16 +0100 Subject: drm/rcar-du: dsi: Clean up CLOCKSET1 CLKINSEL macros Introduce CLOCKSET1_CLKINSEL_MASK macro and remove bitshift from values to make this bitfield usable with FIELD_PREP(). There are no users of this bitfield, hence no updates to the DSI driver. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-7-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 2db3dda030db..44220c711231 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -269,9 +269,10 @@ #define CLOCKSET1 0x101c #define CLOCKSET1_LOCK_PHY (1 << 17) #define CLOCKSET1_CLKSEL (1 << 8) -#define CLOCKSET1_CLKINSEL_EXTAL (0 << 2) -#define CLOCKSET1_CLKINSEL_DIG (1 << 2) -#define CLOCKSET1_CLKINSEL_DU (1 << 3) +#define CLOCKSET1_CLKINSEL_MASK (3 << 2) +#define CLOCKSET1_CLKINSEL_EXTAL FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0) +#define CLOCKSET1_CLKINSEL_DIG FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1) +#define CLOCKSET1_CLKINSEL_DU FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2) #define CLOCKSET1_SHADOW_CLEAR (1 << 1) #define CLOCKSET1_UPDATEPLL (1 << 0) -- cgit v1.2.3 From 7d9949a8fbe4d66d4a8a96d3528633bcbd509a12 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:17 +0100 Subject: drm/rcar-du: dsi: Clean up TXVMPSPHSETR DT macros Introduce TXVMPSPHSETR_DT_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-8-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 44220c711231..cfaa9b345308 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -168,11 +168,12 @@ #define TXVMSCR_STR (1 << 16) #define TXVMPSPHSETR 0x1c0 -#define TXVMPSPHSETR_DT_RGB16 (0x0e << 16) -#define TXVMPSPHSETR_DT_RGB18 (0x1e << 16) -#define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16) -#define TXVMPSPHSETR_DT_RGB24 (0x3e << 16) -#define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16) +#define TXVMPSPHSETR_DT_MASK (0x3f << 16) +#define TXVMPSPHSETR_DT_RGB16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x0e) +#define TXVMPSPHSETR_DT_RGB18 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x1e) +#define TXVMPSPHSETR_DT_RGB18_LS FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2e) +#define TXVMPSPHSETR_DT_RGB24 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x3e) +#define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c) #define TXVMVPRMSET0R 0x1d0 #define TXVMVPRMSET0R_HSPOL_HIG (0 << 17) -- cgit v1.2.3 From dd3957e026c2379b073636b7ece053f22efa1608 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:18 +0100 Subject: drm/rcar-du: dsi: Respect DSI mode flags Cache DSI mode flags in new mode_flags member of struct rcar_mipi_dsi . Configure TXVMSETR register based on the content of DSI mode flags in case the controller operates in video mode. Rename TXVMSETR_H..BPEN_EN to TXVMSETR_H..BPEN and drop TXVMSETR_H..BPEN_DIS which resolves to 0. Update TXVMSETR_VSEN in the same manner. Replace TXVMSETR_SYNSEQ_PULSES with a code comment next to TXVMSETR_SYNSEQ_EVENTS because TXVMSETR_SYNSEQ_PULSES resolves to 0. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Laurent Pinchart Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-9-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 18 +++++++++++++++--- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 15 +++++---------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c index f6427476feb7..78e512de7cf9 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c @@ -72,6 +72,7 @@ struct rcar_mipi_dsi { } clocks; enum mipi_dsi_pixel_format format; + unsigned long mode_flags; unsigned int num_data_lanes; unsigned int lanes; }; @@ -474,9 +475,19 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi, } /* Configuration for Blanking sequence and Input Pixel */ - setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN - | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES - | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM; + setr = TXVMSETR_PIXWDTH | TXVMSETR_VSTPM; + + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) + setr |= TXVMSETR_SYNSEQ_EVENTS; + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)) + setr |= TXVMSETR_HFPBPEN; + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)) + setr |= TXVMSETR_HBPBPEN; + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)) + setr |= TXVMSETR_HSABPEN; + } + rcar_mipi_dsi_write(dsi, TXVMSETR, setr); /* Configuration for Video Parameters */ @@ -917,6 +928,7 @@ static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host, dsi->lanes = device->lanes; dsi->format = device->format; + dsi->mode_flags = device->mode_flags; dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index cfaa9b345308..75b0ae207a64 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -140,19 +140,14 @@ * Video Mode Register */ #define TXVMSETR 0x180 -#define TXVMSETR_SYNSEQ_PULSES (0 << 16) -#define TXVMSETR_SYNSEQ_EVENTS (1 << 16) +#define TXVMSETR_SYNSEQ_EVENTS (1 << 16) /* 0:Pulses 1:Events */ #define TXVMSETR_VSTPM (1 << 15) #define TXVMSETR_PIXWDTH_MASK (7 << 8) #define TXVMSETR_PIXWDTH (1 << 8) /* Only allowed value */ -#define TXVMSETR_VSEN_EN (1 << 4) -#define TXVMSETR_VSEN_DIS (0 << 4) -#define TXVMSETR_HFPBPEN_EN (1 << 2) -#define TXVMSETR_HFPBPEN_DIS (0 << 2) -#define TXVMSETR_HBPBPEN_EN (1 << 1) -#define TXVMSETR_HBPBPEN_DIS (0 << 1) -#define TXVMSETR_HSABPEN_EN (1 << 0) -#define TXVMSETR_HSABPEN_DIS (0 << 0) +#define TXVMSETR_VSEN (1 << 4) +#define TXVMSETR_HFPBPEN (1 << 2) +#define TXVMSETR_HBPBPEN (1 << 1) +#define TXVMSETR_HSABPEN (1 << 0) #define TXVMCR 0x190 #define TXVMCR_VFCLR (1 << 12) -- cgit v1.2.3 From 94fe479fae96ba9a31bd252782dcc06a15f33b22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:19 +0100 Subject: drm/rcar-du: dsi: Clean up handling of DRM mode flags Introduce TXVMVPRMSET0R_BPP_MASK macro and use FIELD_PREP() to generate appropriate bitfield from mask and value without bitshift, assign this value into vprmset0r. Remove TXVMVPRMSET0R_CSPC_RGB which is never used, replace it with code comment next to TXVMVPRMSET0R_CSPC_YCbCr. Replace (mode->flags & DRM_MODE_FLAG_P.SYNC) test with inverted conditional (mode->flags & DRM_MODE_FLAG_N.SYNC) and bitwise orr vprmset0r with either or both TXVMVPRMSET0R_HSPOL_LOW and TXVMVPRMSET0R_VSPOL_LOW if conditional matches. Do not convert bits and bitfields to BIT() and GENMASK() yet, to be consisten with the current style. Conversion to BIT() and GENMASK() macros is done at the very end of this series in the last two patches. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-10-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 12 ++++++------ drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 16 +++++++--------- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c index 78e512de7cf9..9413b76d0bfc 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c @@ -490,12 +490,12 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi, rcar_mipi_dsi_write(dsi, TXVMSETR, setr); - /* Configuration for Video Parameters */ - vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ? - TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW) - | (mode->flags & DRM_MODE_FLAG_PHSYNC ? - TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW) - | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24; + /* Configuration for Video Parameters, input is always RGB888 */ + vprmset0r = TXVMVPRMSET0R_BPP_24; + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + vprmset0r |= TXVMVPRMSET0R_VSPOL_LOW; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + vprmset0r |= TXVMVPRMSET0R_HSPOL_LOW; vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay) | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start); diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 75b0ae207a64..88ed427f6dd2 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -171,15 +171,13 @@ #define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c) #define TXVMVPRMSET0R 0x1d0 -#define TXVMVPRMSET0R_HSPOL_HIG (0 << 17) -#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) -#define TXVMVPRMSET0R_VSPOL_HIG (0 << 16) -#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) -#define TXVMVPRMSET0R_CSPC_RGB (0 << 4) -#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) -#define TXVMVPRMSET0R_BPP_16 (0 << 0) -#define TXVMVPRMSET0R_BPP_18 (1 << 0) -#define TXVMVPRMSET0R_BPP_24 (2 << 0) +#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) /* 0:High 1:Low */ +#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) /* 0:High 1:Low */ +#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) /* 0:RGB 1:YCbCr */ +#define TXVMVPRMSET0R_BPP_MASK (7 << 0) +#define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0) +#define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1) +#define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2) #define TXVMVPRMSET1R 0x1d4 #define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16) -- cgit v1.2.3 From 6ade1742e380188fafea4d50ebafe909fad33b7a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:20 +0100 Subject: drm/rcar-du: dsi: Convert register bits to BIT() macro Convert register bits to BIT() macro where applicable. This is done automatically using regex 's@(1 << \([0-9]\+\))@BIT(\1)', except for bitfields which are manually updated to use GENMASK(). Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-11-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- .../gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 252 ++++++++++----------- 1 file changed, 126 insertions(+), 126 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index 88ed427f6dd2..d3a1b91637ed 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -9,37 +9,37 @@ #define __RCAR_MIPI_DSI_REGS_H__ #define LINKSR 0x010 -#define LINKSR_LPBUSY (1 << 1) -#define LINKSR_HSBUSY (1 << 0) +#define LINKSR_LPBUSY BIT_U32(1) +#define LINKSR_HSBUSY BIT_U32(0) #define TXSETR 0x100 -#define TXSETR_LANECNT_MASK (0x3 << 0) +#define TXSETR_LANECNT_MASK GENMASK(1, 0) /* * DSI Command Transfer Registers */ #define TXCMSETR 0x110 -#define TXCMSETR_SPDTYP (1 << 8) /* 0:HS 1:LP */ -#define TXCMSETR_LPPDACC (1 << 0) +#define TXCMSETR_SPDTYP BIT_U32(8) /* 0:HS 1:LP */ +#define TXCMSETR_LPPDACC BIT_U32(0) #define TXCMCR 0x120 -#define TXCMCR_BTATYP (1 << 2) -#define TXCMCR_BTAREQ (1 << 1) -#define TXCMCR_TXREQ (1 << 0) +#define TXCMCR_BTATYP BIT_U32(2) +#define TXCMCR_BTAREQ BIT_U32(1) +#define TXCMCR_TXREQ BIT_U32(0) #define TXCMSR 0x130 -#define TXCMSR_CLSNERR (1 << 18) -#define TXCMSR_AXIERR (1 << 16) -#define TXCMSR_TXREQEND (1 << 0) +#define TXCMSR_CLSNERR BIT_U32(18) +#define TXCMSR_AXIERR BIT_U32(16) +#define TXCMSR_TXREQEND BIT_U32(0) #define TXCMSCR 0x134 -#define TXCMSCR_CLSNERR (1 << 18) -#define TXCMSCR_AXIERR (1 << 16) -#define TXCMSCR_TXREQEND (1 << 0) +#define TXCMSCR_CLSNERR BIT_U32(18) +#define TXCMSCR_AXIERR BIT_U32(16) +#define TXCMSCR_TXREQEND BIT_U32(0) #define TXCMIER 0x138 -#define TXCMIER_CLSNERR (1 << 18) -#define TXCMIER_AXIERR (1 << 16) -#define TXCMIER_TXREQEND (1 << 0) +#define TXCMIER_CLSNERR BIT_U32(18) +#define TXCMIER_AXIERR BIT_U32(16) +#define TXCMIER_TXREQEND BIT_U32(0) #define TXCMADDRSET0R 0x140 #define TXCMPHDR 0x150 -#define TXCMPHDR_FMT (1 << 24) /* 0:SP 1:LP */ +#define TXCMPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */ #define TXCMPHDR_VC(n) (((n) & 0x3) << 22) #define TXCMPHDR_DT(n) (((n) & 0x3f) << 16) #define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8) @@ -53,63 +53,63 @@ #define RXSETR_CRCEN(n) (((n) & 0xf) << 24) #define RXSETR_ECCEN(n) (((n) & 0xf) << 16) #define RXPSETR 0x210 -#define RXPSETR_LPPDACC (1 << 0) +#define RXPSETR_LPPDACC BIT_U32(0) #define RXPSR 0x220 -#define RXPSR_ECCERR1B (1 << 28) -#define RXPSR_UEXTRGERR (1 << 25) -#define RXPSR_RESPTOERR (1 << 24) -#define RXPSR_OVRERR (1 << 23) -#define RXPSR_AXIERR (1 << 22) -#define RXPSR_CRCERR (1 << 21) -#define RXPSR_WCERR (1 << 20) -#define RXPSR_UEXDTERR (1 << 19) -#define RXPSR_UEXPKTERR (1 << 18) -#define RXPSR_ECCERR (1 << 17) -#define RXPSR_MLFERR (1 << 16) -#define RXPSR_RCVACK (1 << 14) -#define RXPSR_RCVEOT (1 << 10) -#define RXPSR_RCVAKE (1 << 9) -#define RXPSR_RCVRESP (1 << 8) -#define RXPSR_BTAREQEND (1 << 0) +#define RXPSR_ECCERR1B BIT_U32(28) +#define RXPSR_UEXTRGERR BIT_U32(25) +#define RXPSR_RESPTOERR BIT_U32(24) +#define RXPSR_OVRERR BIT_U32(23) +#define RXPSR_AXIERR BIT_U32(22) +#define RXPSR_CRCERR BIT_U32(21) +#define RXPSR_WCERR BIT_U32(20) +#define RXPSR_UEXDTERR BIT_U32(19) +#define RXPSR_UEXPKTERR BIT_U32(18) +#define RXPSR_ECCERR BIT_U32(17) +#define RXPSR_MLFERR BIT_U32(16) +#define RXPSR_RCVACK BIT_U32(14) +#define RXPSR_RCVEOT BIT_U32(10) +#define RXPSR_RCVAKE BIT_U32(9) +#define RXPSR_RCVRESP BIT_U32(8) +#define RXPSR_BTAREQEND BIT_U32(0) #define RXPSCR 0x224 -#define RXPSCR_ECCERR1B (1 << 28) -#define RXPSCR_UEXTRGERR (1 << 25) -#define RXPSCR_RESPTOERR (1 << 24) -#define RXPSCR_OVRERR (1 << 23) -#define RXPSCR_AXIERR (1 << 22) -#define RXPSCR_CRCERR (1 << 21) -#define RXPSCR_WCERR (1 << 20) -#define RXPSCR_UEXDTERR (1 << 19) -#define RXPSCR_UEXPKTERR (1 << 18) -#define RXPSCR_ECCERR (1 << 17) -#define RXPSCR_MLFERR (1 << 16) -#define RXPSCR_RCVACK (1 << 14) -#define RXPSCR_RCVEOT (1 << 10) -#define RXPSCR_RCVAKE (1 << 9) -#define RXPSCR_RCVRESP (1 << 8) -#define RXPSCR_BTAREQEND (1 << 0) +#define RXPSCR_ECCERR1B BIT_U32(28) +#define RXPSCR_UEXTRGERR BIT_U32(25) +#define RXPSCR_RESPTOERR BIT_U32(24) +#define RXPSCR_OVRERR BIT_U32(23) +#define RXPSCR_AXIERR BIT_U32(22) +#define RXPSCR_CRCERR BIT_U32(21) +#define RXPSCR_WCERR BIT_U32(20) +#define RXPSCR_UEXDTERR BIT_U32(19) +#define RXPSCR_UEXPKTERR BIT_U32(18) +#define RXPSCR_ECCERR BIT_U32(17) +#define RXPSCR_MLFERR BIT_U32(16) +#define RXPSCR_RCVACK BIT_U32(14) +#define RXPSCR_RCVEOT BIT_U32(10) +#define RXPSCR_RCVAKE BIT_U32(9) +#define RXPSCR_RCVRESP BIT_U32(8) +#define RXPSCR_BTAREQEND BIT_U32(0) #define RXPIER 0x228 -#define RXPIER_ECCERR1B (1 << 28) -#define RXPIER_UEXTRGERR (1 << 25) -#define RXPIER_RESPTOERR (1 << 24) -#define RXPIER_OVRERR (1 << 23) -#define RXPIER_AXIERR (1 << 22) -#define RXPIER_CRCERR (1 << 21) -#define RXPIER_WCERR (1 << 20) -#define RXPIER_UEXDTERR (1 << 19) -#define RXPIER_UEXPKTERR (1 << 18) -#define RXPIER_ECCERR (1 << 17) -#define RXPIER_MLFERR (1 << 16) -#define RXPIER_RCVACK (1 << 14) -#define RXPIER_RCVEOT (1 << 10) -#define RXPIER_RCVAKE (1 << 9) -#define RXPIER_RCVRESP (1 << 8) -#define RXPIER_BTAREQEND (1 << 0) +#define RXPIER_ECCERR1B BIT_U32(28) +#define RXPIER_UEXTRGERR BIT_U32(25) +#define RXPIER_RESPTOERR BIT_U32(24) +#define RXPIER_OVRERR BIT_U32(23) +#define RXPIER_AXIERR BIT_U32(22) +#define RXPIER_CRCERR BIT_U32(21) +#define RXPIER_WCERR BIT_U32(20) +#define RXPIER_UEXDTERR BIT_U32(19) +#define RXPIER_UEXPKTERR BIT_U32(18) +#define RXPIER_ECCERR BIT_U32(17) +#define RXPIER_MLFERR BIT_U32(16) +#define RXPIER_RCVACK BIT_U32(14) +#define RXPIER_RCVEOT BIT_U32(10) +#define RXPIER_RCVAKE BIT_U32(9) +#define RXPIER_RCVRESP BIT_U32(8) +#define RXPIER_BTAREQEND BIT_U32(0) #define RXPADDRSET0R 0x230 #define RXPSIZESETR 0x238 #define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3) #define RXPHDR 0x240 -#define RXPHDR_FMT (1 << 24) /* 0:SP 1:LP */ +#define RXPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */ #define RXPHDR_VC(n) (((n) & 0x3) << 22) #define RXPHDR_DT(n) (((n) & 0x3f) << 16) #define RXPHDR_DATA1(n) (((n) & 0xff) << 8) @@ -128,39 +128,39 @@ #define TASCR 0x514 #define TAIER 0x518 #define TOSR 0x610 -#define TOSR_TATO (1 << 2) -#define TOSR_LRXHTO (1 << 1) -#define TOSR_HRXTO (1 << 0) +#define TOSR_TATO BIT_U32(2) +#define TOSR_LRXHTO BIT_U32(1) +#define TOSR_HRXTO BIT_U32(0) #define TOSCR 0x614 -#define TOSCR_TATO (1 << 2) -#define TOSCR_LRXHTO (1 << 1) -#define TOSCR_HRXTO (1 << 0) +#define TOSCR_TATO BIT_U32(2) +#define TOSCR_LRXHTO BIT_U32(1) +#define TOSCR_HRXTO BIT_U32(0) /* * Video Mode Register */ #define TXVMSETR 0x180 -#define TXVMSETR_SYNSEQ_EVENTS (1 << 16) /* 0:Pulses 1:Events */ -#define TXVMSETR_VSTPM (1 << 15) -#define TXVMSETR_PIXWDTH_MASK (7 << 8) -#define TXVMSETR_PIXWDTH (1 << 8) /* Only allowed value */ -#define TXVMSETR_VSEN (1 << 4) -#define TXVMSETR_HFPBPEN (1 << 2) -#define TXVMSETR_HBPBPEN (1 << 1) -#define TXVMSETR_HSABPEN (1 << 0) +#define TXVMSETR_SYNSEQ_EVENTS BIT_U32(16) /* 0:Pulses 1:Events */ +#define TXVMSETR_VSTPM BIT_U32(15) +#define TXVMSETR_PIXWDTH_MASK GENMASK(10, 8) +#define TXVMSETR_PIXWDTH BIT_U32(8) /* Only allowed value */ +#define TXVMSETR_VSEN BIT_U32(4) +#define TXVMSETR_HFPBPEN BIT_U32(2) +#define TXVMSETR_HBPBPEN BIT_U32(1) +#define TXVMSETR_HSABPEN BIT_U32(0) #define TXVMCR 0x190 -#define TXVMCR_VFCLR (1 << 12) -#define TXVMCR_EN_VIDEO (1 << 0) +#define TXVMCR_VFCLR BIT_U32(12) +#define TXVMCR_EN_VIDEO BIT_U32(0) #define TXVMSR 0x1a0 -#define TXVMSR_STR (1 << 16) -#define TXVMSR_VFRDY (1 << 12) -#define TXVMSR_ACT (1 << 8) -#define TXVMSR_RDY (1 << 0) +#define TXVMSR_STR BIT_U32(16) +#define TXVMSR_VFRDY BIT_U32(12) +#define TXVMSR_ACT BIT_U32(8) +#define TXVMSR_RDY BIT_U32(0) #define TXVMSCR 0x1a4 -#define TXVMSCR_STR (1 << 16) +#define TXVMSCR_STR BIT_U32(16) #define TXVMPSPHSETR 0x1c0 #define TXVMPSPHSETR_DT_MASK (0x3f << 16) @@ -171,10 +171,10 @@ #define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c) #define TXVMVPRMSET0R 0x1d0 -#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) /* 0:High 1:Low */ -#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) /* 0:High 1:Low */ -#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) /* 0:RGB 1:YCbCr */ -#define TXVMVPRMSET0R_BPP_MASK (7 << 0) +#define TXVMVPRMSET0R_HSPOL_LOW BIT_U32(17) /* 0:High 1:Low */ +#define TXVMVPRMSET0R_VSPOL_LOW BIT_U32(16) /* 0:High 1:Low */ +#define TXVMVPRMSET0R_CSPC_YCbCr BIT_U32(4) /* 0:RGB 1:YCbCr */ +#define TXVMVPRMSET0R_BPP_MASK GENMASK(2, 0) #define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0) #define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1) #define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2) @@ -199,51 +199,51 @@ * PHY-Protocol Interface (PPI) Registers */ #define PPISETR 0x700 -#define PPISETR_DLEN_MASK (0xf << 0) -#define PPISETR_CLEN (1 << 8) +#define PPISETR_DLEN_MASK GENMASK(3, 0) +#define PPISETR_CLEN BIT_U32(8) #define PPICLCR 0x710 -#define PPICLCR_TXREQHS (1 << 8) -#define PPICLCR_TXULPSEXT (1 << 1) -#define PPICLCR_TXULPSCLK (1 << 0) +#define PPICLCR_TXREQHS BIT_U32(8) +#define PPICLCR_TXULPSEXT BIT_U32(1) +#define PPICLCR_TXULPSCLK BIT_U32(0) #define PPICLSR 0x720 -#define PPICLSR_HSTOLP (1 << 27) -#define PPICLSR_TOHS (1 << 26) -#define PPICLSR_STPST (1 << 0) +#define PPICLSR_HSTOLP BIT_U32(27) +#define PPICLSR_TOHS BIT_U32(26) +#define PPICLSR_STPST BIT_U32(0) #define PPICLSCR 0x724 -#define PPICLSCR_HSTOLP (1 << 27) -#define PPICLSCR_TOHS (1 << 26) +#define PPICLSCR_HSTOLP BIT_U32(27) +#define PPICLSCR_TOHS BIT_U32(26) #define PPIDL0SR 0x740 -#define PPIDL0SR_DIR (1 << 10) -#define PPIDL0SR_STPST (1 << 6) +#define PPIDL0SR_DIR BIT_U32(10) +#define PPIDL0SR_STPST BIT_U32(6) #define PPIDLSR 0x760 -#define PPIDLSR_STPST (0xf << 0) +#define PPIDLSR_STPST GENMASK(3, 0) /* * Clocks registers */ #define LPCLKSET 0x1000 -#define LPCLKSET_CKEN (1 << 8) +#define LPCLKSET_CKEN BIT_U32(8) #define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0) #define CFGCLKSET 0x1004 -#define CFGCLKSET_CKEN (1 << 8) +#define CFGCLKSET_CKEN BIT_U32(8) #define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0) #define DOTCLKDIV 0x1008 -#define DOTCLKDIV_CKEN (1 << 8) +#define DOTCLKDIV_CKEN BIT_U32(8) #define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0) #define VCLKSET 0x100c -#define VCLKSET_CKEN (1 << 16) -#define VCLKSET_COLOR_YCC (1 << 8) /* 0:RGB 1:YCbCr */ +#define VCLKSET_CKEN BIT_U32(16) +#define VCLKSET_COLOR_YCC BIT_U32(8) /* 0:RGB 1:YCbCr */ #define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4) #define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4) -#define VCLKSET_BPP_MASK (3 << 2) +#define VCLKSET_BPP_MASK GENMASK(3, 2) #define VCLKSET_BPP_16 FIELD_PREP(VCLKSET_BPP_MASK, 0) #define VCLKSET_BPP_18 FIELD_PREP(VCLKSET_BPP_MASK, 1) #define VCLKSET_BPP_18L FIELD_PREP(VCLKSET_BPP_MASK, 2) @@ -251,24 +251,24 @@ #define VCLKSET_LANE(x) (((x) & 0x3) << 0) #define VCLKEN 0x1010 -#define VCLKEN_CKEN (1 << 0) +#define VCLKEN_CKEN BIT_U32(0) #define PHYSETUP 0x1014 #define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16) -#define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16) +#define PHYSETUP_HSFREQRANGE_MASK GENMASK(22, 16) #define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8) -#define PHYSETUP_SHUTDOWNZ (1 << 1) -#define PHYSETUP_RSTZ (1 << 0) +#define PHYSETUP_SHUTDOWNZ BIT_U32(1) +#define PHYSETUP_RSTZ BIT_U32(0) #define CLOCKSET1 0x101c -#define CLOCKSET1_LOCK_PHY (1 << 17) -#define CLOCKSET1_CLKSEL (1 << 8) -#define CLOCKSET1_CLKINSEL_MASK (3 << 2) +#define CLOCKSET1_LOCK_PHY BIT_U32(17) +#define CLOCKSET1_CLKSEL BIT_U32(8) +#define CLOCKSET1_CLKINSEL_MASK GENMASK(3, 2) #define CLOCKSET1_CLKINSEL_EXTAL FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0) #define CLOCKSET1_CLKINSEL_DIG FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1) #define CLOCKSET1_CLKINSEL_DU FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2) -#define CLOCKSET1_SHADOW_CLEAR (1 << 1) -#define CLOCKSET1_UPDATEPLL (1 << 0) +#define CLOCKSET1_SHADOW_CLEAR BIT_U32(1) +#define CLOCKSET1_UPDATEPLL BIT_U32(0) #define CLOCKSET2 0x1020 #define CLOCKSET2_M(x) (((x) & 0xfff) << 16) @@ -282,16 +282,16 @@ #define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0) #define PHTW 0x1034 -#define PHTW_DWEN (1 << 24) +#define PHTW_DWEN BIT_U32(24) #define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16) -#define PHTW_CWEN (1 << 8) +#define PHTW_CWEN BIT_U32(8) #define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0) #define PHTR 0x1038 -#define PHTR_TESTDOUT (0xff << 16) -#define PHTR_TESTDOUT_TEST (1 << 16) +#define PHTR_TESTDOUT GENMASK(23, 16) +#define PHTR_TESTDOUT_TEST BIT_U32(16) #define PHTC 0x103c -#define PHTC_TESTCLR (1 << 0) +#define PHTC_TESTCLR BIT_U32(0) #endif /* __RCAR_MIPI_DSI_REGS_H__ */ -- cgit v1.2.3 From 4f716a1db661cfb31502a0a6d7e62c06daf2e603 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Oct 2025 00:28:21 +0100 Subject: drm/rcar-du: dsi: Convert register bitfields to GENMASK() macro Convert register bitfields to GENMASK() macro where applicable. Use FIELD_PREP() throughout the driver. Reviewed-by: Tomi Valkeinen Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20251028232959.109936-12-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen --- .../gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 118 ++++++++++++--------- 1 file changed, 70 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h index d3a1b91637ed..b6fb58c2f9f6 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h @@ -13,7 +13,7 @@ #define LINKSR_HSBUSY BIT_U32(0) #define TXSETR 0x100 -#define TXSETR_LANECNT_MASK GENMASK(1, 0) +#define TXSETR_LANECNT_MASK GENMASK_U32(1, 0) /* * DSI Command Transfer Registers @@ -40,18 +40,22 @@ #define TXCMADDRSET0R 0x140 #define TXCMPHDR 0x150 #define TXCMPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */ -#define TXCMPHDR_VC(n) (((n) & 0x3) << 22) -#define TXCMPHDR_DT(n) (((n) & 0x3f) << 16) -#define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8) -#define TXCMPHDR_DATA0(n) (((n) & 0xff) << 0) +#define TXCMPHDR_VC_MASK GENMASK_U32(23, 22) +#define TXCMPHDR_VC(n) FIELD_PREP(TXCMPHDR_VC_MASK, (n)) +#define TXCMPHDR_DT_MASK GENMASK_U32(21, 16) +#define TXCMPHDR_DT(n) FIELD_PREP(TXCMPHDR_DT_MASK, (n)) +#define TXCMPHDR_DATA1_MASK GENMASK_U32(15, 8) +#define TXCMPHDR_DATA1(n) FIELD_PREP(TXCMPHDR_DATA1_MASK, (n)) +#define TXCMPHDR_DATA0_MASK GENMASK_U32(7, 0) +#define TXCMPHDR_DATA0(n) FIELD_PREP(TXCMPHDR_DATA0_MASK, (n)) #define TXCMPPD0R 0x160 #define TXCMPPD1R 0x164 #define TXCMPPD2R 0x168 #define TXCMPPD3R 0x16c #define RXSETR 0x200 -#define RXSETR_CRCEN(n) (((n) & 0xf) << 24) -#define RXSETR_ECCEN(n) (((n) & 0xf) << 16) +#define RXSETR_CRCEN_MASK GENMASK_U32(27, 24) +#define RXSETR_ECCEN_MASK GENMASK_U32(19, 16) #define RXPSETR 0x210 #define RXPSETR_LPPDACC BIT_U32(0) #define RXPSR 0x220 @@ -107,21 +111,21 @@ #define RXPIER_BTAREQEND BIT_U32(0) #define RXPADDRSET0R 0x230 #define RXPSIZESETR 0x238 -#define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3) +#define RXPSIZESETR_SIZE_MASK GENMASK_U32(6, 3) #define RXPHDR 0x240 #define RXPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */ -#define RXPHDR_VC(n) (((n) & 0x3) << 22) -#define RXPHDR_DT(n) (((n) & 0x3f) << 16) -#define RXPHDR_DATA1(n) (((n) & 0xff) << 8) -#define RXPHDR_DATA0(n) (((n) & 0xff) << 0) +#define RXPHDR_VC_MASK GENMASK_U32(23, 22) +#define RXPHDR_DT_MASK GENMASK_U32(21, 16) +#define RXPHDR_DATA1_MASK GENMASK_U32(15, 8) +#define RXPHDR_DATA0_MASK GENMASK_U32(7, 0) #define RXPPD0R 0x250 #define RXPPD1R 0x254 #define RXPPD2R 0x258 #define RXPPD3R 0x25c #define AKEPR 0x300 -#define AKEPR_VC(n) (((n) & 0x3) << 22) -#define AKEPR_DT(n) (((n) & 0x3f) << 16) -#define AKEPR_ERRRPT(n) (((n) & 0xffff) << 0) +#define AKEPR_VC_MASK GENMASK_U32(23, 22) +#define AKEPR_DT_MASK GENMASK_U32(21, 16) +#define AKEPR_ERRRPT_MASK GENMASK_U32(15, 0) #define RXRESPTOSETR 0x400 #define TACR 0x500 #define TASR 0x510 @@ -142,7 +146,7 @@ #define TXVMSETR 0x180 #define TXVMSETR_SYNSEQ_EVENTS BIT_U32(16) /* 0:Pulses 1:Events */ #define TXVMSETR_VSTPM BIT_U32(15) -#define TXVMSETR_PIXWDTH_MASK GENMASK(10, 8) +#define TXVMSETR_PIXWDTH_MASK GENMASK_U32(10, 8) #define TXVMSETR_PIXWDTH BIT_U32(8) /* Only allowed value */ #define TXVMSETR_VSEN BIT_U32(4) #define TXVMSETR_HFPBPEN BIT_U32(2) @@ -174,32 +178,40 @@ #define TXVMVPRMSET0R_HSPOL_LOW BIT_U32(17) /* 0:High 1:Low */ #define TXVMVPRMSET0R_VSPOL_LOW BIT_U32(16) /* 0:High 1:Low */ #define TXVMVPRMSET0R_CSPC_YCbCr BIT_U32(4) /* 0:RGB 1:YCbCr */ -#define TXVMVPRMSET0R_BPP_MASK GENMASK(2, 0) +#define TXVMVPRMSET0R_BPP_MASK GENMASK_U32(2, 0) #define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0) #define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1) #define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2) #define TXVMVPRMSET1R 0x1d4 -#define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16) -#define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0) +#define TXVMVPRMSET1R_VACTIVE_MASK GENMASK_U32(30, 16) +#define TXVMVPRMSET1R_VACTIVE(n) FIELD_PREP(TXVMVPRMSET1R_VACTIVE_MASK, (n)) +#define TXVMVPRMSET1R_VSA_MASK GENMASK_U32(11, 0) +#define TXVMVPRMSET1R_VSA(n) FIELD_PREP(TXVMVPRMSET1R_VSA_MASK, (n)) #define TXVMVPRMSET2R 0x1d8 -#define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16) -#define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0) +#define TXVMVPRMSET2R_VFP_MASK GENMASK_U32(28, 16) +#define TXVMVPRMSET2R_VFP(n) FIELD_PREP(TXVMVPRMSET2R_VFP_MASK, (n)) +#define TXVMVPRMSET2R_VBP_MASK GENMASK_U32(12, 0) +#define TXVMVPRMSET2R_VBP(n) FIELD_PREP(TXVMVPRMSET2R_VBP_MASK, (n)) #define TXVMVPRMSET3R 0x1dc -#define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16) -#define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0) +#define TXVMVPRMSET3R_HACTIVE_MASK GENMASK_U32(30, 16) +#define TXVMVPRMSET3R_HACTIVE(n) FIELD_PREP(TXVMVPRMSET3R_HACTIVE_MASK, (n)) +#define TXVMVPRMSET3R_HSA_MASK GENMASK_U32(11, 0) +#define TXVMVPRMSET3R_HSA(n) FIELD_PREP(TXVMVPRMSET3R_HSA_MASK, (n)) #define TXVMVPRMSET4R 0x1e0 -#define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16) -#define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0) +#define TXVMVPRMSET4R_HFP_MASK GENMASK_U32(28, 16) +#define TXVMVPRMSET4R_HFP(n) FIELD_PREP(TXVMVPRMSET4R_HFP_MASK, (n)) +#define TXVMVPRMSET4R_HBP_MASK GENMASK_U32(12, 0) +#define TXVMVPRMSET4R_HBP(n) FIELD_PREP(TXVMVPRMSET4R_HBP_MASK, (n)) /* * PHY-Protocol Interface (PPI) Registers */ #define PPISETR 0x700 -#define PPISETR_DLEN_MASK GENMASK(3, 0) +#define PPISETR_DLEN_MASK GENMASK_U32(3, 0) #define PPISETR_CLEN BIT_U32(8) #define PPICLCR 0x710 @@ -221,49 +233,52 @@ #define PPIDL0SR_STPST BIT_U32(6) #define PPIDLSR 0x760 -#define PPIDLSR_STPST GENMASK(3, 0) +#define PPIDLSR_STPST GENMASK_U32(3, 0) /* * Clocks registers */ #define LPCLKSET 0x1000 #define LPCLKSET_CKEN BIT_U32(8) -#define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0) +#define LPCLKSET_LPCLKDIV_MASK GENMASK_U32(5, 0) #define CFGCLKSET 0x1004 #define CFGCLKSET_CKEN BIT_U32(8) -#define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0) +#define CFGCLKSET_CFGCLKDIV_MASK GENMASK_U32(5, 0) #define DOTCLKDIV 0x1008 #define DOTCLKDIV_CKEN BIT_U32(8) -#define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0) +#define DOTCLKDIV_DOTCLKDIV_MASK GENMASK_U32(5, 0) #define VCLKSET 0x100c #define VCLKSET_CKEN BIT_U32(16) #define VCLKSET_COLOR_YCC BIT_U32(8) /* 0:RGB 1:YCbCr */ -#define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4) -#define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4) -#define VCLKSET_BPP_MASK GENMASK(3, 2) +#define VCLKSET_DIV_V3U_MASK GENMASK_U32(5, 4) +#define VCLKSET_DIV_V3U(n) FIELD_PREP(VCLKSET_DIV_V3U_MASK, (n)) +#define VCLKSET_DIV_V4H_MASK GENMASK_U32(6, 4) +#define VCLKSET_DIV_V4H(n) FIELD_PREP(VCLKSET_DIV_V4H_MASK, (n)) +#define VCLKSET_BPP_MASK GENMASK_U32(3, 2) #define VCLKSET_BPP_16 FIELD_PREP(VCLKSET_BPP_MASK, 0) #define VCLKSET_BPP_18 FIELD_PREP(VCLKSET_BPP_MASK, 1) #define VCLKSET_BPP_18L FIELD_PREP(VCLKSET_BPP_MASK, 2) #define VCLKSET_BPP_24 FIELD_PREP(VCLKSET_BPP_MASK, 3) -#define VCLKSET_LANE(x) (((x) & 0x3) << 0) +#define VCLKSET_LANE_MASK GENMASK_U32(1, 0) +#define VCLKSET_LANE(n) FIELD_PREP(VCLKSET_LANE_MASK, (n)) #define VCLKEN 0x1010 #define VCLKEN_CKEN BIT_U32(0) #define PHYSETUP 0x1014 -#define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16) -#define PHYSETUP_HSFREQRANGE_MASK GENMASK(22, 16) -#define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8) +#define PHYSETUP_HSFREQRANGE_MASK GENMASK_U32(22, 16) +#define PHYSETUP_HSFREQRANGE(n) FIELD_PREP(PHYSETUP_HSFREQRANGE_MASK, (n)) +#define PHYSETUP_CFGCLKFREQRANGE_MASK GENMASK_U32(13, 8) #define PHYSETUP_SHUTDOWNZ BIT_U32(1) #define PHYSETUP_RSTZ BIT_U32(0) #define CLOCKSET1 0x101c #define CLOCKSET1_LOCK_PHY BIT_U32(17) #define CLOCKSET1_CLKSEL BIT_U32(8) -#define CLOCKSET1_CLKINSEL_MASK GENMASK(3, 2) +#define CLOCKSET1_CLKINSEL_MASK GENMASK_U32(3, 2) #define CLOCKSET1_CLKINSEL_EXTAL FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 0) #define CLOCKSET1_CLKINSEL_DIG FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 1) #define CLOCKSET1_CLKINSEL_DU FIELD_PREP(CLOCKSET1_CLKINSEL_MASK, 2) @@ -271,24 +286,31 @@ #define CLOCKSET1_UPDATEPLL BIT_U32(0) #define CLOCKSET2 0x1020 -#define CLOCKSET2_M(x) (((x) & 0xfff) << 16) -#define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8) -#define CLOCKSET2_N(x) (((x) & 0xf) << 0) +#define CLOCKSET2_M_MASK GENMASK_U32(27, 16) +#define CLOCKSET2_M(n) FIELD_PREP(CLOCKSET2_M_MASK, (n)) +#define CLOCKSET2_VCO_CNTRL_MASK GENMASK_U32(13, 8) +#define CLOCKSET2_VCO_CNTRL(n) FIELD_PREP(CLOCKSET2_VCO_CNTRL_MASK, (n)) +#define CLOCKSET2_N_MASK GENMASK_U32(3, 0) +#define CLOCKSET2_N(n) FIELD_PREP(CLOCKSET2_N_MASK, (n)) #define CLOCKSET3 0x1024 -#define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24) -#define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16) -#define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8) -#define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0) +#define CLOCKSET3_PROP_CNTRL_MASK GENMASK_U32(29, 24) +#define CLOCKSET3_PROP_CNTRL(n) FIELD_PREP(CLOCKSET3_PROP_CNTRL_MASK, (n)) +#define CLOCKSET3_INT_CNTRL_MASK GENMASK_U32(21, 16) +#define CLOCKSET3_INT_CNTRL(n) FIELD_PREP(CLOCKSET3_INT_CNTRL_MASK, (n)) +#define CLOCKSET3_CPBIAS_CNTRL_MASK GENMASK_U32(14, 8) +#define CLOCKSET3_CPBIAS_CNTRL(n) FIELD_PREP(CLOCKSET3_CPBIAS_CNTRL_MASK, (n)) +#define CLOCKSET3_GMP_CNTRL_MASK GENMASK_U32(1, 0) +#define CLOCKSET3_GMP_CNTRL(n) FIELD_PREP(CLOCKSET3_GMP_CNTRL_MASK, (n)) #define PHTW 0x1034 #define PHTW_DWEN BIT_U32(24) -#define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16) +#define PHTW_TESTDIN_DATA_MASK GENMASK_U32(23, 16) #define PHTW_CWEN BIT_U32(8) -#define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0) +#define PHTW_TESTDIN_CODE_MASK GENMASK_U32(7, 0) #define PHTR 0x1038 -#define PHTR_TESTDOUT GENMASK(23, 16) +#define PHTR_TESTDOUT GENMASK_U32(23, 16) #define PHTR_TESTDOUT_TEST BIT_U32(16) #define PHTC 0x103c -- cgit v1.2.3 From c063c1bbee67391f12956d2ffdd5da00eb87ff79 Mon Sep 17 00:00:00 2001 From: Maciej Falkowski Date: Mon, 27 Oct 2025 16:09:32 +0100 Subject: accel/ivpu: Remove skip of dma unmap for imported buffers Rework of imported buffers introduced in the commit e0c0891cd63b ("accel/ivpu: Rework bind/unbind of imported buffers") switched the logic of imported buffers by dma mapping/unmapping them just as the regular buffers. The commit didn't include removal of skipping dma unmap of imported buffers which results in them being mapped without unmapping. Fixes: e0c0891cd63b ("accel/ivpu: Rework bind/unbind of imported buffers") Reviewed-by: Jeff Hugo Reviewed-by: Karol Wachowski Signed-off-by: Maciej Falkowski Link: https://patch.msgid.link/20251027150933.2384538-1-maciej.falkowski@linux.intel.com --- drivers/accel/ivpu/ivpu_gem.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/accel/ivpu/ivpu_gem.c b/drivers/accel/ivpu/ivpu_gem.c index e7277e02840a..2a159535421a 100644 --- a/drivers/accel/ivpu/ivpu_gem.c +++ b/drivers/accel/ivpu/ivpu_gem.c @@ -158,9 +158,6 @@ static void ivpu_bo_unbind_locked(struct ivpu_bo *bo) bo->ctx = NULL; } - if (drm_gem_is_imported(&bo->base.base)) - return; - if (bo->base.sgt) { if (bo->base.base.import_attach) { dma_buf_unmap_attachment(bo->base.base.import_attach, -- cgit v1.2.3 From c57e43231ed73f3f385d14f1358114643f13d767 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 27 Oct 2025 15:39:56 +0200 Subject: accel/ivpu: Remove redundant pm_runtime_mark_last_busy() calls pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus Reviewed-by: Jacek Lawrynowicz Reviewed-by: Maciej Falkowski Reviewed-by: Karol Wachowski Signed-off-by: Maciej Falkowski Link: https://patch.msgid.link/20251027133956.393375-1-sakari.ailus@linux.intel.com --- drivers/accel/ivpu/ivpu_job.c | 1 - drivers/accel/ivpu/ivpu_pm.c | 2 -- 2 files changed, 3 deletions(-) diff --git a/drivers/accel/ivpu/ivpu_job.c b/drivers/accel/ivpu/ivpu_job.c index ba4535a75aa7..4eb7287cd083 100644 --- a/drivers/accel/ivpu/ivpu_job.c +++ b/drivers/accel/ivpu/ivpu_job.c @@ -1114,6 +1114,5 @@ void ivpu_context_abort_work_fn(struct work_struct *work) mutex_unlock(&vdev->submitted_jobs_lock); runtime_put: - pm_runtime_mark_last_busy(vdev->drm.dev); pm_runtime_put_autosuspend(vdev->drm.dev); } diff --git a/drivers/accel/ivpu/ivpu_pm.c b/drivers/accel/ivpu/ivpu_pm.c index 63c95307faa1..fe6f93af6ab0 100644 --- a/drivers/accel/ivpu/ivpu_pm.c +++ b/drivers/accel/ivpu/ivpu_pm.c @@ -359,7 +359,6 @@ int ivpu_rpm_get(struct ivpu_device *vdev) void ivpu_rpm_put(struct ivpu_device *vdev) { - pm_runtime_mark_last_busy(vdev->drm.dev); pm_runtime_put_autosuspend(vdev->drm.dev); } @@ -428,7 +427,6 @@ void ivpu_pm_enable(struct ivpu_device *vdev) struct device *dev = vdev->drm.dev; pm_runtime_allow(dev); - pm_runtime_mark_last_busy(dev); pm_runtime_put_autosuspend(dev); } -- cgit v1.2.3 From b21c47d71bc321785d61e6649bf1992ff157514d Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Thu, 19 Jun 2025 16:22:09 +0300 Subject: drm/panel: nv3052c: Reduce duplication of init sequences Although there are various small changes between the init sequences, the second half is common for all 3 currently supported displays. Note that this is only compile-tested. Signed-off-by: Priit Laes Tested-by: John Watts Reviewed-by: John Watts Signed-off-by: Neil Armstrong Link: https://patch.msgid.link/20250619132211.556027-1-plaes@plaes.org --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 408 +++++------------------- 1 file changed, 74 insertions(+), 334 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c index 0db9cadd868e..18130bc14201 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -43,59 +43,12 @@ struct nv3052c { struct gpio_desc *reset_gpio; }; -static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { - // EXTC Command set enable, select page 1 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, - // Mostly unknown registers - { 0xe3, 0x00 }, - { 0x40, 0x00 }, - { 0x03, 0x40 }, - { 0x04, 0x00 }, - { 0x05, 0x03 }, - { 0x08, 0x00 }, - { 0x09, 0x07 }, - { 0x0a, 0x01 }, - { 0x0b, 0x32 }, - { 0x0c, 0x32 }, - { 0x0d, 0x0b }, - { 0x0e, 0x00 }, - { 0x23, 0xa0 }, - { 0x24, 0x0c }, - { 0x25, 0x06 }, - { 0x26, 0x14 }, - { 0x27, 0x14 }, - { 0x38, 0xcc }, // VCOM_ADJ1 - { 0x39, 0xd7 }, // VCOM_ADJ2 - { 0x3a, 0x4a }, // VCOM_ADJ3 - { 0x28, 0x40 }, - { 0x29, 0x01 }, - { 0x2a, 0xdf }, - { 0x49, 0x3c }, - { 0x91, 0x77 }, // EXTPW_CTRL2 - { 0x92, 0x77 }, // EXTPW_CTRL3 - { 0xa0, 0x55 }, - { 0xa1, 0x50 }, - { 0xa4, 0x9c }, - { 0xa7, 0x02 }, - { 0xa8, 0x01 }, - { 0xa9, 0x01 }, - { 0xaa, 0xfc }, - { 0xab, 0x28 }, - { 0xac, 0x06 }, - { 0xad, 0x06 }, - { 0xae, 0x06 }, - { 0xaf, 0x03 }, - { 0xb0, 0x08 }, - { 0xb1, 0x26 }, - { 0xb2, 0x28 }, - { 0xb3, 0x28 }, - { 0xb4, 0x33 }, - { 0xb5, 0x08 }, - { 0xb6, 0x26 }, - { 0xb7, 0x08 }, - { 0xb8, 0x26 }, - { 0xf0, 0x00 }, - { 0xf6, 0xc0 }, +/* + * Common initialization registers for all currently + * supported displays. Mostly seem to be related + * to Gamma correction curves and output pad mappings. + */ +static const struct nv3052c_reg common_init_regs[] = { // EXTC Command set enable, select page 2 { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, // Set gray scale voltage to adjust gamma @@ -215,7 +168,7 @@ static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { { 0xa0, 0x01 }, // PANELU2D33 // EXTC Command set enable, select page 2 { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, - // Unknown registers + // Page 2 register values (0x01..0x10) are same for nv3051d and nv3052c { 0x01, 0x01 }, { 0x02, 0xda }, { 0x03, 0xba }, @@ -236,6 +189,62 @@ static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, // Display Access Control { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 + +}; + +static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0xa0 }, + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0xcc }, // VCOM_ADJ1 + { 0x39, 0xd7 }, // VCOM_ADJ2 + { 0x3a, 0x4a }, // VCOM_ADJ3 + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x77 }, // EXTPW_CTRL2 + { 0x92, 0x77 }, // EXTPW_CTRL3 + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x33 }, + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, }; static const struct nv3052c_reg fs035vg158_panel_regs[] = { @@ -291,146 +300,6 @@ static const struct nv3052c_reg fs035vg158_panel_regs[] = { { 0xb8, 0x26 }, { 0xf0, 0x00 }, { 0xf6, 0xc0 }, - // EXTC Command set enable, select page 0 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, - // Set gray scale voltage to adjust gamma - { 0xb0, 0x0b }, // PGAMVR0 - { 0xb1, 0x16 }, // PGAMVR1 - { 0xb2, 0x17 }, // PGAMVR2 - { 0xb3, 0x2c }, // PGAMVR3 - { 0xb4, 0x32 }, // PGAMVR4 - { 0xb5, 0x3b }, // PGAMVR5 - { 0xb6, 0x29 }, // PGAMPR0 - { 0xb7, 0x40 }, // PGAMPR1 - { 0xb8, 0x0d }, // PGAMPK0 - { 0xb9, 0x05 }, // PGAMPK1 - { 0xba, 0x12 }, // PGAMPK2 - { 0xbb, 0x10 }, // PGAMPK3 - { 0xbc, 0x12 }, // PGAMPK4 - { 0xbd, 0x15 }, // PGAMPK5 - { 0xbe, 0x19 }, // PGAMPK6 - { 0xbf, 0x0e }, // PGAMPK7 - { 0xc0, 0x16 }, // PGAMPK8 - { 0xc1, 0x0a }, // PGAMPK9 - // Set gray scale voltage to adjust gamma - { 0xd0, 0x0c }, // NGAMVR0 - { 0xd1, 0x17 }, // NGAMVR0 - { 0xd2, 0x14 }, // NGAMVR1 - { 0xd3, 0x2e }, // NGAMVR2 - { 0xd4, 0x32 }, // NGAMVR3 - { 0xd5, 0x3c }, // NGAMVR4 - { 0xd6, 0x22 }, // NGAMPR0 - { 0xd7, 0x3d }, // NGAMPR1 - { 0xd8, 0x0d }, // NGAMPK0 - { 0xd9, 0x07 }, // NGAMPK1 - { 0xda, 0x13 }, // NGAMPK2 - { 0xdb, 0x13 }, // NGAMPK3 - { 0xdc, 0x11 }, // NGAMPK4 - { 0xdd, 0x15 }, // NGAMPK5 - { 0xde, 0x19 }, // NGAMPK6 - { 0xdf, 0x10 }, // NGAMPK7 - { 0xe0, 0x17 }, // NGAMPK8 - { 0xe1, 0x0a }, // NGAMPK9 - // EXTC Command set enable, select page 3 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, - // Set various timing settings - { 0x00, 0x2a }, // GIP_VST_1 - { 0x01, 0x2a }, // GIP_VST_2 - { 0x02, 0x2a }, // GIP_VST_3 - { 0x03, 0x2a }, // GIP_VST_4 - { 0x04, 0x61 }, // GIP_VST_5 - { 0x05, 0x80 }, // GIP_VST_6 - { 0x06, 0xc7 }, // GIP_VST_7 - { 0x07, 0x01 }, // GIP_VST_8 - { 0x08, 0x03 }, // GIP_VST_9 - { 0x09, 0x04 }, // GIP_VST_10 - { 0x70, 0x22 }, // GIP_ECLK1 - { 0x71, 0x80 }, // GIP_ECLK2 - { 0x30, 0x2a }, // GIP_CLK_1 - { 0x31, 0x2a }, // GIP_CLK_2 - { 0x32, 0x2a }, // GIP_CLK_3 - { 0x33, 0x2a }, // GIP_CLK_4 - { 0x34, 0x61 }, // GIP_CLK_5 - { 0x35, 0xc5 }, // GIP_CLK_6 - { 0x36, 0x80 }, // GIP_CLK_7 - { 0x37, 0x23 }, // GIP_CLK_8 - { 0x40, 0x03 }, // GIP_CLKA_1 - { 0x41, 0x04 }, // GIP_CLKA_2 - { 0x42, 0x05 }, // GIP_CLKA_3 - { 0x43, 0x06 }, // GIP_CLKA_4 - { 0x44, 0x11 }, // GIP_CLKA_5 - { 0x45, 0xe8 }, // GIP_CLKA_6 - { 0x46, 0xe9 }, // GIP_CLKA_7 - { 0x47, 0x11 }, // GIP_CLKA_8 - { 0x48, 0xea }, // GIP_CLKA_9 - { 0x49, 0xeb }, // GIP_CLKA_10 - { 0x50, 0x07 }, // GIP_CLKB_1 - { 0x51, 0x08 }, // GIP_CLKB_2 - { 0x52, 0x09 }, // GIP_CLKB_3 - { 0x53, 0x0a }, // GIP_CLKB_4 - { 0x54, 0x11 }, // GIP_CLKB_5 - { 0x55, 0xec }, // GIP_CLKB_6 - { 0x56, 0xed }, // GIP_CLKB_7 - { 0x57, 0x11 }, // GIP_CLKB_8 - { 0x58, 0xef }, // GIP_CLKB_9 - { 0x59, 0xf0 }, // GIP_CLKB_10 - // Map internal GOA signals to GOA output pad - { 0xb1, 0x01 }, // PANELD2U2 - { 0xb4, 0x15 }, // PANELD2U5 - { 0xb5, 0x16 }, // PANELD2U6 - { 0xb6, 0x09 }, // PANELD2U7 - { 0xb7, 0x0f }, // PANELD2U8 - { 0xb8, 0x0d }, // PANELD2U9 - { 0xb9, 0x0b }, // PANELD2U10 - { 0xba, 0x00 }, // PANELD2U11 - { 0xc7, 0x02 }, // PANELD2U24 - { 0xca, 0x17 }, // PANELD2U27 - { 0xcb, 0x18 }, // PANELD2U28 - { 0xcc, 0x0a }, // PANELD2U29 - { 0xcd, 0x10 }, // PANELD2U30 - { 0xce, 0x0e }, // PANELD2U31 - { 0xcf, 0x0c }, // PANELD2U32 - { 0xd0, 0x00 }, // PANELD2U33 - // Map internal GOA signals to GOA output pad - { 0x81, 0x00 }, // PANELU2D2 - { 0x84, 0x15 }, // PANELU2D5 - { 0x85, 0x16 }, // PANELU2D6 - { 0x86, 0x10 }, // PANELU2D7 - { 0x87, 0x0a }, // PANELU2D8 - { 0x88, 0x0c }, // PANELU2D9 - { 0x89, 0x0e }, // PANELU2D10 - { 0x8a, 0x02 }, // PANELU2D11 - { 0x97, 0x00 }, // PANELU2D24 - { 0x9a, 0x17 }, // PANELU2D27 - { 0x9b, 0x18 }, // PANELU2D28 - { 0x9c, 0x0f }, // PANELU2D29 - { 0x9d, 0x09 }, // PANELU2D30 - { 0x9e, 0x0b }, // PANELU2D31 - { 0x9f, 0x0d }, // PANELU2D32 - { 0xa0, 0x01 }, // PANELU2D33 - // EXTC Command set enable, select page 2 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, - // Unknown registers - { 0x01, 0x01 }, - { 0x02, 0xda }, - { 0x03, 0xba }, - { 0x04, 0xa8 }, - { 0x05, 0x9a }, - { 0x06, 0x70 }, - { 0x07, 0xff }, - { 0x08, 0x91 }, - { 0x09, 0x90 }, - { 0x0a, 0xff }, - { 0x0b, 0x8f }, - { 0x0c, 0x60 }, - { 0x0d, 0x58 }, - { 0x0e, 0x48 }, - { 0x0f, 0x38 }, - { 0x10, 0x2b }, - // EXTC Command set enable, select page 0 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, - // Display Access Control - { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 }; @@ -487,146 +356,6 @@ static const struct nv3052c_reg wl_355608_a8_panel_regs[] = { { 0xb8, 0x26 }, { 0xf0, 0x00 }, { 0xf6, 0xc0 }, - // EXTC Command set enable, select page 2 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, - // Set gray scale voltage to adjust gamma - { 0xb0, 0x0b }, // PGAMVR0 - { 0xb1, 0x16 }, // PGAMVR1 - { 0xb2, 0x17 }, // PGAMVR2 - { 0xb3, 0x2c }, // PGAMVR3 - { 0xb4, 0x32 }, // PGAMVR4 - { 0xb5, 0x3b }, // PGAMVR5 - { 0xb6, 0x29 }, // PGAMPR0 - { 0xb7, 0x40 }, // PGAMPR1 - { 0xb8, 0x0d }, // PGAMPK0 - { 0xb9, 0x05 }, // PGAMPK1 - { 0xba, 0x12 }, // PGAMPK2 - { 0xbb, 0x10 }, // PGAMPK3 - { 0xbc, 0x12 }, // PGAMPK4 - { 0xbd, 0x15 }, // PGAMPK5 - { 0xbe, 0x19 }, // PGAMPK6 - { 0xbf, 0x0e }, // PGAMPK7 - { 0xc0, 0x16 }, // PGAMPK8 - { 0xc1, 0x0a }, // PGAMPK9 - // Set gray scale voltage to adjust gamma - { 0xd0, 0x0c }, // NGAMVR0 - { 0xd1, 0x17 }, // NGAMVR0 - { 0xd2, 0x14 }, // NGAMVR1 - { 0xd3, 0x2e }, // NGAMVR2 - { 0xd4, 0x32 }, // NGAMVR3 - { 0xd5, 0x3c }, // NGAMVR4 - { 0xd6, 0x22 }, // NGAMPR0 - { 0xd7, 0x3d }, // NGAMPR1 - { 0xd8, 0x0d }, // NGAMPK0 - { 0xd9, 0x07 }, // NGAMPK1 - { 0xda, 0x13 }, // NGAMPK2 - { 0xdb, 0x13 }, // NGAMPK3 - { 0xdc, 0x11 }, // NGAMPK4 - { 0xdd, 0x15 }, // NGAMPK5 - { 0xde, 0x19 }, // NGAMPK6 - { 0xdf, 0x10 }, // NGAMPK7 - { 0xe0, 0x17 }, // NGAMPK8 - { 0xe1, 0x0a }, // NGAMPK9 - // EXTC Command set enable, select page 3 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, - // Set various timing settings - { 0x00, 0x2a }, // GIP_VST_1 - { 0x01, 0x2a }, // GIP_VST_2 - { 0x02, 0x2a }, // GIP_VST_3 - { 0x03, 0x2a }, // GIP_VST_4 - { 0x04, 0x61 }, // GIP_VST_5 - { 0x05, 0x80 }, // GIP_VST_6 - { 0x06, 0xc7 }, // GIP_VST_7 - { 0x07, 0x01 }, // GIP_VST_8 - { 0x08, 0x03 }, // GIP_VST_9 - { 0x09, 0x04 }, // GIP_VST_10 - { 0x70, 0x22 }, // GIP_ECLK1 - { 0x71, 0x80 }, // GIP_ECLK2 - { 0x30, 0x2a }, // GIP_CLK_1 - { 0x31, 0x2a }, // GIP_CLK_2 - { 0x32, 0x2a }, // GIP_CLK_3 - { 0x33, 0x2a }, // GIP_CLK_4 - { 0x34, 0x61 }, // GIP_CLK_5 - { 0x35, 0xc5 }, // GIP_CLK_6 - { 0x36, 0x80 }, // GIP_CLK_7 - { 0x37, 0x23 }, // GIP_CLK_8 - { 0x40, 0x03 }, // GIP_CLKA_1 - { 0x41, 0x04 }, // GIP_CLKA_2 - { 0x42, 0x05 }, // GIP_CLKA_3 - { 0x43, 0x06 }, // GIP_CLKA_4 - { 0x44, 0x11 }, // GIP_CLKA_5 - { 0x45, 0xe8 }, // GIP_CLKA_6 - { 0x46, 0xe9 }, // GIP_CLKA_7 - { 0x47, 0x11 }, // GIP_CLKA_8 - { 0x48, 0xea }, // GIP_CLKA_9 - { 0x49, 0xeb }, // GIP_CLKA_10 - { 0x50, 0x07 }, // GIP_CLKB_1 - { 0x51, 0x08 }, // GIP_CLKB_2 - { 0x52, 0x09 }, // GIP_CLKB_3 - { 0x53, 0x0a }, // GIP_CLKB_4 - { 0x54, 0x11 }, // GIP_CLKB_5 - { 0x55, 0xec }, // GIP_CLKB_6 - { 0x56, 0xed }, // GIP_CLKB_7 - { 0x57, 0x11 }, // GIP_CLKB_8 - { 0x58, 0xef }, // GIP_CLKB_9 - { 0x59, 0xf0 }, // GIP_CLKB_10 - // Map internal GOA signals to GOA output pad - { 0xb1, 0x01 }, // PANELD2U2 - { 0xb4, 0x15 }, // PANELD2U5 - { 0xb5, 0x16 }, // PANELD2U6 - { 0xb6, 0x09 }, // PANELD2U7 - { 0xb7, 0x0f }, // PANELD2U8 - { 0xb8, 0x0d }, // PANELD2U9 - { 0xb9, 0x0b }, // PANELD2U10 - { 0xba, 0x00 }, // PANELD2U11 - { 0xc7, 0x02 }, // PANELD2U24 - { 0xca, 0x17 }, // PANELD2U27 - { 0xcb, 0x18 }, // PANELD2U28 - { 0xcc, 0x0a }, // PANELD2U29 - { 0xcd, 0x10 }, // PANELD2U30 - { 0xce, 0x0e }, // PANELD2U31 - { 0xcf, 0x0c }, // PANELD2U32 - { 0xd0, 0x00 }, // PANELD2U33 - // Map internal GOA signals to GOA output pad - { 0x81, 0x00 }, // PANELU2D2 - { 0x84, 0x15 }, // PANELU2D5 - { 0x85, 0x16 }, // PANELU2D6 - { 0x86, 0x10 }, // PANELU2D7 - { 0x87, 0x0a }, // PANELU2D8 - { 0x88, 0x0c }, // PANELU2D9 - { 0x89, 0x0e }, // PANELU2D10 - { 0x8a, 0x02 }, // PANELU2D11 - { 0x97, 0x00 }, // PANELU2D24 - { 0x9a, 0x17 }, // PANELU2D27 - { 0x9b, 0x18 }, // PANELU2D28 - { 0x9c, 0x0f }, // PANELU2D29 - { 0x9d, 0x09 }, // PANELU2D30 - { 0x9e, 0x0b }, // PANELU2D31 - { 0x9f, 0x0d }, // PANELU2D32 - { 0xa0, 0x01 }, // PANELU2D33 - // EXTC Command set enable, select page 2 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, - // Unknown registers - { 0x01, 0x01 }, - { 0x02, 0xda }, - { 0x03, 0xba }, - { 0x04, 0xa8 }, - { 0x05, 0x9a }, - { 0x06, 0x70 }, - { 0x07, 0xff }, - { 0x08, 0x91 }, - { 0x09, 0x90 }, - { 0x0a, 0xff }, - { 0x0b, 0x8f }, - { 0x0c, 0x60 }, - { 0x0d, 0x58 }, - { 0x0e, 0x48 }, - { 0x0f, 0x38 }, - { 0x10, 0x2b }, - // EXTC Command set enable, select page 0 - { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, - // Display Access Control - { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 }; static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) @@ -655,6 +384,7 @@ static int nv3052c_prepare(struct drm_panel *panel) gpiod_set_value_cansleep(priv->reset_gpio, 0); usleep_range(5000, 20000); + /* Apply panel-specific initialization registers */ for (i = 0; i < panel_regs_len; i++) { err = mipi_dbi_command(dbi, panel_regs[i].cmd, panel_regs[i].val); @@ -665,6 +395,16 @@ static int nv3052c_prepare(struct drm_panel *panel) } } + /* Apply common initialization registers */ + for (i = 0; i < ARRAY_SIZE(common_init_regs); i++) { + err = mipi_dbi_command(dbi, common_init_regs[i].cmd, + common_init_regs[i].val); + if (err) { + dev_err(priv->dev, "Unable to set register: %d\n", err); + goto err_disable_regulator; + } + } + err = mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); if (err) { dev_err(priv->dev, "Unable to exit sleep mode: %d\n", err); -- cgit v1.2.3 From 986f28f3a71e44ebd984ee45c4f75c09109ae7ee Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 23 Oct 2025 22:24:25 +0200 Subject: dt-bindings: panel: Add Samsung S6E3FC2X01 DDIC with panel Basic description for S6E3FC2X01 DDIC with attached panel AMS641RW. Samsung AMS641RW is 6.41 inch, 1080x2340 pixels, 19.5:9 ratio panel This panel has three supplies, while panel-simple-dsi is limited to one. There is no user of this compatible, nor the compatible make sense. Remove it from simple DSI panel definitions. Signed-off-by: David Heidelberg Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong Link: https://patch.msgid.link/20251023-s6e3fc2x01-v5-1-8f8852e67417@ixit.cz --- .../bindings/display/panel/panel-simple-dsi.yaml | 3 - .../bindings/display/panel/samsung,s6e3fc2x01.yaml | 81 ++++++++++++++++++++++ MAINTAINERS | 5 ++ 3 files changed, 86 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index 9b92a05791cc..ac2db8cf5eb7 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -56,8 +56,6 @@ properties: - panasonic,vvx10f034n00 # Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel - samsung,s6e3fa7-ams559nk06 - # Samsung s6e3fc2x01 1080x2340 AMOLED panel - - samsung,s6e3fc2x01 # Samsung sofef00 1080x2280 AMOLED panel - samsung,sofef00 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel @@ -80,7 +78,6 @@ allOf: properties: compatible: enum: - - samsung,s6e3fc2x01 - samsung,sofef00 then: properties: diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml new file mode 100644 index 000000000000..d48354fb52ea --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6e3fc2x01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S6E3FC2X01 AMOLED DDIC + +description: The S6E3FC2X01 is display driver IC with connected panel. + +maintainers: + - David Heidelberg + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + # Samsung 6.41 inch, 1080x2340 pixels, 19.5:9 ratio + - samsung,s6e3fc2x01-ams641rw + - const: samsung,s6e3fc2x01 + + reg: + maxItems: 1 + + reset-gpios: true + + port: true + + vddio-supply: + description: VDD regulator + + vci-supply: + description: VCI regulator + + poc-supply: + description: POC regulator + +required: + - compatible + - reset-gpios + - vddio-supply + - vci-supply + - poc-supply + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01"; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + vci-supply = <&s2dos05_buck1>; + poc-supply = <&s2dos05_ldo1>; + + te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 1083598bb2b6..eb9292a6ff7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8068,6 +8068,11 @@ S: Maintained F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c +DRM DRIVER FOR SAMSUNG S6E3FC2X01 DDIC +M: David Heidelberg +S: Maintained +F: Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml + DRM DRIVER FOR SAMSUNG S6E3HA8 PANELS M: Dzmitry Sankouski S: Maintained -- cgit v1.2.3 From 88148c30ef26593e239ee65284126541b11e0726 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 23 Oct 2025 22:24:26 +0200 Subject: drm/panel: Add Samsung S6E3FC2X01 DDIC with AMS641RW panel Add panel driver used in the OnePlus 6T. No datasheet, based mostly on EDK2 init sequence and the downstream driver. Note: This driver doesn't use previously mentioned "samsung,s6e3fc2x01" by OnePlus 6T device-tree. The reason is because DDIC itself without knowing the panel type used with it will not give the driver enough information about the panel used, as the panel cannot be autodetected. While would be more practical to support the original compatible, I would like to avoid it, to prevent confusing devs upstreaming DDICs. Based on work of: Casey Connolly Joel Selvaraj Nia Espera Signed-off-by: David Heidelberg Reviewed-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://patch.msgid.link/20251023-s6e3fc2x01-v5-2-8f8852e67417@ixit.cz --- MAINTAINERS | 1 + drivers/gpu/drm/panel/Kconfig | 13 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c | 385 +++++++++++++++++++++++ 4 files changed, 400 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c diff --git a/MAINTAINERS b/MAINTAINERS index eb9292a6ff7a..5d59ff76cfc6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8072,6 +8072,7 @@ DRM DRIVER FOR SAMSUNG S6E3FC2X01 DDIC M: David Heidelberg S: Maintained F: Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml +F: drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c DRM DRIVER FOR SAMSUNG S6E3HA8 PANELS M: Dzmitry Sankouski diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 045ffb2ccd0f..fadb7f397837 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -801,6 +801,19 @@ config DRM_PANEL_SAMSUNG_S6D7AA0 select DRM_MIPI_DSI select VIDEOMODE_HELPERS +config DRM_PANEL_SAMSUNG_S6E3FC2X01 + tristate "Samsung S6E3FC2X01 DSI panel controller" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the + Samsung S6E3FC2 DDIC and connected MIPI DSI panel. + Currently supported panels: + + Samsung AMS641RW (found in the OnePlus 6T smartphone) + config DRM_PANEL_SAMSUNG_S6E3HA2 tristate "Samsung S6E3HA2 DSI video mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 0356775a443a..ae56f64982cf 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) += panel-samsung-s6d7aa0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7) += panel-samsung-s6e3fa7.o +obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3FC2X01) += panel-samsung-s6e3fc2x01.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8) += panel-samsung-s6e3ha8.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c b/drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c new file mode 100644 index 000000000000..e63080204af7 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c @@ -0,0 +1,385 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Nia Espera + * Copyright (c) 2025 David Heidelberg + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include