From 96a43d3325e370de6fd72b814d083b2777cb4595 Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Thu, 12 Feb 2026 11:16:51 +0000 Subject: dt-bindings: arm: Add Zena CSS compatibility Add compatibility to Arm Zena CSS Fixed Virtual Platform [1]. [1] https://www.arm.com/products/automotive/compute-subsystems/zena Reviewed-by: Rob Herring (Arm) Signed-off-by: Debbie Horsfall Message-Id: <20260212-zena-css-v2-1-d33ea23cb9c2@arm.com> Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index ba04576f0ad6..95d4baa85506 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -119,6 +119,16 @@ properties: items: - const: arm,foundation-aarch64 - const: arm,vexpress + - description: Arm Zena Compute Subsystem Platforms + Arm Zena Compute Subsystem (CSS) is a compute platform targeting + the automotive sector. Arm Zena CSS is a high-performance Arm + Cortex-A720AE Application Processor system augmented with an Arm + Cortex-R82AE based Safety Island and real-time domain. + items: + - enum: + - arm,zena-css-fvp + - const: arm,zena-css + - const: arm,vexpress arm,vexpress,position: description: When daughterboards are stacked on one site, their position -- cgit v1.2.3 From 164148d0a16351ad3027cf3a3bb96d197633aecb Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Thu, 12 Feb 2026 11:16:52 +0000 Subject: arm64: dts: zena: Add support for Zena CSS Introduce the Zena CSS Fixed Virtual Platform (FVP) dts. This is currently the only Zena CSS variant, however the common definitions are included in a common dtsi for extensibility. Signed-off-by: Debbie Horsfall Message-Id: <20260212-zena-css-v2-2-d33ea23cb9c2@arm.com> Reviewed-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/zena-css-fvp.dts | 55 +++ arch/arm64/boot/dts/arm/zena-css.dtsi | 777 +++++++++++++++++++++++++++++++ 3 files changed, 833 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/zena-css-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/zena-css.dtsi diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index f30ee045dc95..770fb145b4a9 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -8,3 +8,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += zena-css-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/zena-css-fvp.dts b/arch/arm64/boot/dts/arm/zena-css-fvp.dts new file mode 100644 index 000000000000..b75204a91882 --- /dev/null +++ b/arch/arm64/boot/dts/arm/zena-css-fvp.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arm Limited. All rights reserved. + */ + +/dts-v1/; + +#include "zena-css.dtsi" + +/ { + model = "Zena CSS Fixed Virtual Platform"; + compatible = "arm,zena-css-fvp", "arm,zena-css", "arm,vexpress"; + + chosen { + stdout-path = &soc_serial0; + }; +}; + +&soc { + virtio@30020000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30020000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30030000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30040000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30040000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30050000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30060000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30060000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30080000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = ; + }; +}; diff --git a/arch/arm64/boot/dts/arm/zena-css.dtsi b/arch/arm64/boot/dts/arm/zena-css.dtsi new file mode 100644 index 000000000000..9899d2883337 --- /dev/null +++ b/arch/arm64/boot/dts/arm/zena-css.dtsi @@ -0,0 +1,777 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arm Limited. All rights reserved. + */ + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + soc_clk24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "refclk24mhz"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * The latency and residency numbers below are for illustrative + * purposes only and may vary on actual silicon. These values are + * considered just to demonstrate that the cpuidle governor logic + * works. + */ + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <800>; + exit-latency-us = <3200>; + local-timer-stop; + min-residency-us = <4200>; + }; + + cluster_sleep: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <3200>; + local-timer-stop; + min-residency-us = <4500>; + }; + }; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu4: cpu@10000 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu5: cpu@10100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu6: cpu@10200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu7: cpu@10300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu8: cpu@20000 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu9: cpu@20100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu10: cpu@20200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu11: cpu@20300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu12: cpu@30000 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cpu13: cpu@30100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cpu14: cpu@30200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cpu15: cpu@30300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cl0_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + + cl1_l3: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + + cl2_l3: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + + cl3_l3: l3-cache3 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + #address-cells = <1>; + #size-cells = <0>; + + mbox-names = "tx", "tx_reply", "rx"; + mboxes = <&mbox_db_tx 0 0 0>, + <&mbox_db_rx 0 0 0>, + <&mbox_db_rx 0 0 2>; + shmem = <&scmi_shmem_tx &scmi_shmem_rx>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + interrupts = ; + }; + + dsu-pmu-1 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + interrupts = ; + }; + + dsu-pmu-2 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu8 &cpu9 &cpu10 &cpu11>; + interrupts = ; + }; + + dsu-pmu-3 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu12 &cpu13 &cpu14 &cpu15>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + timer@1a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x1a810000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Map child space [0x0..0x30000) to parent @ 0x1a810000 + */ + ranges = <0x0 0x0 0x1a810000 0x00030000>; + + frame@20000 { + reg = <0x20000 0x10000>; + frame-number = <0>; + interrupts = ; + }; + }; + + gic: interrupt-controller@20800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + #redistributor-regions = <16>; + interrupt-controller; + interrupts = ; + ranges; + + /* + * With GIC-A720AE multiview enabled, GICR_TYPER.Last is + * always reported as 1 on redistributor views other than + * view 0. This breaks discovery of a single contiguous + * GICR frame region, so each core is described with its own + * redistributor region. + */ + reg = <0x0 0x20800000 0x0 0x10000>, /* GICD */ + <0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */ + <0x0 0x208c0000 0x0 0x40000>, + <0x0 0x20900000 0x0 0x40000>, + <0x0 0x20940000 0x0 0x40000>, + <0x0 0x20980000 0x0 0x40000>, + <0x0 0x209c0000 0x0 0x40000>, + <0x0 0x20a00000 0x0 0x40000>, + <0x0 0x20a40000 0x0 0x40000>, + <0x0 0x20a80000 0x0 0x40000>, + <0x0 0x20ac0000 0x0 0x40000>, + <0x0 0x20b00000 0x0 0x40000>, + <0x0 0x20b40000 0x0 0x40000>, + <0x0 0x20b80000 0x0 0x40000>, + <0x0 0x20bc0000 0x0 0x40000>, + <0x0 0x20c00000 0x0 0x40000>, + <0x0 0x20c40000 0x0 0x40000>; + + its: msi-controller@20840000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x20840000 0x0 0x40000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + /* + * UART is fixed at 24MHz, both UARTCLK and PCLK. + */ + soc_serial0: serial@1a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x1a400000 0x0 0x10000>; + interrupts = ; + clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + watchdog@1a420000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x1a420000 0x0 0x10000>, + <0x0 0x1a430000 0x0 0x10000>; + interrupts = ; + }; + + rtc@300d0000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x300d0000 0x0 0x10000>; + interrupts = ; + clocks = <&soc_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mbox_db_tx: mailbox@40020000 { + compatible = "arm,mhuv3"; + reg = <0x0 0x40020000 0x0 0x30000>; + interrupts = ; + interrupt-names = "combined"; + clocks = <&soc_clk24mhz>; + #mbox-cells = <3>; + }; + + mbox_db_rx: mailbox@40060000 { + compatible = "arm,mhuv3"; + reg = <0x0 0x40060000 0x0 0x30000>; + interrupts = ; + interrupt-names = "combined"; + clocks = <&soc_clk24mhz>; + #mbox-cells = <3>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; + + sram: sram@104000 { + compatible = "mmio-sram"; + reg = <0x0 0x00104000 0x0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x00104000 0x00001000>; + + scmi_shmem_tx: scpshmem-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + + scmi_shmem_rx: scpshmem-sram-section@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x100>; + }; + }; + + memory@80000000 { + device_type = "memory"; + + /* ~2GB mapped at 2GB, another 2GB at 2TB */ + reg = <0x00000000 0x80000000 0x00000000 0x7f000000>, + <0x00000200 0x00000000 0x00000000 0x80000000>; + }; +}; -- cgit v1.2.3 From 021915c7885fb1c83810930d527fa513877138d6 Mon Sep 17 00:00:00 2001 From: Debbie Horsfall Date: Wed, 11 Mar 2026 17:39:48 +0000 Subject: arm64: dts: zena: Move SRAM into SoC and memory node out of SoC Move the SRAM node into the SoC node. Move the memory node out of the include to make it customizable for each platform variant. Signed-off-by: Debbie Horsfall Message-Id: <20260311173948.3478931-1-debbie.horsfall@arm.com> Reviewed-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/zena-css-fvp.dts | 8 ++++++ arch/arm64/boot/dts/arm/zena-css.dtsi | 44 +++++++++++++------------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/arm/zena-css-fvp.dts b/arch/arm64/boot/dts/arm/zena-css-fvp.dts index b75204a91882..53c5412d92b2 100644 --- a/arch/arm64/boot/dts/arm/zena-css-fvp.dts +++ b/arch/arm64/boot/dts/arm/zena-css-fvp.dts @@ -14,6 +14,14 @@ chosen { stdout-path = &soc_serial0; }; + + memory@80000000 { + device_type = "memory"; + + /* ~2GB mapped at 2GB, another 2GB at 2TB */ + reg = <0x00000000 0x80000000 0x00000000 0x7f000000>, + <0x00000200 0x00000000 0x00000000 0x80000000>; + }; }; &soc { diff --git a/arch/arm64/boot/dts/arm/zena-css.dtsi b/arch/arm64/boot/dts/arm/zena-css.dtsi index 9899d2883337..0b41ee4bf4c6 100644 --- a/arch/arm64/boot/dts/arm/zena-css.dtsi +++ b/arch/arm64/boot/dts/arm/zena-css.dtsi @@ -634,6 +634,24 @@ #size-cells = <2>; ranges; + sram: sram@104000 { + compatible = "mmio-sram"; + reg = <0x0 0x00104000 0x0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x00104000 0x00001000>; + + scmi_shmem_tx: scpshmem-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + + scmi_shmem_rx: scpshmem-sram-section@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x100>; + }; + }; + timer@1a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x1a810000 0x0 0x10000>; @@ -748,30 +766,4 @@ , ; }; - - sram: sram@104000 { - compatible = "mmio-sram"; - reg = <0x0 0x00104000 0x0 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x00104000 0x00001000>; - - scmi_shmem_tx: scpshmem-sram-section@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - - scmi_shmem_rx: scpshmem-sram-section@100 { - compatible = "arm,scmi-shmem"; - reg = <0x100 0x100>; - }; - }; - - memory@80000000 { - device_type = "memory"; - - /* ~2GB mapped at 2GB, another 2GB at 2TB */ - reg = <0x00000000 0x80000000 0x00000000 0x7f000000>, - <0x00000200 0x00000000 0x00000000 0x80000000>; - }; }; -- cgit v1.2.3 From f9d162866f2f2b76c91d72564d1f93757222c566 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:14 -0500 Subject: dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp" The Arm Corstone1000-A320 is a variation of the Corstone1000 with Cortex-A320 cores and an Ethos-U85 NPU. An FVP for the platform is available here[1]. [1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/IoT%20FVPs Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski Message-Id: <20260320-dt-corstone1000-a320-v1-1-a549dfcfe8da@kernel.org> Signed-off-by: Sudeep Holla --- .../devicetree/bindings/arm/arm,corstone1000.yaml | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml index cff1cdaadb13..48ab3356e383 100644 --- a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -15,11 +15,11 @@ description: |+ provides a flexible compute architecture that combines Cortex‑A and Cortex‑M processors. - Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion - systems for M-Class (or other) processors for adding sensors, connectivity, - video, audio and machine learning at the edge System and security IPs to build - a secure SoC for a range of rich IoT applications, for example gateways, smart - cameras and embedded systems. + Support for Cortex‑A32, Cortex‑A35, Cortex‑A53 and Cortex-A320 processors. + Two expansion systems for M-Class (or other) processors for adding sensors, + connectivity, video, audio and machine learning at the edge System and + security IPs to build a secure SoC for a range of rich IoT applications, for + example gateways, smart cameras and embedded systems. Integrated Secure Enclave providing hardware Root of Trust and supporting seamless integration of the optional CryptoCell™-312 cryptographic @@ -39,6 +39,11 @@ properties: implementation of this system. See ARM ecosystems FVP's. items: - const: arm,corstone1000-fvp + - description: Corstone1000-A320 FVP is the Fixed Virtual Platform + implementation of this system with Cortex-A320 cores and Ethos-U85 + NPU. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-a320-fvp additionalProperties: true -- cgit v1.2.3 From 55de145c8ec2d5d8f0813de2f2c5015585089b30 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:15 -0500 Subject: dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85" The Corstone-1000-A320 platform contains an Ethos-U85 NPU. Add a specific compatible for it. Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski Message-Id: <20260320-dt-corstone1000-a320-v1-2-a549dfcfe8da@kernel.org> Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/npu/arm,ethos.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/npu/arm,ethos.yaml b/Documentation/devicetree/bindings/npu/arm,ethos.yaml index 716c4997f976..d5a1fae4db9d 100644 --- a/Documentation/devicetree/bindings/npu/arm,ethos.yaml +++ b/Documentation/devicetree/bindings/npu/arm,ethos.yaml @@ -30,7 +30,7 @@ properties: - fsl,imx93-npu - const: arm,ethos-u65 - items: - - {} + - const: arm,corstone1000-ethos-u85 - const: arm,ethos-u85 reg: -- cgit v1.2.3 From 903528ac234ab354b68c5e3008986ee7123b1039 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:16 -0500 Subject: arm64: dts: arm/corstone1000: Move cpu nodes In preparation to add a new Corstone-1000 variation with different CPUs, move the CPU nodes into the specific platforms and out of the common corstone1000.dtsi. Signed-off-by: Rob Herring (Arm) Message-Id: <20260320-dt-corstone1000-a320-v1-3-a549dfcfe8da@kernel.org> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 54 ++++++++++++++++----------- arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 13 +++++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 13 ------- 3 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index 66ba6b027193..e479c79c1ea7 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -48,30 +48,40 @@ clocks = <&smbclk>, <&refclk100mhz>; clock-names = "smclk", "apb_pclk"; }; -}; + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; -&cpus { - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; }; }; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts index 10d265be0c02..adcfaf7c55b8 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -13,6 +13,19 @@ model = "ARM Corstone1000 FPGA MPS3 board"; compatible = "arm,corstone1000-mps3"; + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + }; + smsc: ethernet@4010000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x40100000 0x10000>; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index f35a5c96f3da..4d57dc197918 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -21,19 +21,6 @@ stdout-path = "serial0:115200n8"; }; - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - }; - memory@88200000 { device_type = "memory"; reg = <0x88200000 0x77e00000>; -- cgit v1.2.3 From 9c3904f94fdbee59cd359d6a267595261d6039c4 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:17 -0500 Subject: arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi The FVPs have a common set of peripherals specific to the FVP. Move these to a separate .dtsi so they can be shared across FVP platforms. Signed-off-by: Rob Herring (Arm) Message-Id: <20260320-dt-corstone1000-a320-v1-4-a549dfcfe8da@kernel.org> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 36 +--------------------- arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi | 44 +++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 35 deletions(-) create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index e479c79c1ea7..fac0999b1901 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -8,46 +8,12 @@ /dts-v1/; #include "corstone1000.dtsi" +#include "corstone1000-fvp.dtsi" / { model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; compatible = "arm,corstone1000-fvp"; - smsc: ethernet@4010000 { - compatible = "smsc,lan91c111"; - reg = <0x40100000 0x10000>; - phy-mode = "mii"; - interrupts = ; - reg-io-width = <2>; - }; - - vmmc_v3_3d: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdmmc0: mmc@40300000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x40300000 0x1000>; - interrupts = ; - max-frequency = <12000000>; - vmmc-supply = <&vmmc_v3_3d>; - clocks = <&smbclk>, <&refclk100mhz>; - clock-names = "smclk", "apb_pclk"; - }; - - sdmmc1: mmc@50000000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x50000000 0x10000>; - interrupts = ; - max-frequency = <12000000>; - vmmc-supply = <&vmmc_v3_3d>; - clocks = <&smbclk>, <&refclk100mhz>; - clock-names = "smclk", "apb_pclk"; - }; cpus: cpus { #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi new file mode 100644 index 000000000000..dc6d77446e8f --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/ { + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; + + vmmc_v3_3d: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; -- cgit v1.2.3 From 87599f1843d3baa4083dc9dd01c95826b536de24 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 20 Mar 2026 11:47:18 -0500 Subject: arm64: dts: arm/corstone1000: Add corstone-1000-a320 The Corstone-1000-a320 is a Corstone-1000 derivative with Cortex-A320 cores, GIC-600, and Ethos-U85 NPU. Signed-off-by: Rob Herring (Arm) Message-Id: <20260320-dt-corstone1000-a320-v1-5-a549dfcfe8da@kernel.org> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts | 15 ++++ arch/arm64/boot/dts/arm/corstone1000-a320.dtsi | 91 +++++++++++++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000-a320.dtsi diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 770fb145b4a9..b35b03da2d84 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,5 +7,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-a320-fvp.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += zena-css-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts new file mode 100644 index 000000000000..0f72af78b5e1 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000-a320.dtsi" +#include "corstone1000-fvp.dtsi" + +/ { + model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-a320-fvp"; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi new file mode 100644 index 000000000000..f0937914350c --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +#include + +#include "corstone1000.dtsi" + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + sram: sram@2400000 { + compatible = "mmio-sram"; + reg = <0x02400000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x1c000000 0x10000>, + <0x1c040000 0x80000>; + interrupts = ; + }; + + + soc { + npu@1a050000 { + compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85"; + reg = <0x1a050000 0x1400>; + interrupts = ; + clocks = <&refclk100mhz>, <&refclk100mhz>; + clock-names = "core", "apb"; + sram = <&sram>; + }; + }; +}; -- cgit v1.2.3