From e8061ea925314c57248fafc1d0c30b8dc39e23b6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:34 -0600 Subject: arm64: dts: marvell: Add missing "#phy-cells" to "usb-nop-xceiv" The "usb-nop-xceiv" binding requires "#phy-cells" property with a value of 0 though it is not really used. Add it where missing from Marvell platforms. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 1 + arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 1 + arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 ++ arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 2 ++ arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 ++ arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 1 + arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 2 ++ 7 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index bd4e61d5448e..06d4a3a93f84 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -41,6 +41,7 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&exp_usb3_vbus>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 97a180c8dcd9..e82284888b9a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -37,6 +37,7 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <®_usb3_vbus>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 21ecb9c12505..c7102f74d4d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -51,6 +51,7 @@ cp0_usb3_0_phy: cp0-usb3-0-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_0_vbus>; }; @@ -65,6 +66,7 @@ cp1_usb3_0_phy: cp1-usb3-0-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp1_reg_usb3_0_vbus>; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 5e7d6de3cdde..5689a8bdfd03 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -47,10 +47,12 @@ cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus1>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 3cc320f569ad..7156739aa31a 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -50,6 +50,7 @@ cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus0>; }; @@ -64,6 +65,7 @@ cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus1>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index 626042fce7e2..26dc91c88677 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -31,6 +31,7 @@ cp1_usb3_0_phy0: usb-phy-3 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp1_reg_usb3_vbus0>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index f91fc69905b8..f82d45e62753 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -28,6 +28,7 @@ cp2_usb3_0_phy0: usb-phy-4 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp2_reg_usb3_vbus0>; }; @@ -42,6 +43,7 @@ cp2_usb3_0_phy1: usb-phy-5 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp2_reg_usb3_vbus1>; }; -- cgit v1.2.3 From 5336444472700244147b04601235ca8b7fd1ec16 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:41 -0600 Subject: arm64: dts: marvell: Fix stray and typo "pinctrl-names" properties There's several cases of "pinctrl-names" used without any "pinctrl-0" properties. Drop them. Fix the typo "pintrl-names" as well. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 1 - arch/arm64/boot/dts/marvell/cn9130-cf-base.dts | 2 +- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 1 - arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 -- arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 1 - 5 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index e82284888b9a..0ab33aa928e7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -42,7 +42,6 @@ }; gpio-leds { - pinctrl-names = "default"; compatible = "gpio-leds"; /* No assigned functions to the LEDs by default */ led1 { diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts index 788a5c302b17..212865f6cf6a 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts @@ -137,7 +137,7 @@ &cp0_pinctrl { pinctrl-0 = <&sim_select_pins>; - pintrl-names = "default"; + pinctrl-names = "default"; rear_button_pins: cp0-rear-button-pins { marvell,pins = "mpp31"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 5689a8bdfd03..c9050e707a60 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -93,7 +93,6 @@ /* on-board eMMC U6 */ &ap_sdhci0 { - pinctrl-names = "default"; bus-width = <8>; status = "okay"; mmc-ddr-1_8v; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 7156739aa31a..8e413286e019 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -111,7 +111,6 @@ /* on-board eMMC - U9 */ &ap_sdhci0 { - pinctrl-names = "default"; bus-width = <8>; vqmmc-supply = <&ap0_reg_sd_vccq>; status = "okay"; @@ -166,7 +165,6 @@ /* U36 */ expander0: pca953x@21 { compatible = "nxp,pca9555"; - pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index f82d45e62753..98eee9e4e10b 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -142,7 +142,6 @@ /* U12 */ cp2_module_expander1: pca9555@21 { compatible = "nxp,pca9555"; - pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; -- cgit v1.2.3 From e509bd563114c3730bf4be48436a4741c0ab4dc9 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:46 -0600 Subject: arm64: dts: marvell: cn9131-cf-solidwan: Add missing GPIO properties on "nxp,pca9536" The PCA9536 is always a GPIO provider, so add the missing properties. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts index 338853d3b179..b6aeba7d0a61 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts @@ -202,6 +202,8 @@ expander0: gpio@41 { compatible = "nxp,pca9536"; reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; usb-a-vbus0-ilimit-hog { gpio-hog; -- cgit v1.2.3 From dd1aadd29de3645c08a160c3b3cfc0d7a5c9bf35 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:52 -0600 Subject: arm64: dts: marvell: change regulator-gpio to regulator-fixed A "regulator-gpio" must have a GPIO control, hence the name. There's no GPIO on a couple of Marvell platforms at least as far as the DT is defined, so change the regulator type from GPIO to fixed. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts | 9 ++------- arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi | 3 ++- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 9f4bafeddd82..a881a3326dba 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -26,16 +26,11 @@ }; vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; + compatible = "regulator-fixed"; regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; }; keys { diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi index 6f3914bcfd01..71c225221617 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi @@ -15,8 +15,9 @@ }; &ap0_reg_sd_vccq { + compatible = "regulator-fixed"; regulator-max-microvolt = <1800000>; - states = <1800000 0x1 1800000 0x0>; + /delete-property/ states; /delete-property/ gpios; }; -- cgit v1.2.3 From f6c8955f08749e2ded547a48ce6002df2c100859 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 12 Jan 2026 15:55:57 +0100 Subject: arm64: dts: marvell: Add SoC specific compatibles to SafeXcel crypto Following the changes in the binding for the SafeXcel crypto engine, add SoC specific compatibles to the existing nodes in Armada 37xx and CP11x. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 3 ++- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index c612317043ea..87f9367aec12 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -427,7 +427,8 @@ }; crypto: crypto@90000 { - compatible = "inside-secure,safexcel-eip97ies"; + compatible = "marvell,armada-3700-crypto", + "inside-secure,safexcel-eip97ies"; reg = <0x90000 0x20000>; interrupts = , , diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index d9d409eac259..39599171d51b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -512,7 +512,8 @@ }; CP11X_LABEL(crypto): crypto@800000 { - compatible = "inside-secure,safexcel-eip197b"; + compatible = "marvell,armada-cp110-crypto", + "inside-secure,safexcel-eip197b"; reg = <0x800000 0x200000>; interrupts = <88 IRQ_TYPE_LEVEL_HIGH>, <89 IRQ_TYPE_LEVEL_HIGH>, -- cgit v1.2.3 From b3370479a5f7edf4baf0e307f1163f8fe9e09e17 Mon Sep 17 00:00:00 2001 From: Elad Nachman Date: Thu, 22 Jan 2026 18:59:22 +0200 Subject: arm64: dts: a7k: add COM Express boards Add support for Armada 7020 Express Type 7 CPU module board by Marvell. Define this COM Express CPU module as dtsi and provide a dtsi file for the carrier board (Marvell DB-98CX85x0 COM Express type 7 carrier board). Since memory is soldered on CPU module, memory node is on CPU module dtsi file. This Carrier board only utilizes the PCIe link, hence no special device or driver support is provided by this dtsi file. Devise a dts file for the combined com express carrier and CPU module. The Aramda 7020 CPU COM Express board offers the following features: 1. Armada 7020 CPU, with dual ARM A72 cores 2. DDR4 memory, 8GB, on board soldered 3. 1Gbit Out of Band Ethernet via RGMII to PHY and RJ45 connector, all are present on A7K CPU module (none on the carrier) 4. Optional 10G KR Ethernet going via the COM Express type 7 connector 5. On-board 8 Gbit, 8-bit bus width NAND flash 6. On-board 512 Mbit SPI flash 7. PCIe Root Complex, 4 lanes PCIe gen3 connectivity, going via the COM Express type 7 connector 8. m.2 SATA connector 9. Micro-SD card connector 10. USB 2.0 via COM Express type 7 connector 11. Two i2c interfaces - one to the CPU module, and one to the carrier board via the COM Express type 7 connector 12. UART (mini USB connector by virtue of FT2232D UART to USB converter, connected to the Armada 7020 UART0) gc: 10gbase-kr is legacy, use "10gbase-r" instead in cp0_eth0 node Signed-off-by: Elad Nachman Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-7020-comexpress.dtsi | 161 +++++++++++++++++++++ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 7 + arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 4 +- .../boot/dts/marvell/db-falcon-carrier-a7k.dts | 27 ++++ arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi | 22 +++ 6 files changed, 220 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi create mode 100644 arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts create mode 100644 arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index a774bc74a0a0..09d1544041af 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb +dtb-$(CONFIG_ARCH_MVEBU) += db-falcon-carrier-a7k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-mochabin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi new file mode 100644 index 000000000000..2b5ec4a451e3 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 7020 Com Express CPU module board. + */ + +#include "armada-7020.dtsi" + +/ { + model = "Marvell Armada-7020 COMEXPRESS board setup"; + compatible = "marvell,armada7020-cpu-module", "marvell,armada7020", + "marvell,armada-ap806-dual", "marvell,armada-ap806"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x00000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp0_eth1; + }; +}; + +&ap_clk { + status = "okay"; +}; + +&gic { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&cp0_mdio { + status = "okay"; + + phy0: ethernet-phy@10 { + reg = <0x10>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy4 0>; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +&cp0_clk { + status = "okay"; +}; + +&cp0_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x400000 0x100000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x500000 0x1e00000>; + }; + }; + }; +}; + +&cp0_pcie0 { + status = "okay"; + num-lanes = <4>; + num-viewport = <8>; + + ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000 + 0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>; + + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy0 0 + &cp0_comphy1 0 + &cp0_comphy2 0 + &cp0_comphy3 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status = "okay"; + + sata-port@1 { + status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy5 1>; + }; +}; + +&cp0_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + status = "okay"; + bus-width = <4>; + no-1-8-v; + broken-cd; +}; + diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index df939426d258..36e0a8a0ade3 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -47,6 +47,13 @@ cp0_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; + + sdhci_pins: sdhci-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61", "mpp62"; + marvell,function = "sdio"; + }; + nand_pins: nand-pins { marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 82f4dedfc25e..0868d59d561b 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -54,7 +54,7 @@ }; thermal-zones { - /delete-node/ ap-thermal-cpu2; - /delete-node/ ap-thermal-cpu3; + /delete-node/ ap-cpu2-thermal; + /delete-node/ ap-cpu3-thermal; }; }; diff --git a/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts b/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts new file mode 100644 index 000000000000..5d1ae7b35b62 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the Falcon DB Type 7 Com Express carrier board, + * Utilizing the Armada 7020 COM Express CPU module board. + * This specific carrier board (DB-98CX8540/80) + * only maintains a PCIe link with the CPU module, + * which does not require any special DTS definitions. + * + * There is no Linux CPU booting in this mode on the carrier, only on the + * Armada 7020 COM Express CPU module. + * What runs the Linux is the Armada 7020 on the COM Express CPU module, + * And it accesses the switch end-point on the Falcon DB portion of the carrier + * via PCIe. + */ + +#include "armada-7020-comexpress.dtsi" +#include "db-falcon-carrier.dtsi" + +/ { + model = "Marvell Falcon DB COM EXPRESS type 7 carrier board with Armada 7020 CPU module"; + compatible = "marvell,armada7020-falcon-carrier", "marvell,db-falcon-carrier", + "marvell,armada7020-cpu-module", "marvell,armada7020", + "marvell,armada-ap806-dual", "marvell,armada-ap806"; + +}; diff --git a/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi b/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi new file mode 100644 index 000000000000..c85ad1547ec5 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the Falcon DB Type 7 Com Express carrier board, + * This (DB-98CX8540/80) specific carrier board only maintains + * a PCIe link with the COM Express CPU module, which does not + * require any special DTS definitions. + * + * The board contains the 98CX8540/80 Switch, which connects by + * PCIe to the COM Express CPU module. + * This CPU module can be any standard COM Express CPU module with + * PCIe support. + * + * There is no Linux CPU booting in this mode on the carrier, + * only on the COM Express CPU module. + */ + +/ { + model = "Marvell Armada Falcon DB COM EXPRESS type 7 carrier board"; + compatible = "marvell,db-falcon-carrier"; +}; -- cgit v1.2.3 From fcaf733ca526b69595ed1d227e2cc59ddd24eff7 Mon Sep 17 00:00:00 2001 From: Elad Nachman Date: Thu, 22 Jan 2026 18:59:23 +0200 Subject: MAINTAINERS: Add Falcon DB Add Falcon DB to the list of maintained Marvell Armada dts files Signed-off-by: Elad Nachman Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..f502b13643e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2943,6 +2943,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ F: arch/arm/boot/dts/marvell/armada* +F: arch/arm/boot/dts/marvell/db-falcon* F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ -- cgit v1.2.3